From nobody Fri Oct 23 22:16:18 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF475549376; Thu, 15 Oct 2026 16:01:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792080126; cv=none; b=k+Mz6vtdYEqkwxbIQqPy/NtQ2IqKTgGSQsB/p9Jc08JYJqyLuGxu9IPHCgJt3KgABhcshFAyBE6txOADqVmJh2+JRCMHah2MTFYgmoczl3VJD7GUx/K43/OThp9FboIoSJrLSppRpy5V/aEC4EZ8Klaqo7kaYPkgoL+p+PKClZ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792080126; c=relaxed/simple; bh=lxbO9HoZ0tMZ4DrDeBnR1LYDmJ8EYjEayTOfy1FnLY8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=K5zNCTbmpwcjMX/xrKYjH2FMEfHOVfOBSPb3vegJ02TjstBcUjANX1Dl7r6euzWmApJ6sprRGcmWHFknsDzF3Zd0pjFeCPEo1tT9eGGRwWOEAPaDnwPAtoAEyIrJYMazet0is7v15d4yIT4uhVuA5mTqMLgt4nkRBx0klWVPd5I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=EB9b9/JE; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="EB9b9/JE" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 179174E4124F; Thu, 15 Oct 2026 16:01:45 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id DDFBD6075C; Thu, 15 Oct 2026 16:01:44 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id F214110328CEA; Thu, 15 Oct 2026 18:01:36 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1792080100; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=qfIhijod798pa8RCWSDyRgPjsCTwOoNyPUM8VWiIooU=; b=EB9b9/JE+60DSJrkgd4qA/rHsNMO1VFFybWMZXRELCB09t4IsVkiPihJ86l8DVVJsUUvAM mlYxEpDkOsHGLaDzOpPP5HXHKVD+pufq3EwhhpNB0kuj8tCfbFTKFxq9r3Tcbk3OI51om8 m9eCJdtlpU+XkC0n9zv6hkmRHpPyOQFmst2r7S1l7PDniE4N6gbZdHlEaiDfZqYoXKkZnw DqYytg+Xn7zRSQqNVhBgwpv2BiMUGgJFgHpv2Z+g3IcrpCLKYaqhahPArJdeNt9FitDEMf F89n19GXMIp332epCOxGSD/vzG51wUIBVT897YfRMx6L24Y31Slk/GoMKf5pVQ== From: Miquel Raynal Date: Thu, 15 Oct 2026 18:01:14 +0200 Subject: [PATCH v10 01/10] clk: nuvoton: ma35d1: Use clk_hw pointers as mux parents Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-perso-ma35d1-upstream-clk-v10-1-47c97b54a809@bootlin.com> References: <20261015-perso-ma35d1-upstream-clk-v10-0-47c97b54a809@bootlin.com> In-Reply-To: <20261015-perso-ma35d1-upstream-clk-v10-0-47c97b54a809@bootlin.com> To: Jacky Huang , Shan-Chun Hung , Michael Turquette , Stephen Boyd , Richard Cochran , Arnd Bergmann , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair Cc: Thomas Petazzoni , Steam Lin , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, Miquel Raynal , stable@vger.kernel.org X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The MA35D1 clock provider registers its muxes with parent data structures filling .fw_name. This is not the ideal approach since that would require a massive amount of internal clock names declaration in the DT. Since the DT does not play the game of exposing all these names, none of the parent lookups performed when instantiating the muxes succeed. As a result, these muxes get registered as root clocks, leading to a sadly flat clock tree and no frequency assigned to most of the peripheral clocks: enable prepare protect clock count count count rate usbphy1 0 0 0 480000000 usbphy0 0 0 0 480000000 husbh1_gate 0 0 0 480000000 husbh0_gate 0 0 0 480000000 usbh_gate 0 0 0 480000000 usbd_gate 0 0 0 480000000 syspll 0 0 0 180000000 lirc 0 0 0 32000 lirc_gate 0 0 0 32000 hirc 0 0 0 12000000 gtmr_gate 0 0 0 12000000 hirc_gate 0 0 0 12000000 lxt 0 0 0 32768 rtc_gate 0 0 0 32768 lxt_gate 0 0 0 32768 hxt 0 0 0 24000000 vpll 0 0 0 1224000000 dcup_div 0 0 0 612000000 epll 0 0 0 6000000000 epll_div8 0 0 0 750000000 epll_div4 0 0 0 1500000000 epll_div2 0 0 0 3000000000 emac1_gate 0 0 0 3000000000 emac0_gate 0 0 0 3000000000 apll 0 0 0 6048000000 ddrpll 0 0 0 266460000 ddr_gate 0 0 0 266460000 ddr6_gate 0 0 0 266460000 ddr0_gate 0 0 0 266460000 capll 0 0 0 2400000000 hxt_gate 0 0 0 24000000 clk_hxt 0 0 0 24000000 spi3_mux 0 0 0 0 spi3_gate 0 0 0 0 spi2_mux 0 0 0 0 spi2_gate 0 0 0 0 spi1_mux 0 0 0 0 spi1_gate 0 0 0 0 spi0_mux 0 0 0 0 spi0_gate 0 0 0 0 i2s1_mux 0 0 0 0 i2s1_gate 0 0 0 0 i2s0_mux 0 0 0 0 i2s0_gate 0 0 0 0 ... Apart from the wrong clock tree representation, it means that none of the device drivers (spi & i2c in the excerpt above) can actually query their clock rate, or they would get 0Hz. Instead of declaring the parents in the clk_parent_data structure, use the actual HW clocks to lookup the parents directly: parents are described by an array of indices into the controller's main clock table (like in other clock controller drivers), which the "new" mux helper now resolves. The WDT and WWDT muxes list the /4096 children of PCLK3 and PCLK4 among their possible parents. Those two clocks are now registered by the previous commit, so their entries in the parent tables are restored instead of being turned into invalid slots. enable prepare protect clock count count count rate usbphy1 0 0 0 480000000 usbphy0 0 0 0 480000000 husbh1_gate 0 0 0 480000000 husbh0_gate 0 0 0 480000000 usbh_gate 0 0 0 480000000 usbd_gate 0 0 0 480000000 syspll 1 1 0 180000000 dbg_mux 0 0 0 180000000 sdh1_mux 0 0 0 180000000 sdh1_gate 0 0 0 180000000 sdh0_mux 0 0 0 180000000 sdh0_gate 0 0 0 180000000 sysclk1_mux 2 2 0 180000000 pclk4 0 0 0 90000000 pclk3 0 0 0 90000000 sspcc_gate 0 0 0 90000000 ssmcc_gate 0 0 0 90000000 hclk3 0 0 0 90000000 pclk2 0 0 0 180000000 eadc_div 0 0 0 90000000 eadc_gate 0 0 0 90000000 qei1_gate 0 0 0 180000000 ecap1_gate 0 0 0 180000000 spi3_mux 0 0 0 180000000 spi3_gate 0 0 0 180000000 spi1_mux 0 0 0 180000000 spi1_gate 0 0 0 180000000 epwm1_gate 0 0 0 180000000 i2c5_gate 0 0 0 180000000 i2c2_gate 0 0 0 180000000 pclk1 0 0 0 180000000 qei2_gate 0 0 0 180000000 qei0_gate 0 0 0 180000000 ecap2_gate 0 0 0 180000000 ecap0_gate 0 0 0 180000000 spi2_mux 0 0 0 180000000 spi2_gate 0 0 0 180000000 spi0_mux 0 0 0 180000000 spi0_gate 0 0 0 180000000 epwm2_gate 0 0 0 180000000 epwm0_gate 0 0 0 180000000 i2c4_gate 0 0 0 180000000 i2c1_gate 0 0 0 180000000 pclk0 1 1 0 180000000 adc_div 0 0 0 90000000 adc_gate 0 0 0 90000000 qspi1_mux 0 0 0 180000000 qspi1_gate 0 0 0 180000000 qspi0_mux 1 1 0 180000000 qspi0_gate 1 1 0 180000000 i2c3_gate 0 0 0 180000000 i2c0_gate 0 0 0 180000000 Note: while switching the API, let's use the devm_ alternative to manage the clock registration automatically. Fixes: f50a000b4219 ("clk: nuvoton: Use clk_parent_data instead of string f= or parent clock") Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal --- drivers/clk/nuvoton/clk-ma35d1.c | 626 +++++++++++------------------------= ---- 1 file changed, 177 insertions(+), 449 deletions(-) diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma3= 5d1.c index c914079cee2d..ba3550c083ac 100644 --- a/drivers/clk/nuvoton/clk-ma35d1.c +++ b/drivers/clk/nuvoton/clk-ma35d1.c @@ -63,300 +63,49 @@ static DEFINE_SPINLOCK(ma35d1_lock); #define PLL_MODE_FRAC 1 #define PLL_MODE_SS 2 =20 -static const struct clk_parent_data ca35clk_sel_clks[] =3D { - { .fw_name =3D "hxt", }, - { .fw_name =3D "capll", }, - { .fw_name =3D "ddrpll", }, -}; +#define MA35D1_MUX_MAX_PARENTS 10 =20 -static const struct clk_parent_data sysclk0_sel_clks[] =3D { - { .fw_name =3D "epll_div2", }, - { .fw_name =3D "syspll", }, -}; - -static const struct clk_parent_data sysclk1_sel_clks[] =3D { - { .fw_name =3D "hxt", }, - { .fw_name =3D "syspll", }, -}; - -static const struct clk_parent_data axiclk_sel_clks[] =3D { - { .fw_name =3D "capll_div2", }, - { .fw_name =3D "capll_div4", }, -}; - -static const struct clk_parent_data ccap_sel_clks[] =3D { - { .fw_name =3D "hxt", }, - { .fw_name =3D "vpll", }, - { .fw_name =3D "apll", }, - { .fw_name =3D "syspll", }, -}; - -static const struct clk_parent_data sdh_sel_clks[] =3D { - { .fw_name =3D "syspll", }, - { .fw_name =3D "apll", }, -}; - -static const struct clk_parent_data dcu_sel_clks[] =3D { - { .fw_name =3D "epll_div2", }, - { .fw_name =3D "syspll", }, -}; - -static const struct clk_parent_data gfx_sel_clks[] =3D { - { .fw_name =3D "epll", }, - { .fw_name =3D "syspll", }, -}; - -static const struct clk_parent_data dbg_sel_clks[] =3D { - { .fw_name =3D "hirc", }, - { .fw_name =3D "syspll", }, -}; - -static const struct clk_parent_data timer0_sel_clks[] =3D { - { .fw_name =3D "hxt", }, - { .fw_name =3D "lxt", }, - { .fw_name =3D "pclk0", }, - { .index =3D -1, }, - { .index =3D -1, }, - { .fw_name =3D "lirc", }, - { .index =3D -1, }, - { .fw_name =3D "hirc", }, -}; - -static const struct clk_parent_data timer1_sel_clks[] =3D { - { .fw_name =3D "hxt", }, - { .fw_name =3D "lxt", }, - { .fw_name =3D "pclk0", }, - { .index =3D -1, }, - { .index =3D -1, }, - { .fw_name =3D "lirc", }, - { .index =3D -1, }, - { .fw_name =3D "hirc", }, -}; - -static const struct clk_parent_data timer2_sel_clks[] =3D { - { .fw_name =3D "hxt", }, - { .fw_name =3D "lxt", }, - { .fw_name =3D "pclk1", }, - { .index =3D -1, }, - { .index =3D -1, }, - { .fw_name =3D "lirc", }, - { .index =3D -1, }, - { .fw_name =3D "hirc", }, -}; - -static const struct clk_parent_data timer3_sel_clks[] =3D { - { .fw_name =3D "hxt", }, - { .fw_name =3D "lxt", }, - { .fw_name =3D "pclk1", }, - { .index =3D -1, }, - { .index =3D -1, }, - { .fw_name =3D "lirc", }, - { .index =3D -1, }, - { .fw_name =3D "hirc", }, -}; - -static const struct clk_parent_data timer4_sel_clks[] =3D { - { .fw_name =3D "hxt", }, - { .fw_name =3D "lxt", }, - { .fw_name =3D "pclk2", }, - { .index =3D -1, }, - { .index =3D -1, }, - { .fw_name =3D "lirc", }, - { .index =3D -1, }, - { .fw_name =3D "hirc", }, -}; - -static const struct clk_parent_data timer5_sel_clks[] =3D { - { .fw_name =3D "hxt", }, - { .fw_name =3D "lxt", }, - { .fw_name =3D "pclk2", }, - { .index =3D -1, }, - { .index =3D -1, }, - { .fw_name =3D "lirc", }, - { .index =3D -1, }, - { .fw_name =3D "hirc", }, -}; - -static const struct clk_parent_data timer6_sel_clks[] =3D { - { .fw_name =3D "hxt", }, - { .fw_name =3D "lxt", }, - { .fw_name =3D "pclk0", }, - { .index =3D -1, }, - { .index =3D -1, }, - { .fw_name =3D "lirc", }, - { .index =3D -1, }, - { .fw_name =3D "hirc", }, -}; - -static const struct clk_parent_data timer7_sel_clks[] =3D { - { .fw_name =3D "hxt", }, - { .fw_name =3D "lxt", }, - { .fw_name =3D "pclk0", }, - { .index =3D -1, }, - { .index =3D -1, }, - { .fw_name =3D "lirc", }, - { .index =3D -1, }, - { .fw_name =3D "hirc", }, -}; - -static const struct clk_parent_data timer8_sel_clks[] =3D { - { .fw_name =3D "hxt", }, - { .fw_name =3D "lxt", }, - { .fw_name =3D "pclk1", }, - { .index =3D -1, }, - { .index =3D -1, }, - { .fw_name =3D "lirc", }, - { .index =3D -1, }, - { .fw_name =3D "hirc", }, -}; - -static const struct clk_parent_data timer9_sel_clks[] =3D { - { .fw_name =3D "hxt", }, - { .fw_name =3D "lxt", }, - { .fw_name =3D "pclk1", }, - { .index =3D -1, }, - { .index =3D -1, }, - { .fw_name =3D "lirc", }, - { .index =3D -1, }, - { .fw_name =3D "hirc", }, -}; - -static const struct clk_parent_data timer10_sel_clks[] =3D { - { .fw_name =3D "hxt", }, - { .fw_name =3D "lxt", }, - { .fw_name =3D "pclk2", }, - { .index =3D -1, }, - { .index =3D -1, }, - { .fw_name =3D "lirc", }, - { .index =3D -1, }, - { .fw_name =3D "hirc", }, -}; - -static const struct clk_parent_data timer11_sel_clks[] =3D { - { .fw_name =3D "hxt", }, - { .fw_name =3D "lxt", }, - { .fw_name =3D "pclk2", }, - { .index =3D -1, }, - { .index =3D -1, }, - { .fw_name =3D "lirc", }, - { .index =3D -1, }, - { .fw_name =3D "hirc", }, -}; - -static const struct clk_parent_data uart_sel_clks[] =3D { - { .fw_name =3D "hxt", }, - { .fw_name =3D "sysclk1_div2", }, -}; - -static const struct clk_parent_data wdt0_sel_clks[] =3D { - { .index =3D -1, }, - { .fw_name =3D "lxt", }, - { .fw_name =3D "pclk3_div4096", }, - { .fw_name =3D "lirc", }, -}; - -static const struct clk_parent_data wdt1_sel_clks[] =3D { - { .index =3D -1, }, - { .fw_name =3D "lxt", }, - { .fw_name =3D "pclk3_div4096", }, - { .fw_name =3D "lirc", }, -}; - -static const struct clk_parent_data wdt2_sel_clks[] =3D { - { .index =3D -1, }, - { .fw_name =3D "lxt", }, - { .fw_name =3D "pclk4_div4096", }, - { .fw_name =3D "lirc", }, -}; - -static const struct clk_parent_data wwdt0_sel_clks[] =3D { - { .index =3D -1, }, - { .index =3D -1, }, - { .fw_name =3D "pclk3_div4096", }, - { .fw_name =3D "lirc", }, -}; - -static const struct clk_parent_data wwdt1_sel_clks[] =3D { - { .index =3D -1, }, - { .index =3D -1, }, - { .fw_name =3D "pclk3_div4096", }, - { .fw_name =3D "lirc", }, -}; - -static const struct clk_parent_data wwdt2_sel_clks[] =3D { - { .index =3D -1, }, - { .index =3D -1, }, - { .fw_name =3D "pclk4_div4096", }, - { .fw_name =3D "lirc", }, -}; - -static const struct clk_parent_data spi0_sel_clks[] =3D { - { .fw_name =3D "pclk1", }, - { .fw_name =3D "apll", }, -}; - -static const struct clk_parent_data spi1_sel_clks[] =3D { - { .fw_name =3D "pclk2", }, - { .fw_name =3D "apll", }, -}; - -static const struct clk_parent_data spi2_sel_clks[] =3D { - { .fw_name =3D "pclk1", }, - { .fw_name =3D "apll", }, -}; - -static const struct clk_parent_data spi3_sel_clks[] =3D { - { .fw_name =3D "pclk2", }, - { .fw_name =3D "apll", }, -}; - -static const struct clk_parent_data qspi0_sel_clks[] =3D { - { .fw_name =3D "pclk0", }, - { .fw_name =3D "apll", }, -}; - -static const struct clk_parent_data qspi1_sel_clks[] =3D { - { .fw_name =3D "pclk0", }, - { .fw_name =3D "apll", }, -}; - -static const struct clk_parent_data i2s0_sel_clks[] =3D { - { .fw_name =3D "apll", }, - { .fw_name =3D "sysclk1_div2", }, -}; - -static const struct clk_parent_data i2s1_sel_clks[] =3D { - { .fw_name =3D "apll", }, - { .fw_name =3D "sysclk1_div2", }, -}; - -static const struct clk_parent_data can_sel_clks[] =3D { - { .fw_name =3D "apll", }, - { .fw_name =3D "vpll", }, -}; - -static const struct clk_parent_data cko_sel_clks[] =3D { - { .fw_name =3D "hxt", }, - { .fw_name =3D "lxt", }, - { .fw_name =3D "hirc", }, - { .fw_name =3D "lirc", }, - { .fw_name =3D "capll_div4", }, - { .fw_name =3D "syspll", }, - { .fw_name =3D "ddrpll", }, - { .fw_name =3D "epll_div2", }, - { .fw_name =3D "apll", }, - { .fw_name =3D "vpll", }, -}; - -static const struct clk_parent_data smc_sel_clks[] =3D { - { .fw_name =3D "hxt", }, - { .fw_name =3D "pclk4", }, -}; - -static const struct clk_parent_data kpi_sel_clks[] =3D { - { .fw_name =3D "hxt", }, - { .fw_name =3D "lxt", }, -}; +/* Mux parent selection, by index into the controller's clock table */ +static const int ca35clk_parent_idx[] =3D { HXT, CAPLL, DDRPLL }; +static const int sysclk0_parent_idx[] =3D { EPLL_DIV2, SYSPLL }; +static const int sysclk1_parent_idx[] =3D { HXT, SYSPLL }; +static const int axiclk_parent_idx[] =3D { AXICLK_DIV2, AXICLK_DIV4 }; +static const int ccap_parent_idx[] =3D { HXT, VPLL, APLL, SYSPLL }; +static const int sdh_parent_idx[] =3D { SYSPLL, APLL }; +static const int dcu_parent_idx[] =3D { EPLL_DIV2, SYSPLL }; +static const int gfx_parent_idx[] =3D { EPLL, SYSPLL }; +static const int dbg_parent_idx[] =3D { HIRC, SYSPLL }; +static const int timer0_parent_idx[] =3D { HXT, LXT, PCLK0, -1, -1, LIRC, = -1, HIRC }; +static const int timer1_parent_idx[] =3D { HXT, LXT, PCLK0, -1, -1, LIRC, = -1, HIRC }; +static const int timer2_parent_idx[] =3D { HXT, LXT, PCLK1, -1, -1, LIRC, = -1, HIRC }; +static const int timer3_parent_idx[] =3D { HXT, LXT, PCLK1, -1, -1, LIRC, = -1, HIRC }; +static const int timer4_parent_idx[] =3D { HXT, LXT, PCLK2, -1, -1, LIRC, = -1, HIRC }; +static const int timer5_parent_idx[] =3D { HXT, LXT, PCLK2, -1, -1, LIRC, = -1, HIRC }; +static const int timer6_parent_idx[] =3D { HXT, LXT, PCLK0, -1, -1, LIRC, = -1, HIRC }; +static const int timer7_parent_idx[] =3D { HXT, LXT, PCLK0, -1, -1, LIRC, = -1, HIRC }; +static const int timer8_parent_idx[] =3D { HXT, LXT, PCLK1, -1, -1, LIRC, = -1, HIRC }; +static const int timer9_parent_idx[] =3D { HXT, LXT, PCLK1, -1, -1, LIRC, = -1, HIRC }; +static const int timer10_parent_idx[] =3D { HXT, LXT, PCLK2, -1, -1, LIRC,= -1, HIRC }; +static const int timer11_parent_idx[] =3D { HXT, LXT, PCLK2, -1, -1, LIRC,= -1, HIRC }; +static const int uart_parent_idx[] =3D { HXT, SYSCLK1_DIV2 }; +static const int wdt0_parent_idx[] =3D { -1, LXT, PCLK3_DIV4096, LIRC }; +static const int wdt1_parent_idx[] =3D { -1, LXT, PCLK3_DIV4096, LIRC }; +static const int wdt2_parent_idx[] =3D { -1, LXT, PCLK4_DIV4096, LIRC }; +static const int wwdt0_parent_idx[] =3D { -1, -1, PCLK3_DIV4096, LIRC }; +static const int wwdt1_parent_idx[] =3D { -1, -1, PCLK3_DIV4096, LIRC }; +static const int wwdt2_parent_idx[] =3D { -1, -1, PCLK4_DIV4096, LIRC }; +static const int spi0_parent_idx[] =3D { PCLK1, APLL }; +static const int spi1_parent_idx[] =3D { PCLK2, APLL }; +static const int spi2_parent_idx[] =3D { PCLK1, APLL }; +static const int spi3_parent_idx[] =3D { PCLK2, APLL }; +static const int qspi_parent_idx[] =3D { PCLK0, APLL }; +static const int i2s_parent_idx[] =3D { APLL, SYSCLK1_DIV2 }; +static const int can_parent_idx[] =3D { APLL, VPLL }; +static const int cko_parent_idx[] =3D { HXT, LXT, HIRC, LIRC, + AXICLK_DIV4, SYSPLL, DDRPLL, + EPLL_DIV2, APLL, VPLL }; +static const int smc_parent_idx[] =3D { HXT, PCLK4 }; +static const int kpi_parent_idx[] =3D { HXT, LXT }; =20 static const struct clk_div_table ip_div_table[] =3D { {0, 2}, {1, 4}, {2, 6}, {3, 8}, {4, 10}, @@ -375,24 +124,20 @@ static struct clk_hw *ma35d1_clk_fixed(const char *na= me, int rate) return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); } =20 -static struct clk_hw *ma35d1_clk_mux_parent(struct device *dev, const char= *name, - void __iomem *reg, u8 shift, u8 width, - const struct clk_parent_data *pdata, - int num_pdata) -{ - return clk_hw_register_mux_parent_data(dev, name, pdata, num_pdata, - CLK_SET_RATE_NO_REPARENT, reg, shift, - width, 0, &ma35d1_lock); -} - static struct clk_hw *ma35d1_clk_mux(struct device *dev, const char *name, void __iomem *reg, u8 shift, u8 width, - const struct clk_parent_data *pdata, - int num_pdata) + struct clk_hw **hws, + const int *parent_idx, int num_parents) { - return clk_hw_register_mux_parent_data(dev, name, pdata, num_pdata, - CLK_SET_RATE_NO_REPARENT, reg, shift, - width, 0, &ma35d1_lock); + const struct clk_hw *parent_hws[MA35D1_MUX_MAX_PARENTS] =3D {}; + int i; + + for (i =3D 0; i < num_parents; i++) + parent_hws[i] =3D (parent_idx[i] >=3D 0) ? hws[parent_idx[i]] : NULL; + + return devm_clk_hw_register_mux_parent_hws(dev, name, parent_hws, num_par= ents, + CLK_SET_RATE_NO_REPARENT, reg, shift, + width, 0, &ma35d1_lock); } =20 static struct clk_hw *ma35d1_clk_divider(struct device *dev, const char *n= ame, @@ -515,22 +260,17 @@ static int ma35d1_clocks_probe(struct platform_device= *pdev) hws[EPLL_DIV4] =3D ma35d1_clk_fixed_factor(dev, "epll_div4", "epll", 1, 4= ); hws[EPLL_DIV8] =3D ma35d1_clk_fixed_factor(dev, "epll_div8", "epll", 1, 8= ); =20 - hws[CA35CLK_MUX] =3D ma35d1_clk_mux_parent(dev, "ca35clk_mux", - clk_base + REG_CLK_CLKSEL0, 0, 2, - ca35clk_sel_clks, - ARRAY_SIZE(ca35clk_sel_clks)); + hws[CA35CLK_MUX] =3D ma35d1_clk_mux(dev, "ca35clk_mux", clk_base + REG_CL= K_CLKSEL0, 0, 2, hws, + ca35clk_parent_idx, ARRAY_SIZE(ca35clk_parent_idx)); hws[AXICLK_DIV2] =3D ma35d1_clk_fixed_factor(dev, "capll_div2", "ca35clk_= mux", 1, 2); hws[AXICLK_DIV4] =3D ma35d1_clk_fixed_factor(dev, "capll_div4", "ca35clk_= mux", 1, 4); =20 - hws[AXICLK_MUX] =3D ma35d1_clk_mux(dev, "axiclk_mux", clk_base + REG_CLK_= CLKDIV0, - 26, 1, axiclk_sel_clks, - ARRAY_SIZE(axiclk_sel_clks)); - hws[SYSCLK0_MUX] =3D ma35d1_clk_mux(dev, "sysclk0_mux", clk_base + REG_CL= K_CLKSEL0, - 2, 1, sysclk0_sel_clks, - ARRAY_SIZE(sysclk0_sel_clks)); - hws[SYSCLK1_MUX] =3D ma35d1_clk_mux(dev, "sysclk1_mux", clk_base + REG_CL= K_CLKSEL0, - 4, 1, sysclk1_sel_clks, - ARRAY_SIZE(sysclk1_sel_clks)); + hws[AXICLK_MUX] =3D ma35d1_clk_mux(dev, "axiclk_mux", clk_base + REG_CLK_= CLKDIV0, 26, 1, hws, + axiclk_parent_idx, ARRAY_SIZE(axiclk_parent_idx)); + hws[SYSCLK0_MUX] =3D ma35d1_clk_mux(dev, "sysclk0_mux", clk_base + REG_CL= K_CLKSEL0, 2, 1, hws, + sysclk0_parent_idx, ARRAY_SIZE(sysclk0_parent_idx)); + hws[SYSCLK1_MUX] =3D ma35d1_clk_mux(dev, "sysclk1_mux", clk_base + REG_CL= K_CLKSEL0, 4, 1, hws, + sysclk1_parent_idx, ARRAY_SIZE(sysclk1_parent_idx)); hws[SYSCLK1_DIV2] =3D ma35d1_clk_fixed_factor(dev, "sysclk1_div2", "syscl= k1_mux", 1, 2); =20 /* HCLK0~3 & PCLK0~4 */ @@ -556,41 +296,41 @@ static int ma35d1_clocks_probe(struct platform_device= *pdev) hws[DDR6_GATE] =3D ma35d1_clk_gate(dev, "ddr6_gate", "ddrpll", clk_base + REG_CLK_SYSCLK0, 5); =20 - hws[CAN0_MUX] =3D ma35d1_clk_mux(dev, "can0_mux", clk_base + REG_CLK_CLKS= EL4, - 16, 1, can_sel_clks, ARRAY_SIZE(can_sel_clks)); + hws[CAN0_MUX] =3D ma35d1_clk_mux(dev, "can0_mux", clk_base + REG_CLK_CLKS= EL4, 16, 1, hws, + can_parent_idx, ARRAY_SIZE(can_parent_idx)); hws[CAN0_DIV] =3D ma35d1_clk_divider_table(dev, "can0_div", "can0_mux", clk_base + REG_CLK_CLKDIV0, 0, 3, ip_div_table); hws[CAN0_GATE] =3D ma35d1_clk_gate(dev, "can0_gate", "can0_div", clk_base + REG_CLK_SYSCLK0, 8); - hws[CAN1_MUX] =3D ma35d1_clk_mux(dev, "can1_mux", clk_base + REG_CLK_CLKS= EL4, - 17, 1, can_sel_clks, ARRAY_SIZE(can_sel_clks)); + hws[CAN1_MUX] =3D ma35d1_clk_mux(dev, "can1_mux", clk_base + REG_CLK_CLKS= EL4, 17, 1, hws, + can_parent_idx, ARRAY_SIZE(can_parent_idx)); hws[CAN1_DIV] =3D ma35d1_clk_divider_table(dev, "can1_div", "can1_mux", clk_base + REG_CLK_CLKDIV0, 4, 3, ip_div_table); hws[CAN1_GATE] =3D ma35d1_clk_gate(dev, "can1_gate", "can1_div", clk_base + REG_CLK_SYSCLK0, 9); - hws[CAN2_MUX] =3D ma35d1_clk_mux(dev, "can2_mux", clk_base + REG_CLK_CLKS= EL4, - 18, 1, can_sel_clks, ARRAY_SIZE(can_sel_clks)); + hws[CAN2_MUX] =3D ma35d1_clk_mux(dev, "can2_mux", clk_base + REG_CLK_CLKS= EL4, 18, 1, hws, + can_parent_idx, ARRAY_SIZE(can_parent_idx)); hws[CAN2_DIV] =3D ma35d1_clk_divider_table(dev, "can2_div", "can2_mux", clk_base + REG_CLK_CLKDIV0, 8, 3, ip_div_table); hws[CAN2_GATE] =3D ma35d1_clk_gate(dev, "can2_gate", "can2_div", clk_base + REG_CLK_SYSCLK0, 10); - hws[CAN3_MUX] =3D ma35d1_clk_mux(dev, "can3_mux", clk_base + REG_CLK_CLKS= EL4, - 19, 1, can_sel_clks, ARRAY_SIZE(can_sel_clks)); + hws[CAN3_MUX] =3D ma35d1_clk_mux(dev, "can3_mux", clk_base + REG_CLK_CLKS= EL4, 19, 1, hws, + can_parent_idx, ARRAY_SIZE(can_parent_idx)); hws[CAN3_DIV] =3D ma35d1_clk_divider_table(dev, "can3_div", "can3_mux", clk_base + REG_CLK_CLKDIV0, 12, 3, ip_div_table); hws[CAN3_GATE] =3D ma35d1_clk_gate(dev, "can3_gate", "can3_div", clk_base + REG_CLK_SYSCLK0, 11); =20 - hws[SDH0_MUX] =3D ma35d1_clk_mux(dev, "sdh0_mux", clk_base + REG_CLK_CLKS= EL0, - 16, 2, sdh_sel_clks, ARRAY_SIZE(sdh_sel_clks)); + hws[SDH0_MUX] =3D ma35d1_clk_mux(dev, "sdh0_mux", clk_base + REG_CLK_CLKS= EL0, 16, 2, hws, + sdh_parent_idx, ARRAY_SIZE(sdh_parent_idx)); hws[SDH0_GATE] =3D ma35d1_clk_gate(dev, "sdh0_gate", "sdh0_mux", clk_base + REG_CLK_SYSCLK0, 16); - hws[SDH1_MUX] =3D ma35d1_clk_mux(dev, "sdh1_mux", clk_base + REG_CLK_CLKS= EL0, - 18, 2, sdh_sel_clks, ARRAY_SIZE(sdh_sel_clks)); + hws[SDH1_MUX] =3D ma35d1_clk_mux(dev, "sdh1_mux", clk_base + REG_CLK_CLKS= EL0, 18, 2, hws, + sdh_parent_idx, ARRAY_SIZE(sdh_parent_idx)); hws[SDH1_GATE] =3D ma35d1_clk_gate(dev, "sdh1_gate", "sdh1_mux", clk_base + REG_CLK_SYSCLK0, 17); =20 @@ -606,14 +346,14 @@ static int ma35d1_clocks_probe(struct platform_device= *pdev) hws[HUSBH1_GATE] =3D ma35d1_clk_gate(dev, "husbh1_gate", "usbphy0", clk_base + REG_CLK_SYSCLK0, 22); =20 - hws[GFX_MUX] =3D ma35d1_clk_mux(dev, "gfx_mux", clk_base + REG_CLK_CLKSEL= 0, - 26, 1, gfx_sel_clks, ARRAY_SIZE(gfx_sel_clks)); + hws[GFX_MUX] =3D ma35d1_clk_mux(dev, "gfx_mux", clk_base + REG_CLK_CLKSEL= 0, 26, 1, hws, + gfx_parent_idx, ARRAY_SIZE(gfx_parent_idx)); hws[GFX_GATE] =3D ma35d1_clk_gate(dev, "gfx_gate", "gfx_mux", clk_base + REG_CLK_SYSCLK0, 24); hws[VC8K_GATE] =3D ma35d1_clk_gate(dev, "vc8k_gate", "sysclk0_mux", clk_base + REG_CLK_SYSCLK0, 25); - hws[DCU_MUX] =3D ma35d1_clk_mux(dev, "dcu_mux", clk_base + REG_CLK_CLKSEL= 0, - 24, 1, dcu_sel_clks, ARRAY_SIZE(dcu_sel_clks)); + hws[DCU_MUX] =3D ma35d1_clk_mux(dev, "dcu_mux", clk_base + REG_CLK_CLKSEL= 0, 24, 1, hws, + dcu_parent_idx, ARRAY_SIZE(dcu_parent_idx)); hws[DCU_GATE] =3D ma35d1_clk_gate(dev, "dcu_gate", "dcu_mux", clk_base + REG_CLK_SYSCLK0, 26); hws[DCUP_DIV] =3D ma35d1_clk_divider_table(dev, "dcup_div", "vpll", @@ -625,14 +365,14 @@ static int ma35d1_clocks_probe(struct platform_device= *pdev) hws[EMAC1_GATE] =3D ma35d1_clk_gate(dev, "emac1_gate", "epll_div2", clk_base + REG_CLK_SYSCLK0, 28); =20 - hws[CCAP0_MUX] =3D ma35d1_clk_mux(dev, "ccap0_mux", clk_base + REG_CLK_CL= KSEL0, - 12, 1, ccap_sel_clks, ARRAY_SIZE(ccap_sel_clks)); + hws[CCAP0_MUX] =3D ma35d1_clk_mux(dev, "ccap0_mux", clk_base + REG_CLK_CL= KSEL0, 12, 1, hws, + ccap_parent_idx, ARRAY_SIZE(ccap_parent_idx)); hws[CCAP0_DIV] =3D ma35d1_clk_divider(dev, "ccap0_div", "ccap0_mux", clk_base + REG_CLK_CLKDIV1, 8, 4); hws[CCAP0_GATE] =3D ma35d1_clk_gate(dev, "ccap0_gate", "ccap0_div", clk_base + REG_CLK_SYSCLK0, 29); - hws[CCAP1_MUX] =3D ma35d1_clk_mux(dev, "ccap1_mux", clk_base + REG_CLK_CL= KSEL0, - 14, 1, ccap_sel_clks, ARRAY_SIZE(ccap_sel_clks)); + hws[CCAP1_MUX] =3D ma35d1_clk_mux(dev, "ccap1_mux", clk_base + REG_CLK_CL= KSEL0, 14, 1, hws, + ccap_parent_idx, ARRAY_SIZE(ccap_parent_idx)); hws[CCAP1_DIV] =3D ma35d1_clk_divider(dev, "ccap1_div", "ccap1_mux", clk_base + REG_CLK_CLKDIV1, 12, 4); @@ -670,13 +410,13 @@ static int ma35d1_clocks_probe(struct platform_device= *pdev) hws[TRA_GATE] =3D ma35d1_clk_gate(dev, "tra_gate", "hclk0", clk_base + REG_CLK_SYSCLK1, 11); =20 - hws[DBG_MUX] =3D ma35d1_clk_mux(dev, "dbg_mux", clk_base + REG_CLK_CLKSEL= 0, - 27, 1, dbg_sel_clks, ARRAY_SIZE(dbg_sel_clks)); + hws[DBG_MUX] =3D ma35d1_clk_mux(dev, "dbg_mux", clk_base + REG_CLK_CLKSEL= 0, 27, 1, hws, + dbg_parent_idx, ARRAY_SIZE(dbg_parent_idx)); hws[DBG_GATE] =3D ma35d1_clk_gate(dev, "dbg_gate", "hclk0", clk_base + REG_CLK_SYSCLK1, 12); =20 - hws[CKO_MUX] =3D ma35d1_clk_mux(dev, "cko_mux", clk_base + REG_CLK_CLKSEL= 4, - 24, 4, cko_sel_clks, ARRAY_SIZE(cko_sel_clks)); + hws[CKO_MUX] =3D ma35d1_clk_mux(dev, "cko_mux", clk_base + REG_CLK_CLKSEL= 4, 24, 4, hws, + cko_parent_idx, ARRAY_SIZE(cko_parent_idx)); hws[CKO_DIV] =3D ma35d1_clk_divider_pow2(dev, "cko_div", "cko_mux", clk_base + REG_CLK_CLKOCTL, 0, 4); hws[CKO_GATE] =3D ma35d1_clk_gate(dev, "cko_gate", "cko_div", @@ -714,181 +454,169 @@ static int ma35d1_clocks_probe(struct platform_devi= ce *pdev) hws[GPN_GATE] =3D ma35d1_clk_gate(dev, "gpn_gate", "hclk0", clk_base + REG_CLK_SYSCLK1, 29); =20 - hws[TMR0_MUX] =3D ma35d1_clk_mux(dev, "tmr0_mux", clk_base + REG_CLK_CLKS= EL1, - 0, 3, timer0_sel_clks, - ARRAY_SIZE(timer0_sel_clks)); + hws[TMR0_MUX] =3D ma35d1_clk_mux(dev, "tmr0_mux", clk_base + REG_CLK_CLKS= EL1, 0, 3, hws, + timer0_parent_idx, ARRAY_SIZE(timer0_parent_idx)); hws[TMR0_GATE] =3D ma35d1_clk_gate(dev, "tmr0_gate", "tmr0_mux", clk_base + REG_CLK_APBCLK0, 0); - hws[TMR1_MUX] =3D ma35d1_clk_mux(dev, "tmr1_mux", clk_base + REG_CLK_CLKS= EL1, - 4, 3, timer1_sel_clks, - ARRAY_SIZE(timer1_sel_clks)); + hws[TMR1_MUX] =3D ma35d1_clk_mux(dev, "tmr1_mux", clk_base + REG_CLK_CLKS= EL1, 4, 3, hws, + timer1_parent_idx, ARRAY_SIZE(timer1_parent_idx)); hws[TMR1_GATE] =3D ma35d1_clk_gate(dev, "tmr1_gate", "tmr1_mux", clk_base + REG_CLK_APBCLK0, 1); - hws[TMR2_MUX] =3D ma35d1_clk_mux(dev, "tmr2_mux", clk_base + REG_CLK_CLKS= EL1, - 8, 3, timer2_sel_clks, - ARRAY_SIZE(timer2_sel_clks)); + hws[TMR2_MUX] =3D ma35d1_clk_mux(dev, "tmr2_mux", clk_base + REG_CLK_CLKS= EL1, 8, 3, hws, + timer2_parent_idx, ARRAY_SIZE(timer2_parent_idx)); hws[TMR2_GATE] =3D ma35d1_clk_gate(dev, "tmr2_gate", "tmr2_mux", clk_base + REG_CLK_APBCLK0, 2); - hws[TMR3_MUX] =3D ma35d1_clk_mux(dev, "tmr3_mux", clk_base + REG_CLK_CLKS= EL1, - 12, 3, timer3_sel_clks, - ARRAY_SIZE(timer3_sel_clks)); + hws[TMR3_MUX] =3D ma35d1_clk_mux(dev, "tmr3_mux", clk_base + REG_CLK_CLKS= EL1, 12, 3, hws, + timer3_parent_idx, ARRAY_SIZE(timer3_parent_idx)); hws[TMR3_GATE] =3D ma35d1_clk_gate(dev, "tmr3_gate", "tmr3_mux", clk_base + REG_CLK_APBCLK0, 3); - hws[TMR4_MUX] =3D ma35d1_clk_mux(dev, "tmr4_mux", clk_base + REG_CLK_CLKS= EL1, - 16, 3, timer4_sel_clks, - ARRAY_SIZE(timer4_sel_clks)); + hws[TMR4_MUX] =3D ma35d1_clk_mux(dev, "tmr4_mux", clk_base + REG_CLK_CLKS= EL1, 16, 3, hws, + timer4_parent_idx, ARRAY_SIZE(timer4_parent_idx)); hws[TMR4_GATE] =3D ma35d1_clk_gate(dev, "tmr4_gate", "tmr4_mux", clk_base + REG_CLK_APBCLK0, 4); - hws[TMR5_MUX] =3D ma35d1_clk_mux(dev, "tmr5_mux", clk_base + REG_CLK_CLKS= EL1, - 20, 3, timer5_sel_clks, - ARRAY_SIZE(timer5_sel_clks)); + hws[TMR5_MUX] =3D ma35d1_clk_mux(dev, "tmr5_mux", clk_base + REG_CLK_CLKS= EL1, 20, 3, hws, + timer5_parent_idx, ARRAY_SIZE(timer5_parent_idx)); hws[TMR5_GATE] =3D ma35d1_clk_gate(dev, "tmr5_gate", "tmr5_mux", clk_base + REG_CLK_APBCLK0, 5); - hws[TMR6_MUX] =3D ma35d1_clk_mux(dev, "tmr6_mux", clk_base + REG_CLK_CLKS= EL1, - 24, 3, timer6_sel_clks, - ARRAY_SIZE(timer6_sel_clks)); + hws[TMR6_MUX] =3D ma35d1_clk_mux(dev, "tmr6_mux", clk_base + REG_CLK_CLKS= EL1, 24, 3, hws, + timer6_parent_idx, ARRAY_SIZE(timer6_parent_idx)); hws[TMR6_GATE] =3D ma35d1_clk_gate(dev, "tmr6_gate", "tmr6_mux", clk_base + REG_CLK_APBCLK0, 6); - hws[TMR7_MUX] =3D ma35d1_clk_mux(dev, "tmr7_mux", clk_base + REG_CLK_CLKS= EL1, - 28, 3, timer7_sel_clks, - ARRAY_SIZE(timer7_sel_clks)); + hws[TMR7_MUX] =3D ma35d1_clk_mux(dev, "tmr7_mux", clk_base + REG_CLK_CLKS= EL1, 28, 3, hws, + timer7_parent_idx, ARRAY_SIZE(timer7_parent_idx)); hws[TMR7_GATE] =3D ma35d1_clk_gate(dev, "tmr7_gate", "tmr7_mux", clk_base + REG_CLK_APBCLK0, 7); - hws[TMR8_MUX] =3D ma35d1_clk_mux(dev, "tmr8_mux", clk_base + REG_CLK_CLKS= EL2, - 0, 3, timer8_sel_clks, - ARRAY_SIZE(timer8_sel_clks)); + hws[TMR8_MUX] =3D ma35d1_clk_mux(dev, "tmr8_mux", clk_base + REG_CLK_CLKS= EL2, 0, 3, hws, + timer8_parent_idx, ARRAY_SIZE(timer8_parent_idx)); hws[TMR8_GATE] =3D ma35d1_clk_gate(dev, "tmr8_gate", "tmr8_mux", clk_base + REG_CLK_APBCLK0, 8); - hws[TMR9_MUX] =3D ma35d1_clk_mux(dev, "tmr9_mux", clk_base + REG_CLK_CLKS= EL2, - 4, 3, timer9_sel_clks, - ARRAY_SIZE(timer9_sel_clks)); + hws[TMR9_MUX] =3D ma35d1_clk_mux(dev, "tmr9_mux", clk_base + REG_CLK_CLKS= EL2, 4, 3, hws, + timer9_parent_idx, ARRAY_SIZE(timer9_parent_idx)); hws[TMR9_GATE] =3D ma35d1_clk_gate(dev, "tmr9_gate", "tmr9_mux", clk_base + REG_CLK_APBCLK0, 9); - hws[TMR10_MUX] =3D ma35d1_clk_mux(dev, "tmr10_mux", clk_base + REG_CLK_CL= KSEL2, - 8, 3, timer10_sel_clks, - ARRAY_SIZE(timer10_sel_clks)); + hws[TMR10_MUX] =3D ma35d1_clk_mux(dev, "tmr10_mux", clk_base + REG_CLK_CL= KSEL2, 8, 3, hws, + timer10_parent_idx, ARRAY_SIZE(timer10_parent_idx)); hws[TMR10_GATE] =3D ma35d1_clk_gate(dev, "tmr10_gate", "tmr10_mux", clk_base + REG_CLK_APBCLK0, 10); - hws[TMR11_MUX] =3D ma35d1_clk_mux(dev, "tmr11_mux", clk_base + REG_CLK_CL= KSEL2, - 12, 3, timer11_sel_clks, - ARRAY_SIZE(timer11_sel_clks)); + hws[TMR11_MUX] =3D ma35d1_clk_mux(dev, "tmr11_mux", clk_base + REG_CLK_CL= KSEL2, 12, 3, hws, + timer11_parent_idx, ARRAY_SIZE(timer11_parent_idx)); hws[TMR11_GATE] =3D ma35d1_clk_gate(dev, "tmr11_gate", "tmr11_mux", clk_base + REG_CLK_APBCLK0, 11); =20 - hws[UART0_MUX] =3D ma35d1_clk_mux(dev, "uart0_mux", clk_base + REG_CLK_CL= KSEL2, - 16, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART0_MUX] =3D ma35d1_clk_mux(dev, "uart0_mux", clk_base + REG_CLK_CL= KSEL2, 16, 2, hws, + uart_parent_idx, ARRAY_SIZE(uart_parent_idx)); hws[UART0_DIV] =3D ma35d1_clk_divider(dev, "uart0_div", "uart0_mux", clk_base + REG_CLK_CLKDIV1, 16, 4); hws[UART0_GATE] =3D ma35d1_clk_gate(dev, "uart0_gate", "uart0_div", clk_base + REG_CLK_APBCLK0, 12); - hws[UART1_MUX] =3D ma35d1_clk_mux(dev, "uart1_mux", clk_base + REG_CLK_CL= KSEL2, - 18, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART1_MUX] =3D ma35d1_clk_mux(dev, "uart1_mux", clk_base + REG_CLK_CL= KSEL2, 18, 2, hws, + uart_parent_idx, ARRAY_SIZE(uart_parent_idx)); hws[UART1_DIV] =3D ma35d1_clk_divider(dev, "uart1_div", "uart1_mux", clk_base + REG_CLK_CLKDIV1, 20, 4); hws[UART1_GATE] =3D ma35d1_clk_gate(dev, "uart1_gate", "uart1_div", clk_base + REG_CLK_APBCLK0, 13); - hws[UART2_MUX] =3D ma35d1_clk_mux(dev, "uart2_mux", clk_base + REG_CLK_CL= KSEL2, - 20, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART2_MUX] =3D ma35d1_clk_mux(dev, "uart2_mux", clk_base + REG_CLK_CL= KSEL2, 20, 2, hws, + uart_parent_idx, ARRAY_SIZE(uart_parent_idx)); hws[UART2_DIV] =3D ma35d1_clk_divider(dev, "uart2_div", "uart2_mux", clk_base + REG_CLK_CLKDIV1, 24, 4); hws[UART2_GATE] =3D ma35d1_clk_gate(dev, "uart2_gate", "uart2_div", clk_base + REG_CLK_APBCLK0, 14); - hws[UART3_MUX] =3D ma35d1_clk_mux(dev, "uart3_mux", clk_base + REG_CLK_CL= KSEL2, - 22, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART3_MUX] =3D ma35d1_clk_mux(dev, "uart3_mux", clk_base + REG_CLK_CL= KSEL2, 22, 2, hws, + uart_parent_idx, ARRAY_SIZE(uart_parent_idx)); hws[UART3_DIV] =3D ma35d1_clk_divider(dev, "uart3_div", "uart3_mux", clk_base + REG_CLK_CLKDIV1, 28, 4); hws[UART3_GATE] =3D ma35d1_clk_gate(dev, "uart3_gate", "uart3_div", clk_base + REG_CLK_APBCLK0, 15); - hws[UART4_MUX] =3D ma35d1_clk_mux(dev, "uart4_mux", clk_base + REG_CLK_CL= KSEL2, - 24, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART4_MUX] =3D ma35d1_clk_mux(dev, "uart4_mux", clk_base + REG_CLK_CL= KSEL2, 24, 2, hws, + uart_parent_idx, ARRAY_SIZE(uart_parent_idx)); hws[UART4_DIV] =3D ma35d1_clk_divider(dev, "uart4_div", "uart4_mux", clk_base + REG_CLK_CLKDIV2, 0, 4); hws[UART4_GATE] =3D ma35d1_clk_gate(dev, "uart4_gate", "uart4_div", clk_base + REG_CLK_APBCLK0, 16); - hws[UART5_MUX] =3D ma35d1_clk_mux(dev, "uart5_mux", clk_base + REG_CLK_CL= KSEL2, - 26, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART5_MUX] =3D ma35d1_clk_mux(dev, "uart5_mux", clk_base + REG_CLK_CL= KSEL2, 26, 2, hws, + uart_parent_idx, ARRAY_SIZE(uart_parent_idx)); hws[UART5_DIV] =3D ma35d1_clk_divider(dev, "uart5_div", "uart5_mux", clk_base + REG_CLK_CLKDIV2, 4, 4); hws[UART5_GATE] =3D ma35d1_clk_gate(dev, "uart5_gate", "uart5_div", clk_base + REG_CLK_APBCLK0, 17); - hws[UART6_MUX] =3D ma35d1_clk_mux(dev, "uart6_mux", clk_base + REG_CLK_CL= KSEL2, - 28, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART6_MUX] =3D ma35d1_clk_mux(dev, "uart6_mux", clk_base + REG_CLK_CL= KSEL2, 28, 2, hws, + uart_parent_idx, ARRAY_SIZE(uart_parent_idx)); hws[UART6_DIV] =3D ma35d1_clk_divider(dev, "uart6_div", "uart6_mux", clk_base + REG_CLK_CLKDIV2, 8, 4); hws[UART6_GATE] =3D ma35d1_clk_gate(dev, "uart6_gate", "uart6_div", clk_base + REG_CLK_APBCLK0, 18); - hws[UART7_MUX] =3D ma35d1_clk_mux(dev, "uart7_mux", clk_base + REG_CLK_CL= KSEL2, - 30, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART7_MUX] =3D ma35d1_clk_mux(dev, "uart7_mux", clk_base + REG_CLK_CL= KSEL2, 30, 2, hws, + uart_parent_idx, ARRAY_SIZE(uart_parent_idx)); hws[UART7_DIV] =3D ma35d1_clk_divider(dev, "uart7_div", "uart7_mux", clk_base + REG_CLK_CLKDIV2, 12, 4); hws[UART7_GATE] =3D ma35d1_clk_gate(dev, "uart7_gate", "uart7_div", clk_base + REG_CLK_APBCLK0, 19); - hws[UART8_MUX] =3D ma35d1_clk_mux(dev, "uart8_mux", clk_base + REG_CLK_CL= KSEL3, - 0, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART8_MUX] =3D ma35d1_clk_mux(dev, "uart8_mux", clk_base + REG_CLK_CL= KSEL3, 0, 2, hws, + uart_parent_idx, ARRAY_SIZE(uart_parent_idx)); hws[UART8_DIV] =3D ma35d1_clk_divider(dev, "uart8_div", "uart8_mux", clk_base + REG_CLK_CLKDIV2, 16, 4); hws[UART8_GATE] =3D ma35d1_clk_gate(dev, "uart8_gate", "uart8_div", clk_base + REG_CLK_APBCLK0, 20); - hws[UART9_MUX] =3D ma35d1_clk_mux(dev, "uart9_mux", clk_base + REG_CLK_CL= KSEL3, - 2, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART9_MUX] =3D ma35d1_clk_mux(dev, "uart9_mux", clk_base + REG_CLK_CL= KSEL3, 2, 2, hws, + uart_parent_idx, ARRAY_SIZE(uart_parent_idx)); hws[UART9_DIV] =3D ma35d1_clk_divider(dev, "uart9_div", "uart9_mux", clk_base + REG_CLK_CLKDIV2, 20, 4); hws[UART9_GATE] =3D ma35d1_clk_gate(dev, "uart9_gate", "uart9_div", clk_base + REG_CLK_APBCLK0, 21); - hws[UART10_MUX] =3D ma35d1_clk_mux(dev, "uart10_mux", clk_base + REG_CLK_= CLKSEL3, - 4, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART10_MUX] =3D ma35d1_clk_mux(dev, "uart10_mux", clk_base + REG_CLK_= CLKSEL3, 4, 2, hws, + uart_parent_idx, ARRAY_SIZE(uart_parent_idx)); hws[UART10_DIV] =3D ma35d1_clk_divider(dev, "uart10_div", "uart10_mux", clk_base + REG_CLK_CLKDIV2, 24, 4); hws[UART10_GATE] =3D ma35d1_clk_gate(dev, "uart10_gate", "uart10_div", clk_base + REG_CLK_APBCLK0, 22); - hws[UART11_MUX] =3D ma35d1_clk_mux(dev, "uart11_mux", clk_base + REG_CLK_= CLKSEL3, - 6, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART11_MUX] =3D ma35d1_clk_mux(dev, "uart11_mux", clk_base + REG_CLK_= CLKSEL3, 6, 2, hws, + uart_parent_idx, ARRAY_SIZE(uart_parent_idx)); hws[UART11_DIV] =3D ma35d1_clk_divider(dev, "uart11_div", "uart11_mux", clk_base + REG_CLK_CLKDIV2, 28, 4); hws[UART11_GATE] =3D ma35d1_clk_gate(dev, "uart11_gate", "uart11_div", clk_base + REG_CLK_APBCLK0, 23); - hws[UART12_MUX] =3D ma35d1_clk_mux(dev, "uart12_mux", clk_base + REG_CLK_= CLKSEL3, - 8, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART12_MUX] =3D ma35d1_clk_mux(dev, "uart12_mux", clk_base + REG_CLK_= CLKSEL3, 8, 2, hws, + uart_parent_idx, ARRAY_SIZE(uart_parent_idx)); hws[UART12_DIV] =3D ma35d1_clk_divider(dev, "uart12_div", "uart12_mux", clk_base + REG_CLK_CLKDIV3, 0, 4); hws[UART12_GATE] =3D ma35d1_clk_gate(dev, "uart12_gate", "uart12_div", clk_base + REG_CLK_APBCLK0, 24); - hws[UART13_MUX] =3D ma35d1_clk_mux(dev, "uart13_mux", clk_base + REG_CLK_= CLKSEL3, - 10, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART13_MUX] =3D ma35d1_clk_mux(dev, "uart13_mux", clk_base + REG_CLK_= CLKSEL3, 10, 2, hws, + uart_parent_idx, ARRAY_SIZE(uart_parent_idx)); hws[UART13_DIV] =3D ma35d1_clk_divider(dev, "uart13_div", "uart13_mux", clk_base + REG_CLK_CLKDIV3, 4, 4); hws[UART13_GATE] =3D ma35d1_clk_gate(dev, "uart13_gate", "uart13_div", clk_base + REG_CLK_APBCLK0, 25); - hws[UART14_MUX] =3D ma35d1_clk_mux(dev, "uart14_mux", clk_base + REG_CLK_= CLKSEL3, - 12, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART14_MUX] =3D ma35d1_clk_mux(dev, "uart14_mux", clk_base + REG_CLK_= CLKSEL3, 12, 2, hws, + uart_parent_idx, ARRAY_SIZE(uart_parent_idx)); hws[UART14_DIV] =3D ma35d1_clk_divider(dev, "uart14_div", "uart14_mux", clk_base + REG_CLK_CLKDIV3, 8, 4); hws[UART14_GATE] =3D ma35d1_clk_gate(dev, "uart14_gate", "uart14_div", clk_base + REG_CLK_APBCLK0, 26); - hws[UART15_MUX] =3D ma35d1_clk_mux(dev, "uart15_mux", clk_base + REG_CLK_= CLKSEL3, - 14, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART15_MUX] =3D ma35d1_clk_mux(dev, "uart15_mux", clk_base + REG_CLK_= CLKSEL3, 14, 2, hws, + uart_parent_idx, ARRAY_SIZE(uart_parent_idx)); hws[UART15_DIV] =3D ma35d1_clk_divider(dev, "uart15_div", "uart15_mux", clk_base + REG_CLK_CLKDIV3, 12, 4); hws[UART15_GATE] =3D ma35d1_clk_gate(dev, "uart15_gate", "uart15_div", clk_base + REG_CLK_APBCLK0, 27); - hws[UART16_MUX] =3D ma35d1_clk_mux(dev, "uart16_mux", clk_base + REG_CLK_= CLKSEL3, - 16, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART16_MUX] =3D ma35d1_clk_mux(dev, "uart16_mux", clk_base + REG_CLK_= CLKSEL3, 16, 2, hws, + uart_parent_idx, ARRAY_SIZE(uart_parent_idx)); hws[UART16_DIV] =3D ma35d1_clk_divider(dev, "uart16_div", "uart16_mux", clk_base + REG_CLK_CLKDIV3, 16, 4); @@ -900,8 +628,8 @@ static int ma35d1_clocks_probe(struct platform_device *= pdev) hws[DDR_GATE] =3D ma35d1_clk_gate(dev, "ddr_gate", "ddrpll", clk_base + REG_CLK_APBCLK0, 30); =20 - hws[KPI_MUX] =3D ma35d1_clk_mux(dev, "kpi_mux", clk_base + REG_CLK_CLKSEL= 4, - 30, 1, kpi_sel_clks, ARRAY_SIZE(kpi_sel_clks)); + hws[KPI_MUX] =3D ma35d1_clk_mux(dev, "kpi_mux", clk_base + REG_CLK_CLKSEL= 4, 30, 1, hws, + kpi_parent_idx, ARRAY_SIZE(kpi_parent_idx)); hws[KPI_DIV] =3D ma35d1_clk_divider(dev, "kpi_div", "kpi_mux", clk_base + REG_CLK_CLKDIV4, 24, 8); @@ -921,49 +649,49 @@ static int ma35d1_clocks_probe(struct platform_device= *pdev) hws[I2C5_GATE] =3D ma35d1_clk_gate(dev, "i2c5_gate", "pclk2", clk_base + REG_CLK_APBCLK1, 5); =20 - hws[QSPI0_MUX] =3D ma35d1_clk_mux(dev, "qspi0_mux", clk_base + REG_CLK_CL= KSEL4, - 8, 2, qspi0_sel_clks, ARRAY_SIZE(qspi0_sel_clks)); + hws[QSPI0_MUX] =3D ma35d1_clk_mux(dev, "qspi0_mux", clk_base + REG_CLK_CL= KSEL4, 8, 2, hws, + qspi_parent_idx, ARRAY_SIZE(qspi_parent_idx)); hws[QSPI0_GATE] =3D ma35d1_clk_gate(dev, "qspi0_gate", "qspi0_mux", clk_base + REG_CLK_APBCLK1, 6); - hws[QSPI1_MUX] =3D ma35d1_clk_mux(dev, "qspi1_mux", clk_base + REG_CLK_CL= KSEL4, - 10, 2, qspi1_sel_clks, ARRAY_SIZE(qspi1_sel_clks)); + hws[QSPI1_MUX] =3D ma35d1_clk_mux(dev, "qspi1_mux", clk_base + REG_CLK_CL= KSEL4, 10, 2, hws, + qspi_parent_idx, ARRAY_SIZE(qspi_parent_idx)); hws[QSPI1_GATE] =3D ma35d1_clk_gate(dev, "qspi1_gate", "qspi1_mux", clk_base + REG_CLK_APBCLK1, 7); =20 - hws[SMC0_MUX] =3D ma35d1_clk_mux(dev, "smc0_mux", clk_base + REG_CLK_CLKS= EL4, - 28, 1, smc_sel_clks, ARRAY_SIZE(smc_sel_clks)); + hws[SMC0_MUX] =3D ma35d1_clk_mux(dev, "smc0_mux", clk_base + REG_CLK_CLKS= EL4, 28, 1, hws, + smc_parent_idx, ARRAY_SIZE(smc_parent_idx)); hws[SMC0_DIV] =3D ma35d1_clk_divider(dev, "smc0_div", "smc0_mux", clk_base + REG_CLK_CLKDIV1, 0, 4); hws[SMC0_GATE] =3D ma35d1_clk_gate(dev, "smc0_gate", "smc0_div", clk_base + REG_CLK_APBCLK1, 12); - hws[SMC1_MUX] =3D ma35d1_clk_mux(dev, "smc1_mux", clk_base + REG_CLK_CLKS= EL4, - 29, 1, smc_sel_clks, ARRAY_SIZE(smc_sel_clks)); + hws[SMC1_MUX] =3D ma35d1_clk_mux(dev, "smc1_mux", clk_base + REG_CLK_CLKS= EL4, 29, 1, hws, + smc_parent_idx, ARRAY_SIZE(smc_parent_idx)); hws[SMC1_DIV] =3D ma35d1_clk_divider(dev, "smc1_div", "smc1_mux", clk_base + REG_CLK_CLKDIV1, 4, 4); hws[SMC1_GATE] =3D ma35d1_clk_gate(dev, "smc1_gate", "smc1_div", clk_base + REG_CLK_APBCLK1, 13); =20 - hws[WDT0_MUX] =3D ma35d1_clk_mux(dev, "wdt0_mux", clk_base + REG_CLK_CLKS= EL3, - 20, 2, wdt0_sel_clks, ARRAY_SIZE(wdt0_sel_clks)); + hws[WDT0_MUX] =3D ma35d1_clk_mux(dev, "wdt0_mux", clk_base + REG_CLK_CLKS= EL3, 20, 2, hws, + wdt0_parent_idx, ARRAY_SIZE(wdt0_parent_idx)); hws[WDT0_GATE] =3D ma35d1_clk_gate(dev, "wdt0_gate", "wdt0_mux", clk_base + REG_CLK_APBCLK1, 16); - hws[WDT1_MUX] =3D ma35d1_clk_mux(dev, "wdt1_mux", clk_base + REG_CLK_CLKS= EL3, - 24, 2, wdt1_sel_clks, ARRAY_SIZE(wdt1_sel_clks)); + hws[WDT1_MUX] =3D ma35d1_clk_mux(dev, "wdt1_mux", clk_base + REG_CLK_CLKS= EL3, 24, 2, hws, + wdt1_parent_idx, ARRAY_SIZE(wdt1_parent_idx)); hws[WDT1_GATE] =3D ma35d1_clk_gate(dev, "wdt1_gate", "wdt1_mux", clk_base + REG_CLK_APBCLK1, 17); - hws[WDT2_MUX] =3D ma35d1_clk_mux(dev, "wdt2_mux", clk_base + REG_CLK_CLKS= EL3, - 28, 2, wdt2_sel_clks, ARRAY_SIZE(wdt2_sel_clks)); + hws[WDT2_MUX] =3D ma35d1_clk_mux(dev, "wdt2_mux", clk_base + REG_CLK_CLKS= EL3, 28, 2, hws, + wdt2_parent_idx, ARRAY_SIZE(wdt2_parent_idx)); hws[WDT2_GATE] =3D ma35d1_clk_gate(dev, "wdt2_gate", "wdt2_mux", clk_base + REG_CLK_APBCLK1, 18); =20 - hws[WWDT0_MUX] =3D ma35d1_clk_mux(dev, "wwdt0_mux", clk_base + REG_CLK_CL= KSEL3, - 22, 2, wwdt0_sel_clks, ARRAY_SIZE(wwdt0_sel_clks)); - hws[WWDT1_MUX] =3D ma35d1_clk_mux(dev, "wwdt1_mux", clk_base + REG_CLK_CL= KSEL3, - 26, 2, wwdt1_sel_clks, ARRAY_SIZE(wwdt1_sel_clks)); - hws[WWDT2_MUX] =3D ma35d1_clk_mux(dev, "wwdt2_mux", clk_base + REG_CLK_CL= KSEL3, - 30, 2, wwdt2_sel_clks, ARRAY_SIZE(wwdt2_sel_clks)); + hws[WWDT0_MUX] =3D ma35d1_clk_mux(dev, "wwdt0_mux", clk_base + REG_CLK_CL= KSEL3, 22, 2, hws, + wwdt0_parent_idx, ARRAY_SIZE(wwdt0_parent_idx)); + hws[WWDT1_MUX] =3D ma35d1_clk_mux(dev, "wwdt1_mux", clk_base + REG_CLK_CL= KSEL3, 26, 2, hws, + wwdt1_parent_idx, ARRAY_SIZE(wwdt1_parent_idx)); + hws[WWDT2_MUX] =3D ma35d1_clk_mux(dev, "wwdt2_mux", clk_base + REG_CLK_CL= KSEL3, 30, 2, hws, + wwdt2_parent_idx, ARRAY_SIZE(wwdt2_parent_idx)); =20 hws[EPWM0_GATE] =3D ma35d1_clk_gate(dev, "epwm0_gate", "pclk1", clk_base + REG_CLK_APBCLK1, 24); @@ -972,12 +700,12 @@ static int ma35d1_clocks_probe(struct platform_device= *pdev) hws[EPWM2_GATE] =3D ma35d1_clk_gate(dev, "epwm2_gate", "pclk1", clk_base + REG_CLK_APBCLK1, 26); =20 - hws[I2S0_MUX] =3D ma35d1_clk_mux(dev, "i2s0_mux", clk_base + REG_CLK_CLKS= EL4, - 12, 2, i2s0_sel_clks, ARRAY_SIZE(i2s0_sel_clks)); + hws[I2S0_MUX] =3D ma35d1_clk_mux(dev, "i2s0_mux", clk_base + REG_CLK_CLKS= EL4, 12, 2, hws, + i2s_parent_idx, ARRAY_SIZE(i2s_parent_idx)); hws[I2S0_GATE] =3D ma35d1_clk_gate(dev, "i2s0_gate", "i2s0_mux", clk_base + REG_CLK_APBCLK2, 0); - hws[I2S1_MUX] =3D ma35d1_clk_mux(dev, "i2s1_mux", clk_base + REG_CLK_CLKS= EL4, - 14, 2, i2s1_sel_clks, ARRAY_SIZE(i2s1_sel_clks)); + hws[I2S1_MUX] =3D ma35d1_clk_mux(dev, "i2s1_mux", clk_base + REG_CLK_CLKS= EL4, 14, 2, hws, + i2s_parent_idx, ARRAY_SIZE(i2s_parent_idx)); hws[I2S1_GATE] =3D ma35d1_clk_gate(dev, "i2s1_gate", "i2s1_mux", clk_base + REG_CLK_APBCLK2, 1); =20 @@ -986,20 +714,20 @@ static int ma35d1_clocks_probe(struct platform_device= *pdev) hws[SSPCC_GATE] =3D ma35d1_clk_gate(dev, "sspcc_gate", "pclk3", clk_base + REG_CLK_APBCLK2, 3); =20 - hws[SPI0_MUX] =3D ma35d1_clk_mux(dev, "spi0_mux", clk_base + REG_CLK_CLKS= EL4, - 0, 2, spi0_sel_clks, ARRAY_SIZE(spi0_sel_clks)); + hws[SPI0_MUX] =3D ma35d1_clk_mux(dev, "spi0_mux", clk_base + REG_CLK_CLKS= EL4, 0, 2, hws, + spi0_parent_idx, ARRAY_SIZE(spi0_parent_idx)); hws[SPI0_GATE] =3D ma35d1_clk_gate(dev, "spi0_gate", "spi0_mux", clk_base + REG_CLK_APBCLK2, 4); - hws[SPI1_MUX] =3D ma35d1_clk_mux(dev, "spi1_mux", clk_base + REG_CLK_CLKS= EL4, - 2, 2, spi1_sel_clks, ARRAY_SIZE(spi1_sel_clks)); + hws[SPI1_MUX] =3D ma35d1_clk_mux(dev, "spi1_mux", clk_base + REG_CLK_CLKS= EL4, 2, 2, hws, + spi1_parent_idx, ARRAY_SIZE(spi1_parent_idx)); hws[SPI1_GATE] =3D ma35d1_clk_gate(dev, "spi1_gate", "spi1_mux", clk_base + REG_CLK_APBCLK2, 5); - hws[SPI2_MUX] =3D ma35d1_clk_mux(dev, "spi2_mux", clk_base + REG_CLK_CLKS= EL4, - 4, 2, spi2_sel_clks, ARRAY_SIZE(spi2_sel_clks)); + hws[SPI2_MUX] =3D ma35d1_clk_mux(dev, "spi2_mux", clk_base + REG_CLK_CLKS= EL4, 4, 2, hws, + spi2_parent_idx, ARRAY_SIZE(spi2_parent_idx)); hws[SPI2_GATE] =3D ma35d1_clk_gate(dev, "spi2_gate", "spi2_mux", clk_base + REG_CLK_APBCLK2, 6); - hws[SPI3_MUX] =3D ma35d1_clk_mux(dev, "spi3_mux", clk_base + REG_CLK_CLKS= EL4, - 6, 2, spi3_sel_clks, ARRAY_SIZE(spi3_sel_clks)); + hws[SPI3_MUX] =3D ma35d1_clk_mux(dev, "spi3_mux", clk_base + REG_CLK_CLKS= EL4, 6, 2, hws, + spi3_parent_idx, ARRAY_SIZE(spi3_parent_idx)); hws[SPI3_GATE] =3D ma35d1_clk_gate(dev, "spi3_gate", "spi3_mux", clk_base + REG_CLK_APBCLK2, 7); =20 --=20 2.55.0 From nobody Fri Oct 23 22:16:18 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B0F453F6A7; Thu, 15 Oct 2026 16:01:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792080125; cv=none; b=SBfVmBsPnDA43pl7wS9sM/xqFgjkUxfhlqENN9IqOeuvW/xb8TD+hE8OEfB6b98mjjENQM9zf3PT+FAbKp1uopSDMWLXXs7074dBlnRTqKaM+C0zf7oJ16TY7OEyDEfBdCEfAGISOYGYJGAUYSUT31vMgP91UhyrS7OJF9iamAc= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-perso-ma35d1-upstream-clk-v10-2-47c97b54a809@bootlin.com> References: <20261015-perso-ma35d1-upstream-clk-v10-0-47c97b54a809@bootlin.com> In-Reply-To: <20261015-perso-ma35d1-upstream-clk-v10-0-47c97b54a809@bootlin.com> To: Jacky Huang , Shan-Chun Hung , Michael Turquette , Stephen Boyd , Richard Cochran , Arnd Bergmann , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair Cc: Thomas Petazzoni , Steam Lin , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 MA35D1 registration helpers store their parent_hw argument straight into the parent data, without checking it first. In case of registration failure an error pointer will be stored in the table, which is then forwarded to the clk core, which treats any non-NULL parent as valid handles. Bail out early when the parent is an error pointer, instead of building the parent data. This issue is mostly theoretical in practice, since reaching such an error would involve a very early -ENOMEM. Signed-off-by: Miquel Raynal --- drivers/clk/nuvoton/clk-ma35d1-divider.c | 3 +++ drivers/clk/nuvoton/clk-ma35d1-pll.c | 3 +++ drivers/clk/nuvoton/clk-ma35d1.c | 13 +++++++++++-- 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/clk/nuvoton/clk-ma35d1-divider.c b/drivers/clk/nuvoton= /clk-ma35d1-divider.c index e992e7c30341..57a7b4ed3b5e 100644 --- a/drivers/clk/nuvoton/clk-ma35d1-divider.c +++ b/drivers/clk/nuvoton/clk-ma35d1-divider.c @@ -90,6 +90,9 @@ struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, = const char *name, int ret; int i; =20 + if (IS_ERR(parent_hw)) + return parent_hw; + div =3D devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); if (!div) return ERR_PTR(-ENOMEM); diff --git a/drivers/clk/nuvoton/clk-ma35d1-pll.c b/drivers/clk/nuvoton/clk= -ma35d1-pll.c index c7c0dc91a012..92424e9c669d 100644 --- a/drivers/clk/nuvoton/clk-ma35d1-pll.c +++ b/drivers/clk/nuvoton/clk-ma35d1-pll.c @@ -336,6 +336,9 @@ struct clk_hw *ma35d1_reg_clk_pll(struct device *dev, u= 32 id, u8 u8mode, const c struct clk_hw *hw; int ret; =20 + if (IS_ERR(parent_hw)) + return parent_hw; + pll =3D devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); if (!pll) return ERR_PTR(-ENOMEM); diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma3= 5d1.c index ba3550c083ac..00d635cdb604 100644 --- a/drivers/clk/nuvoton/clk-ma35d1.c +++ b/drivers/clk/nuvoton/clk-ma35d1.c @@ -130,10 +130,19 @@ static struct clk_hw *ma35d1_clk_mux(struct device *d= ev, const char *name, const int *parent_idx, int num_parents) { const struct clk_hw *parent_hws[MA35D1_MUX_MAX_PARENTS] =3D {}; + struct clk_hw *parent; int i; =20 - for (i =3D 0; i < num_parents; i++) - parent_hws[i] =3D (parent_idx[i] >=3D 0) ? hws[parent_idx[i]] : NULL; + for (i =3D 0; i < num_parents; i++) { + if (parent_idx[i] < 0) + continue; + + parent =3D hws[parent_idx[i]]; + if (IS_ERR(parent)) + return parent; + + parent_hws[i] =3D parent; + } =20 return devm_clk_hw_register_mux_parent_hws(dev, name, parent_hws, num_par= ents, CLK_SET_RATE_NO_REPARENT, reg, shift, --=20 2.55.0 From nobody Fri Oct 23 22:16:18 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8970854CF6C; Thu, 15 Oct 2026 16:01:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792080128; cv=none; b=mLKpn9NPiMQe0/zDWlqpiP8VSOjD1NvZizgQovBSQhNtB7gUqmGQTC4Ft1CEQAAeIDmBEz1UrlBPxkMDbvbJ9+IPshGmEBIRIRAl7qoALFVVNSSpgUDxtVl8ZIBN7/sfYGmHYHU/+r+mBXhfdusq+cLqhZLmSDOCQi4XsMEBNsI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792080128; c=relaxed/simple; bh=decc+Wr6UJ0ByH9Edl6BEOzsYbiIxvfP90wgst42Tzk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=I1uG4u4arPcqVOoGh8o+euONYkJwuruVw6tnZMfKpdVTNfl7A4suZblZgKjTbBImejdSvmnvVtxlmWiJtxPGEAMDwRZ2mMqw1miZFE+xv1EQSK7nFq28CNqy0ATdwjL0V8f6JoY0+O0KXmZ3JntC15YwWQbpe3GdvrUcD0zGe28= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=W5+00O2z; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="W5+00O2z" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 39DE4C62209; Thu, 15 Oct 2026 16:02:52 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id C107D6075C; Thu, 15 Oct 2026 16:01:55 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 89B8910328CEA; Thu, 15 Oct 2026 18:01:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1792080110; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=osC9h2DgP8+Sy60hIz0GAzP/N2fjsvvA92VkvYCVuW0=; b=W5+00O2zwe7FwCCYdl5Li9OgEJfPC42WUI6bmj9uXbEaaJR4Fk1JjiGW0Ik5VfuzRCECq9 6n0eF5ilPb+kGVFl8jS2TcMqgfKlcHTiChZ5csqdm8GHT9n6ohB93ckYLkW1+o5ssbpDKU Oddbfwk7Koz5b1qP5dGiPBAeIcnNK8jZzQJMY/R7WzukVWd0XmZUjaTDKAQSCL/OLwbtwo av7sowNKxzPTk+mUFUStvBti62LUk/+xhp1dUvcZxueCmhQ1HP6nVf3deg2HLZAUoNcRzf qPIvDUJUdD8DBiPsEo7LSjLK1lrL+ofcvyh8/eujUnX0wr3WLuEEI160Iht6Iw== From: Miquel Raynal Date: Thu, 15 Oct 2026 18:01:16 +0200 Subject: [PATCH v10 03/10] clk: nuvoton: ma35d1: Retrieve HXT/LXT from DT when possible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-perso-ma35d1-upstream-clk-v10-3-47c97b54a809@bootlin.com> References: <20261015-perso-ma35d1-upstream-clk-v10-0-47c97b54a809@bootlin.com> In-Reply-To: <20261015-perso-ma35d1-upstream-clk-v10-0-47c97b54a809@bootlin.com> To: Jacky Huang , Shan-Chun Hung , Michael Turquette , Stephen Boyd , Richard Cochran , Arnd Bergmann , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair Cc: Thomas Petazzoni , Steam Lin , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, Miquel Raynal , stable@vger.kernel.org X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 HXT and LXT are crystal oscillator inputs of the clock controller. As such, they are external clock sources which should not be registered by this driver. HXT is already described in the DT, but is not named. In order to point to this parent from its direct child which is HXT_GATE, we must provide a fw_name (when it is named, new DTs) and a .name (for when it's not named, but the fixed clock node name is used). LXT is missing in old DTs, so we must create that clock and register it for backward compatibility reasons. It should however be described and pointed at in updated DTs. Both HXT and LXT are exposed by this driver only in the backward compatibility case. Otherwise, both clocks are expected to be retrieved from the DT. Fixes: 691521a367cf ("clk: nuvoton: Add clock driver for ma35d1 clock contr= oller") Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal --- drivers/clk/nuvoton/clk-ma35d1.c | 44 +++++++++++++++++++++++++++++++++---= ---- 1 file changed, 37 insertions(+), 7 deletions(-) diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma3= 5d1.c index 00d635cdb604..33b397d7b7c5 100644 --- a/drivers/clk/nuvoton/clk-ma35d1.c +++ b/drivers/clk/nuvoton/clk-ma35d1.c @@ -65,6 +65,14 @@ static DEFINE_SPINLOCK(ma35d1_lock); =20 #define MA35D1_MUX_MAX_PARENTS 10 =20 +static const struct clk_parent_data hxtg_parent_data[] =3D { + { .fw_name =3D "hxt", .name =3D "clk_hxt" }, +}; + +static const struct clk_parent_data lxtg_parent_data[] =3D { + { .fw_name =3D "lxt", .name =3D "lxt" }, +}; + /* Mux parent selection, by index into the controller's clock table */ static const int ca35clk_parent_idx[] =3D { HXT, CAPLL, DDRPLL }; static const int sysclk0_parent_idx[] =3D { EPLL_DIV2, SYSPLL }; @@ -191,6 +199,15 @@ static struct clk_hw *ma35d1_clk_gate(struct device *d= ev, const char *name, cons reg, shift, 0, &ma35d1_lock); } =20 +static struct clk_hw *ma35d1_clk_gate_parent_data(struct device *dev, cons= t char *name, + const struct clk_parent_data *parent_data, + void __iomem *reg, u8 shift) +{ + return devm_clk_hw_register_gate_parent_data(dev, name, parent_data, + CLK_SET_RATE_PARENT, + reg, shift, 0, &ma35d1_lock); +} + static int ma35d1_get_pll_setting(struct device_node *clk_node, u32 *pllmo= de) { const char *of_str; @@ -219,7 +236,7 @@ static int ma35d1_clocks_probe(struct platform_device *= pdev) static struct clk_hw **hws; static struct clk_hw_onecell_data *ma35d1_hw_data; u32 pllmode[PLL_MAX_NUM]; - int ret; + int ret, num_clks; =20 ma35d1_hw_data =3D devm_kzalloc(dev, struct_size(ma35d1_hw_data, hws, MA35D1_CLK_COUNT), @@ -240,12 +257,25 @@ static int ma35d1_clocks_probe(struct platform_device= *pdev) return -EINVAL; } =20 - hws[HXT] =3D ma35d1_clk_fixed("hxt", 24000000); - hws[HXT_GATE] =3D ma35d1_clk_gate(dev, "hxt_gate", "hxt", - clk_base + REG_CLK_PWRCTL, 0); - hws[LXT] =3D ma35d1_clk_fixed("lxt", 32768); - hws[LXT_GATE] =3D ma35d1_clk_gate(dev, "lxt_gate", "lxt", - clk_base + REG_CLK_PWRCTL, 1); + num_clks =3D of_clk_get_parent_count(clk_node); + if (num_clks < 1 || num_clks > 2) + return -EINVAL; + + /* + * Old DTs do not describe the low-speed crystal. They may also expect + * an HXT output from this driver. In practice, nobody should use these + * clocks directly, but they must be kept for backward compatility + * purposes. + */ + if (num_clks =3D=3D 1) { + hws[HXT] =3D ma35d1_clk_fixed("hxt", 24000000); + hws[LXT] =3D ma35d1_clk_fixed("lxt", 32768); + } + + hws[HXT_GATE] =3D ma35d1_clk_gate_parent_data(dev, "hxt_gate", hxtg_paren= t_data, + clk_base + REG_CLK_PWRCTL, 0); + hws[LXT_GATE] =3D ma35d1_clk_gate_parent_data(dev, "lxt_gate", lxtg_paren= t_data, + clk_base + REG_CLK_PWRCTL, 1); hws[HIRC] =3D ma35d1_clk_fixed("hirc", 12000000); hws[HIRC_GATE] =3D ma35d1_clk_gate(dev, "hirc_gate", "hirc", clk_base + REG_CLK_PWRCTL, 2); --=20 2.55.0 From nobody Fri Oct 23 22:16:18 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5948C3845C1; Thu, 15 Oct 2026 16:02:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792080138; cv=none; b=QduoU30wycaOuwIhn4C1WVYPjPHIOD9G+oD+J+Dgjo3BQCzAKpl82FyiepXZ4ih9E9G8hZ03zPDQ9NEXOj9uMF4tYjzM+DZNNurLILUHnEwmjQx5v/BcksEDzQ4P3Md5jp+IrWV6DUfy1JKRjYwT4y9lbLFWGsXqv7cjmhuGyK8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792080138; c=relaxed/simple; bh=LzwB/qlJrcfsenqkOCJ7QiHgvKTGnJiw/+P+8Th9R6k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Cw4WxzWpnerYEvgZe7AKStSypCCYxJWKEpJ1RXENsi3BH860NQWOXhPBVUlYyLNBXlSbhss1eO920/sIHOyNNykz085Pam2WCWzH1pTUY7LQGzW9DLAmjMOq2EfwmLKAJNWBzNTGeQv6+62ICjdiwYgJqjl1ReEntjmtOWkeb4g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Zz3b8CKk; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Zz3b8CKk" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id B6FAF4E41256; Thu, 15 Oct 2026 16:02:03 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 834916075C; Thu, 15 Oct 2026 16:02:03 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 8695F10328BDA; Thu, 15 Oct 2026 18:01:54 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1792080117; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=J8vjuXvr8Q1wFLjWm2vkt6zJIeX/anM+9dkQv1ylWxs=; b=Zz3b8CKk/cYQKUwfe2JgccvZJ4Ja+XkHxIAXA/RvaQJ/WUAFLhkQIql5LCd1aiC4JG7Bvo X6bVvLFCin48Xfvjqym38lK229T/2A8nzrObwU7/gGhQs1VKMrrWXjFSDcDM2TZvs75GXe tmeetT0pvOXEIJstIl9zTuNTCqgR/Oxc88VXfmt8H2DoD1x2nhbcKZuX4uYJTrqxOTJYj5 GkORHEqxjOcNXWkxRw3FK9slu/AZ2oyxrcIBFKDO8aIdjZm6m+OegfUfeMQervcQHFftH/ 4P9jHRCoz2auy3qkdn9tvE9VOnukbvS0XHU512tSoIfijYguzLRjGEi7l7ZgpA== From: Miquel Raynal Date: Thu, 15 Oct 2026 18:01:17 +0200 Subject: [PATCH v10 04/10] clk: nuvoton: ma35d1: Reparent the gates correctly Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-perso-ma35d1-upstream-clk-v10-4-47c97b54a809@bootlin.com> References: <20261015-perso-ma35d1-upstream-clk-v10-0-47c97b54a809@bootlin.com> In-Reply-To: <20261015-perso-ma35d1-upstream-clk-v10-0-47c97b54a809@bootlin.com> To: Jacky Huang , Shan-Chun Hung , Michael Turquette , Stephen Boyd , Richard Cochran , Arnd Bergmann , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair Cc: Thomas Petazzoni , Steam Lin , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, Miquel Raynal , stable@vger.kernel.org X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The clock tree is still incorrect. There are four main clocks in this system: - HXT: external high-speed crystal oscillator - LXT: external low-speed crystal oscillator - HIRC: internal high-speed RC oscillator - LIRC: internal low-speed RC oscillator Each clock has a 'gate' control to disable it. While in the TRM the 'gate' appears aside, in the CCF topology, the gates should be below. This is because if we gate one of those clocks, none of the children clocks continue ticking. Reparent hxt_gate under hxt, and all hxt children under hxt_gate. Do the same for the three other clock sources listed above. After this change, the frequencies are identical, but the clock tree looks much closer to the reality. Fixes: 691521a367cf ("clk: nuvoton: Add clock driver for ma35d1 clock contr= oller") Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal --- drivers/clk/nuvoton/clk-ma35d1.c | 78 +++++++++++++++++++++++-------------= ---- 1 file changed, 45 insertions(+), 33 deletions(-) diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma3= 5d1.c index 33b397d7b7c5..65a2691002a7 100644 --- a/drivers/clk/nuvoton/clk-ma35d1.c +++ b/drivers/clk/nuvoton/clk-ma35d1.c @@ -74,34 +74,46 @@ static const struct clk_parent_data lxtg_parent_data[] = =3D { }; =20 /* Mux parent selection, by index into the controller's clock table */ -static const int ca35clk_parent_idx[] =3D { HXT, CAPLL, DDRPLL }; +static const int ca35clk_parent_idx[] =3D { HXT_GATE, CAPLL, DDRPLL }; static const int sysclk0_parent_idx[] =3D { EPLL_DIV2, SYSPLL }; -static const int sysclk1_parent_idx[] =3D { HXT, SYSPLL }; +static const int sysclk1_parent_idx[] =3D { HXT_GATE, SYSPLL }; static const int axiclk_parent_idx[] =3D { AXICLK_DIV2, AXICLK_DIV4 }; -static const int ccap_parent_idx[] =3D { HXT, VPLL, APLL, SYSPLL }; +static const int ccap_parent_idx[] =3D { HXT_GATE, VPLL, APLL, SYSPLL }; static const int sdh_parent_idx[] =3D { SYSPLL, APLL }; static const int dcu_parent_idx[] =3D { EPLL_DIV2, SYSPLL }; static const int gfx_parent_idx[] =3D { EPLL, SYSPLL }; -static const int dbg_parent_idx[] =3D { HIRC, SYSPLL }; -static const int timer0_parent_idx[] =3D { HXT, LXT, PCLK0, -1, -1, LIRC, = -1, HIRC }; -static const int timer1_parent_idx[] =3D { HXT, LXT, PCLK0, -1, -1, LIRC, = -1, HIRC }; -static const int timer2_parent_idx[] =3D { HXT, LXT, PCLK1, -1, -1, LIRC, = -1, HIRC }; -static const int timer3_parent_idx[] =3D { HXT, LXT, PCLK1, -1, -1, LIRC, = -1, HIRC }; -static const int timer4_parent_idx[] =3D { HXT, LXT, PCLK2, -1, -1, LIRC, = -1, HIRC }; -static const int timer5_parent_idx[] =3D { HXT, LXT, PCLK2, -1, -1, LIRC, = -1, HIRC }; -static const int timer6_parent_idx[] =3D { HXT, LXT, PCLK0, -1, -1, LIRC, = -1, HIRC }; -static const int timer7_parent_idx[] =3D { HXT, LXT, PCLK0, -1, -1, LIRC, = -1, HIRC }; -static const int timer8_parent_idx[] =3D { HXT, LXT, PCLK1, -1, -1, LIRC, = -1, HIRC }; -static const int timer9_parent_idx[] =3D { HXT, LXT, PCLK1, -1, -1, LIRC, = -1, HIRC }; -static const int timer10_parent_idx[] =3D { HXT, LXT, PCLK2, -1, -1, LIRC,= -1, HIRC }; -static const int timer11_parent_idx[] =3D { HXT, LXT, PCLK2, -1, -1, LIRC,= -1, HIRC }; -static const int uart_parent_idx[] =3D { HXT, SYSCLK1_DIV2 }; -static const int wdt0_parent_idx[] =3D { -1, LXT, PCLK3_DIV4096, LIRC }; -static const int wdt1_parent_idx[] =3D { -1, LXT, PCLK3_DIV4096, LIRC }; -static const int wdt2_parent_idx[] =3D { -1, LXT, PCLK4_DIV4096, LIRC }; -static const int wwdt0_parent_idx[] =3D { -1, -1, PCLK3_DIV4096, LIRC }; -static const int wwdt1_parent_idx[] =3D { -1, -1, PCLK3_DIV4096, LIRC }; -static const int wwdt2_parent_idx[] =3D { -1, -1, PCLK4_DIV4096, LIRC }; +static const int dbg_parent_idx[] =3D { HIRC_GATE, SYSPLL }; +static const int timer0_parent_idx[] =3D { HXT_GATE, LXT_GATE, PCLK0, -1, = -1, + LIRC_GATE, -1, HIRC_GATE }; +static const int timer1_parent_idx[] =3D { HXT_GATE, LXT_GATE, PCLK0, -1, = -1, + LIRC_GATE, -1, HIRC_GATE }; +static const int timer2_parent_idx[] =3D { HXT_GATE, LXT_GATE, PCLK1, -1, = -1, + LIRC_GATE, -1, HIRC_GATE }; +static const int timer3_parent_idx[] =3D { HXT_GATE, LXT_GATE, PCLK1, -1, = -1, + LIRC_GATE, -1, HIRC_GATE }; +static const int timer4_parent_idx[] =3D { HXT_GATE, LXT_GATE, PCLK2, -1, = -1, + LIRC_GATE, -1, HIRC_GATE }; +static const int timer5_parent_idx[] =3D { HXT_GATE, LXT_GATE, PCLK2, -1, = -1, + LIRC_GATE, -1, HIRC_GATE }; +static const int timer6_parent_idx[] =3D { HXT_GATE, LXT_GATE, PCLK0, -1, = -1, + LIRC_GATE, -1, HIRC_GATE }; +static const int timer7_parent_idx[] =3D { HXT_GATE, LXT_GATE, PCLK0, -1, = -1, + LIRC_GATE, -1, HIRC_GATE }; +static const int timer8_parent_idx[] =3D { HXT_GATE, LXT_GATE, PCLK1, -1, = -1, + LIRC_GATE, -1, HIRC_GATE }; +static const int timer9_parent_idx[] =3D { HXT_GATE, LXT_GATE, PCLK1, -1, = -1, + LIRC_GATE, -1, HIRC_GATE }; +static const int timer10_parent_idx[] =3D { HXT_GATE, LXT_GATE, PCLK2, -1,= -1, + LIRC_GATE, -1, HIRC_GATE }; +static const int timer11_parent_idx[] =3D { HXT_GATE, LXT_GATE, PCLK2, -1,= -1, + LIRC_GATE, -1, HIRC_GATE }; +static const int uart_parent_idx[] =3D { HXT_GATE, SYSCLK1_DIV2 }; +static const int wdt0_parent_idx[] =3D { -1, LXT_GATE, PCLK3_DIV4096, LIRC= _GATE }; +static const int wdt1_parent_idx[] =3D { -1, LXT_GATE, PCLK3_DIV4096, LIRC= _GATE }; +static const int wdt2_parent_idx[] =3D { -1, LXT_GATE, PCLK4_DIV4096, LIRC= _GATE }; +static const int wwdt0_parent_idx[] =3D { -1, -1, PCLK3_DIV4096, LIRC_GATE= }; +static const int wwdt1_parent_idx[] =3D { -1, -1, PCLK3_DIV4096, LIRC_GATE= }; +static const int wwdt2_parent_idx[] =3D { -1, -1, PCLK4_DIV4096, LIRC_GATE= }; static const int spi0_parent_idx[] =3D { PCLK1, APLL }; static const int spi1_parent_idx[] =3D { PCLK2, APLL }; static const int spi2_parent_idx[] =3D { PCLK1, APLL }; @@ -109,11 +121,11 @@ static const int spi3_parent_idx[] =3D { PCLK2, APLL = }; static const int qspi_parent_idx[] =3D { PCLK0, APLL }; static const int i2s_parent_idx[] =3D { APLL, SYSCLK1_DIV2 }; static const int can_parent_idx[] =3D { APLL, VPLL }; -static const int cko_parent_idx[] =3D { HXT, LXT, HIRC, LIRC, +static const int cko_parent_idx[] =3D { HXT_GATE, LXT_GATE, HIRC_GATE, LIR= C_GATE, AXICLK_DIV4, SYSPLL, DDRPLL, EPLL_DIV2, APLL, VPLL }; -static const int smc_parent_idx[] =3D { HXT, PCLK4 }; -static const int kpi_parent_idx[] =3D { HXT, LXT }; +static const int smc_parent_idx[] =3D { HXT_GATE, PCLK4 }; +static const int kpi_parent_idx[] =3D { HXT_GATE, LXT_GATE }; =20 static const struct clk_div_table ip_div_table[] =3D { {0, 2}, {1, 4}, {2, 6}, {3, 8}, {4, 10}, @@ -284,16 +296,16 @@ static int ma35d1_clocks_probe(struct platform_device= *pdev) clk_base + REG_CLK_PWRCTL, 3); =20 hws[CAPLL] =3D ma35d1_reg_clk_pll(dev, CAPLL, pllmode[0], "capll", - hws[HXT], clk_base + REG_CLK_PLL0CTL0); + hws[HXT_GATE], clk_base + REG_CLK_PLL0CTL0); hws[SYSPLL] =3D ma35d1_clk_fixed("syspll", 180000000); hws[DDRPLL] =3D ma35d1_reg_clk_pll(dev, DDRPLL, pllmode[1], "ddrpll", - hws[HXT], clk_base + REG_CLK_PLL2CTL0); + hws[HXT_GATE], clk_base + REG_CLK_PLL2CTL0); hws[APLL] =3D ma35d1_reg_clk_pll(dev, APLL, pllmode[2], "apll", - hws[HXT], clk_base + REG_CLK_PLL3CTL0); + hws[HXT_GATE], clk_base + REG_CLK_PLL3CTL0); hws[EPLL] =3D ma35d1_reg_clk_pll(dev, EPLL, pllmode[3], "epll", - hws[HXT], clk_base + REG_CLK_PLL4CTL0); + hws[HXT_GATE], clk_base + REG_CLK_PLL4CTL0); hws[VPLL] =3D ma35d1_reg_clk_pll(dev, VPLL, pllmode[4], "vpll", - hws[HXT], clk_base + REG_CLK_PLL5CTL0); + hws[HXT_GATE], clk_base + REG_CLK_PLL5CTL0); =20 hws[EPLL_DIV2] =3D ma35d1_clk_fixed_factor(dev, "epll_div2", "epll", 1, 2= ); hws[EPLL_DIV4] =3D ma35d1_clk_fixed_factor(dev, "epll_div4", "epll", 1, 4= ); @@ -461,7 +473,7 @@ static int ma35d1_clocks_probe(struct platform_device *= pdev) hws[CKO_GATE] =3D ma35d1_clk_gate(dev, "cko_gate", "cko_div", clk_base + REG_CLK_SYSCLK1, 13); =20 - hws[GTMR_GATE] =3D ma35d1_clk_gate(dev, "gtmr_gate", "hirc", + hws[GTMR_GATE] =3D ma35d1_clk_gate(dev, "gtmr_gate", "hirc_gate", clk_base + REG_CLK_SYSCLK1, 14); =20 hws[GPA_GATE] =3D ma35d1_clk_gate(dev, "gpa_gate", "hclk0", @@ -662,7 +674,7 @@ static int ma35d1_clocks_probe(struct platform_device *= pdev) hws[UART16_GATE] =3D ma35d1_clk_gate(dev, "uart16_gate", "uart16_div", clk_base + REG_CLK_APBCLK0, 28); =20 - hws[RTC_GATE] =3D ma35d1_clk_gate(dev, "rtc_gate", "lxt", + hws[RTC_GATE] =3D ma35d1_clk_gate(dev, "rtc_gate", "lxt_gate", clk_base + REG_CLK_APBCLK0, 29); hws[DDR_GATE] =3D ma35d1_clk_gate(dev, "ddr_gate", "ddrpll", clk_base + REG_CLK_APBCLK0, 30); --=20 2.55.0 From nobody Fri Oct 23 22:16:18 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 002C8559C8E for ; Thu, 15 Oct 2026 16:02:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="YbsK4dDk" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 535824E41249; Thu, 15 Oct 2026 16:02:11 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 11E366075C; Thu, 15 Oct 2026 16:02:11 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 3887410328C76; Thu, 15 Oct 2026 18:02:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1792080125; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=6BO4/TMDN+AnX7zo6BpkAHZoFqQTddTDZMpqSSN1Y88=; b=YbsK4dDkdw8cpJW1uT51lUNexQ/MUagKsifJKYr/Twca5is8nt395izZ79rVefGvY9wT8P B66zV9haE1mrzIcJHRgJF0ZQndGIE4da+tSSgqRuBQBtYiyJDvIeOBnHYq7TEuYsef9nNs SSvbK20HOtepxw3shYudVlXfFEmtZ2YBoI+AqLYiyQ3hqSTHUukmY1K+um5C1c1mehp71g JF1LGkqmKgIori5mBbyX78deBkBJvISkNkK8gkw8LXeNMr+3jrpczOe0KNCEgm5H4KmzQ9 yBj9zXHV04QORf3Dk9yyj5gAlb60jo1qYoLlD9snjWSbq/RVMM7pX5OFxw7CmQ== From: Miquel Raynal Date: Thu, 15 Oct 2026 18:01:18 +0200 Subject: [PATCH v10 05/10] clk: nuvoton: ma35d1: Use device managed helpers for fixed rate clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-perso-ma35d1-upstream-clk-v10-5-47c97b54a809@bootlin.com> References: <20261015-perso-ma35d1-upstream-clk-v10-0-47c97b54a809@bootlin.com> In-Reply-To: <20261015-perso-ma35d1-upstream-clk-v10-0-47c97b54a809@bootlin.com> To: Jacky Huang , Shan-Chun Hung , Michael Turquette , Stephen Boyd , Richard Cochran , Arnd Bergmann , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair Cc: Thomas Petazzoni , Steam Lin , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Most of the clocks are already registered with device managed helpers, except the fixed clocks. Harmonize the driver by using the already available managed helper for that. Signed-off-by: Miquel Raynal --- drivers/clk/nuvoton/clk-ma35d1.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma3= 5d1.c index 65a2691002a7..8fab3c563316 100644 --- a/drivers/clk/nuvoton/clk-ma35d1.c +++ b/drivers/clk/nuvoton/clk-ma35d1.c @@ -139,9 +139,9 @@ static const struct clk_div_table eadc_div_table[] =3D { {13, 28}, {14, 30}, {15, 32}, {0, 0}, }; =20 -static struct clk_hw *ma35d1_clk_fixed(const char *name, int rate) +static struct clk_hw *ma35d1_clk_fixed(struct device *dev, const char *nam= e, int rate) { - return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); + return devm_clk_hw_register_fixed_rate(dev, name, NULL, 0, rate); } =20 static struct clk_hw *ma35d1_clk_mux(struct device *dev, const char *name, @@ -280,24 +280,24 @@ static int ma35d1_clocks_probe(struct platform_device= *pdev) * purposes. */ if (num_clks =3D=3D 1) { - hws[HXT] =3D ma35d1_clk_fixed("hxt", 24000000); - hws[LXT] =3D ma35d1_clk_fixed("lxt", 32768); + hws[HXT] =3D ma35d1_clk_fixed(dev, "hxt", 24000000); + hws[LXT] =3D ma35d1_clk_fixed(dev, "lxt", 32768); } =20 hws[HXT_GATE] =3D ma35d1_clk_gate_parent_data(dev, "hxt_gate", hxtg_paren= t_data, clk_base + REG_CLK_PWRCTL, 0); hws[LXT_GATE] =3D ma35d1_clk_gate_parent_data(dev, "lxt_gate", lxtg_paren= t_data, clk_base + REG_CLK_PWRCTL, 1); - hws[HIRC] =3D ma35d1_clk_fixed("hirc", 12000000); + hws[HIRC] =3D ma35d1_clk_fixed(dev, "hirc", 12000000); hws[HIRC_GATE] =3D ma35d1_clk_gate(dev, "hirc_gate", "hirc", clk_base + REG_CLK_PWRCTL, 2); - hws[LIRC] =3D ma35d1_clk_fixed("lirc", 32000); + hws[LIRC] =3D ma35d1_clk_fixed(dev, "lirc", 32000); hws[LIRC_GATE] =3D ma35d1_clk_gate(dev, "lirc_gate", "lirc", clk_base + REG_CLK_PWRCTL, 3); =20 hws[CAPLL] =3D ma35d1_reg_clk_pll(dev, CAPLL, pllmode[0], "capll", hws[HXT_GATE], clk_base + REG_CLK_PLL0CTL0); - hws[SYSPLL] =3D ma35d1_clk_fixed("syspll", 180000000); + hws[SYSPLL] =3D ma35d1_clk_fixed(dev, "syspll", 180000000); hws[DDRPLL] =3D ma35d1_reg_clk_pll(dev, DDRPLL, pllmode[1], "ddrpll", hws[HXT_GATE], clk_base + REG_CLK_PLL2CTL0); hws[APLL] =3D ma35d1_reg_clk_pll(dev, APLL, pllmode[2], "apll", @@ -338,8 +338,8 @@ static int ma35d1_clocks_probe(struct platform_device *= pdev) hws[PCLK3_DIV4096] =3D ma35d1_clk_fixed_factor(dev, "pclk3_div4096", "pcl= k3", 1, 4096); hws[PCLK4_DIV4096] =3D ma35d1_clk_fixed_factor(dev, "pclk4_div4096", "pcl= k4", 1, 4096); =20 - hws[USBPHY0] =3D ma35d1_clk_fixed("usbphy0", 480000000); - hws[USBPHY1] =3D ma35d1_clk_fixed("usbphy1", 480000000); + hws[USBPHY0] =3D ma35d1_clk_fixed(dev, "usbphy0", 480000000); + hws[USBPHY1] =3D ma35d1_clk_fixed(dev, "usbphy1", 480000000); =20 /* DDR */ hws[DDR0_GATE] =3D ma35d1_clk_gate(dev, "ddr0_gate", "ddrpll", --=20 2.55.0 From nobody Fri Oct 23 22:16:18 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CA9B556BB0; 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arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="o7TXHpLL" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 9A95A1A1244; Thu, 15 Oct 2026 16:02:18 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 6DA386075C; Thu, 15 Oct 2026 16:02:18 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 8C1F410328D09; Thu, 15 Oct 2026 18:02:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1792080132; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=CMFy2QOZK7zANSOk5PDCpb3dFWclqXWbQfTgV5KP3e4=; b=o7TXHpLLorhxrFanhAhVhqads2VpvOYzZruhknmQ/+eTmcIRa8mxXI5ppl/RNrNwdl6v90 oOVc/tp9Vq1z+AkWvtgzmCIsLDNQEhPyCo7EIHXY+4iB+7WAjq0rAOeD4dntpQd8cQQZul a4a/ENSgDcAsi7vVHIy6hzUyV95vc7u6YetG05HA5ZODWVam/cCBKqO+9ZZuqhUu982vFi k8fZvnq12LBv6hZPoGLgXycm/nOHwMrqq/eGhnG25TWc8fYQwqQeQED79RJjt8Us1/6oMc qPVCSy/pthXbxlQ0Y+XE3R8sRlfntiOQqUWFY8t3gwmZ3eh7m6QNM0D0O1W+aA== From: Miquel Raynal Date: Thu, 15 Oct 2026 18:01:19 +0200 Subject: [PATCH v10 06/10] clk: Create devm_clk_hw_register_fixed_rate_parent_hw() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-perso-ma35d1-upstream-clk-v10-6-47c97b54a809@bootlin.com> References: <20261015-perso-ma35d1-upstream-clk-v10-0-47c97b54a809@bootlin.com> In-Reply-To: <20261015-perso-ma35d1-upstream-clk-v10-0-47c97b54a809@bootlin.com> To: Jacky Huang , Shan-Chun Hung , Michael Turquette , Stephen Boyd , Richard Cochran , Arnd Bergmann , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair Cc: Thomas Petazzoni , Steam Lin , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 clk-provider.h exposes many different helpers to help registering clocks. Most of them expose both a 'basic' variant and their 'devm_' extension (with just the last parameter of the inner function call becoming true instead of false). Do the same with: clk_hw_register_fixed_rate_parent_hw() by creating devm_clk_hw_register_fixed_rate_parent_hw(). Signed-off-by: Miquel Raynal Reviewed-by: Jerome Brunet --- include/linux/clk-provider.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index a355d1ee5189..c2b80cb3ab0b 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -458,6 +458,19 @@ struct clk *clk_register_fixed_rate(struct device *dev= , const char *name, fixed_rate) \ __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \ NULL, (flags), (fixed_rate), 0, 0, false) +/** + * devm_clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock w= ith + * the clock framework + * @dev: device that is registering this clock + * @name: name of this clock + * @parent_hw: pointer to parent clk + * @flags: framework-specific flags + * @fixed_rate: non-adjustable clock rate + */ +#define devm_clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, fl= ags, \ + fixed_rate) \ + __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \ + NULL, (flags), (fixed_rate), 0, 0, true) /** * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with * the clock framework --=20 2.55.0 From nobody Fri Oct 23 22:16:18 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B9AF55C31B; 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arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="rGmCtVyl" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 1B29D4E4124F; Thu, 15 Oct 2026 16:02:26 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id E1DD26075C; Thu, 15 Oct 2026 16:02:25 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 0481010328CF4; Thu, 15 Oct 2026 18:02:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1792080140; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=4axd8RvbmAiH7g9oCEuJCNbjk0G7L7I4ZKsUL9l2L0c=; b=rGmCtVylxsZOartwAYi8B7J9JTXEaFc6Vun5fCMwmF0lKMLAkkMETHFhNtgPMHftIbj3ag Ph7rzgNksTo3qTmheOfdlwceZICGaOeH1/yjhcAfUF3iX/HO13pKYtYKOPbd7Ej2cR60Es atpjO4t//znD0CB4DnBlMLg+utmVkZkcDFA2VWNOQdlvvjZYyzkUKDlHY/htCzxBLvoWaU OSx+gqAh5Ukz/gem4u9fVWvbCc+QP9j8abR/LmTp3Su/hE83VneI4D0lMc0L70g+HkJ2sF kx3muAUf6F5Dg1xBwaEU3tcDKFG0gkzED2FG2D44VgnDkxvXwy8eIXHjUYkMKw== From: Miquel Raynal Date: Thu, 15 Oct 2026 18:01:20 +0200 Subject: [PATCH v10 07/10] clk: nuvoton: ma35d1: Reparent SYSPLL correctly Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-perso-ma35d1-upstream-clk-v10-7-47c97b54a809@bootlin.com> References: <20261015-perso-ma35d1-upstream-clk-v10-0-47c97b54a809@bootlin.com> In-Reply-To: <20261015-perso-ma35d1-upstream-clk-v10-0-47c97b54a809@bootlin.com> To: Jacky Huang , Shan-Chun Hung , Michael Turquette , Stephen Boyd , Richard Cochran , Arnd Bergmann , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair Cc: Thomas Petazzoni , Steam Lin , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, Miquel Raynal , stable@vger.kernel.org X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The clock tree is still incorrect. SYSPLL is derived from HXT_GATE, very much like CAPLL, DDRPLL, VPLL, APLL and EPLL. SYSPLL has a fixed frequency, but if HXT gets gated, SYSPLL stops running. Reparent SYSPLL under HXT_GATE to properly define the clock tree topology. After this change, the frequencies are identical, but the clock tree looks (again) much closer to the reality. Since the TRM does not explicitly shows that HIRC and LIRC are internally sourced from HXT and LXT, respectively, I haven't reparented them (even though that was tempting). This can be done later anyway. Fixes: 691521a367cf ("clk: nuvoton: Add clock driver for ma35d1 clock contr= oller") Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal --- drivers/clk/nuvoton/clk-ma35d1.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma3= 5d1.c index 8fab3c563316..3015c49ee852 100644 --- a/drivers/clk/nuvoton/clk-ma35d1.c +++ b/drivers/clk/nuvoton/clk-ma35d1.c @@ -139,6 +139,12 @@ static const struct clk_div_table eadc_div_table[] =3D= { {13, 28}, {14, 30}, {15, 32}, {0, 0}, }; =20 +static struct clk_hw *ma35d1_clk_fixed_parent_hw(struct device *dev, const= char *name, int rate, + const struct clk_hw *parent_hw) +{ + return devm_clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, 0,= rate); +} + static struct clk_hw *ma35d1_clk_fixed(struct device *dev, const char *nam= e, int rate) { return devm_clk_hw_register_fixed_rate(dev, name, NULL, 0, rate); @@ -286,6 +292,9 @@ static int ma35d1_clocks_probe(struct platform_device *= pdev) =20 hws[HXT_GATE] =3D ma35d1_clk_gate_parent_data(dev, "hxt_gate", hxtg_paren= t_data, clk_base + REG_CLK_PWRCTL, 0); + if (IS_ERR(hws[HXT_GATE])) + return PTR_ERR(hws[HXT_GATE]); + hws[LXT_GATE] =3D ma35d1_clk_gate_parent_data(dev, "lxt_gate", lxtg_paren= t_data, clk_base + REG_CLK_PWRCTL, 1); hws[HIRC] =3D ma35d1_clk_fixed(dev, "hirc", 12000000); @@ -297,7 +306,7 @@ static int ma35d1_clocks_probe(struct platform_device *= pdev) =20 hws[CAPLL] =3D ma35d1_reg_clk_pll(dev, CAPLL, pllmode[0], "capll", hws[HXT_GATE], clk_base + REG_CLK_PLL0CTL0); - hws[SYSPLL] =3D ma35d1_clk_fixed(dev, "syspll", 180000000); + hws[SYSPLL] =3D ma35d1_clk_fixed_parent_hw(dev, "syspll", 180000000, hws[= HXT_GATE]); hws[DDRPLL] =3D ma35d1_reg_clk_pll(dev, DDRPLL, pllmode[1], "ddrpll", hws[HXT_GATE], clk_base + REG_CLK_PLL2CTL0); hws[APLL] =3D ma35d1_reg_clk_pll(dev, APLL, pllmode[2], "apll", --=20 2.55.0 From nobody Fri Oct 23 22:16:18 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE813560AA7 for ; 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bh=oUZJWgh1jtbi+p1yrcW64LX48+HiL8UrWIoerSJqBPI=; b=KFhvYlcJ9F22guPUjZxJPxJYLAH9q4fjgmaXZ+8gV7KT68G1HOHtoBIeUiFh+ixPw3Roo5 oFbNqrPTplqQq6xi8B/x2Urk3sfAVW982EqN0D6CY2+6iJ0baGIkhkKLbKLFofTbUuN2Uc Se1egGcwX1g2Tg9KvjMZs8klYroS2EpC1wlTJDQKbnHJYPHPsYteX25gKW4cNApXIg3zhQ H6iUIhiB3QkPHRwmJloogKIgpz4v1R/dbfE0nLObxtAgmBE3WzC3BdS+kIyaV8qe3lcABn giZHno8HDLemMMbzlZ/+Fb9cSVSYTWEbjcTPYoTL6iYRoTp6qDDzPQ7w5Gk4GA== From: Miquel Raynal Date: Thu, 15 Oct 2026 18:01:21 +0200 Subject: [PATCH v10 08/10] MAINTAINERS: Add myself as Nuvoton MA35D1 clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-perso-ma35d1-upstream-clk-v10-8-47c97b54a809@bootlin.com> References: <20261015-perso-ma35d1-upstream-clk-v10-0-47c97b54a809@bootlin.com> In-Reply-To: <20261015-perso-ma35d1-upstream-clk-v10-0-47c97b54a809@bootlin.com> To: Jacky Huang , Shan-Chun Hung , Michael Turquette , Stephen Boyd , Richard Cochran , Arnd Bergmann , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair Cc: Thomas Petazzoni , Steam Lin , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 I have the platform, I currently use it for my developpements and therefore I care about the clock controller driver and the SPI controller driver not being constantly broken. I would like to step up to help the Nuvoton team (not visible in the diff since they created an MA35D1 catch-all entry) in the maintaince of this driver. Signed-off-by: Miquel Raynal --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 6977bc6245b0..c9f482b5edd8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19541,6 +19541,14 @@ F: drivers/nubus/ F: include/linux/nubus.h F: include/uapi/linux/nubus.h =20 +NUVOTON MA35D1 CLOCK CONTROLLER DRIVER +M: Miquel Raynal +L: linux-clk@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml +F: drivers/clk/nuvoton/clk-ma35d1* +F: include/dt-bindings/clock/nuvoton,ma35d1-clk.h + NUVOTON NCT6694 MFD DRIVER M: Ming Yu S: Supported --=20 2.55.0 From nobody Fri Oct 23 22:16:18 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C9D75625E3 for ; Thu, 15 Oct 2026 16:02:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792080177; cv=none; b=QNhxJ0vGZ7xMscOIxUmSkD7Tc/HQwjoLJNFFDLNtEazpUuj/KVc+DZF5VRL1jC6vVrqpsdeQsN2OuIndDcWVymOKt5Ux4Auk90nZodlV1gl2i36CvT/xL/wV9gDvr72PHWQPiCuUOGklWvisl837HbXrwE58w5aGnp36OlQfpd0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792080177; c=relaxed/simple; bh=mUHMTVPD8VErgL9cNoJhVICpP2cuq1gdAZMTARUlWbY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cqJzDndFr5e8K2g7kdQKIjT/G8xBTtS2kHPmm5e/tjHI8vwruyVXa7sjokzoB6QQlvz99zn9lNWQmvlKLGg3qNTpL9AQeqy4K9GqognxrLF/zZNGhCwZWuzZZR89s+Gq847j6vFUgiMLT6WPsbJixRAzRcuyLanvGn9WDE8jwjQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=WX+PHVm+; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="WX+PHVm+" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id B5B824E4124F; Thu, 15 Oct 2026 16:02:41 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 890F36075C; Thu, 15 Oct 2026 16:02:41 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 703BB10328B42; Thu, 15 Oct 2026 18:02:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1792080155; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=dkEV3NU/xjxq6SJuLLAVWiQsTCv0N4E8zuSVpty49hU=; b=WX+PHVm+NUlQ1Ip641v/NskvAApUPXyftYa6uAZQMl+jqNOTkVd7dCLcuzpVkToOZnzBqK sEf8H5j9hJP1hu6AczeZxd6k+H4Y2LP2+zsGPyMK9OgK1zX/OVQPVW049W+jD09pL/zCzT vON8v+O1zGNKMeJqlSjtJluCO0vZ4XcNXtqwn+XePIictvYDgU9I3QvCb3yP9x37i2p6+r Ugz0YG0PPI7Ga39jBHMna5ydbCp3pRnxRo3z3GK6nSkktIbHbhXoylYnNpmgOTnC05cm1w WTryKVX7rKpyrDoUc0VU9XQ6zILZ311BH7TkdBS4oULZk2KQ6XR3+GkWokhyvg== From: Miquel Raynal Date: Thu, 15 Oct 2026 18:01:22 +0200 Subject: [PATCH v10 09/10] arm64: dts: nuvoton: ma35d1: Drop HXT clock output name Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-perso-ma35d1-upstream-clk-v10-9-47c97b54a809@bootlin.com> References: <20261015-perso-ma35d1-upstream-clk-v10-0-47c97b54a809@bootlin.com> In-Reply-To: <20261015-perso-ma35d1-upstream-clk-v10-0-47c97b54a809@bootlin.com> To: Jacky Huang , Shan-Chun Hung , Michael Turquette , Stephen Boyd , Richard Cochran , Arnd Bergmann , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair Cc: Thomas Petazzoni , Steam Lin , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The clock-output-names property is not useful since there is only one output clock, and the naming of that clock would already be clock-hxt after the node name if we were not providing that property (so very similar). Just drop it. I want to clean this name before introducing another very similar fixed clock in the DT: LXT Another solution could have been to rename it "hxt", which would have been more aligned with the other clock names. Sashiko complained that this could break DT compatibility with an -EEXIST error because of the colliding names. Signed-off-by: Miquel Raynal --- arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts | 1 - arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts b/arch/arm64/b= oot/dts/nuvoton/ma35d1-iot-512m.dts index 78534d613486..d7670afb0a63 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts @@ -35,7 +35,6 @@ clk_hxt: clock-hxt { compatible =3D "fixed-clock"; #clock-cells =3D <0>; clock-frequency =3D <24000000>; - clock-output-names =3D "clk_hxt"; }; }; =20 diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/b= oot/dts/nuvoton/ma35d1-som-256m.dts index a029b660e8dc..8f3cb18d39b6 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts @@ -35,7 +35,6 @@ clk_hxt: clock-hxt { compatible =3D "fixed-clock"; #clock-cells =3D <0>; clock-frequency =3D <24000000>; - clock-output-names =3D "clk_hxt"; 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Thu, 15 Oct 2026 18:02:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1792080163; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=AbpkMZVsBdBOWRwxjTkLihKxr/UR5S6eo3rRMVyn4ks=; b=oS25sV93XSD557wIB4lBXK1AG3ECjXQ3/Xlt8i7iz5CqRstbNl9cYZbGW70uIC1wRn5iNg ExzMWfb8ZDgKP7VxkURJiqTz4/JC91q9DmmWR2rdv7Hml3dQ9b8NKfvLAvZEMCBE6dFCBd MjlEZIyMoearzV0TbcgmMTd6JWLu+HpzAOjM8wrqNUEmCaB5LuWctAB84QR8v77Fw2n1dA Hc42OYjblLicTn3fhzlEAuAB1WbhnHsACYUtXAsPpBIg4lss4dthUKiIGCGP5+Iw1mcQaZ xizj3KcIO3aEn9DMnW2WfwJR3kSm18N0uw10Q1vIsTZc302ETniRGUF2mLn68g== From: Miquel Raynal Date: Thu, 15 Oct 2026 18:01:23 +0200 Subject: [PATCH v10 10/10] arm64: dts: nuvoton: ma35d1: Add LXT crystal and clock-names Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-perso-ma35d1-upstream-clk-v10-10-47c97b54a809@bootlin.com> References: <20261015-perso-ma35d1-upstream-clk-v10-0-47c97b54a809@bootlin.com> In-Reply-To: <20261015-perso-ma35d1-upstream-clk-v10-0-47c97b54a809@bootlin.com> To: Jacky Huang , Shan-Chun Hung , Michael Turquette , Stephen Boyd , Richard Cochran , Arnd Bergmann , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair Cc: Thomas Petazzoni , Steam Lin , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, Miquel Raynal , stable@vger.kernel.org X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The clock controller takes its two crystal oscillator inputs from the board: HXT and LXT. The LXT crystal is not described at all: add the fixed clock node for it and reference both inputs from the clock controller node, with their respective clock-names. Fixes: 691521a367cf ("clk: nuvoton: Add clock driver for ma35d1 clock contr= oller") Fixes: b69af0984732 ("arm64: dts: nuvoton: Add initial ma35d1 device tree") Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal --- --- arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts | 6 ++++++ arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts | 6 ++++++ arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 3 ++- 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts b/arch/arm64/b= oot/dts/nuvoton/ma35d1-iot-512m.dts index d7670afb0a63..7752e85734ac 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts @@ -36,6 +36,12 @@ clk_hxt: clock-hxt { #clock-cells =3D <0>; clock-frequency =3D <24000000>; }; + + clk_lxt: clock-lxt { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + }; }; =20 &clk { diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/b= oot/dts/nuvoton/ma35d1-som-256m.dts index 8f3cb18d39b6..5c65f1fe5da9 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts @@ -36,6 +36,12 @@ clk_hxt: clock-hxt { #clock-cells =3D <0>; clock-frequency =3D <24000000>; }; + + clk_lxt: clock-lxt { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + }; }; =20 &clk { diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/= nuvoton/ma35d1.dtsi index 7228ad4735b5..9a341c2b1397 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi +++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi @@ -92,7 +92,8 @@ clk: clock-controller@40460200 { compatible =3D "nuvoton,ma35d1-clk"; reg =3D <0x00000000 0x40460200 0x0 0x100>; #clock-cells =3D <1>; - clocks =3D <&clk_hxt>; + clocks =3D <&clk_hxt>, <&clk_lxt>; + clock-names =3D "hxt", "lxt"; }; =20 pinctrl: pinctrl@40040000 { --=20 2.55.0