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Thu, 15 Oct 2026 09:54:44 -0700 (PDT) From: Ettore Chimenti Date: Thu, 15 Oct 2026 18:54:30 +0200 Subject: [PATCH 1/4] clk: ti: fapll: remove ti_dt_clk_name helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-patch-ektor5-dm8168-clk-v1-1-8b99c5cd5541@linaro.org> References: <20261015-patch-ektor5-dm8168-clk-v1-0-8b99c5cd5541@linaro.org> In-Reply-To: <20261015-patch-ektor5-dm8168-clk-v1-0-8b99c5cd5541@linaro.org> To: Tero Kristo , Stephen Boyd , Brian Masney , Jerome Brunet , Tony Lindgren , Andrew Goodbody , Rouven Czerwinski Cc: linux-omap@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Ettore Chimenti X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792083282; l=2116; i=ettore.chimenti@linaro.org; s=20261014; h=from:subject:message-id; bh=V1lJHYLAgA/nBlfBnu6hravYqMFQUVNrtE+t8AZRuXU=; b=Wl37l+fJKC0jK9zAPXXOWj2SG/X4dwbai04ly9CrEmdpnrWfIfzXaNzQvDyoVeVdDFxEhCdIx raOlehQINIZAcIxEa5JqQf3TA0zCfLC8m3u9b76SzZaqMAJeDGcprvJ X-Developer-Key: i=ettore.chimenti@linaro.org; a=ed25519; pk=wCaUblFVaqhuBTQt/hAtysafsAaEsqj/yOD9SPlz6NM= From: Rouven Czerwinski The fapll driver uses multiple `clock-output-names`, so we cannot use the DT helper in this driver because that would assign the first clock output name as the parent name. This change do not affect other SoCs as the only consumer is DM816x. Fixes: 9e56a7d4263c ("clk: ti: Update pll and clockdomain clocks to use ti_= dt_clk_name()") Signed-off-by: Rouven Czerwinski Tested-by: Andrew Goodbody Signed-off-by: Ettore Chimenti --- drivers/clk/ti/fapll.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c index e54b1df3436e..ae2f6fed10f6 100644 --- a/drivers/clk/ti/fapll.c +++ b/drivers/clk/ti/fapll.c @@ -10,8 +10,6 @@ #include #include =20 -#include "clock.h" - /* FAPLL Control Register PLL_CTRL */ #define FAPLL_MAIN_MULT_N_SHIFT 16 #define FAPLL_MAIN_DIV_P_SHIFT 8 @@ -541,7 +539,6 @@ static void __init ti_fapll_setup(struct device_node *n= ode) struct clk_init_data *init =3D NULL; const char *parent_name[2]; struct clk *pll_clk; - const char *name; int i; =20 fd =3D kzalloc_obj(*fd); @@ -559,8 +556,7 @@ static void __init ti_fapll_setup(struct device_node *n= ode) goto free; =20 init->ops =3D &ti_fapll_ops; - name =3D ti_dt_clk_name(node); - init->name =3D name; + init->name =3D node->name; =20 init->num_parents =3D of_clk_get_parent_count(node); if (init->num_parents !=3D 2) { @@ -592,7 +588,7 @@ static void __init ti_fapll_setup(struct device_node *n= ode) if (fapll_is_ddr_pll(fd->base)) fd->bypass_bit_inverted =3D true; =20 - fd->name =3D name; + fd->name =3D node->name; fd->hw.init =3D init; =20 /* Register the parent PLL */ @@ -639,7 +635,7 @@ static void __init ti_fapll_setup(struct device_node *n= ode) freq =3D NULL; } synth_clk =3D ti_fapll_synth_setup(fd, freq, div, output_instance, - output_name, name, pll_clk); + output_name, node->name, pll_clk); if (IS_ERR(synth_clk)) continue; =20 --=20 2.56.0 From nobody Fri Oct 23 22:16:17 2026 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2474C3EC804 for ; Thu, 15 Oct 2026 16:54:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 15 Oct 2026 09:54:46 -0700 (PDT) Received: from z13-ek5.local ([151.41.28.233]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48de0aaa5dbsm20775664f8f.12.2026.10.15.09.54.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 09:54:45 -0700 (PDT) From: Ettore Chimenti Date: Thu, 15 Oct 2026 18:54:31 +0200 Subject: [PATCH 2/4] clk: ti: fapll: Fix clock speed calculation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-patch-ektor5-dm8168-clk-v1-2-8b99c5cd5541@linaro.org> References: <20261015-patch-ektor5-dm8168-clk-v1-0-8b99c5cd5541@linaro.org> In-Reply-To: <20261015-patch-ektor5-dm8168-clk-v1-0-8b99c5cd5541@linaro.org> To: Tero Kristo , Stephen Boyd , Brian Masney , Jerome Brunet , Tony Lindgren , Andrew Goodbody , Rouven Czerwinski Cc: linux-omap@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Ettore Chimenti X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792083282; l=1034; i=ettore.chimenti@linaro.org; s=20261014; h=from:subject:message-id; bh=fBTD64HW6udC2yGl6I8fIRV564MzcGzaqjs261VGICI=; b=l/dbkURMpePhSEWvypYoRZlI9vzGFMFaCM9Q6CaCjA3UFI0DhdX13It/6H6eJCJkN+nzCGSf8 FeOm2+7dNnCBmuBuRH4svkON+awYpeVhjA/7zgOJR2knKKfpPEU776N X-Developer-Key: i=ettore.chimenti@linaro.org; a=ed25519; pk=wCaUblFVaqhuBTQt/hAtysafsAaEsqj/yOD9SPlz6NM= From: Andrew Goodbody The fractional part of the divider was being treated as 1/10000000 wheras it is in fact 1/16777215. This led to incorrect clock speeds being reported when a fractional divider was in use. Correct it. Signed-off-by: Andrew Goodbody Signed-off-by: Ettore Chimenti --- drivers/clk/ti/fapll.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c index ae2f6fed10f6..008a61f45ac1 100644 --- a/drivers/clk/ti/fapll.c +++ b/drivers/clk/ti/fapll.c @@ -336,8 +336,8 @@ static unsigned long ti_fapll_synth_recalc_rate(struct = clk_hw *hw, v =3D readl_relaxed(synth->freq); synth_int_div =3D (v >> 24) & 0xf; synth_frac_div =3D v & 0xffffff; - synth_div_freq =3D (synth_int_div * 10000000) + synth_frac_div; - rate *=3D 10000000; + synth_div_freq =3D (synth_int_div * 16777215) + synth_frac_div; + rate *=3D 16777215; do_div(rate, synth_div_freq); rate *=3D SYNTH_PHASE_K; } --=20 2.56.0 From nobody Fri Oct 23 22:16:17 2026 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73158312836 for ; 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Thu, 15 Oct 2026 09:54:48 -0700 (PDT) Received: from z13-ek5.local ([151.41.28.233]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48de0aaa5dbsm20775664f8f.12.2026.10.15.09.54.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 09:54:46 -0700 (PDT) From: Ettore Chimenti Date: Thu, 15 Oct 2026 18:54:32 +0200 Subject: [PATCH 3/4] clk: ti: fapll: print clock name that fails to register Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-patch-ektor5-dm8168-clk-v1-3-8b99c5cd5541@linaro.org> References: <20261015-patch-ektor5-dm8168-clk-v1-0-8b99c5cd5541@linaro.org> In-Reply-To: <20261015-patch-ektor5-dm8168-clk-v1-0-8b99c5cd5541@linaro.org> To: Tero Kristo , Stephen Boyd , Brian Masney , Jerome Brunet , Tony Lindgren , Andrew Goodbody , Rouven Czerwinski Cc: linux-omap@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Ettore Chimenti X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792083282; l=826; i=ettore.chimenti@linaro.org; s=20261014; h=from:subject:message-id; bh=Ja3D73iaM0XrrX8Ixe84Fx5s+9skcP8lleOkVCdvv/o=; b=Xci4KTRtILDfRu0hmxsWfO/nunPhLFDznA3uG4T4fWqGPu7dmThhKO+TibQMZrU4q6OC+sp76 Px5shKBBIpwAhCyVsbdCgTE7utS17Y1mwhPyqi5yN6CFe3LgHYp2L1c X-Developer-Key: i=ettore.chimenti@linaro.org; a=ed25519; pk=wCaUblFVaqhuBTQt/hAtysafsAaEsqj/yOD9SPlz6NM= From: Rouven Czerwinski Improve the error message when a clock fails to register by including the clock's name and its parent's name for better debugging. Signed-off-by: Rouven Czerwinski Signed-off-by: Ettore Chimenti --- drivers/clk/ti/fapll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c index 008a61f45ac1..5aab90cf5438 100644 --- a/drivers/clk/ti/fapll.c +++ b/drivers/clk/ti/fapll.c @@ -520,7 +520,7 @@ static struct clk * __init ti_fapll_synth_setup(struct = fapll_data *fd, =20 clk =3D clk_register(NULL, &synth->hw); if (IS_ERR(clk)) { - pr_err("failed to register clock\n"); + pr_err("failed to register clock '%s' for parent '%s'\n", name, parent); goto free; } =20 --=20 2.56.0 From nobody Fri Oct 23 22:16:17 2026 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A35145505FA for ; Thu, 15 Oct 2026 16:54:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; 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Thu, 15 Oct 2026 09:54:49 -0700 (PDT) Received: from z13-ek5.local ([151.41.28.233]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48de0aaa5dbsm20775664f8f.12.2026.10.15.09.54.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 09:54:49 -0700 (PDT) From: Ettore Chimenti Date: Thu, 15 Oct 2026 18:54:33 +0200 Subject: [PATCH 4/4] clk-816x: add sys_ck clock as sys_clkin_ck alias Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-patch-ektor5-dm8168-clk-v1-4-8b99c5cd5541@linaro.org> References: <20261015-patch-ektor5-dm8168-clk-v1-0-8b99c5cd5541@linaro.org> In-Reply-To: <20261015-patch-ektor5-dm8168-clk-v1-0-8b99c5cd5541@linaro.org> To: Tero Kristo , Stephen Boyd , Brian Masney , Jerome Brunet , Tony Lindgren , Andrew Goodbody , Rouven Czerwinski Cc: linux-omap@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Ettore Chimenti X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792083282; l=1025; i=ettore.chimenti@linaro.org; s=20261014; h=from:subject:message-id; bh=2inYdETjS1/0iXkUB93PtZKo6J17s5dPHUL/VIsncwk=; b=1O5ZnXuEuCnMjVuOJ4/eQtTIjxT1rnz127MjHOzITCjBaKT4WFTMzwIdwSnN3JBq7HUuWeMkK TtnNlcvtqHgAr67OdDdCYKEthyZ5kv0y+0ALBbuBnHrA6OOgOB7mXzO X-Developer-Key: i=ettore.chimenti@linaro.org; a=ed25519; pk=wCaUblFVaqhuBTQt/hAtysafsAaEsqj/yOD9SPlz6NM= This patch adds a new clock alias for the DM816x system, mapping 'sys_ck' to 'sys_clkin_ck'. This change is necessary because the voltage management driver searches for 'sys_ck' in these systems and fails without this alias. By including 'sys_ck' as an alias for 'sys_clkin_ck', we ensure compatibility with existing drivers that may reference 'sys_ck'. Tested-by: Andrew Goodbody Signed-off-by: Ettore Chimenti --- drivers/clk/ti/clk-816x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/ti/clk-816x.c b/drivers/clk/ti/clk-816x.c index 3b8e483aec92..fe6f66fc5a05 100644 --- a/drivers/clk/ti/clk-816x.c +++ b/drivers/clk/ti/clk-816x.c @@ -57,6 +57,7 @@ static struct ti_dt_clk dm816x_clks[] =3D { DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"), DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"), + DT_CLK(NULL, "sys_ck", "sys_clkin_ck"), { .node_name =3D NULL }, }; =20 --=20 2.56.0