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Wed, 14 Oct 2026 16:34:21 -0500 From: Ben Levinsky To: , , , , , CC: , , , , , , Subject: [PATCH 1/6] remoteproc: amd_mbv_bram: Bound device name formatting Date: Wed, 14 Oct 2026 14:34:21 -0700 Message-ID: <20261014213426.2957480-2-ben.levinsky@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261014213426.2957480-1-ben.levinsky@amd.com> References: <20261014213426.2957480-1-ben.levinsky@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001E9:EE_|MW4PR12MB7381:EE_ X-MS-Office365-Filtering-Correlation-Id: 9bf3c622-a1b4-4868-c62c-08df2a3aefba X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|23010399003|7416014|36860700016|1800799024|82310400026|56012099006|11063799006|261009223027099003|10067099003|18002099003|22082099003|3023799007; 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charset="utf-8" rproc_mem_entry_init() interprets its name argument as a printf format string. Passing the device name directly allows percent conversions in a DT-derived platform device name to consume nonexistent variadic arguments. Pass the device name through a constant format so it is always handled as data. Limit the formatted name to 31 characters to match the space available in rproc_mem_entry::name while leaving room for its terminating null byte. Fixes: f87b4998994e ("remoteproc: Add AMD MicroBlaze/V BRAM-based remote pr= ocessor driver") Reviewed-by: Tanmay Shah Signed-off-by: Ben Levinsky --- drivers/remoteproc/amd_mbv_bram_rproc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/remoteproc/amd_mbv_bram_rproc.c b/drivers/remoteproc/a= md_mbv_bram_rproc.c index e4a103cf8455..6cf33c7b7e64 100644 --- a/drivers/remoteproc/amd_mbv_bram_rproc.c +++ b/drivers/remoteproc/amd_mbv_bram_rproc.c @@ -72,7 +72,7 @@ static int amd_bram_rproc_prepare(struct rproc *rproc) resource_size(&res), da, rproc_mem_entry_ioremap_wc, rproc_mem_entry_iounmap, - dev_name(priv->dev)); + "%.31s", dev_name(priv->dev)); if (!mem) return -ENOMEM; =20 --=20 2.34.1 From nobody Wed Oct 14 23:29:32 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011025.outbound.protection.outlook.com [40.107.208.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5A523A168E; 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charset="utf-8" Partial reconfiguration of the programmable logic restores the AXI GPIO that drives the soft-core reset to its hardware default direction, but gpiolib keeps its cached output direction. gpiod_set_value_cansleep() then only updates the data register, so the processor never sees a reset transition: remoteproc reports it as running while the newly loaded firmware never starts. Use gpiod_direction_output() for every reset transition so the output direction is re-established, and assert reset briefly before releasing it so each start produces a clean reset pulse after the firmware has been loaded. Fixes: f87b4998994e ("remoteproc: Add AMD MicroBlaze/V BRAM-based remote pr= ocessor driver") Assisted-by: LLM sparse Signed-off-by: Ben Levinsky --- drivers/remoteproc/amd_mbv_bram_rproc.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/remoteproc/amd_mbv_bram_rproc.c b/drivers/remoteproc/a= md_mbv_bram_rproc.c index 6cf33c7b7e64..da621f62f7df 100644 --- a/drivers/remoteproc/amd_mbv_bram_rproc.c +++ b/drivers/remoteproc/amd_mbv_bram_rproc.c @@ -16,6 +16,7 @@ */ =20 #include +#include #include #include #include @@ -94,8 +95,24 @@ static int amd_bram_rproc_start(struct rproc *rproc) return ret; } =20 + /* + * Partial reconfiguration restores the PL GPIO hardware defaults but + * leaves gpiolib's cached direction unchanged. Re-establish the output + * direction and generate a reset pulse after firmware has been loaded. + * gpiod_set_value_cansleep() is insufficient here because it changes the + * value without restoring an output direction lost during DFX. + */ + ret =3D gpiod_direction_output(priv->reset, 1); + if (ret) { + dev_err(priv->dev, "failed to assert reset: %d\n", ret); + clk_disable_unprepare(priv->clk); + return ret; + } + /* Hold reset asserted long enough to provide a clean reset pulse. */ + usleep_range(10, 20); + /* Deassert reset and let the processor run. */ - ret =3D gpiod_set_value_cansleep(priv->reset, 0); + ret =3D gpiod_direction_output(priv->reset, 0); if (ret) { dev_err(priv->dev, "failed to deassert reset: %d\n", ret); clk_disable_unprepare(priv->clk); @@ -110,8 +127,8 @@ static int amd_bram_rproc_stop(struct rproc *rproc) struct amd_bram_rproc *priv =3D rproc->priv; int ret; =20 - /* Assert reset before disabling the processor clock. */ - ret =3D gpiod_set_value_cansleep(priv->reset, 1); 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charset="utf-8" Document the AMD programmable-logic Mailbox IP used for bidirectional FIFO communication between two processor-facing interfaces. The same IP is used on ZynqMP, Versal, Versal NET and Versal Gen 2. Name each SoC in its compatible, and use amd,zynqmp-pl-mbox-2.1 as the fallback that drivers match. Define the transmit and receive channel indices together with the register aperture, interrupt, and interface clock. Describe the FIFO depth chosen when the IP is configured, so that the driver can size received messages to it. Assisted-by: LLM sparse Signed-off-by: Ben Levinsky --- .../mailbox/amd,zynqmp-pl-mbox-2.1.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/amd,zynqmp-pl= -mbox-2.1.yaml diff --git a/Documentation/devicetree/bindings/mailbox/amd,zynqmp-pl-mbox-2= .1.yaml b/Documentation/devicetree/bindings/mailbox/amd,zynqmp-pl-mbox-2.1.= yaml new file mode 100644 index 000000000000..2cc0d106b888 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/amd,zynqmp-pl-mbox-2.1.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/amd,zynqmp-pl-mbox-2.1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Programmable Logic Mailbox IP + +maintainers: + - Ben Levinsky + +description: | + The AMD Programmable Logic Mailbox IP provides bidirectional message pas= sing + between two processor-facing interfaces. Each interface writes messages = to + a send FIFO and reads messages from a receive FIFO. The register apertur= e, + interrupt, and clock described by a node belong to one processor-facing + interface. Channel 0 represents transmit and channel 1 represents receive + for that interface. + +properties: + compatible: + oneOf: + - const: amd,zynqmp-pl-mbox-2.1 + - items: + - enum: + - amd,versal-pl-mbox-2.1 + - amd,versal-net-pl-mbox-2.1 + - amd,versal2-pl-mbox-2.1 + - const: amd,zynqmp-pl-mbox-2.1 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + amd,mbox-pl-fifo-len: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 16 + maximum: 8192 + default: 16 + description: + Depth of the send and receive FIFOs in 32-bit words, as configured by + the C_MAILBOX_DEPTH parameter of the IP. Must match the configured + depth. + + '#mbox-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - '#mbox-cells' + +additionalProperties: false + +examples: + - | + #include + + mailbox@b2060000 { + compatible =3D "amd,zynqmp-pl-mbox-2.1"; + reg =3D <0xb2060000 0x10000>; + interrupts =3D ; + clocks =3D <&pl_clk>; + amd,mbox-pl-fifo-len =3D <16>; + #mbox-cells =3D <1>; + }; +... --=20 2.34.1 From nobody Wed Oct 14 23:29:32 2026 Received: from BL2PR02CU003.outbound.protection.outlook.com (mail-eastusazon11011001.outbound.protection.outlook.com [52.101.52.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 699E9472F95; Wed, 14 Oct 2026 21:34:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.52.1 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792013688; cv=fail; b=JnOSa8qGBV5GGmuKmESL0Kt+qnCKZQaQ9+zImb/Dlt7uurJ4k/oWmQvY32vC2E4vtVAAK6nPVAPP/m51fMQVQVOoEM9ucvvAZqIjoQOsCH7da2PdJ3vKAapkBVqiQYNueoBqVzaFHHvScledq37GcFYAlWOds7Z5CadnKuXD4os= ARC-Message-Signature: i=2; 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Wed, 14 Oct 2026 16:34:25 -0500 From: Ben Levinsky To: , , , , , CC: , , , , , , Subject: [PATCH 4/6] mailbox: Add AMD PL Mailbox soft IP controller Date: Wed, 14 Oct 2026 14:34:24 -0700 Message-ID: <20261014213426.2957480-5-ben.levinsky@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261014213426.2957480-1-ben.levinsky@amd.com> References: <20261014213426.2957480-1-ben.levinsky@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001EF:EE_|SJ0PR12MB6992:EE_ X-MS-Office365-Filtering-Correlation-Id: 67269bf0-89c4-4eab-c515-08df2a3af3af X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|376014|7416014|82310400026|23010399003|10067099003|11063799006|56012099006|261009223027099003|22082099003|18002099003|6133799003|13003099007; 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charset="utf-8" Add a mailbox-framework controller for the AMD programmable-logic Mailbox soft IP. Expose separate transmit and receive FIFO channels. Enable the interface clock only while a channel is started, before any register access, and disable it last when the channel shuts down. Keep provider probe free of register accesses and leave the IRQ disabled until a client starts the receive channel. Initialize each FIFO when its channel starts, use receive-threshold interrupts for incoming words, and poll the send-threshold status for transmit completion. Stop that polling from accessing registers once the transmit channel begins to shut down. Carry mailbox payloads in struct zynqmp_ipi_message, limited to the FIFO depth given by the device tree. The FIFO transfers 32-bit words and the hardware conveys neither a byte count nor the FIFO occupancy, so a transmit length that is not a multiple of four is zero-padded to a whole word. On a receive-threshold interrupt, read up to one FIFO depth of words and deliver them as one message, then acknowledge the interrupt. The event latches only when the FIFO goes from empty to nonempty, so a word that arrives between the drain and the acknowledge, or words left by the bounded drain, raise no new event. If the FIFO is nonempty after the acknowledge, toggle the threshold to latch a new event for them. Assisted-by: LLM sparse Signed-off-by: Ben Levinsky --- MAINTAINERS | 7 + drivers/mailbox/Kconfig | 10 + drivers/mailbox/Makefile | 1 + drivers/mailbox/amd-pl-mailbox.c | 369 +++++++++++++++++++++++++++++++ 4 files changed, 387 insertions(+) create mode 100644 drivers/mailbox/amd-pl-mailbox.c diff --git a/MAINTAINERS b/MAINTAINERS index f53047aa8d3c..4e28e0c311c0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1287,6 +1287,13 @@ S: Supported T: git https://gitlab.freedesktop.org/agd5f/linux.git F: drivers/gpu/drm/amd/pm/ =20 +AMD PROGRAMMABLE LOGIC MAILBOX DRIVER +M: Ben Levinsky +L: linux-kernel@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/mailbox/amd,zynqmp-pl-mbox-2.1.yaml +F: drivers/mailbox/amd-pl-mailbox.c + AMD PSTATE DRIVER M: Huang Rui M: Mario Limonciello diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index ab869769e278..3c3f262c903c 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -8,6 +8,16 @@ menuconfig MAILBOX =20 if MAILBOX =20 +config AMD_PL_MAILBOX + tristate "AMD PL Mailbox soft IP controller" + depends on HAS_IOMEM + depends on OF + help + Mailbox controller for the AMD Programmable Logic Mailbox soft IP. + The controller exposes transmit and receive FIFO channels to mailbox + clients. It supports interrupt-driven receive notification and + polling-based transmit completion through the common mailbox framework. + config ARM_MHU tristate "ARM MHU Mailbox" depends on ARM_AMBA diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 45dc59bb3e7f..5614d7e1e2f8 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_MAILBOX) +=3D mailbox.o =20 obj-$(CONFIG_MAILBOX_TEST) +=3D mailbox-test.o +obj-$(CONFIG_AMD_PL_MAILBOX) +=3D amd-pl-mailbox.o =20 obj-$(CONFIG_ARM_MHU) +=3D arm_mhu.o arm_mhu_db.o =20 diff --git a/drivers/mailbox/amd-pl-mailbox.c b/drivers/mailbox/amd-pl-mail= box.c new file mode 100644 index 000000000000..bd6595332f53 --- /dev/null +++ b/drivers/mailbox/amd-pl-mailbox.c @@ -0,0 +1,369 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AMD_PL_MBOX_WRDATA 0x00 +#define AMD_PL_MBOX_RDDATA 0x08 +#define AMD_PL_MBOX_STATUS 0x10 +#define AMD_PL_MBOX_ERROR 0x14 +#define AMD_PL_MBOX_SEND_THRESHOLD 0x18 +#define AMD_PL_MBOX_RECV_THRESHOLD 0x1c +#define AMD_PL_MBOX_IRQ_STATUS 0x20 +#define AMD_PL_MBOX_IRQ_ENABLE 0x24 +#define AMD_PL_MBOX_CTRL 0x2c + +#define AMD_PL_MBOX_STS_RX_EMPTY BIT(0) +#define AMD_PL_MBOX_STS_TX_FULL BIT(1) +#define AMD_PL_MBOX_STS_TX_THRESHOLD BIT(2) +#define AMD_PL_MBOX_IRQ_RX_THRESHOLD BIT(1) +#define AMD_PL_MBOX_IRQ_ERROR BIT(2) +#define AMD_PL_MBOX_CTRL_TX_RESET BIT(0) +#define AMD_PL_MBOX_CTRL_RX_RESET BIT(1) + +/* FIFO depth range of the IP, in 32-bit words. */ +#define AMD_PL_MBOX_FIFO_LEN_MIN 16 +#define AMD_PL_MBOX_FIFO_LEN_MAX 8192 + +/* + * The send threshold is active while send FIFO occupancy is less than or + * equal to the programmed value. The receive threshold is active while + * receive FIFO occupancy is greater than the programmed value. The related + * interrupt status bits latch when a threshold condition becomes active, + * and a new event takes priority over a simultaneous status clear. + * + * A send threshold of zero makes the status bit indicate an empty TX FIFO. + * A receive threshold of zero raises an interrupt for the first received + * word after the RX FIFO becomes empty. + */ + +enum { + AMD_PL_MBOX_CHAN_TX =3D 0, + AMD_PL_MBOX_CHAN_RX =3D 1, + AMD_PL_MBOX_NUM_CHANS =3D 2, +}; + +/** + * struct amd_pl_mbox - AMD PL Mailbox controller state + * @regs: mapped register aperture + * @clk: interface clock, enabled while a channel is started + * @irq: receive interrupt + * @fifo_len: FIFO depth in 32-bit words + * @tx_lock: serializes TX completion polling against TX shutdown + * @tx_active: TX channel is started and its registers may be accessed + * @controller: common mailbox controller + * @chans: transmit and receive mailbox channels + * @rx_msg: receive buffer passed to mailbox clients + */ +struct amd_pl_mbox { + void __iomem *regs; + struct clk *clk; + int irq; + u32 fifo_len; + spinlock_t tx_lock; /* protects tx_active */ + bool tx_active; + struct mbox_controller controller; + struct mbox_chan chans[AMD_PL_MBOX_NUM_CHANS]; + struct zynqmp_ipi_message *rx_msg; +}; + +static int amd_pl_mbox_send_data(struct mbox_chan *chan, void *data) +{ + struct amd_pl_mbox *mb =3D chan->con_priv; + struct zynqmp_ipi_message *msg =3D data; + size_t offset; + + if (chan !=3D &mb->chans[AMD_PL_MBOX_CHAN_TX]) + return -EINVAL; + + /* The TX FIFO is empty here, since TX completion waits for it. */ + if (!msg || !msg->len || msg->len > mb->fifo_len * sizeof(u32)) + return -EINVAL; + + for (offset =3D 0; offset < msg->len; offset +=3D sizeof(u32)) { + size_t count =3D min(sizeof(u32), msg->len - offset); + u32 word =3D 0; + + if (readl(mb->regs + AMD_PL_MBOX_STATUS) & + AMD_PL_MBOX_STS_TX_FULL) + return -EBUSY; + + memcpy(&word, &msg->data[offset], count); + writel(word, mb->regs + AMD_PL_MBOX_WRDATA); + } + + return 0; +} + +static bool amd_pl_mbox_last_tx_done(struct mbox_chan *chan) +{ + struct amd_pl_mbox *mb =3D chan->con_priv; + unsigned long flags; + bool done =3D true; + + /* + * The mailbox core can poll after shutdown() has started, while the + * interface clock is being disabled. Do not access registers then. + */ + spin_lock_irqsave(&mb->tx_lock, flags); + if (mb->tx_active) + /* SIT is zero, so the threshold status means TX FIFO empty. */ + done =3D readl(mb->regs + AMD_PL_MBOX_STATUS) & + AMD_PL_MBOX_STS_TX_THRESHOLD; + spin_unlock_irqrestore(&mb->tx_lock, flags); + + return done; +} + +static int amd_pl_mbox_startup(struct mbox_chan *chan) +{ + struct amd_pl_mbox *mb =3D chan->con_priv; + unsigned long flags; + u32 irq_enable; + int ret; + + if (chan !=3D &mb->chans[AMD_PL_MBOX_CHAN_TX] && + chan !=3D &mb->chans[AMD_PL_MBOX_CHAN_RX]) + return -EINVAL; + + ret =3D clk_prepare_enable(mb->clk); + if (ret) + return ret; + + if (chan =3D=3D &mb->chans[AMD_PL_MBOX_CHAN_TX]) { + writel(AMD_PL_MBOX_CTRL_TX_RESET, mb->regs + AMD_PL_MBOX_CTRL); + writel(0, mb->regs + AMD_PL_MBOX_SEND_THRESHOLD); + + spin_lock_irqsave(&mb->tx_lock, flags); + mb->tx_active =3D true; + spin_unlock_irqrestore(&mb->tx_lock, flags); + + return 0; + } + + writel(AMD_PL_MBOX_CTRL_RX_RESET, mb->regs + AMD_PL_MBOX_CTRL); + /* Interrupt when the RX FIFO changes from empty to nonempty. */ + writel(0, mb->regs + AMD_PL_MBOX_RECV_THRESHOLD); + writel(AMD_PL_MBOX_IRQ_RX_THRESHOLD | AMD_PL_MBOX_IRQ_ERROR, + mb->regs + AMD_PL_MBOX_IRQ_STATUS); + irq_enable =3D readl(mb->regs + AMD_PL_MBOX_IRQ_ENABLE); + irq_enable |=3D AMD_PL_MBOX_IRQ_RX_THRESHOLD | AMD_PL_MBOX_IRQ_ERROR; + writel(irq_enable, mb->regs + AMD_PL_MBOX_IRQ_ENABLE); + enable_irq(mb->irq); + + return 0; +} + +static void amd_pl_mbox_shutdown(struct mbox_chan *chan) +{ + struct amd_pl_mbox *mb =3D chan->con_priv; + unsigned long flags; + u32 irq_enable; + + if (chan =3D=3D &mb->chans[AMD_PL_MBOX_CHAN_TX]) { + spin_lock_irqsave(&mb->tx_lock, flags); + mb->tx_active =3D false; + spin_unlock_irqrestore(&mb->tx_lock, flags); + + writel(AMD_PL_MBOX_CTRL_TX_RESET, mb->regs + AMD_PL_MBOX_CTRL); + clk_disable_unprepare(mb->clk); + return; + } + + if (chan !=3D &mb->chans[AMD_PL_MBOX_CHAN_RX]) + return; + + disable_irq(mb->irq); + irq_enable =3D readl(mb->regs + AMD_PL_MBOX_IRQ_ENABLE); + irq_enable &=3D ~(AMD_PL_MBOX_IRQ_RX_THRESHOLD | AMD_PL_MBOX_IRQ_ERROR); + writel(irq_enable, mb->regs + AMD_PL_MBOX_IRQ_ENABLE); + writel(AMD_PL_MBOX_IRQ_RX_THRESHOLD | AMD_PL_MBOX_IRQ_ERROR, + mb->regs + AMD_PL_MBOX_IRQ_STATUS); + writel(AMD_PL_MBOX_CTRL_RX_RESET, mb->regs + AMD_PL_MBOX_CTRL); + clk_disable_unprepare(mb->clk); +} + +static const struct mbox_chan_ops amd_pl_mbox_ops =3D { + .send_data =3D amd_pl_mbox_send_data, + .last_tx_done =3D amd_pl_mbox_last_tx_done, + .startup =3D amd_pl_mbox_startup, + .shutdown =3D amd_pl_mbox_shutdown, +}; + +static void amd_pl_mbox_rx(struct amd_pl_mbox *mb) +{ + /* data[] follows a size_t in a kzalloc() buffer: u32 aligned. */ + u32 *rx_words =3D (u32 *)mb->rx_msg->data; + u32 words; + + /* + * The hardware reports neither the peer's message length nor the FIFO + * occupancy. Read until the FIFO is empty, up to one FIFO depth, and + * deliver the words as one message. + */ + for (words =3D 0; words < mb->fifo_len; words++) { + if (readl(mb->regs + AMD_PL_MBOX_STATUS) & + AMD_PL_MBOX_STS_RX_EMPTY) + break; + + rx_words[words] =3D readl(mb->regs + AMD_PL_MBOX_RDDATA); + } + + if (words) { + mb->rx_msg->len =3D words * sizeof(u32); + mbox_chan_received_data(&mb->chans[AMD_PL_MBOX_CHAN_RX], + mb->rx_msg); + } +} + +static void amd_pl_mbox_rx_rearm(struct amd_pl_mbox *mb) +{ + /* + * The receive event latches only when the FIFO goes from empty to + * nonempty. A word that arrived after the drain, but before the event + * was acknowledged, had its event cleared, and words left by the + * bounded drain never raised one. Raise the threshold and lower it + * again to latch a new event, so that the interrupt fires for them. + * This cannot latch an event while the FIFO is full, which happens only + * if the peer writes a full FIFO depth during one interrupt. + */ + if (!(readl(mb->regs + AMD_PL_MBOX_STATUS) & + AMD_PL_MBOX_STS_RX_EMPTY)) { + writel(mb->fifo_len - 1, mb->regs + AMD_PL_MBOX_RECV_THRESHOLD); + writel(0, mb->regs + AMD_PL_MBOX_RECV_THRESHOLD); + } +} + +static irqreturn_t amd_pl_mbox_irq(int irq, void *data) +{ + struct amd_pl_mbox *mb =3D data; + u32 pending_intr; + u32 irq_enable; + u32 irq_status; + + irq_status =3D readl(mb->regs + AMD_PL_MBOX_IRQ_STATUS); + irq_enable =3D readl(mb->regs + AMD_PL_MBOX_IRQ_ENABLE); + pending_intr =3D irq_status & irq_enable; + + if (!pending_intr) { + dev_warn_ratelimited(mb->controller.dev, + "unexpected interrupt: status %#x enable %#x\n", + irq_status, irq_enable); + return IRQ_NONE; + } + + if (pending_intr & AMD_PL_MBOX_IRQ_RX_THRESHOLD) + amd_pl_mbox_rx(mb); + + if (pending_intr & AMD_PL_MBOX_IRQ_ERROR) + dev_warn_ratelimited(mb->controller.dev, + "mailbox FIFO error: %#x\n", + readl(mb->regs + AMD_PL_MBOX_ERROR)); + + writel(pending_intr, mb->regs + AMD_PL_MBOX_IRQ_STATUS); + + if (pending_intr & AMD_PL_MBOX_IRQ_RX_THRESHOLD) + amd_pl_mbox_rx_rearm(mb); + + return IRQ_HANDLED; +} + +static struct mbox_chan *amd_pl_mbox_xlate(struct mbox_controller *ctlr, + const struct of_phandle_args *sp) +{ + if (sp->args_count !=3D 1 || sp->args[0] >=3D AMD_PL_MBOX_NUM_CHANS) + return ERR_PTR(-EINVAL); + + return &ctlr->chans[sp->args[0]]; +} + +static int amd_pl_mbox_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct amd_pl_mbox *mb; + int ret; + int i; + + mb =3D devm_kzalloc(dev, sizeof(*mb), GFP_KERNEL); + if (!mb) + return -ENOMEM; + + spin_lock_init(&mb->tx_lock); + + mb->fifo_len =3D AMD_PL_MBOX_FIFO_LEN_MIN; + ret =3D of_property_read_u32(dev->of_node, "amd,mbox-pl-fifo-len", + &mb->fifo_len); + if (ret && ret !=3D -EINVAL) + return dev_err_probe(dev, ret, "failed to read FIFO length\n"); + + if (mb->fifo_len < AMD_PL_MBOX_FIFO_LEN_MIN || + mb->fifo_len > AMD_PL_MBOX_FIFO_LEN_MAX) + return dev_err_probe(dev, -EINVAL, "invalid FIFO length %u\n", + mb->fifo_len); + + mb->rx_msg =3D devm_kzalloc(dev, struct_size(mb->rx_msg, data, + mb->fifo_len * sizeof(u32)), + GFP_KERNEL); + if (!mb->rx_msg) + return -ENOMEM; + + mb->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(mb->regs)) + return PTR_ERR(mb->regs); + + mb->clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(mb->clk)) + return dev_err_probe(dev, PTR_ERR(mb->clk), "failed to get clock\n"); + + mb->irq =3D platform_get_irq(pdev, 0); + if (mb->irq < 0) + return mb->irq; + + for (i =3D 0; i < AMD_PL_MBOX_NUM_CHANS; i++) + mb->chans[i].con_priv =3D mb; + + mb->controller.dev =3D dev; + mb->controller.ops =3D &amd_pl_mbox_ops; + mb->controller.chans =3D mb->chans; + mb->controller.num_chans =3D AMD_PL_MBOX_NUM_CHANS; + mb->controller.txdone_poll =3D true; + mb->controller.txpoll_period =3D 1; + mb->controller.of_xlate =3D amd_pl_mbox_xlate; + + ret =3D devm_request_irq(dev, mb->irq, amd_pl_mbox_irq, + IRQF_NO_AUTOEN, + dev_name(dev), mb); + if (ret) + return ret; + + return devm_mbox_controller_register(dev, &mb->controller); +} + +static const struct of_device_id amd_pl_mbox_of_match[] =3D { + { .compatible =3D "amd,zynqmp-pl-mbox-2.1" }, + { .compatible =3D "amd,versal-pl-mbox-2.1" }, + { .compatible =3D "amd,versal-net-pl-mbox-2.1" }, + { .compatible =3D "amd,versal2-pl-mbox-2.1" }, + { } +}; +MODULE_DEVICE_TABLE(of, amd_pl_mbox_of_match); + +static struct platform_driver amd_pl_mbox_driver =3D { + .probe =3D amd_pl_mbox_probe, + .driver =3D { + .name =3D "amd-pl-mailbox", + .of_match_table =3D amd_pl_mbox_of_match, + }, +}; +module_platform_driver(amd_pl_mbox_driver); + +MODULE_DESCRIPTION("AMD PL Mailbox soft IP controller"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Wed Oct 14 23:29:32 2026 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012070.outbound.protection.outlook.com [40.93.195.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6350446075; 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charset="utf-8" Describe the optional mailbox channels and named reserved-memory regions used for RPMsg communication with a BRAM-based MicroBlaze remote processor. The three named memory regions provide the two virtio vrings and the shared RPMsg buffer pool. Firmware and its loaded resource table remain in the executable BRAM described by reg. Assisted-by: LLM sparse Signed-off-by: Ben Levinsky --- .../bindings/remoteproc/amd,bram-rproc.yaml | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/Documentation/devicetree/bindings/remoteproc/amd,bram-rproc.ya= ml b/Documentation/devicetree/bindings/remoteproc/amd,bram-rproc.yaml index c0359f447ea8..daff8e615ab6 100644 --- a/Documentation/devicetree/bindings/remoteproc/amd,bram-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/amd,bram-rproc.yaml @@ -84,6 +84,33 @@ properties: description: GPIO specifier controlling the soft-core reset input. =20 + mboxes: + maxItems: 2 + + mbox-names: + items: + - const: tx + - const: rx + + memory-region: + maxItems: 3 + + memory-region-names: + items: + - const: vdev0vring0 + - const: vdev0vring1 + - const: vdev0buffer + +dependentRequired: + mboxes: + - mbox-names + mbox-names: + - mboxes + memory-region: + - memory-region-names + memory-region-names: + - memory-region + required: - compatible - reg @@ -101,5 +128,9 @@ examples: clocks =3D <&pl_clk>; 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Wed, 14 Oct 2026 16:34:27 -0500 From: Ben Levinsky To: , , , , , CC: , , , , , , Subject: [PATCH 6/6] remoteproc: amd_mbv_bram: Add RPMsg support Date: Wed, 14 Oct 2026 14:34:26 -0700 Message-ID: <20261014213426.2957480-7-ben.levinsky@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261014213426.2957480-1-ben.levinsky@amd.com> References: <20261014213426.2957480-1-ben.levinsky@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001EF:EE_|SA1PR12MB6704:EE_ X-MS-Office365-Filtering-Correlation-Id: f3085e30-ef5b-47f5-549b-08df2a3af4a5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|23010399003|7416014|36860700016|1800799024|82310400026|56012099006|11063799006|261009223027099003|261009223327099003|261009221227099003|261009221727099003|261009220027099003|10067099003|18002099003|22082099003|6133799003|3023799007; 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charset="utf-8" Register named reserved-memory carveouts and expose the firmware resource table after it has been loaded into BRAM. This lets remoteproc create virtqueues backed by reserved shared DDR without deriving carveout roles from DT node names. Map the shared-memory carveouts with the common rproc_mem_entry_ioremap_wc() and rproc_mem_entry_iounmap() callbacks. Use the mailbox framework to send virtqueue notification IDs. Defer received notifications to process context before dispatching them to the remoteproc virtqueues. Keep mailbox payload storage valid until transmit completion and order write-combined vring updates before each kick. For designs where the mailbox and remote processor share a clock, request the mailbox channels only after enabling that clock, while the processor is still held in reset. Release the channels before disabling the clock during stop. The mailboxes are optional. Without them the driver keeps supporting load, start, and stop only. Select the mailbox framework, the AMD PL Mailbox controller and the virtio RPMsg bus, which the driver uses for notifications and RPMsg channels. Selecting MAILBOX while depending on GPIOLIB creates a Kconfig recursive dependency, because GPIOLIB is selected by drivers that are reachable from MAILBOX, so select GPIOLIB as well instead of depending on it. The driver always needs GPIO for the reset line. Depend on HAS_IOMEM, which the selected mailbox controller and the write-combined carveout mappings require. Assisted-by: LLM sparse Signed-off-by: Ben Levinsky --- drivers/remoteproc/Kconfig | 6 +- drivers/remoteproc/amd_mbv_bram_rproc.c | 231 +++++++++++++++++++++++- 2 files changed, 235 insertions(+), 2 deletions(-) diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index 5b56b2dcc725..9ebbbf76289f 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -25,7 +25,11 @@ config REMOTEPROC_CDEV =20 config AMD_MBV_BRAM_REMOTEPROC tristate "AMD MicroBlaze/V BRAM-based remoteproc support" - depends on OF && COMMON_CLK && (GPIOLIB || COMPILE_TEST) + depends on OF && COMMON_CLK && HAS_IOMEM + select GPIOLIB + select MAILBOX + select AMD_PL_MAILBOX + select RPMSG_VIRTIO help Say y or m here to support a MicroBlaze/V BRAM-based remote processor managed through the remoteproc framework. diff --git a/drivers/remoteproc/amd_mbv_bram_rproc.c b/drivers/remoteproc/a= md_mbv_bram_rproc.c index da621f62f7df..65d2c3946325 100644 --- a/drivers/remoteproc/amd_mbv_bram_rproc.c +++ b/drivers/remoteproc/amd_mbv_bram_rproc.c @@ -15,15 +15,20 @@ * Reset is controlled via GPIO connected to Processor System Reset IP. */ =20 +#include #include #include #include #include +#include +#include #include #include #include +#include #include #include +#include =20 #include "remoteproc_internal.h" =20 @@ -32,13 +37,207 @@ * @dev: device pointer * @reset: GPIO descriptor for reset control (active-low) * @clk: processor clock + * @rproc: remote processor instance + * @tx_client: mailbox client used for virtqueue kicks + * @rx_client: mailbox client used for remote notifications + * @tx_chan: transmit mailbox channel + * @rx_chan: receive mailbox channel + * @notify_msgs: persistent mailbox payload storage indexed by notify ID + * @pending_notify_ids: notifications awaiting process-context dispatch + * @rx_work: work item that dispatches received virtqueue notifications */ struct amd_bram_rproc { struct device *dev; struct gpio_desc *reset; struct clk *clk; + struct rproc *rproc; + struct mbox_client tx_client; + struct mbox_client rx_client; + struct mbox_chan *tx_chan; + struct mbox_chan *rx_chan; + struct zynqmp_ipi_message *notify_msgs[256]; + DECLARE_BITMAP(pending_notify_ids, 256); + struct work_struct rx_work; }; =20 +static void amd_bram_rproc_rx_work(struct work_struct *work) +{ + struct amd_bram_rproc *priv =3D + container_of(work, struct amd_bram_rproc, rx_work); + unsigned long notifyid; + + for_each_set_bit(notifyid, priv->pending_notify_ids, + ARRAY_SIZE(priv->notify_msgs)) { + clear_bit(notifyid, priv->pending_notify_ids); + if (rproc_vq_interrupt(priv->rproc, notifyid) =3D=3D IRQ_NONE) + dev_dbg(priv->dev, "no virtqueue for notifyid %lu\n", + notifyid); + } +} + +static void amd_bram_rproc_rx_callback(struct mbox_client *client, void *m= sg) +{ + struct amd_bram_rproc *priv =3D + container_of(client, struct amd_bram_rproc, rx_client); + struct zynqmp_ipi_message *mb_msg =3D msg; + size_t offset; + u32 notifyid; + + if (!msg) { + dev_warn_ratelimited(priv->dev, + "received mailbox notification without data\n"); + return; + } + + /* Each notification is one 32-bit notify ID. */ + if (!mb_msg->len || mb_msg->len % sizeof(u32)) { + dev_warn_ratelimited(priv->dev, + "malformed mailbox notification: %zu bytes\n", + mb_msg->len); + return; + } + + for (offset =3D 0; offset < mb_msg->len; offset +=3D sizeof(u32)) { + memcpy(¬ifyid, &mb_msg->data[offset], sizeof(notifyid)); + if (notifyid >=3D ARRAY_SIZE(priv->notify_msgs)) { + dev_warn_ratelimited(priv->dev, "invalid notify id %u\n", + notifyid); + continue; + } + + set_bit(notifyid, priv->pending_notify_ids); + } + + schedule_work(&priv->rx_work); +} + +static void amd_bram_rproc_kick(struct rproc *rproc, int vqid) +{ + struct amd_bram_rproc *priv =3D rproc->priv; + struct zynqmp_ipi_message *msg; + int ret; + + if (!priv->tx_chan) { + dev_warn_ratelimited(priv->dev, + "cannot kick vq%d: no TX mailbox\n", vqid); + return; + } + + if (vqid < 0 || vqid >=3D ARRAY_SIZE(priv->notify_msgs)) { + dev_err_ratelimited(priv->dev, "invalid notify id %d\n", vqid); + return; + } + + /* + * The mailbox core queues message pointers. Keep each notification word + * in persistent storage until the controller reports TX completion. + */ + msg =3D priv->notify_msgs[vqid]; + msg->len =3D sizeof(u32); + memcpy(msg->data, &vqid, sizeof(u32)); + /* Order writes to WC vring mappings before notifying the remote. */ + wmb(); + ret =3D mbox_send_message(priv->tx_chan, msg); + if (ret < 0) + dev_err_ratelimited(priv->dev, "failed to kick vq%d: %d\n", + vqid, ret); +} + +static void amd_bram_rproc_free_mboxes(struct amd_bram_rproc *priv) +{ + if (priv->rx_chan) { + mbox_free_channel(priv->rx_chan); + priv->rx_chan =3D NULL; + } + if (priv->tx_chan) { + mbox_free_channel(priv->tx_chan); + priv->tx_chan =3D NULL; + } +} + +static int amd_bram_rproc_request_mboxes(struct amd_bram_rproc *priv) +{ + int ret; + + /* Without mailboxes the driver supports load, start, and stop only. */ + if (!of_property_present(priv->dev->of_node, "mboxes")) + return 0; + + priv->tx_chan =3D mbox_request_channel_byname(&priv->tx_client, "tx"); + if (IS_ERR(priv->tx_chan)) { + ret =3D PTR_ERR(priv->tx_chan); + priv->tx_chan =3D NULL; + dev_err(priv->dev, "failed to request tx mailbox: %d\n", ret); + return ret; + } + + priv->rx_chan =3D mbox_request_channel_byname(&priv->rx_client, "rx"); + if (IS_ERR(priv->rx_chan)) { + ret =3D PTR_ERR(priv->rx_chan); + priv->rx_chan =3D NULL; + mbox_free_channel(priv->tx_chan); + priv->tx_chan =3D NULL; + dev_err(priv->dev, "failed to request rx mailbox: %d\n", ret); + return ret; + } + + return 0; +} + +static int amd_bram_rproc_add_reserved_mem(struct rproc *rproc) +{ + struct amd_bram_rproc *priv =3D rproc->priv; + struct device_node *np =3D priv->dev->of_node; + struct rproc_mem_entry *mem; + int count; + int ret; + int i; + + if (!of_property_present(np, "memory-region")) + return 0; + + count =3D of_reserved_mem_region_count(np); + if (count < 0) + return count; + + for (i =3D 0; i < count; i++) { + struct resource res; + const char *name; + + ret =3D of_property_read_string_index(np, "memory-region-names", + i, &name); + if (ret) + return dev_err_probe(priv->dev, ret, + "failed to read memory-region name %d\n", + i); + + ret =3D of_reserved_mem_region_to_resource(np, i, &res); + if (ret) + return dev_err_probe(priv->dev, ret, + "failed to parse memory-region %d\n", i); + + if (!strcmp(name, "vdev0buffer")) + mem =3D rproc_of_resm_mem_entry_init(priv->dev, i, + resource_size(&res), + res.start, name); + else + mem =3D rproc_mem_entry_init(priv->dev, NULL, + (dma_addr_t)res.start, + resource_size(&res), res.start, + rproc_mem_entry_ioremap_wc, + rproc_mem_entry_iounmap, + "%s", name); + if (!mem) + return -ENOMEM; + + rproc_add_carveout(rproc, mem); + rproc_coredump_add_segment(rproc, res.start, resource_size(&res)); + dev_dbg(priv->dev, "reserved memory carveout %pR\n", &res); + } + + return 0; +} + static int amd_bram_rproc_prepare(struct rproc *rproc) { struct amd_bram_rproc *priv =3D rproc->priv; @@ -80,7 +279,7 @@ static int amd_bram_rproc_prepare(struct rproc *rproc) rproc_add_carveout(rproc, mem); rproc_coredump_add_segment(rproc, da, resource_size(&res)); =20 - return 0; + return amd_bram_rproc_add_reserved_mem(rproc); } =20 static int amd_bram_rproc_start(struct rproc *rproc) @@ -111,10 +310,17 @@ static int amd_bram_rproc_start(struct rproc *rproc) /* Hold reset asserted long enough to provide a clean reset pulse. */ usleep_range(10, 20); =20 + ret =3D amd_bram_rproc_request_mboxes(priv); + if (ret) { + clk_disable_unprepare(priv->clk); + return ret; + } + /* Deassert reset and let the processor run. */ ret =3D gpiod_direction_output(priv->reset, 0); if (ret) { dev_err(priv->dev, "failed to deassert reset: %d\n", ret); + amd_bram_rproc_free_mboxes(priv); clk_disable_unprepare(priv->clk); return ret; } @@ -133,6 +339,10 @@ static int amd_bram_rproc_stop(struct rproc *rproc) dev_err(priv->dev, "failed to assert reset: %d\n", ret); return ret; } + cancel_work_sync(&priv->rx_work); + bitmap_zero(priv->pending_notify_ids, + ARRAY_SIZE(priv->notify_msgs)); + amd_bram_rproc_free_mboxes(priv); =20 /* Disable clock after asserting reset */ clk_disable_unprepare(priv->clk); @@ -156,6 +366,8 @@ static const struct rproc_ops amd_bram_rproc_ops =3D { .sanity_check =3D rproc_elf_sanity_check, .get_boot_addr =3D rproc_elf_get_boot_addr, .parse_fw =3D amd_bram_rproc_parse_fw, + .find_loaded_rsc_table =3D rproc_elf_find_loaded_rsc_table, + .kick =3D amd_bram_rproc_kick, }; =20 static int amd_bram_rproc_probe(struct platform_device *pdev) @@ -165,6 +377,7 @@ static int amd_bram_rproc_probe(struct platform_device = *pdev) const char *fw_name =3D NULL; struct rproc *rproc; int ret; + int i; =20 ret =3D rproc_of_parse_firmware(dev, 0, &fw_name); if (ret < 0 && ret !=3D -EINVAL) @@ -178,6 +391,8 @@ static int amd_bram_rproc_probe(struct platform_device = *pdev) =20 priv =3D rproc->priv; priv->dev =3D dev; + priv->rproc =3D rproc; + INIT_WORK(&priv->rx_work, amd_bram_rproc_rx_work); =20 /* Get the processor clock */ priv->clk =3D devm_clk_get(dev, NULL); @@ -195,6 +410,20 @@ static int amd_bram_rproc_probe(struct platform_device= *pdev) return dev_err_probe(dev, PTR_ERR(priv->reset), "failed to get reset gpio\n"); =20 + priv->tx_client.dev =3D dev; + priv->tx_client.tx_block =3D false; + priv->tx_client.knows_txdone =3D false; + priv->rx_client.dev =3D dev; + priv->rx_client.rx_callback =3D amd_bram_rproc_rx_callback; + for (i =3D 0; i < ARRAY_SIZE(priv->notify_msgs); i++) { + priv->notify_msgs[i] =3D + devm_kzalloc(dev, struct_size(priv->notify_msgs[i], + data, sizeof(u32)), + GFP_KERNEL); + if (!priv->notify_msgs[i]) + return -ENOMEM; + } + rproc->auto_boot =3D false; =20 ret =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); --=20 2.34.1