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Tue, 13 Oct 2026 14:15:58 -0700 (PDT) From: Magnus Lindholm To: richard.henderson@linaro.org, mattst88@gmail.com, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org Cc: linmag7@gmail.com Subject: [PATCH v7 1/5] alpha: move Tsunami machine check handling to err_tsunami.c Date: Tue, 13 Oct 2026 23:15:34 +0200 Message-ID: <20261013211551.991723-2-linmag7@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261013211551.991723-1-linmag7@gmail.com> References: <20261013211551.991723-1-linmag7@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the existing handler and PCI error clearing helpers without changing their behavior. Build the error objects for ALPHA_TSUNAMI so that all Tsunami configurations, including non-generic Shark, can use them. Signed-off-by: Magnus Lindholm Reviewed-by: Matt Turner --- arch/alpha/kernel/Makefile | 4 ++- arch/alpha/kernel/core_tsunami.c | 34 ----------------------- arch/alpha/kernel/err_tsunami.c | 47 ++++++++++++++++++++++++++++++++ 3 files changed, 50 insertions(+), 35 deletions(-) create mode 100644 arch/alpha/kernel/err_tsunami.c diff --git a/arch/alpha/kernel/Makefile b/arch/alpha/kernel/Makefile index 4ea5c189e60e..a453e487b9d0 100644 --- a/arch/alpha/kernel/Makefile +++ b/arch/alpha/kernel/Makefile @@ -39,7 +39,7 @@ obj-y +=3D err_ev7.o err_titan.o err_marvel.o endif =20 obj-y +=3D irq_pyxis.o irq_i8259.o irq_srm.o -obj-y +=3D err_ev6.o +obj-y +=3D err_ev6.o err_tsunami.o obj-y +=3D es1888.o smc37c669.o smc37c93x.o pc873xx.o gct.o obj-y +=3D srmcons.o =20 @@ -89,4 +89,6 @@ obj-$(CONFIG_ALPHA_MARVEL) +=3D err_ev7.o err_marvel.o obj-$(CONFIG_ALPHA_NAUTILUS) +=3D err_ev6.o obj-$(CONFIG_ALPHA_TITAN) +=3D err_ev6.o err_titan.o =20 +obj-$(CONFIG_ALPHA_TSUNAMI) +=3D err_tsunami.o + endif # GENERIC diff --git a/arch/alpha/kernel/core_tsunami.c b/arch/alpha/kernel/core_tsun= ami.c index fc1ab73f23de..d435ec9fb828 100644 --- a/arch/alpha/kernel/core_tsunami.c +++ b/arch/alpha/kernel/core_tsunami.c @@ -448,37 +448,3 @@ tsunami_kill_arch(int mode) if (TSUNAMI_cchip->csc.csr & 1L<<14) tsunami_kill_one_pchip(TSUNAMI_pchip1, 1); } - -static inline void -tsunami_pci_clr_err_1(tsunami_pchip *pchip) -{ - pchip->perror.csr; - pchip->perror.csr =3D 0x040; - mb(); - pchip->perror.csr; -} - -static inline void -tsunami_pci_clr_err(void) -{ - tsunami_pci_clr_err_1(TSUNAMI_pchip0); - - /* TSUNAMI and TYPHOON can have 2, but might only have 1 (DS10) */ - if (TSUNAMI_cchip->csc.csr & 1L<<14) - tsunami_pci_clr_err_1(TSUNAMI_pchip1); -} - -void -tsunami_machine_check(unsigned long vector, unsigned long la_ptr) -{ - /* Clear error before any reporting. */ - mb(); - mb(); /* magic */ - draina(); - tsunami_pci_clr_err(); - wrmces(0x7); - mb(); - - process_mcheck_info(vector, la_ptr, "TSUNAMI", - mcheck_expected(smp_processor_id())); -} diff --git a/arch/alpha/kernel/err_tsunami.c b/arch/alpha/kernel/err_tsunam= i.c new file mode 100644 index 000000000000..1045b920fa6b --- /dev/null +++ b/arch/alpha/kernel/err_tsunami.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Machine check handling for Tsunami/Typhoon systems. */ +#include +#include +#include +#include +#include +#include +#include +#include +#include "err_impl.h" +#include "proto.h" +#include "pci_impl.h" + +static inline void +tsunami_pci_clr_err_1(tsunami_pchip *pchip) +{ + pchip->perror.csr; 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Tue, 13 Oct 2026 14:16:00 -0700 (PDT) Received: from buildhost.darklands.se ([2001:9b1:ff:d701:51eb:176f:63d9:53f8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c355555f483sm256776766b.23.2026.10.13.14.16.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2026 14:16:00 -0700 (PDT) From: Magnus Lindholm To: richard.henderson@linaro.org, mattst88@gmail.com, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org Cc: linmag7@gmail.com Subject: [PATCH v7 2/5] alpha: describe the Tsunami system machine check frame Date: Tue, 13 Oct 2026 23:15:35 +0200 Message-ID: <20261013211551.991723-3-linmag7@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261013211551.991723-1-linmag7@gmail.com> References: <20261013211551.991723-1-linmag7@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define the five system-specific quadwords in the SRM logout frame, as documented in the AlphaServer ES40 Service Guide, Table D-19. Signed-off-by: Magnus Lindholm Reviewed-by: Matt Turner --- arch/alpha/include/asm/core_tsunami.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/alpha/include/asm/core_tsunami.h b/arch/alpha/include/asm= /core_tsunami.h index 3391e95754f2..fe3fd4570fac 100644 --- a/arch/alpha/include/asm/core_tsunami.h +++ b/arch/alpha/include/asm/core_tsunami.h @@ -283,6 +283,11 @@ union TPchipPERRMASK { * Data structure for handling TSUNAMI machine checks: */ struct el_TSUNAMI_sysdata_mcheck { + u64 sesf; + u64 dir; + u64 misc; + u64 p0_perror; + u64 p1_perror; }; =20 =20 --=20 2.43.0 From nobody Sat Oct 24 13:20:04 2026 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7B97542EFD for ; Tue, 13 Oct 2026 21:16:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.51 ARC-Seal: i=1; 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Tue, 13 Oct 2026 14:16:01 -0700 (PDT) Received: from buildhost.darklands.se ([2001:9b1:ff:d701:51eb:176f:63d9:53f8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c355555f483sm256776766b.23.2026.10.13.14.16.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2026 14:16:01 -0700 (PDT) From: Magnus Lindholm To: richard.henderson@linaro.org, mattst88@gmail.com, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org Cc: linmag7@gmail.com Subject: [PATCH v7 3/5] alpha: bound EV6 logout decoding by the processor area Date: Tue, 13 Oct 2026 23:15:36 +0200 Message-ID: <20261013211551.991723-4-linmag7@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261013211551.991723-1-linmag7@gmail.com> References: <20261013211551.991723-1-linmag7@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ES40 Service Guide, Table D-19, documents a correctable frame with its system area at 0x58 and total size 0x80. The existing EV6 decoder interprets system words as extended CPU registers and reads past its end. This establishes the layout for ES40; whether Titan and Nautilus PALcode also emits this short frame has not been verified. Validate the processor area before decoding it and only print extended registers when present. Preserve rejected frames with a raw dump rather than trusting their invalid offsets. Cap the dump at 1 KiB and round down to complete quadwords. This still relies on firmware supplying an accessible frame of its advertised size; the cap is not pointer validation. Signed-off-by: Magnus Lindholm Reviewed-by: Matt Turner --- arch/alpha/kernel/err_common.c | 13 ++++++++++++ arch/alpha/kernel/err_ev6.c | 38 +++++++++++++++++++++++++--------- arch/alpha/kernel/err_impl.h | 1 + 3 files changed, 42 insertions(+), 10 deletions(-) diff --git a/arch/alpha/kernel/err_common.c b/arch/alpha/kernel/err_common.c index 94e1b3dcf6d4..9271ea425a7b 100644 --- a/arch/alpha/kernel/err_common.c +++ b/arch/alpha/kernel/err_common.c @@ -44,6 +44,19 @@ mchk_dump_mem(void *data, size_t length, char **annotati= on) } } =20 +/* Preserve rejected frames without trusting their internal offsets. */ +void +mchk_dump_logout_frame_raw(struct el_common *header) +{ + size_t length =3D header->size; + + /* Bound diagnostic output and never read a partial final quadword. */ + if (length > 1024) + length =3D 1024; + length &=3D ~7UL; + mchk_dump_mem(header, length, NULL); +} + void mchk_dump_logout_frame(struct el_common *mchk_header) { diff --git a/arch/alpha/kernel/err_ev6.c b/arch/alpha/kernel/err_ev6.c index 8144f2045b5b..f12299ae1f24 100644 --- a/arch/alpha/kernel/err_ev6.c +++ b/arch/alpha/kernel/err_ev6.c @@ -190,6 +190,25 @@ ev6_process_logout_frame(struct el_common *mchk_header= , int print) (struct el_common_EV6_mcheck *)mchk_header; int status =3D MCHK_DISPOSITION_UNKNOWN_ERROR; =20 + /* + * ES40 correctable frames end the CPU area before EXC_ADDR (Table + * D-19). Validate both regions before decoding or dumping any data. + */ + if (mchk_header->proc_offset !=3D offsetof(struct el_common_EV6_mcheck, + I_STAT) || + mchk_header->sys_offset < offsetof(struct el_common_EV6_mcheck, + EXC_ADDR) || + mchk_header->sys_offset > mchk_header->size || + ((mchk_header->sys_offset | mchk_header->size) & 7)) { + if (print) { + printk("%s Invalid EV6 logout frame: size %x, CPU %x, system %x\n", + err_print_prefix, mchk_header->size, + mchk_header->proc_offset, mchk_header->sys_offset); + mchk_dump_logout_frame_raw(mchk_header); + } + return MCHK_DISPOSITION_UNKNOWN_ERROR; + } + status |=3D ev6_parse_ibox(ev6mchk->I_STAT, print); status |=3D ev6_parse_mbox(ev6mchk->MM_STAT, ev6mchk->DC_STAT,=20 ev6mchk->C_STAT, print); @@ -203,16 +222,15 @@ ev6_process_logout_frame(struct el_common *mchk_heade= r, int print) if (status !=3D MCHK_DISPOSITION_DISMISS) { char *saved_err_prefix =3D err_print_prefix; =20 - /* - * Dump some additional information from the frame - */ - printk("%s EXC_ADDR: 0x%016lx IER_CM: 0x%016lx" - " ISUM: 0x%016lx\n" - " PAL_BASE: 0x%016lx I_CTL: 0x%016lx" - " PCTX: 0x%016lx\n", - err_print_prefix, - ev6mchk->EXC_ADDR, ev6mchk->IER_CM, ev6mchk->ISUM, - ev6mchk->PAL_BASE, ev6mchk->I_CTL, ev6mchk->PCTX); + /* These registers are absent from short correctable frames. */ + if (mchk_header->sys_offset >=3D sizeof(*ev6mchk)) + printk("%s EXC_ADDR: 0x%016lx IER_CM: 0x%016lx" + " ISUM: 0x%016lx\n" + " PAL_BASE: 0x%016lx I_CTL: 0x%016lx" + " PCTX: 0x%016lx\n", + err_print_prefix, + ev6mchk->EXC_ADDR, ev6mchk->IER_CM, ev6mchk->ISUM, + ev6mchk->PAL_BASE, ev6mchk->I_CTL, ev6mchk->PCTX); =20 if (status =3D=3D MCHK_DISPOSITION_UNKNOWN_ERROR) { printk("%s UNKNOWN error, frame follows:\n", diff --git a/arch/alpha/kernel/err_impl.h b/arch/alpha/kernel/err_impl.h index 737b958a586d..5bef23a00942 100644 --- a/arch/alpha/kernel/err_impl.h +++ b/arch/alpha/kernel/err_impl.h @@ -47,6 +47,7 @@ struct el_subpacket_handler { extern char *err_print_prefix; =20 extern void mchk_dump_mem(void *, size_t, char **); +extern void mchk_dump_logout_frame_raw(struct el_common *header); extern void mchk_dump_logout_frame(struct el_common *); extern void el_print_timestamp(union el_timestamp *); extern void el_process_subpackets(struct el_subpacket *, int); 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Tue, 13 Oct 2026 14:16:02 -0700 (PDT) From: Magnus Lindholm To: richard.henderson@linaro.org, mattst88@gmail.com, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org Cc: linmag7@gmail.com Subject: [PATCH v7 4/5] alpha: decode and acknowledge Tsunami system machine checks Date: Tue, 13 Oct 2026 23:15:37 +0200 Message-ID: <20261013211551.991723-5-linmag7@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261013211551.991723-1-linmag7@gmail.com> References: <20261013211551.991723-1-linmag7@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Decode PCI and ECC transactions separately, honor invalid transaction information, and select Pchip errors using the logout summary. Report master aborts without importing Titan-specific dismissal policy. Delegate processor vectors to the bounded EV6 decoder. Capture live PERROR and MISC before acknowledging their defined W1C bits and report live status absent from the saved frame. Leave PERRMASK unchanged. HRM revision 4.0, Table 10-42 marks bit 9 reserved (MBZ/RAZ); remove the obsolete RTO definition and reserve its bitfield position. Use the system vector and frame bounds without restricting the reason code to the ES40 values. Preserve invalid frames and unknown environmental layouts in bounded raw dumps. Restore CPU register output for system errors, including the PC needed to diagnose NXM. For correctable system errors, gate the register dump on CONFIG_VERBOSE_MCHECK and alpha_verbose_mcheck while retaining the error decode. HRM 10.2.5.7 states that a cleared PERRMASK bit prevents the corresponding PERROR bit from being set, including by PERRSET. This does not establish firmware's mask value or clear a previously latched error. Leave firmware's mask untouched and report snapshots as live state, not proof of which transaction caused the current vector. Keep transaction information unavailable whenever SERR is set: HRM 8.8.2.6 gives no exception for SERR combined with another error. Follow Table 10-42's ECC interpretation for CRE/UECC and document that combined ECC/PCI bits do not reveal error ordering. Do not retain expected-probe handling: its only Tsunami writer is under the undefined NXM_MACHINE_CHECKS_ON_TSUNAMI. New fatal-error policy is defe= rred to a follow-up; reporting and acknowledgment do not establish recovery. Signed-off-by: Magnus Lindholm Reviewed-by: Matt Turner --- arch/alpha/include/asm/core_tsunami.h | 3 +- arch/alpha/kernel/Makefile | 2 +- arch/alpha/kernel/err_tsunami.c | 253 ++++++++++++++++++++++++-- 3 files changed, 237 insertions(+), 21 deletions(-) diff --git a/arch/alpha/include/asm/core_tsunami.h b/arch/alpha/include/asm= /core_tsunami.h index fe3fd4570fac..5c5d3ff849ed 100644 --- a/arch/alpha/include/asm/core_tsunami.h +++ b/arch/alpha/include/asm/core_tsunami.h @@ -105,7 +105,6 @@ extern int TSUNAMI_bootcpu; #define perror_m_ta 0x40 #define perror_m_rdpe 0x80 #define perror_m_nds 0x100 -#define perror_m_rto 0x200 #define perror_m_uecc 0x400 #define perror_m_cre 0x800 #define perror_m_addrl 0xFFFFFFFF0000UL @@ -123,7 +122,7 @@ union TPchipPERROR { unsigned perror_v_ta : 1; unsigned perror_v_rdpe : 1; unsigned perror_v_nds : 1; - unsigned perror_v_rto : 1; + unsigned perror_v_reserved : 1; /* PERROR<9>: MBZ, RAZ */ unsigned perror_v_uecc : 1; unsigned perror_v_cre : 1; =20 unsigned perror_v_rsvd1 : 4; diff --git a/arch/alpha/kernel/Makefile b/arch/alpha/kernel/Makefile index a453e487b9d0..0178f6a5bdb8 100644 --- a/arch/alpha/kernel/Makefile +++ b/arch/alpha/kernel/Makefile @@ -89,6 +89,6 @@ obj-$(CONFIG_ALPHA_MARVEL) +=3D err_ev7.o err_marvel.o obj-$(CONFIG_ALPHA_NAUTILUS) +=3D err_ev6.o obj-$(CONFIG_ALPHA_TITAN) +=3D err_ev6.o err_titan.o =20 -obj-$(CONFIG_ALPHA_TSUNAMI) +=3D err_tsunami.o +obj-$(CONFIG_ALPHA_TSUNAMI) +=3D err_ev6.o err_tsunami.o =20 endif # GENERIC diff --git a/arch/alpha/kernel/err_tsunami.c b/arch/alpha/kernel/err_tsunam= i.c index 1045b920fa6b..e89a11e567be 100644 --- a/arch/alpha/kernel/err_tsunami.c +++ b/arch/alpha/kernel/err_tsunami.c @@ -1,5 +1,10 @@ // SPDX-License-Identifier: GPL-2.0 -/* Machine check handling for Tsunami/Typhoon systems. */ +/* + * Machine check handling for Tsunami/Typhoon systems. + * Author: Magnus Lindholm + * Based on Titan error handling by Jeff Wiedemeier (Compaq). + * Register definitions: 21272 Hardware Reference Manual, revision 4.0. + */ #include #include #include @@ -12,36 +17,248 @@ #include "proto.h" #include "pci_impl.h" =20 -static inline void -tsunami_pci_clr_err_1(tsunami_pchip *pchip) +#define TSUNAMI_PERROR_ERRMASK 0xdffUL +#define TSUNAMI_PERROR_ECCMASK (perror_m_uecc | perror_m_cre) +#define TSUNAMI_PERROR_INV (1UL << 51) +#define TSUNAMI_MISC_NXM (1UL << 28) + +static int +tsunami_frame_valid(struct el_common *header, size_t size) { - pchip->perror.csr; - pchip->perror.csr =3D 0x040; + return !((header->sys_offset | header->size) & 7) && + header->sys_offset >=3D sizeof(*header) && + header->sys_offset <=3D header->size && + size <=3D header->size - header->sys_offset; +} + +static int +tsunami_parse_p_perror(int which, u64 perror, int print) +{ + static const char * const errors[] =3D { + "Lost error", "SERR asserted", "PERR asserted", + "Delayed-completion retry timeout", "Invalid scatter-gather PTE", + "Address parity error", "Target abort", "Read data parity error", + "No DEVSEL (master abort)", NULL, + "Uncorrectable ECC error", "Correctable ECC error" + }; + static const char * const pci_cmd[] =3D { + "Interrupt acknowledge", "Special cycle", "I/O read", "I/O write", + "Reserved", "Reserved", "Memory read", "Memory write", + "Reserved", "Reserved", "Configuration read", "Configuration write", + "Memory read multiple", "Dual address cycle", + "Memory read line", "Memory write and invalidate" + }; + unsigned long addr; + unsigned int cmd; + int i; + + if (!(perror & TSUNAMI_PERROR_ERRMASK)) + return MCHK_DISPOSITION_UNKNOWN_ERROR; + /* Do not import Titan's BIOS master-abort dismissal policy. */ + if (!print) + return MCHK_DISPOSITION_REPORT; + + printk("%s Pchip %d PERROR: %016llx\n", err_print_prefix, which, perror); + for (i =3D 0; i < ARRAY_SIZE(errors); i++) + if ((perror & TSUNAMI_PERROR_ERRMASK & (1UL << i)) && errors[i]) + printk("%s %s\n", err_print_prefix, errors[i]); + + /* + * INV invalidates SYN, CMD and ADDR. HRM 8.8.2.6 leaves command/address + * undefined whenever SERR is set, including with other error bits. + */ + if (perror & (TSUNAMI_PERROR_INV | perror_m_serr)) { + printk("%s Transaction information unavailable\n", err_print_prefix); + return MCHK_DISPOSITION_REPORT; + } + cmd =3D (perror & perror_m_cmd) >> 52; + /* + * Table 10-42 selects the ECC fields whenever CRE or UECC is set. + * Mixed ECC/PCI bits do not establish which error occurred first. + */ + if (perror & TSUNAMI_PERROR_ECCMASK) { + const char *command =3D "Reserved"; + + if (cmd =3D=3D 0) + command =3D "DMA read"; + else if (cmd =3D=3D 1) + command =3D "DMA RMW"; + else if (cmd =3D=3D 3) + command =3D "SGTE read"; + addr =3D ((perror >> 19) & 0xffffffffUL) << 3; + printk("%s Command: %s (%x), syndrome: %02llx\n", + err_print_prefix, command, cmd, (perror & perror_m_syn) >> 56); + printk("%s System address: %lx\n", err_print_prefix, addr); + } else { + addr =3D ((perror >> 18) & 0x3fffffffUL) << 2; + /* SGE captures only PCI address bits <31:13> (8KB page). */ + if (perror & perror_m_sge) + addr &=3D ~0x1fffUL; + printk("%s Command: %s (%x), PCI address: %lx%s\n", + err_print_prefix, pci_cmd[cmd], cmd, addr, + (perror & perror_m_sge) ? " (8KB page)" : ""); + if (perror & (1UL << 17)) + printk("%s Monster window\n", err_print_prefix); + else if (perror & (1UL << 16)) + printk("%s DAC scatter-gather window 3\n", err_print_prefix); + } + return MCHK_DISPOSITION_REPORT; +} + +/* SESF bits 0/1 identify PCI errors, bit 2 covers ECC on either Pchip/CPU= . */ +static u64 +tsunami_pchip_error(struct el_TSUNAMI_sysdata_mcheck *frame, int which) +{ + u64 perror =3D which ? frame->p1_perror : frame->p0_perror; + + if (frame->sesf & (1UL << which)) + return perror; + if ((frame->sesf & 4) && (perror & TSUNAMI_PERROR_ECCMASK)) + return perror; + return 0; +} + +static struct el_TSUNAMI_sysdata_mcheck * +tsunami_system_frame(struct el_common *header) +{ + if (!tsunami_frame_valid(header, sizeof(struct el_TSUNAMI_sysdata_mcheck)= )) + return NULL; + return (void *)header + header->sys_offset; +} + +static int +tsunami_process_logout_frame(struct el_common *header, int print) +{ + struct el_TSUNAMI_sysdata_mcheck *frame =3D tsunami_system_frame(header); + int status =3D MCHK_DISPOSITION_UNKNOWN_ERROR; + int i; + + if (!frame) { + if (print) { + printk("%s Invalid Tsunami system frame; raw frame follows\n", + err_print_prefix); + mchk_dump_logout_frame_raw(header); + } + return MCHK_DISPOSITION_UNKNOWN_ERROR; + } + if (print) + printk("%s SESF: %016llx DIR: %016llx MISC: %016llx\n", + err_print_prefix, frame->sesf, frame->dir, frame->misc); + if (frame->misc & TSUNAMI_MISC_NXM) { + status =3D MCHK_DISPOSITION_REPORT; + if (print) + printk("%s Non-existent memory, NXS: %llu\n", + err_print_prefix, (frame->misc >> 29) & 7); + } + for (i =3D 0; i < 2; i++) + status |=3D tsunami_parse_p_perror(i, tsunami_pchip_error(frame, i), pri= nt); + return status; +} + +struct tsunami_error_state { + u64 perror[2]; + u64 misc; +}; + +static void +tsunami_ack_pchip(tsunami_pchip *pchip, u64 perror) +{ + if (!(perror & TSUNAMI_PERROR_ERRMASK)) + return; + pchip->perror.csr =3D perror & TSUNAMI_PERROR_ERRMASK; + /* Complete the W1C write before releasing the logout frame. */ mb(); pchip->perror.csr; } =20 -static inline void -tsunami_pci_clr_err(void) +static void +tsunami_clear_errors(struct tsunami_error_state *state) { - tsunami_pci_clr_err_1(TSUNAMI_pchip0); + bool pchip1 =3D TSUNAMI_cchip->csc.csr & (1UL << 14); + + /* HRM 10.2.5.7: PERRMASK gates latching, not just notification. */ + + /* Preserve each chip's transaction and the NXM source before clearing. */ + state->perror[0] =3D TSUNAMI_pchip0->perror.csr; + state->perror[1] =3D pchip1 ? TSUNAMI_pchip1->perror.csr : 0; + state->misc =3D TSUNAMI_cchip->misc.csr; =20 - /* TSUNAMI and TYPHOON can have 2, but might only have 1 (DS10) */ - if (TSUNAMI_cchip->csc.csr & 1L<<14) - tsunami_pci_clr_err_1(TSUNAMI_pchip1); + tsunami_ack_pchip(TSUNAMI_pchip0, state->perror[0]); + /* Do not access the second Pchip on single-Pchip systems. */ + if (pchip1) + tsunami_ack_pchip(TSUNAMI_pchip1, state->perror[1]); + if (state->misc & TSUNAMI_MISC_NXM) { + /* Zero writes leave the other MISC fields unchanged. */ + TSUNAMI_cchip->misc.csr =3D TSUNAMI_MISC_NXM; + /* Complete the NXM acknowledgment before releasing the frame. */ + mb(); + TSUNAMI_cchip->misc.csr; + } +} + +static void +tsunami_report_live_errors(struct tsunami_error_state *state, + struct el_TSUNAMI_sysdata_mcheck *frame) +{ + int i; + + /* PALcode's frame may predate these errors, or describe another chip. */ + for (i =3D 0; i < 2; i++) { + if (!(state->perror[i] & TSUNAMI_PERROR_ERRMASK) || + (frame && state->perror[i] =3D=3D tsunami_pchip_error(frame, i))) + continue; + printk("%s Live Pchip status before acknowledgment:\n", err_print_prefi= x); + tsunami_parse_p_perror(i, state->perror[i], 1); + } + if ((state->misc & TSUNAMI_MISC_NXM) && + (!frame || ((state->misc ^ frame->misc) & (0xfUL << 28)))) + printk("%s Live MISC: %016llx, non-existent memory, NXS: %llu\n", + err_print_prefix, state->misc, (state->misc >> 29) & 7); } =20 void tsunami_machine_check(unsigned long vector, unsigned long la_ptr) { - /* Clear error before any reporting. */ + struct el_common *header =3D (void *)la_ptr; + struct el_TSUNAMI_sysdata_mcheck *frame =3D NULL; + struct tsunami_error_state live; + char *saved_err_prefix =3D err_print_prefix; + bool show_regs =3D vector =3D=3D SCB_Q_SYSMCHK; + + /* Synchronize pending accesses before inspecting the chipset. */ mb(); - mb(); /* magic */ - draina(); - tsunami_pci_clr_err(); - wrmces(0x7); mb(); + draina(); + tsunami_clear_errors(&live); + if (vector =3D=3D SCB_Q_SYSMCHK || vector =3D=3D SCB_Q_SYSERR) + frame =3D tsunami_system_frame(header); + +#ifdef CONFIG_VERBOSE_MCHECK + show_regs |=3D alpha_verbose_mcheck !=3D 0; +#endif + err_print_prefix =3D KERN_CRIT; + if (vector =3D=3D SCB_Q_SYSMCHK || vector =3D=3D SCB_Q_SYSERR) { + printk("%sSystem %s error (vector %lx, code %x) on CPU %d:\n", + err_print_prefix, vector =3D=3D SCB_Q_SYSERR ? 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Tue, 13 Oct 2026 14:16:03 -0700 (PDT) Received: from buildhost.darklands.se ([2001:9b1:ff:d701:51eb:176f:63d9:53f8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c355555f483sm256776766b.23.2026.10.13.14.16.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2026 14:16:03 -0700 (PDT) From: Magnus Lindholm To: richard.henderson@linaro.org, mattst88@gmail.com, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org Cc: linmag7@gmail.com Subject: [PATCH v7 5/5] alpha: decode Clipper environmental events and retain console logs Date: Tue, 13 Oct 2026 23:15:38 +0200 Message-ID: <20261013211551.991723-6-linmag7@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261013211551.991723-1-linmag7@gmail.com> References: <20261013211551.991723-1-linmag7@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Restrict ES40 live environmental decoding to Clipper. Honor print control, validate bounds and masks, and separate fault bits from status context. Report valid notifications even when no recognized fault bits are set, so door-closed and supply-return notifications are not silently discarded. Do not infer a recovery transition from a single status snapshot. Keep SMIR bit 0 and inverted halt/reset bits as raw context. During the ES40 PSU cable test, bit 0 remained set after the individual PSU failure indication cleared. Its polarity/latching is unverified, so do not call it a current PSU failure. Use mask 0x14 for the remaining SMIR faults. Remove the redundant silent first pass now that every valid environmental notification is reported. Include the CPU ID for processor console frames. Use plain door-status messages without the manual's "Set =3D" prefix. Dump unknown or truncated environmental frames raw. Register bounded console decoders from the error file, but keep the PCI init hook and console-log invocation in sys_dp264.c, as Titan does. Limit console-log scanning to Clipper pending older-board firmware tests. The ES40 boot and QEMU Clipper test do not establish that nonempty console logs are safe on DS10, DS20 or XP1000 firmware. Print console environmental packets raw: ES40 Table D-18's sys_offset conflicts with its field offsets. Actual SRM records are still needed. Terminate annotation arrays and reject invalid packet bounds/revisions. Use a Clipper-only console scanner bounded by the HWRPB log length. Check wrapper fields and each child extent before decoding; reject unsupported wrappers, including the class-5/type-4 record seen on ES40. Retain the firmware log pointer if parsing is incomplete, and print up to 1 KiB of raw bytes without reading beyond the supplied log length. Only acknowledge a log after reaching a complete termination packet. The generic scanner otherwise clears the pointer even on parse failure. Signed-off-by: Magnus Lindholm --- arch/alpha/include/asm/err_common.h | 2 + arch/alpha/kernel/err_tsunami.c | 460 ++++++++++++++++++++++++++++ arch/alpha/kernel/proto.h | 3 + arch/alpha/kernel/sys_dp264.c | 5 +- 4 files changed, 469 insertions(+), 1 deletion(-) diff --git a/arch/alpha/include/asm/err_common.h b/arch/alpha/include/asm/e= rr_common.h index 610e01fe73ab..63d4320581e2 100644 --- a/arch/alpha/include/asm/err_common.h +++ b/arch/alpha/include/asm/err_common.h @@ -47,6 +47,8 @@ # define EL_TYPE__REGATTA__PROCESSOR_ERROR_FRAME (1) # define EL_TYPE__REGATTA__SYSTEM_ERROR_FRAME (2) # define EL_TYPE__REGATTA__ENVIRONMENTAL_FRAME (3) +# define EL_TYPE__REGATTA__TSUNAMI_PCHIP0_EXTENDED (6) +# define EL_TYPE__REGATTA__TSUNAMI_PCHIP1_EXTENDED (7) # define EL_TYPE__REGATTA__TITAN_PCHIP0_EXTENDED (8) # define EL_TYPE__REGATTA__TITAN_PCHIP1_EXTENDED (9) # define EL_TYPE__REGATTA__TITAN_MEMORY_EXTENDED (10) diff --git a/arch/alpha/kernel/err_tsunami.c b/arch/alpha/kernel/err_tsunam= i.c index e89a11e567be..f7989008c270 100644 --- a/arch/alpha/kernel/err_tsunami.c +++ b/arch/alpha/kernel/err_tsunami.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -262,3 +263,462 @@ tsunami_machine_check(unsigned long vector, unsigned = long la_ptr) mb(); } } + +static const char * const CLIPPER_EnvQW1SMIR[] =3D { + "", /* SMIR<0>: retain as raw context until its semantics are known. */ + "OCP or RMC halt detected", + "Sys_DC_Notok failure detected", + "", + "System temperature over 50 degrees C failure", + "PCI Bus #0 is in reset", + "PCI Bus #1 is in reset", + "System is being reset" +}; + +static const char * const CLIPPER_EnvQW2CPUIR[] =3D { + "CPU0 regulator is enabled", + "CPU1 regulator is enabled", + "CPU2 regulator is enabled", + "CPU3 regulator is enabled", + "CPU0 regulator or configuration sequence fail", + "CPU1 regulator or configuration sequence fail", + "CPU2 regulator or configuration sequence fail", + "CPU3 regulator or configuration sequence fail" +}; + +static const char * const CLIPPER_EnvQW3PSIR[] =3D { + "Power Supply 0 is enabled", + "Power Supply 1 is enabled", + "Power Supply 2 is enabled", + "", + "Power Supply 0 was enabled but failed", + "Power Supply 1 was enabled but failed", + "Power Supply 2 was enabled but failed" +}; + +static const char * const CLIPPER_EnvQW4LM78ISR[] =3D { + "PS +3.3V out of tolerance", + "PS +5V out of tolerance", + "PS +12V out of tolerance", + "VTERM out of tolerance", + "Temperature zone 0 (PCI Backplane slots 1-3 area) over limit failure", + "LM75 CPU0-3 Temperature over limit failure", + "System Fan 1 failure", + "System Fan 2 failure", + "CTERM out of tolerance", + "", + "-12V out of tolerance", + "", + "", + "", + "", + "", + "CPU0_VCORE +2V out of tolerance", + "CPU0_VIO +1.5V out of tolerance", + "CPU1_VCORE +2V out of tolerance", + "CPU1_VIO +1.5V out of tolerance", + "Temperature zone 1 (PCI Backplane slots 7-10 area) over limit failure", + "", + "System Fan 4 failure", + "System Fan 5 failure", + "", + "", + "", + "", + "", + "", + "", + "", + "CPU2_VCORE +2V out of tolerance", + "CPU2_VIO +1.5V out of tolerance", + "CPU3_VCORE +2V out of tolerance", + "CPU3_VIO +1.5V out of tolerance", + "Temperature zone 2 (PCI Backplane slots 4-6 area) over limit failure", + "", + "System Fan 3 failure", + "System Fan 6 failure", + "", + "", + "Power supply 3.3V rail above high amperage warning", + "Power supply 5.0V rail above high amperage warning", + "Power supply 12V rail above high amperage warning", + "Power supply high temperature warning", + "Power supply AC input low limit warning", + "Power supply AC input high limit warning" +}; + +static const char * const CLIPPER_EnvQW5DOOR[] =3D { + "", + "System CPU door is open", + "System Fan door is open", + "System PCI door is open", + "", + "System CPU door is closed", + "System Fan door is closed", + "System PCI door is closed" +}; + +static const char * const CLIPPER_EnvQW6TEMP[] =3D { + "CPU0 temperature warning fault has occurred", + "CPU1 temperature warning fault has occurred", + "CPU2 temperature warning fault has occurred", + "CPU3 temperature warning fault has occurred", + "System temperature zone 0 warning fault has occurred", + "System temperature zone 1 warning fault has occurred", + "System temperature zone 2 warning fault has occurred" +}; + +static const char * const CLIPPER_EnvQW7FAN[] =3D { + "System Fan 1 is not responding to RMC Commands", + "System Fan 2 is not responding to RMC Commands", + "System Fan 3 is not responding to RMC Commands", + "System Fan 4 is not responding to RMC Commands", + "System Fan 5 is not responding to RMC Commands", + "System Fan 6 is not responding to RMC Commands", + "", + "", + "CPU fans 5/6 at maximum speed", + "CPU fans 5/6 reduced speed from maximum", + "PCI fans 1-4 at maximum speed", + "PCI fans 1-4 reduced speed from maximum" +}; + +#define CLIPPER_ENV_LM78ISR_MASK 0xfcdf00df05ffUL + +static char *el_tsunami_pchip0_extended_annotation[] =3D { +"Subpacket Header", "P0_PCTL", "P0_PERRMASK", +"P0_WSBA0", "P0_WSBA1", "P0_WSBA2", "P0_WSBA3", +"P0_WSM0", "P0_WSM1", "P0_WSM2", "P0_WSM3", +"P0_TBA0", "P0_TBA1", "P0_TBA2", "P0_TBA3", NULL +}; + +static char *el_tsunami_pchip1_extended_annotation[] =3D { +"Subpacket Header", "P1_PCTL", "P1_PERRMASK", +"P1_WSBA0", "P1_WSBA1", "P1_WSBA2", "P1_WSBA3", +"P1_WSM0", "P1_WSM1", "P1_WSM2", "P1_WSM3", +"P1_TBA0", "P1_TBA1", "P1_TBA2", "P1_TBA3", NULL +}; + + +static struct el_subpacket_annotation el_tsunami_annotations[] =3D { + SUBPACKET_ANNOTATION(EL_CLASS__REGATTA_FAMILY, + EL_TYPE__REGATTA__TSUNAMI_PCHIP0_EXTENDED, + 1, + "Tsunami PChip 0 Extended Frame", + el_tsunami_pchip0_extended_annotation), + SUBPACKET_ANNOTATION(EL_CLASS__REGATTA_FAMILY, + EL_TYPE__REGATTA__TSUNAMI_PCHIP1_EXTENDED, + 1, + "Tsunami PChip 1 Extended Frame", + el_tsunami_pchip1_extended_annotation), + SUBPACKET_ANNOTATION(EL_CLASS__REGATTA_FAMILY, + EL_TYPE__TERMINATION__TERMINATION, + 1, + "Termination Subpacket", + NULL) +}; + +/* ES40 Service Guide EK-ES240-SV A01, live frame: Tables D-20 and D-21. */ +struct el_clipper_envdata { + u64 summary; + u64 dir; + u64 smir; + u64 cpuir; + u64 psir; + u64 fault; + u64 doors; + u64 temp_warn; + u64 fan_ctrl; + u64 fatal_power_down; + u64 reserved; +}; + +static int +clipper_print_bits(const char * const *messages, size_t count, + u64 value, u64 mask, int print) +{ + size_t i; + + if (!(value & mask)) + return MCHK_DISPOSITION_DISMISS; + if (print) + for (i =3D 0; i < count; i++) + if (value & mask & (1UL << i)) + printk("%s %s\n", err_print_prefix, messages[i]); + return MCHK_DISPOSITION_REPORT; +} + +#define CLIPPER_BITS(table, value, mask) \ + clipper_print_bits(table, ARRAY_SIZE(table), value, mask, print) + +static int +clipper_process_environment(struct el_common *header, int print) +{ + struct el_clipper_envdata *frame; + int status =3D 0; + + if (!tsunami_frame_valid(header, sizeof(*frame))) { + if (print) { + printk("%s Truncated Clipper environmental frame\n", err_print_prefix); + mchk_dump_logout_frame_raw(header); + } + return MCHK_DISPOSITION_UNKNOWN_ERROR; + } + frame =3D (void *)header + header->sys_offset; + /* Only QW1 through QW7 carry error state in the live 680 frame. */ + /* PSU summary and inverted halt/reset signals remain raw context. */ + status |=3D CLIPPER_BITS(CLIPPER_EnvQW1SMIR, frame->smir, 0x14); + status |=3D CLIPPER_BITS(CLIPPER_EnvQW2CPUIR, frame->cpuir, 0xf0); + status |=3D CLIPPER_BITS(CLIPPER_EnvQW3PSIR, frame->psir, 0x70); + status |=3D CLIPPER_BITS(CLIPPER_EnvQW4LM78ISR, + frame->fault, CLIPPER_ENV_LM78ISR_MASK); + status |=3D CLIPPER_BITS(CLIPPER_EnvQW5DOOR, frame->doors, 0x0e); + status |=3D CLIPPER_BITS(CLIPPER_EnvQW6TEMP, frame->temp_warn, 0x7f); + status |=3D CLIPPER_BITS(CLIPPER_EnvQW7FAN, frame->fan_ctrl, 0x3f); + /* A notification with no recognized fault can describe recovery. */ + if (print && !(status & MCHK_DISPOSITION_REPORT)) + printk("%s No recognized environmental fault bits set\n", + err_print_prefix); + if (print) { + printk("%s Environmental summary: %016llx DIR: %016llx\n", + err_print_prefix, frame->summary, frame->dir); + printk("%s SMIR: %016llx (PSU summary/halt/reset bits undecoded)\n", + err_print_prefix, frame->smir); + CLIPPER_BITS(CLIPPER_EnvQW2CPUIR, frame->cpuir, 0x0f); + CLIPPER_BITS(CLIPPER_EnvQW3PSIR, frame->psir, 0x07); + CLIPPER_BITS(CLIPPER_EnvQW5DOOR, frame->doors, 0xe0); + CLIPPER_BITS(CLIPPER_EnvQW7FAN, frame->fan_ctrl, 0xf00); + if (frame->fault & (0x3fUL << 42)) + printk("%s Power supply warning source: %llu (3 =3D reserved)\n", + err_print_prefix, (frame->fault >> 40) & 3); + } + return MCHK_DISPOSITION_REPORT; +} + +void +clipper_machine_check(unsigned long vector, unsigned long la_ptr) +{ + struct el_common *header =3D (void *)la_ptr; + char *saved_err_prefix =3D err_print_prefix; + + if (vector !=3D SCB_Q_SYSEVENT) { + tsunami_machine_check(vector, la_ptr); + return; + } + /* Drain pending accesses before inspecting the environmental frame. */ + mb(); + draina(); + err_print_prefix =3D KERN_CRIT; + printk("%sSystem correctable environmental event (code %x) on CPU %d:\n", + err_print_prefix, header->code, smp_processor_id()); + if (header->code =3D=3D 0x206) + clipper_process_environment(header, 1); + else { + printk("%s Unrecognized environmental event; raw frame follows\n", + err_print_prefix); + mchk_dump_logout_frame_raw(header); + } + err_print_prefix =3D saved_err_prefix; + wrmces(0x7); + /* Complete acknowledgment before returning from the event. */ + mb(); +} + +static struct el_subpacket * +tsunami_process_subpacket(struct el_subpacket *packet) +{ + struct el_common *frame; + size_t offset =3D offsetof(struct el_subpacket, by_type.regatta_frame.dat= a_start); + int status; + + /* Raw dumps consume whole quadwords, and the next packet must advance. */ + if (packet->length < offsetof(struct el_subpacket, by_type) || + (packet->length & 7)) + return NULL; + if (packet->revision !=3D 1) { + el_annotate_subpacket(packet); + return (void *)packet + packet->length; + } + + switch (packet->type) { + case EL_TYPE__REGATTA__PROCESSOR_ERROR_FRAME: + case EL_TYPE__REGATTA__PROCESSOR_DBL_ERROR_HALT: + case EL_TYPE__REGATTA__SYSTEM_ERROR_FRAME: + case EL_TYPE__REGATTA__SYSTEM_DBL_ERROR_HALT: + if (packet->length < offset + sizeof(*frame)) + return NULL; + frame =3D (void *)packet + offset; + if (frame->size > packet->length - offset || frame->size < sizeof(*frame= )) + return NULL; + if (packet->type =3D=3D EL_TYPE__REGATTA__PROCESSOR_ERROR_FRAME || + packet->type =3D=3D EL_TYPE__REGATTA__PROCESSOR_DBL_ERROR_HALT) { + printk("%s ** Occurred on CPU %d:\n", err_print_prefix, + (int)packet->by_type.regatta_frame.cpuid); + status =3D ev6_process_logout_frame(frame, 0); + if (status !=3D MCHK_DISPOSITION_DISMISS) + ev6_process_logout_frame(frame, 1); + } else { + tsunami_process_logout_frame(frame, 1); + } + break; + case EL_TYPE__REGATTA__ENVIRONMENTAL_FRAME: + /* + * ES40 Table D-18 gives sys_offset=3D0x20, but places the + * summary at frame+0x18. Preserve the complete packet until + * the console layout is verified; do not apply the live layout. + */ + printk("%s Console environmental layout unverified; raw packet follows\= n", + err_print_prefix); + el_annotate_subpacket(packet); + break; + default: + el_annotate_subpacket(packet); + break; + } + return (void *)packet + packet->length; +} + +/* + * Clipper console logs have an HWRPB byte count. Do not use the generic + * unbounded dispatcher: a rejected record must not acknowledge the log. + */ +static bool +tsunami_console_log(void *data, size_t remaining) +{ + struct el_subpacket *packet; + unsigned char *pos =3D data; + size_t size, length; + u32 count; + + while (remaining >=3D offsetof(struct el_subpacket, by_type)) { + packet =3D (void *)pos; + size =3D packet->length; + if (size < offsetof(struct el_subpacket, by_type) || + size > remaining || (size & 7)) + return false; + if (packet->class =3D=3D EL_CLASS__TERMINATION) + return packet->type =3D=3D EL_TYPE__TERMINATION__TERMINATION; + if (packet->class !=3D EL_CLASS__HEADER || packet->revision !=3D 1) + return false; + + /* Check each header's extent before accessing its union member. */ +#define CONSOLE_HEADER_SIZE(member) \ + (offsetof(struct el_subpacket, by_type.member) + \ + sizeof(packet->by_type.member)) + switch (packet->type) { + case EL_TYPE__HEADER__SYSTEM_ERROR_FRAME: + if (size < CONSOLE_HEADER_SIZE(sys_err)) + return false; + length =3D packet->by_type.sys_err.frame_length; + count =3D packet->by_type.sys_err.frame_packet_count; + break; + case EL_TYPE__HEADER__SYSTEM_EVENT_FRAME: + if (size < CONSOLE_HEADER_SIZE(sys_event)) + return false; + length =3D packet->by_type.sys_event.frame_length; + count =3D packet->by_type.sys_event.frame_packet_count; + break; + case EL_TYPE__HEADER__HALT_FRAME: + if (size < CONSOLE_HEADER_SIZE(err_halt)) + return false; + length =3D packet->by_type.err_halt.frame_length; + count =3D packet->by_type.err_halt.frame_packet_count; + break; + case EL_TYPE__HEADER__LOGOUT_FRAME: + if (size < CONSOLE_HEADER_SIZE(logout_header)) + return false; + length =3D packet->by_type.logout_header.frame_length; + count =3D 1; + break; + default: + return false; + } +#undef CONSOLE_HEADER_SIZE + if (length > remaining - size || (length & 7) || + count > length / offsetof(struct el_subpacket, by_type)) + return false; + pos +=3D size; + remaining -=3D size + length; + while (count--) { + if (length < offsetof(struct el_subpacket, by_type)) + return false; + packet =3D (void *)pos; + size =3D packet->length; + if (size < offsetof(struct el_subpacket, by_type) || + size > length || (size & 7) || + packet->class !=3D EL_CLASS__REGATTA_FAMILY) + return false; + /* This handler checks embedded logout-frame bounds. */ + if (tsunami_process_subpacket(packet) !=3D (void *)pos + size) + return false; + pos +=3D size; + length -=3D size; + } + if (length) + return false; + } + /* Exhaustion without a complete termination packet is incomplete. */ + return false; +} + +static void +tsunami_console_data_log(int cpu, struct percpu_struct *pcpu) +{ + unsigned char *data =3D (void *)(IDENT_ADDR | pcpu->console_data_log_pa); + size_t length =3D pcpu->console_data_log_length; + size_t dump =3D length < 1024 ? length : 1024; + size_t i; + + printk("%sConsole data log for CPU %d (%zu bytes):\n", + err_print_prefix, cpu, length); + if (!(pcpu->console_data_log_pa & 7) && + length <=3D ~0UL - (unsigned long)data && + tsunami_console_log(data, length)) { + /* Acknowledge only after reaching a valid termination packet. */ + pcpu->console_data_log_pa =3D 0; + return; + } + printk("%s Incomplete console log; retaining firmware pointer\n", + err_print_prefix); + /* Byte reads preserve partial headers without rounding beyond length. */ + if (dump > ~0UL - (unsigned long)data) + return; + for (i =3D 0; i < dump; i++) { + if (!(i & 15)) + printk("%s %04zx:", err_print_prefix, i); + printk(KERN_CONT " %02x", data[i]); + if ((i & 15) =3D=3D 15 || i + 1 =3D=3D dump) + printk(KERN_CONT "\n"); + } + if (dump < length) + printk("%s Raw console log truncated to %zu bytes\n", + err_print_prefix, dump); +} + +void __init +tsunami_check_console_data_log(void) +{ + struct percpu_struct *pcpu; + unsigned long cpu; + + for (cpu =3D 0; cpu < hwrpb->nr_processors; cpu++) { + pcpu =3D (void *)hwrpb + hwrpb->processor_offset + + cpu * hwrpb->processor_size; + if (pcpu->console_data_log_pa) + tsunami_console_data_log(cpu, pcpu); + } +} + +static struct el_subpacket_handler tsunami_subpacket_handler =3D + SUBPACKET_HANDLER_INIT(EL_CLASS__REGATTA_FAMILY, tsunami_process_subpacke= t); + +void __init +tsunami_register_error_handlers(void) +{ + size_t i; + + for (i =3D 0; i < ARRAY_SIZE(el_tsunami_annotations); i++) + cdl_register_subpacket_annotation(&el_tsunami_annotations[i]); + cdl_register_subpacket_handler(&tsunami_subpacket_handler); + ev6_register_error_handlers(); +} diff --git a/arch/alpha/kernel/proto.h b/arch/alpha/kernel/proto.h index f138bd494628..a704acd7da6a 100644 --- a/arch/alpha/kernel/proto.h +++ b/arch/alpha/kernel/proto.h @@ -78,6 +78,9 @@ extern struct _alpha_agp_info *titan_agp_info(void); extern struct pci_ops tsunami_pci_ops; extern void tsunami_init_arch(void); extern void tsunami_kill_arch(int); +extern void tsunami_register_error_handlers(void); +extern void tsunami_check_console_data_log(void); +extern void clipper_machine_check(unsigned long vector, unsigned long la_p= tr); extern void tsunami_machine_check(unsigned long vector, unsigned long la_p= tr); extern void tsunami_pci_tbi(struct pci_controller *, dma_addr_t, dma_addr_= t); =20 diff --git a/arch/alpha/kernel/sys_dp264.c b/arch/alpha/kernel/sys_dp264.c index 0a2d319bb1c8..614e989a7849 100644 --- a/arch/alpha/kernel/sys_dp264.c +++ b/arch/alpha/kernel/sys_dp264.c @@ -32,6 +32,7 @@ =20 #include "proto.h" #include "irq_impl.h" +#include "err_impl.h" #include "pci_impl.h" #include "machvec_impl.h" =20 @@ -533,6 +534,8 @@ monet_init_pci(void) static void __init clipper_init_pci(void) { + tsunami_register_error_handlers(); + tsunami_check_console_data_log(); common_init_pci(); locate_and_init_vga(NULL); } @@ -627,7 +630,7 @@ struct alpha_machine_vector clipper_mv __initmv =3D { DO_EV6_MMU, DO_DEFAULT_RTC, DO_TSUNAMI_IO, - .machine_check =3D tsunami_machine_check, + .machine_check =3D clipper_machine_check, .max_isa_dma_address =3D ALPHA_MAX_ISA_DMA_ADDRESS, .min_io_address =3D DEFAULT_IO_BASE, .min_mem_address =3D DEFAULT_MEM_BASE, --=20 2.43.0