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[2a02:3100:a189:2701:8c58:155a:279:7389]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1b481b7f8sm5237345e9.3.2026.10.13.13.31.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 13 Oct 2026 13:31:52 -0700 (PDT) From: Karl Mehltretter To: Russell King , Miguel Ojeda Cc: Karl Mehltretter , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Daniel Almeida , Tamir Duberstein , Alexandre Courbot , =?UTF-8?q?Onur=20=C3=96zkan?= , Arnd Bergmann , Linus Walleij , Christian Schrefl , Bradley Morgan , "Paul E . McKenney" , Peter Zijlstra , FUJITA Tomonori , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , linux-arm-kernel@lists.infradead.org, rust-for-linux@vger.kernel.org, llvm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/6] ARM: cmpxchg: always inline __arch_xchg() and __cmpxchg() Date: Tue, 13 Oct 2026 22:31:35 +0200 Message-Id: <20261013203140.31741-2-kmehltretter@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20261013203140.31741-1-kmehltretter@gmail.com> References: <20261013203140.31741-1-kmehltretter@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" __arch_xchg(), __cmpxchg() and __cmpxchg_local() rely on inlining to remove their undefined-function calls for unsupported sizes. With gcc 8.1.0 and CC_OPTIMIZE_FOR_SIZE, bcm2835_defconfig with RUST=3Dy fails to link. The compiler emits out-of-line copies for the many callers in rust/helpers/helpers.c, retaining those calls: helpers.c:(.text+0x424): undefined reference to `__bad_xchg' helpers.c:(.text+0x4ac): undefined reference to `__bad_cmpxchg' Mark the functions __always_inline so the compiler can remove the unsupported-size path for each caller's constant size. Fixes: ab717dd98bee ("rust: helpers: Add i8/i16 atomic xchg_acquire helpers= ") Fixes: ac8f06ade38a ("rust: sync: atomic: Add Atomic<*{mut,const} T> suppor= t") Cc: stable@vger.kernel.org Reviewed-by: Bradley Morgan Reviewed-by: Gary Guo Assisted-by: LLM Signed-off-by: Karl Mehltretter --- arch/arm/include/asm/cmpxchg.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h index 9beb64d30586..0ce5225af442 100644 --- a/arch/arm/include/asm/cmpxchg.h +++ b/arch/arm/include/asm/cmpxchg.h @@ -26,7 +26,7 @@ #define swp_is_buggy #endif =20 -static inline unsigned long +static __always_inline unsigned long __arch_xchg(unsigned long x, volatile void *ptr, int size) { extern void __bad_xchg(volatile void *, int); @@ -155,8 +155,8 @@ extern void __bad_cmpxchg(volatile void *ptr, int size); * cmpxchg only support 32-bits operands on ARMv6. */ =20 -static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long ol= d, - unsigned long new, int size) +static __always_inline unsigned long +__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int si= ze) { unsigned long oldval, res; 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[2a02:3100:a189:2701:8c58:155a:279:7389]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1b481b7f8sm5237345e9.3.2026.10.13.13.31.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 13 Oct 2026 13:31:58 -0700 (PDT) From: Karl Mehltretter To: Russell King , Miguel Ojeda Cc: Karl Mehltretter , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Daniel Almeida , Tamir Duberstein , Alexandre Courbot , =?UTF-8?q?Onur=20=C3=96zkan?= , Arnd Bergmann , Linus Walleij , Christian Schrefl , Bradley Morgan , "Paul E . McKenney" , Peter Zijlstra , FUJITA Tomonori , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , linux-arm-kernel@lists.infradead.org, rust-for-linux@vger.kernel.org, llvm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/6] ARM: cmpxchg: support 2-byte xchg() on pre-ARMv6 CPUs Date: Tue, 13 Oct 2026 22:31:36 +0200 Message-Id: <20261013203140.31741-3-kmehltretter@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20261013203140.31741-1-kmehltretter@gmail.com> References: <20261013203140.31741-1-kmehltretter@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Pre-ARMv6 CPUs have no halfword swp, so __arch_xchg() only handles 1- and 4-byte exchanges there and turns any other size into a link error via __bad_xchg(). No C code needs a 16-bit xchg() on these CPUs, but the Rust atomic helpers in rust/helpers/atomic_ext.c provide xchg() for Atomic unconditionally, so building with CONFIG_RUST=3Dy for ARMv5 fails: ld.lld: error: undefined symbol: __bad_xchg >>> referenced by helpers.c >>> rust/helpers/helpers.o:(rust_helper_atomic_i16_xchg) Implement the 2-byte case with interrupts disabled, as the pre-ARMv6 atomic_t operations already do. This is safe because a kernel built for ARMv5 or older is never SMP. ARMv6 before ARMv6K (ARM1136r0) has no 16-bit exclusive access either. It is not handled here. Rust stays disabled for those kernels, and they cannot be SMP since commit d70242427110 ("ARM: rework ARM11 CPU selection logic"). Acked-by: Arnd Bergmann Reviewed-by: Linus Walleij Reviewed-by: Bradley Morgan Assisted-by: LLM Signed-off-by: Karl Mehltretter --- arch/arm/include/asm/cmpxchg.h | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h index 0ce5225af442..18555ae22893 100644 --- a/arch/arm/include/asm/cmpxchg.h +++ b/arch/arm/include/asm/cmpxchg.h @@ -31,11 +31,10 @@ __arch_xchg(unsigned long x, volatile void *ptr, int si= ze) { extern void __bad_xchg(volatile void *, int); unsigned long ret; -#ifdef swp_is_buggy - unsigned long flags; -#endif #if __LINUX_ARM_ARCH__ >=3D 6 unsigned int tmp; +#else + unsigned long flags; #endif =20 prefetchw((const void *)ptr); @@ -106,6 +105,15 @@ __arch_xchg(unsigned long x, volatile void *ptr, int s= ize) : "r" (x), "r" (ptr) : "memory", "cc"); break; +#endif +#if __LINUX_ARM_ARCH__ < 6 + case 2: + /* swp has no halfword form. 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[2a02:3100:a189:2701:8c58:155a:279:7389]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1b481b7f8sm5237345e9.3.2026.10.13.13.31.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 13 Oct 2026 13:32:00 -0700 (PDT) From: Karl Mehltretter To: Russell King , Miguel Ojeda Cc: Karl Mehltretter , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Daniel Almeida , Tamir Duberstein , Alexandre Courbot , =?UTF-8?q?Onur=20=C3=96zkan?= , Arnd Bergmann , Linus Walleij , Christian Schrefl , Bradley Morgan , "Paul E . McKenney" , Peter Zijlstra , FUJITA Tomonori , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , linux-arm-kernel@lists.infradead.org, rust-for-linux@vger.kernel.org, llvm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/6] ARM: rust: Enable Rust support for ARMv6K-only kernels Date: Tue, 13 Oct 2026 22:31:37 +0200 Message-Id: <20261013203140.31741-4-kmehltretter@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20261013203140.31741-1-kmehltretter@gmail.com> References: <20261013203140.31741-1-kmehltretter@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" HAVE_RUST currently requires CPU_32v7, excluding ARMv6K-only kernels even though arm-unknown-linux-gnueabi already builds ARMv6 code. Select HAVE_RUST for CPU_32v6K. CPU_V7 selects CPU_32v6K, so ARMv7 remains covered. Keep plain ARMv6 (CPU_V6, ARM1136r0) excluded. It lacks 1- and 2-byte xchg() and 2-byte cmpxchg(), which the Rust atomic helpers need. The old condition exposes Rust on combined CPU_V6 and ARMv7 kernels, which do not link. Tested the Rust samples, KUnit suites and doctests in QEMU raspi0 (ARM1176) with bcm2835_defconfig without ARCH_MULTI_V7. Assisted-by: LLM Signed-off-by: Karl Mehltretter --- Tested the full six-patch series on a Raspberry Pi 1 Model B+ Rev 1.2 (ARM1176JZF-S), with bcm2835_defconfig without ARCH_MULTI_V7, clang 22.1.8, rustc 1.99.0 and bindgen 0.73.2. All 368 doctests and the Rust KUnit suites passed. The intentionally disabled KUnit selftest was skipped. Ten Rust modules loaded and unloaded. Misc ioctls, configfs, scoped debugfs and rnull read/write checks passed. No warnings or oopses in the test kernel. Documentation/rust/arch-support.rst | 2 +- arch/arm/Kconfig | 2 +- rust/helpers/atomic_ext.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/rust/arch-support.rst b/Documentation/rust/arch-= support.rst index 4f980815e92a..bdc42a24bf30 100644 --- a/Documentation/rust/arch-support.rst +++ b/Documentation/rust/arch-support.rst @@ -15,7 +15,7 @@ support corresponds to ``S`` values in the ``MAINTAINERS`= ` file. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D Architecture Level of support Constraints =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D -``arm`` Maintained ARMv7 Little Endian only. +``arm`` Maintained ARMv6K and ARMv7, Little Endian only. ``arm64`` Maintained Little Endian only. ``loongarch`` Maintained \- ``riscv`` Maintained ``riscv64`` and LLVM/Clang only. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ffbc7f386131..b5816f28783a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -138,7 +138,7 @@ config ARM select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_RSEQ - select HAVE_RUST if CPU_LITTLE_ENDIAN && CPU_32v7 && !KASAN + select HAVE_RUST if CPU_LITTLE_ENDIAN && CPU_32v6K && !CPU_V6 && !KASAN select HAVE_STACKPROTECTOR select HAVE_SYSCALL_TRACEPOINTS select HAVE_UID16 diff --git a/rust/helpers/atomic_ext.c b/rust/helpers/atomic_ext.c index c267d5190529..1d157df29229 100644 --- a/rust/helpers/atomic_ext.c +++ b/rust/helpers/atomic_ext.c @@ -42,7 +42,7 @@ GEN_READ_SET_HELPERS(ptr, const void *) * xchg helpers depend on ARCH_SUPPORTS_ATOMIC_RMW and on the * architecture provding xchg() support for i8 and i16. * - * The architectures that currently support Rust (x86_64, armv7, + * The architectures that currently support Rust (x86_64, arm, * arm64, riscv, and loongarch) satisfy these requirements. */ #define GEN_XCHG_HELPER(tname, type, suffix) \ @@ -66,7 +66,7 @@ GEN_XCHG_HELPERS(ptr, const void *) * try_cmpxchg helpers depend on ARCH_SUPPORTS_ATOMIC_RMW and on the * architecture provding try_cmpxchg() support for i8 and i16. * - * The architectures that currently support Rust (x86_64, armv7, + * The architectures that currently support Rust (x86_64, arm, * arm64, riscv, and loongarch) satisfy these requirements. */ #define GEN_TRY_CMPXCHG_HELPER(tname, type, suffix) \ --=20 2.39.5 (Apple Git-154) From nobody Sat Oct 24 13:20:53 2026 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C14CF54DAF2 for ; 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[2a02:3100:a189:2701:8c58:155a:279:7389]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1b481b7f8sm5237345e9.3.2026.10.13.13.32.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 13 Oct 2026 13:32:04 -0700 (PDT) From: Karl Mehltretter To: Russell King , Miguel Ojeda Cc: Karl Mehltretter , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Daniel Almeida , Tamir Duberstein , Alexandre Courbot , =?UTF-8?q?Onur=20=C3=96zkan?= , Arnd Bergmann , Linus Walleij , Christian Schrefl , Bradley Morgan , "Paul E . McKenney" , Peter Zijlstra , FUJITA Tomonori , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , linux-arm-kernel@lists.infradead.org, rust-for-linux@vger.kernel.org, llvm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/6] ARM: rust: Enable Rust support for ARMv5TE Date: Tue, 13 Oct 2026 22:31:38 +0200 Message-Id: <20261013203140.31741-5-kmehltretter@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20261013203140.31741-1-kmehltretter@gmail.com> References: <20261013203140.31741-1-kmehltretter@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The arm-unknown-linux-gnueabi target enables +v6 and emits instructions that ARMv5 does not support. -Ctarget-cpu=3Darm926ej-s does not remove +v6, while -Ctarget-feature=3D-v6 produces an unstable-feature warning. Use armv5te-unknown-linux-gnueabi for CPU_32v5. It uses the Linux soft-float EABI, requires strict alignment and declares 32-bit atomics. Select it alongside -march so Rust and C follow the same CPU selection. Kernels containing ARMv4 or ARMv4T CPUs remain excluded. CPU_32v5 also covers ARM1020, for which C already uses -march=3Darmv5te. The kernel crate implements atomics through C helpers. The preceding patch supplies the missing 2-byte xchg() on pre-ARMv6 CPUs. core::sync::atomic remains unusable because LLVM lowers its operations to __sync_* libcalls that the kernel does not provide. No in-tree code uses them. Tested the Rust samples, KUnit suites and doctests in QEMU versatilepb with versatile_defconfig and on a Microchip SAM9X75 Curiosity board. Link: https://lore.kernel.org/rust-for-linux/CACRpkdYF0sVB2-qgy=3DGzETSR3+2= sagVQPGdunDQDJrn8KqJorA@mail.gmail.com/ Link: https://lore.kernel.org/rust-for-linux/b13d37bd-ec68-4713-94e5-e9ed4d= 6a6354@gmail.com/ Assisted-by: LLM Signed-off-by: Karl Mehltretter --- Documentation/rust/arch-support.rst | 2 +- arch/arm/Kconfig | 8 +++++++- arch/arm/Makefile | 7 ++++++- 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/Documentation/rust/arch-support.rst b/Documentation/rust/arch-= support.rst index bdc42a24bf30..d6d1bef44c8f 100644 --- a/Documentation/rust/arch-support.rst +++ b/Documentation/rust/arch-support.rst @@ -15,7 +15,7 @@ support corresponds to ``S`` values in the ``MAINTAINERS`= ` file. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D Architecture Level of support Constraints =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D -``arm`` Maintained ARMv6K and ARMv7, Little Endian only. +``arm`` Maintained ARMv5TE, ARMv6K and ARMv7, Little Endian = only. ``arm64`` Maintained Little Endian only. ``loongarch`` Maintained \- ``riscv`` Maintained ``riscv64`` and LLVM/Clang only. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b5816f28783a..9275a85f95e9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -138,7 +138,7 @@ config ARM select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_RSEQ - select HAVE_RUST if CPU_LITTLE_ENDIAN && CPU_32v6K && !CPU_V6 && !KASAN + select HAVE_RUST if CPU_LITTLE_ENDIAN && ARM_RUST_TARGET && !KASAN select HAVE_STACKPROTECTOR select HAVE_SYSCALL_TRACEPOINTS select HAVE_UID16 @@ -172,6 +172,12 @@ config ARM Europe. There is an ARM Linux project with a web page at . =20 +# The CPU selections for which rustc has a matching target +config ARM_RUST_TARGET + def_bool y + depends on (CPU_32v6K && !CPU_V6) || \ + (CPU_32v5 && !CPU_32v4T && !CPU_32v4) + config ARM_HAS_GROUP_RELOCS def_bool !COMPILE_TEST help diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 573813ef5e77..168779e9e93d 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -73,6 +73,11 @@ arch-$(CONFIG_CPU_32v4T) :=3D-march=3Darmv4t arch-$(CONFIG_CPU_32v4) :=3D-march=3Darmv4 arch-$(CONFIG_CPU_32v3) :=3D-march=3Darmv3m =20 +# The rustc target fixes the instruction set. -Ctarget-cpu cannot remove +# the +v6 of the generic target, so older CPUs need their own target. +rust-target-y :=3Darm-unknown-linux-gnueabi +rust-target-$(CONFIG_CPU_32v5) :=3Darmv5te-unknown-linux-gnueabi + # Note that GCC does not numerically define an architecture version # macro, but instead defines a whole series of macros which makes # testing for a specific architecture or later rather impossible. @@ -150,7 +155,7 @@ endif KBUILD_CPPFLAGS +=3D$(cpp-y) KBUILD_CFLAGS +=3D$(CFLAGS_ABI) $(CFLAGS_ISA) $(arch-y) $(tune-y) $(call c= c-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-fl= oat -Uarm KBUILD_AFLAGS +=3D$(CFLAGS_ABI) $(AFLAGS_ISA) -Wa,$(arch-y) $(tune-y) -inc= lude $(srctree)/arch/arm/include/asm/unified.h -msoft-float -KBUILD_RUSTFLAGS +=3D --target=3Darm-unknown-linux-gnueabi +KBUILD_RUSTFLAGS +=3D --target=3D$(rust-target-y) =20 CHECKFLAGS +=3D -D__arm__ =20 --=20 2.39.5 (Apple Git-154) From nobody Sat Oct 24 13:20:53 2026 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0101354EEAE for ; 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[2a02:3100:a189:2701:8c58:155a:279:7389]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1b481b7f8sm5237345e9.3.2026.10.13.13.32.09 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 13 Oct 2026 13:32:12 -0700 (PDT) From: Karl Mehltretter To: Russell King , Miguel Ojeda Cc: Karl Mehltretter , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Daniel Almeida , Tamir Duberstein , Alexandre Courbot , =?UTF-8?q?Onur=20=C3=96zkan?= , Arnd Bergmann , Linus Walleij , Christian Schrefl , Bradley Morgan , "Paul E . McKenney" , Peter Zijlstra , FUJITA Tomonori , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , linux-arm-kernel@lists.infradead.org, rust-for-linux@vger.kernel.org, llvm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 5/6] ARM: rust: Enable Rust support for ARMv4T Date: Tue, 13 Oct 2026 22:31:39 +0200 Message-Id: <20261013203140.31741-6-kmehltretter@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20261013203140.31741-1-kmehltretter@gmail.com> References: <20261013203140.31741-1-kmehltretter@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The armv5te target emits clz and blx, which ARMv4T lacks. Use rustc's armv4t-unknown-linux-gnueabi target for CPU_32v4T. A combined ARMv4T and ARMv5 kernel then uses ARMv4T code for both C and Rust. Plain ARMv4 remains excluded because rustc has no matching Linux target. This also depends on the preceding 16-bit xchg() support for pre-ARMv6 CPUs. Tested the Rust samples, KUnit suites and doctests in QEMU sx1 (ARM925T) with omap1_defconfig and on a Microchip SAM9X75 Curiosity board with at91_dt_defconfig. Assisted-by: LLM Signed-off-by: Karl Mehltretter --- Documentation/rust/arch-support.rst | 8 ++++---- arch/arm/Kconfig | 2 +- arch/arm/Makefile | 1 + 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/Documentation/rust/arch-support.rst b/Documentation/rust/arch-= support.rst index d6d1bef44c8f..3f39cf55b6f4 100644 --- a/Documentation/rust/arch-support.rst +++ b/Documentation/rust/arch-support.rst @@ -12,15 +12,15 @@ which uses ``libclang``. Below is a general summary of architectures that currently work. Level of support corresponds to ``S`` values in the ``MAINTAINERS`` file. =20 -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Architecture Level of support Constraints -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D -``arm`` Maintained ARMv5TE, ARMv6K and ARMv7, Little Endian = only. +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +``arm`` Maintained ARMv4T, ARMv5TE, ARMv6K and ARMv7, Little= Endian only. ``arm64`` Maintained Little Endian only. ``loongarch`` Maintained \- ``riscv`` Maintained ``riscv64`` and LLVM/Clang only. ``s390`` Maintained ``CONFIG_EXPOLINE`` must be disabled. ``um`` Maintained \- ``x86`` Maintained ``x86_64`` only. -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9275a85f95e9..cf782fc04872 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -176,7 +176,7 @@ config ARM config ARM_RUST_TARGET def_bool y depends on (CPU_32v6K && !CPU_V6) || \ - (CPU_32v5 && !CPU_32v4T && !CPU_32v4) + ((CPU_32v5 || CPU_32v4T) && !CPU_32v4) =20 config ARM_HAS_GROUP_RELOCS def_bool !COMPILE_TEST diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 168779e9e93d..a72843890241 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -77,6 +77,7 @@ arch-$(CONFIG_CPU_32v3) :=3D-march=3Darmv3m # the +v6 of the generic target, so older CPUs need their own target. rust-target-y :=3Darm-unknown-linux-gnueabi rust-target-$(CONFIG_CPU_32v5) :=3Darmv5te-unknown-linux-gnueabi +rust-target-$(CONFIG_CPU_32v4T) :=3Darmv4t-unknown-linux-gnueabi =20 # Note that GCC does not numerically define an architecture version # macro, but instead defines a whole series of macros which makes --=20 2.39.5 (Apple Git-154) From nobody Sat Oct 24 13:20:53 2026 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B913551986 for ; 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[2a02:3100:a189:2701:8c58:155a:279:7389]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1b481b7f8sm5237345e9.3.2026.10.13.13.32.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 13 Oct 2026 13:32:19 -0700 (PDT) From: Karl Mehltretter To: Russell King , Miguel Ojeda Cc: Karl Mehltretter , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Daniel Almeida , Tamir Duberstein , Alexandre Courbot , =?UTF-8?q?Onur=20=C3=96zkan?= , Arnd Bergmann , Linus Walleij , Christian Schrefl , Bradley Morgan , "Paul E . McKenney" , Peter Zijlstra , FUJITA Tomonori , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , linux-arm-kernel@lists.infradead.org, rust-for-linux@vger.kernel.org, llvm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 6/6] ARM: rust: Build Rust code for ARMv7 on ARMv7 kernels Date: Tue, 13 Oct 2026 22:31:40 +0200 Message-Id: <20261013203140.31741-7-kmehltretter@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20261013203140.31741-1-kmehltretter@gmail.com> References: <20261013203140.31741-1-kmehltretter@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The arm-unknown-linux-gnueabi target builds ARMv6 code, so ARMv7 kernels cannot use ARMv7 instructions in Rust code. Use armv7-unknown-linux-gnueabi when C is built with -march=3Darmv7-a. The target uses the soft-float EABI with NEON disabled and permits unaligned word and halfword accesses, matching C on MMU-enabled ARMv7 kernels. A kernel that also contains an ARMv6K CPU is built with -march=3Darmv6k and keeps the generic target. In the tested Raspberry Pi 400 configuration, Rust text grows by 1.9%. Six small benchmarks range from 10% shorter to 5% longer runtimes. Tested on a Raspberry Pi 400 (Cortex-A72, LPAE) with clang 22.1.8 and in QEMU virt (Cortex-A15) with the minimum tool versions. Rust modules load with the movw/movt relocations. Suggested-by: Arnd Bergmann Assisted-by: LLM Signed-off-by: Karl Mehltretter --- arch/arm/Makefile | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/Makefile b/arch/arm/Makefile index a72843890241..28eb8484ff82 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -73,9 +73,11 @@ arch-$(CONFIG_CPU_32v4T) :=3D-march=3Darmv4t arch-$(CONFIG_CPU_32v4) :=3D-march=3Darmv4 arch-$(CONFIG_CPU_32v3) :=3D-march=3Darmv3m =20 -# The rustc target fixes the instruction set. -Ctarget-cpu cannot remove -# the +v6 of the generic target, so older CPUs need their own target. +# The rustc target fixes the instruction set, so pick it like -march above. +# The generic target builds ARMv6 code. -Ctarget-cpu cannot remove its +v6. rust-target-y :=3Darm-unknown-linux-gnueabi +rust-target-$(CONFIG_CPU_32v7) :=3Darmv7-unknown-linux-gnueabi +rust-target-$(CONFIG_CPU_32v6) :=3Darm-unknown-linux-gnueabi rust-target-$(CONFIG_CPU_32v5) :=3Darmv5te-unknown-linux-gnueabi rust-target-$(CONFIG_CPU_32v4T) :=3Darmv4t-unknown-linux-gnueabi =20 --=20 2.39.5 (Apple Git-154)