From nobody Sat Oct 24 20:10:37 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADE9A2C08D0; Sun, 11 Oct 2026 16:52:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791737532; cv=none; b=tKCPyi00QwWCIh06G0zWhSLY2fgxpxJ1TFdWFEmSiQRV1frckFCjCki6fJVNryFCkfjf80B4He2dXr1AfgEaJWgATztoY5Uoh9uOlCfI+eleGgVK8Gc9muAPbPvZ3VF1STnph46gLu0++pExSi1ugthd+fpuLT/ir+ukV192Avo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791737532; c=relaxed/simple; bh=Fnd+0sqejGQ0KX+O+NuogAH/m8bc5UQymiGVlXraqlI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HV/wYipYUoTn0QNevHP1zAqr32x3hLiLej/oDp4OVtjaUzfO4raHRAT35hJkHF6aVstuoEMrPIe7Hu3pcBufy+8U4RDe0Cz9lGOLbHaMsi8rVH8+nJwxU4vUtRtR2dY3OuHIazH6s1UWoNlylrhS+wltUXVJomIgsU2aMZQ3SAQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bd4bKnHg; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bd4bKnHg" Received: by smtp.kernel.org (Postfix) with ESMTPS id 47AEFC2BCF7; Sun, 11 Oct 2026 16:52:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1791737532; bh=Fnd+0sqejGQ0KX+O+NuogAH/m8bc5UQymiGVlXraqlI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=bd4bKnHg+wjZuVfwKpmiD84UKuxdOJ3sShL+ZX8nB+2ZkS8mT6f20A8IA/BKHrRg2 QB1TL3b8ygtjQOfqnodO/Q321YJHCbRzB1nBq3rMQE2vdz2h3QZdVAR2BgWVJrPJaI o9jQWVbWT3P7+GWyasj5gIdfp9YU6LBzCifboHrb6aI5dxGg0X+BlNdAyNveul3VCq /cG3BEe7yjySV/wTK7cwXJduzIuE+fDJiE2PpL/dDG/pZ3+aejF5ySejr+OvRB9QOZ q7JvOLdUGLMgoseWo7iSGDII/Qdy5qSIAal/GIVEs4/FaP1g9HBaw4dTObcYhgY5+g o8+1NJBj7Pngg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2571ACA9EBD; Sun, 11 Oct 2026 16:52:12 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sun, 11 Oct 2026 19:51:23 +0300 Subject: [PATCH v5 1/7] dt-bindings: nvmem: Add compatible for MSM8952 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261011-msm8952-initial-support-v5-1-1857074992ec@mainlining.org> References: <20261011-msm8952-initial-support-v5-0-1857074992ec@mainlining.org> In-Reply-To: <20261011-msm8952-initial-support-v5-0-1857074992ec@mainlining.org> To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Konrad Dybcio , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Bjorn Andersson , Abel Vesa , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir , Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1791737529; l=867; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=6JMvRgvxX2he4PG9Fo4mqxxQVXCwNkBZtmdxWuS+a1o=; b=rTH5to7L7PETOvi7zfk8qVjP+OKs2EQDB5LNVFqYdp3+qNOlp5KoTUPOPblmkyzWJN1JJcOOy i3Rs2ntQoFWAV5PY4KEe515nxqt3+T/VywnON3rPX1yqvZ9OlOshiHN X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Document the QFPROM block found on MSM8952. Acked-by: Krzysztof Kozlowski Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Doc= umentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 566304ed4c78..646f2e8dcf4d 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -37,6 +37,7 @@ properties: - qcom,msm8916-qfprom - qcom,msm8917-qfprom - qcom,msm8937-qfprom + - qcom,msm8952-qfprom - qcom,msm8960-qfprom - qcom,msm8974-qfprom - qcom,msm8976-qfprom --=20 2.55.0 From nobody Sat Oct 24 20:10:37 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C26F634C9A6; Sun, 11 Oct 2026 16:52:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791737532; cv=none; b=EdfxKrggvB2kcJaemAg1ni1z2OCwvs4TYf/wbHaX9srmSTvg6bfjRVFLnXjY+yFcJqR/0XuexTPNZvH6JzDhEQ00vv9/eQ6dCBOg4GFupLHUHoalEcNiKA6BdrxYXvpRnlnsB0KX9GXFbtfV/RGRg+cIL1u+pMp++Xhbtf0+Vq4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791737532; c=relaxed/simple; bh=td2I24nRoQ5+bn5CQxQqEo0inmSjlf0k47TwwMGhEuI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lznFjYvkv8zbH/fFCyTqmHqVYsiMG+jIsITRrFCFNIgqFb+xUJRHe+kyindSJS2oOFTmXxfKiFymMhdxuywUsvwXxEovTNoSyh/UCbESttbqUJ0+HumpghZ6TL2hjinSUKS0z0y2Kd1Xya/takp5ZRkUhX/DHgSnhEolqZkx4B0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mOYfk7hC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mOYfk7hC" Received: by smtp.kernel.org (Postfix) with ESMTPS id 566F4C4AF0B; Sun, 11 Oct 2026 16:52:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1791737532; bh=td2I24nRoQ5+bn5CQxQqEo0inmSjlf0k47TwwMGhEuI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=mOYfk7hCsFxctEl8DpLPXbA8Co/0AfvfBv2t6+XLYlfIif/YItMNUIqeY5bdYMyzD xIEl0VbL70+a6LvUoawaWux3gUktlvLoIg2ARb9T6TBi+5qw4tDJVpGM1sHvL4xG2Y cYYtU1syhtaqTUYCw61urzNjD7CSFZ+sBO2n53vCHEg19oDvmR5PDp0bvBOgE79jeM 0PhanuW5jVfpumU8CKd9uS/0jUGXKfg0u5A1tNZEXvwUynnoZX1EpxPdrXEa9CqD5H Y5Z2Ou1PZyzs14JXaGz/6YiGrVTyJNZS9qb4mTdNIs5HRITjmrtX0ZeHPz/6GKle/J DuwSGObOhWvqQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3793ACA9ECF; Sun, 11 Oct 2026 16:52:12 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sun, 11 Oct 2026 19:51:24 +0300 Subject: [PATCH v5 2/7] dt-bindings: iommu: qcom,iommu: Add MSM8952 IOMMU to SMMUv2 compatibles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261011-msm8952-initial-support-v5-2-1857074992ec@mainlining.org> References: <20261011-msm8952-initial-support-v5-0-1857074992ec@mainlining.org> In-Reply-To: <20261011-msm8952-initial-support-v5-0-1857074992ec@mainlining.org> To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Konrad Dybcio , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Bjorn Andersson , Abel Vesa , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir , Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1791737529; l=969; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=ITO15xkGcBa687Mp0TLRvjwHoI0S0V/a2UgW08TP0cI=; b=m76TWNS/Yat00OIAy5Qh80LXCoUB5NfPswR+KOcfXkGHQrLab27a2eCCeFLpEGI/T1wnMGXjI guKTnMZv7vpD54GmHW3RLL2Mny+BXnhwJB0QHKvEH+//hdhyKzMZ+f+ X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add MSM8952 compatible string with "qcom,msm-iommu-v2" as fallback for the MSM8952 IOMMU which is compatible with Qualcomm's secure fw "SMMU v2" implementation. Acked-by: Krzysztof Kozlowski Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/iommu/qcom,iommu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml b/Docu= mentation/devicetree/bindings/iommu/qcom,iommu.yaml index 93a489025317..9952b9da9a6a 100644 --- a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml @@ -27,6 +27,7 @@ properties: - const: qcom,msm-iommu-v1 - items: - enum: + - qcom,msm8952-iommu - qcom,msm8953-iommu - qcom,msm8976-iommu - const: qcom,msm-iommu-v2 --=20 2.55.0 From nobody Sat Oct 24 20:10:37 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAE7434D916; Sun, 11 Oct 2026 16:52:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791737532; cv=none; b=lZ+IiHifY6yityLeNX45uLAV+7MtiZPuHMj/QAP+booCIxN7fHLpAv4r5mUhlYKHY7gfrBgaFvfTR04XlZacdNzGSs5LBR/O6SeSp261fZjHlf18rjKtJiKArJEFknK6O+c50sMCWM4vou8vnjwE2BUZcziTogTSpHWvXPNVt44= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791737532; c=relaxed/simple; bh=01L3auXbWsKqF5qDXyY0RBxMKrA08Ada2I0PI6iBeVg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ofs7v5pYLDljp5AVPy17CGJX9vf+iiWnrkO2ZeqPTcBSiT7szoepzmzVHOqvnVRY1uoYA8M7CBxXSY8LU/xp7IisRDjIeJHAnvhZUntKxrPMJZoow5Rgg6KFNHozHRr8X6bEcpAR0X46ApugIDjYr+JitEhMjKEDAg5YwkuG620= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Qgm8XePm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Qgm8XePm" Received: by smtp.kernel.org (Postfix) with ESMTPS id 661D0C32786; Sun, 11 Oct 2026 16:52:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1791737532; bh=01L3auXbWsKqF5qDXyY0RBxMKrA08Ada2I0PI6iBeVg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Qgm8XePmj3gTFNoe6UgoMXJ0d/fFSsCmp84NndLQyuC5qjtjOdq9+OgPJQNmokF8W z/phgLlY0bSVhtanibaXbVxYpyiaGO1SQS4y/wjrk2o0GnpNXPhtBqpwAoe14GTjfH NNtFiQvF9EVAAjfVgLQNwwne2S3tiaEuRkgJ7QsKQRwb5H18qOXT1u0aVH/FR7znco l4RLdZtfW9t8P16zErdW05k1JD/jPBEsKFMQXMBHcZUnRuSK6BUFZNTMzxVjNT+RYO DDnR2BuuNOK6Umb//vMpPi4UVesjPrQo50UpkZnNUwrKNNo7lqtRdzudGfGyxFV7El cFY6HwwoP8CmQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CDC1CA9EC7; Sun, 11 Oct 2026 16:52:12 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sun, 11 Oct 2026 19:51:25 +0300 Subject: [PATCH v5 3/7] dt-bindings: thermal: tsens: Add MSM8952 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261011-msm8952-initial-support-v5-3-1857074992ec@mainlining.org> References: <20261011-msm8952-initial-support-v5-0-1857074992ec@mainlining.org> In-Reply-To: <20261011-msm8952-initial-support-v5-0-1857074992ec@mainlining.org> To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Konrad Dybcio , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Bjorn Andersson , Abel Vesa , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir , Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1791737529; l=867; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=3ZgUceNunaKIIu3OLKt6YNZfU8fyIjpBkrf/ZfEKkk0=; b=iWHncuGzyNZtyYMyHGcqyvmXiKzKnWl72x4xB0B4ZXsGT+yFYOZmMqtQS7oiFsjFoQEE2gqZ1 irTsJM7DWGeBz9ePE5SUZ8kjKTkakPlaY55lyQ3tVCZPzPKi9QPgwbp X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add compatible string for tsens block found in MSM8952. Acked-by: Krzysztof Kozlowski Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Do= cumentation/devicetree/bindings/thermal/qcom-tsens.yaml index 5a8f7673e730..c78074fbcecf 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -46,6 +46,7 @@ properties: items: - enum: - qcom,msm8937-tsens + - qcom,msm8952-tsens - qcom,msm8956-tsens - qcom,msm8976-tsens - qcom,qcs404-tsens --=20 2.55.0 From nobody Sat Oct 24 20:10:37 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4E5435B653; Sun, 11 Oct 2026 16:52:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791737533; cv=none; b=WRQ4O/K/oFwYmANQCrgCu21qyKH8WPCQ/exqRt2KWIVEQvh9ceNGQ2nIzbdjNl+ax+kcTyMPaKBruI0wNvh7q3onae5ZwHlw2yLbbBcTUzi9uzHKK6depCriPYmfdmRbTayOTGIkRudLmt/gmH0AqyIc1v+gH3qXZBLiWNXNQU8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791737533; c=relaxed/simple; bh=1VAUGUtsIzrRS3NpZWYQU6qxN7QwSxApdg6TWS5po8s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IzMp+yoMl2awmLKdcLrC96UOifV0KLCET7PlHv+cG3o3ywHuEzWoKAmhruFeGopF7QXw0jRC5zYSnRHzKlGrUd1Bsm25J84ooAWXXXHcL6+l23PK5K1wdJ5jW9LG0mBhPCpJMbR7FjY9cEa18MgmRFGGd6gm4RKPYyOIWi+I2aA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=T2T3avxO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="T2T3avxO" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7E4FEC4AF65; Sun, 11 Oct 2026 16:52:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1791737532; bh=1VAUGUtsIzrRS3NpZWYQU6qxN7QwSxApdg6TWS5po8s=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=T2T3avxOi200/WoJuWZ96a7KrKKwM2R2WNC7Fr/J3/3Sy1Hk3h/tWWqDKXC83JQam 5bsGIIJiPzToj5l5+52c4TISxO+5wimOC3cdp6wKpw5gjLOahVRK29aM//9T0t3sw/ HV+CMcJ5amC2AV7/iRfxAPud0yZkJsndcaprtWwRdfpAnib099Ll6KGVtzsM7jzUcA ktnsqbBS1J8N+XI1sggOENQVvfs4dh3zy1hSVQIaya2fvq/GjDsur0XJZKNfqXA4b8 OV1R9MBtf200rk44WwNDQaTCmHQKXmjFIRBE6ZiZJPJeWXLYpTNLG/ENgcPmgduCqb MBqG7vT/iGfaw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6319FCA9ED1; Sun, 11 Oct 2026 16:52:12 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sun, 11 Oct 2026 19:51:26 +0300 Subject: [PATCH v5 4/7] thermal: qcom: tsens: Add support for MSM8952 tsens Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261011-msm8952-initial-support-v5-4-1857074992ec@mainlining.org> References: <20261011-msm8952-initial-support-v5-0-1857074992ec@mainlining.org> In-Reply-To: <20261011-msm8952-initial-support-v5-0-1857074992ec@mainlining.org> To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Konrad Dybcio , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Bjorn Andersson , Abel Vesa , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir , Dmitry Baryshkov X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1791737529; l=3695; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=3h8bz/deABOTAvqHXeSaJkIEOawr/vek4uhwmg7uHiw=; b=O53CIdJr3BqCGpBzC2c1J5nZ9cVQ/IJS62Tjt5wfh5KWXVquYVK2mrBRYeVmslLSUL72hA4vk A6cZsCAfkIRAqhdtytx4g+GVd56Uo4yapWT8a8DoHGBTqVpW8KY5qc5 X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add support for tsens v1 block that exists on MSM8952 with 11 tsens sensors. Sensor Offsets are taken from downstream. Link: https://android.googlesource.com/kernel/msm.git/+/refs/tags/android-w= ear-7.0.0_r0.3/drivers/thermal/msm-tsens.c#1621 Signed-off-by: Muzaffer Kadir Reviewed-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v1.c | 41 +++++++++++++++++++++++++++++++++++++= ++++ drivers/thermal/qcom/tsens.c | 3 +++ drivers/thermal/qcom/tsens.h | 2 +- 3 files changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v= 1.c index faa5d00788ca..7bda8e6087c4 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -145,6 +145,34 @@ static const struct reg_field tsens_v1_regfields[MAX_R= EGFIELDS] =3D { [TRDY] =3D REG_FIELD(TM_TRDY_OFF, 0, 0), }; =20 +static int __init init_8952(struct tsens_priv *priv) +{ + priv->sensor[0].p1_calib_offset =3D 2; + priv->sensor[0].p2_calib_offset =3D -1; + priv->sensor[1].p1_calib_offset =3D -4; + priv->sensor[1].p2_calib_offset =3D -4; + priv->sensor[2].p1_calib_offset =3D 4; + priv->sensor[2].p2_calib_offset =3D 5; + priv->sensor[3].p1_calib_offset =3D 1; + priv->sensor[3].p2_calib_offset =3D 1; + priv->sensor[4].p1_calib_offset =3D 2; + priv->sensor[4].p2_calib_offset =3D 3; + priv->sensor[5].p1_calib_offset =3D -1; + priv->sensor[5].p2_calib_offset =3D -1; + priv->sensor[6].p1_calib_offset =3D 0; + priv->sensor[6].p2_calib_offset =3D -1; + priv->sensor[7].p1_calib_offset =3D 3; + priv->sensor[7].p2_calib_offset =3D 4; + priv->sensor[8].p1_calib_offset =3D 2; + priv->sensor[8].p2_calib_offset =3D 4; + priv->sensor[9].p1_calib_offset =3D 0; + priv->sensor[9].p2_calib_offset =3D 0; + priv->sensor[10].p1_calib_offset =3D -3; + priv->sensor[10].p2_calib_offset =3D -2; + + return init_common(priv); +} + static int __init init_8956(struct tsens_priv *priv) { priv->sensor[0].slope =3D 3313; priv->sensor[1].slope =3D 3275; @@ -223,6 +251,19 @@ struct tsens_plat_data data_8937 =3D { .fields =3D tsens_v1_regfields, }; =20 +static const struct tsens_ops ops_8952 =3D { + .init =3D init_8952, + .calibrate =3D tsens_calibrate_common, + .get_temp =3D get_temp_tsens_valid, +}; + +struct tsens_plat_data data_8952 =3D { + .num_sensors =3D 11, + .ops =3D &ops_8952, + .feat =3D &tsens_v1_feat, + .fields =3D tsens_v1_regfields, +}; + static const struct tsens_ops ops_8956 =3D { .init =3D init_8956, .calibrate =3D tsens_calibrate_common, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index b5ec70201e2f..4d7013fc79d6 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -1191,6 +1191,9 @@ static const struct of_device_id tsens_table[] =3D { }, { .compatible =3D "qcom,msm8939-tsens", .data =3D &data_8939, + }, { + .compatible =3D "qcom,msm8952-tsens", + .data =3D &data_8952, }, { .compatible =3D "qcom,msm8956-tsens", .data =3D &data_8956, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index e8376accdff3..a35b15312961 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -669,7 +669,7 @@ extern struct tsens_plat_data data_8960; extern struct tsens_plat_data data_8226, data_8909, data_8916, data_8939, = data_8974, data_9607; =20 /* TSENS v1 targets */ -extern struct tsens_plat_data data_tsens_v1, data_8937, data_8976, data_89= 56; +extern struct tsens_plat_data data_tsens_v1, data_8937, data_8952, data_89= 76, data_8956; =20 /* TSENS v1 with no RPM targets */ extern const struct tsens_plat_data data_ipq5018; --=20 2.55.0 From nobody Sat Oct 24 20:10:37 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F316035DA68; Sun, 11 Oct 2026 16:52:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791737533; cv=none; b=qaoz3oKgsEUrrWRVmkq/4X9H0RfCNIdU8a0BBmWX6QP6E/fXBk86Nm2+ceKEbsK/fZ3RJ0K601K7ZCu6CMS+qJ6i0G/OE69oRvIGnDFZLYW9ssYMrFVJby8V6QwBe2UiKpTBRDvEFeT2gzAAzjNvlC2EKodcr4lHEAb6JCCrsUE= ARC-Message-Signature: i=1; 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b=SMCS9MaZygdLl9ka1k2SBHqZnn5VSUJbyzaj4/6REzNEX6cEVvVJJSKf5hmIaeVWQ VLeedc56EmZebFoFx5i0z8k9POCQjsWV9UN4sH/2kQu4Z0hD4ubRobIwYvA1vhz26a E5XxES4ThS87XbEYsvjIRxNXGWOh4Ci/c7obSjrez/pFmWssc/zmQ8QP+khr9frr5J Wxlc6xpY98KRDqAx4iD3jfGlsinypbJRKN2S/7ESN6W1pIzouP383lThlnvTOseFe7 tQ5wQPjaeIq0/UzRkJby96JZDWn7SivtwMyZqQTNKLXvO3FaqOn0Y7DHFva6NwqYEz +2YT4mVA9sEFA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 873BCCA9EC7; Sun, 11 Oct 2026 16:52:12 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sun, 11 Oct 2026 19:51:27 +0300 Subject: [PATCH v5 5/7] arm64: dts: qcom: Add initial support for MSM8952 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261011-msm8952-initial-support-v5-5-1857074992ec@mainlining.org> References: <20261011-msm8952-initial-support-v5-0-1857074992ec@mainlining.org> In-Reply-To: <20261011-msm8952-initial-support-v5-0-1857074992ec@mainlining.org> To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Konrad Dybcio , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Bjorn Andersson , Abel Vesa , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1791737529; l=67800; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=txed2BHH0Ui0wTTpfHUgqR360j1hfqelaRmLdfySug0=; b=hPk3+kbJNGsazUeFJNMWjlrYm3z9Wnz+uBQL2ZhDMA94W4eMUbJkXJX9UZOcK/ztyjUVx1+ql BrvJusAujrTAdH3mCLHR4ac8MivZ97HLYydRwJv453xAxXSi6pD6aQk X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add initial support for MSM8952 SoC. AI help is used for calculating qfprom nodes. Downstream reference for port is [1] which is very lightly modified version of [2]. Downstream reference used to calculate qfprom: [3] Currently supported features in this port: - Internal Storage support - MDSS - Basic Adsp remote proc support - Blsp 1 and 2 with all i2c and spi - Tsens support - USB - RPM with mpm and master-stats [1] https://github.com/Asderdd/android_kernel_generalmobile_shamrock/blob/c= m-14.1/arch/arm/boot/dts/qcom/msm8952.dtsi [2] https://android.googlesource.com/kernel/msm.git/+/refs/tags/android-wea= r-7.0.0_r0.3/arch/arm/boot/dts/qcom/msm8952.dtsi [3] https://android.googlesource.com/kernel/msm.git/+/refs/tags/android-wea= r-7.0.0_r0.3/drivers/thermal/msm-tsens.c#1621 Assisted-by: LLM Signed-off-by: Muzaffer Kadir --- arch/arm64/boot/dts/qcom/msm8952.dtsi | 2784 +++++++++++++++++++++++++++++= ++++ 1 file changed, 2784 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8952.dtsi b/arch/arm64/boot/dts/qc= om/msm8952.dtsi new file mode 100644 index 000000000000..18010f56ac5d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8952.dtsi @@ -0,0 +1,2784 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2026 Muzaffer Kadir + * + * Based on msm8937.dtsi: + * Copyright (c) 2023, Dang Huynh + * adapted with data from msm8952.dtsi and msm8952-*.dtsi files in Qualcom= m's msm-3.10 release: + * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + clocks { + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + xo_board: xo-board { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c0>; + next-level-cache =3D <&l2_0>; + clocks =3D <&apcs0>; + #cooling-cells =3D <2>; + qcom,acc =3D <&acc0>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x40000>; + cache-unified; + }; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x1>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c0>; + next-level-cache =3D <&l2_0>; + clocks =3D <&apcs0>; + #cooling-cells =3D <2>; + qcom,acc =3D <&acc1>; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x2>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c0>; + next-level-cache =3D <&l2_0>; + clocks =3D <&apcs0>; + #cooling-cells =3D <2>; + qcom,acc =3D <&acc2>; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x3>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c0>; + next-level-cache =3D <&l2_0>; + clocks =3D <&apcs0>; + #cooling-cells =3D <2>; + qcom,acc =3D <&acc3>; + }; + + cpu4: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x100>; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + clocks =3D <&apcs1>; + operating-points-v2 =3D <&cpu_opp_table_c1>; + #cooling-cells =3D <2>; + qcom,acc =3D <&acc4>; + + l2_1: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-unified; + }; + }; + + cpu5: cpu@101 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x101>; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + clocks =3D <&apcs1>; + operating-points-v2 =3D <&cpu_opp_table_c1>; + #cooling-cells =3D <2>; + qcom,acc =3D <&acc5>; + }; + + cpu6: cpu@102 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x102>; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + clocks =3D <&apcs1>; + operating-points-v2 =3D <&cpu_opp_table_c1>; + #cooling-cells =3D <2>; + qcom,acc =3D <&acc6>; + }; + + cpu7: cpu@103 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x103>; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + clocks =3D <&apcs1>; + operating-points-v2 =3D <&cpu_opp_table_c1>; + #cooling-cells =3D <2>; + qcom,acc =3D <&acc7>; + }; + + cpu-map { + /* Little Cores */ + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + + /* Big Cores */ + cluster1 { + core0 { + cpu =3D <&cpu4>; + }; + + core1 { + cpu =3D <&cpu5>; + }; + + core2 { + cpu =3D <&cpu6>; + }; + + core3 { + cpu =3D <&cpu7>; + }; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-msm8952", "qcom,scm"; + clocks =3D <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names =3D "core", + "bus", + "iface"; + #reset-cells =3D <1>; + + qcom,dload-mode =3D <&tcsr 0x6100>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the reg */ + reg =3D <0 0x80000000 0 0>; + }; + + cpu_opp_table_c0: opp-table-c0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-403200000 { + opp-hz =3D /bits/ 64 <403200000>; + }; + + opp-806400000 { + opp-hz =3D /bits/ 64 <806400000>; + }; + + opp-998400000 { + opp-hz =3D /bits/ 64 <998400000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + + opp-1209600000 { + opp-hz =3D /bits/ 64 <1209600000>; + }; + }; + + cpu_opp_table_c1: opp-table-c1 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-499200000 { + opp-hz =3D /bits/ 64 <499200000>; + }; + + opp-806400000 { + opp-hz =3D /bits/ 64 <806400000>; + }; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + + opp-1344000000 { + opp-hz =3D /bits/ 64 <1344000000>; + }; + + opp-1440000000 { + opp-hz =3D /bits/ 64 <1440000000>; + }; + + opp-1516800000 { + opp-hz =3D /bits/ 64 <1516800000>; + }; + }; + + spi_opp_table: opp-table-spi { + compatible =3D "operating-points-v2"; + + opp-25000000 { + opp-hz =3D /bits/ 64 <25000000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-50000000 { + opp-hz =3D /bits/ 64 <50000000>; + required-opps =3D <&rpmpd_opp_nom>; + }; + }; + + uart_opp_table: opp-table-uart { + compatible =3D "operating-points-v2"; + + opp-32000000 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-64000000 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmpd_opp_nom>; + }; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + rpm: remoteproc { + compatible =3D "qcom,msm8952-rpm-proc", "qcom,rpm-proc"; + + mpm: interrupt-controller { + compatible =3D "qcom,mpm"; + + interrupts =3D ; + + mboxes =3D <&apcs1 1>; + interrupt-controller; + #interrupt-cells =3D <2>; + #power-domain-cells =3D <0>; + interrupt-parent =3D <&intc>; + qcom,rpm-msg-ram =3D <&apss_mpm>; + qcom,mpm-pin-count =3D <64>; + qcom,mpm-pin-map =3D <2 184>, /* TSENS UPLOW */ + <49 140>, /* USB ASYNC */ + <53 72>, /* MDSS */ + <58 134>, /* USB */ + <62 190>; /* SPMI */ + }; + + master-stats { + compatible =3D "qcom,rpm-master-stats"; + qcom,rpm-msg-ram =3D <&apss_master_stats>, + <&mpss_master_stats>, + <&pronto_master_stats>, + <&tz_master_stats>, + <&lpass_master_stats>; + qcom,master-names =3D "APSS", + "MPSS", + "PRONTO", + "TZ", + "LPASS"; + }; + + smd-edge { + interrupts =3D ; + qcom,ipc =3D <&apcs1 8 0>; + qcom,smd-edge =3D <15>; + + rpm_requests: rpm-requests { + compatible =3D "qcom,rpm-msm8952", "qcom,smd-rpm"; + qcom,smd-channels =3D "rpm_requests"; + + rpmcc: clock-controller { + compatible =3D "qcom,rpmcc-msm8952", + "qcom,rpmcc-msm8976", + "qcom,rpmcc"; + #clock-cells =3D <1>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + }; + + rpmpd: power-controller { + compatible =3D "qcom,msm8952-rpmpd", + "qcom,msm8917-rpmpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level =3D ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level =3D ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level =3D ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level =3D ; + }; + + rpmpd_opp_svs: opp5 { + opp-level =3D ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level =3D ; + }; + + rpmpd_opp_nom: opp7 { + opp-level =3D ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level =3D ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level =3D ; + }; + }; + }; + }; + }; + }; + + reserved-memory { + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + qseecom_mem: reserved@85b00000 { + reg =3D <0x0 0x85b00000 0x0 0x800000>; + no-map; + }; + + smem@86300000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x86300000 0x0 0x100000>; + no-map; + + hwlocks =3D <&tcsr_mutex 3>; + qcom,rpm-msg-ram =3D <&rpm_msg_ram>; + }; + + reserved@86400000 { + reg =3D <0x0 0x86400000 0x0 0x400000>; + no-map; + }; + + mpss_mem: mpss@86c00000 { + reg =3D <0x0 0x86c00000 0x0 0x5600000>; + no-map; + }; + + adsp_fw_mem: adsp@8c200000 { + reg =3D <0x0 0x8c200000 0x0 0x1700000>; + no-map; + }; + + rmtfs_mem: rmtfs { + compatible =3D "qcom,rmtfs-mem"; + + size =3D <0x0 0x200000>; + alloc-ranges =3D <0x0 0xa0000000 0x0 0x2000000>; + no-map; + + qcom,client-id =3D <1>; + }; + + ramoops_mem: ramoops@dffc0000 { + compatible =3D "ramoops"; + reg =3D <0x0 0xdffc0000 0x0 0x40000>; + + record-size =3D <0x10000>; + console-size =3D <0x10000>; + pmsg-size =3D <0x20000>; + + status =3D "disabled"; + }; + + gps_mem: gps { + size =3D <0x0 0x200000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + + status =3D "disabled"; + }; + + mba_mem: mba { + size =3D <0x0 0x100000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + + status =3D "disabled"; + }; + + wcnss_mem: wcnss { + size =3D <0x0 0x700000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + + status =3D "disabled"; + }; + + venus_mem: venus { + size =3D <0x0 0x500000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + + status =3D "disabled"; + }; + + adsp_mem: adsp { + compatible =3D "shared-dma-pool"; + size =3D <0x0 0x400000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + + status =3D "disabled"; + }; + }; + + smp2p-adsp { + compatible =3D "qcom,smp2p"; + + interrupts =3D ; + + mboxes =3D <&apcs1 10>; + qcom,smem =3D <443>, <429>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + adsp_smp2p_in: slave-kernel { + interrupt-controller; + #interrupt-cells =3D <2>; + + qcom,entry-name =3D "slave-kernel"; + }; + }; + + smp2p-modem { + compatible =3D "qcom,smp2p"; + + interrupts =3D ; + + mboxes =3D <&apcs1 14>; + qcom,smem =3D <435>, <428>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + modem_smp2p_in: slave-kernel { + interrupt-controller; + #interrupt-cells =3D <2>; + qcom,entry-name =3D "slave-kernel"; + }; + }; + + smp2p-wcnss { + compatible =3D "qcom,smp2p"; + + interrupts =3D ; + + mboxes =3D <&apcs1 18>; + qcom,smem =3D <451>, <431>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + wcnss_smp2p_in: slave-kernel { + interrupt-controller; + #interrupt-cells =3D <2>; + + qcom,entry-name =3D "slave-kernel"; + }; + }; + + smsm { + compatible =3D "qcom,smsm"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + mboxes =3D <0>, <&apcs1 13>, <&apcs1 9>, <&apcs1 19>; + + apps_smsm: apps@0 { + reg =3D <0>; + + #qcom,smem-state-cells =3D <1>; + }; + + hexagon_smsm: hexagon@1 { + reg =3D <1>; + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + wcnss_smsm: wcnss@6 { + reg =3D <6>; + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + ranges =3D <0 0 0 0xffffffff>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + rng@22000 { + compatible =3D "qcom,prng"; + reg =3D <0x00022000 0x140>; + clocks =3D <&gcc GCC_PRNG_AHB_CLK>; + clock-names =3D "core"; + }; + + qfprom: qfprom@5c000 { + compatible =3D "qcom,msm8952-qfprom", "qcom,qfprom"; + reg =3D <0x0005c000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + tsens_base0: base0@a0 { + reg =3D <0xa0 0x1>; + bits =3D <0 8>; + }; + + tsens_s5_p1: s5-p1@a1 { + reg =3D <0xa1 0x1>; + bits =3D <0 6>; + }; + + tsens_s5_p2: s5-p2@a1 { + reg =3D <0xa1 0x2>; + bits =3D <6 6>; + }; + + tsens_s6_p1: s6-p1@a2 { + reg =3D <0xa2 0x2>; + bits =3D <4 6>; + }; + + tsens_s6_p2: s6-p2@a3 { + reg =3D <0xa3 0x1>; + bits =3D <2 6>; + }; + + tsens_s7_p1: s7-p1@a4 { + reg =3D <0xa4 0x1>; + bits =3D <0 6>; + }; + + tsens_s7_p2: s7-p2@a4 { + reg =3D <0xa4 0x2>; + bits =3D <6 6>; + }; + + tsens_s8_p1: s8-p1@a5 { + reg =3D <0xa5 0x2>; + bits =3D <4 6>; + }; + + tsens_s8_p2: s8-p2@a6 { + reg =3D <0xa6 0x1>; + bits =3D <2 6>; + }; + + tsens_base1: base1@a7 { + reg =3D <0xa7 0x1>; + bits =3D <0 8>; + }; + + tsens_mode: mode@d0 { + reg =3D <0xd0 0x1>; + bits =3D <0 3>; + }; + + tsens_s0_p1: s0-p1@d0 { + reg =3D <0xd0 0x2>; + bits =3D <3 6>; + }; + + tsens_s0_p2: s0-p2@d1 { + reg =3D <0xd1 0x1>; + bits =3D <1 6>; + }; + + tsens_s1_p1: s1-p1@d1 { + reg =3D <0xd1 0x2>; + bits =3D <7 6>; + }; + + tsens_s1_p2: s1-p2@d2 { + reg =3D <0xd2 0x2>; + bits =3D <5 6>; + }; + + tsens_s2_p1: s2-p1@d3 { + reg =3D <0xd3 0x2>; + bits =3D <3 6>; + }; + + tsens_s2_p2: s2-p2@d4 { + reg =3D <0xd4 0x1>; + bits =3D <1 6>; + }; + + tsens_s3_p1: s3-p1@d4 { + reg =3D <0xd4 0x2>; + bits =3D <7 6>; + }; + + tsens_s3_p2: s3-p2@d5 { + reg =3D <0xd5 0x2>; + bits =3D <5 6>; + }; + + tsens_s4_p1: s4-p1@d6 { + reg =3D <0xd6 0x2>; + bits =3D <3 6>; + }; + + tsens_s4_p2: s4-p2@d7 { + reg =3D <0xd7 0x1>; + bits =3D <1 6>; + }; + + tsens_s9_p1: s9-p1@f0 { + reg =3D <0xf0 0x1>; + bits =3D <0 6>; + }; + + tsens_s9_p2: s9-p2@f0 { + reg =3D <0xf0 0x2>; + bits =3D <6 6>; + }; + + tsens_s10_p1: s10-p1@f1 { + reg =3D <0xf1 0x2>; + bits =3D <4 6>; + }; + + tsens_s10_p2: s10-p2@f2 { + reg =3D <0xf2 0x1>; + bits =3D <2 6>; + }; + }; + + rpm_msg_ram: sram@60000 { + compatible =3D "qcom,rpm-msg-ram", "mmio-sram"; + reg =3D <0x00060000 0x8000>; + + ranges =3D <0 0x00060000 0x8000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + apss_master_stats: sram@150 { + reg =3D <0x150 0x14>; + }; + + apss_mpm: sram@1d0 { + reg =3D <0x1d0 0x64>; + }; + + mpss_master_stats: sram@1150 { + reg =3D <0x1150 0x14>; + }; + + pronto_master_stats: sram@2550 { + reg =3D <0x2550 0x14>; + }; + + tz_master_stats: sram@3550 { + reg =3D <0x3550 0x14>; + }; + + lpass_master_stats: sram@4550 { + reg =3D <0x4550 0x14>; + }; + }; + + usb_hs_phy: phy@6c000 { + compatible =3D "qcom,usb-hs-28nm-femtophy"; + reg =3D <0x0006c000 0x200>; + #phy-cells =3D <0>; + clocks =3D <&xo_board>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names =3D "ref", + "ahb", + "sleep"; + resets =3D <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names =3D "phy", "por"; + + status =3D "disabled"; + }; + + tsens: thermal-sensor@4a9000 { + compatible =3D "qcom,msm8952-tsens", "qcom,tsens-v1"; + reg =3D <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + nvmem-cells =3D <&tsens_mode>, + <&tsens_base0>, <&tsens_base1>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>; + nvmem-cell-names =3D "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2"; + interrupts-extended =3D <&mpm 2 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "uplow"; + #thermal-sensor-cells =3D <1>; + #qcom,sensors =3D <11>; + }; + + restart@4ab000 { + compatible =3D "qcom,pshold"; + reg =3D <0x004ab000 0x4>; + }; + + crypto_dma: dma-controller@704000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x00704000 0x20000>; + interrupts =3D ; + #dma-cells =3D <1>; + num-channels =3D <16>; + qcom,ee =3D <1>; + qcom,num-ees =3D <4>; + qcom,controlled-remotely; + }; + + crypto: crypto@73a000 { + compatible =3D "qcom,crypto-v5.4"; + reg =3D <0x0073a000 0x6000>; + clocks =3D <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_CLK>; + clock-names =3D "iface", + "bus", + "core"; + dmas =3D <&crypto_dma 2>, <&crypto_dma 3>; + dma-names =3D "rx", "tx"; + }; + + tlmm: pinctrl@1000000 { + compatible =3D "qcom,msm8952-pinctrl"; + reg =3D <0x01000000 0x300000>; + interrupts =3D ; + gpio-controller; + gpio-ranges =3D <&tlmm 0 0 134>; + wakeup-parent =3D <&mpm>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + + blsp1_uart1_console_default: blsp1-uart1-console-default-state { + rx-pins { + pins =3D "gpio1"; + function =3D "blsp_uart1"; + drive-strength =3D <16>; + bias-pull-up; + bootph-all; + }; + + tx-pins { + pins =3D "gpio0"; + function =3D "blsp_uart1"; + drive-strength =3D <16>; + bias-disable; + bootph-all; + }; + }; + + blsp1_uart1_console_sleep: blsp1-uart1-console-sleep-state { + pins =3D "gpio0", "gpio1"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp1_uart1_default: blsp1-uart1-default-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "blsp_uart1"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_uart1_sleep: blsp1-uart1-sleep-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c1_default: blsp1-i2c1-default-state { + pins =3D "gpio2", "gpio3"; + function =3D "blsp_i2c1"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c1_sleep: blsp1-i2c1-sleep-state { + pins =3D "gpio2", "gpio3"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_spi1_default: blsp1-spi1-default-state { + cs-pins { + pins =3D "gpio2"; + function =3D "blsp_spi1"; + drive-strength =3D <2>; + bias-disable; + }; + + spi-pins { + pins =3D "gpio0", "gpio1", "gpio3"; + function =3D "blsp_spi1"; + drive-strength =3D <12>; + bias-disable; + }; + }; + + blsp1_spi1_sleep: blsp1-spi1-sleep-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp1_uart2_default: blsp1-uart2-default-state { + pins =3D "gpio4", "gpio5"; + function =3D "blsp_uart2"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_uart2_sleep: blsp1-uart2-sleep-state { + pins =3D "gpio4", "gpio5"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp1_i2c2_default: blsp1-i2c2-default-state { + pins =3D "gpio6", "gpio7"; + function =3D "blsp_i2c2"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { + pins =3D "gpio6", "gpio7"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_spi2_default: blsp1-spi2-default-state { + cs-pins { + pins =3D "gpio6"; + function =3D "blsp_spi2"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + + spi-pins { + pins =3D "gpio4", "gpio5", "gpio7"; + function =3D "blsp_spi2"; + drive-strength =3D <12>; + bias-disable; + }; + }; + + blsp1_spi2_sleep: blsp1-spi2-sleep-state { + pins =3D "gpio4", "gpio5", "gpio6", "gpio7"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp1_i2c3_default: blsp1-i2c3-default-state { + pins =3D "gpio10", "gpio11"; + function =3D "blsp_i2c3"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { + pins =3D "gpio10", "gpio11"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_spi3_default: blsp1-spi3-default-state { + cs-pins { + pins =3D "gpio10"; + function =3D "blsp_spi3"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + + spi-pins { + pins =3D "gpio8", "gpio9", "gpio11"; + function =3D "blsp_spi3"; + drive-strength =3D <12>; + bias-disable; + }; + }; + + blsp1_spi3_sleep: blsp1-spi3-sleep-state { + pins =3D "gpio8", "gpio9", "gpio10", "gpio11"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp1_i2c4_default: blsp1-i2c4-default-state { + pins =3D "gpio14", "gpio15"; + function =3D "blsp_i2c4"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { + pins =3D "gpio14", "gpio15"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_spi4_default: blsp1-spi4-default-state { + cs-pins { + pins =3D "gpio14"; + function =3D "blsp_spi4"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + + spi-pins { + pins =3D "gpio12", "gpio13", "gpio15"; + function =3D "blsp_spi4"; + drive-strength =3D <12>; + bias-disable; + }; + }; + + blsp1_spi4_sleep: blsp1-spi4-sleep-state { + pins =3D "gpio12", "gpio13", "gpio14", "gpio15"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp2_i2c1_default: blsp2-i2c1-default-state { + pins =3D "gpio18", "gpio19"; + function =3D "blsp_i2c5"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { + pins =3D "gpio18", "gpio19"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_spi1_default: blsp2-spi1-default-state { + cs-pins { + pins =3D "gpio18"; + function =3D "blsp_spi5"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + + spi-pins { + pins =3D "gpio16", "gpio17", "gpio19"; + function =3D "blsp_spi5"; + drive-strength =3D <12>; + bias-disable; + }; + }; + + blsp2_spi1_sleep: blsp2-spi1-sleep-state { + pins =3D "gpio16", "gpio17", "gpio18", "gpio19"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp2_i2c2_default: blsp2-i2c2-default-state { + pins =3D "gpio22", "gpio23"; + function =3D "blsp_i2c6"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { + pins =3D "gpio22", "gpio23"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_spi2_default: blsp2-spi2-default-state { + cs-pins { + pins =3D "gpio22"; + function =3D "blsp_spi6"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + + spi-pins { + pins =3D "gpio20", "gpio21", "gpio23"; + function =3D "blsp_spi6"; + drive-strength =3D <12>; + bias-disable; + }; + }; + + blsp2_spi2_sleep: blsp2-spi2-sleep-state { + pins =3D "gpio20", "gpio21", "gpio22", "gpio23"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp2_i2c3_default: blsp2-i2c3-default-state { + pins =3D "gpio94", "gpio95"; + function =3D "blsp_i2c7"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { + pins =3D "gpio94", "gpio95"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_spi3_default: blsp2-spi3-default-state { + cs-pins { + pins =3D "gpio94"; + function =3D "blsp_spi7"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + + spi-pins { + pins =3D "gpio92", "gpio93", "gpio95"; + function =3D "blsp_spi7"; + drive-strength =3D <12>; + bias-disable; + }; + }; + + blsp2_spi3_sleep: blsp2-spi3-sleep-state { + pins =3D "gpio92", "gpio93", "gpio94", "gpio95"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp2_i2c4_default: blsp2-i2c4-default-state { + pins =3D "gpio98", "gpio99"; + function =3D "blsp_i2c8"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { + pins =3D "gpio98", "gpio99"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_spi4_default: blsp2-spi4-default-state { + cs-pins { + pins =3D "gpio98"; + function =3D "blsp_spi8"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + + spi-pins { + pins =3D "gpio96", "gpio97", "gpio99"; + function =3D "blsp_spi8"; + drive-strength =3D <12>; + bias-disable; + }; + }; + + blsp2_spi4_sleep: blsp2-spi4-sleep-state { + pins =3D "gpio96", "gpio97", "gpio98", "gpio99"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + sdc1_default: sdc1-default-state { + clk-pins { + pins =3D "sdc1_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc1_cmd"; + drive-strength =3D <10>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc1_data"; + drive-strength =3D <10>; + bias-pull-up; + }; + + rclk-pins { + pins =3D "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins =3D "sdc1_clk"; + drive-strength =3D <2>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc1_cmd"; + drive-strength =3D <2>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc1_data"; + drive-strength =3D <2>; + bias-pull-up; + }; + + rclk-pins { + pins =3D "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins =3D "sdc2_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + sdc2_cmd_default: cmd-pins { + pins =3D "sdc2_cmd"; + drive-strength =3D <16>; + bias-pull-up; + }; + + sdc2_data_default: data-pins { + pins =3D "sdc2_data"; + drive-strength =3D <16>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins =3D "sdc2_clk"; + drive-strength =3D <2>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc2_cmd"; + drive-strength =3D <2>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc2_data"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + }; + + gcc: clock-controller@1800000 { + compatible =3D "qcom,gcc-msm8952"; + reg =3D <0x01800000 0x80000>; + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + tcsr_mutex: hwlock@1905000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x01905000 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: syscon@1937000 { + compatible =3D "qcom,tcsr-msm8952", "syscon"; + reg =3D <0x01937000 0x30000>; + }; + + mdss: display-subsystem@1a00000 { + compatible =3D "qcom,mdss"; + reg =3D <0x01a00000 0x1000>, + <0x01ac8000 0x3000>; + reg-names =3D "mdss_phys", + "vbif_phys"; + + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + + power-domains =3D <&gcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", + "bus", + "vsync"; + + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <1>; + + resets =3D <&gcc GCC_MDSS_BCR>; + + status =3D "disabled"; + + mdss_mdp: display-controller@1a01000 { + compatible =3D "qcom,msm8952-mdp5", "qcom,mdp5"; + reg =3D <0x01a01000 0x89000>; + reg-names =3D "mdp_phys"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", + "bus", + "core", + "vsync"; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&gcc MDSS_GDSC>; + + iommus =3D <&apps_iommu 0x17>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_mdp_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-160000000 { + opp-hz =3D /bits/ 64 <160000000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-266670000 { + opp-hz =3D /bits/ 64 <266670000>; + required-opps =3D <&rpmpd_opp_svs_plus>; + }; + + opp-320000000 { + opp-hz =3D /bits/ 64 <320000000>; + required-opps =3D <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@1a98000 { + compatible =3D "qcom,msm8916-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg =3D <0x01a98000 0x25c>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + assigned-clocks =3D <&gcc BYTE0_CLK_SRC>, + <&gcc PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + clocks =3D <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names =3D "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + phys =3D <&mdss_dsi0_phy>; + + operating-points-v2 =3D <&dsi0_opp_table>; + power-domains =3D <&gcc MDSS_GDSC>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&mdss_mdp_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + dsi0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-120000000 { + opp-hz =3D /bits/ 64 <120000000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi0_phy: phy@1a98300 { + compatible =3D "qcom,dsi-phy-28nm-lp"; + reg =3D <0x01a98300 0xd4>, + <0x01a98500 0x280>, + <0x01a98780 0x30>; + reg-names =3D "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", "ref"; + + status =3D "disabled"; + }; + }; + + gpu: gpu@1c00000 { + compatible =3D "qcom,adreno-405.0", "qcom,adreno"; + reg =3D <0x01c00000 0x10000>; + reg-names =3D "kgsl_3d0_reg_memory"; + interrupts =3D ; + interrupt-names =3D "kgsl_3d0_irq"; + clocks =3D <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_OXILI_GMEM_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc GFX3D_CLK_SRC>, + <&gcc GCC_OXILI_TIMER_CLK>; + clock-names =3D "core", + "iface", + "mem", + "mem_iface", + "alt_mem_iface", + "gfx3d", + "rbbmtimer"; + power-domains =3D <&gcc OXILI_GX_GDSC>; + operating-points-v2 =3D <&opp_table>; + iommus =3D <&gpu_iommu 0>, <&gpu_iommu 1>; + #cooling-cells =3D <2>; + + status =3D "disabled"; + + opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-19200000 { + opp-hz =3D /bits/ 64 <19200000>; + required-opps =3D <&rpmpd_opp_min_svs>; + }; + + opp-240000000 { + opp-hz =3D /bits/ 64 <240000000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + required-opps =3D <&rpmpd_opp_svs_plus>; + }; + + opp-465000000 { + opp-hz =3D /bits/ 64 <465000000>; + required-opps =3D <&rpmpd_opp_nom>; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + required-opps =3D <&rpmpd_opp_nom_plus>; + }; + + opp-550000000 { + opp-hz =3D /bits/ 64 <550000000>; + required-opps =3D <&rpmpd_opp_turbo>; + }; + }; + }; + + apps_iommu: iommu@1e20000 { + compatible =3D "qcom,msm8952-iommu", "qcom,msm-iommu-v2"; + ranges =3D <0 0x01e20000 0x20000>; + + clocks =3D <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names =3D "iface", "bus"; + + #address-cells =3D <1>; + #size-cells =3D <1>; + #iommu-cells =3D <1>; + + qcom,iommu-secure-id =3D <17>; + + /* CPP */ + iommu-ctx@13000 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x13000 0x1000>; + interrupts =3D ; + }; + + /* JPEG ENC0 */ + iommu-ctx@14000 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x14000 0x1000>; + interrupts =3D ; + }; + + /* VFE */ + iommu-ctx@15000 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x15000 0x1000>; + interrupts =3D ; + }; + + /* VENUS NS */ + iommu-ctx@16000 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x16000 0x1000>; + interrupts =3D ; + }; + + /* MDP0 */ + iommu-ctx@17000 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x17000 0x1000>; + interrupts =3D ; + }; + + /* PRONTO */ + iommu-ctx@18000 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x18000 0x1000>; + interrupts =3D ; + }; + }; + + gpu_iommu: iommu@1f08000 { + compatible =3D "qcom,msm8952-iommu", "qcom,msm-iommu-v2"; + ranges =3D <0 0x01f08000 0x10000>; + + clocks =3D <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>; + clock-names =3D "iface", "bus"; + + #address-cells =3D <1>; + #size-cells =3D <1>; + #iommu-cells =3D <1>; + + qcom,iommu-secure-id =3D <18>; + + /* gfx3d user */ + iommu-ctx@0 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x0 0x1000>; + interrupts =3D ; + qcom,ctx-asid =3D <0>; + }; + + /* gfx3d secure */ + iommu-ctx@1000 { + compatible =3D "qcom,msm-iommu-v2-sec"; + reg =3D <0x1000 0x1000>; + interrupts =3D ; + qcom,ctx-asid =3D <2>; + }; + + /* gfx3d priv */ + iommu-ctx@3000 { + compatible =3D "qcom,msm-iommu-v2-sec"; + reg =3D <0x3000 0x1000>; + interrupts =3D ; + qcom,ctx-asid =3D <1>; + }; + }; + + spmi_bus: spmi@200f000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0x0200f000 0x001000>, + <0x02400000 0x800000>, + <0x02c00000 0x800000>, + <0x03800000 0x200000>, + <0x0200a000 0x002100>; + reg-names =3D "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupt-names =3D "periph_irq"; + interrupts-extended =3D <&mpm 62 IRQ_TYPE_LEVEL_HIGH>; + #address-cells =3D <2>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <4>; + qcom,ee =3D <0>; + qcom,channel =3D <0>; + }; + + bam_dmux_dma: dma-controller@4044000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x04044000 0x19000>; + interrupts =3D ; + #dma-cells =3D <1>; + + num-channels =3D <6>; + qcom,ee =3D <0>; + qcom,num-ees =3D <1>; + qcom,powered-remotely; + + status =3D "disabled"; + }; + + sdhc_1: mmc@7824900 { + compatible =3D "qcom,msm8952-sdhci", "qcom,sdhci-msm-v4"; + reg =3D <0x07824900 0x500>, <0x07824000 0x800>, <0x7824e00 0x200>; + reg-names =3D "hc", "core", "cqhci"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", "core", "xo"; + + resets =3D <&gcc GCC_SDCC1_BCR>; + + pinctrl-0 =3D <&sdc1_default>; + pinctrl-1 =3D <&sdc1_sleep>; + pinctrl-names =3D "default", "sleep"; + + power-domains =3D <&rpmpd RPMPD_VDDCX>; + + mmc-hs400-1_8v; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + bus-width =3D <8>; + non-removable; + + status =3D "disabled"; + }; + + sdhc_2: mmc@7864900 { + compatible =3D "qcom,msm8952-sdhci", "qcom,sdhci-msm-v4"; + reg =3D <0x07864900 0x11c>, <0x07864000 0x800>; + reg-names =3D "hc", "core"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", "core", "xo"; + + resets =3D <&gcc GCC_SDCC2_BCR>; + + pinctrl-0 =3D <&sdc2_default>; + pinctrl-1 =3D <&sdc2_sleep>; + pinctrl-names =3D "default", "sleep"; + + power-domains =3D <&rpmpd RPMPD_VDDCX>; + + bus-width =3D <4>; + + status =3D "disabled"; + }; + + blsp1_dma: dma-controller@7884000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x07884000 0x1f000>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "bam_clk"; + #dma-cells =3D <1>; + num-channels =3D <12>; + qcom,num-ees =3D <4>; + qcom,ee =3D <0>; + qcom,controlled-remotely; + }; + + blsp1_uart1: serial@78af000 { + compatible =3D "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg =3D <0x078af000 0x200>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 0>, <&blsp1_dma 1>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_uart1_console_default>; + pinctrl-1 =3D <&blsp1_uart1_console_sleep>; + pinctrl-names =3D "default", "sleep"; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + operating-points-v2 =3D <&uart_opp_table>; + + status =3D "disabled"; + }; + + blsp1_uart2: serial@78b0000 { + compatible =3D "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg =3D <0x078b0000 0x200>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 2>, <&blsp1_dma 3>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_uart2_default>; + pinctrl-1 =3D <&blsp1_uart2_sleep>; + pinctrl-names =3D "default", "sleep"; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + operating-points-v2 =3D <&uart_opp_table>; + + status =3D "disabled"; + }; + + blsp1_i2c1: i2c@78b5000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b5000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp1_dma 4>, <&blsp1_dma 5>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_i2c1_default>; + pinctrl-1 =3D <&blsp1_i2c1_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + required-opps =3D <&rpmpd_opp_svs>; + + status =3D "disabled"; + }; + + blsp1_spi1: spi@78b5000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x078b5000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 4>, <&blsp1_dma 5>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_spi1_default>; + pinctrl-1 =3D <&blsp1_spi1_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + operating-points-v2 =3D <&spi_opp_table>; + + status =3D "disabled"; + }; + + blsp1_i2c2: i2c@78b6000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b6000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_i2c2_default>; + pinctrl-1 =3D <&blsp1_i2c2_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + required-opps =3D <&rpmpd_opp_svs>; + + status =3D "disabled"; + }; + + blsp1_spi2: spi@78b6000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x078b6000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_spi2_default>; + pinctrl-1 =3D <&blsp1_spi2_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + operating-points-v2 =3D <&spi_opp_table>; + + status =3D "disabled"; + }; + + blsp1_i2c3: i2c@78b7000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b7000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp1_dma 8>, <&blsp1_dma 9>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_i2c3_default>; + pinctrl-1 =3D <&blsp1_i2c3_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + required-opps =3D <&rpmpd_opp_svs>; + + status =3D "disabled"; + }; + + blsp1_spi3: spi@78b7000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x078b7000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 8>, <&blsp1_dma 9>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_spi3_default>; + pinctrl-1 =3D <&blsp1_spi3_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + operating-points-v2 =3D <&spi_opp_table>; + + status =3D "disabled"; + }; + + blsp1_i2c4: i2c@78b8000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b8000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp1_dma 10>, <&blsp1_dma 11>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_i2c4_default>; + pinctrl-1 =3D <&blsp1_i2c4_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + required-opps =3D <&rpmpd_opp_svs>; + + status =3D "disabled"; + }; + + blsp1_spi4: spi@78b8000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x078b8000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 10>, <&blsp1_dma 11>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_spi4_default>; + pinctrl-1 =3D <&blsp1_spi4_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + operating-points-v2 =3D <&spi_opp_table>; + + status =3D "disabled"; + }; + + usb_dma: dma-controller@78c4000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x078c4000 0x17000>; + interrupts =3D ; + #dma-cells =3D <1>; + num-channels =3D <4>; + qcom,num-ees =3D <4>; + qcom,ee =3D <0>; + qcom,controlled-remotely; + }; + + usb: usb@78db000 { + compatible =3D "qcom,ci-hdrc"; + reg =3D <0x078db000 0x200>, + <0x078db200 0x200>; + interrupts-extended =3D <&mpm 58 IRQ_TYPE_LEVEL_HIGH>, + <&mpm 49 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names =3D "iface", + "core"; + assigned-clocks =3D <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates =3D <80000000>; + resets =3D <&gcc GCC_USB_HS_BCR>; + reset-names =3D "core"; + hnp-disable; + srp-disable; + adp-disable; + ahb-burst-config =3D <0>; + dr_mode =3D "otg"; + phy_type =3D "ulpi"; + phys =3D <&usb_hs_phy>; + phy-names =3D "usb-phy"; + #reset-cells =3D <1>; + + status =3D "disabled"; + }; + + blsp2_dma: dma-controller@7ac4000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x07ac4000 0x1f000>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "bam_clk"; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + qcom,controlled-remotely; + }; + + blsp2_i2c1: i2c@7af5000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x07af5000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp2_dma 4>, <&blsp2_dma 5>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp2_i2c1_default>; + pinctrl-1 =3D <&blsp2_i2c1_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + required-opps =3D <&rpmpd_opp_svs>; + + status =3D "disabled"; + }; + + blsp2_spi1: spi@7af5000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x07af5000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp2_dma 4>, <&blsp2_dma 5>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp2_spi1_default>; + pinctrl-1 =3D <&blsp2_spi1_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + operating-points-v2 =3D <&spi_opp_table>; + + status =3D "disabled"; + }; + + blsp2_i2c2: i2c@7af6000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x07af6000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp2_dma 6>, <&blsp2_dma 7>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp2_i2c2_default>; + pinctrl-1 =3D <&blsp2_i2c2_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + required-opps =3D <&rpmpd_opp_svs>; + + status =3D "disabled"; + }; + + blsp2_spi2: spi@7af6000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x07af6000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp2_dma 6>, <&blsp2_dma 7>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp2_spi2_default>; + pinctrl-1 =3D <&blsp2_spi2_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + operating-points-v2 =3D <&spi_opp_table>; + + status =3D "disabled"; + }; + + blsp2_i2c3: i2c@7af7000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x07af7000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp2_dma 8>, <&blsp2_dma 9>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp2_i2c3_default>; + pinctrl-1 =3D <&blsp2_i2c3_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + required-opps =3D <&rpmpd_opp_svs>; + + status =3D "disabled"; + }; + + blsp2_spi3: spi@7af7000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x07af7000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp2_dma 8>, <&blsp2_dma 9>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp2_spi3_default>; + pinctrl-1 =3D <&blsp2_spi3_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + operating-points-v2 =3D <&spi_opp_table>; + + status =3D "disabled"; + }; + + blsp2_i2c4: i2c@7af8000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x07af8000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp2_dma 10>, <&blsp2_dma 11>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp2_i2c4_default>; + pinctrl-1 =3D <&blsp2_i2c4_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + required-opps =3D <&rpmpd_opp_svs>; + + status =3D "disabled"; + }; + + blsp2_spi4: spi@7af8000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x07af8000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp2_dma 10>, <&blsp2_dma 11>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp2_spi4_default>; + pinctrl-1 =3D <&blsp2_spi4_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + operating-points-v2 =3D <&spi_opp_table>; + + status =3D "disabled"; + }; + + imem: sram@8600000 { + compatible =3D "qcom,msm8976-imem", + "syscon", "simple-mfd"; + reg =3D <0x08600000 0x1000>; + + ranges =3D <0 0x08600000 0x1000>; + #size-cells =3D <1>; + #address-cells =3D <1>; + + pil-reloc@94c { + compatible =3D "qcom,pil-reloc-info"; + reg =3D <0x94c 0xc8>; + }; + }; + + intc: interrupt-controller@b000000 { + compatible =3D "qcom,msm-qgic2"; + reg =3D <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + interrupt-controller; + #interrupt-cells =3D <3>; + }; + + apcs1: mailbox@b011000 { + compatible =3D "qcom,msm8939-apcs-kpss-global", "syscon"; + reg =3D <0x0b011000 0x1000>; + #mbox-cells =3D <1>; + clocks =3D <&a53pll_c1>, + <&gcc GPLL0_VOTE>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "pll", + "aux", + "ref"; + #clock-cells =3D <0>; + }; + + a53pll_c1: clock@b016000 { + compatible =3D "qcom,msm8939-a53pll"; + reg =3D <0x0b016000 0x40>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + #clock-cells =3D <0>; + operating-points-v2 =3D <&pll_opp_table_c1>; + + pll_opp_table_c1: opp-table { + compatible =3D "operating-points-v2"; + + opp-499200000 { + opp-hz =3D /bits/ 64 <499200000>; + }; + + opp-806400000 { + opp-hz =3D /bits/ 64 <806400000>; + }; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + + opp-1344000000 { + opp-hz =3D /bits/ 64 <1344000000>; + }; + + opp-1440000000 { + opp-hz =3D /bits/ 64 <1440000000>; + }; + + opp-1516800000 { + opp-hz =3D /bits/ 64 <1516800000>; + }; + + opp-1651200000 { + opp-hz =3D /bits/ 64 <1651200000>; + }; + }; + }; + + watchdog@b017000 { + compatible =3D "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; + reg =3D <0x0b017000 0x1000>; + interrupts =3D , + ; + clocks =3D <&sleep_clk>; + }; + + acc4: clock-controller@b088000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b088000 0x1000>; + }; + + acc5: clock-controller@b098000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b098000 0x1000>; + }; + + acc6: clock-controller@b0a8000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b0a8000 0x1000>; + }; + + acc7: clock-controller@b0b8000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b0b8000 0x1000>; + }; + + apcs0: mailbox@b111000 { + compatible =3D "qcom,msm8939-apcs-kpss-global", "syscon"; + reg =3D <0x0b111000 0x1000>; + #mbox-cells =3D <1>; + clocks =3D <&a53pll_c0>, + <&gcc GPLL0_VOTE>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "pll", + "aux", + "ref"; + #clock-cells =3D <0>; + }; + + a53pll_c0: clock@b116000 { + compatible =3D "qcom,msm8939-a53pll"; + reg =3D <0x0b116000 0x40>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + #clock-cells =3D <0>; + operating-points-v2 =3D <&pll_opp_table_c0>; + + pll_opp_table_c0: opp-table { + compatible =3D "operating-points-v2"; + + opp-403200000 { + opp-hz =3D /bits/ 64 <403200000>; + }; + + opp-806400000 { + opp-hz =3D /bits/ 64 <806400000>; + }; + + opp-998400000 { + opp-hz =3D /bits/ 64 <998400000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + + opp-1209600000 { + opp-hz =3D /bits/ 64 <1209600000>; + }; + }; + }; + + timer@b120000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0b120000 0x1000>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clock-frequency =3D <19200000>; + + frame@b121000 { + reg =3D <0x0b121000 0x1000>, <0x0b122000 0x1000>; + interrupts =3D , + ; + frame-number =3D <0>; + }; + + frame@b123000 { + reg =3D <0x0b123000 0x1000>; + interrupts =3D ; + frame-number =3D <1>; + + status =3D "disabled"; + }; + + frame@b124000 { + reg =3D <0x0b124000 0x1000>; + interrupts =3D ; + frame-number =3D <2>; + + status =3D "disabled"; + }; + + frame@b125000 { + reg =3D <0x0b125000 0x1000>; + interrupts =3D ; + frame-number =3D <3>; + + status =3D "disabled"; + }; + + frame@b126000 { + reg =3D <0x0b126000 0x1000>; + interrupts =3D ; + frame-number =3D <4>; + + status =3D "disabled"; + }; + + frame@b127000 { + reg =3D <0x0b127000 0x1000>; + interrupts =3D ; + frame-number =3D <5>; + + status =3D "disabled"; + }; + + frame@b128000 { + reg =3D <0x0b128000 0x1000>; + interrupts =3D ; + frame-number =3D <6>; + + status =3D "disabled"; + }; + }; + + acc0: clock-controller@b188000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b188000 0x1000>; + }; + + acc1: clock-controller@b198000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b198000 0x1000>; + }; + + acc2: clock-controller@b1a8000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b1a8000 0x1000>; + }; + + acc3: clock-controller@b1b8000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b1b8000 0x1000>; + }; + + a53pll_cci: clock@b1d0000 { + compatible =3D "qcom,msm8939-a53pll"; + reg =3D <0x0b1d0000 0x40>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + #clock-cells =3D <0>; + }; + + apcs2: mailbox@b1d1000 { + compatible =3D "qcom,msm8939-apcs-kpss-global", "syscon"; + reg =3D <0x0b1d1000 0x1000>; + clocks =3D <&a53pll_cci>, + <&gcc GPLL0_VOTE>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "pll", + "aux", + "ref"; + #clock-cells =3D <0>; + #mbox-cells =3D <1>; + }; + + adsp: remoteproc@c200000 { + compatible =3D "qcom,msm8996-adsp-pil"; + reg =3D <0x0c200000 0x100>; + + interrupts-extended =3D <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", "fatal", "ready", "handover", "stop-ack"; + + clocks =3D <&rpmcc RPM_SMD_BB_CLK1>; + clock-names =3D "xo"; + + power-domains =3D <&rpmpd RPMPD_VDDCX>; + power-domain-names =3D "cx"; + + memory-region =3D <&adsp_fw_mem>; + + qcom,smem-states =3D <&adsp_smp2p_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + smd-edge { + interrupts =3D ; + + mboxes =3D <&apcs1 8>; + + qcom,smd-edge =3D <1>; + qcom,remote-pid =3D <2>; + }; + }; + }; + + thermal-zones { + aoss0-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 0>; + + trips { + aoss0_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + modem-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 1>; + + trips { + modem_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + qdsp-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 2>; + + trips { + qdsp_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + camera-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 3>; + + trips { + camera_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + l2-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 4>; + + trips { + l2_alert0: trip-point0 { + temperature =3D <50000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + l2_alert1: trip-point1 { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + l2_crit: l2-crit { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 5>; + + cooling-maps { + map0 { + trip =3D <&cpu4_alert1>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu4_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu4_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu4_crit: cpu-crit { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 6>; + + cooling-maps { + map0 { + trip =3D <&cpu5_alert1>; + cooling-device =3D <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu5_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu5_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu5_crit: cpu-crit { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 7>; + + cooling-maps { + map0 { + trip =3D <&cpu6_alert1>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu6_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu6_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu6_crit: cpu-crit { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 8>; + + cooling-maps { + map0 { + trip =3D <&cpu7_alert1>; + cooling-device =3D <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu7_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu7_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu7_crit: cpu-crit { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu0-3-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 9>; + + cooling-maps { + map0 { + trip =3D <&cpu0_alert1>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu0_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu0_crit: cpu-crit { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 10>; + + trips { + gpu_crit: gpu-crit { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + clock-frequency =3D <19200000>; + }; +}; --=20 2.55.0 From nobody Sat Oct 24 20:10:37 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 405C1364EAB; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261011-msm8952-initial-support-v5-6-1857074992ec@mainlining.org> References: <20261011-msm8952-initial-support-v5-0-1857074992ec@mainlining.org> In-Reply-To: <20261011-msm8952-initial-support-v5-0-1857074992ec@mainlining.org> To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Konrad Dybcio , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Bjorn Andersson , Abel Vesa , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir , Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1791737529; l=1656; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=WcI6NF2jH7/1jsgO/qq/6GfopHH27DV/LBlXLYlg2yo=; b=Rd1+yUTn+zEQ8PrK7lbHPgXmB+k4Y09qQsr7ueDMR9GqQWjKcGeNJnMzBDj5zaF9wSZpPUlCP 3XGa5o9eOtPA2OOvesO8/wWA+wxNKN7K2Y9aucmrE7DH1w42JQVuOIw X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir GT970 works with GT911 driver, document it to be used with GT911 compatible. Acked-by: Krzysztof Kozlowski Signed-off-by: Muzaffer Kadir --- .../bindings/input/touchscreen/goodix.yaml | 35 ++++++++++++------= ---- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/input/touchscreen/goodix.yam= l b/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml index a26a54d63a1c..4be2c137abd7 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml @@ -14,21 +14,26 @@ allOf: =20 properties: compatible: - enum: - - goodix,gt1151 - - goodix,gt1158 - - goodix,gt5663 - - goodix,gt5688 - - goodix,gt911 - - goodix,gt9110 - - goodix,gt912 - - goodix,gt9147 - - goodix,gt917s - - goodix,gt927 - - goodix,gt9271 - - goodix,gt928 - - goodix,gt9286 - - goodix,gt967 + oneOf: + - enum: + - goodix,gt1151 + - goodix,gt1158 + - goodix,gt5663 + - goodix,gt5688 + - goodix,gt911 + - goodix,gt9110 + - goodix,gt912 + - goodix,gt9147 + - goodix,gt917s + - goodix,gt927 + - goodix,gt9271 + - goodix,gt928 + - goodix,gt9286 + - goodix,gt967 + - items: + - enum: + - goodix,gt970 + - const: goodix,gt911 =20 reg: enum: [ 0x5d, 0x14 ] --=20 2.55.0 From nobody Sat Oct 24 20:10:37 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 406BF3655C0; Sun, 11 Oct 2026 16:52:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791737533; cv=none; b=pU9NB5VbosqdNZQLm21FShkiPxmhIn4Od+/VggmBix/YtZuUtEprbjCYuV3+a7vhLZly1Z0SHjGQXKbNIJRO5bjWBaK1U3pJEYB8UqfqGkuJfuAT7Y4hIJgrKTPH7G2O8i5mJGqKrnhu5J0JMsXs5fHarE7LVhqEgik68EoEVlY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791737533; c=relaxed/simple; bh=6SRT3574ngYng/Gk5dyY/GIUvlILwgq/HP04R7VdNtc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gnvfF9O61dX/K94ffpG7DsND4VwC5GC1h2T5iBNmw3XfmvlAS3QjdOZZAUztpP8Qqh6Xu/g5sM5DlZuZQpCCe1dEZQx3hUidR+yCMmiL93/FvZB1hL5O8141bHku/U0ZZl8VTSP8dE6Bh7wn0cIdvwK/E6Ue8/M9pYg/dP1LKGs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=S7vMAKCG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="S7vMAKCG" Received: by smtp.kernel.org (Postfix) with ESMTPS id C95C4C4AF60; Sun, 11 Oct 2026 16:52:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1791737532; bh=6SRT3574ngYng/Gk5dyY/GIUvlILwgq/HP04R7VdNtc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=S7vMAKCG7mNMCt8nsAjhhG9O1d8k+Dm0bFB16E1iKii4Mf+JHLoL9wl2vEI7Aojfu yao3cP1PJGn2g1MHwFTyJBwEs3Yvzv5Rlosd9pY1zxkre4resogRPuCVFlqr354bjm m4dDugGBdAYDSoHeK4iLyeW5v+pjfuc/58CgSvZMOmLWqhsagZqQhY9QR21ssh+dUT oNYykMcb/eKxJru05mKpOrOhxQzeWn9PPdETzVbMzxBeNVtCsaXGWy71XJtTGB2dgH XcLp/7dS7jLBOkM57+AvX6jXDvh7I6s+briOSgrQGffqg56NyE2ra9RKTPigxL1zpW m8F/6lu3Flx7w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4F77CA9ECF; Sun, 11 Oct 2026 16:52:12 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sun, 11 Oct 2026 19:51:29 +0300 Subject: [PATCH v5 7/7] arm64: dts: qcom: generalmobile-shamrock: new device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261011-msm8952-initial-support-v5-7-1857074992ec@mainlining.org> References: <20261011-msm8952-initial-support-v5-0-1857074992ec@mainlining.org> In-Reply-To: <20261011-msm8952-initial-support-v5-0-1857074992ec@mainlining.org> To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Konrad Dybcio , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Bjorn Andersson , Abel Vesa , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1791737529; l=11249; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=ffFFkJidU1ps/YRl6Y6TqqB8qywb5ps7t3vcLKjZ4Kg=; b=9BwtJcjzC9QDtFG5mKo9e23tXgoR6sAnJdV7OfCi1P6TXNcmr2pU9WXQYfmeFVT2bJvr967+p mwjN70tNdxLBOo+Ol84f4zETyQipXIc7tDpwuuIHDatfWXz9hojT13K X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add General Mobile Shamrock (GM 5 Plus). Shamrock is designed similar to L9300. Downstream reference is [1]. [1] https://github.com/Asderdd/android_kernel_generalmobile_shamrock/blob/c= m-14.1/arch/arm/boot/dts/qcom/msm8952-l9300.dtsi Signed-off-by: Muzaffer Kadir --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/msm8952-generalmobile-shamrock.dts | 435 +++++++++++++++++= ++++ 2 files changed, 436 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 88230c4e00ea..898df8754657 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -130,6 +130,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-samsung-a7.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-sony-xperia-kanuti-tulip.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-wingtech-wt82918.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-wingtech-wt82918hd.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D msm8952-generalmobile-shamrock.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8953-flipkart-rimob.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8953-motorola-deen.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8953-motorola-potter.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8952-generalmobile-shamrock.dts b/= arch/arm64/boot/dts/qcom/msm8952-generalmobile-shamrock.dts new file mode 100644 index 000000000000..9114b232cb1b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8952-generalmobile-shamrock.dts @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8952.dtsi" +#include "pm8950.dtsi" +#include "pmi8950.dtsi" +#include +#include + +/ { + model =3D "General Mobile GM 5 Plus"; + compatible =3D "generalmobile,shamrock", "qcom,msm8952"; + chassis-type =3D "handset"; + qcom,msm-id =3D ; + qcom,board-id =3D ; + + aliases { + mmc0 =3D &sdhc_1; /* SDC1 eMMC slot */ + mmc1 =3D &sdhc_2; /* SDC2 SD card slot */ + serial0 =3D &blsp1_uart2; + }; + + battery: battery { + compatible =3D "simple-battery"; + + charge-term-current-microamp =3D <100000>; + charge-full-design-microamp-hours =3D <3100000>; + constant-charge-current-max-microamp =3D <3000000>; + constant-charge-voltage-max-microvolt =3D <4400000>; + voltage-min-design-microvolt =3D <3400000>; + voltage-max-design-microvolt =3D <4400000>; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + + framebuffer { + compatible =3D "simple-framebuffer"; + memory-region =3D <&cont_splash_mem>; + + width =3D <1080>; + height =3D <1920>; + stride =3D <(1080 * 3)>; + format =3D "r8g8b8"; + + power-domains =3D <&gcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + }; + }; + + /* Front Flash */ + flash-led-controller { + compatible =3D "sgmicro,sgm3140"; + + enable-gpios =3D <&tlmm 33 GPIO_ACTIVE_HIGH>; + flash-gpios =3D <&tlmm 128 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&front_flash_default>; + pinctrl-names =3D "default"; + + front_flash_led: led { + function =3D LED_FUNCTION_FLASH; + color =3D ; + flash-max-microamp =3D <1000000>; + led-max-microamp =3D <625000>; + flash-max-timeout-us =3D <1280000>; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&gpio_hall_sensor_default>, <&gpio_keys_default>; + pinctrl-names =3D "default"; + + button-volume-up { + label =3D "Volume Up"; + gpios =3D <&tlmm 85 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + wakeup-source; + linux,code =3D ; + }; + + event-hall-sensor { + label =3D "Hall Effect Sensor"; + gpios =3D <&tlmm 46 GPIO_ACTIVE_LOW>; + wakeup-source; + linux,input-type =3D ; + linux,code =3D ; + linux,can-disable; + }; + }; + + multi-led { + compatible =3D "leds-group-multicolor"; + color =3D ; + function =3D LED_FUNCTION_INDICATOR; + leds =3D <&red_status>, <&green_status>, <&blue_status>; + }; + + reserved-memory { + cont_splash_mem: cont-splash@83200000 { + reg =3D <0x0 0x83200000 0x0 (1080 * 1920 * 3)>; + no-map; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph-pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&adsp { + status =3D "okay"; +}; + +&blsp1_i2c2 { + status =3D "okay"; + /* SMB1351 @1d charger */ + /* wsa881x-i2c @e @44 @f @45 audio amplifier */ +}; + +&blsp1_i2c3 { + status =3D "okay"; + + /* himax,852x@48 Touchscreen */ + + touchscreen@5d { + compatible =3D "goodix,gt970", "goodix,gt911"; + reg =3D <0x5d>; + interrupts-extended =3D <&tlmm 65 IRQ_TYPE_EDGE_FALLING>; + irq-gpios =3D <&tlmm 65 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&tlmm 64 GPIO_ACTIVE_HIGH>; + AVDD28-supply =3D <&pm8950_l10>; + VDDIO-supply =3D <&pm8950_l6>; + + pinctrl-0 =3D <&touchscreen_default>; + pinctrl-names =3D "default"; + + touchscreen-size-x =3D <1080>; + touchscreen-size-y =3D <1920>; + }; +}; + +&blsp2_i2c1 { + status =3D "okay"; + + /* FUSB301 @25 USB-C Controller */ + + tpa6130a2: audio-controller@60 { + compatible =3D "ti,tpa6130a2"; + reg =3D <0x60>; + pinctrl-0 =3D <&tpa6130a2_default>; + pinctrl-names =3D "default"; + power-gpio =3D <&tlmm 61 GPIO_ACTIVE_HIGH>; + Vdd-supply =3D <&pm8950_l22>; + }; + + tusb320: usb@67 { + compatible =3D "ti,tusb320"; + reg =3D <0x67>; + interrupts-extended =3D <&tlmm 45 IRQ_TYPE_EDGE_FALLING>; + }; + + led-controller@68 { + compatible =3D "si-en,sn3193"; + reg =3D <0x68>; + + shutdown-gpios =3D <&tlmm 68 GPIO_ACTIVE_HIGH>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + red_status: led@1 { + reg =3D <1>; + label =3D "red:status"; + led-max-microamp =3D <17500>; + }; + + green_status: led@2 { + reg =3D <2>; + label =3D "green:status"; + led-max-microamp =3D <17500>; + }; + + blue_status: led@3 { + reg =3D <3>; + label =3D "blue:status"; + led-max-microamp =3D <17500>; + }; + }; +}; + +&pm8950_spmi_regulators { + /* PM8950 S5 + S6 =3D VDD_APC supply */ + pm8950_s5: s5 { + regulator-min-microvolt =3D <1050000>; + regulator-max-microvolt =3D <1350000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&pm8950_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&pmi8950_wled { + qcom,enabled-strings =3D <0 1>; + qcom,current-limit-microamp =3D <30000>; + qcom,ovp-millivolt =3D <29500>; + qcom,external-pfet; + + status =3D "okay"; +}; + +&ramoops_mem { + status =3D "okay"; +}; + +&rpm_requests { + pm8950_rpm_regulators: regulators { + compatible =3D "qcom,rpm-pm8950-regulators"; + vdd_s1-supply =3D <&vph_pwr>; + vdd_s2-supply =3D <&vph_pwr>; + vdd_s3-supply =3D <&vph_pwr>; + vdd_s4-supply =3D <&vph_pwr>; + vdd_s6-supply =3D <&vph_pwr>; + vdd_l1_l19-supply =3D <&pm8950_s3>; + vdd_l2_l23-supply =3D <&pm8950_s3>; + vdd_l3-supply =3D <&pm8950_s3>; + vdd_l5_l6_l7_l16-supply =3D <&pm8950_s4>; + vdd_l8_l11_l12_l17_l22-supply =3D <&vph_pwr>; + vdd_l9_l10_l13_l14_l15_l18-supply =3D <&vph_pwr>; + + pm8950_s1: s1 { + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1225000>; + }; + + pm8950_s3: s3 { + regulator-min-microvolt =3D <1300000>; + regulator-max-microvolt =3D <1300000>; + }; + + pm8950_s4: s4 { + regulator-min-microvolt =3D <2050000>; + regulator-max-microvolt =3D <2050000>; + }; + + pm8950_l2: l2 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + /* pm8950_l3 is managed by rpmpd (RPMPD_VDDMX) */ + + pm8950_l5: l5 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8950_l6: l6 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8950_l7: l7 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8950_l8: l8 { + regulator-min-microvolt =3D <2850000>; + regulator-max-microvolt =3D <2900000>; + }; + + pm8950_l9: l9 { + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8950_l10: l10 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + }; + + pm8950_l11: l11 { + regulator-min-microvolt =3D <2950000>; + regulator-max-microvolt =3D <2950000>; + regulator-allow-set-load; + regulator-system-load =3D <200000>; + }; + + pm8950_l12: l12 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2950000>; + }; + + pm8950_l13: l13 { + regulator-min-microvolt =3D <3075000>; + regulator-max-microvolt =3D <3075000>; + }; + + pm8950_l14: l14 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8950_l15: l15 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8950_l16: l16 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8950_l17: l17 { + regulator-min-microvolt =3D <2850000>; + regulator-max-microvolt =3D <2850000>; + }; + + pm8950_l19: l19 { + regulator-min-microvolt =3D <1225000>; + regulator-max-microvolt =3D <1350000>; + }; + + pm8950_l22: l22 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + }; + + pm8950_l23: l23 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply =3D <&pm8950_l8>; + vqmmc-supply =3D <&pm8950_l5>; + + status =3D "okay"; +}; + +&sdhc_2 { + cd-gpios =3D <&tlmm 67 GPIO_ACTIVE_HIGH>; + vmmc-supply =3D <&pm8950_l11>; + vqmmc-supply =3D <&pm8950_l12>; + + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32768>; +}; + +&tlmm { + gpio-reserved-ranges =3D <20 4>; /* Unknown, TZ Protected */ + + gpio_hall_sensor_default: gpio-hall-sensor-default-state { + pins =3D "gpio46"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-pull-up; + }; + + tpa6130a2_default: tpa6130a2-default-state { + pins =3D "gpio61"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-down; + }; + + touchscreen_default: touchscreen-default-state { + reset-pins { + pins =3D "gpio64"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + irq-pins { + pins =3D "gpio65"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + gpio_keys_default: gpio-keys-default-state { + pins =3D "gpio85"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + front_flash_default: front-flash-default-state { + enable-pins { + pins =3D "gpio33"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + flash-pins { + pins =3D "gpio128"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; +}; + +&xo_board { + clock-frequency =3D <19200000>; +}; --=20 2.55.0