From nobody Fri Oct 2 01:56:21 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6665489FDF; Thu, 1 Oct 2026 12:41:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790858460; cv=none; b=f6MFu+nA6CdQYbijTQUPwMxRoX+1AyLFJZfh30SqDVr+e3IeW60VRCGcT9EBPTlGWY/mIAeQaiA7KPAFDKhPFNYVInd5BTC1gFI8r8dfiTaIvMoPERG5YjAol/2LshqInGjVLydz+NAq+d5NYRHpbJ5OH2FbSKnMF33bde4EKgA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790858460; c=relaxed/simple; bh=/EqyzhFKjVT1Spu2ADyKiMSyXx4yZn96DdPYCnXHJf8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dYp58Kewg3OhjHHfVEj7FHWJ/fwZohn7ciI7Dl0s4GwsyqJkCz4zK7Gag0r5rlnP7ck77qcdG1RIVQSR5YG9bQFUx5NgZzS2ZEeKUOLsHVMsz5kchIG0/OqzkaJFkWWvtjVdaiLhQTEAx0wfU8K5o5UqQPUMgTJNGWHO6FSvgDY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=npJeSmZp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="npJeSmZp" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4BDDCC4AF12; Thu, 1 Oct 2026 12:41:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790858460; bh=/EqyzhFKjVT1Spu2ADyKiMSyXx4yZn96DdPYCnXHJf8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=npJeSmZpn6aCV0AhHp/GazOwmbgnO6xDX/3fSCHleKbQWnOWBl1KJv0CtqffuaDbw o4sp4EnfND/jJNNTz4unClHqlBbzqQl2y+68W9gyA+ujpyjuJDE2rKHLOaplw0UrZD MA92mGEU5JG1cGALrShVBokZKs7tuxke1kMYSujPCVkVK2KF4BjGhq9TRe0jYY5rxW E8XDRoCLZALKeJgz4rLlngYPe9QOFkB+0FPoiP1oA5o7ArsnpkeJ48WKfYnSuRGmEl L7MIs5KWsSL2mFRrU29tunLhazTqp3OzwuQqzst6L9f4yFSJq8NcV3yIKSzcr6QRwB 0uEsqMWDQV8TQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 206A1CA5FCB; Thu, 1 Oct 2026 12:41:00 +0000 (UTC) From: Long Zhao via B4 Relay Date: Thu, 01 Oct 2026 20:40:50 +0800 Subject: [PATCH v9 01/15] dt-bindings: arm: add Ambarella CV75 platforms Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-cv75-v5-v9-1-486cc289a4b8@ambarella.com> References: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> In-Reply-To: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Michael Walle , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790858457; l=1876; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=a3UsADFSuMY/QlkptOgZJzk4a6/aFRhf9dYNkAufvC4=; b=D5JwkD6jH4aBAdqYa1xs//yHF3NPePp0Cr6PH+34Op69RvuPm9lTfx2ghIFWo4tZbFcXCRDgb 3vM0iJiNv5WBUNe6afv+m1VyYB8m7cqkLBVRWU03cp/irWIuscGDJx5 X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Add the Ambarella vendor prefix and CV75 EVK board compatible for the initial SoC bring-up. Reviewed-by: Linus Walleij Reviewed-by: Krzysztof Kozlowski Signed-off-by: Long Zhao --- .../devicetree/bindings/arm/ambarella.yaml | 24 ++++++++++++++++++= ++++ .../devicetree/bindings/vendor-prefixes.yaml | 2 ++ 2 files changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ambarella.yaml b/Documen= tation/devicetree/bindings/arm/ambarella.yaml new file mode 100644 index 000000000000..72946e94fa76 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ambarella.yaml @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/ambarella.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ambarella SoC platforms + +maintainers: + - Long Zhao + +properties: + $nodename: + const: "/" + + compatible: + oneOf: + - description: Ambarella CV75 boards + items: + - enum: + - ambarella,cv75-evk + - const: ambarella,cv75 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 85a27937832e..f48aa6dabbe9 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -112,6 +112,8 @@ patternProperties: description: Amarula Solutions "^amazon,.*": description: Amazon.com, Inc. + "^ambarella,.*": + description: Ambarella, Inc. "^amcc,.*": description: Applied Micro Circuits Corporation (APM, formally AMCC) "^amd,.*": --=20 2.34.1 From nobody Fri Oct 2 01:56:21 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFD6C48F03F; Thu, 1 Oct 2026 12:41:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790858460; cv=none; b=uYekDc0HkyuR0Hxt2HySqXDe7sulzRF80VSuLpo5k5LLMZrVG/6yN0QZv1AfN8FW7TbD4cATY2CdHofNAa7HCmXyDfI2yOohJLm8MFIGn6PIYOfUQ6NwODTPiyXu7Lq9glon5tFRQUnZbuiV91vGgGjhsPqw4fJMvdJzNMc0Q/k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790858460; c=relaxed/simple; bh=n2PC5Ygmm3kKQRsnARaZvzzaiZN9N9d+mwOfSpacRzw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dDer88XPWAJ9YItu+RyGnYk5radMeqU0rtxDcK0w8VUM68J3XQdb3/uORtMsgmMfAW1i4v3Qav+CN7mkUnxkd86HGKO9pkReQmT90PUDlsWZt4DRtKiFiXq70fAWHET3eGFNsNG5J/qrULhoxTeMM+pxqHLt0bjkbJJgKwHF22I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=axY04V11; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="axY04V11" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5BD0BC4AF0B; Thu, 1 Oct 2026 12:41:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790858460; bh=n2PC5Ygmm3kKQRsnARaZvzzaiZN9N9d+mwOfSpacRzw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=axY04V11caQs/FYp1d84t6qg1LHcYssPcunhfV9pReaT2QaxnrMtZlSneObNRLWrU Ww3xnhphs5gaskfmqSLgttlpYmjtJIIi0XQj4fYkNvJKad4DQH86ZKq0ZjXusI2yUu QmuemBWEqEtNZtyCLDCx6gE0sqFfPYekpb9PI8tEXpZovQ46nyM4C1X6ovoTkxhvLs KOzuFTmI9G1L1p/P1B7Godbdp6tPwdQ0lhA+9TB3ku7wUVk8TyqNIle/tnjZ22KKtG jyayhQI8f6MBR7i+wXzZCFSt+aPOIRdg3MOjo/Dx88djWSsTklDvMJAcZVCJeFTs7N 5cDE2KP9ejifA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36595CA5FD2; Thu, 1 Oct 2026 12:41:00 +0000 (UTC) From: Long Zhao via B4 Relay Date: Thu, 01 Oct 2026 20:40:51 +0800 Subject: [PATCH v9 02/15] dt-bindings: mfd: syscon: add Ambarella CV75 secure scratchpad Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-cv75-v5-v9-2-486cc289a4b8@ambarella.com> References: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> In-Reply-To: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Michael Walle , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790858457; l=934; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=sWEDtsH7Lmq1R/x+RLJKvlPiYjtNzkc/ykiOxa9OBkU=; b=Ur7au6+duy42kHSViIdX8c/1puUmSrN25+m7krt+Is2WpDy85zhJCbuesB+VUyB23ny0NBpmF ACpeHUNY0jkAIMSwtxcqEphsZd4KJRYy/tDOgpIdZflOFXsRPKy2F9T X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Allow ambarella,cv75-sec-scratchpad as a syscon for the shared secure scratchpad registers on CV75. Acked-by: Krzysztof Kozlowski Signed-off-by: Long Zhao --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index fe882d3f828b..9ebf702c06f1 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -32,6 +32,7 @@ properties: - allwinner,sun50i-a64-system-controller - altr,l3regs - altr,sdr-ctl + - ambarella,cv75-sec-scratchpad - amd,pensando-elba-syscon - amlogic,meson-mx-assist - amlogic,meson-mx-bootrom --=20 2.34.1 From nobody Fri Oct 2 01:56:21 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFE1148F827; Thu, 1 Oct 2026 12:41:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790858460; cv=none; b=XySM5GJ1LvT1EzGzgnoDzfW+NKptNIF5XAZH2hi+KZPDwYSgKLi9JdDsfECr5+Lfyt6GOymV+m3an2BypVi35+NOCnsSE8ZXi0L1lKGno3a9UqU5F6Nipl/Dk4pctfaDh0Iaw3alyBwXeRyfuoeJgKoM8NCBtiRqmDmUrBkxBF4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790858460; c=relaxed/simple; bh=TA4UvtPaI6N/mD+iZIrCt55LdDwZ1OZdGI9FuRlVZFs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ShRDg6Nu8BxeunwK8NTImsVbpZzRPLwOg2dO9gFOCN80DVbpGrqPGFNmVdh6mEZmOBu6nYaDUgrd4ooZ1vpnbN4+3TcyqyHTI0xKqO7mikJIFlYshZPwcJAm4f/PRPw0P84MC4CWB15RC26irHwbMrgLf3f3w4gBtzwqGftFlr0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NAY5v30S; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NAY5v30S" Received: by smtp.kernel.org (Postfix) with ESMTPS id 68761C4AF1C; Thu, 1 Oct 2026 12:41:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790858460; bh=TA4UvtPaI6N/mD+iZIrCt55LdDwZ1OZdGI9FuRlVZFs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=NAY5v30SwqDl2eaxP6g0qGMcRQvQTwEFtxTF3loIjcOEMkfPPTxH1ZqKpj5Bd2vO+ 2CohcSEy4dwkTBXgSnrKEEJzIvGXRMoeCJJoxvkRpK1QCS74WFlvFEEzQVa7133H5t fXrHoI239EgtqNNm61+GOM5mz3WK5eqieahoCmwrR1GrwkSf+riJGFQfsIj/vIftW5 v2wG+vcqcmP6Z6/M5J0CeEOKbwkEUHNDwhx5Q2fxZl065guOR0cN37SfOoZSxkde1h l2erXJsQT7EEWysDAQXRyKlXbu93iRcphss6SU7xRaPNyTRmk6PIJ4sWGSwJefHlJ2 8Hy6SZiC1/q9Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BA71CA5FD4; Thu, 1 Oct 2026 12:41:00 +0000 (UTC) From: Long Zhao via B4 Relay Date: Thu, 01 Oct 2026 20:40:52 +0800 Subject: [PATCH v9 03/15] dt-bindings: clock: add Ambarella CV75 RCT Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-cv75-v5-v9-3-486cc289a4b8@ambarella.com> References: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> In-Reply-To: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Michael Walle , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790858457; l=2969; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=gEKr05f9YAOrNVHJfKB47io9QNiMkJyDyO/ZJBUGYg0=; b=u7dATT7wovn/IzB7hOxdMtQfu2TUxzRgNkKQ39Z1EcHYb35bAClImZoJ8ho3BL/DMU+yHDbEA CPIgGMCt6wNBF6lEORnSXvvSdijqmTcbHfSanh6jfTOQUvRI8WcsCxC X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Document the CV75 RCT clock controller and the clock ID header used by DT consumers. Document #reset-cells for the RCT reset-provider role. Soft-reset line IDs and the reset provider driver are deferred; this series has no resets=3D consumers. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Long Zhao --- .../bindings/clock/ambarella,cv75-rct.yaml | 64 ++++++++++++++++++= ++++ include/dt-bindings/clock/ambarella,cv75-rct.h | 14 +++++ 2 files changed, 78 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yam= l b/Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yaml new file mode 100644 index 000000000000..be89bd75f9e2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ambarella,cv75-rct.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ambarella CV75 RCT Clock Controller + +maintainers: + - Long Zhao + +description: | + The RCT (Reset and Clock Tree) block on the Ambarella CV75 SoC provides + PLLs, clock muxes, dividers and soft-reset controls for on-chip + peripherals. + + The same register region is also exposed as a syscon for other SoC + blocks (e.g. pin drive-strength), hence the "syscon" compatible. + + Clock indices are defined in include/dt-bindings/clock/ambarella,cv75-rc= t.h. + +properties: + + compatible: + items: + - const: ambarella,cv75-rct + - const: syscon + + reg: + maxItems: 1 + + clocks: + description: Reference crystal oscillator (typically 24 MHz) + maxItems: 1 + + clock-names: + const: osc + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@ed080000 { + compatible =3D "ambarella,cv75-rct", "syscon"; + reg =3D <0xed080000 0x1000>; + clocks =3D <&osc>; + clock-names =3D "osc"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; diff --git a/include/dt-bindings/clock/ambarella,cv75-rct.h b/include/dt-bi= ndings/clock/ambarella,cv75-rct.h new file mode 100644 index 000000000000..b3e965b4ff2e --- /dev/null +++ b/include/dt-bindings/clock/ambarella,cv75-rct.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2026 Ambarella, Inc. + */ + +#ifndef _DT_BINDINGS_CLOCK_AMBARELLA_CV75_RCT_H +#define _DT_BINDINGS_CLOCK_AMBARELLA_CV75_RCT_H + +#define CV75_GCLK_UART0 0 +#define CV75_GCLK_CORE 1 +#define CV75_GCLK_AHB 2 +#define CV75_GCLK_APB 3 + +#endif --=20 2.34.1 From nobody Fri Oct 2 01:56:21 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDE2E495AC2; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-cv75-v5-v9-4-486cc289a4b8@ambarella.com> References: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> In-Reply-To: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Michael Walle , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790858457; l=2025; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=GVEIXtfx8rpLQa9TzFd09VjRop28rVpySsmXjUcyqZs=; b=Y8pd3ddXl8IoS7dP8eJy1gqZI5BES85+71MExgOd+u1qD/1c0VXaLRMz8aW0dqWVexEzuiblT +wWPeAhuRbtBRapWsXfa0VADQa2yri6b17o/4w5jcXuoxYe3FLk7NFG X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao The CV75 GPIO banks sit on the AMBA PrimeCell bus but are not register-compatible with the ARM PL061. Each bank is 32-bit and 32 lines, with extra mask/enable registers, so arm,pl061 must not be used as a fallback compatible. The AMBA core matches the PL061 driver by PrimeCell ID, not by the DT compatible string. These blocks do not implement the standard PL061 ID (0x00041061) in the ID registers, so arm,primecell-periphid is required and is fixed to 0x000e8061; the driver uses that ID to select the Ambarella layout. gpio-ranges is required because each bank is a slice of the SoC pinctrl pin space. Signed-off-by: Long Zhao Acked-by: Conor Dooley --- .../devicetree/bindings/gpio/pl061-gpio.yaml | 25 ++++++++++++++++++= +--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml b/Docum= entation/devicetree/bindings/gpio/pl061-gpio.yaml index 4d970e55104b..c22dd8a1d2c1 100644 --- a/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml @@ -15,7 +15,9 @@ select: properties: compatible: contains: - const: arm,pl061 + enum: + - arm,pl061 + - ambarella,cv75-gpio required: - compatible =20 @@ -25,7 +27,9 @@ properties: =20 compatible: items: - - const: arm,pl061 + - enum: + - ambarella,cv75-gpio + - arm,pl061 - const: arm,primecell =20 reg: @@ -64,6 +68,21 @@ required: - "#gpio-cells" - gpio-controller =20 -additionalProperties: false +allOf: + - $ref: /schemas/arm/primecell.yaml# + - if: + properties: + compatible: + contains: + const: ambarella,cv75-gpio + then: + properties: + arm,primecell-periphid: + const: 0x000e8061 + required: + - arm,primecell-periphid + - gpio-ranges + +unevaluatedProperties: false =20 ... --=20 2.34.1 From nobody Fri Oct 2 01:56:21 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C20549D5B2; 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bh=aI42/QWFrT0q/wEmjSA5wdZvhIPXU9faQz3G+ySJ344=; b=GJyR08f2m1KBM40itHZIVPxg3lvd9r9y6CUpV2Ai8ClGQ/FUWgpQIFuuO90FvVU3YnUMMEkj6 4oYVmJRfounAKLKknYAZ1rifH3WZ48+AGulMe0TOCQR3pIqHkUpwlPD X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Add the Ambarella CV75 compatible string to the Synopsys DW APB UART binding. The block is Ambarella IP with a DW-like register map, so it is described as a DW APB UART variant. Acked-by: Krzysztof Kozlowski Reviewed-by: Linus Walleij Signed-off-by: Long Zhao --- Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml= b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index 49f51b002879..cec5c679f1a9 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -51,6 +51,7 @@ properties: - const: renesas,rzn1-uart - items: - enum: + - ambarella,cv75-uart - anlogic,dr1v90-uart - brcm,bcm11351-dw-apb-uart - brcm,bcm21664-dw-apb-uart --=20 2.34.1 From nobody Fri Oct 2 01:56:21 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01C46499F28; Thu, 1 Oct 2026 12:41:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790858461; cv=none; b=PBSTZn1Y29hfHV3ji7Yw07tLvSeFLvnkzDSOo5MX4gMNy4ejzHKc/jSBKyvefhXcePkioR3xCZ+eC/QWbNu8uCbjK0t+/BDUhYIbvQg24CrzmXccrvqyw0O3akykEhrQwDhKaKlncF2dpAjP2/SV+5uGZSpHm/8bMQa9Iv3XONo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790858461; c=relaxed/simple; bh=bqgS5XpvrstWVWKP9LuvnDwflt0rXBSfiLBunIlP0Gs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NGWXjotAqLJ30YmQOKjmzrlIlWu3g1a3FuFYGvH78LCdKGgz/zG9aynQrw2lvmkAV0pk6R232jREkm9kF7dX+zyPLz7nZ+UBfow09z0LH1YwZJaz9LlmryGlYpuo1tH7o627VdsXcKEyr31vtl7lFgPr9jqa5knkeIZVXOg5fhE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=h4HWw9pu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="h4HWw9pu" Received: by smtp.kernel.org (Postfix) with ESMTPS id A85DFC4DDF1; Thu, 1 Oct 2026 12:41:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790858460; bh=bqgS5XpvrstWVWKP9LuvnDwflt0rXBSfiLBunIlP0Gs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=h4HWw9puFIZ/vU7BzvNAQalkwNEfgQWkhZUH+VfAHy8VxowGTBzeCmSBbggKPr8Rx ir+irtTYj95m90U7qNJQZsjViFhIfVyZUD1OB1tZRGMmELJGY4yLXPRV98LmkCIR7I r58z6lR0TKGbOev3SkGrZmnFg5UMDcEy8ayA6dIgvmroU5y+4Xlqaz8ftmknjZ4B2W 9d2RL/x5+E0oeYuLvP5MoWC5nYLtrNZcnFSFx9xZeYmSKcDdEwWbI0WQzvgQA9LNJq nEeAf0OO9EJ3NViDRcA8EpBCju7lPMiyfEDIDmhldl7Qgr9YPLdCZT6j45kSc+Jwpq p2NuVzVwOGLjQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91E38CA5FA5; Thu, 1 Oct 2026 12:41:00 +0000 (UTC) From: Long Zhao via B4 Relay Date: Thu, 01 Oct 2026 20:40:55 +0800 Subject: [PATCH v9 06/15] clk: ambarella: add CV75 RCT clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-cv75-v5-v9-6-486cc289a4b8@ambarella.com> References: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> In-Reply-To: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Michael Walle , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790858457; l=12327; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=QChNsrVZVY8Pzfog5BXibva/KN+iXooU+fbG0vVELS4=; b=iaW9N26cQh9EZLY3CVgDJlyDcsaHV+pC3kUodWmLp/c9JfaEOe2gEm96R33rAPger8nmlggMB pXaRXlZdBw7DKve6AQ5hjLTdVgoU5AlN8qRzp7iYTsoAO4y7Vt5T2J2 X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Add a table-driven CCF driver for the CV75 root clock tree. Register the core PLL, AHB/APB fixed factors and UART0 composite clock, with osc supplied via clk_parent_data. Signed-off-by: Long Zhao --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/ambarella/Kconfig | 9 + drivers/clk/ambarella/Makefile | 3 + drivers/clk/ambarella/clk-cv75.c | 365 +++++++++++++++++++++++++++++++++++= ++++ 5 files changed, 379 insertions(+) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 1717ce75a907..fbbf4963716c 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -506,6 +506,7 @@ config COMMON_CLK_RPMI the RISC-V platform management interface (RPMI) specification. =20 source "drivers/clk/actions/Kconfig" +source "drivers/clk/ambarella/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/aspeed/Kconfig" source "drivers/clk/bcm/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index cc108a75a900..30d823ee606f 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -112,6 +112,7 @@ obj-$(CONFIG_COMMON_CLK_XGENE) +=3D clk-xgene.o =20 # please keep this section sorted lexicographically by directory path name obj-y +=3D actions/ +obj-y +=3D ambarella/ obj-y +=3D analogbits/ obj-y +=3D aspeed/ obj-$(CONFIG_COMMON_CLK_AT91) +=3D at91/ diff --git a/drivers/clk/ambarella/Kconfig b/drivers/clk/ambarella/Kconfig new file mode 100644 index 000000000000..720eebdc5c9c --- /dev/null +++ b/drivers/clk/ambarella/Kconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config CLK_AMBARELLA_CV75 + bool "Ambarella CV75 RCT clock controller" + depends on ARCH_AMBARELLA || COMPILE_TEST + default ARCH_AMBARELLA + help + Say Y to enable the Ambarella CV75 RCT clock controller for + early bring-up clocks (core PLL, AHB, APB, UART0). diff --git a/drivers/clk/ambarella/Makefile b/drivers/clk/ambarella/Makefile new file mode 100644 index 000000000000..29555e452441 --- /dev/null +++ b/drivers/clk/ambarella/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_CLK_AMBARELLA_CV75) +=3D clk-cv75.o diff --git a/drivers/clk/ambarella/clk-cv75.c b/drivers/clk/ambarella/clk-c= v75.c new file mode 100644 index 000000000000..4071dfd75659 --- /dev/null +++ b/drivers/clk/ambarella/clk-cv75.c @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Ambarella CV75 RCT clock controller + * + * Copyright (C) 2026 Ambarella, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define CV75_NUM_CLKS (CV75_GCLK_APB + 1) + +#define PLL_CTRL_BYPASS BIT(2) +#define PLL_CTRL_FRAC_MODE BIT(3) +#define PLL_CTRL_FORCE_RESET BIT(4) +#define PLL_CTRL_POWER_DOWN BIT(5) +#define PLL_CTRL_HALT_VCO BIT(6) +#define PLL_CTRL_SDIV GENMASK(15, 12) +#define PLL_CTRL_SOUT GENMASK(19, 16) +#define PLL_CTRL_INTP GENMASK(30, 24) + +#define PLL_CTRL2_VCODIV_DIV2 BIT(8) +#define PLL_CTRL2_FSDIV_DIV2 BIT(9) +#define PLL_CTRL2_FSOUT_DIV2 BIT(11) +#define PLL_CTRL2_BYPASS_HSDIV BIT(12) + +struct cv75_pll_hw { + struct clk_hw hw; + u32 ctrl; + u32 frac; + u32 ctrl2; +}; + +struct cv75_clk { + void __iomem *base; + spinlock_t lock; + struct cv75_pll_hw core; + struct cv75_pll_hw enet; + struct cv75_pll_hw sd; +}; + +struct cv75_pll { + const char *name; + struct cv75_pll_hw *hw; + unsigned long flags; + u32 ctrl; + u32 frac; + u32 ctrl2; + int id; +}; + +struct cv75_fixed_factor { + const char *name; + u32 id; + struct u16_fract ratio; +}; + +struct cv75_composite { + const char *name; + const struct clk_parent_data *parents; + unsigned long flags; + u32 id; + u16 mux_reg; + u16 div_reg; + u8 num_parents; + u8 mux_shift; + u8 mux_width; + u8 div_shift; + u8 div_width; +}; + +struct cv75_composite_hw { + struct clk_mux mux; + struct clk_divider div; + struct clk_gate gate; +}; + +static struct cv75_clk cv75_ccu; + +#define CV75_PLL(_id, _name, _ctrl, _frac, _ctrl2, _flags, _hw) { \ + .name =3D _name, \ + .hw =3D _hw, \ + .flags =3D _flags, \ + .ctrl =3D _ctrl, \ + .frac =3D _frac, \ + .ctrl2 =3D _ctrl2, \ + .id =3D _id, \ +} + +static const struct cv75_pll cv75_plls[] =3D { + CV75_PLL(CV75_GCLK_CORE, "core", 0x000, 0x004, 0x100, + CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL, &cv75_ccu.core), + CV75_PLL(-1, "pll_enet", 0x520, 0x524, 0x528, + CLK_GET_RATE_NOCACHE, &cv75_ccu.enet), + CV75_PLL(-1, "pll_sd", 0x4ac, 0x4b0, 0x4b4, + CLK_GET_RATE_NOCACHE, &cv75_ccu.sd), +}; + +static const struct cv75_fixed_factor cv75_fixed_factors[] =3D { + { .id =3D CV75_GCLK_AHB, .name =3D "ahb", .ratio =3D { 1, 2 } }, + { .id =3D CV75_GCLK_APB, .name =3D "apb", .ratio =3D { 1, 4 } }, +}; + +static const struct clk_parent_data cv75_uart_parents[] =3D { + { .fw_name =3D "osc" }, + { .hw =3D &cv75_ccu.core.hw }, + { .hw =3D &cv75_ccu.enet.hw }, + { .hw =3D &cv75_ccu.sd.hw }, +}; + +#define CV75_COMPOSITE(_id, _name, _parents, _mreg, _mshift, _mwidth, \ + _dreg, _dshift, _dwidth, _flags) \ +{ \ + .id =3D _id, \ + .name =3D _name, \ + .parents =3D _parents, \ + .num_parents =3D ARRAY_SIZE(_parents), \ + .mux_reg =3D _mreg, \ + .mux_shift =3D _mshift, \ + .mux_width =3D _mwidth, \ + .div_reg =3D _dreg, \ + .div_shift =3D _dshift, \ + .div_width =3D _dwidth, \ + .flags =3D _flags, \ +} + +static const struct cv75_composite cv75_composites[] =3D { + CV75_COMPOSITE(CV75_GCLK_UART0, "uart0", cv75_uart_parents, + 0x1c8, 0, 2, 0x038, 0, 24, + CLK_SET_RATE_NO_REPARENT), +}; + +#define to_cv75_pll(_hw) container_of(_hw, struct cv75_pll_hw, hw) + +static unsigned long cv75_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct cv75_pll_hw *pll =3D to_cv75_pll(hw); + u32 ctrl, ctrl2, frac_val; + u32 intp, sdiv, sout; + u32 vcodiv, fsdiv, fsout; + u64 vco, frac =3D 0; + + ctrl =3D readl_relaxed(cv75_ccu.base + pll->ctrl); + if (ctrl & (PLL_CTRL_POWER_DOWN | PLL_CTRL_HALT_VCO | PLL_CTRL_FORCE_RESE= T)) + return 0; + + if (ctrl & PLL_CTRL_BYPASS) + return parent_rate; + + ctrl2 =3D readl_relaxed(cv75_ccu.base + pll->ctrl2); + intp =3D FIELD_GET(PLL_CTRL_INTP, ctrl) + 1; + sdiv =3D FIELD_GET(PLL_CTRL_SDIV, ctrl) + 1; + sout =3D FIELD_GET(PLL_CTRL_SOUT, ctrl) + 1; + vcodiv =3D (ctrl2 & PLL_CTRL2_VCODIV_DIV2) ? 2 : 1; + fsdiv =3D (ctrl2 & PLL_CTRL2_FSDIV_DIV2) ? 2 : 1; + fsout =3D (ctrl2 & PLL_CTRL2_FSOUT_DIV2) ? 2 : 1; + + vco =3D (u64)parent_rate * vcodiv * fsdiv * intp * sdiv; + if (ctrl & PLL_CTRL_FRAC_MODE) { + frac_val =3D readl_relaxed(cv75_ccu.base + pll->frac); + frac =3D mul_u64_u32_shr((u64)parent_rate * vcodiv * fsdiv * sdiv, + frac_val, 32); + vco +=3D frac; + } + + if (!(ctrl2 & PLL_CTRL2_BYPASS_HSDIV)) + vco =3D div_u64(vco, (u64)vcodiv * fsout * sout); + + return vco; +} + +static const struct clk_ops cv75_pll_ops =3D { + .recalc_rate =3D cv75_pll_recalc_rate, +}; + +static int cv75_register_plls(struct device *dev, + struct clk_hw_onecell_data *data) +{ + struct clk_parent_data parent_data =3D { .fw_name =3D "osc" }; + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(cv75_plls); i++) { + const struct cv75_pll *desc =3D &cv75_plls[i]; + struct cv75_pll_hw *pll =3D desc->hw; + struct clk_init_data init =3D {}; + int ret; + + pll->ctrl =3D desc->ctrl; + pll->frac =3D desc->frac; + pll->ctrl2 =3D desc->ctrl2; + + init.name =3D desc->name; + init.ops =3D &cv75_pll_ops; + init.parent_data =3D &parent_data; + init.num_parents =3D 1; + init.flags =3D desc->flags; + pll->hw.init =3D &init; + + ret =3D devm_clk_hw_register(dev, &pll->hw); + if (ret) + return ret; + + if (desc->id >=3D 0) + data->hws[desc->id] =3D &pll->hw; + } + + return 0; +} + +static int cv75_register_fixed_factors(struct device *dev, + struct clk_hw_onecell_data *data) +{ + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(cv75_fixed_factors); i++) { + const struct cv75_fixed_factor *f =3D &cv75_fixed_factors[i]; + struct clk_hw *hw; + + hw =3D devm_clk_hw_register_fixed_factor_parent_hw(dev, f->name, + &cv75_ccu.core.hw, 0, + f->ratio.numerator, + f->ratio.denominator); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + data->hws[f->id] =3D hw; + } + + return 0; +} + +static struct clk_hw *cv75_register_composite(struct device *dev, + const struct cv75_composite *c) +{ + const struct clk_ops *mux_ops =3D NULL, *div_ops =3D NULL, *gate_ops =3D = NULL; + struct clk_hw *mux_hw =3D NULL, *div_hw =3D NULL, *gate_hw =3D NULL; + struct cv75_composite_hw *comp; + + comp =3D devm_kzalloc(dev, sizeof(*comp), GFP_KERNEL); + if (!comp) + return ERR_PTR(-ENOMEM); + + if (c->mux_width) { + comp->mux.reg =3D cv75_ccu.base + c->mux_reg; + comp->mux.shift =3D c->mux_shift; + comp->mux.mask =3D GENMASK(c->mux_width - 1, 0); + comp->mux.lock =3D &cv75_ccu.lock; + mux_hw =3D &comp->mux.hw; + mux_ops =3D &clk_mux_ops; + } + + if (c->div_width) { + comp->div.reg =3D cv75_ccu.base + c->div_reg; + comp->div.shift =3D c->div_shift; + comp->div.width =3D c->div_width; + comp->div.flags =3D CLK_DIVIDER_ONE_BASED; + comp->div.lock =3D &cv75_ccu.lock; + div_hw =3D &comp->div.hw; + div_ops =3D &clk_divider_ops; + + comp->gate.reg =3D cv75_ccu.base + c->div_reg; + comp->gate.bit_idx =3D c->div_shift + c->div_width; + comp->gate.flags =3D CLK_GATE_SET_TO_DISABLE; + comp->gate.lock =3D &cv75_ccu.lock; + gate_hw =3D &comp->gate.hw; + gate_ops =3D &clk_gate_ops; + } + + return devm_clk_hw_register_composite_pdata(dev, c->name, c->parents, + c->num_parents, + mux_hw, mux_ops, + div_hw, div_ops, + gate_hw, gate_ops, c->flags); +} + +static int cv75_register_composites(struct device *dev, + struct clk_hw_onecell_data *data) +{ + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(cv75_composites); i++) { + const struct cv75_composite *c =3D &cv75_composites[i]; + struct clk_hw *hw; + + hw =3D cv75_register_composite(dev, c); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + data->hws[c->id] =3D hw; + } + + return 0; +} + +static int cv75_rct_probe(struct platform_device *pdev) +{ + struct clk_hw_onecell_data *data; + struct device *dev =3D &pdev->dev; + int ret; + + spin_lock_init(&cv75_ccu.lock); + + cv75_ccu.base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(cv75_ccu.base)) + return PTR_ERR(cv75_ccu.base); + + data =3D devm_kzalloc(dev, struct_size(data, hws, CV75_NUM_CLKS), GFP_KER= NEL); + if (!data) + return -ENOMEM; + data->num =3D CV75_NUM_CLKS; + + ret =3D cv75_register_plls(dev, data); + if (ret) + return dev_err_probe(dev, ret, "failed to register plls\n"); + + ret =3D cv75_register_fixed_factors(dev, data); + if (ret) + return dev_err_probe(dev, ret, "failed to register fixed factors\n"); + + ret =3D cv75_register_composites(dev, data); + if (ret) + return dev_err_probe(dev, ret, "failed to register composites\n"); + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data); + if (ret) + return dev_err_probe(dev, ret, "failed to add clock provider\n"); + + return 0; +} + +static const struct of_device_id cv75_rct_match[] =3D { + { .compatible =3D "ambarella,cv75-rct" }, + { } +}; +MODULE_DEVICE_TABLE(of, cv75_rct_match); + +static struct platform_driver cv75_rct_driver =3D { + .probe =3D cv75_rct_probe, + .driver =3D { + .name =3D "ambarella-cv75-rct", + .of_match_table =3D cv75_rct_match, + }, +}; +module_platform_driver(cv75_rct_driver); + +MODULE_AUTHOR("Cao Rongrong "); +MODULE_DESCRIPTION("Ambarella CV75 RCT clock controller"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Fri Oct 2 01:56:21 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C0ED49D5A6; Thu, 1 Oct 2026 12:41:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-cv75-v5-v9-7-486cc289a4b8@ambarella.com> References: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> In-Reply-To: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Michael Walle , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790858457; l=3373; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=IBa8epd2/4YpoCQ3nIa3WOdoI+AIcLQgC3bWWH4FGyQ=; b=PZWnOerKLdbdqt73Nvu/XDtzQRIy2lsM4PdHcH8CH5y17x+sAN9UWgrUMW9kuwNW4ypkuU9KS BEbgND5KgcxA55t3qvSMiTmFLGcNrwKlfOKDK0dmsavbSpK2QeFgd1b X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Some controllers ignore output writes while a line is still an input. Add a behaviour flag so the output value is written after the direction change. This is a legacy quirk. New hardware must not use it. Signed-off-by: Long Zhao --- drivers/gpio/gpio-regmap.c | 15 +++++++++++++-- include/linux/gpio/regmap.h | 14 ++++++++++++++ 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c index 51b4d69b8740..728bf3d90c48 100644 --- a/drivers/gpio/gpio-regmap.c +++ b/drivers/gpio/gpio-regmap.c @@ -31,6 +31,7 @@ struct gpio_regmap { unsigned int reg_clr_base; unsigned int reg_dir_in_base; unsigned int reg_dir_out_base; + unsigned long quirks; unsigned long *fixed_direction_mask; unsigned long *fixed_direction_output; =20 @@ -271,9 +272,17 @@ static int gpio_regmap_direction_output(struct gpio_ch= ip *chip, return ret; } =20 - gpio_regmap_set(chip, offset, value); + if (!(gpio->quirks & GPIO_REGMAP_QUIRK_SET_AFTER_DIR)) + gpio_regmap_set(chip, offset, value); =20 - return gpio_regmap_set_direction(chip, offset, true); + ret =3D gpio_regmap_set_direction(chip, offset, true); + if (ret) + return ret; + + if (gpio->quirks & GPIO_REGMAP_QUIRK_SET_AFTER_DIR) + gpio_regmap_set(chip, offset, value); + + return 0; } =20 void *gpio_regmap_get_drvdata(struct gpio_regmap *gpio) @@ -376,6 +385,8 @@ struct gpio_regmap *gpio_regmap_register(const struct g= pio_regmap_config *config config->fixed_direction_output, chip->ngpio); } =20 + gpio->quirks =3D config->quirks; + /* if not set, assume there is only one register */ gpio->ngpio_per_reg =3D config->ngpio_per_reg; if (!gpio->ngpio_per_reg) diff --git a/include/linux/gpio/regmap.h b/include/linux/gpio/regmap.h index 06255756710d..e5a343512efb 100644 --- a/include/linux/gpio/regmap.h +++ b/include/linux/gpio/regmap.h @@ -3,6 +3,8 @@ #ifndef _LINUX_GPIO_REGMAP_H #define _LINUX_GPIO_REGMAP_H =20 +#include + struct device; struct fwnode_handle; struct gpio_regmap; @@ -13,6 +15,14 @@ struct regmap; #define GPIO_REGMAP_ADDR_ZERO ((unsigned int)(-1)) #define GPIO_REGMAP_ADDR(addr) ((addr) ? : GPIO_REGMAP_ADDR_ZERO) =20 +/* + * Write the output value after the line is switched to output. + * Needed when hardware ignores output writes while the line is an input. + * This is a legacy quirk; new hardware must not use it. Direction changes + * will glitch. + */ +#define GPIO_REGMAP_QUIRK_SET_AFTER_DIR BIT(0) + /** * struct gpio_regmap_config - Description of a generic regmap gpio_chip. * @parent: The parent device @@ -24,6 +34,7 @@ struct regmap; * If not given, the name of the device is used. * @ngpio: (Optional) Number of GPIOs * @names: (Optional) Array of names for gpios + * @quirks: (Optional) Behaviour flags, OR of GPIO_REGMAP_QUIRK_*. * @reg_dat_base: (Optional) (in) register base address * @reg_set_base: (Optional) set register base address * @reg_clr_base: (Optional) clear register base address @@ -87,6 +98,9 @@ struct gpio_regmap_config { int ngpio; const char *const *names; =20 + /* Regmap GPIO behaviour flags */ + unsigned long quirks; + unsigned int reg_dat_base; unsigned int reg_set_base; unsigned int reg_clr_base; --=20 2.34.1 From nobody Fri Oct 2 01:56:21 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3723749E5D9; Thu, 1 Oct 2026 12:41:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790858461; cv=none; b=Y0QvG9LuimCY3dEwYmOAl9jHimsbE3p4s4U2M6cZBaj08FJClJN/kXmanBkAT+X73xtPlD04OX0bJO0ElG8ao8pI10JVPVlxlYcZU4Mn9n/53NBXEMoStH3WKeKCMYspVusB4N00JW3tUiSbMo8xExgHReofs34BUdSVg/SyWQc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790858461; c=relaxed/simple; bh=A6TKI0IEGVMFdx8CFDfSgaU1YD5Nt5zfxVsEGII7wcY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=E93FuiSc3RY7nyPFXkjl8d+JmvBUDhVO2eyI7K00bu4bXKckUVsKaRuY5YG2SNsoZPmRPcf77T1/NSSkmd1GdSj7wjqeTDAZxT9lGglCueorVjBghOd0o4gUgw4Hta6Gn3UsCMVUMm1XAblgljJad2c0DFY2EIlcjg5TAmY191g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=B0FhEXet; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="B0FhEXet" Received: by smtp.kernel.org (Postfix) with ESMTPS id CF7F2C4AF63; Thu, 1 Oct 2026 12:41:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790858460; bh=A6TKI0IEGVMFdx8CFDfSgaU1YD5Nt5zfxVsEGII7wcY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=B0FhEXetmubFk5A0uAW8VT7IuslY1koHHJFebMms3DZ1wdwpMEAQb6ztcVaGGNV3/ FGTZI+bsb1TAL719VKn59RvRb+ktU77ubFd/WAgOZ59HwA5W/aRAcYLJPQS4BVfZYY 7LXkuI6XKUogQ+t0DY63kK69PlOAmsD1qDMld0T+2ongPDy6/ji5AROhO2BJttQX8H g5GCG+0G1URetpCzyNUYGDPrM33x99S0AmCc2xI3goUnrtNUo3u0JLrRPq2r1cq3wk vkbCEr20xoz+EqpKwcUGiriVGnzoky0k/iHptaqo/gLks87qY9UzBXdZvQ3vuN5K9N oCc4+fSupmG9w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8E48CA5FD4; Thu, 1 Oct 2026 12:41:00 +0000 (UTC) From: Long Zhao via B4 Relay Date: Thu, 01 Oct 2026 20:40:57 +0800 Subject: [PATCH v9 08/15] gpio: pl061: convert register access to regmap Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-cv75-v5-v9-8-486cc289a4b8@ambarella.com> References: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> In-Reply-To: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Michael Walle , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790858457; l=11303; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=uA7OlKuOGQYG2GvBwBpLkW2V50ylczQZjnla8/gJ09Q=; b=UVxJ8/cur2KGMQAJzKg6fp3KkLU3VEVcTrEHp5lxCvYPWKyyHxBi6wCPMHIq0w2xRFaq7Xb0m kzZzzTajgOrDM9exQ19sNHcXbtJdWRpDrzqiPsWUiQNzeUjSeJvWqVc X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Replace readb()/writeb() with a MMIO regmap while keeping the existing gpio_chip and girq irqchip. Use a raw spinlock so irq_ack() can run under the irq descriptor lock. Reviewed-by: Linus Walleij Signed-off-by: Long Zhao --- drivers/gpio/Kconfig | 1 + drivers/gpio/gpio-pl061.c | 134 ++++++++++++++++++++++++++++++------------= ---- 2 files changed, 89 insertions(+), 46 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index f03c05288376..2a1487bd1a94 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -583,6 +583,7 @@ config GPIO_PL061 depends on ARM_AMBA || COMPILE_TEST select IRQ_DOMAIN select GPIOLIB_IRQCHIP + select REGMAP_MMIO help Say yes here to support the PrimeCell PL061 GPIO device. =20 diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index 919cf86fd590..66aea0856bc4 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -19,9 +19,11 @@ #include #include #include +#include #include #include #include +#include #include #include #include @@ -36,6 +38,7 @@ #define GPIOIC 0x41C =20 #define PL061_GPIO_NR 8 +#define PL061_DATA_OFFSET 2 =20 struct pl061_context_save_regs { u8 gpio_data; @@ -49,18 +52,49 @@ struct pl061_context_save_regs { struct pl061 { raw_spinlock_t lock; =20 - void __iomem *base; + struct regmap *regmap; struct gpio_chip gc; int parent_irq; =20 struct pl061_context_save_regs csave_regs; }; =20 +static bool pl061_is_data_reg(unsigned int reg) +{ + return is_power_of_2(reg) && + reg >=3D BIT(PL061_DATA_OFFSET) && + reg <=3D BIT(PL061_DATA_OFFSET + PL061_GPIO_NR - 1); +} + +static bool pl061_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case GPIOMIS: + case GPIOIC: + return true; + default: + return pl061_is_data_reg(reg); + } +} + +static const struct regmap_config pl061_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .reg_stride =3D 4, + .max_register =3D GPIOIC, + .volatile_reg =3D pl061_volatile_reg, + .fast_io =3D true, + .use_raw_spinlock =3D true, +}; + static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) { struct pl061 *pl061 =3D gpiochip_get_data(gc); + unsigned int gpiodir =3D 0; =20 - if (readb(pl061->base + GPIODIR) & BIT(offset)) + regmap_read(pl061->regmap, GPIODIR, &gpiodir); + + if (gpiodir & BIT(offset)) return GPIO_LINE_DIRECTION_OUT; =20 return GPIO_LINE_DIRECTION_IN; @@ -70,12 +104,9 @@ static int pl061_direction_input(struct gpio_chip *gc, = unsigned offset) { struct pl061 *pl061 =3D gpiochip_get_data(gc); unsigned long flags; - unsigned char gpiodir; =20 raw_spin_lock_irqsave(&pl061->lock, flags); - gpiodir =3D readb(pl061->base + GPIODIR); - gpiodir &=3D ~(BIT(offset)); - writeb(gpiodir, pl061->base + GPIODIR); + regmap_update_bits(pl061->regmap, GPIODIR, BIT(offset), 0); raw_spin_unlock_irqrestore(&pl061->lock, flags); =20 return 0; @@ -86,19 +117,19 @@ static int pl061_direction_output(struct gpio_chip *gc= , unsigned offset, { struct pl061 *pl061 =3D gpiochip_get_data(gc); unsigned long flags; - unsigned char gpiodir; + unsigned int mask =3D BIT(offset); =20 raw_spin_lock_irqsave(&pl061->lock, flags); - writeb(!!value << offset, pl061->base + (BIT(offset + 2))); - gpiodir =3D readb(pl061->base + GPIODIR); - gpiodir |=3D BIT(offset); - writeb(gpiodir, pl061->base + GPIODIR); + regmap_write(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), + !!value << offset); + regmap_update_bits(pl061->regmap, GPIODIR, mask, mask); =20 /* * gpio value is set again, because pl061 doesn't allow to set value of * a gpio pin before configuring it in OUT mode. */ - writeb(!!value << offset, pl061->base + (BIT(offset + 2))); + regmap_write(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), + !!value << offset); raw_spin_unlock_irqrestore(&pl061->lock, flags); =20 return 0; @@ -107,15 +138,19 @@ static int pl061_direction_output(struct gpio_chip *g= c, unsigned offset, static int pl061_get_value(struct gpio_chip *gc, unsigned offset) { struct pl061 *pl061 =3D gpiochip_get_data(gc); + unsigned int val =3D 0; + + regmap_read(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), &val); =20 - return !!readb(pl061->base + (BIT(offset + 2))); + return !!val; } =20 static int pl061_set_value(struct gpio_chip *gc, unsigned int offset, int = value) { struct pl061 *pl061 =3D gpiochip_get_data(gc); =20 - writeb(!!value << offset, pl061->base + (BIT(offset + 2))); + regmap_write(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), + !!value << offset); =20 return 0; } @@ -126,8 +161,8 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) struct pl061 *pl061 =3D gpiochip_get_data(gc); int offset =3D irqd_to_hwirq(d); unsigned long flags; - u8 gpiois, gpioibe, gpioiev; - u8 bit =3D BIT(offset); + unsigned int gpiois =3D 0, gpioibe =3D 0, gpioiev =3D 0; + unsigned int bit =3D BIT(offset); =20 if (offset < 0 || offset >=3D PL061_GPIO_NR) return -EINVAL; @@ -145,9 +180,9 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) =20 raw_spin_lock_irqsave(&pl061->lock, flags); =20 - gpioiev =3D readb(pl061->base + GPIOIEV); - gpiois =3D readb(pl061->base + GPIOIS); - gpioibe =3D readb(pl061->base + GPIOIBE); + regmap_read(pl061->regmap, GPIOIEV, &gpioiev); + regmap_read(pl061->regmap, GPIOIS, &gpiois); + regmap_read(pl061->regmap, GPIOIBE, &gpioibe); =20 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { bool polarity =3D trigger & IRQ_TYPE_LEVEL_HIGH; @@ -199,9 +234,9 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) offset); } =20 - writeb(gpiois, pl061->base + GPIOIS); - writeb(gpioibe, pl061->base + GPIOIBE); - writeb(gpioiev, pl061->base + GPIOIEV); + regmap_write(pl061->regmap, GPIOIS, gpiois); + regmap_write(pl061->regmap, GPIOIBE, gpioibe); + regmap_write(pl061->regmap, GPIOIEV, gpioiev); =20 raw_spin_unlock_irqrestore(&pl061->lock, flags); =20 @@ -211,6 +246,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) static void pl061_irq_handler(struct irq_desc *desc) { unsigned long pending; + unsigned int mis =3D 0; int offset; struct gpio_chip *gc =3D irq_desc_get_handler_data(desc); struct pl061 *pl061 =3D gpiochip_get_data(gc); @@ -218,8 +254,9 @@ static void pl061_irq_handler(struct irq_desc *desc) =20 chained_irq_enter(irqchip, desc); =20 - pending =3D readb(pl061->base + GPIOMIS); - if (pending) { + regmap_read(pl061->regmap, GPIOMIS, &mis); + if (mis) { + pending =3D mis; for_each_set_bit(offset, &pending, PL061_GPIO_NR) generic_handle_domain_irq(gc->irq.domain, offset); @@ -233,11 +270,9 @@ static void pl061_irq_mask(struct irq_data *d) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct pl061 *pl061 =3D gpiochip_get_data(gc); u8 mask =3D BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); - u8 gpioie; =20 raw_spin_lock(&pl061->lock); - gpioie =3D readb(pl061->base + GPIOIE) & ~mask; - writeb(gpioie, pl061->base + GPIOIE); + regmap_update_bits(pl061->regmap, GPIOIE, mask, 0); raw_spin_unlock(&pl061->lock); =20 gpiochip_disable_irq(gc, d->hwirq); @@ -248,13 +283,11 @@ static void pl061_irq_unmask(struct irq_data *d) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct pl061 *pl061 =3D gpiochip_get_data(gc); u8 mask =3D BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); - u8 gpioie; =20 gpiochip_enable_irq(gc, d->hwirq); =20 raw_spin_lock(&pl061->lock); - gpioie =3D readb(pl061->base + GPIOIE) | mask; - writeb(gpioie, pl061->base + GPIOIE); + regmap_update_bits(pl061->regmap, GPIOIE, mask, mask); raw_spin_unlock(&pl061->lock); } =20 @@ -272,9 +305,7 @@ static void pl061_irq_ack(struct irq_data *d) struct pl061 *pl061 =3D gpiochip_get_data(gc); u8 mask =3D BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); =20 - raw_spin_lock(&pl061->lock); - writeb(mask, pl061->base + GPIOIC); - raw_spin_unlock(&pl061->lock); + regmap_write(pl061->regmap, GPIOIC, mask); } =20 static int pl061_irq_set_wake(struct irq_data *d, unsigned int state) @@ -308,15 +339,20 @@ static int pl061_probe(struct amba_device *adev, cons= t struct amba_id *id) struct device *dev =3D &adev->dev; struct pl061 *pl061; struct gpio_irq_chip *girq; + void __iomem *base; int ret, irq; =20 pl061 =3D devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL); if (pl061 =3D=3D NULL) return -ENOMEM; =20 - pl061->base =3D devm_ioremap_resource(dev, &adev->res); - if (IS_ERR(pl061->base)) - return PTR_ERR(pl061->base); + base =3D devm_ioremap_resource(dev, &adev->res); + if (IS_ERR(base)) + return PTR_ERR(base); + + pl061->regmap =3D devm_regmap_init_mmio(dev, base, &pl061_regmap_config); + if (IS_ERR(pl061->regmap)) + return PTR_ERR(pl061->regmap); =20 raw_spin_lock_init(&pl061->lock); pl061->gc.request =3D gpiochip_generic_request; @@ -335,7 +371,7 @@ static int pl061_probe(struct amba_device *adev, const = struct amba_id *id) /* * irq_chip support */ - writeb(0, pl061->base + GPIOIE); /* disable irqs */ + regmap_write(pl061->regmap, GPIOIE, 0); /* disable irqs */ irq =3D adev->irq[0]; if (!irq) dev_warn(&adev->dev, "IRQ support disabled\n"); @@ -366,14 +402,20 @@ static int pl061_probe(struct amba_device *adev, cons= t struct amba_id *id) static int pl061_suspend(struct device *dev) { struct pl061 *pl061 =3D dev_get_drvdata(dev); + unsigned int val =3D 0; int offset; =20 pl061->csave_regs.gpio_data =3D 0; - pl061->csave_regs.gpio_dir =3D readb(pl061->base + GPIODIR); - pl061->csave_regs.gpio_is =3D readb(pl061->base + GPIOIS); - pl061->csave_regs.gpio_ibe =3D readb(pl061->base + GPIOIBE); - pl061->csave_regs.gpio_iev =3D readb(pl061->base + GPIOIEV); - pl061->csave_regs.gpio_ie =3D readb(pl061->base + GPIOIE); + regmap_read(pl061->regmap, GPIODIR, &val); + pl061->csave_regs.gpio_dir =3D val; + regmap_read(pl061->regmap, GPIOIS, &val); + pl061->csave_regs.gpio_is =3D val; + regmap_read(pl061->regmap, GPIOIBE, &val); + pl061->csave_regs.gpio_ibe =3D val; + regmap_read(pl061->regmap, GPIOIEV, &val); + pl061->csave_regs.gpio_iev =3D val; + regmap_read(pl061->regmap, GPIOIE, &val); + pl061->csave_regs.gpio_ie =3D val; =20 for (offset =3D 0; offset < PL061_GPIO_NR; offset++) { if (pl061->csave_regs.gpio_dir & (BIT(offset))) @@ -398,10 +440,10 @@ static int pl061_resume(struct device *dev) pl061_direction_input(&pl061->gc, offset); } =20 - writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS); - writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE); - writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV); - writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE); + regmap_write(pl061->regmap, GPIOIS, pl061->csave_regs.gpio_is); + regmap_write(pl061->regmap, GPIOIBE, pl061->csave_regs.gpio_ibe); + regmap_write(pl061->regmap, GPIOIEV, pl061->csave_regs.gpio_iev); + regmap_write(pl061->regmap, GPIOIE, pl061->csave_regs.gpio_ie); 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Thu, 1 Oct 2026 12:41:00 +0000 (UTC) From: Long Zhao via B4 Relay Date: Thu, 01 Oct 2026 20:40:58 +0800 Subject: [PATCH v9 09/15] gpio: pl061: use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-cv75-v5-v9-9-486cc289a4b8@ambarella.com> References: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> In-Reply-To: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Michael Walle , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790858457; l=1367; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=U1oCsZKXHVZucP03LrQEhXlOSCt4fTuqBZIwSw3whzE=; b=oISmmqpKlMHmBfYFuNu7aVod0hPkDafFoFPAccJZKcSf0O39lInAb+3XmP60uGUCD5bTh7Uy/ R9+cRpsyABHCow/ECwU51tuSweEnUBwxd7m1aanD7hza/wMfkUym3P+ X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Use the standard IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH helpers instead of open-coded edge and level comparisons. Reviewed-by: Linus Walleij Signed-off-by: Long Zhao --- drivers/gpio/gpio-pl061.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index 66aea0856bc4..2913daf46aff 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -167,9 +167,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) if (offset < 0 || offset >=3D PL061_GPIO_NR) return -EINVAL; =20 - if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) && - (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))) - { + if ((trigger & IRQ_TYPE_LEVEL_MASK) && (trigger & IRQ_TYPE_EDGE_BOTH)) { dev_err(gc->parent, "trying to configure line %d for both level and edge " "detection, choose one!\n", @@ -184,7 +182,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) regmap_read(pl061->regmap, GPIOIS, &gpiois); regmap_read(pl061->regmap, GPIOIBE, &gpioibe); =20 - if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { + if (trigger & IRQ_TYPE_LEVEL_MASK) { bool polarity =3D trigger & IRQ_TYPE_LEVEL_HIGH; =20 /* Disable edge detection */ --=20 2.34.1 From nobody Fri Oct 2 01:56:21 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A5884A0156; Thu, 1 Oct 2026 12:41:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790858461; cv=none; b=YpR8RaXHfIEKdC1yBFuCVoyHLtwbONp8L+/4wc18yUhkW3lBuEtLGeI/98dOzleAGimZ6aWil8FtXbEhA6WJuk+PR1BtGllObTbmQI5lFmTcSNEM6HlOS6qgjyvmkLDz8eP2MAe3V0qSfQCH4ZRWZzF3WuXuckgrMxnjl7RTCaQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790858461; c=relaxed/simple; bh=If0wC+GOiQ7zcxsssRs823pSXS0Gmw97hDpAPwdxstg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ic16woHs+xrvrtnUd9A3JMtOxhUK+CadfllFFU/q5c7HvQxsWSN6OkMnRisC0ZlMryXi5ZQqJVYdBrDtPlbqv7JRPirGgqWSwZqWlIWVpfyCn9/aglHU8fiHHjAsRgt2jhenezcXjLK3mAGmYPdEUfkmW8mJOcxh1eHh839PDFA= ARC-Authentication-Results: i=1; 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Thu, 1 Oct 2026 12:41:00 +0000 (UTC) From: Long Zhao via B4 Relay Date: Thu, 01 Oct 2026 20:40:59 +0800 Subject: [PATCH v9 10/15] gpio: pl061: use cleanup helpers for locks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-cv75-v5-v9-10-486cc289a4b8@ambarella.com> References: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> In-Reply-To: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Michael Walle , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790858457; l=3433; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=+p9wSAL+DIMK9lo0zXJaXcEuuSD77Y+AjND9Nt/NUOI=; b=7O+R2M1e7s6OW/XgM+x2MDDy0dwOhixg9SQo9cKMIjKrGD5VORzvyoNy3jYonqytR3bLl5NrR sW91ecsgi7NDNlgeGtgX0V0stpD8YF2CPou9Yvm+HSZr3wVKEEKY/Pk X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Convert raw_spinlock critical sections to guard() from cleanup.h. Reviewed-by: Linus Walleij Signed-off-by: Long Zhao --- drivers/gpio/gpio-pl061.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index 2913daf46aff..c821a5117eed 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -10,6 +10,7 @@ */ #include #include +#include #include #include #include @@ -103,11 +104,9 @@ static int pl061_get_direction(struct gpio_chip *gc, u= nsigned offset) static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) { struct pl061 *pl061 =3D gpiochip_get_data(gc); - unsigned long flags; =20 - raw_spin_lock_irqsave(&pl061->lock, flags); + guard(raw_spinlock_irqsave)(&pl061->lock); regmap_update_bits(pl061->regmap, GPIODIR, BIT(offset), 0); - raw_spin_unlock_irqrestore(&pl061->lock, flags); =20 return 0; } @@ -116,10 +115,9 @@ static int pl061_direction_output(struct gpio_chip *gc= , unsigned offset, int value) { struct pl061 *pl061 =3D gpiochip_get_data(gc); - unsigned long flags; unsigned int mask =3D BIT(offset); =20 - raw_spin_lock_irqsave(&pl061->lock, flags); + guard(raw_spinlock_irqsave)(&pl061->lock); regmap_write(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), !!value << offset); regmap_update_bits(pl061->regmap, GPIODIR, mask, mask); @@ -130,7 +128,6 @@ static int pl061_direction_output(struct gpio_chip *gc,= unsigned offset, */ regmap_write(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), !!value << offset); - raw_spin_unlock_irqrestore(&pl061->lock, flags); =20 return 0; } @@ -160,7 +157,6 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct pl061 *pl061 =3D gpiochip_get_data(gc); int offset =3D irqd_to_hwirq(d); - unsigned long flags; unsigned int gpiois =3D 0, gpioibe =3D 0, gpioiev =3D 0; unsigned int bit =3D BIT(offset); =20 @@ -176,7 +172,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) } =20 =20 - raw_spin_lock_irqsave(&pl061->lock, flags); + guard(raw_spinlock_irqsave)(&pl061->lock); =20 regmap_read(pl061->regmap, GPIOIEV, &gpioiev); regmap_read(pl061->regmap, GPIOIS, &gpiois); @@ -236,7 +232,6 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) regmap_write(pl061->regmap, GPIOIBE, gpioibe); regmap_write(pl061->regmap, GPIOIEV, gpioiev); =20 - raw_spin_unlock_irqrestore(&pl061->lock, flags); =20 return 0; } @@ -269,9 +264,8 @@ static void pl061_irq_mask(struct irq_data *d) struct pl061 *pl061 =3D gpiochip_get_data(gc); u8 mask =3D BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); =20 - raw_spin_lock(&pl061->lock); + guard(raw_spinlock)(&pl061->lock); regmap_update_bits(pl061->regmap, GPIOIE, mask, 0); - raw_spin_unlock(&pl061->lock); =20 gpiochip_disable_irq(gc, d->hwirq); } @@ -284,9 +278,8 @@ static void pl061_irq_unmask(struct irq_data *d) =20 gpiochip_enable_irq(gc, d->hwirq); =20 - raw_spin_lock(&pl061->lock); + guard(raw_spinlock)(&pl061->lock); regmap_update_bits(pl061->regmap, GPIOIE, mask, mask); - raw_spin_unlock(&pl061->lock); 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Thu, 1 Oct 2026 12:41:01 +0000 (UTC) From: Long Zhao via B4 Relay Date: Thu, 01 Oct 2026 20:41:00 +0800 Subject: [PATCH v9 11/15] gpio: pl061: switch data path to gpio-regmap Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-cv75-v5-v9-11-486cc289a4b8@ambarella.com> References: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> In-Reply-To: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Michael Walle , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790858457; l=22239; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=8OSNsvOswMdmuAn7i9MfCzVpUtShhIApyFX55kKTOOA=; b=Gqnfm2j+662uBE+ONVppaZ4au2cgwcnACTwrxiESLfU6m94ChsXUv6i9L7DdTA5hKVpnFKQ02 AIxg+2TiKSSBCqLZ7tGLK9DTVzOSRwGS2Tlyb3zZhTn2NlLr80KXwCC X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Move get, set and direction onto gpio-regmap. ARM PL061 sets GPIO_REGMAP_QUIRK_SET_AFTER_DIR so the output value is written after the direction change. Keep a custom irqchip and irq domain. Create the domain with the PL061 private data and let gpio-regmap attach it. Check the chained-handler regmap_read() return and always run chained_irq_exit(). irq_type still ignores MMIO write returns. irq_set_parent() nests the GPIO irq_desc under the AMBA parent for irq_set_wake() and lockdep; checked with PROVE_LOCKING on CV75. Signed-off-by: Long Zhao --- drivers/gpio/Kconfig | 1 + drivers/gpio/gpio-pl061.c | 505 ++++++++++++++++++++++++++----------------= ---- 2 files changed, 288 insertions(+), 218 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 2a1487bd1a94..55a129836158 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -583,6 +583,7 @@ config GPIO_PL061 depends on ARM_AMBA || COMPILE_TEST select IRQ_DOMAIN select GPIOLIB_IRQCHIP + select GPIO_REGMAP select REGMAP_MMIO help Say yes here to support the PrimeCell PL061 GPIO device. diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index c821a5117eed..08d45f8923c2 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -12,171 +12,111 @@ #include #include #include -#include -#include -#include +#include +#include #include #include #include #include #include +#include #include #include -#include #include #include #include -#include #include =20 -#define GPIODIR 0x400 -#define GPIOIS 0x404 -#define GPIOIBE 0x408 -#define GPIOIEV 0x40C -#define GPIOIE 0x410 -#define GPIORIS 0x414 -#define GPIOMIS 0x418 -#define GPIOIC 0x41C - #define PL061_GPIO_NR 8 #define PL061_DATA_OFFSET 2 =20 -struct pl061_context_save_regs { - u8 gpio_data; - u8 gpio_dir; - u8 gpio_is; - u8 gpio_ibe; - u8 gpio_iev; - u8 gpio_ie; +#define PL061_DIR 0x400 +#define PL061_IS 0x404 +#define PL061_IBE 0x408 +#define PL061_IEV 0x40c +#define PL061_IE 0x410 +#define PL061_MIS 0x418 +#define PL061_IC 0x41c + +struct pl061_regs { + unsigned int dat; + unsigned int dir; + unsigned int is; + unsigned int ibe; + unsigned int iev; + unsigned int ie; + unsigned int mis; + unsigned int ic; + unsigned int mask; + unsigned int enable; +}; + +struct pl061_drvdata { + const struct regmap_config *regmap_config; + const struct pl061_regs *regs; + unsigned int ngpio; + unsigned long quirks; + bool clear_irq_on_type; + bool pm; + int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base, + unsigned int offset, unsigned int *reg, + unsigned int *mask); }; =20 struct pl061 { raw_spinlock_t lock; =20 + struct device *dev; struct regmap *regmap; - struct gpio_chip gc; + const struct pl061_drvdata *data; + struct irq_domain *irq_domain; int parent_irq; =20 - struct pl061_context_save_regs csave_regs; + u32 saved_dat; }; =20 -static bool pl061_is_data_reg(unsigned int reg) -{ - return is_power_of_2(reg) && - reg >=3D BIT(PL061_DATA_OFFSET) && - reg <=3D BIT(PL061_DATA_OFFSET + PL061_GPIO_NR - 1); -} - -static bool pl061_volatile_reg(struct device *dev, unsigned int reg) -{ - switch (reg) { - case GPIOMIS: - case GPIOIC: - return true; - default: - return pl061_is_data_reg(reg); - } -} - -static const struct regmap_config pl061_regmap_config =3D { - .reg_bits =3D 16, - .val_bits =3D 8, - .reg_stride =3D 4, - .max_register =3D GPIOIC, - .volatile_reg =3D pl061_volatile_reg, - .fast_io =3D true, - .use_raw_spinlock =3D true, -}; - -static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) -{ - struct pl061 *pl061 =3D gpiochip_get_data(gc); - unsigned int gpiodir =3D 0; - - regmap_read(pl061->regmap, GPIODIR, &gpiodir); - - if (gpiodir & BIT(offset)) - return GPIO_LINE_DIRECTION_OUT; - - return GPIO_LINE_DIRECTION_IN; -} - -static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) -{ - struct pl061 *pl061 =3D gpiochip_get_data(gc); - - guard(raw_spinlock_irqsave)(&pl061->lock); - regmap_update_bits(pl061->regmap, GPIODIR, BIT(offset), 0); - - return 0; -} - -static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, - int value) +static unsigned int pl061_line_mask(struct pl061 *pl061, irq_hw_number_t h= wirq) { - struct pl061 *pl061 =3D gpiochip_get_data(gc); - unsigned int mask =3D BIT(offset); - - guard(raw_spinlock_irqsave)(&pl061->lock); - regmap_write(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), - !!value << offset); - regmap_update_bits(pl061->regmap, GPIODIR, mask, mask); - - /* - * gpio value is set again, because pl061 doesn't allow to set value of - * a gpio pin before configuring it in OUT mode. - */ - regmap_write(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), - !!value << offset); - - return 0; + return BIT(hwirq % pl061->data->ngpio); } =20 -static int pl061_get_value(struct gpio_chip *gc, unsigned offset) +static int pl061_arm_reg_mask_xlate(struct gpio_regmap *gpio, unsigned int= base, + unsigned int offset, unsigned int *reg, + unsigned int *mask) { - struct pl061 *pl061 =3D gpiochip_get_data(gc); - unsigned int val =3D 0; - - regmap_read(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), &val); - - return !!val; -} - -static int pl061_set_value(struct gpio_chip *gc, unsigned int offset, int = value) -{ - struct pl061 *pl061 =3D gpiochip_get_data(gc); - - regmap_write(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), - !!value << offset); + if (base =3D=3D 0) + *reg =3D BIT(offset + PL061_DATA_OFFSET); + else + *reg =3D base; + *mask =3D BIT(offset); =20 return 0; } =20 -static int pl061_irq_type(struct irq_data *d, unsigned trigger) +static int pl061_irq_type(struct irq_data *d, unsigned int trigger) { - struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); - struct pl061 *pl061 =3D gpiochip_get_data(gc); + struct pl061 *pl061 =3D irq_data_get_irq_chip_data(d); + const struct pl061_regs *regs =3D pl061->data->regs; int offset =3D irqd_to_hwirq(d); unsigned int gpiois =3D 0, gpioibe =3D 0, gpioiev =3D 0; unsigned int bit =3D BIT(offset); =20 - if (offset < 0 || offset >=3D PL061_GPIO_NR) + if (offset < 0 || offset >=3D pl061->data->ngpio) return -EINVAL; =20 if ((trigger & IRQ_TYPE_LEVEL_MASK) && (trigger & IRQ_TYPE_EDGE_BOTH)) { - dev_err(gc->parent, + dev_err(pl061->dev, "trying to configure line %d for both level and edge " "detection, choose one!\n", offset); return -EINVAL; } =20 - guard(raw_spinlock_irqsave)(&pl061->lock); =20 - regmap_read(pl061->regmap, GPIOIEV, &gpioiev); - regmap_read(pl061->regmap, GPIOIS, &gpiois); - regmap_read(pl061->regmap, GPIOIBE, &gpioibe); + regmap_read(pl061->regmap, regs->iev, &gpioiev); + regmap_read(pl061->regmap, regs->is, &gpiois); + regmap_read(pl061->regmap, regs->ibe, &gpioibe); =20 if (trigger & IRQ_TYPE_LEVEL_MASK) { bool polarity =3D trigger & IRQ_TYPE_LEVEL_HIGH; @@ -191,7 +131,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) else gpioiev &=3D ~bit; irq_set_handler_locked(d, handle_level_irq); - dev_dbg(gc->parent, "line %d: IRQ on %s level\n", + dev_dbg(pl061->dev, "line %d: IRQ on %s level\n", offset, polarity ? "HIGH" : "LOW"); } else if ((trigger & IRQ_TYPE_EDGE_BOTH) =3D=3D IRQ_TYPE_EDGE_BOTH) { @@ -200,7 +140,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) /* Select both edges, setting this makes GPIOEV be ignored */ gpioibe |=3D bit; irq_set_handler_locked(d, handle_edge_irq); - dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset); + dev_dbg(pl061->dev, "line %d: IRQ on both edges\n", offset); } else if ((trigger & IRQ_TYPE_EDGE_RISING) || (trigger & IRQ_TYPE_EDGE_FALLING)) { bool rising =3D trigger & IRQ_TYPE_EDGE_RISING; @@ -215,7 +155,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) else gpioiev &=3D ~bit; irq_set_handler_locked(d, handle_edge_irq); - dev_dbg(gc->parent, "line %d: IRQ on %s edge\n", + dev_dbg(pl061->dev, "line %d: IRQ on %s edge\n", offset, rising ? "RISING" : "FALLING"); } else { @@ -224,14 +164,15 @@ static int pl061_irq_type(struct irq_data *d, unsigne= d trigger) gpioibe &=3D ~bit; gpioiev &=3D ~bit; irq_set_handler_locked(d, handle_bad_irq); - dev_warn(gc->parent, "no trigger selected for line %d\n", + dev_warn(pl061->dev, "no trigger selected for line %d\n", offset); } =20 - regmap_write(pl061->regmap, GPIOIS, gpiois); - regmap_write(pl061->regmap, GPIOIBE, gpioibe); - regmap_write(pl061->regmap, GPIOIEV, gpioiev); - + regmap_write(pl061->regmap, regs->is, gpiois); + regmap_write(pl061->regmap, regs->ibe, gpioibe); + regmap_write(pl061->regmap, regs->iev, gpioiev); + if (pl061->data->clear_irq_on_type) + regmap_write(pl061->regmap, regs->ic, bit); =20 return 0; } @@ -240,46 +181,40 @@ static void pl061_irq_handler(struct irq_desc *desc) { unsigned long pending; unsigned int mis =3D 0; - int offset; - struct gpio_chip *gc =3D irq_desc_get_handler_data(desc); - struct pl061 *pl061 =3D gpiochip_get_data(gc); + int offset, ret; + struct pl061 *pl061 =3D irq_desc_get_handler_data(desc); struct irq_chip *irqchip =3D irq_desc_get_chip(desc); =20 chained_irq_enter(irqchip, desc); =20 - regmap_read(pl061->regmap, GPIOMIS, &mis); + ret =3D regmap_read(pl061->regmap, pl061->data->regs->mis, &mis); + if (ret) + goto out; + if (mis) { pending =3D mis; - for_each_set_bit(offset, &pending, PL061_GPIO_NR) - generic_handle_domain_irq(gc->irq.domain, - offset); + for_each_set_bit(offset, &pending, pl061->data->ngpio) + generic_handle_domain_irq(pl061->irq_domain, offset); } =20 +out: chained_irq_exit(irqchip, desc); } =20 static void pl061_irq_mask(struct irq_data *d) { - struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); - struct pl061 *pl061 =3D gpiochip_get_data(gc); - u8 mask =3D BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); - - guard(raw_spinlock)(&pl061->lock); - regmap_update_bits(pl061->regmap, GPIOIE, mask, 0); + struct pl061 *pl061 =3D irq_data_get_irq_chip_data(d); + unsigned int mask =3D pl061_line_mask(pl061, irqd_to_hwirq(d)); =20 - gpiochip_disable_irq(gc, d->hwirq); + regmap_update_bits(pl061->regmap, pl061->data->regs->ie, mask, 0); } =20 static void pl061_irq_unmask(struct irq_data *d) { - struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); - struct pl061 *pl061 =3D gpiochip_get_data(gc); - u8 mask =3D BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); + struct pl061 *pl061 =3D irq_data_get_irq_chip_data(d); + unsigned int mask =3D pl061_line_mask(pl061, irqd_to_hwirq(d)); =20 - gpiochip_enable_irq(gc, d->hwirq); - - guard(raw_spinlock)(&pl061->lock); - regmap_update_bits(pl061->regmap, GPIOIE, mask, mask); + regmap_update_bits(pl061->regmap, pl061->data->regs->ie, mask, mask); } =20 /** @@ -292,29 +227,28 @@ static void pl061_irq_unmask(struct irq_data *d) */ static void pl061_irq_ack(struct irq_data *d) { - struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); - struct pl061 *pl061 =3D gpiochip_get_data(gc); - u8 mask =3D BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); + struct pl061 *pl061 =3D irq_data_get_irq_chip_data(d); + unsigned int mask =3D pl061_line_mask(pl061, irqd_to_hwirq(d)); =20 - regmap_write(pl061->regmap, GPIOIC, mask); + regmap_write(pl061->regmap, pl061->data->regs->ic, mask); } =20 static int pl061_irq_set_wake(struct irq_data *d, unsigned int state) { - struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); - struct pl061 *pl061 =3D gpiochip_get_data(gc); + struct pl061 *pl061 =3D irq_data_get_irq_chip_data(d); =20 return irq_set_irq_wake(pl061->parent_irq, state); } =20 static void pl061_irq_print_chip(struct irq_data *data, struct seq_file *p) { - struct gpio_chip *gc =3D irq_data_get_irq_chip_data(data); + struct pl061 *pl061 =3D irq_data_get_irq_chip_data(data); =20 - seq_puts(p, dev_name(gc->parent)); + seq_puts(p, dev_name(pl061->dev)); } =20 -static const struct irq_chip pl061_irq_chip =3D { +static const struct irq_chip pl061_irqchip =3D { + .name =3D "pl061", .irq_ack =3D pl061_irq_ack, .irq_mask =3D pl061_irq_mask, .irq_unmask =3D pl061_irq_unmask, @@ -322,67 +256,187 @@ static const struct irq_chip pl061_irq_chip =3D { .irq_set_wake =3D pl061_irq_set_wake, .irq_print_chip =3D pl061_irq_print_chip, .flags =3D IRQCHIP_IMMUTABLE, - GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static int pl061_irq_domain_map(struct irq_domain *d, unsigned int virq, + irq_hw_number_t hwirq) +{ + struct pl061 *pl061 =3D d->host_data; + + irq_set_chip_data(virq, pl061); + irq_set_chip_and_handler(virq, &pl061_irqchip, handle_bad_irq); + irq_set_noprobe(virq); + irq_set_parent(virq, pl061->parent_irq); + + return 0; +} + +static void pl061_irq_domain_unmap(struct irq_domain *d, unsigned int virq) +{ + irq_set_chip_and_handler(virq, NULL, NULL); + irq_set_chip_data(virq, NULL); +} + +static const struct irq_domain_ops pl061_irq_domain_ops =3D { + .map =3D pl061_irq_domain_map, + .unmap =3D pl061_irq_domain_unmap, + .xlate =3D irq_domain_xlate_twothreecell, +}; + +static void pl061_remove_irq(void *data) +{ + struct pl061 *pl061 =3D data; + + irq_set_chained_handler_and_data(pl061->parent_irq, NULL, NULL); + + for (unsigned int i =3D 0; i < pl061->data->ngpio; i++) { + unsigned int virq; + + virq =3D irq_find_mapping(pl061->irq_domain, i); + if (virq) + irq_dispose_mapping(virq); + } + + irq_domain_remove(pl061->irq_domain); +} + +static bool pl061_arm_is_data_reg(unsigned int reg) +{ + return reg >=3D BIT(PL061_DATA_OFFSET) && + reg <=3D BIT(PL061_DATA_OFFSET + PL061_GPIO_NR - 1) && + is_power_of_2(reg); +} + +static bool pl061_arm_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case PL061_MIS: + case PL061_IC: + return true; + default: + return pl061_arm_is_data_reg(reg); + } +} + +static const struct regmap_config pl061_arm_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .reg_stride =3D 4, + .max_register =3D PL061_IC, + .volatile_reg =3D pl061_arm_volatile_reg, + .cache_type =3D REGCACHE_FLAT_S, + .fast_io =3D true, + .use_raw_spinlock =3D true, +}; + +static const struct pl061_regs pl061_arm_regs =3D { + .dir =3D PL061_DIR, + .is =3D PL061_IS, + .ibe =3D PL061_IBE, + .iev =3D PL061_IEV, + .ie =3D PL061_IE, + .mis =3D PL061_MIS, + .ic =3D PL061_IC, +}; + +static const struct pl061_drvdata pl061_arm =3D { + .regmap_config =3D &pl061_arm_regmap_config, + .regs =3D &pl061_arm_regs, + .ngpio =3D PL061_GPIO_NR, + .quirks =3D GPIO_REGMAP_QUIRK_SET_AFTER_DIR, + .pm =3D true, + .reg_mask_xlate =3D pl061_arm_reg_mask_xlate, }; =20 static int pl061_probe(struct amba_device *adev, const struct amba_id *id) { struct device *dev =3D &adev->dev; + const struct pl061_drvdata *data; + const struct pl061_regs *regs; + struct gpio_regmap_config config =3D {}; + struct gpio_regmap *gpio_regmap; struct pl061 *pl061; - struct gpio_irq_chip *girq; void __iomem *base; int ret, irq; =20 + data =3D id->data; + if (!data) + return -ENODATA; + + regs =3D data->regs; + pl061 =3D devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL); if (pl061 =3D=3D NULL) return -ENOMEM; =20 + pl061->dev =3D dev; + pl061->data =3D data; + base =3D devm_ioremap_resource(dev, &adev->res); if (IS_ERR(base)) return PTR_ERR(base); =20 - pl061->regmap =3D devm_regmap_init_mmio(dev, base, &pl061_regmap_config); + pl061->regmap =3D devm_regmap_init_mmio(dev, base, data->regmap_config); if (IS_ERR(pl061->regmap)) return PTR_ERR(pl061->regmap); =20 raw_spin_lock_init(&pl061->lock); - pl061->gc.request =3D gpiochip_generic_request; - pl061->gc.free =3D gpiochip_generic_free; - pl061->gc.base =3D -1; - pl061->gc.get_direction =3D pl061_get_direction; - pl061->gc.direction_input =3D pl061_direction_input; - pl061->gc.direction_output =3D pl061_direction_output; - pl061->gc.get =3D pl061_get_value; - pl061->gc.set =3D pl061_set_value; - pl061->gc.ngpio =3D PL061_GPIO_NR; - pl061->gc.label =3D dev_name(dev); - pl061->gc.parent =3D dev; - pl061->gc.owner =3D THIS_MODULE; + + if (regs->enable) { + ret =3D regmap_write(pl061->regmap, regs->enable, ~0U); + if (ret) + return ret; + } + if (regs->mask) { + ret =3D regmap_write(pl061->regmap, regs->mask, ~0U); + if (ret) + return ret; + } =20 /* * irq_chip support */ - regmap_write(pl061->regmap, GPIOIE, 0); /* disable irqs */ + regmap_write(pl061->regmap, regs->ie, 0); /* disable irqs */ + irq =3D adev->irq[0]; if (!irq) - dev_warn(&adev->dev, "IRQ support disabled\n"); + dev_warn(dev, "IRQ support disabled\n"); pl061->parent_irq =3D irq; =20 - girq =3D &pl061->gc.irq; - gpio_irq_chip_set_chip(girq, &pl061_irq_chip); - girq->parent_handler =3D pl061_irq_handler; - girq->num_parents =3D 1; - girq->parents =3D devm_kcalloc(dev, 1, sizeof(*girq->parents), - GFP_KERNEL); - if (!girq->parents) - return -ENOMEM; - girq->parents[0] =3D irq; - girq->default_type =3D IRQ_TYPE_NONE; - girq->handler =3D handle_bad_irq; + if (irq) { + pl061->irq_domain =3D irq_domain_create_linear(dev_fwnode(dev), + data->ngpio, + &pl061_irq_domain_ops, + pl061); + if (!pl061->irq_domain) + return -ENOMEM; + } =20 - ret =3D devm_gpiochip_add_data(dev, &pl061->gc, pl061); - if (ret) - return ret; + config.parent =3D dev; + config.regmap =3D pl061->regmap; + config.ngpio =3D data->ngpio; + config.reg_dat_base =3D GPIO_REGMAP_ADDR(regs->dat); + config.reg_set_base =3D GPIO_REGMAP_ADDR(regs->dat); + config.reg_dir_out_base =3D GPIO_REGMAP_ADDR(regs->dir); + config.reg_mask_xlate =3D data->reg_mask_xlate; + config.quirks =3D data->quirks; + config.irq_domain =3D pl061->irq_domain; + config.drvdata =3D pl061; + + gpio_regmap =3D devm_gpio_regmap_register(dev, &config); + if (IS_ERR(gpio_regmap)) { + if (pl061->irq_domain) + irq_domain_remove(pl061->irq_domain); + return PTR_ERR(gpio_regmap); + } + + if (irq) { + ret =3D devm_add_action_or_reset(dev, pl061_remove_irq, pl061); + if (ret) + return ret; + + irq_set_chained_handler_and_data(irq, pl061_irq_handler, pl061); + } =20 amba_set_drvdata(adev, pl061); dev_info(dev, "PL061 GPIO chip registered\n"); @@ -390,28 +444,38 @@ static int pl061_probe(struct amba_device *adev, cons= t struct amba_id *id) return 0; } =20 +static void pl061_cache_ctrl_regs(struct pl061 *pl061, unsigned int *dir) +{ + const struct pl061_regs *regs =3D pl061->data->regs; + unsigned int val; + + regmap_read(pl061->regmap, regs->dir, dir); + regmap_read(pl061->regmap, regs->is, &val); + regmap_read(pl061->regmap, regs->ibe, &val); + regmap_read(pl061->regmap, regs->iev, &val); + regmap_read(pl061->regmap, regs->ie, &val); +} + static int pl061_suspend(struct device *dev) { struct pl061 *pl061 =3D dev_get_drvdata(dev); - unsigned int val =3D 0; - int offset; - - pl061->csave_regs.gpio_data =3D 0; - regmap_read(pl061->regmap, GPIODIR, &val); - pl061->csave_regs.gpio_dir =3D val; - regmap_read(pl061->regmap, GPIOIS, &val); - pl061->csave_regs.gpio_is =3D val; - regmap_read(pl061->regmap, GPIOIBE, &val); - pl061->csave_regs.gpio_ibe =3D val; - regmap_read(pl061->regmap, GPIOIEV, &val); - pl061->csave_regs.gpio_iev =3D val; - regmap_read(pl061->regmap, GPIOIE, &val); - pl061->csave_regs.gpio_ie =3D val; - - for (offset =3D 0; offset < PL061_GPIO_NR; offset++) { - if (pl061->csave_regs.gpio_dir & (BIT(offset))) - pl061->csave_regs.gpio_data |=3D - pl061_get_value(&pl061->gc, offset) << offset; + unsigned long dir_mask; + unsigned int dir =3D 0, val; + unsigned int offset; + + if (!pl061->data->pm) + return 0; + + pl061_cache_ctrl_regs(pl061, &dir); + + pl061->saved_dat =3D 0; + dir_mask =3D dir; + for_each_set_bit(offset, &dir_mask, pl061->data->ngpio) { + val =3D 0; + regmap_read_bypassed(pl061->regmap, + BIT(offset + PL061_DATA_OFFSET), + &val); + pl061->saved_dat |=3D val; } =20 return 0; @@ -420,23 +484,27 @@ static int pl061_suspend(struct device *dev) static int pl061_resume(struct device *dev) { struct pl061 *pl061 =3D dev_get_drvdata(dev); - int offset; + const struct pl061_regs *regs; + unsigned long dir_mask; + unsigned int dir =3D 0, offset; =20 - for (offset =3D 0; offset < PL061_GPIO_NR; offset++) { - if (pl061->csave_regs.gpio_dir & (BIT(offset))) - pl061_direction_output(&pl061->gc, offset, - pl061->csave_regs.gpio_data & - (BIT(offset))); - else - pl061_direction_input(&pl061->gc, offset); - } + if (!pl061->data->pm) + return 0; =20 - regmap_write(pl061->regmap, GPIOIS, pl061->csave_regs.gpio_is); - regmap_write(pl061->regmap, GPIOIBE, pl061->csave_regs.gpio_ibe); - regmap_write(pl061->regmap, GPIOIEV, pl061->csave_regs.gpio_iev); - regmap_write(pl061->regmap, GPIOIE, pl061->csave_regs.gpio_ie); + regs =3D pl061->data->regs; =20 - return 0; + regmap_read(pl061->regmap, regs->dir, &dir); + + regcache_mark_dirty(pl061->regmap); + regcache_sync_region(pl061->regmap, regs->dir, regs->dir); + + dir_mask =3D dir; + for_each_set_bit(offset, &dir_mask, pl061->data->ngpio) + regmap_write(pl061->regmap, + BIT(offset + PL061_DATA_OFFSET), + !!(pl061->saved_dat & BIT(offset)) << offset); + + return regcache_sync_region(pl061->regmap, regs->is, regs->ie); } =20 static DEFINE_SIMPLE_DEV_PM_OPS(pl061_dev_pm_ops, pl061_suspend, pl061_res= ume); @@ -445,6 +513,7 @@ static const struct amba_id pl061_ids[] =3D { { .id =3D 0x00041061, .mask =3D 0x000fffff, + .data =3D (void *)&pl061_arm, }, { 0, 0 }, }; --=20 2.34.1 From nobody Fri Oct 2 01:56:21 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 926044A3F3A; Thu, 1 Oct 2026 12:41:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-cv75-v5-v9-12-486cc289a4b8@ambarella.com> References: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> In-Reply-To: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Michael Walle , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790858457; l=3980; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=zkcP1Kw3eAzvUqGloHYc7RvGy1ic8OilRLpgIyaHt+g=; b=aELpVqcQ75J00/Y5KnPay/cS7j5IeCOQryL+L5vSiG/TcrKE0DpqxnBrzWttyUQuRamUnMB5I Kym3GxpVmgZCA6rt/platVmD1Cja7CNcUSjL36GKB7D33soedss7XiV X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Add a 32-bit, 32-line layout with DAT/DIR/IS/IBE/IEV/IE/MIS/IC plus MASK and ENABLE. Probe unmasks the bank and enables the controller. IRQ type changes also clear the pending bit. This derivative does not need write-after-direction or system suspend save/restore. Match the part with designer AMBA_VENDOR_AMBARELLA (JEP106 identity 0x68, bit 7 set) and part number 0x061. Reviewed-by: Andy Shevchenko Reviewed-by: Linus Walleij Signed-off-by: Long Zhao --- drivers/gpio/gpio-pl061.c | 59 +++++++++++++++++++++++++++++++++++++++++++= ++++ include/linux/amba/bus.h | 1 + 2 files changed, 60 insertions(+) diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index 08d45f8923c2..bbb9eeeb074a 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -38,6 +38,18 @@ #define PL061_MIS 0x418 #define PL061_IC 0x41c =20 +#define AMBARELLA_GPIO_NR 32 +#define AMBARELLA_DAT 0x00 +#define AMBARELLA_DIR 0x04 +#define AMBARELLA_IS 0x08 +#define AMBARELLA_IBE 0x0c +#define AMBARELLA_IEV 0x10 +#define AMBARELLA_IE 0x14 +#define AMBARELLA_MIS 0x20 +#define AMBARELLA_IC 0x24 +#define AMBARELLA_MASK 0x28 +#define AMBARELLA_ENABLE 0x2c + struct pl061_regs { unsigned int dat; unsigned int dir; @@ -318,6 +330,18 @@ static bool pl061_arm_volatile_reg(struct device *dev,= unsigned int reg) } } =20 +static bool pl061_ambarella_volatile_reg(struct device *dev, unsigned int = reg) +{ + switch (reg) { + case AMBARELLA_DAT: + case AMBARELLA_MIS: + case AMBARELLA_IC: + return true; + default: + return false; + } +} + static const struct regmap_config pl061_arm_regmap_config =3D { .reg_bits =3D 16, .val_bits =3D 8, @@ -329,6 +353,16 @@ static const struct regmap_config pl061_arm_regmap_con= fig =3D { .use_raw_spinlock =3D true, }; =20 +static const struct regmap_config pl061_ambarella_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D AMBARELLA_ENABLE, + .volatile_reg =3D pl061_ambarella_volatile_reg, + .fast_io =3D true, + .use_raw_spinlock =3D true, +}; + static const struct pl061_regs pl061_arm_regs =3D { .dir =3D PL061_DIR, .is =3D PL061_IS, @@ -339,6 +373,19 @@ static const struct pl061_regs pl061_arm_regs =3D { .ic =3D PL061_IC, }; =20 +static const struct pl061_regs pl061_ambarella_regs =3D { + .dat =3D AMBARELLA_DAT, + .dir =3D AMBARELLA_DIR, + .is =3D AMBARELLA_IS, + .ibe =3D AMBARELLA_IBE, + .iev =3D AMBARELLA_IEV, + .ie =3D AMBARELLA_IE, + .mis =3D AMBARELLA_MIS, + .ic =3D AMBARELLA_IC, + .mask =3D AMBARELLA_MASK, + .enable =3D AMBARELLA_ENABLE, +}; + static const struct pl061_drvdata pl061_arm =3D { .regmap_config =3D &pl061_arm_regmap_config, .regs =3D &pl061_arm_regs, @@ -348,6 +395,13 @@ static const struct pl061_drvdata pl061_arm =3D { .reg_mask_xlate =3D pl061_arm_reg_mask_xlate, }; =20 +static const struct pl061_drvdata pl061_ambarella =3D { + .regmap_config =3D &pl061_ambarella_regmap_config, + .regs =3D &pl061_ambarella_regs, + .ngpio =3D AMBARELLA_GPIO_NR, + .clear_irq_on_type =3D true, +}; + static int pl061_probe(struct amba_device *adev, const struct amba_id *id) { struct device *dev =3D &adev->dev; @@ -515,6 +569,11 @@ static const struct amba_id pl061_ids[] =3D { .mask =3D 0x000fffff, .data =3D (void *)&pl061_arm, }, + { + .id =3D (AMBA_VENDOR_AMBARELLA << 12) | 0x061, + .mask =3D 0x000fffff, + .data =3D (void *)&pl061_ambarella, + }, { 0, 0 }, }; MODULE_DEVICE_TABLE(amba, pl061_ids); diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h index 80a74cd2da7e..411533bfa61d 100644 --- a/include/linux/amba/bus.h +++ b/include/linux/amba/bus.h @@ -98,6 +98,7 @@ enum amba_vendor { AMBA_VENDOR_ST =3D 0x80, AMBA_VENDOR_QCOM =3D 0x51, AMBA_VENDOR_LSI =3D 0xb6, + AMBA_VENDOR_AMBARELLA =3D 0xe8, }; =20 extern const struct bus_type amba_bustype; --=20 2.34.1 From nobody Fri Oct 2 01:56:21 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A4E94A482B; Thu, 1 Oct 2026 12:41:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790858461; cv=none; b=neydT0zj5gg07CxHVPEOPbl7tgKNSHNOifsV8rjoPw4Jt/YO5Dz6nCVZaMqHS96eGSs6j+3ScdPUUbtgTLwiLvuobvte/AMHFzLxUqzOAeo5lfWog9zgTiTSS1WNbtOSqELHK9nSXHaTElu0Gv/+X37FXJnEMY0kG6w2FoRjmmk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790858461; c=relaxed/simple; bh=5GFqfQIbCg2UdEeRrw8f0OXijIQlOGnsXzu/vsVQh9g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Thu, 1 Oct 2026 12:41:01 +0000 (UTC) From: Long Zhao via B4 Relay Date: Thu, 01 Oct 2026 20:41:02 +0800 Subject: [PATCH v9 13/15] serial: 8250_dw: add Ambarella CV75 quirks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-cv75-v5-v9-13-486cc289a4b8@ambarella.com> References: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> In-Reply-To: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Michael Walle , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790858457; l=3394; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=r8t/FG9wW+i95rGWMVag4aWVspLRurIpWPfr+INLVog=; b=zYqXL5VhVoN6IFAyuoqzAJMa9KMzDITFw8Ug5wFqGP1Xfm4cl4chVZ+rzAZyG1Fl35oaT7iBU ybJvCbw6+TcCcf/gBsmOrr1aVIdq7mLXTz4JqQeE4RTXI2Tr2PDNPo2 X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao The Ambarella CV75 UART is Ambarella IP, not a Synopsys DesignWare licensed block. At the register level it is close enough to DW APB UART that a full custom UART driver is unnecessary: reuse 8250_dw with a small platform quirk. Quirks: - keep IER ETOI (bit 5) set for RX timeout behaviour - skip set_rate; baud clock is managed outside the UART block Reviewed-by: Linus Walleij Reviewed-by: Andy Shevchenko Reviewed-by: Ilpo J=C3=A4rvinen Signed-off-by: Long Zhao --- drivers/tty/serial/8250/8250_dw.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/82= 50_dw.c index 5fba913f3301..06f03e893346 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -43,6 +43,9 @@ #define RZN1_UART_xDMACR_8_WORD_BURST (2 << 1) #define RZN1_UART_xDMACR_BLK_SZ(x) ((x) << 3) =20 +/* Ambarella IER: receive timeout interrupt enable */ +#define AMBARELLA_UART_IER_ETOI BIT(5) + /* Quirks */ #define DW_UART_QUIRK_OCTEON BIT(0) #define DW_UART_QUIRK_ARMADA_38X BIT(1) @@ -60,6 +63,7 @@ =20 struct dw8250_platform_data { u8 usr_reg; + u8 ier_mask; u32 cpr_value; unsigned int quirks; }; @@ -572,6 +576,25 @@ static void dw8250_prepare_rx_dma(struct uart_8250_por= t *p) dw8250_writel_ext(up, RZN1_UART_RDMACR, val); } =20 +static int dw8250_ier_mask_startup(struct uart_port *p) +{ + struct dw8250_data *d =3D to_dw8250_data(p->private_data); + struct uart_8250_port *up =3D up_to_u8250p(p); + int ret; + + ret =3D serial8250_do_startup(p); + if (ret) + return ret; + + /* + * Ambarella keeps variant IER bits (e.g. ETOI) set for correct RX + * timeout behaviour. + */ + up->ier |=3D d->pdata->ier_mask; + + return 0; +} + static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) { unsigned int quirks =3D data->pdata->quirks; @@ -606,6 +629,8 @@ static void dw8250_quirks(struct uart_port *p, struct d= w8250_data *data) p->serial_in =3D dw8250_serial_in32; data->uart_16550_compatible =3D true; } + if (data->pdata->ier_mask) + p->startup =3D dw8250_ier_mask_startup; } =20 static void dw8250_reset_control_assert(void *data) @@ -879,6 +904,12 @@ static const struct dw8250_platform_data dw8250_intc10= ee =3D { .quirks =3D DW_UART_QUIRK_IER_KICK, }; =20 +static const struct dw8250_platform_data dw8250_ambarella_cv75_data =3D { + .usr_reg =3D DW_UART_USR, + .ier_mask =3D AMBARELLA_UART_IER_ETOI, + .quirks =3D DW_UART_QUIRK_SKIP_SET_RATE, +}; + static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data =3D { .usr_reg =3D DW_UART_USR, .cpr_value =3D FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) | @@ -890,6 +921,7 @@ static const struct dw8250_platform_data dw8250_ultrari= sc_dp1000_data =3D { =20 static const struct of_device_id dw8250_of_match[] =3D { { .compatible =3D "snps,dw-apb-uart", .data =3D &dw8250_dw_apb }, + { .compatible =3D "ambarella,cv75-uart", .data =3D &dw8250_ambarella_cv75= _data }, { .compatible =3D "cavium,octeon-3860-uart", .data =3D &dw8250_octeon_386= 0_data }, { .compatible =3D "marvell,armada-38x-uart", .data =3D &dw8250_armada_38x= _data }, { .compatible =3D "renesas,rzn1-uart", .data =3D &dw8250_renesas_rzn1_dat= a }, --=20 2.34.1 From nobody Fri Oct 2 01:56:21 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA8474A64D4; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-cv75-v5-v9-14-486cc289a4b8@ambarella.com> References: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> In-Reply-To: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Michael Walle , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790858457; l=8107; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=DEAMc2vofaBUV896UxD87q9HiCotMrVdpC7L4SePgqQ=; b=gMUhRvVsooteiO91gN6VHmeL4sr01gdREvC0cmsbgXCHk7UlQcNEjjrM8hPECBo5VVDrEKhmn 9LT9KUgSkB1ABvvzfkPC6vfxcxd3vnDOcQznbOALCATUiQWwjl0nMdg X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Enable ARCH_AMBARELLA and add a minimal CV75 SoC / EVK device tree for console bring-up with the RCT clocks, UART, pinctrl and GPIO banks. Reviewed-by: Linus Walleij Signed-off-by: Long Zhao --- arch/arm64/Kconfig.platforms | 6 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/ambarella/Makefile | 3 + arch/arm64/boot/dts/ambarella/cv75-evk.dts | 30 +++++ arch/arm64/boot/dts/ambarella/cv75.dtsi | 177 +++++++++++++++++++++++++= ++++ arch/arm64/configs/defconfig | 1 + 6 files changed, 218 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index d2acfac73003..16d7e3a4c2d6 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -26,6 +26,12 @@ config ARCH_SUNXI help This enables support for Allwinner sunxi based SoCs like the A64. =20 +config ARCH_AMBARELLA + bool "Ambarella SoC family" + select PINCTRL + help + This enables support for the ARM64 based Ambarella SoCs like CV75. + config ARCH_ALPINE bool "Annapurna Labs Alpine platform" select ALPINE_MSI if PCI diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index fc726b215f12..f1709eb5d915 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -4,6 +4,7 @@ subdir-y +=3D airoha subdir-y +=3D allwinner subdir-y +=3D altera subdir-y +=3D amazon +subdir-y +=3D ambarella subdir-y +=3D amd subdir-y +=3D amlogic subdir-y +=3D apm diff --git a/arch/arm64/boot/dts/ambarella/Makefile b/arch/arm64/boot/dts/a= mbarella/Makefile new file mode 100644 index 000000000000..ddca3d7b18cc --- /dev/null +++ b/arch/arm64/boot/dts/ambarella/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +dtb-$(CONFIG_ARCH_AMBARELLA) +=3D cv75-evk.dtb diff --git a/arch/arm64/boot/dts/ambarella/cv75-evk.dts b/arch/arm64/boot/d= ts/ambarella/cv75-evk.dts new file mode 100644 index 000000000000..42a0fe24b83b --- /dev/null +++ b/arch/arm64/boot/dts/ambarella/cv75-evk.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Ambarella CV75 EVK board + */ + +/dts-v1/; + +#include "cv75.dtsi" + +/ { + model =3D "Ambarella CV75 EVK Board"; + compatible =3D "ambarella,cv75-evk", "ambarella,cv75"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D &uart0; + }; + + memory@200000 { + device_type =3D "memory"; + reg =3D <0x0 0x00200000 0x0 0x07e00000>; + }; +}; + +&uart0 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/ambarella/cv75.dtsi b/arch/arm64/boot/dts/= ambarella/cv75.dtsi new file mode 100644 index 000000000000..c36b6af48237 --- /dev/null +++ b/arch/arm64/boot/dts/ambarella/cv75.dtsi @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Ambarella CV75 SoC + * + * Boot peripheral: UART0 console. + * Clocks: a single ambarella,cv75-rct provider. + */ + +#include +#include + +/ { + compatible =3D "ambarella,cv75"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + compatible =3D "arm,cortex-a76"; + device_type =3D "cpu"; + reg =3D <0x000>; + enable-method =3D "psci"; + }; + + cpu@1 { + compatible =3D "arm,cortex-a76"; + device_type =3D "cpu"; + reg =3D <0x100>; + enable-method =3D "psci"; + }; + }; + + osc: oscillator { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "osc"; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + ahb@ffe0000000 { + compatible =3D "simple-bus"; + reg =3D <0xff 0xe0000000 0x0 0x01000000>; + ranges =3D <0xe0000000 0xff 0xe0000000 0x01000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + s_scratchpad_syscon: scratchpad@e002e000 { + compatible =3D "ambarella,cv75-sec-scratchpad", "syscon"; + reg =3D <0xe002e000 0x1000>; + }; + }; + + apb@ffe4000000 { + compatible =3D "simple-bus"; + reg =3D <0xff 0xe4000000 0x0 0x01000000>; + ranges =3D <0xe4000000 0xff 0xe4000000 0x01000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + uart0: serial@e4000000 { + compatible =3D "ambarella,cv75-uart", "snps,dw-apb-uart"; + reg =3D <0xe4000000 0x1000>; + clocks =3D <&rct CV75_GCLK_UART0>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pins>; + + status =3D "disabled"; + }; + + pinctrl: pinctrl@e4010000 { + compatible =3D "ambarella,cv75-pinctrl"; + reg =3D <0xe4010000 0x1000>; + ambarella,drive-strength-syscon =3D <&rct>; + ambarella,pull-syscon =3D <&s_scratchpad_syscon>; + + uart0_pins: uart0-pins { + function =3D "uart0"; + groups =3D "uart0"; + }; + }; + + gpio0: gpio@e4013000 { + compatible =3D "ambarella,cv75-gpio", "arm,primecell"; + reg =3D <0xe4013000 0x1000>; + clocks =3D <&rct CV75_GCLK_APB>; + clock-names =3D "apb_pclk"; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells =3D <2>; + arm,primecell-periphid =3D <0x000e8061>; + }; + + gpio1: gpio@e4014000 { + compatible =3D "ambarella,cv75-gpio", "arm,primecell"; + reg =3D <0xe4014000 0x1000>; + clocks =3D <&rct CV75_GCLK_APB>; + clock-names =3D "apb_pclk"; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells =3D <2>; + arm,primecell-periphid =3D <0x000e8061>; + }; + + gpio2: gpio@e4015000 { + compatible =3D "ambarella,cv75-gpio", "arm,primecell"; + reg =3D <0xe4015000 0x1000>; + clocks =3D <&rct CV75_GCLK_APB>; + clock-names =3D "apb_pclk"; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 64 32>; + interrupt-controller; + #interrupt-cells =3D <2>; + arm,primecell-periphid =3D <0x000e8061>; + }; + }; + + rct: clock-controller@ffed080000 { + compatible =3D "ambarella,cv75-rct", "syscon"; + reg =3D <0xff 0xed080000 0x0 0x1000>; + clocks =3D <&osc>; + clock-names =3D "osc"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + assigned-clocks =3D <&rct CV75_GCLK_UART0>; + assigned-clock-parents =3D <&osc>; + assigned-clock-rates =3D <24000000>; + }; + + gic: interrupt-controller@fff0101000 { + compatible =3D "arm,gic-400"; + reg =3D <0xff 0xf0101000 0x0 0x1000>, + <0xff 0xf0102000 0x0 0x2000>, + <0xff 0xf0104000 0x0 0x2000>, + <0xff 0xf0106000 0x0 0x2000>; + interrupt-controller; + #interrupt-cells =3D <3>; + #address-cells =3D <0>; + interrupts =3D ; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + , + ; + }; +}; diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index ad3bd3d9507b..454f07a6a6a6 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -36,6 +36,7 @@ CONFIG_CRASH_DUMP=3Dy CONFIG_ARCH_ACTIONS=3Dy CONFIG_ARCH_AIROHA=3Dy CONFIG_ARCH_SUNXI=3Dy +CONFIG_ARCH_AMBARELLA=3Dy CONFIG_ARCH_ALPINE=3Dy CONFIG_ARCH_APPLE=3Dy CONFIG_ARCH_ARTPEC=3Dy --=20 2.34.1 From nobody Fri Oct 2 01:56:21 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8F1E4A64F4; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-cv75-v5-v9-15-486cc289a4b8@ambarella.com> References: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> In-Reply-To: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Michael Walle , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790858457; l=1241; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=66/FpPmSuU75AtQewU8cj7mu+Qa/5qamx4Km8ySoeYo=; b=UQEl4EIWvylxjuSUeW+DDd+fd5g+2eGGqIKwhHMf9YI70cTL6LbHVpa5wqSiKPNpe6eKu2mWu eHXXcsemHpjA4uicqb+wmHcy8JyKaRCF4Qi4Uzwzc1fUxslGyxbvNAm X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Add a maintainer entry covering Ambarella CV75 bindings, DTS and related drivers. Reviewed-by: Linus Walleij Signed-off-by: Long Zhao --- MAINTAINERS | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 803b60ad628f..59e5b32d7a02 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2502,6 +2502,20 @@ F: drivers/clocksource/asm9260_timer.c F: drivers/rtc/rtc-asm9260.c F: drivers/watchdog/asm9260_wdt.c =20 +ARM/AMBARELLA SOC SUPPORT +M: Long Zhao +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: devicetree@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/arm/ambarella.yaml +F: Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yaml +F: Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml +F: arch/arm64/boot/dts/ambarella/ +F: drivers/clk/ambarella/ +F: drivers/pinctrl/pinctrl-ambarella* +F: include/dt-bindings/clock/ambarella,cv75-rct.h +N: ambarella + ARM/AMD PENSANDO ARM64 ARCHITECTURE M: Brad Larson L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) --=20 2.34.1