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charset="utf-8" auxiliary_device_init() returns an error before device_initialize() is called, so the release callback never runs on this path and the rdev allocated in jh7110_reset_controller_register() is leaked. Free rdev when auxiliary_device_init() fails. Fixes: edab7204afe5 ("clk: starfive: Add StarFive JH7110 system clock drive= r") Signed-off-by: Changhuang Liang --- drivers/clk/starfive/clk-starfive-jh7110-sys.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/s= tarfive/clk-starfive-jh7110-sys.c index 847c0a39e5ab..1d460a03f936 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c @@ -360,8 +360,10 @@ int jh7110_reset_controller_register(struct jh71x0_clk= _priv *priv, adev->id =3D adev_id; =20 ret =3D auxiliary_device_init(adev); - if (ret) + if (ret) { + kfree(rdev); return ret; + } =20 ret =3D auxiliary_device_add(adev); if (ret) { --=20 2.25.1 From nobody Wed Sep 30 16:18:44 2026 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2092.outbound.protection.partner.outlook.cn [139.219.146.92]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 406E34DAFA4; Wed, 30 Sep 2026 12:43:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=139.219.146.92 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790772233; cv=fail; b=dARZiE2EOBuNeyx6mkUTmhhUkCFnBCgqzSkZmRyqdS8466RMsJXsYfOSydJBNdQWG2SVgpynL2KpOd4T163X8Slt/2waltwed6y0H5QPUQLXrYWnEgw031UaUxtWMCi9hd5Ne9aPzkZHTysC5f4tZMBfvPZQhkbuoVDD+E2lgus= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790772233; c=relaxed/simple; bh=wjMsCJVW98TN4PBUv6MiH3veqXqkOcyObH8bVCHFZqA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=rJqjFpevE2dtB1WryjfqoR7Y30/b432+NC0dLdXQVqBb7VGjfrLhTJX5sojORwXRfaz0aBCH8cUDwpR+MsKJHUMZSMe2a8wg4zdvXMj53fuMJVvd8gEApQ0nAdtCX/BtFqlVqIH0dVtVobCVtIISGDiknfsBTScc8KGgFqKTg50= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=starfivetech.com; spf=pass smtp.mailfrom=starfivetech.com; arc=fail smtp.client-ip=139.219.146.92 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=dCZYRr53hZOy5RIENjE+zKvcgD1PbDm6EmzgwnKYnNUg0EQEiSKCJgV8PLIiWHxbsw1OqgYnw3MDgGDhFOnY0RDRD/caHQDu5MKaQiO3yGOhgqBAjE/0nQ5mv4M4lfwsHjC2m0ZB4okai+H3sViunIylg5NgsXCxvB0wKLKRrmFE0cjzD9JyNufg9DfmzqdwMrMNJE4Bn/q4uQIWX0m3hWFMwJ1OJHqdA12+YWjt6u1PLZQFeYptYwc8UAfHp27S+v7+Wt5+ByBbif7x36sfzbUTreaRwNGvHq89bUcR6vc6J45QJD3cyuBTgs2l+JOgrykcKrDidD3xpFB9xwRfzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=vxN378Fl91XwyIRxcPY3l9M7RWfQNVX8cDr5JYi4Mp8=; b=WRBYLEi5n/LEOHS/fbNwssVzc8ifAdsQ1eF2sdRGg4s8Gi5Ft7TmAv9trQw1cePfHl7epNqt7mvzj18l9hp61mAa8S2Po67eSbRYUmkBi4diWS7IfAOx9XbktK0WTs/2B8xT6KBCwrt47hL5pzKEU55KfEHGDh5eTXsp7bkk9Lh2c5aHAcZFXbffLGMbj8+/pwL9104XPkQml05hnBwinQBkSchY0lze/dtgI3UP97LnfRZMWHYoXU9h6u3VWrIOii09LGgbnJh1bUFKTQYwObrqCKDhJv04YreTTcrihN5zlxw+ARstHS4xNb7P0o+ii5CR1IvLXjhrcpeVpzQAXg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) by ZQ4PR01MB1297.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:13::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.16; Wed, 30 Sep 2026 12:43:35 +0000 Received: from ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn ([fe80::e7d4:256c:b066:850d]) by ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn ([fe80::e7d4:256c:b066:850d%4]) with mapi id 15.21.0451.026; Wed, 30 Sep 2026 12:43:35 +0000 From: Changhuang Liang To: Michael Turquette , Brian Masney , Jerome Brunet , Stephen Boyd , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Emil Renner Berthing , Kees Cook , "Gustavo A . R . Silva" , Richard Cochran Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-hardening@vger.kernel.org, netdev@vger.kernel.org, Hal Feng , Changhuang Liang Subject: [PATCH v5 02/23] clk: starfive: JH71x0: Move reset controller registration to jh71x0 common code Date: Wed, 30 Sep 2026 05:42:56 -0700 Message-Id: <20260930124317.5648-3-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260930124317.5648-1-changhuang.liang@starfivetech.com> References: <20260930124317.5648-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BJSPR01CA0006.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:c::18) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1297:EE_ X-MS-Office365-Filtering-Correlation-Id: 67f02ef9-288a-4bfc-b36c-08df1ef07131 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|23010399003|376014|7416014|52116014|10067099003|56012099006|22082099003|18002099003|921020|38350700014; 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charset="utf-8" jh7110_reset_controller_register() is only tied to the JH7110 system clock driver by its location. Its logic is generic: allocate a struct jh71x0_reset_adev, point it at the CRG register base and add it as an auxiliary device for the reset driver to bind to. Move it to clk-starfive-jh71x0.c as jh71x0_reset_controller_register() so that the clock drivers of other StarFive SoCs can reuse it, and make CLK_STARFIVE_JH71X0 select AUXILIARY_BUS accordingly. The auxiliary device ID is dropped: every CRG already uses a distinct auxiliary device name, so the ID is not needed to keep the device names unique, and it is always 0 now. Signed-off-by: Changhuang Liang --- drivers/clk/starfive/Kconfig | 2 +- .../clk/starfive/clk-starfive-jh7110-aon.c | 2 +- .../clk/starfive/clk-starfive-jh7110-isp.c | 2 +- .../clk/starfive/clk-starfive-jh7110-stg.c | 2 +- .../clk/starfive/clk-starfive-jh7110-sys.c | 59 +------------------ .../clk/starfive/clk-starfive-jh7110-vout.c | 2 +- drivers/clk/starfive/clk-starfive-jh7110.h | 4 -- drivers/clk/starfive/clk-starfive-jh71x0.c | 54 +++++++++++++++++ drivers/clk/starfive/clk-starfive-jh71x0.h | 2 + 9 files changed, 62 insertions(+), 67 deletions(-) diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index bd29358ffeec..51716655554f 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -2,6 +2,7 @@ =20 config CLK_STARFIVE_JH71X0 bool + select AUXILIARY_BUS =20 config CLK_STARFIVE_JH7100 bool "StarFive JH7100 clock support" @@ -32,7 +33,6 @@ config CLK_STARFIVE_JH7110_PLL config CLK_STARFIVE_JH7110_SYS bool "StarFive JH7110 system clock support" depends on ARCH_STARFIVE || COMPILE_TEST - select AUXILIARY_BUS select CLK_STARFIVE_JH71X0 select RESET_STARFIVE_JH7110 if RESET_CONTROLLER select CLK_STARFIVE_JH7110_PLL diff --git a/drivers/clk/starfive/clk-starfive-jh7110-aon.c b/drivers/clk/s= tarfive/clk-starfive-jh7110-aon.c index 6f67587f4335..66f1c56a7169 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-aon.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-aon.c @@ -121,7 +121,7 @@ static int jh7110_aoncrg_probe(struct platform_device *= pdev) if (ret) return ret; =20 - return jh7110_reset_controller_register(priv, "rst-aon", 1); + return jh71x0_reset_controller_register(priv, "rst-aon"); } =20 static const struct of_device_id jh7110_aoncrg_match[] =3D { diff --git a/drivers/clk/starfive/clk-starfive-jh7110-isp.c b/drivers/clk/s= tarfive/clk-starfive-jh7110-isp.c index c02c8b29a123..f8222d3c81ee 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-isp.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-isp.c @@ -180,7 +180,7 @@ static int jh7110_ispcrg_probe(struct platform_device *= pdev) if (ret) goto err_exit; =20 - ret =3D jh7110_reset_controller_register(priv, "rst-isp", 3); + ret =3D jh71x0_reset_controller_register(priv, "rst-isp"); if (ret) goto err_exit; =20 diff --git a/drivers/clk/starfive/clk-starfive-jh7110-stg.c b/drivers/clk/s= tarfive/clk-starfive-jh7110-stg.c index 2a5ad0e07d1d..5ae63e18aa4f 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-stg.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-stg.c @@ -139,7 +139,7 @@ static int jh7110_stgcrg_probe(struct platform_device *= pdev) if (ret) return ret; =20 - return jh7110_reset_controller_register(priv, "rst-stg", 2); + return jh71x0_reset_controller_register(priv, "rst-stg"); } =20 static const struct of_device_id jh7110_stgcrg_match[] =3D { diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/s= tarfive/clk-starfive-jh7110-sys.c index 1d460a03f936..6c5e9c54dfcd 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c @@ -6,15 +6,11 @@ * Copyright (C) 2022 StarFive Technology Co., Ltd. */ =20 -#include #include #include #include #include #include -#include - -#include =20 #include =20 @@ -323,59 +319,6 @@ static const struct jh71x0_clk_data jh7110_sysclk_data= [] __initconst =3D { JH7110_SYSCLK_OSC), }; =20 -static void jh7110_reset_unregister_adev(void *_adev) -{ - struct auxiliary_device *adev =3D _adev; - - auxiliary_device_delete(adev); - auxiliary_device_uninit(adev); -} - -static void jh7110_reset_adev_release(struct device *dev) -{ - struct auxiliary_device *adev =3D to_auxiliary_dev(dev); - struct jh71x0_reset_adev *rdev =3D to_jh71x0_reset_adev(adev); - - kfree(rdev); -} - -int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, - const char *adev_name, - u32 adev_id) -{ - struct jh71x0_reset_adev *rdev; - struct auxiliary_device *adev; - int ret; - - rdev =3D kzalloc_obj(*rdev); - if (!rdev) - return -ENOMEM; - - rdev->base =3D priv->base; - - adev =3D &rdev->adev; - adev->name =3D adev_name; - adev->dev.parent =3D priv->dev; - adev->dev.release =3D jh7110_reset_adev_release; - adev->id =3D adev_id; - - ret =3D auxiliary_device_init(adev); - if (ret) { - kfree(rdev); - return ret; - } - - ret =3D auxiliary_device_add(adev); - if (ret) { - auxiliary_device_uninit(adev); - return ret; - } - - return devm_add_action_or_reset(priv->dev, - jh7110_reset_unregister_adev, adev); -} -EXPORT_SYMBOL_GPL(jh7110_reset_controller_register); - /* * This clock notifier is called when the rate of PLL0 clock is to be chan= ged. * The cpu_root clock should save the current parent clock and switch its = parent @@ -525,7 +468,7 @@ static int __init jh7110_syscrg_probe(struct platform_d= evice *pdev) if (ret) return ret; =20 - return jh7110_reset_controller_register(priv, "rst-sys", 0); + return jh71x0_reset_controller_register(priv, "rst-sys"); } =20 static const struct of_device_id jh7110_syscrg_match[] =3D { diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/= starfive/clk-starfive-jh7110-vout.c index aeba42cd3c44..14e5b8286671 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-vout.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c @@ -189,7 +189,7 @@ static int jh7110_voutcrg_probe(struct platform_device = *pdev) if (ret) goto err_exit; =20 - ret =3D jh7110_reset_controller_register(priv, "rst-vo", 4); + ret =3D jh71x0_reset_controller_register(priv, "rst-vo"); if (ret) goto err_exit; =20 diff --git a/drivers/clk/starfive/clk-starfive-jh7110.h b/drivers/clk/starf= ive/clk-starfive-jh7110.h index 0659adae4d76..55374ee24d4d 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110.h +++ b/drivers/clk/starfive/clk-starfive-jh7110.h @@ -10,8 +10,4 @@ struct jh7110_top_sysclk { int top_clks_num; }; =20 -int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, - const char *adev_name, - u32 adev_id); - #endif diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starf= ive/clk-starfive-jh71x0.c index 80e9157347eb..2cc71f49ddee 100644 --- a/drivers/clk/starfive/clk-starfive-jh71x0.c +++ b/drivers/clk/starfive/clk-starfive-jh71x0.c @@ -5,10 +5,13 @@ * Copyright (C) 2021-2022 Emil Renner Berthing */ =20 +#include #include #include #include #include +#include +#include =20 #include "clk-starfive-jh71x0.h" =20 @@ -337,3 +340,54 @@ struct clk_hw *jh71x0_clk_get(struct of_phandle_args *= clkspec, void *data) return ERR_PTR(-EINVAL); } EXPORT_SYMBOL_GPL(jh71x0_clk_get); + +static void jh71x0_reset_unregister_adev(void *_adev) +{ + struct auxiliary_device *adev =3D _adev; + + auxiliary_device_delete(adev); + auxiliary_device_uninit(adev); +} + +static void jh71x0_reset_adev_release(struct device *dev) +{ + struct auxiliary_device *adev =3D to_auxiliary_dev(dev); + struct jh71x0_reset_adev *rdev =3D to_jh71x0_reset_adev(adev); + + kfree(rdev); +} + +int jh71x0_reset_controller_register(struct jh71x0_clk_priv *priv, + const char *adev_name) +{ + struct jh71x0_reset_adev *rdev; + struct auxiliary_device *adev; + int ret; + + rdev =3D kzalloc_obj(*rdev); + if (!rdev) + return -ENOMEM; + + rdev->base =3D priv->base; + + adev =3D &rdev->adev; + adev->name =3D adev_name; + adev->dev.parent =3D priv->dev; + adev->dev.release =3D jh71x0_reset_adev_release; + + ret =3D auxiliary_device_init(adev); + if (ret) { + kfree(rdev); + return ret; + } + + ret =3D auxiliary_device_add(adev); + if (ret) { + auxiliary_device_uninit(adev); + return ret; + } + + return devm_add_action_or_reset(priv->dev, + jh71x0_reset_unregister_adev, adev); +} +EXPORT_SYMBOL_GPL(jh71x0_reset_controller_register); diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starf= ive/clk-starfive-jh71x0.h index 9d5dec1d5cd1..322a05157faf 100644 --- a/drivers/clk/starfive/clk-starfive-jh71x0.h +++ b/drivers/clk/starfive/clk-starfive-jh71x0.h @@ -123,5 +123,7 @@ struct jh71x0_clk_priv { =20 const struct clk_ops *starfive_jh71x0_clk_ops(u32 max); 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charset="utf-8" The JH7110 reset driver binds to auxiliary devices created by the StarFive clock driver. As part of moving the reset controller registration helper into clk-starfive-jh71x0.c so that it can be shared by other StarFive SoCs, the auxiliary device names are now prefixed with "clk_starfive_jh71x0" instead of "clk_starfive_jh7110_sys". Update the auxiliary_device_id table accordingly, otherwise the reset driver fails to probe. Signed-off-by: Changhuang Liang --- drivers/reset/starfive/reset-starfive-jh7110.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/reset/starfive/reset-starfive-jh7110.c b/drivers/reset= /starfive/reset-starfive-jh7110.c index 29a43f0f2ad6..c936e61156a2 100644 --- a/drivers/reset/starfive/reset-starfive-jh7110.c +++ b/drivers/reset/starfive/reset-starfive-jh7110.c @@ -69,23 +69,23 @@ static int jh7110_reset_probe(struct auxiliary_device *= adev, =20 static const struct auxiliary_device_id jh7110_reset_ids[] =3D { { - .name =3D "clk_starfive_jh7110_sys.rst-sys", + .name =3D "clk_starfive_jh71x0.rst-sys", .driver_data =3D (kernel_ulong_t)&jh7110_sys_info, }, { - .name =3D "clk_starfive_jh7110_sys.rst-aon", + .name =3D "clk_starfive_jh71x0.rst-aon", .driver_data =3D (kernel_ulong_t)&jh7110_aon_info, }, { - .name =3D "clk_starfive_jh7110_sys.rst-stg", + .name =3D "clk_starfive_jh71x0.rst-stg", .driver_data =3D (kernel_ulong_t)&jh7110_stg_info, }, { - .name =3D "clk_starfive_jh7110_sys.rst-isp", + .name =3D "clk_starfive_jh71x0.rst-isp", .driver_data =3D (kernel_ulong_t)&jh7110_isp_info, }, { - .name =3D "clk_starfive_jh7110_sys.rst-vo", + .name =3D "clk_starfive_jh71x0.rst-vo", .driver_data =3D (kernel_ulong_t)&jh7110_vout_info, }, { /* sentinel */ } --=20 2.25.1 From nobody Wed Sep 30 16:18:44 2026 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2092.outbound.protection.partner.outlook.cn [139.219.146.92]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A767C4DEC19; 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charset="utf-8" The StarFive JHB100 SoC has several clock and reset generators (CRGs) which share the same probe flow: map the registers, register all the clocks described by a table, add the clock provider and register the auxiliary reset device. Add jh71x0_crg_probe() together with struct jh71x0_crg_domain_info so that each CRG driver only needs to provide its clock table, external clock names and reset auxiliary device name. The reset auxiliary device is registered with jh71x0_reset_controller_register(). The clock index space of these CRGs is sparse, so also make jh71x0_clk_get() reject indexes that were never registered when the domain info is available. Signed-off-by: Changhuang Liang --- drivers/clk/starfive/clk-starfive-jh71x0.c | 95 +++++++++++++++++++++- drivers/clk/starfive/clk-starfive-jh71x0.h | 12 +++ 2 files changed, 104 insertions(+), 3 deletions(-) diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starf= ive/clk-starfive-jh71x0.c index 2cc71f49ddee..bb7706ede1a6 100644 --- a/drivers/clk/starfive/clk-starfive-jh71x0.c +++ b/drivers/clk/starfive/clk-starfive-jh71x0.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include =20 @@ -334,10 +335,14 @@ struct clk_hw *jh71x0_clk_get(struct of_phandle_args = *clkspec, void *data) struct jh71x0_clk_priv *priv =3D data; unsigned int idx =3D clkspec->args[0]; =20 - if (idx < priv->num_reg) - return &priv->reg[idx].hw; + if (idx >=3D priv->num_reg) + return ERR_PTR(-EINVAL); =20 - return ERR_PTR(-EINVAL); + /* Index space is sparse: reject holes that were never registered. */ + if (priv->info && !priv->info->clk_data[idx].name) + return ERR_PTR(-ENOENT); + + return &priv->reg[idx].hw; } EXPORT_SYMBOL_GPL(jh71x0_clk_get); =20 @@ -391,3 +396,87 @@ int jh71x0_reset_controller_register(struct jh71x0_clk= _priv *priv, jh71x0_reset_unregister_adev, adev); } EXPORT_SYMBOL_GPL(jh71x0_reset_controller_register); + +int jh71x0_crg_probe(struct platform_device *pdev) +{ + const struct jh71x0_crg_domain_info *info; + struct jh71x0_clk_priv *priv; + unsigned int idx; + int ret; + + info =3D device_get_match_data(&pdev->dev); + if (!info) + return -ENODEV; + + priv =3D devm_kzalloc(&pdev->dev, struct_size(priv, reg, info->num_clk), + GFP_KERNEL); + if (!priv) + return -ENOMEM; + + spin_lock_init(&priv->rmw_lock); + priv->info =3D info; + priv->num_reg =3D info->num_clk; + priv->dev =3D &pdev->dev; + priv->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + if (info->power_domain) { + ret =3D devm_pm_runtime_enable(priv->dev); + if (ret) + return dev_err_probe(priv->dev, ret, + "failed to enable runtime PM\n"); + } + + for (idx =3D 0; idx < info->num_clk; idx++) { + u32 max =3D info->clk_data[idx].max; + struct clk_parent_data parents[4] =3D {}; + struct clk_init_data init =3D { + .name =3D info->clk_data[idx].name, + .ops =3D starfive_jh71x0_clk_ops(max), + .parent_data =3D parents, + .num_parents =3D + ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, + .flags =3D info->clk_data[idx].flags, + }; + struct jh71x0_clk *clk =3D &priv->reg[idx]; + unsigned int i; + + if (!init.name) + continue; + + if (init.num_parents > ARRAY_SIZE(parents)) + return dev_err_probe(priv->dev, -EINVAL, + "clock %s: too many parents (%u > %zu)\n", + init.name, init.num_parents, ARRAY_SIZE(parents)); + + for (i =3D 0; i < init.num_parents; i++) { + unsigned int pidx =3D info->clk_data[idx].parents[i]; + + if (pidx < info->num_clk) { + parents[i].hw =3D &priv->reg[pidx].hw; + } else { + if (pidx - info->num_clk >=3D info->num_ext_clk) + return -EINVAL; + + parents[i].fw_name =3D info->ext_clk[pidx - info->num_clk]; + } + } + + clk->hw.init =3D &init; + clk->idx =3D idx; + clk->max_div =3D max & JH71X0_CLK_DIV_MASK; + + ret =3D devm_clk_hw_register(&pdev->dev, &clk->hw); + if (ret) + return dev_err_probe(priv->dev, ret, "Failed to register clock %s\n", + init.name); + } + + ret =3D devm_of_clk_add_hw_provider(&pdev->dev, jh71x0_clk_get, priv); + if (ret) + return ret; + + return jh71x0_reset_controller_register(priv, info->rst_name); +} +EXPORT_SYMBOL_GPL(jh71x0_crg_probe); diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starf= ive/clk-starfive-jh71x0.h index 322a05157faf..2a1f0fb4cbb1 100644 --- a/drivers/clk/starfive/clk-starfive-jh71x0.h +++ b/drivers/clk/starfive/clk-starfive-jh71x0.h @@ -5,6 +5,7 @@ #include #include #include +#include #include =20 /* register fields */ @@ -109,6 +110,15 @@ struct jh71x0_clk { unsigned int max_div; }; =20 +struct jh71x0_crg_domain_info { + const struct jh71x0_clk_data *clk_data; + unsigned int num_clk; + const char * const *ext_clk; + unsigned int num_ext_clk; + const char *rst_name; + bool power_domain; +}; + struct jh71x0_clk_priv { /* protect clk enable and set rate/parent from happening at the same time= */ spinlock_t rmw_lock; @@ -116,6 +126,7 @@ struct jh71x0_clk_priv { void __iomem *base; struct clk *original_clk; struct notifier_block pll_clk_nb; + const struct jh71x0_crg_domain_info *info; struct clk_hw *pll[3]; unsigned int num_reg; struct jh71x0_clk reg[] __counted_by(num_reg); @@ -125,5 +136,6 @@ const struct clk_ops *starfive_jh71x0_clk_ops(u32 max); struct clk_hw *jh71x0_clk_get(struct of_phandle_args *clkspec, void *data); int jh71x0_reset_controller_register(struct jh71x0_clk_priv *priv, const char *adev_name); +int jh71x0_crg_probe(struct platform_device *pdev); =20 #endif --=20 2.25.1 From nobody Wed Sep 30 16:18:44 2026 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2092.outbound.protection.partner.outlook.cn [139.219.146.92]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 768FE27F4F5; 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R . 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charset="utf-8" Add bindings for the System-0 clocks and reset generator (SYS0CRG) on JHB100 SoC. Signed-off-by: Changhuang Liang Reviewed-by: Rob Herring (Arm) --- .../clock/starfive,jhb100-sys0crg.yaml | 63 +++++++++++++++++++ .../dt-bindings/clock/starfive,jhb100-crg.h | 56 +++++++++++++++++ .../dt-bindings/reset/starfive,jhb100-crg.h | 28 +++++++++ 3 files changed, 147 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100= -sys0crg.yaml create mode 100644 include/dt-bindings/clock/starfive,jhb100-crg.h create mode 100644 include/dt-bindings/reset/starfive,jhb100-crg.h diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-sys0cr= g.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys0crg.ya= ml new file mode 100644 index 000000000000..cf1b0175b158 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys0crg.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jhb100-sys0crg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 System-0 Clock and Reset Generator + +maintainers: + - Changhuang Liang + +properties: + compatible: + const: starfive,jhb100-sys0crg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (25 MHz) + - description: PLL0 + - description: PLL1 + - description: PLL2 + + clock-names: + items: + - const: osc + - const: pll0 + - const: pll1 + - const: pll2 + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@13000000 { + compatible =3D "starfive,jhb100-sys0crg"; + reg =3D <0x13000000 0x4000>; + clocks =3D <&osc>, <&pll0>, <&pll1>, + <&syspll 0>; + clock-names =3D "osc", "pll0", "pll1", "pll2"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-b= indings/clock/starfive,jhb100-crg.h new file mode 100644 index 000000000000..24ef2663f05a --- /dev/null +++ b/include/dt-bindings/clock/starfive,jhb100-crg.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * Author: Changhuang Liang + * + */ + +#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ +#define __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ + +/* SYS0CRG clocks */ +#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_MAIN 17 +#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_CFG 18 + +#define JHB100_SYS0CLK_PCIE_REF_CML 20 +#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_DATA_INIT 21 +#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_CFG_INIT 22 +#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_TARG 23 + +#define JHB100_SYS0CLK_BMCPCIERP_PCU 26 +#define JHB100_SYS0CLK_HOSTSS0_NCNOC_CFG 27 +#define JHB100_SYS0CLK_HOSTSS0_NCNOC_DATA 28 +#define JHB100_SYS0CLK_HOSTSS0_PHY_SCAN_400 29 +#define JHB100_SYS0CLK_GPIO_ESPI0_EXT 30 + +#define JHB100_SYS0CLK_BMCUSB_NCNOC_INIT 34 +#define JHB100_SYS0CLK_BMCUSB_NCNOC_TARG 35 +#define JHB100_SYS0CLK_BMCUSB_SCANCLK 36 +#define JHB100_SYS0CLK_BMCUSB_480M_SCANCLK 37 + +#define JHB100_SYS0CLK_VCE_NCNOC_INIT 50 +#define JHB100_SYS0CLK_VCE_NCNOC_TARG 51 +#define JHB100_SYS0CLK_BMCPER2_NCNOC_INIT 52 +#define JHB100_SYS0CLK_BMCPER2_NCNOC_TARG 53 +#define JHB100_SYS0CLK_BMCPER2_CFG_400 54 +#define JHB100_SYS0CLK_BMCPER2_CFG_125 55 + +#define JHB100_SYS0CLK_HOSTSS1_NCNOC_DATA 58 +#define JHB100_SYS0CLK_HOSTSS1_PHY_SCAN_400 59 +#define JHB100_SYS0CLK_HOSTSS1_PHY_SCAN_400_ICG_BUF 60 +#define JHB100_SYS0CLK_NPU_NCNOC_INIT 61 +#define JHB100_SYS0CLK_VOUT_NCNOC_INIT 62 +#define JHB100_SYS0CLK_VOUT_AUX 63 + +#define JHB100_SYS0CLK_BMCPER3_NCNOC_INIT 65 +#define JHB100_SYS0CLK_HOSTUSB_NCNOC_INIT 66 +#define JHB100_SYS0CLK_HOSTUSBCMN_CFG_480 67 +#define JHB100_SYS0CLK_BMCPER1_NCNOC_INIT 68 +#define JHB100_SYS0CLK_BMCPER1_CFG_800 69 +#define JHB100_SYS0CLK_BMCPER0_NCNOC_INIT 70 +#define JHB100_SYS0CLK_BMCPER0_CFG_400 71 +#define JHB100_SYS0CLK_BMCPER0_CFG_800 72 +#define JHB100_SYS0CLK_GPU0_NCNOC_INIT 73 +#define JHB100_SYS0CLK_GPU1_NCNOC_INIT 74 + +#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-b= indings/reset/starfive,jhb100-crg.h new file mode 100644 index 000000000000..5c7b00afda73 --- /dev/null +++ b/include/dt-bindings/reset/starfive,jhb100-crg.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * Author: Changhuang Liang + * + */ + +#ifndef __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ +#define __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ + +/* SYS0CRG resets */ +#define JHB100_SYS0RST_RESOURCE_ARB 0 +#define JHB100_SYS0RST_SYS0_IOMUX_PRESETN 1 +#define JHB100_SYS0RST_SYS0H_IOMUX_PRESETN 2 +#define JHB100_SYS0RST_RST_ADAPTOR_TIMEOUT_RSTN 3 +#define JHB100_SYS0RST_BMCPCIERP_RSTN_BUS 4 +#define JHB100_SYS0RST_BMCPCIERP_RSTN_CRG 5 +#define JHB100_SYS0RST_HOSTSS0_RSTN_BUS_ESPI 6 +#define JHB100_SYS0RST_HOSTSS0_RSTN_BUS_PCIE 7 +#define JHB100_SYS0RST_HOSTSS0_RSTN_CRG 8 +#define JHB100_SYS0RST_BMCPERIPH2_RSTN_CRG 9 +#define JHB100_SYS0RST_BMCPERIPH2_RSTN_BUS 10 +#define JHB100_SYS0RST_VCE_RSTN_CRG 11 +#define JHB100_SYS0RST_VCE_RSTN_BUS 12 +#define JHB100_SYS0RST_BMCUSB_RSTN_BUS 13 +#define JHB100_SYS0RST_BMCUSB_RSTN_CRG 14 + +#endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */ --=20 2.25.1 From nobody Wed Sep 30 16:18:44 2026 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2092.outbound.protection.partner.outlook.cn [139.219.146.92]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C8F94E0B75; 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R . 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charset="utf-8" Add support for JHB100 System-0 clock generator (SYS0CRG). Signed-off-by: Changhuang Liang --- MAINTAINERS | 7 + drivers/clk/starfive/Kconfig | 10 ++ drivers/clk/starfive/Makefile | 2 + .../clk/starfive/clk-starfive-jhb100-sys0.c | 150 ++++++++++++++++++ 4 files changed, 169 insertions(+) create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys0.c diff --git a/MAINTAINERS b/MAINTAINERS index c9f542965ec5..d22078bcf488 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -26217,6 +26217,13 @@ F: Documentation/devicetree/bindings/phy/starfive,= jh7110-usb-phy.yaml F: drivers/phy/starfive/phy-jh7110-pcie.c F: drivers/phy/starfive/phy-jh7110-usb.c =20 +STARFIVE JHB100 CLOCK DRIVERS +M: Changhuang Liang +S: Supported +F: Documentation/devicetree/bindings/clock/starfive,jhb1*.yaml +F: drivers/clk/starfive/clk-starfive-jhb1* +F: include/dt-bindings/clock/starfive,jhb1*.h + STARFIVE JHB100 DEVICETREES M: Changhuang Liang L: linux-riscv@lists.infradead.org diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index 51716655554f..cd5b7754403e 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -72,3 +72,13 @@ config CLK_STARFIVE_JH7110_VOUT help Say yes here to support the Video-Output clock controller on the StarFive JH7110 SoC. + +config CLK_STARFIVE_JHB100_SYS0 + bool "StarFive JHB100 system-0 clock support" + depends on ARCH_STARFIVE || COMPILE_TEST + select CLK_STARFIVE_JH71X0 + select RESET_STARFIVE_JHB100 if RESET_CONTROLLER + default ARCH_STARFIVE + help + Say yes here to support the system-0 clock controller on the + StarFive JHB100 SoC. diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index 199ac0f37a2f..d2ba83d7d02c 100644 --- a/drivers/clk/starfive/Makefile +++ b/drivers/clk/starfive/Makefile @@ -10,3 +10,5 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) +=3D clk-starfive-j= h7110-aon.o obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) +=3D clk-starfive-jh7110-stg.o obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) +=3D clk-starfive-jh7110-isp.o obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) +=3D clk-starfive-jh7110-vout.o + +obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) +=3D clk-starfive-jhb100-sys0.o diff --git a/drivers/clk/starfive/clk-starfive-jhb100-sys0.c b/drivers/clk/= starfive/clk-starfive-jhb100-sys0.c new file mode 100644 index 000000000000..498afb787311 --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jhb100-sys0.c @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JHB100 System-0 Clock Driver + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * + * Author: Changhuang Liang + * + */ + +#include +#include +#include + +#include "clk-starfive-jh71x0.h" + +#define JHB100_SYS0CLK_NUM_CLKS (JHB100_SYS0CLK_GPU1_NCNOC_INIT + 1) + +/* external clocks */ +#define JHB100_SYS0CLK_OSC (JHB100_SYS0CLK_NUM_CLKS + 0) +#define JHB100_SYS0CLK_PLL0 (JHB100_SYS0CLK_NUM_CLKS + 1) +#define JHB100_SYS0CLK_PLL1 (JHB100_SYS0CLK_NUM_CLKS + 2) +#define JHB100_SYS0CLK_PLL2 (JHB100_SYS0CLK_NUM_CLKS + 3) + +static const char * const jhb100_sys0_ext_clk[] =3D { + "osc", + "pll0", + "pll1", + "pll2", +}; + +static const struct jh71x0_clk_data jhb100_sys0crg_clk_data[] =3D { + /* bmcpcierp */ + JH71X0__DIV(JHB100_SYS0CLK_BMCPCIERP_NCNOC_MAIN, "bmcpcierp_ncnoc_main", = 6, + JHB100_SYS0CLK_PLL0), + JH71X0__DIV(JHB100_SYS0CLK_BMCPCIERP_NCNOC_CFG, "bmcpcierp_ncnoc_cfg", 12, + JHB100_SYS0CLK_PLL1), + JH71X0__DIV(JHB100_SYS0CLK_PCIE_REF_CML, "pcie_ref_cml", 24, + JHB100_SYS0CLK_PLL0), + JH71X0_GATE(JHB100_SYS0CLK_BMCPCIERP_NCNOC_DATA_INIT, "bmcpcierp_ncnoc_da= ta_init", + CLK_IS_CRITICAL, JHB100_SYS0CLK_BMCPCIERP_NCNOC_MAIN), + JH71X0_GATE(JHB100_SYS0CLK_BMCPCIERP_NCNOC_CFG_INIT, "bmcpcierp_ncnoc_cfg= _init", + CLK_IS_CRITICAL, JHB100_SYS0CLK_BMCPCIERP_NCNOC_CFG), + JH71X0_GATE(JHB100_SYS0CLK_BMCPCIERP_NCNOC_TARG, "bmcpcierp_ncnoc_targ", + CLK_IS_CRITICAL, JHB100_SYS0CLK_BMCPCIERP_NCNOC_MAIN), + JH71X0_GATE(JHB100_SYS0CLK_BMCPCIERP_PCU, "bmcpcierp_pcu", + CLK_IS_CRITICAL, JHB100_SYS0CLK_OSC), + /* hostss0 */ + JH71X0__DIV(JHB100_SYS0CLK_HOSTSS0_NCNOC_CFG, "hostss0_ncnoc_cfg", 12, + JHB100_SYS0CLK_PLL1), + JH71X0__DIV(JHB100_SYS0CLK_HOSTSS0_NCNOC_DATA, "hostss0_ncnoc_data", 6, + JHB100_SYS0CLK_PLL0), + JH71X0__DIV(JHB100_SYS0CLK_HOSTSS0_PHY_SCAN_400, "hostss0_phy_scan_400", = 6, + JHB100_SYS0CLK_PLL0), + JH71X0__DIV(JHB100_SYS0CLK_GPIO_ESPI0_EXT, "gpio_espi0_ext", 14, + JHB100_SYS0CLK_PLL2), + /* bmcusb */ + JH71X0__DIV(JHB100_SYS0CLK_BMCUSB_NCNOC_INIT, "bmcusb_ncnoc_init", 6, + JHB100_SYS0CLK_PLL0), + JH71X0__DIV(JHB100_SYS0CLK_BMCUSB_NCNOC_TARG, "bmcusb_ncnoc_targ", 6, + JHB100_SYS0CLK_PLL1), + JH71X0__DIV(JHB100_SYS0CLK_BMCUSB_SCANCLK, "bmcusb_scanclk", 5, + JHB100_SYS0CLK_PLL0), + JH71X0_GATE(JHB100_SYS0CLK_BMCUSB_480M_SCANCLK, "bmcusb_480m_scanclk", + CLK_IS_CRITICAL, JHB100_SYS0CLK_BMCUSB_SCANCLK), + /* vce */ + JH71X0__DIV(JHB100_SYS0CLK_VCE_NCNOC_INIT, "vce_ncnoc_init", 10, + JHB100_SYS0CLK_PLL0), + JH71X0__DIV(JHB100_SYS0CLK_VCE_NCNOC_TARG, "vce_ncnoc_targ", 12, + JHB100_SYS0CLK_PLL1), + /* bmcperiph2 */ + JH71X0__DIV(JHB100_SYS0CLK_BMCPER2_NCNOC_INIT, "bmcper2_ncnoc_init", 6, + JHB100_SYS0CLK_PLL0), + JH71X0__DIV(JHB100_SYS0CLK_BMCPER2_NCNOC_TARG, "bmcper2_ncnoc_targ", 12, + JHB100_SYS0CLK_PLL1), + JH71X0__DIV(JHB100_SYS0CLK_BMCPER2_CFG_400, "bmcper2_cfg_400", 8, + JHB100_SYS0CLK_PLL0), + JH71X0__DIV(JHB100_SYS0CLK_BMCPER2_CFG_125, "bmcper2_cfg_125", 10, + JHB100_SYS0CLK_PLL1), + /* hostss1 */ + JH71X0__DIV(JHB100_SYS0CLK_HOSTSS1_NCNOC_DATA, "hostss1_ncnoc_data", 6, + JHB100_SYS0CLK_PLL0), + JH71X0__DIV(JHB100_SYS0CLK_HOSTSS1_PHY_SCAN_400, "hostss1_phy_scan_400", = 6, + JHB100_SYS0CLK_PLL0), + JH71X0_GATE(JHB100_SYS0CLK_HOSTSS1_PHY_SCAN_400_ICG_BUF, + "hostss1_phy_scan_400_icg_buf", CLK_IS_CRITICAL, + JHB100_SYS0CLK_HOSTSS1_PHY_SCAN_400), + /* npu */ + JH71X0__DIV(JHB100_SYS0CLK_NPU_NCNOC_INIT, "npu_ncnoc_init", 6, + JHB100_SYS0CLK_PLL0), + /* vout */ + JH71X0__DIV(JHB100_SYS0CLK_VOUT_NCNOC_INIT, "vout_ncnoc_init", 6, + JHB100_SYS0CLK_PLL0), + JH71X0__DIV(JHB100_SYS0CLK_VOUT_AUX, "vout_aux", 150, + JHB100_SYS0CLK_PLL0), + /* bmcperiph3 */ + JH71X0__DIV(JHB100_SYS0CLK_BMCPER3_NCNOC_INIT, "bmcper3_ncnoc_init", 6, + JHB100_SYS0CLK_PLL0), + /* hostusb */ + JH71X0__DIV(JHB100_SYS0CLK_HOSTUSB_NCNOC_INIT, "hostusb_ncnoc_init", 6, + JHB100_SYS0CLK_PLL0), + /* hostusbcmn */ + JH71X0__DIV(JHB100_SYS0CLK_HOSTUSBCMN_CFG_480, "hostusbcmn_cfg_480", 5, + JHB100_SYS0CLK_PLL0), + /* bmcperiph1 */ + JH71X0__DIV(JHB100_SYS0CLK_BMCPER1_NCNOC_INIT, "bmcper1_ncnoc_init", 6, + JHB100_SYS0CLK_PLL0), + JH71X0__DIV(JHB100_SYS0CLK_BMCPER1_CFG_800, "bmcper1_cfg_800", 4, + JHB100_SYS0CLK_PLL0), + /* bmcperiph0 */ + JH71X0__DIV(JHB100_SYS0CLK_BMCPER0_NCNOC_INIT, "bmcper0_ncnoc_init", 6, + JHB100_SYS0CLK_PLL0), + JH71X0__DIV(JHB100_SYS0CLK_BMCPER0_CFG_400, "bmcper0_cfg_400", 8, + JHB100_SYS0CLK_PLL0), + JH71X0__DIV(JHB100_SYS0CLK_BMCPER0_CFG_800, "bmcper0_cfg_800", 8, + JHB100_SYS0CLK_PLL0), + /* gpu0 */ + JH71X0__DIV(JHB100_SYS0CLK_GPU0_NCNOC_INIT, "gpu0_ncnoc_init", 10, + JHB100_SYS0CLK_PLL0), + /* gpu1 */ + JH71X0__DIV(JHB100_SYS0CLK_GPU1_NCNOC_INIT, "gpu1_ncnoc_init", 10, + JHB100_SYS0CLK_PLL0), +}; + +static const struct jh71x0_crg_domain_info jhb100_sys0crg_info =3D { + .clk_data =3D jhb100_sys0crg_clk_data, + .num_clk =3D ARRAY_SIZE(jhb100_sys0crg_clk_data), + .ext_clk =3D jhb100_sys0_ext_clk, + .num_ext_clk =3D ARRAY_SIZE(jhb100_sys0_ext_clk), + .rst_name =3D "jhb100-r-sys0", + .power_domain =3D false, +}; + +static const struct of_device_id jhb100_sys0crg_match[] =3D { + { + .compatible =3D "starfive,jhb100-sys0crg", + .data =3D &jhb100_sys0crg_info, + }, + { /* sentinel */ } +}; + +static struct platform_driver jhb100_sys0crg_driver =3D { + .probe =3D jh71x0_crg_probe, + .driver =3D { + .name =3D "clk-starfive-jhb100-sys0", + .of_match_table =3D jhb100_sys0crg_match, + .suppress_bind_attrs =3D true, + }, +}; +builtin_platform_driver(jhb100_sys0crg_driver); --=20 2.25.1 From nobody Wed Sep 30 16:18:44 2026 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2129.outbound.protection.partner.outlook.cn [139.219.146.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 303194848AB; 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charset="utf-8" Add bindings for the System-1 clocks and reset generator (SYS1CRG) on JHB100 SoC. Signed-off-by: Changhuang Liang Reviewed-by: Rob Herring (Arm) --- .../clock/starfive,jhb100-sys1crg.yaml | 71 +++++++++++++++++++ .../dt-bindings/clock/starfive,jhb100-crg.h | 20 ++++++ .../dt-bindings/reset/starfive,jhb100-crg.h | 11 +++ 3 files changed, 102 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100= -sys1crg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-sys1cr= g.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys1crg.ya= ml new file mode 100644 index 000000000000..70cbfa38c100 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys1crg.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jhb100-sys1crg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 System-1 Clock and Reset Generator + +maintainers: + - Changhuang Liang + +properties: + compatible: + const: starfive,jhb100-sys1crg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (25 MHz) + - description: PLL0 + - description: PLL1 + - description: PLL2 + - description: PLL4 + - description: PLL5 + - description: NPU Non Coherent NOC Initiator + + clock-names: + items: + - const: osc + - const: pll0 + - const: pll1 + - const: pll2 + - const: pll4 + - const: pll5 + - const: npu_ncnoc_init + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@13004000 { + compatible =3D "starfive,jhb100-sys1crg"; + reg =3D <0x13004000 0x4000>; + clocks =3D <&osc>, <&pll0>, <&pll1>, + <&syspll 0>, <&syspll 2>, + <&syspll 3>, <&sys0crg 61>; + clock-names =3D "osc", "pll0", "pll1", "pll2", + "pll4", "pll5", "npu_ncnoc_init"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-b= indings/clock/starfive,jhb100-crg.h index 24ef2663f05a..d7904b32bd51 100644 --- a/include/dt-bindings/clock/starfive,jhb100-crg.h +++ b/include/dt-bindings/clock/starfive,jhb100-crg.h @@ -53,4 +53,24 @@ #define JHB100_SYS0CLK_GPU0_NCNOC_INIT 73 #define JHB100_SYS0CLK_GPU1_NCNOC_INIT 74 =20 +/* SYS1CRG clocks */ +#define JHB100_SYS1CLK_APB_MAIN_SYS1 0 +#define JHB100_SYS1CLK_APB_SENSOR_ICG_BUF 1 + +#define JHB100_SYS1CLK_GPIO_ESPI1_EXT 5 + +#define JHB100_SYS1CLK_HOSTSS1_NCNOC_CFG 7 +#define JHB100_SYS1CLK_HOSTSS1_PHY_SCAN_1000_ICG_BUF 8 +#define JHB100_SYS1CLK_NPU_NCNOC_CFG 9 +#define JHB100_SYS1CLK_NPU_CORE_DIV 10 +#define JHB100_SYS1CLK_DOM_NPU_CORE_CLK 11 +#define JHB100_SYS1CLK_DOM_NPU_BUS_CLK 12 +#define JHB100_SYS1CLK_DOM_NPU_INIT_CLK 13 +#define JHB100_SYS1CLK_DOM_NPU_OSC_CLK 14 +#define JHB100_SYS1CLK_VOUT_NCNOC_TARG 15 +#define JHB100_SYS1CLK_VOUT_PIX0 16 +#define JHB100_SYS1CLK_VOUT_PIX1 17 +#define JHB100_SYS1CLK_BMCPER3_NCNOC_TARG 18 +#define JHB100_SYS1CLK_BMCPER3_CFG_125 19 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-b= indings/reset/starfive,jhb100-crg.h index 5c7b00afda73..da1b51621172 100644 --- a/include/dt-bindings/reset/starfive,jhb100-crg.h +++ b/include/dt-bindings/reset/starfive,jhb100-crg.h @@ -25,4 +25,15 @@ #define JHB100_SYS0RST_BMCUSB_RSTN_BUS 13 #define JHB100_SYS0RST_BMCUSB_RSTN_CRG 14 =20 +/* SYS1CRG resets */ +#define JHB100_SYS1RST_SYS1_IOMUX_PRESETN 0 +#define JHB100_SYS1RST_MAIN_RSTN_CHIPTOP_SENSOR 1 +#define JHB100_SYS1RST_VOUT_RSTN_HOST0 2 +#define JHB100_SYS1RST_VOUT_RSTN_HOST1 3 +#define JHB100_SYS1RST_HOSTSS1_RSTN_BUS_ESPI 4 +#define JHB100_SYS1RST_HOSTSS1_RSTN_BUS_PCIE 5 +#define JHB100_SYS1RST_HOSTSS1_RSTN_CRG 6 +#define JHB100_SYS1RST_BMCPERIPH3_RSTN_CRG 7 +#define JHB100_SYS1RST_BMCPERIPH3_RSTN_BUS 8 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */ --=20 2.25.1 From nobody Wed Sep 30 16:18:44 2026 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2115.outbound.protection.partner.outlook.cn [139.219.146.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E9804F96B5; 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R . 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charset="utf-8" Add support for JHB100 System-1 clock generator (SYS1CRG). Signed-off-by: Changhuang Liang --- drivers/clk/starfive/Kconfig | 10 ++ drivers/clk/starfive/Makefile | 1 + .../clk/starfive/clk-starfive-jhb100-sys1.c | 105 ++++++++++++++++++ 3 files changed, 116 insertions(+) create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys1.c diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index cd5b7754403e..11da8bcc4046 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -82,3 +82,13 @@ config CLK_STARFIVE_JHB100_SYS0 help Say yes here to support the system-0 clock controller on the StarFive JHB100 SoC. + +config CLK_STARFIVE_JHB100_SYS1 + bool "StarFive JHB100 system-1 clock support" + depends on ARCH_STARFIVE || COMPILE_TEST + select CLK_STARFIVE_JH71X0 + select RESET_STARFIVE_JHB100 if RESET_CONTROLLER + default ARCH_STARFIVE + help + Say yes here to support the system-1 clock controller on the + StarFive JHB100 SoC. diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index d2ba83d7d02c..0061550e0f7e 100644 --- a/drivers/clk/starfive/Makefile +++ b/drivers/clk/starfive/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) +=3D clk-starfive-j= h7110-isp.o obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) +=3D clk-starfive-jh7110-vout.o =20 obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) +=3D clk-starfive-jhb100-sys0.o +obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) +=3D clk-starfive-jhb100-sys1.o diff --git a/drivers/clk/starfive/clk-starfive-jhb100-sys1.c b/drivers/clk/= starfive/clk-starfive-jhb100-sys1.c new file mode 100644 index 000000000000..92e9c66ca0ff --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jhb100-sys1.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JHB100 System-1 Clock Driver + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * + * Author: Changhuang Liang + * + */ + +#include +#include +#include + +#include "clk-starfive-jh71x0.h" + +#define JHB100_SYS1CLK_NUM_CLKS (JHB100_SYS1CLK_BMCPER3_CFG_125 + 1) + +/* external clocks */ +#define JHB100_SYS1CLK_OSC (JHB100_SYS1CLK_NUM_CLKS + 0) +#define JHB100_SYS1CLK_PLL0 (JHB100_SYS1CLK_NUM_CLKS + 1) +#define JHB100_SYS1CLK_PLL1 (JHB100_SYS1CLK_NUM_CLKS + 2) +#define JHB100_SYS1CLK_PLL2 (JHB100_SYS1CLK_NUM_CLKS + 3) +#define JHB100_SYS1CLK_PLL4 (JHB100_SYS1CLK_NUM_CLKS + 4) +#define JHB100_SYS1CLK_PLL5 (JHB100_SYS1CLK_NUM_CLKS + 5) +#define JHB100_SYS1CLK_NPU_NCNOC_INIT (JHB100_SYS1CLK_NUM_CLKS + 6) + +static const char * const jhb100_sys1_ext_clk[] =3D { + "osc", + "pll0", + "pll1", + "pll2", + "pll4", + "pll5", + "npu_ncnoc_init", +}; + +static const struct jh71x0_clk_data jhb100_sys1crg_clk_data[] =3D { + /* root */ + JH71X0__DIV(JHB100_SYS1CLK_APB_MAIN_SYS1, "apb_main_sys1", 12, + JHB100_SYS1CLK_PLL1), + /* sensor */ + JH71X0_GATE(JHB100_SYS1CLK_APB_SENSOR_ICG_BUF, "apb_sensor_icg_buf", + CLK_IS_CRITICAL, JHB100_SYS1CLK_APB_MAIN_SYS1), + /* hostss1 */ + JH71X0__DIV(JHB100_SYS1CLK_GPIO_ESPI1_EXT, "gpio_espi1_ext", 14, + JHB100_SYS1CLK_PLL2), + JH71X0__DIV(JHB100_SYS1CLK_HOSTSS1_NCNOC_CFG, "hostss1_ncnoc_cfg", 12, + JHB100_SYS1CLK_PLL1), + JH71X0_GATE(JHB100_SYS1CLK_HOSTSS1_PHY_SCAN_1000_ICG_BUF, + "hostss1_phy_scan_1000_icg_buf", CLK_IS_CRITICAL, + JHB100_SYS1CLK_PLL1), + /* npu */ + JH71X0__DIV(JHB100_SYS1CLK_NPU_NCNOC_CFG, "npu_ncnoc_cfg", 6, + JHB100_SYS1CLK_PLL1), + JH71X0__DIV(JHB100_SYS1CLK_NPU_CORE_DIV, "npu_core_div", 10, + JHB100_SYS1CLK_PLL0), + JH71X0_GATE(JHB100_SYS1CLK_DOM_NPU_CORE_CLK, "dom_npu_core_clk", + CLK_IS_CRITICAL, JHB100_SYS1CLK_NPU_CORE_DIV), + JH71X0_GATE(JHB100_SYS1CLK_DOM_NPU_BUS_CLK, "dom_npu_bus_clk", + CLK_IS_CRITICAL, JHB100_SYS1CLK_NPU_NCNOC_INIT), + JH71X0_GATE(JHB100_SYS1CLK_DOM_NPU_INIT_CLK, "dom_npu_init_clk", + CLK_IS_CRITICAL, JHB100_SYS1CLK_NPU_NCNOC_CFG), + JH71X0_GATE(JHB100_SYS1CLK_DOM_NPU_OSC_CLK, "dom_npu_osc_clk", + CLK_IS_CRITICAL, JHB100_SYS1CLK_OSC), + /* vout */ + JH71X0__DIV(JHB100_SYS1CLK_VOUT_NCNOC_TARG, "vout_ncnoc_targ", 12, + JHB100_SYS1CLK_PLL1), + JH71X0__DIV(JHB100_SYS1CLK_VOUT_PIX0, "vout_pix0", 4, + JHB100_SYS1CLK_PLL4), + JH71X0__DIV(JHB100_SYS1CLK_VOUT_PIX1, "vout_pix1", 4, + JHB100_SYS1CLK_PLL5), + /* bmcperiph3 */ + JH71X0__DIV(JHB100_SYS1CLK_BMCPER3_NCNOC_TARG, "bmcper3_ncnoc_targ", 12, + JHB100_SYS1CLK_PLL1), + JH71X0__DIV(JHB100_SYS1CLK_BMCPER3_CFG_125, "bmcper3_cfg_125", 10, + JHB100_SYS1CLK_PLL1), +}; + +static const struct jh71x0_crg_domain_info jhb100_sys1crg_info =3D { + .clk_data =3D jhb100_sys1crg_clk_data, + .num_clk =3D ARRAY_SIZE(jhb100_sys1crg_clk_data), + .ext_clk =3D jhb100_sys1_ext_clk, + .num_ext_clk =3D ARRAY_SIZE(jhb100_sys1_ext_clk), + .rst_name =3D "jhb100-r-sys1", + .power_domain =3D false, +}; + +static const struct of_device_id jhb100_sys1crg_match[] =3D { + { + .compatible =3D "starfive,jhb100-sys1crg", + .data =3D &jhb100_sys1crg_info, + }, + { /* sentinel */ } +}; + +static struct platform_driver jhb100_sys1crg_driver =3D { + .probe =3D jh71x0_crg_probe, + .driver =3D { + .name =3D "clk-starfive-jhb100-sys1", + .of_match_table =3D jhb100_sys1crg_match, + .suppress_bind_attrs =3D true, + }, +}; +builtin_platform_driver(jhb100_sys1crg_driver); --=20 2.25.1 From nobody Wed Sep 30 16:18:44 2026 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2129.outbound.protection.partner.outlook.cn [139.219.146.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A72C4D9F6A; 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charset="utf-8" Add bindings for the System-2 clocks and reset generator (SYS2CRG) on JHB100 SoC. Signed-off-by: Changhuang Liang Reviewed-by: Rob Herring (Arm) --- .../clock/starfive,jhb100-sys2crg.yaml | 64 +++++++++++++++++++ .../dt-bindings/clock/starfive,jhb100-crg.h | 33 ++++++++++ .../dt-bindings/reset/starfive,jhb100-crg.h | 25 ++++++++ 3 files changed, 122 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100= -sys2crg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-sys2cr= g.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys2crg.ya= ml new file mode 100644 index 000000000000..a63809c72e2a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys2crg.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jhb100-sys2crg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 System-2 Clock and Reset Generator + +maintainers: + - Changhuang Liang + +properties: + compatible: + const: starfive,jhb100-sys2crg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (25 MHz) + - description: PLL1 + - description: GPU0 Non Coherent NOC Initiator + - description: GPU1 Non Coherent NOC Initiator + + clock-names: + items: + - const: osc + - const: pll1 + - const: gpu0_ncnoc_init + - const: gpu1_ncnoc_init + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@13008000 { + compatible =3D "starfive,jhb100-sys2crg"; + reg =3D <0x13008000 0x4000>; + clocks =3D <&osc>, <&pll1>, <&sys0crg 73>, + <&sys0crg 74>; + clock-names =3D "osc", "pll1", "gpu0_ncnoc_init", + "gpu1_ncnoc_init"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-b= indings/clock/starfive,jhb100-crg.h index d7904b32bd51..d19618e2a846 100644 --- a/include/dt-bindings/clock/starfive,jhb100-crg.h +++ b/include/dt-bindings/clock/starfive,jhb100-crg.h @@ -73,4 +73,37 @@ #define JHB100_SYS1CLK_BMCPER3_NCNOC_TARG 18 #define JHB100_SYS1CLK_BMCPER3_CFG_125 19 =20 +/* SYS2CRG clocks */ +#define JHB100_SYS2CLK_JTAGM0_HCLK 3 +#define JHB100_SYS2CLK_JTAGM1_HCLK 4 +#define JHB100_SYS2CLK_JTAGM0_ATPG 5 +#define JHB100_SYS2CLK_JTAGM1_ATPG 6 +#define JHB100_SYS2CLK_JTAGM0_ATPG_TCLOCK 7 +#define JHB100_SYS2CLK_JTAGM1_ATPG_TCLOCK 8 +#define JHB100_SYS2CLK_JTAG0_MST_WRAP_HCLK 9 +#define JHB100_SYS2CLK_JTAG0_MST_WRAP_CLK_JTAG 10 +#define JHB100_SYS2CLK_JTAG0_MST_WRAP_APB_PCLK 11 +#define JHB100_SYS2CLK_JTAG0_MST_WRAP_ATPG_TCLOCK 12 +#define JHB100_SYS2CLK_JTAG1_MST_WRAP_HCLK 13 +#define JHB100_SYS2CLK_JTAG1_MST_WRAP_CLK_JTAG 14 +#define JHB100_SYS2CLK_JTAG1_MST_WRAP_APB_PCLK 15 +#define JHB100_SYS2CLK_JTAG1_MST_WRAP_ATPG_TCLOCK 16 +#define JHB100_SYS2CLK_HOSTUSB_NCNOC_TARG 17 +#define JHB100_SYS2CLK_HOSTUSBCMN_CFG_500 18 +#define JHB100_SYS2CLK_BMCPER1_NCNOC_TARG 19 +#define JHB100_SYS2CLK_BMCPER1_CFG_250 20 +#define JHB100_SYS2CLK_BMCPER1_CFG_143_DFT 21 +#define JHB100_SYS2CLK_BMCPER1_CFG_143 22 +#define JHB100_SYS2CLK_BMCPER0_NCNOC_TARG 23 +#define JHB100_SYS2CLK_GPU0_NCNOC_TARG 24 +#define JHB100_SYS2CLK_GPU0_BUS_CLK 25 +#define JHB100_SYS2CLK_GPU0_APB_CLK 26 +#define JHB100_SYS2CLK_GPU0_OSC_CLK 27 +#define JHB100_SYS2CLK_GPU1_NCNOC_TARG 28 +#define JHB100_SYS2CLK_GPU1_BUS_CLK 29 +#define JHB100_SYS2CLK_GPU1_APB_CLK 30 +#define JHB100_SYS2CLK_GPU1_OSC_CLK 31 +#define JHB100_SYS2CLK_MAIN_ICG_EN_JTAG0 32 +#define JHB100_SYS2CLK_MAIN_ICG_EN_JTAG1 33 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-b= indings/reset/starfive,jhb100-crg.h index da1b51621172..fbc55f95e76c 100644 --- a/include/dt-bindings/reset/starfive,jhb100-crg.h +++ b/include/dt-bindings/reset/starfive,jhb100-crg.h @@ -36,4 +36,29 @@ #define JHB100_SYS1RST_BMCPERIPH3_RSTN_CRG 7 #define JHB100_SYS1RST_BMCPERIPH3_RSTN_BUS 8 =20 +/* SYS2CRG resets */ +#define JHB100_SYS2RST_JTAG0_MST_WRAP_HRESETN 0 +#define JHB100_SYS2RST_JTAG0_MST_WRAP_APB_PRESETN 1 +#define JHB100_SYS2RST_JTAG1_MST_WRAP_HRESETN 2 +#define JHB100_SYS2RST_JTAG1_MST_WRAP_APB_PRESETN 3 +#define JHB100_SYS2RST_HUSBCMN_HOSTCMN_RSTN_BUS_NCNOC_INIT 4 +#define JHB100_SYS2RST_HUSBCMN_RSTN_HOSTCMN_CRG 5 +#define JHB100_SYS2RST_HUSBCMN_HOSTUSB0_RSTN_BUS_NCNOC_BMC_TARG 6 +#define JHB100_SYS2RST_HUSBCMN_HOSTUSB0_RSTN_BUS_NCNOC_HOST_TARG 7 +#define JHB100_SYS2RST_HUSBCMN_RSTN_BMC_CRG 8 +#define JHB100_SYS2RST_HUSBCMN_RSTN_HOSTUSB0_CRG 9 +#define JHB100_SYS2RST_HUSBCMN_HOSTUSB1_RSTN_BUS_NCNOC_BMC_TARG 10 +#define JHB100_SYS2RST_HUSBCMN_HOSTUSB1_RSTN_BUS_NCNOC_HOST_TARG 11 +#define JHB100_SYS2RST_HUSBCMN_RSTN_HOSTUSB1_CRG 12 +#define JHB100_SYS2RST_BMCPERIPH1_RSTN_CRG 13 +#define JHB100_SYS2RST_BMCPERIPH1_RSTN_BUS 14 +#define JHB100_SYS2RST_BMCPERIPH0_RSTN_CRG 15 +#define JHB100_SYS2RST_BMCPERIPH0_RSTN_BUS 16 +#define JHB100_SYS2RST_GPU0_RSTN_CRG 17 +#define JHB100_SYS2RST_GPU0_RSTN_BUS 18 +#define JHB100_SYS2RST_GPU0_HOST_PCIE_RST_N 19 +#define JHB100_SYS2RST_GPU1_RSTN_CRG 20 +#define JHB100_SYS2RST_GPU1_RSTN_BUS 21 +#define JHB100_SYS2RST_GPU1_HOST_PCIE_RST_N 22 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */ --=20 2.25.1 From nobody Wed Sep 30 16:18:44 2026 Received: from CHN02-BJS-obe.outbound.protection.partner.outlook.cn (mail-bjschn02on2118.outbound.protection.partner.outlook.cn [139.219.17.118]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A1FB4D9908; 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charset="utf-8" Add support for JHB100 System-2 clock generator (SYS2CRG). Signed-off-by: Changhuang Liang --- drivers/clk/starfive/Kconfig | 10 ++ drivers/clk/starfive/Makefile | 1 + .../clk/starfive/clk-starfive-jhb100-sys2.c | 129 ++++++++++++++++++ 3 files changed, 140 insertions(+) create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys2.c diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index 11da8bcc4046..cfaac934a8e0 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -92,3 +92,13 @@ config CLK_STARFIVE_JHB100_SYS1 help Say yes here to support the system-1 clock controller on the StarFive JHB100 SoC. + +config CLK_STARFIVE_JHB100_SYS2 + bool "StarFive JHB100 system-2 clock support" + depends on ARCH_STARFIVE || COMPILE_TEST + select CLK_STARFIVE_JH71X0 + select RESET_STARFIVE_JHB100 if RESET_CONTROLLER + default ARCH_STARFIVE + help + Say yes here to support the system-2 clock controller on the + StarFive JHB100 SoC. diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index 0061550e0f7e..29cdef20575e 100644 --- a/drivers/clk/starfive/Makefile +++ b/drivers/clk/starfive/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) +=3D clk-starfive-= jh7110-vout.o =20 obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) +=3D clk-starfive-jhb100-sys0.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) +=3D clk-starfive-jhb100-sys1.o +obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) +=3D clk-starfive-jhb100-sys2.o diff --git a/drivers/clk/starfive/clk-starfive-jhb100-sys2.c b/drivers/clk/= starfive/clk-starfive-jhb100-sys2.c new file mode 100644 index 000000000000..a2c7e8eba9b6 --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jhb100-sys2.c @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JHB100 System-2 Clock Driver + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * + * Author: Changhuang Liang + * + */ + +#include +#include +#include + +#include "clk-starfive-jh71x0.h" + +#define JHB100_SYS2CLK_NUM_CLKS (JHB100_SYS2CLK_MAIN_ICG_EN_JTAG1 + 1) + +/* external clocks */ +#define JHB100_SYS2CLK_OSC (JHB100_SYS2CLK_NUM_CLKS + 0) +#define JHB100_SYS2CLK_PLL1 (JHB100_SYS2CLK_NUM_CLKS + 1) +#define JHB100_SYS2CLK_GPU0_NCNOC_INIT (JHB100_SYS2CLK_NUM_CLKS + 2) +#define JHB100_SYS2CLK_GPU1_NCNOC_INIT (JHB100_SYS2CLK_NUM_CLKS + 3) + +static const char * const jhb100_sys2_ext_clk[] =3D { + "osc", + "pll1", + "gpu0_ncnoc_init", + "gpu1_ncnoc_init", +}; + +static const struct jh71x0_clk_data jhb100_sys2crg_clk_data[] =3D { + /* jtag mst*/ + JH71X0__DIV(JHB100_SYS2CLK_JTAGM0_HCLK, "jtagm0_hclk", 6, + JHB100_SYS2CLK_PLL1), + JH71X0__DIV(JHB100_SYS2CLK_JTAGM1_HCLK, "jtagm1_hclk", 6, + JHB100_SYS2CLK_PLL1), + JH71X0__DIV(JHB100_SYS2CLK_JTAGM0_ATPG, "jtagm0_ATPG", 12, + JHB100_SYS2CLK_PLL1), + JH71X0__DIV(JHB100_SYS2CLK_JTAGM1_ATPG, "jtagm1_ATPG", 12, + JHB100_SYS2CLK_PLL1), + JH71X0__DIV(JHB100_SYS2CLK_JTAGM0_ATPG_TCLOCK, "jtagm0_atpg_tclock", 2, + JHB100_SYS2CLK_JTAGM0_ATPG), + JH71X0__DIV(JHB100_SYS2CLK_JTAGM1_ATPG_TCLOCK, "jtagm1_atpg_tclock", 2, + JHB100_SYS2CLK_JTAGM1_ATPG), + JH71X0_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_HCLK, "jtag0_mst_wrap_hclk", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_HCLK), + JH71X0_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_CLK_JTAG, "jtag0_mst_wrap_clk_j= tag", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_HCLK), + JH71X0_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_APB_PCLK, "jtag0_mst_wrap_apb_p= clk", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_ATPG), + JH71X0_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_ATPG_TCLOCK, "jtag0_mst_wrap_at= pg_tclock", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_ATPG), + JH71X0_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_HCLK, "jtag1_mst_wrap_hclk", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_HCLK), + JH71X0_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_CLK_JTAG, "jtag1_mst_wrap_clk_j= tag", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_HCLK), + JH71X0_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_APB_PCLK, "jtag1_mst_wrap_apb_p= clk", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_ATPG), + JH71X0_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_ATPG_TCLOCK, "jtag1_mst_wrap_at= pg_tclock", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_ATPG), + /* hostusbcmn */ + JH71X0__DIV(JHB100_SYS2CLK_HOSTUSB_NCNOC_TARG, "hostusb_ncnoc_targ", 12, + JHB100_SYS2CLK_PLL1), + JH71X0__DIV(JHB100_SYS2CLK_HOSTUSBCMN_CFG_500, "hostusbcmn_cfg_500", 4, + JHB100_SYS2CLK_PLL1), + /* bmcperiph1 */ + JH71X0__DIV(JHB100_SYS2CLK_BMCPER1_NCNOC_TARG, "bmcper1_ncnoc_targ", 6, + JHB100_SYS2CLK_PLL1), + JH71X0__DIV(JHB100_SYS2CLK_BMCPER1_CFG_250, "bmcper1_cfg_250", 5, + JHB100_SYS2CLK_PLL1), + JH71X0__DIV(JHB100_SYS2CLK_BMCPER1_CFG_143_DFT, "bmcper1_cfg_143_dft", 8, + JHB100_SYS2CLK_PLL1), + JH71X0_GATE(JHB100_SYS2CLK_BMCPER1_CFG_143, "bmcper1_cfg_143", CLK_IS_CRI= TICAL, + JHB100_SYS2CLK_BMCPER1_CFG_143_DFT), + /* bmcperiph0 */ + JH71X0__DIV(JHB100_SYS2CLK_BMCPER0_NCNOC_TARG, "bmcper0_ncnoc_targ", 6, + JHB100_SYS2CLK_PLL1), + /* gpu0 */ + JH71X0__DIV(JHB100_SYS2CLK_GPU0_NCNOC_TARG, "gpu0_ncnoc_targ", 12, + JHB100_SYS2CLK_PLL1), + JH71X0_GATE(JHB100_SYS2CLK_GPU0_BUS_CLK, "gpu0_bus_clk", CLK_IS_CRITICAL, + JHB100_SYS2CLK_GPU0_NCNOC_INIT), + JH71X0_GATE(JHB100_SYS2CLK_GPU0_APB_CLK, "gpu0_apb_clk", CLK_IS_CRITICAL, + JHB100_SYS2CLK_GPU0_NCNOC_TARG), + JH71X0_GATE(JHB100_SYS2CLK_GPU0_OSC_CLK, "gpu0_osc_clk", CLK_IS_CRITICAL, + JHB100_SYS2CLK_OSC), + /* gpu1 */ + JH71X0__DIV(JHB100_SYS2CLK_GPU1_NCNOC_TARG, "gpu1_ncnoc_targ", 12, + JHB100_SYS2CLK_PLL1), + JH71X0_GATE(JHB100_SYS2CLK_GPU1_BUS_CLK, "gpu1_bus_clk", CLK_IS_CRITICAL, + JHB100_SYS2CLK_GPU1_NCNOC_INIT), + JH71X0_GATE(JHB100_SYS2CLK_GPU1_APB_CLK, "gpu1_apb_clk", CLK_IS_CRITICAL, + JHB100_SYS2CLK_GPU1_NCNOC_TARG), + JH71X0_GATE(JHB100_SYS2CLK_GPU1_OSC_CLK, "gpu1_osc_clk", CLK_IS_CRITICAL, + JHB100_SYS2CLK_OSC), + /* main icg */ + JH71X0_GATE(JHB100_SYS2CLK_MAIN_ICG_EN_JTAG0, "main_icg_en_jtag0", 0, + JHB100_SYS2CLK_JTAGM0_HCLK), + JH71X0_GATE(JHB100_SYS2CLK_MAIN_ICG_EN_JTAG1, "main_icg_en_jtag1", 0, + JHB100_SYS2CLK_JTAGM1_HCLK), +}; + +static const struct jh71x0_crg_domain_info jhb100_sys2crg_info =3D { + .clk_data =3D jhb100_sys2crg_clk_data, + .num_clk =3D ARRAY_SIZE(jhb100_sys2crg_clk_data), + .ext_clk =3D jhb100_sys2_ext_clk, + .num_ext_clk =3D ARRAY_SIZE(jhb100_sys2_ext_clk), + .rst_name =3D "jhb100-r-sys2", + .power_domain =3D false, +}; + +static const struct of_device_id jhb100_sys2crg_match[] =3D { + { + .compatible =3D "starfive,jhb100-sys2crg", + .data =3D &jhb100_sys2crg_info, + }, + { /* sentinel */ } +}; + +static struct platform_driver jhb100_sys2crg_driver =3D { + .probe =3D jh71x0_crg_probe, + .driver =3D { + .name =3D "clk-starfive-jhb100-sys2", + .of_match_table =3D jhb100_sys2crg_match, + .suppress_bind_attrs =3D true, + }, +}; +builtin_platform_driver(jhb100_sys2crg_driver); --=20 2.25.1 From nobody Wed Sep 30 16:18:44 2026 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2129.outbound.protection.partner.outlook.cn [139.219.146.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CB184E2F33; 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charset="utf-8" Add bindings for the Peripheral-0 clock and reset generator (PER0CRG) on the JHB100 RISC-V SoC by StarFive Ltd. Signed-off-by: Changhuang Liang Reviewed-by: Rob Herring (Arm) --- .../clock/starfive,jhb100-per0crg.yaml | 70 +++++ .../dt-bindings/clock/starfive,jhb100-crg.h | 281 ++++++++++++++++++ .../dt-bindings/reset/starfive,jhb100-crg.h | 77 +++++ 3 files changed, 428 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100= -per0crg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-per0cr= g.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-per0crg.ya= ml new file mode 100644 index 000000000000..db43e03fd60c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-per0crg.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jhb100-per0crg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 Peripheral-0 Clock and Reset Generator + +maintainers: + - Changhuang Liang + +properties: + compatible: + const: starfive,jhb100-per0crg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (25 MHz) + - description: PLL6 + - description: Configure 400MHz + - description: Configure 800MHZ + - description: Non Coherent NOC Initiator + - description: Non Coherent NOC Target + + clock-names: + items: + - const: osc + - const: pll6 + - const: cfg_400 + - const: cfg_800 + - const: ncnoc_init + - const: ncnoc_targ + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@11a08000 { + compatible =3D "starfive,jhb100-per0crg"; + reg =3D <0x11a08000 0x1000>; + clocks =3D <&osc>, <&pll6>, <&sys0crg 71>, + <&sys0crg 72>, <&sys0crg 70>, + <&sys2crg 23>; + clock-names =3D "osc", "pll6", "cfg_400", + "cfg_800", "ncnoc_init", + "ncnoc_targ"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-b= indings/clock/starfive,jhb100-crg.h index d19618e2a846..add2cd093dbd 100644 --- a/include/dt-bindings/clock/starfive,jhb100-crg.h +++ b/include/dt-bindings/clock/starfive,jhb100-crg.h @@ -106,4 +106,285 @@ #define JHB100_SYS2CLK_MAIN_ICG_EN_JTAG0 32 #define JHB100_SYS2CLK_MAIN_ICG_EN_JTAG1 33 =20 +/* PER0CRG clocks */ +#define JHB100_PER0CLK_CDR_I3C0 0 +#define JHB100_PER0CLK_CDR_I3C1 1 +#define JHB100_PER0CLK_CDR_I3C2 2 +#define JHB100_PER0CLK_CDR_I3C3 3 +#define JHB100_PER0CLK_CDR_I3C4 4 +#define JHB100_PER0CLK_CDR_I3C5 5 +#define JHB100_PER0CLK_CDR_I3C6 6 +#define JHB100_PER0CLK_CDR_I3C7 7 +#define JHB100_PER0CLK_CDR_I3C8 8 +#define JHB100_PER0CLK_CDR_I3C9 9 +#define JHB100_PER0CLK_CDR_I3C10 10 +#define JHB100_PER0CLK_CDR_I3C11 11 +#define JHB100_PER0CLK_CDR_I3C12 12 +#define JHB100_PER0CLK_CDR_I3C13 13 +#define JHB100_PER0CLK_CDR_I3C14 14 +#define JHB100_PER0CLK_CDR_I3C15 15 +#define JHB100_PER0CLK_200 16 +#define JHB100_PER0CLK_600_DIV6 17 +#define JHB100_PER0CLK_600_DIV6_DIV5 18 +#define JHB100_PER0CLK_TIMER0_DUALTIMER0 19 +#define JHB100_PER0CLK_TIMER1_DUALTIMER0 20 +#define JHB100_PER0CLK_TIMER0_DUALTIMER1 21 +#define JHB100_PER0CLK_TIMER1_DUALTIMER1 22 +#define JHB100_PER0CLK_TIMER0_DUALTIMER2 23 +#define JHB100_PER0CLK_TIMER1_DUALTIMER2 24 +#define JHB100_PER0CLK_1200_PH0_LVDS0 25 +#define JHB100_PER0CLK_1200_PH0_LVDS1 26 +#define JHB100_PER0CLK_1200_CORE0 27 +#define JHB100_PER0CLK_1200_CORE1 28 +#define JHB100_PER0CLK_1200_SHIFT90_LVDS0 29 +#define JHB100_PER0CLK_1200_SHIFT90_LVDS1 30 +#define JHB100_PER0CLK_1200_DIV5_CORE0 31 +#define JHB100_PER0CLK_1200_DIV5_CORE1 32 +#define JHB100_PER0CLK_PH0_LTPI0 33 + +#define JHB100_PER0CLK_PH0_LTPI1 35 + +#define JHB100_PER0CLK_PH90_LTPI0 37 + +#define JHB100_PER0CLK_PH90_LTPI1 39 + +#define JHB100_PER0CLK_240_CORE_LTPI0 41 + +#define JHB100_PER0CLK_240_CORE_LTPI1 43 + +#define JHB100_PER0CLK_AXI_DMA_I2C_INIT 45 +#define JHB100_PER0CLK_AXI_DMA_I3C_INIT 46 +#define JHB100_PER0CLK_AXI_DMA_UART_INIT 47 +#define JHB100_PER0CLK_CORE_DMAC0 48 +#define JHB100_PER0CLK_CORE_DMAC1 49 +#define JHB100_PER0CLK_CORE_DMAC2 50 + +#define JHB100_PER0CLK_HDR_TX_I3C0 78 +#define JHB100_PER0CLK_HDR_TX_I3C1 79 +#define JHB100_PER0CLK_HDR_TX_I3C2 80 +#define JHB100_PER0CLK_HDR_TX_I3C3 81 +#define JHB100_PER0CLK_HDR_TX_I3C4 82 +#define JHB100_PER0CLK_HDR_TX_I3C5 83 +#define JHB100_PER0CLK_HDR_TX_I3C6 84 +#define JHB100_PER0CLK_HDR_TX_I3C7 85 +#define JHB100_PER0CLK_HDR_TX_I3C8 86 +#define JHB100_PER0CLK_HDR_TX_I3C9 87 +#define JHB100_PER0CLK_HDR_TX_I3C10 88 +#define JHB100_PER0CLK_HDR_TX_I3C11 89 +#define JHB100_PER0CLK_HDR_TX_I3C12 90 +#define JHB100_PER0CLK_HDR_TX_I3C13 91 +#define JHB100_PER0CLK_HDR_TX_I3C14 92 +#define JHB100_PER0CLK_HDR_TX_I3C15 93 +#define JHB100_PER0CLK_CORE_I2C0 94 +#define JHB100_PER0CLK_CORE_I2C1 95 +#define JHB100_PER0CLK_CORE_I2C2 96 +#define JHB100_PER0CLK_CORE_I2C3 97 +#define JHB100_PER0CLK_CORE_I2C4 98 +#define JHB100_PER0CLK_CORE_I2C5 99 +#define JHB100_PER0CLK_CORE_I2C6 100 +#define JHB100_PER0CLK_CORE_I2C7 101 +#define JHB100_PER0CLK_CORE_I2C8 102 +#define JHB100_PER0CLK_CORE_I2C9 103 +#define JHB100_PER0CLK_CORE_I2C10 104 +#define JHB100_PER0CLK_CORE_I2C11 105 +#define JHB100_PER0CLK_CORE_I2C12 106 +#define JHB100_PER0CLK_CORE_I2C13 107 +#define JHB100_PER0CLK_CORE_I2C14 108 +#define JHB100_PER0CLK_CORE_I2C15 109 + +#define JHB100_PER0CLK_WDOGCLK_WDT0 126 +#define JHB100_PER0CLK_WDOGCLK_WDT1 127 +#define JHB100_PER0CLK_WDOGCLK_WDT2 128 +#define JHB100_PER0CLK_WDOGCLK_WDT3 129 +#define JHB100_PER0CLK_WDOGCLK_WDT_EXTERNAL 130 +#define JHB100_PER0CLK_SCLK_UART4 131 +#define JHB100_PER0CLK_SCLK_UART5 132 +#define JHB100_PER0CLK_SCLK_UART6 133 +#define JHB100_PER0CLK_SCLK_UART7 134 +#define JHB100_PER0CLK_SCLK_UART8 135 +#define JHB100_PER0CLK_SCLK_UART9 136 +#define JHB100_PER0CLK_SCLK_UART10 137 +#define JHB100_PER0CLK_SCLK_UART11 138 +#define JHB100_PER0CLK_SCLK_UART12 139 +#define JHB100_PER0CLK_SCLK_UART13 140 +#define JHB100_PER0CLK_SCLK_UART14 141 + +#define JHB100_PER0CLK_PCLK_DMA_UART_CFG 148 +#define JHB100_PER0CLK_PCLK_DMA_I2C_CFG 149 +#define JHB100_PER0CLK_PCLK_DMA_I3C_CFG 150 +#define JHB100_PER0CLK_PCLK_DUALTIMER0 151 +#define JHB100_PER0CLK_PCLK_DUALTIMER1 152 +#define JHB100_PER0CLK_PCLK_DUALTIMER2 153 + +#define JHB100_PER0CLK_HCLK_TRNG 156 +#define JHB100_PER0CLK_APB_I2C0 157 +#define JHB100_PER0CLK_APB_I2C1 158 +#define JHB100_PER0CLK_APB_I2C2 159 +#define JHB100_PER0CLK_APB_I2C3 160 +#define JHB100_PER0CLK_APB_I2C4 161 +#define JHB100_PER0CLK_APB_I2C5 162 +#define JHB100_PER0CLK_APB_I2C6 163 +#define JHB100_PER0CLK_APB_I2C7 164 +#define JHB100_PER0CLK_APB_I2C8 165 +#define JHB100_PER0CLK_APB_I2C9 166 +#define JHB100_PER0CLK_APB_I2C10 167 +#define JHB100_PER0CLK_APB_I2C11 168 +#define JHB100_PER0CLK_APB_I2C12 169 +#define JHB100_PER0CLK_APB_I2C13 170 +#define JHB100_PER0CLK_APB_I2C14 171 +#define JHB100_PER0CLK_APB_I2C15 172 +#define JHB100_PER0CLK_APB_I2CF0 173 +#define JHB100_PER0CLK_APB_I2CF1 174 +#define JHB100_PER0CLK_APB_I2CF2 175 +#define JHB100_PER0CLK_APB_I2CF3 176 +#define JHB100_PER0CLK_APB_I2CF4 177 +#define JHB100_PER0CLK_APB_I2CF5 178 +#define JHB100_PER0CLK_APB_I2CF6 179 +#define JHB100_PER0CLK_APB_I2CF7 180 +#define JHB100_PER0CLK_APB_I2CF8 181 +#define JHB100_PER0CLK_APB_I2CF9 182 +#define JHB100_PER0CLK_APB_I2CF10 183 +#define JHB100_PER0CLK_APB_I2CF11 184 +#define JHB100_PER0CLK_APB_I2CF12 185 +#define JHB100_PER0CLK_APB_I2CF13 186 +#define JHB100_PER0CLK_APB_I2CF14 187 +#define JHB100_PER0CLK_APB_I2CF15 188 +#define JHB100_PER0CLK_APB_I3C0 189 +#define JHB100_PER0CLK_APB_I3C1 190 +#define JHB100_PER0CLK_APB_I3C2 191 +#define JHB100_PER0CLK_APB_I3C3 192 +#define JHB100_PER0CLK_APB_I3C4 193 +#define JHB100_PER0CLK_APB_I3C5 194 +#define JHB100_PER0CLK_APB_I3C6 195 +#define JHB100_PER0CLK_APB_I3C7 196 +#define JHB100_PER0CLK_APB_I3C8 197 +#define JHB100_PER0CLK_APB_I3C9 198 +#define JHB100_PER0CLK_APB_I3C10 199 +#define JHB100_PER0CLK_APB_I3C11 200 +#define JHB100_PER0CLK_APB_I3C12 201 +#define JHB100_PER0CLK_APB_I3C13 202 +#define JHB100_PER0CLK_APB_I3C14 203 +#define JHB100_PER0CLK_APB_I3C15 204 +#define JHB100_PER0CLK_APB_UART0 205 +#define JHB100_PER0CLK_APB_UART1 206 +#define JHB100_PER0CLK_APB_UART2 207 +#define JHB100_PER0CLK_APB_UART3 208 +#define JHB100_PER0CLK_APB_UART4 209 +#define JHB100_PER0CLK_APB_UART5 210 +#define JHB100_PER0CLK_APB_UART6 211 +#define JHB100_PER0CLK_APB_UART7 212 +#define JHB100_PER0CLK_APB_UART8 213 +#define JHB100_PER0CLK_APB_UART9 214 +#define JHB100_PER0CLK_APB_UART10 215 +#define JHB100_PER0CLK_APB_UART11 216 +#define JHB100_PER0CLK_APB_UART12 217 +#define JHB100_PER0CLK_APB_UART13 218 +#define JHB100_PER0CLK_APB_UART14 219 +#define JHB100_PER0CLK_DMA_I3C0 220 +#define JHB100_PER0CLK_DMA_I3C1 221 +#define JHB100_PER0CLK_DMA_I3C2 222 +#define JHB100_PER0CLK_DMA_I3C3 223 +#define JHB100_PER0CLK_DMA_I3C4 224 +#define JHB100_PER0CLK_DMA_I3C5 225 +#define JHB100_PER0CLK_DMA_I3C6 226 +#define JHB100_PER0CLK_DMA_I3C7 227 +#define JHB100_PER0CLK_DMA_I3C8 228 +#define JHB100_PER0CLK_DMA_I3C9 229 +#define JHB100_PER0CLK_DMA_I3C10 230 +#define JHB100_PER0CLK_DMA_I3C11 231 +#define JHB100_PER0CLK_DMA_I3C12 232 +#define JHB100_PER0CLK_DMA_I3C13 233 +#define JHB100_PER0CLK_DMA_I3C14 234 +#define JHB100_PER0CLK_DMA_I3C15 235 +#define JHB100_PER0CLK_CORE_I3C0 236 +#define JHB100_PER0CLK_CORE_I3C1 237 +#define JHB100_PER0CLK_CORE_I3C2 238 +#define JHB100_PER0CLK_CORE_I3C3 239 +#define JHB100_PER0CLK_CORE_I3C4 240 +#define JHB100_PER0CLK_CORE_I3C5 241 +#define JHB100_PER0CLK_CORE_I3C6 242 +#define JHB100_PER0CLK_CORE_I3C7 243 +#define JHB100_PER0CLK_CORE_I3C8 244 +#define JHB100_PER0CLK_CORE_I3C9 245 +#define JHB100_PER0CLK_CORE_I3C10 246 +#define JHB100_PER0CLK_CORE_I3C11 247 +#define JHB100_PER0CLK_CORE_I3C12 248 +#define JHB100_PER0CLK_CORE_I3C13 249 +#define JHB100_PER0CLK_CORE_I3C14 250 +#define JHB100_PER0CLK_CORE_I3C15 251 +#define JHB100_PER0CLK_DMAC_AXI_PERIPH0_HS_CLK_I2C 252 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C0 253 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C1 254 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C2 255 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C3 256 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C4 257 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C5 258 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C6 259 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C7 260 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C8 261 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C9 262 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C10 263 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C11 264 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C12 265 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C13 266 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C14 267 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C15 268 +#define JHB100_PER0CLK_MAIN_ICG_EN_DUALTIMER0 269 +#define JHB100_PER0CLK_MAIN_ICG_EN_DUALTIMER1 270 +#define JHB100_PER0CLK_MAIN_ICG_EN_DUALTIMER2 271 +#define JHB100_PER0CLK_MAIN_ICG_EN_LTPI0 272 +#define JHB100_PER0CLK_MAIN_ICG_EN_LTPI1 273 +#define JHB100_PER0CLK_MAIN_ICG_EN_DMAC_I2C 274 +#define JHB100_PER0CLK_MAIN_ICG_EN_DMAC_I3C 275 +#define JHB100_PER0CLK_MAIN_ICG_EN_DMAC_UART 276 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL4 277 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL5 278 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL6 279 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL7 280 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL8 281 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL9 282 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL10 283 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL11 284 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL12 285 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL13 286 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL14 287 + +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C0 304 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C1 305 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C2 306 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C3 307 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C4 308 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C5 309 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C6 310 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C7 311 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C8 312 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C9 313 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C10 314 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C11 315 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C12 316 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C13 317 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C14 318 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C15 319 +#define JHB100_PER0CLK_MAIN_ICG_EN_WDT0 320 +#define JHB100_PER0CLK_MAIN_ICG_EN_WDT1 321 +#define JHB100_PER0CLK_MAIN_ICG_EN_WDT2 322 +#define JHB100_PER0CLK_MAIN_ICG_EN_WDT3 323 +#define JHB100_PER0CLK_MAIN_ICG_EN_WDT_EXTERNAL 324 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART4 325 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART5 326 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART6 327 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART7 328 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART8 329 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART9 330 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART10 331 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART11 332 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART12 333 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART13 334 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART14 335 +#define JHB100_PER0CLK_MAIN_ICG_EN_LDO0 336 +#define JHB100_PER0CLK_MAIN_ICG_EN_LDO1 337 +#define JHB100_PER0CLK_MAIN_ICG_EN_SENSORS_PERIPH0 338 +#define JHB100_PER0CLK_MAIN_ICG_EN_SENSORS_DMAC 339 +#define JHB100_PER0CLK_MAIN_ICG_EN_TRNG 340 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-b= indings/reset/starfive,jhb100-crg.h index fbc55f95e76c..ccfb7616e1a7 100644 --- a/include/dt-bindings/reset/starfive,jhb100-crg.h +++ b/include/dt-bindings/reset/starfive,jhb100-crg.h @@ -61,4 +61,81 @@ #define JHB100_SYS2RST_GPU1_RSTN_BUS 21 #define JHB100_SYS2RST_GPU1_HOST_PCIE_RST_N 22 =20 +/* PER0CRG resets */ +#define JHB100_PER0RST_MAIN_RSTN_UART4 0 +#define JHB100_PER0RST_MAIN_RSTN_UART5 1 +#define JHB100_PER0RST_MAIN_RSTN_UART6 2 +#define JHB100_PER0RST_MAIN_RSTN_UART7 3 +#define JHB100_PER0RST_MAIN_RSTN_UART8 4 +#define JHB100_PER0RST_MAIN_RSTN_UART9 5 +#define JHB100_PER0RST_MAIN_RSTN_UART10 6 +#define JHB100_PER0RST_MAIN_RSTN_UART11 7 +#define JHB100_PER0RST_MAIN_RSTN_UART12 8 +#define JHB100_PER0RST_MAIN_RSTN_UART13 9 +#define JHB100_PER0RST_MAIN_RSTN_UART14 10 +#define JHB100_PER0RST_MAIN_RSTN_I2C0 11 +#define JHB100_PER0RST_MAIN_RSTN_I2C1 12 +#define JHB100_PER0RST_MAIN_RSTN_I2C2 13 +#define JHB100_PER0RST_MAIN_RSTN_I2C3 14 +#define JHB100_PER0RST_MAIN_RSTN_I2C4 15 +#define JHB100_PER0RST_MAIN_RSTN_I2C5 16 +#define JHB100_PER0RST_MAIN_RSTN_I2C6 17 +#define JHB100_PER0RST_MAIN_RSTN_I2C7 18 +#define JHB100_PER0RST_MAIN_RSTN_I2C8 19 +#define JHB100_PER0RST_MAIN_RSTN_I2C9 20 +#define JHB100_PER0RST_MAIN_RSTN_I2C10 21 +#define JHB100_PER0RST_MAIN_RSTN_I2C11 22 +#define JHB100_PER0RST_MAIN_RSTN_I2C12 23 +#define JHB100_PER0RST_MAIN_RSTN_I2C13 24 +#define JHB100_PER0RST_MAIN_RSTN_I2C14 25 +#define JHB100_PER0RST_MAIN_RSTN_I2C15 26 +#define JHB100_PER0RST_MAIN_RSTN_I3C0 27 +#define JHB100_PER0RST_MAIN_RSTN_I3C1 28 +#define JHB100_PER0RST_MAIN_RSTN_I3C2 29 +#define JHB100_PER0RST_MAIN_RSTN_I3C3 30 +#define JHB100_PER0RST_MAIN_RSTN_I3C4 31 +#define JHB100_PER0RST_MAIN_RSTN_I3C5 32 +#define JHB100_PER0RST_MAIN_RSTN_I3C6 33 +#define JHB100_PER0RST_MAIN_RSTN_I3C7 34 +#define JHB100_PER0RST_MAIN_RSTN_I3C8 35 +#define JHB100_PER0RST_MAIN_RSTN_I3C9 36 +#define JHB100_PER0RST_MAIN_RSTN_I3C10 37 +#define JHB100_PER0RST_MAIN_RSTN_I3C11 38 +#define JHB100_PER0RST_MAIN_RSTN_I3C12 39 +#define JHB100_PER0RST_MAIN_RSTN_I3C13 40 +#define JHB100_PER0RST_MAIN_RSTN_I3C14 41 +#define JHB100_PER0RST_MAIN_RSTN_I3C15 42 +#define JHB100_PER0RST_MAIN_RSTN_WDT0 43 +#define JHB100_PER0RST_MAIN_RSTN_WDT1 44 +#define JHB100_PER0RST_MAIN_RSTN_WDT2 45 +#define JHB100_PER0RST_MAIN_RSTN_WDT3 46 +#define JHB100_PER0RST_MAIN_RSTN_WDT4 47 +#define JHB100_PER0RST_MAIN_RSTN_DUALTIMER0 48 +#define JHB100_PER0RST_MAIN_RSTN_DUALTIMER1 49 +#define JHB100_PER0RST_MAIN_RSTN_DUALTIMER2 50 +#define JHB100_PER0RST_MAIN_RSTN_TRNG 51 +#define JHB100_PER0RST_MAIN_RSTN_DMAC0 52 +#define JHB100_PER0RST_MAIN_RSTN_DMAC1 53 +#define JHB100_PER0RST_MAIN_RSTN_DMAC2 54 +#define JHB100_PER0RST_MAIN_RSTN_LTPI0 55 +#define JHB100_PER0RST_MAIN_RSTN_LTPI1 56 +#define JHB100_PER0RST_MAIN_RSTN_SOL4 57 +#define JHB100_PER0RST_MAIN_RSTN_SOL5 58 +#define JHB100_PER0RST_MAIN_RSTN_SOL6 59 +#define JHB100_PER0RST_MAIN_RSTN_SOL7 60 +#define JHB100_PER0RST_MAIN_RSTN_SOL8 61 +#define JHB100_PER0RST_MAIN_RSTN_SOL9 62 +#define JHB100_PER0RST_MAIN_RSTN_SOL10 63 +#define JHB100_PER0RST_MAIN_RSTN_SOL11 64 +#define JHB100_PER0RST_MAIN_RSTN_SOL12 65 +#define JHB100_PER0RST_MAIN_RSTN_SOL13 66 +#define JHB100_PER0RST_MAIN_RSTN_SOL14 67 +#define JHB100_PER0RST_MAIN_RSTN_LDO0 68 +#define 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R . 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charset="utf-8" Some StarFive clocks only advertise the divider and invert capabilities (via JH71X0_CLK_INVERT, without ENABLE). Add the JH71X0_IDIV() macro to declare such clocks, and jh71x0_clk_idiv_ops, which combines the divider rate operations with get_phase/set_phase. Signed-off-by: Changhuang Liang --- drivers/clk/starfive/clk-starfive-jh71x0.c | 12 ++++++++++++ drivers/clk/starfive/clk-starfive-jh71x0.h | 8 ++++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starf= ive/clk-starfive-jh71x0.c index bb7706ede1a6..1f98f1f8f0a5 100644 --- a/drivers/clk/starfive/clk-starfive-jh71x0.c +++ b/drivers/clk/starfive/clk-starfive-jh71x0.c @@ -302,6 +302,15 @@ static const struct clk_ops jh71x0_clk_inv_ops =3D { .debug_init =3D jh71x0_clk_debug_init, }; =20 +static const struct clk_ops jh71x0_clk_idiv_ops =3D { + .get_phase =3D jh71x0_clk_get_phase, + .set_phase =3D jh71x0_clk_set_phase, + .recalc_rate =3D jh71x0_clk_recalc_rate, + .determine_rate =3D jh71x0_clk_determine_rate, + .set_rate =3D jh71x0_clk_set_rate, + .debug_init =3D jh71x0_clk_debug_init, +}; + const struct clk_ops *starfive_jh71x0_clk_ops(u32 max) { if (max & JH71X0_CLK_DIV_MASK) { @@ -312,6 +321,9 @@ const struct clk_ops *starfive_jh71x0_clk_ops(u32 max) } if (max & JH71X0_CLK_ENABLE) return &jh71x0_clk_gdiv_ops; + else if (max & JH71X0_CLK_INVERT) + return &jh71x0_clk_idiv_ops; + if (max =3D=3D JH71X0_CLK_FRAC_MAX) return &jh71x0_clk_fdiv_ops; return &jh71x0_clk_div_ops; diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starf= ive/clk-starfive-jh71x0.h index 2a1f0fb4cbb1..4cb3c2ef9525 100644 --- a/drivers/clk/starfive/clk-starfive-jh71x0.h +++ b/drivers/clk/starfive/clk-starfive-jh71x0.h @@ -104,6 +104,14 @@ struct jh71x0_clk_data { .parents =3D { [0] =3D _parent }, \ } =20 +#define JH71X0_IDIV(_idx, _name, _flags, _max, _parent) \ +[_idx] =3D { \ + .name =3D _name, \ + .flags =3D _flags, \ + .max =3D JH71X0_CLK_INVERT | (_max), \ + .parents =3D { [0] =3D _parent }, \ +} + struct jh71x0_clk { struct clk_hw hw; unsigned int idx; --=20 2.25.1 From nobody Wed Sep 30 16:18:44 2026 Received: from CHN02-BJS-obe.outbound.protection.partner.outlook.cn (mail-bjschn02on2097.outbound.protection.partner.outlook.cn [139.219.17.97]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F8994E7814; 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R . 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charset="utf-8" Expand the storage of clock parent index for per0 domain, which parent index over 255. So change u8 to u16. Signed-off-by: Changhuang Liang Reviewed-by: Hal Feng --- drivers/clk/starfive/clk-starfive-jh71x0.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starf= ive/clk-starfive-jh71x0.h index 4cb3c2ef9525..198f6d005415 100644 --- a/drivers/clk/starfive/clk-starfive-jh71x0.h +++ b/drivers/clk/starfive/clk-starfive-jh71x0.h @@ -27,7 +27,7 @@ struct jh71x0_clk_data { const char *name; unsigned long flags; u32 max; - u8 parents[4]; + u16 parents[4]; }; =20 #define JH71X0_GATE(_idx, _name, _flags, _parent) \ --=20 2.25.1 From nobody Wed Sep 30 16:18:44 2026 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2129.outbound.protection.partner.outlook.cn [139.219.146.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 704444D8DAB; Wed, 30 Sep 2026 12:44:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=139.219.146.129 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790772275; cv=fail; b=OL4TliydKD0EJJdre7AhmfkbA9Ek6WlvhhZ/QAzK2TXNxpoT3my0zWXH/ClYS/I6cGowR5u/X+NX/tvMTlGvoO4qbG6SKipCxPrXSdd48iQ+Z8CucbrlDuYHBao81RHUetI2qzBH1CwBjFziOiaE2wLmucI/OAuvtlrSj+7odWc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790772275; c=relaxed/simple; bh=PxfG4geXJYLp8B2RtCzDFeTQYLGECcdqNVRWBmMOYzY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=FshxyaVivePaS95wOzX1hI6Zr2Korov59Pa+NE3Q3ucPZ+SCdRNY8/k4ccPzq3zr8f5iTnm0DkraJX8YmCTvwuzgNwo8t94X265urCbb26lyM0TGAiNiyW/chKyQPnWFnRgeuiHffSeOg9XQm6fJvx4YlhsrJDXdjC2R1l95T9E= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=starfivetech.com; spf=pass smtp.mailfrom=starfivetech.com; arc=fail smtp.client-ip=139.219.146.129 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=g2wFfL8XFSVM71x6aLQR6AIZ5ckEDB1CZyh6iOjFzJz/Nr5uEOOOk9zAHJCOretj3fIQ/p9fBn0JAtU6E/QjKKlXQ0GwN+2E7Mtjn5A2VFNL/As4HCbmWRFZ4sIpyfBQTyYqv6ZNO7n2CcpdNeblgAbseFTWXdQiIe75bvmDqLRrl04d4B+jI5WtPTc6rfyUDeXSsjaZch5mzZw4TjE5sXU0KLyiklYlsMBuB53dbTMKd82iQD5e1bXp8bdjqKhpSr3knXNEGnPTqvwAuJclnuNhldoGosSNhOE0pXfKQsboahyZl92COUxqemVnQOb/0vmyDiFfWsLa8f5rtQ9DXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=OCPQIWIlq1d4vEYoTv4OWOk2aIi6fdQ6zf6T9aKRYm0=; b=jyQS20UVhMMleizbl5HqWC14t7lNHHDmr1frqDHy/5oInP2qJyWslycmBN8rFJHccVfqGtCH8GVcFp59dJMxlbCSGd+/5tb3gwsfCciAzjuHNrxU1NTHa836x8ZE7+6wo3QvnpebYek/rTZZz/C213cj6tpZpZb1Y4xUiuihnbvNQffoZiT+AYfo2iX2r/9jjVrZRrZQkHvZd31Cr1VdlLn2tXkVLnTlb57R9TnDPZQq0zDY31L6HPSo61f/u0fADTUBlqEtwABbz2VjHdF6OfrgN23OH0QY//vK7U4WIMohEnvmqqVjcSxyWEbt91Euwiv8tw3vpPejQdyAQxq6/g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) by ZQ4PR01MB1267.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:16::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.16; Wed, 30 Sep 2026 12:43:57 +0000 Received: from ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn ([fe80::e7d4:256c:b066:850d]) by ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn ([fe80::e7d4:256c:b066:850d%4]) with mapi id 15.21.0451.026; Wed, 30 Sep 2026 12:43:57 +0000 From: Changhuang Liang To: Michael Turquette , Brian Masney , Jerome Brunet , Stephen Boyd , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Emil Renner Berthing , Kees Cook , "Gustavo A . R . Silva" , Richard Cochran Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-hardening@vger.kernel.org, netdev@vger.kernel.org, Hal Feng , Changhuang Liang Subject: [PATCH v5 14/23] clk: starfive: Add StarFive JHB100 Peripheral-0 clock driver Date: Wed, 30 Sep 2026 05:43:08 -0700 Message-Id: <20260930124317.5648-15-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260930124317.5648-1-changhuang.liang@starfivetech.com> References: <20260930124317.5648-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BJSPR01CA0006.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:c::18) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1267:EE_ X-MS-Office365-Filtering-Correlation-Id: c2334234-3971-45db-d412-08df1ef07e5e X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|52116014|23010399003|366016|1800799024|10067099003|56012099006|921020|3023799007|18002099003|22082099003|38350700014; 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charset="utf-8" Add driver for the StarFive JHB100 Peripheral-0 clock controller. Signed-off-by: Changhuang Liang --- drivers/clk/starfive/Kconfig | 10 + drivers/clk/starfive/Makefile | 1 + .../clk/starfive/clk-starfive-jhb100-per0.c | 599 ++++++++++++++++++ 3 files changed, 610 insertions(+) create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per0.c diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index cfaac934a8e0..b2a05bbb450f 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -73,6 +73,16 @@ config CLK_STARFIVE_JH7110_VOUT Say yes here to support the Video-Output clock controller on the StarFive JH7110 SoC. =20 +config CLK_STARFIVE_JHB100_PER0 + bool "StarFive JHB100 peripheral-0 clock support" + depends on ARCH_STARFIVE || COMPILE_TEST + select CLK_STARFIVE_JH71X0 + select RESET_STARFIVE_JHB100 if RESET_CONTROLLER + default ARCH_STARFIVE + help + Say yes here to support the peripheral-0 clock controller + on the StarFive JHB100 SoC. + config CLK_STARFIVE_JHB100_SYS0 bool "StarFive JHB100 system-0 clock support" depends on ARCH_STARFIVE || COMPILE_TEST diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index 29cdef20575e..352717886295 100644 --- a/drivers/clk/starfive/Makefile +++ b/drivers/clk/starfive/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) +=3D clk-starfive-j= h7110-stg.o obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) +=3D clk-starfive-jh7110-isp.o obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) +=3D clk-starfive-jh7110-vout.o =20 +obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0) +=3D clk-starfive-jhb100-per0.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) +=3D clk-starfive-jhb100-sys0.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) +=3D clk-starfive-jhb100-sys1.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) +=3D clk-starfive-jhb100-sys2.o diff --git a/drivers/clk/starfive/clk-starfive-jhb100-per0.c b/drivers/clk/= starfive/clk-starfive-jhb100-per0.c new file mode 100644 index 000000000000..801501046669 --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jhb100-per0.c @@ -0,0 +1,599 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JHB100 Peripheral-0 Clock Driver + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * + * Author: Changhuang Liang + * + */ + +#include +#include + +#include "clk-starfive-jh71x0.h" + +#define JHB100_PER0CLK_NUM_CLKS (JHB100_PER0CLK_MAIN_ICG_EN_TRNG + 1) + +/* external clocks */ +#define JHB100_PER0CLK_OSC (JHB100_PER0CLK_NUM_CLKS + 0) +#define JHB100_PER0CLK_PLL6 (JHB100_PER0CLK_NUM_CLKS + 1) +#define JHB100_PER0CLK_CFG_400 (JHB100_PER0CLK_NUM_CLKS + 2) +#define JHB100_PER0CLK_CFG_800 (JHB100_PER0CLK_NUM_CLKS + 3) +#define JHB100_PER0CLK_NCNOC_INIT (JHB100_PER0CLK_NUM_CLKS + 4) +#define JHB100_PER0CLK_NCNOC_TARG (JHB100_PER0CLK_NUM_CLKS + 5) + +static const char * const jhb100_per0_ext_clk[] =3D { + "osc", + "pll6", + "cfg_400", + "cfg_800", + "ncnoc_init", + "ncnoc_targ", +}; + +static const struct jh71x0_clk_data jhb100_per0crg_clk_data[] =3D { + JH71X0_GATE(JHB100_PER0CLK_CDR_I3C0, "cdr_i3c0", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_CFG_800), + JH71X0_GATE(JHB100_PER0CLK_CDR_I3C1, "cdr_i3c1", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_CFG_800), + JH71X0_GATE(JHB100_PER0CLK_CDR_I3C2, "cdr_i3c2", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_CFG_800), + JH71X0_GATE(JHB100_PER0CLK_CDR_I3C3, "cdr_i3c3", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_CFG_800), + JH71X0_GATE(JHB100_PER0CLK_CDR_I3C4, "cdr_i3c4", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_CFG_800), + JH71X0_GATE(JHB100_PER0CLK_CDR_I3C5, "cdr_i3c5", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_CFG_800), + JH71X0_GATE(JHB100_PER0CLK_CDR_I3C6, "cdr_i3c6", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_CFG_800), + JH71X0_GATE(JHB100_PER0CLK_CDR_I3C7, "cdr_i3c7", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_CFG_800), + JH71X0_GATE(JHB100_PER0CLK_CDR_I3C8, "cdr_i3c8", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_CFG_800), + JH71X0_GATE(JHB100_PER0CLK_CDR_I3C9, "cdr_i3c9", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_CFG_800), + JH71X0_GATE(JHB100_PER0CLK_CDR_I3C10, "cdr_i3c10", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_CFG_800), + JH71X0_GATE(JHB100_PER0CLK_CDR_I3C11, "cdr_i3c11", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_CFG_800), + JH71X0_GATE(JHB100_PER0CLK_CDR_I3C12, "cdr_i3c12", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_CFG_800), + JH71X0_GATE(JHB100_PER0CLK_CDR_I3C13, "cdr_i3c13", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_CFG_800), + JH71X0_GATE(JHB100_PER0CLK_CDR_I3C14, "cdr_i3c14", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_CFG_800), + JH71X0_GATE(JHB100_PER0CLK_CDR_I3C15, "cdr_i3c15", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_CFG_800), + JH71X0__DIV(JHB100_PER0CLK_200, "per0_200", 3, + JHB100_PER0CLK_NCNOC_INIT), + JH71X0__DIV(JHB100_PER0CLK_600_DIV6, "per0_600_div6", 6, + JHB100_PER0CLK_NCNOC_INIT), + JH71X0__DIV(JHB100_PER0CLK_600_DIV6_DIV5, "per0_600_div6_div5", 5, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_TIMER0_DUALTIMER0, "timer0_dualtimer0", 0, + JHB100_PER0CLK_600_DIV6_DIV5), + JH71X0_GATE(JHB100_PER0CLK_TIMER1_DUALTIMER0, "timer1_dualtimer0", 0, + JHB100_PER0CLK_600_DIV6_DIV5), + JH71X0_GATE(JHB100_PER0CLK_TIMER0_DUALTIMER1, "timer0_dualtimer1", 0, + JHB100_PER0CLK_600_DIV6_DIV5), + JH71X0_GATE(JHB100_PER0CLK_TIMER1_DUALTIMER1, "timer1_dualtimer1", 0, + JHB100_PER0CLK_600_DIV6_DIV5), + JH71X0_GATE(JHB100_PER0CLK_TIMER0_DUALTIMER2, "timer0_dualtimer2", 0, + JHB100_PER0CLK_600_DIV6_DIV5), + JH71X0_GATE(JHB100_PER0CLK_TIMER1_DUALTIMER2, "timer1_dualtimer2", 0, + JHB100_PER0CLK_600_DIV6_DIV5), + JH71X0__DIV(JHB100_PER0CLK_1200_PH0_LVDS0, "1200_ph0_lvds0", 2, + JHB100_PER0CLK_PH0_LTPI0), + JH71X0__DIV(JHB100_PER0CLK_1200_PH0_LVDS1, "1200_ph0_lvds1", 2, + JHB100_PER0CLK_PH0_LTPI1), + JH71X0__DIV(JHB100_PER0CLK_1200_CORE0, "1200_core0", 2, + JHB100_PER0CLK_PLL6), + JH71X0__DIV(JHB100_PER0CLK_1200_CORE1, "1200_core1", 2, + JHB100_PER0CLK_PLL6), + JH71X0__DIV(JHB100_PER0CLK_1200_SHIFT90_LVDS0, "1200_shift90_lvds0", 2, + JHB100_PER0CLK_PH90_LTPI0), + JH71X0__DIV(JHB100_PER0CLK_1200_SHIFT90_LVDS1, "1200_shift90_lvds1", 2, + JHB100_PER0CLK_PH90_LTPI1), + JH71X0__DIV(JHB100_PER0CLK_1200_DIV5_CORE0, "1200_div5_core0", 5, + JHB100_PER0CLK_1200_CORE0), + JH71X0__DIV(JHB100_PER0CLK_1200_DIV5_CORE1, "1200_div5_core1", 5, + JHB100_PER0CLK_1200_CORE1), + JH71X0__DIV(JHB100_PER0CLK_PH0_LTPI0, "ph0_ltpi0", 48, + JHB100_PER0CLK_PLL6), + JH71X0__DIV(JHB100_PER0CLK_PH0_LTPI1, "ph0_ltpi1", 48, + JHB100_PER0CLK_PLL6), + JH71X0_IDIV(JHB100_PER0CLK_PH90_LTPI0, "ph90_ltpi0", 0, 48, + JHB100_PER0CLK_PLL6), + JH71X0_IDIV(JHB100_PER0CLK_PH90_LTPI1, "ph90_ltpi1", 0, 48, + JHB100_PER0CLK_PLL6), + JH71X0__DIV(JHB100_PER0CLK_240_CORE_LTPI0, "240_core_ltpi0", 4, + JHB100_PER0CLK_1200_DIV5_CORE0), + JH71X0__DIV(JHB100_PER0CLK_240_CORE_LTPI1, "240_core_ltpi1", 4, + JHB100_PER0CLK_1200_DIV5_CORE1), + JH71X0_GATE(JHB100_PER0CLK_AXI_DMA_I2C_INIT, "axi_dma_i2c_init", CLK_IGNO= RE_UNUSED, + JHB100_PER0CLK_CFG_400), + JH71X0_GATE(JHB100_PER0CLK_AXI_DMA_I3C_INIT, "axi_dma_i3c_init", CLK_IGNO= RE_UNUSED, + JHB100_PER0CLK_CFG_400), + JH71X0_GATE(JHB100_PER0CLK_AXI_DMA_UART_INIT, "axi_dma_uart_init", CLK_IG= NORE_UNUSED, + JHB100_PER0CLK_CFG_400), + JH71X0_GATE(JHB100_PER0CLK_CORE_DMAC0, "core_dmac0", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER0CLK_CORE_DMAC1, "core_dmac1", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER0CLK_CORE_DMAC2, "core_dmac2", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER0CLK_HDR_TX_I3C0, "hdr_tx_i3c0", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_HDR_TX_I3C1, "hdr_tx_i3c1", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_HDR_TX_I3C2, "hdr_tx_i3c2", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_HDR_TX_I3C3, "hdr_tx_i3c3", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_HDR_TX_I3C4, "hdr_tx_i3c4", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_HDR_TX_I3C5, "hdr_tx_i3c5", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_HDR_TX_I3C6, "hdr_tx_i3c6", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_HDR_TX_I3C7, "hdr_tx_i3c7", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_HDR_TX_I3C8, "hdr_tx_i3c8", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_HDR_TX_I3C9, "hdr_tx_i3c9", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_HDR_TX_I3C10, "hdr_tx_i3c10", CLK_IGNORE_UNUSE= D, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_HDR_TX_I3C11, "hdr_tx_i3c11", CLK_IGNORE_UNUSE= D, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_HDR_TX_I3C12, "hdr_tx_i3c12", CLK_IGNORE_UNUSE= D, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_HDR_TX_I3C13, "hdr_tx_i3c13", CLK_IGNORE_UNUSE= D, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_HDR_TX_I3C14, "hdr_tx_i3c14", CLK_IGNORE_UNUSE= D, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_HDR_TX_I3C15, "hdr_tx_i3c15", CLK_IGNORE_UNUSE= D, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_CORE_I2C0, "core_i2c0", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_CORE_I2C1, "core_i2c1", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_CORE_I2C2, "core_i2c2", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_CORE_I2C3, "core_i2c3", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_CORE_I2C4, "core_i2c4", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_CORE_I2C5, "core_i2c5", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_CORE_I2C6, "core_i2c6", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_CORE_I2C7, "core_i2c7", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_CORE_I2C8, "core_i2c8", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_CORE_I2C9, "core_i2c9", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_CORE_I2C10, "core_i2c10", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_CORE_I2C11, "core_i2c11", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_CORE_I2C12, "core_i2c12", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_CORE_I2C13, "core_i2c13", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_CORE_I2C14, "core_i2c14", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_CORE_I2C15, "core_i2c15", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_WDOGCLK_WDT0, "wdogclk_wdt0", CLK_IGNORE_UNUSE= D, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_WDOGCLK_WDT1, "wdogclk_wdt1", CLK_IGNORE_UNUSE= D, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_WDOGCLK_WDT2, "wdogclk_wdt2", CLK_IGNORE_UNUSE= D, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_WDOGCLK_WDT3, "wdogclk_wdt3", CLK_IGNORE_UNUSE= D, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_WDOGCLK_WDT_EXTERNAL, "wdogclk_wdt_external", + CLK_IGNORE_UNUSED, JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_SCLK_UART4, "sclk_uart4", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_SCLK_UART5, "sclk_uart5", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_SCLK_UART6, "sclk_uart6", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_SCLK_UART7, "sclk_uart7", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_SCLK_UART8, "sclk_uart8", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_SCLK_UART9, "sclk_uart9", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_SCLK_UART10, "sclk_uart10", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_SCLK_UART11, "sclk_uart11", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_SCLK_UART12, "sclk_uart12", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_SCLK_UART13, "sclk_uart13", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_SCLK_UART14, "sclk_uart14", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_PCLK_DMA_UART_CFG, "pclk_dma_uart_cfg", CLK_IG= NORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_PCLK_DMA_I2C_CFG, "pclk_dma_i2c_cfg", CLK_IGNO= RE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_PCLK_DMA_I3C_CFG, "pclk_dma_i3c_cfg", CLK_IGNO= RE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_PCLK_DUALTIMER0, "pclk_dualtimer0", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_PCLK_DUALTIMER1, "pclk_dualtimer1", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_PCLK_DUALTIMER2, "pclk_dualtimer2", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_HCLK_TRNG, "hclk_trng", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER0CLK_APB_I2C0, "apb_i2c0", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2C1, "apb_i2c1", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2C2, "apb_i2c2", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2C3, "apb_i2c3", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2C4, "apb_i2c4", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2C5, "apb_i2c5", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2C6, "apb_i2c6", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2C7, "apb_i2c7", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2C8, "apb_i2c8", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2C9, "apb_i2c9", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2C10, "apb_i2c10", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2C11, "apb_i2c11", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2C12, "apb_i2c12", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2C13, "apb_i2c13", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2C14, "apb_i2c14", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2C15, "apb_i2c15", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2CF0, "apb_i2cf0", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2CF1, "apb_i2cf1", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2CF2, "apb_i2cf2", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2CF3, "apb_i2cf3", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2CF4, "apb_i2cf4", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2CF5, "apb_i2cf5", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2CF6, "apb_i2cf6", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2CF7, "apb_i2cf7", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2CF8, "apb_i2cf8", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2CF9, "apb_i2cf9", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2CF10, "apb_i2cf10", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2CF11, "apb_i2cf11", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2CF12, "apb_i2cf12", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2CF13, "apb_i2cf13", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2CF14, "apb_i2cf14", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I2CF15, "apb_i2cf15", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I3C0, "apb_i3c0", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I3C1, "apb_i3c1", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I3C2, "apb_i3c2", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I3C3, "apb_i3c3", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I3C4, "apb_i3c4", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I3C5, "apb_i3c5", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I3C6, "apb_i3c6", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I3C7, "apb_i3c7", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I3C8, "apb_i3c8", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I3C9, "apb_i3c9", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I3C10, "apb_i3c10", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I3C11, "apb_i3c11", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I3C12, "apb_i3c12", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I3C13, "apb_i3c13", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I3C14, "apb_i3c14", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_I3C15, "apb_i3c15", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_UART0, "apb_uart0", CLK_IS_CRITICAL, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_UART1, "apb_uart1", CLK_IS_CRITICAL, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_UART2, "apb_uart2", CLK_IS_CRITICAL, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_UART3, "apb_uart3", CLK_IS_CRITICAL, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_UART4, "apb_uart4", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_UART5, "apb_uart5", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_UART6, "apb_uart6", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_UART7, "apb_uart7", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_UART8, "apb_uart8", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_UART9, "apb_uart9", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_UART10, "apb_uart10", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_UART11, "apb_uart11", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_UART12, "apb_uart12", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_UART13, "apb_uart13", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_APB_UART14, "apb_uart14", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_DMA_I3C0, "dma_i3c0", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_DMA_I3C1, "dma_i3c1", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_DMA_I3C2, "dma_i3c2", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_DMA_I3C3, "dma_i3c3", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_DMA_I3C4, "dma_i3c4", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_DMA_I3C5, "dma_i3c5", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_DMA_I3C6, "dma_i3c6", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_DMA_I3C7, "dma_i3c7", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_DMA_I3C8, "dma_i3c8", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_DMA_I3C9, "dma_i3c9", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_DMA_I3C10, "dma_i3c10", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_DMA_I3C11, "dma_i3c11", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_DMA_I3C12, "dma_i3c12", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_DMA_I3C13, "dma_i3c13", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_DMA_I3C14, "dma_i3c14", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_DMA_I3C15, "dma_i3c15", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_CORE_I3C0, "core_i3c0", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_CORE_I3C1, "core_i3c1", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_CORE_I3C2, "core_i3c2", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_CORE_I3C3, "core_i3c3", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_CORE_I3C4, "core_i3c4", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_CORE_I3C5, "core_i3c5", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_CORE_I3C6, "core_i3c6", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_CORE_I3C7, "core_i3c7", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_CORE_I3C8, "core_i3c8", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_CORE_I3C9, "core_i3c9", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_CORE_I3C10, "core_i3c10", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_CORE_I3C11, "core_i3c11", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_CORE_I3C12, "core_i3c12", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_CORE_I3C13, "core_i3c13", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_CORE_I3C14, "core_i3c14", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_CORE_I3C15, "core_i3c15", CLK_IGNORE_UNUSED, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_DMAC_AXI_PERIPH0_HS_CLK_I2C, "dmac_axi_periph0= _hs_clk_i2c", + CLK_IGNORE_UNUSED, JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C0, "main_icg_en_i3c0", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C1, "main_icg_en_i3c1", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C2, "main_icg_en_i3c2", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C3, "main_icg_en_i3c3", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C4, "main_icg_en_i3c4", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C5, "main_icg_en_i3c5", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C6, "main_icg_en_i3c6", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C7, "main_icg_en_i3c7", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C8, "main_icg_en_i3c8", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C9, "main_icg_en_i3c9", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C10, "main_icg_en_i3c10", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C11, "main_icg_en_i3c11", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C12, "main_icg_en_i3c12", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C13, "main_icg_en_i3c13", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C14, "main_icg_en_i3c14", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C15, "main_icg_en_i3c15", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_DUALTIMER0, "main_icg_en_dualtimer= 0", + CLK_IS_CRITICAL, JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_DUALTIMER1, "main_icg_en_dualtimer= 1", + CLK_IS_CRITICAL, JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_DUALTIMER2, "main_icg_en_dualtimer= 2", + CLK_IS_CRITICAL, JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_LTPI0, "main_icg_en_ltpi0", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_LTPI1, "main_icg_en_ltpi1", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_DMAC_I2C, "main_icg_en_dmac_i2c", + CLK_IS_CRITICAL, JHB100_PER0CLK_CFG_400), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_DMAC_I3C, "main_icg_en_dmac_i3c", + CLK_IS_CRITICAL, JHB100_PER0CLK_CFG_400), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_DMAC_UART, "main_icg_en_dmac_uart", + CLK_IS_CRITICAL, JHB100_PER0CLK_CFG_400), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL4, "main_icg_en_sol4", 0, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL5, "main_icg_en_sol5", 0, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL6, "main_icg_en_sol6", 0, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL7, "main_icg_en_sol7", 0, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL8, "main_icg_en_sol8", 0, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL9, "main_icg_en_sol9", 0, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL10, "main_icg_en_sol10", 0, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL11, "main_icg_en_sol11", 0, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL12, "main_icg_en_sol12", 0, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL13, "main_icg_en_sol13", 0, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL14, "main_icg_en_sol14", 0, + JHB100_PER0CLK_200), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C0, "main_icg_en_i2c0", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C1, "main_icg_en_i2c1", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C2, "main_icg_en_i2c2", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C3, "main_icg_en_i2c3", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C4, "main_icg_en_i2c4", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C5, "main_icg_en_i2c5", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C6, "main_icg_en_i2c6", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C7, "main_icg_en_i2c7", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C8, "main_icg_en_i2c8", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C9, "main_icg_en_i2c9", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C10, "main_icg_en_i2c10", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C11, "main_icg_en_i2c11", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C12, "main_icg_en_i2c12", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C13, "main_icg_en_i2c13", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C14, "main_icg_en_i2c14", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C15, "main_icg_en_i2c15", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_WDT0, "main_icg_en_wdt0", 0, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_WDT1, "main_icg_en_wdt1", 0, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_WDT2, "main_icg_en_wdt2", 0, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_WDT3, "main_icg_en_wdt3", 0, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_WDT_EXTERNAL, "main_icg_en_wdt_ext= ernal", 0, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART4, "main_icg_en_uart4", CLK_IS= _CRITICAL, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART5, "main_icg_en_uart5", CLK_IS= _CRITICAL, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART6, "main_icg_en_uart6", CLK_IS= _CRITICAL, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART7, "main_icg_en_uart7", CLK_IS= _CRITICAL, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART8, "main_icg_en_uart8", CLK_IS= _CRITICAL, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART9, "main_icg_en_uart9", CLK_IS= _CRITICAL, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART10, "main_icg_en_uart10", CLK_= IS_CRITICAL, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART11, "main_icg_en_uart11", CLK_= IS_CRITICAL, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART12, "main_icg_en_uart12", CLK_= IS_CRITICAL, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART13, "main_icg_en_uart13", CLK_= IS_CRITICAL, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART14, "main_icg_en_uart14", CLK_= IS_CRITICAL, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_LDO0, "main_icg_en_ldo0", 0, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_LDO1, "main_icg_en_ldo1", 0, + JHB100_PER0CLK_OSC), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SENSORS_PERIPH0, "main_icg_en_sens= ors_periph0", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SENSORS_DMAC, "main_icg_en_sensors= _dmac", 0, + JHB100_PER0CLK_600_DIV6), + JH71X0_GATE(JHB100_PER0CLK_MAIN_ICG_EN_TRNG, "main_icg_en_trng", 0, + JHB100_PER0CLK_NCNOC_TARG), +}; + +static const struct jh71x0_crg_domain_info jhb100_per0crg_info =3D { + .clk_data =3D jhb100_per0crg_clk_data, + .num_clk =3D ARRAY_SIZE(jhb100_per0crg_clk_data), + .ext_clk =3D jhb100_per0_ext_clk, + .num_ext_clk =3D ARRAY_SIZE(jhb100_per0_ext_clk), + .rst_name =3D "jhb100-r-per0", + .power_domain =3D false, +}; + +static const struct of_device_id jhb100_per0crg_match[] =3D { + { + .compatible =3D "starfive,jhb100-per0crg", + .data =3D &jhb100_per0crg_info, + }, + { /* sentinel */ } +}; + +static struct platform_driver jhb100_per0crg_driver =3D { + .probe =3D jh71x0_crg_probe, + .driver =3D { + .name =3D "clk-starfive-jhb100-per0", + .of_match_table =3D jhb100_per0crg_match, + .suppress_bind_attrs =3D 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R . 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charset="utf-8" Add bindings for the Peripheral-1 clock and reset generator (PER1CRG) on the JHB100 RISC-V SoC by StarFive Ltd. Signed-off-by: Changhuang Liang Reviewed-by: Rob Herring (Arm) --- .../clock/starfive,jhb100-per1crg.yaml | 70 +++++++++++++++++++ .../dt-bindings/clock/starfive,jhb100-crg.h | 60 ++++++++++++++++ .../dt-bindings/reset/starfive,jhb100-crg.h | 19 +++++ 3 files changed, 149 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100= -per1crg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-per1cr= g.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.ya= ml new file mode 100644 index 000000000000..c72a355ceb34 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jhb100-per1crg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 Peripheral-1 Clock and Reset Generator + +maintainers: + - Changhuang Liang + +properties: + compatible: + const: starfive,jhb100-per1crg + + reg: + maxItems: 1 + + clocks: + items: + - description: PLL7 + - description: Non Coherent NOC Initiator + - description: Configure 800MHz + - description: Non Coherent NOC Target + - description: Configure 143MHz + + clock-names: + items: + - const: pll7 + - const: ncnoc_init + - const: cfg_800 + - const: ncnoc_targ + - const: cfg_143 + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@11b40000 { + compatible =3D "starfive,jhb100-per1crg"; + reg =3D <0x11b40000 0x1000>; + clocks =3D <&pll7>, + <&sys0crg 68>, + <&sys0crg 69>, + <&sys2crg 19>, + <&sys2crg 22>; + clock-names =3D "pll7", "ncnoc_init", + "cfg_800", "ncnoc_targ", + "cfg_143"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-b= indings/clock/starfive,jhb100-crg.h index add2cd093dbd..7f508574177c 100644 --- a/include/dt-bindings/clock/starfive,jhb100-crg.h +++ b/include/dt-bindings/clock/starfive,jhb100-crg.h @@ -387,4 +387,64 @@ #define JHB100_PER0CLK_MAIN_ICG_EN_SENSORS_DMAC 339 #define JHB100_PER0CLK_MAIN_ICG_EN_TRNG 340 =20 +/* PER1CRG clocks */ +#define JHB100_PER1CLK_100 0 +#define JHB100_PER1CLK_1 1 +#define JHB100_PER1CLK_200_DIVN0 2 +#define JHB100_PER1CLK_200_DIVN1 3 +#define JHB100_PER1CLK_200_DIVN2 4 +#define JHB100_PER1CLK_200_DIVN3 5 +#define JHB100_PER1CLK_200_CCLK_DIV 6 + +#define JHB100_PER1CLK_SGPIO0_PCLK 15 +#define JHB100_PER1CLK_SGPIO0_DCLK 16 +#define JHB100_PER1CLK_SGPIO1_PCLK 17 +#define JHB100_PER1CLK_SGPIO1_DCLK 18 + +#define JHB100_PER1CLK_EMMC0_BCLK 22 + +#define JHB100_PER1CLK_EMMC0_CCLK 25 + +#define JHB100_PER1CLK_DMAC1_1CH_CORE 29 + +#define JHB100_PER1CLK_DMAC1_1CH_ACLK 31 + +#define JHB100_PER1CLK_DMAC2_1CH_CORE 33 + +#define JHB100_PER1CLK_DMAC2_1CH_ACLK 35 + +#define JHB100_PER1CLK_DMAC3_1CH_CORE 37 + +#define JHB100_PER1CLK_DMAC3_1CH_ACLK 39 + +#define JHB100_PER1CLK_DMAC0_2CH_CORE 41 + +#define JHB100_PER1CLK_DMAC0_2CH_ACLK 43 + +#define JHB100_PER1CLK_UFS_REF 45 +#define JHB100_PER1CLK_UFS_300 46 +#define JHB100_PER1CLK_UFS_150 47 +#define JHB100_PER1CLK_UFS_400 48 +#define JHB100_PER1CLK_UFS_75 49 +#define JHB100_PER1CLK_UFS_37_5 50 +#define JHB100_PER1CLK_UFS_7_5 51 +#define JHB100_PER1CLK_UFS_1_875 52 +#define JHB100_PER1CLK_UFS_7_143 53 +#define JHB100_PER1CLK_UFS_3_5715 54 + +#define JHB100_PER1CLK_MAIN_ICG_EN_SFC0 63 +#define JHB100_PER1CLK_MAIN_ICG_EN_SFC1 64 +#define JHB100_PER1CLK_MAIN_ICG_EN_SFC2 65 +#define JHB100_PER1CLK_MAIN_ICG_EN_SPI0 66 +#define JHB100_PER1CLK_MAIN_ICG_EN_SGPIO0 67 +#define JHB100_PER1CLK_MAIN_ICG_EN_SGPIO1 68 +#define JHB100_PER1CLK_MAIN_ICG_EN_SENSORS_PERIPH1 69 +#define JHB100_PER1CLK_MAIN_ICG_EN_EMMC0 70 +#define JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC0 71 +#define JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC1 72 +#define JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC2 73 +#define JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SPI0 74 +#define JHB100_PER1CLK_MAIN_ICG_EN_RAS 75 +#define JHB100_PER1CLK_MAIN_ICG_EN_UFS 76 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-b= indings/reset/starfive,jhb100-crg.h index ccfb7616e1a7..cf933a1befbb 100644 --- a/include/dt-bindings/reset/starfive,jhb100-crg.h +++ b/include/dt-bindings/reset/starfive,jhb100-crg.h @@ -138,4 +138,23 @@ #define JHB100_PER0RST_GPIO_IOMUX_PRESETN 73 #define JHB100_PER0RST_UART_MUX_REG_WRAP 74 =20 +/* PER1CRG resets */ +#define JHB100_PER1RST_IOMUX_PRESETN 0 +#define JHB100_PER1RST_SYSCON_PRESETN 1 +#define JHB100_PER1RST_MAIN_RSTN_SFC0 2 +#define JHB100_PER1RST_MAIN_RSTN_SFC1 3 +#define JHB100_PER1RST_MAIN_RSTN_SFC2 4 +#define JHB100_PER1RST_MAIN_RSTN_SPI0 5 +#define JHB100_PER1RST_MAIN_RSTN_PERIPH1_SENSORS 6 +#define JHB100_PER1RST_MAIN_RSTN_SGPIO0 7 +#define JHB100_PER1RST_MAIN_RSTN_SGPIO1 8 +#define JHB100_PER1RST_MAIN_RSTN_EMMC0 9 +#define JHB100_PER1RST_MAIN_RSTN_UFS 10 +#define JHB100_PER1RST_MAIN_RSTN_UFS_PHY 11 +#define JHB100_PER1RST_MAIN_RSTN_DMAC_SFC0 12 +#define JHB100_PER1RST_MAIN_RSTN_DMAC_SFC1 13 +#define JHB100_PER1RST_MAIN_RSTN_DMAC_SFC2 14 +#define JHB100_PER1RST_MAIN_RSTN_DMAC_SPI0 15 +#define JHB100_PER1RST_MAIN_RSTN_PERIPH1_RAS 16 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */ --=20 2.25.1 From nobody Wed Sep 30 16:18:44 2026 Received: from CHN02-BJS-obe.outbound.protection.partner.outlook.cn (mail-bjschn02on2103.outbound.protection.partner.outlook.cn [139.219.17.103]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49AA74F3ED6; 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R . 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charset="utf-8" Add driver for the StarFive JHB100 Peripheral-1 clock controller. Signed-off-by: Changhuang Liang --- drivers/clk/starfive/Kconfig | 10 ++ drivers/clk/starfive/Makefile | 1 + .../clk/starfive/clk-starfive-jhb100-per1.c | 149 ++++++++++++++++++ 3 files changed, 160 insertions(+) create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per1.c diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index b2a05bbb450f..62727ce3aef3 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -83,6 +83,16 @@ config CLK_STARFIVE_JHB100_PER0 Say yes here to support the peripheral-0 clock controller on the StarFive JHB100 SoC. =20 +config CLK_STARFIVE_JHB100_PER1 + bool "StarFive JHB100 peripheral-1 clock support" + depends on ARCH_STARFIVE || COMPILE_TEST + select CLK_STARFIVE_JH71X0 + select RESET_STARFIVE_JHB100 if RESET_CONTROLLER + default ARCH_STARFIVE + help + Say yes here to support the peripheral-1 clock controller + on the StarFive JHB100 SoC. + config CLK_STARFIVE_JHB100_SYS0 bool "StarFive JHB100 system-0 clock support" depends on ARCH_STARFIVE || COMPILE_TEST diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index 352717886295..279e0cdfc99b 100644 --- a/drivers/clk/starfive/Makefile +++ b/drivers/clk/starfive/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) +=3D clk-starfive-j= h7110-isp.o obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) +=3D clk-starfive-jh7110-vout.o =20 obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0) +=3D clk-starfive-jhb100-per0.o +obj-$(CONFIG_CLK_STARFIVE_JHB100_PER1) +=3D clk-starfive-jhb100-per1.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) +=3D clk-starfive-jhb100-sys0.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) +=3D clk-starfive-jhb100-sys1.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) +=3D clk-starfive-jhb100-sys2.o diff --git a/drivers/clk/starfive/clk-starfive-jhb100-per1.c b/drivers/clk/= starfive/clk-starfive-jhb100-per1.c new file mode 100644 index 000000000000..82a7255da729 --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jhb100-per1.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JHB100 Peripheral-1 Clock Driver + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * + * Author: Changhuang Liang + * + */ + +#include +#include + +#include "clk-starfive-jh71x0.h" + +#define JHB100_PER1CLK_NUM_CLKS (JHB100_PER1CLK_MAIN_ICG_EN_UFS + 1) + +/* external clocks */ +#define JHB100_PER1CLK_PLL7 (JHB100_PER1CLK_NUM_CLKS + 0) +#define JHB100_PER1CLK_NCNOC_INIT (JHB100_PER1CLK_NUM_CLKS + 1) +#define JHB100_PER1CLK_CFG_800 (JHB100_PER1CLK_NUM_CLKS + 2) +#define JHB100_PER1CLK_NCNOC_TARG (JHB100_PER1CLK_NUM_CLKS + 3) +#define JHB100_PER1CLK_CFG_143 (JHB100_PER1CLK_NUM_CLKS + 4) + +static const char * const jhb100_per1_ext_clk[] =3D { + "pll7", + "ncnoc_init", + "cfg_800", + "ncnoc_targ", + "cfg_143", +}; + +static const struct jh71x0_clk_data jhb100_per1crg_clk_data[] =3D { + JH71X0__DIV(JHB100_PER1CLK_100, "per1_100", 8, JHB100_PER1CLK_NCNOC_INIT), + JH71X0__DIV(JHB100_PER1CLK_1, "per1_1", 100, JHB100_PER1CLK_100), + JH71X0__DIV(JHB100_PER1CLK_200_DIVN0, "200_divn0", 256, + JHB100_PER1CLK_CFG_800), + JH71X0__DIV(JHB100_PER1CLK_200_DIVN1, "200_divn1", 256, + JHB100_PER1CLK_CFG_800), + JH71X0__DIV(JHB100_PER1CLK_200_DIVN2, "200_divn2", 256, + JHB100_PER1CLK_CFG_800), + JH71X0__DIV(JHB100_PER1CLK_200_DIVN3, "200_divn3", 256, + JHB100_PER1CLK_CFG_800), + JH71X0__DIV(JHB100_PER1CLK_200_CCLK_DIV, "200_cclk_div", 2046, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_SGPIO0_PCLK, "sgpio0_pclk", CLK_IGNORE_UNUSED, + JHB100_PER1CLK_100), + JH71X0_GATE(JHB100_PER1CLK_SGPIO0_DCLK, "sgpio0_dclk", CLK_IGNORE_UNUSED, + JHB100_PER1CLK_100), + JH71X0_GATE(JHB100_PER1CLK_SGPIO1_PCLK, "sgpio1_pclk", CLK_IGNORE_UNUSED, + JHB100_PER1CLK_100), + JH71X0_GATE(JHB100_PER1CLK_SGPIO1_DCLK, "sgpio1_dclk", CLK_IGNORE_UNUSED, + JHB100_PER1CLK_100), + JH71X0_GATE(JHB100_PER1CLK_EMMC0_BCLK, "emmc0_bclk", CLK_IGNORE_UNUSED, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_EMMC0_CCLK, "emmc0_cclk", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_DMAC1_1CH_CORE, "dmac1_1ch_core", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_DMAC1_1CH_ACLK, "dmac1_1ch_aclk", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_DMAC2_1CH_CORE, "dmac2_1ch_core", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_DMAC2_1CH_ACLK, "dmac2_1ch_aclk", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_DMAC3_1CH_CORE, "dmac3_1ch_core", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_DMAC3_1CH_ACLK, "dmac3_1ch_aclk", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_DMAC0_2CH_CORE, "dmac0_2ch_core", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_DMAC0_2CH_ACLK, "dmac0_2ch_aclk", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0__DIV(JHB100_PER1CLK_UFS_REF, "ufs_ref", 75, + JHB100_PER1CLK_PLL7), + JH71X0__DIV(JHB100_PER1CLK_UFS_300, "ufs_300", 2, + JHB100_PER1CLK_NCNOC_INIT), + JH71X0__DIV(JHB100_PER1CLK_UFS_150, "ufs_150", 12, + JHB100_PER1CLK_NCNOC_INIT), + JH71X0__DIV(JHB100_PER1CLK_UFS_400, "ufs_400", 2, + JHB100_PER1CLK_CFG_800), + JH71X0__DIV(JHB100_PER1CLK_UFS_75, "ufs_75", 2, + JHB100_PER1CLK_UFS_150), + JH71X0__DIV(JHB100_PER1CLK_UFS_37_5, "ufs_37_5", 2, + JHB100_PER1CLK_UFS_75), + JH71X0__DIV(JHB100_PER1CLK_UFS_7_5, "ufs_7_5", 10, + JHB100_PER1CLK_UFS_75), + JH71X0__DIV(JHB100_PER1CLK_UFS_1_875, "ufs_1_875", 4, + JHB100_PER1CLK_UFS_7_5), + JH71X0__DIV(JHB100_PER1CLK_UFS_7_143, "ufs_7_143", 20, + JHB100_PER1CLK_CFG_143), + JH71X0__DIV(JHB100_PER1CLK_UFS_3_5715, "ufs_3_5715", 2, + JHB100_PER1CLK_UFS_7_143), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SFC0, "main_icg_en_sfc0", CLK_IS_C= RITICAL, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SFC1, "main_icg_en_sfc1", CLK_IS_C= RITICAL, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SFC2, "main_icg_en_sfc2", CLK_IS_C= RITICAL, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SPI0, "main_icg_en_spi0", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_EMMC0, "main_icg_en_emmc0", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SGPIO0, "main_icg_en_sgpio0", 0, + JHB100_PER1CLK_100), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SGPIO1, "main_icg_en_sgpio1", 0, + JHB100_PER1CLK_100), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SENSORS_PERIPH1, "main_icg_en_sens= ors_periph1", 0, + JHB100_PER1CLK_100), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC0, "main_icg_en_dmac_sfc0", + CLK_IS_CRITICAL, JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC1, "main_icg_en_dmac_sfc1", + CLK_IS_CRITICAL, JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC2, "main_icg_en_dmac_sfc2", + CLK_IS_CRITICAL, JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SPI0, "main_icg_en_dmac_spi0", + CLK_IS_CRITICAL, JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_RAS, "main_icg_en_ras", 0, + JHB100_PER1CLK_100), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_UFS, "main_icg_en_ufs", 0, + JHB100_PER1CLK_100), +}; + +static const struct jh71x0_crg_domain_info jhb100_per1crg_info =3D { + .clk_data =3D jhb100_per1crg_clk_data, + .num_clk =3D ARRAY_SIZE(jhb100_per1crg_clk_data), + .ext_clk =3D jhb100_per1_ext_clk, + .num_ext_clk =3D ARRAY_SIZE(jhb100_per1_ext_clk), + .rst_name =3D "jhb100-r-per1", + .power_domain =3D false, +}; + +static const struct of_device_id jhb100_per1crg_match[] =3D { + { + .compatible =3D "starfive,jhb100-per1crg", + .data =3D &jhb100_per1crg_info, + }, + { /* sentinel */ } +}; + +static struct platform_driver jhb100_per1crg_driver =3D { + .probe =3D jh71x0_crg_probe, + .driver =3D { + .name =3D "clk-starfive-jhb100-per1", + .of_match_table =3D jhb100_per1crg_match, + .suppress_bind_attrs =3D true, + }, +}; +builtin_platform_driver(jhb100_per1crg_driver); --=20 2.25.1 From nobody Wed Sep 30 16:18:44 2026 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2129.outbound.protection.partner.outlook.cn [139.219.146.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1B7D4F55A7; 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Silva" , Richard Cochran Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-hardening@vger.kernel.org, netdev@vger.kernel.org, Hal Feng , Changhuang Liang Subject: [PATCH v5 17/23] dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator Date: Wed, 30 Sep 2026 05:43:11 -0700 Message-Id: <20260930124317.5648-18-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260930124317.5648-1-changhuang.liang@starfivetech.com> References: <20260930124317.5648-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BJSPR01CA0006.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:c::18) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1267:EE_ X-MS-Office365-Filtering-Correlation-Id: 0f27ee5e-21a7-4530-c68e-08df1ef08168 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|52116014|23010399003|366016|1800799024|10067099003|56012099006|921020|3023799007|18002099003|22082099003|38350700014; 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charset="utf-8" Add bindings for the Peripheral-2 clock and reset generator (PER2CRG) on the JHB100 RISC-V SoC by StarFive Ltd. Signed-off-by: Changhuang Liang Reviewed-by: Krzysztof Kozlowski --- .../clock/starfive,jhb100-per2crg.yaml | 76 +++++++++++++++++++ .../dt-bindings/clock/starfive,jhb100-crg.h | 57 ++++++++++++++ .../dt-bindings/reset/starfive,jhb100-crg.h | 17 +++++ 3 files changed, 150 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100= -per2crg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-per2cr= g.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-per2crg.ya= ml new file mode 100644 index 000000000000..175654645221 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-per2crg.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jhb100-per2crg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 Peripheral-2 Clock and Reset Generator + +maintainers: + - Changhuang Liang + +properties: + compatible: + const: starfive,jhb100-per2crg + + reg: + maxItems: 1 + + clocks: + items: + - description: Non Coherent NOC Initiator + - description: Configure 400MHz + - description: Configure 125MHz + - description: GMAC2 RGMII RX + - description: GMAC2 RMII Reference + - description: GMAC3 SGMII TX + - description: GMAC3 SGMII RX + - description: Main Oscillator (25 MHz) + + clock-names: + items: + - const: ncnoc_init + - const: cfg_400 + - const: cfg_125 + - const: gmac2_rgmii_rx + - const: gmac2_rmii_ref + - const: gmac3_sgmii_tx + - const: gmac3_sgmii_rx + - const: osc + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@11bc0000 { + compatible =3D "starfive,jhb100-per2crg"; + reg =3D <0x11bc0000 0x1000>; + clocks =3D <&sys0crg 52>, <&sys0crg 54>, <&sys0crg 55>, + <&per2_gmac2_rgmii_rx>, <&per2_gmac2_rmii_ref>, + <&per2_gmac3_sgmii_tx>, <&per2_gmac3_sgmii_rx>, + <&osc>; + clock-names =3D "ncnoc_init", "cfg_400", "cfg_125", + "gmac2_rgmii_rx", "gmac2_rmii_ref", + "gmac3_sgmii_tx", "gmac3_sgmii_rx", + "osc"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-b= indings/clock/starfive,jhb100-crg.h index 7f508574177c..2b2e148ce5ce 100644 --- a/include/dt-bindings/clock/starfive,jhb100-crg.h +++ b/include/dt-bindings/clock/starfive,jhb100-crg.h @@ -447,4 +447,61 @@ #define JHB100_PER1CLK_MAIN_ICG_EN_RAS 75 #define JHB100_PER1CLK_MAIN_ICG_EN_UFS 76 =20 +/* PER2CRG clocks */ +#define JHB100_PER2CLK_300 0 +#define JHB100_PER2CLK_100 1 +#define JHB100_PER2CLK_50 2 +#define JHB100_PER2CLK_GMAC2_RMII_50 3 +#define JHB100_PER2CLK_CAN0_CORE_DIV 4 +#define JHB100_PER2CLK_CAN1_CORE_DIV 5 +#define JHB100_PER2CLK_CAN0_TIMER 6 +#define JHB100_PER2CLK_CAN1_TIMER 7 + +#define JHB100_PER2CLK_RTC_CORE_DIV 11 +#define JHB100_PER2CLK_GMAC2_RMII_MUX_DLY 12 +#define JHB100_PER2CLK_GMAC2_RMII_DIV 13 + +#define JHB100_PER2CLK_GMAC2_RGMII_125_MUX 15 +#define JHB100_PER2CLK_GMAC2_RGMII_DIV 16 +#define JHB100_PER2CLK_GMAC2_TX_MUX 17 +#define JHB100_PER2CLK_GMAC2_TX_180_BUF 18 +#define JHB100_PER2CLK_GMAC2_RX_MUX_DLY 19 +#define JHB100_PER2CLK_GMAC2_RX_180_BUF 20 +#define JHB100_PER2CLK_GMAC2_TXCK_MUX_DLY 21 +#define JHB100_PER2CLK_GMAC3_TX_125_MUX 22 +#define JHB100_PER2CLK_GMAC3_RX_125_MUX 23 +#define JHB100_PER2CLK_GMAC3_TX_DIV 24 +#define JHB100_PER2CLK_GMAC3_RX_DIV 25 +#define JHB100_PER2CLK_SENSORS_PERIPH2 26 + +#define JHB100_PER2CLK_FAN_TACH_PCLK 33 + +#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_TX_I 44 +#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RX_I 45 +#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_TX_180_I 46 +#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RX_180_I 47 +#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_PTP_REF_I 48 +#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RMII_I 49 +#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_CSR_I 50 +#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_ACLK_I 51 +#define JHB100_PER2CLK_RMIIANDRGMII_IOMUX_GMAC2_TXCK 52 +#define JHB100_PER2CLK_ETHER1_SGMII_TX_I 53 +#define JHB100_PER2CLK_ETHER1_SGMII_RX_I 54 +#define JHB100_PER2CLK_ETHER1_SGMII_TX_125_I 55 +#define JHB100_PER2CLK_ETHER1_SGMII_RX_125_I 56 +#define JHB100_PER2CLK_ETHER1_SGMII_PTP_REF_I 57 +#define JHB100_PER2CLK_ETHER1_SGMII_CSR_I 58 +#define JHB100_PER2CLK_ETHER1_SGMII_ACLK_I 59 +#define JHB100_PER2CLK_ETHER1_SGMII_PHY_PCLK_I 60 +#define JHB100_PER2CLK_ETHER1_SGMII_REF_25_I 61 +#define JHB100_PER2CLK_MAIN_ICG_EN_CAN0 62 +#define JHB100_PER2CLK_MAIN_ICG_EN_CAN1 63 + +#define JHB100_PER2CLK_MAIN_ICG_EN_DMAC_8CH 65 +#define JHB100_PER2CLK_MAIN_ICG_EN_RTC_SCAN 66 +#define JHB100_PER2CLK_MAIN_ICG_EN_ADC0 67 +#define JHB100_PER2CLK_MAIN_ICG_EN_ADC1 68 +#define JHB100_PER2CLK_MAIN_ICG_EN_GMAC2 69 +#define JHB100_PER2CLK_MAIN_ICG_EN_GMAC3 70 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-b= indings/reset/starfive,jhb100-crg.h index cf933a1befbb..0965f3798397 100644 --- a/include/dt-bindings/reset/starfive,jhb100-crg.h +++ b/include/dt-bindings/reset/starfive,jhb100-crg.h @@ -157,4 +157,21 @@ #define JHB100_PER1RST_MAIN_RSTN_DMAC_SPI0 15 #define JHB100_PER1RST_MAIN_RSTN_PERIPH1_RAS 16 =20 +/* PER2CRG resets */ +#define JHB100_PER2RST_IOMUX_PRESETN 0 +#define JHB100_PER2RST_POK_IOMUX_PRESETN 1 +#define JHB100_PER2RST_SYSREG_RSTN 2 +#define JHB100_PER2RST_MAIN_RSTN_CAN0 3 +#define JHB100_PER2RST_MAIN_RSTN_CAN1 4 +#define JHB100_PER2RST_FAN_TACH_PRESETN 5 +#define JHB100_PER2RST_MAIN_RSTN_GMAC2 6 +#define JHB100_PER2RST_MAIN_RSTN_GMAC3 7 +#define JHB100_PER2RST_MAIN_RSTN_DMAC_8CH 8 +#define JHB100_PER2RST_MAIN_RSTN_RTC 9 +#define JHB100_PER2RST_ADC0_PRESETN 10 +#define JHB100_PER2RST_ADC0_IOMUX_PRESETN 11 +#define JHB100_PER2RST_ADC1_PRESETN 12 +#define JHB100_PER2RST_ADC1_IOMUX_PRESETN 13 +#define JHB100_PER2RST_MAIN_RSTN_PERIPH2_SENSORS 14 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */ --=20 2.25.1 From nobody Wed Sep 30 16:18:44 2026 Received: from CHN02-BJS-obe.outbound.protection.partner.outlook.cn (mail-bjschn02on2103.outbound.protection.partner.outlook.cn [139.219.17.103]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 595454E4304; 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Silva" , Richard Cochran Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-hardening@vger.kernel.org, netdev@vger.kernel.org, Hal Feng , Changhuang Liang Subject: [PATCH v5 18/23] clk: starfive: Add StarFive JHB100 Peripheral-2 clock driver Date: Wed, 30 Sep 2026 05:43:12 -0700 Message-Id: <20260930124317.5648-19-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260930124317.5648-1-changhuang.liang@starfivetech.com> References: <20260930124317.5648-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BJSPR01CA0006.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:c::18) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1267:EE_ X-MS-Office365-Filtering-Correlation-Id: b0b88075-df6c-423a-3411-08df1ef0826a X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|52116014|23010399003|366016|1800799024|10067099003|56012099006|921020|18002099003|22082099003|38350700014; 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charset="utf-8" Add driver for the StarFive JHB100 Peripheral-2 clock controller. Signed-off-by: Changhuang Liang --- drivers/clk/starfive/Kconfig | 10 + drivers/clk/starfive/Makefile | 1 + .../clk/starfive/clk-starfive-jhb100-per2.c | 174 ++++++++++++++++++ 3 files changed, 185 insertions(+) create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per2.c diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index 62727ce3aef3..57a3838475e9 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -93,6 +93,16 @@ config CLK_STARFIVE_JHB100_PER1 Say yes here to support the peripheral-1 clock controller on the StarFive JHB100 SoC. =20 +config CLK_STARFIVE_JHB100_PER2 + bool "StarFive JHB100 peripheral-2 clock support" + depends on ARCH_STARFIVE || COMPILE_TEST + select CLK_STARFIVE_JH71X0 + select RESET_STARFIVE_JHB100 if RESET_CONTROLLER + default ARCH_STARFIVE + help + Say yes here to support the peripheral-2 clock controller + on the StarFive JHB100 SoC. + config CLK_STARFIVE_JHB100_SYS0 bool "StarFive JHB100 system-0 clock support" depends on ARCH_STARFIVE || COMPILE_TEST diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index 279e0cdfc99b..ca9347d38023 100644 --- a/drivers/clk/starfive/Makefile +++ b/drivers/clk/starfive/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) +=3D clk-starfive-= jh7110-vout.o =20 obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0) +=3D clk-starfive-jhb100-per0.o obj-$(CONFIG_CLK_STARFIVE_JHB100_PER1) +=3D clk-starfive-jhb100-per1.o +obj-$(CONFIG_CLK_STARFIVE_JHB100_PER2) +=3D clk-starfive-jhb100-per2.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) +=3D clk-starfive-jhb100-sys0.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) +=3D clk-starfive-jhb100-sys1.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) +=3D clk-starfive-jhb100-sys2.o diff --git a/drivers/clk/starfive/clk-starfive-jhb100-per2.c b/drivers/clk/= starfive/clk-starfive-jhb100-per2.c new file mode 100644 index 000000000000..7c4af95a3fc9 --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jhb100-per2.c @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JHB100 Peripheral-2 Clock Driver + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * + * Author: Changhuang Liang + * + */ + +#include +#include + +#include "clk-starfive-jh71x0.h" + +#define JHB100_PER2CLK_NUM_CLKS (JHB100_PER2CLK_MAIN_ICG_EN_GMAC3 + 1) + +/* external clocks */ +#define JHB100_PER2CLK_NCNOC_INIT (JHB100_PER2CLK_NUM_CLKS + 0) +#define JHB100_PER2CLK_CFG_400 (JHB100_PER2CLK_NUM_CLKS + 1) +#define JHB100_PER2CLK_CFG_125 (JHB100_PER2CLK_NUM_CLKS + 2) +#define JHB100_PER2CLK_GMAC2_RGMII_RX (JHB100_PER2CLK_NUM_CLKS + 3) +#define JHB100_PER2CLK_GMAC2_RMII_REF (JHB100_PER2CLK_NUM_CLKS + 4) +#define JHB100_PER2CLK_GMAC3_SGMII_TX (JHB100_PER2CLK_NUM_CLKS + 5) +#define JHB100_PER2CLK_GMAC3_SGMII_RX (JHB100_PER2CLK_NUM_CLKS + 6) +#define JHB100_PER2CLK_OSC (JHB100_PER2CLK_NUM_CLKS + 7) + +static const char * const jhb100_per2_ext_clk[] =3D { + "ncnoc_init", + "cfg_400", + "cfg_125", + "gmac2_rgmii_rx", + "gmac2_rmii_ref", + "gmac3_sgmii_tx", + "gmac3_sgmii_rx", + "osc", +}; + +static const struct jh71x0_clk_data jhb100_per2crg_clk_data[] =3D { + JH71X0__DIV(JHB100_PER2CLK_300, "per2_300", 2, + JHB100_PER2CLK_NCNOC_INIT), + JH71X0__DIV(JHB100_PER2CLK_100, "per2_100", 4, + JHB100_PER2CLK_CFG_400), + JH71X0__DIV(JHB100_PER2CLK_50, "per2_50", 2, + JHB100_PER2CLK_100), + JH71X0__DIV(JHB100_PER2CLK_GMAC2_RMII_50, "gmac2_rmii_50", 2, + JHB100_PER2CLK_100), + JH71X0__DIV(JHB100_PER2CLK_CAN0_CORE_DIV, "can0_core_div", 20, + JHB100_PER2CLK_CFG_400), + JH71X0__DIV(JHB100_PER2CLK_CAN1_CORE_DIV, "can1_core_div", 20, + JHB100_PER2CLK_CFG_400), + JH71X0__DIV(JHB100_PER2CLK_CAN0_TIMER, "can0_timer", 100, + JHB100_PER2CLK_100), + JH71X0__DIV(JHB100_PER2CLK_CAN1_TIMER, "can1_timer", 100, + JHB100_PER2CLK_100), + JH71X0__DIV(JHB100_PER2CLK_RTC_CORE_DIV, "rtc_core_div", 763, + JHB100_PER2CLK_OSC), + JH71X0__MUX(JHB100_PER2CLK_GMAC2_RMII_MUX_DLY, "gmac2_rmii_mux_dly", 0, 2, + JHB100_PER2CLK_GMAC2_RMII_REF, + JHB100_PER2CLK_GMAC2_RMII_50), + JH71X0__DIV(JHB100_PER2CLK_GMAC2_RMII_DIV, "gmac2_rmii_div", 20, + JHB100_PER2CLK_GMAC2_RMII_MUX_DLY), + JH71X0__MUX(JHB100_PER2CLK_GMAC2_RGMII_125_MUX, "gmac2_rgmii_125_mux", 0,= 2, + JHB100_PER2CLK_GMAC2_RGMII_RX, + JHB100_PER2CLK_CFG_125), + JH71X0__DIV(JHB100_PER2CLK_GMAC2_RGMII_DIV, "gmac2_rgmii_div", 50, + JHB100_PER2CLK_CFG_125), + JH71X0__MUX(JHB100_PER2CLK_GMAC2_TX_MUX, "gmac2_tx_mux", 0, 2, + JHB100_PER2CLK_GMAC2_RMII_DIV, + JHB100_PER2CLK_GMAC2_RGMII_DIV), + JH71X0__INV(JHB100_PER2CLK_GMAC2_TX_180_BUF, "gmac2_tx_180_buf", + JHB100_PER2CLK_GMAC2_TX_MUX), + JH71X0__MUX(JHB100_PER2CLK_GMAC2_RX_MUX_DLY, "gmac2_rx_mux_dly", 0, 2, + JHB100_PER2CLK_GMAC2_RMII_DIV, + JHB100_PER2CLK_GMAC2_RGMII_125_MUX), + JH71X0__INV(JHB100_PER2CLK_GMAC2_RX_180_BUF, "gmac2_rx_180_buf", + JHB100_PER2CLK_GMAC2_RX_MUX_DLY), + JH71X0__MUX(JHB100_PER2CLK_GMAC2_TXCK_MUX_DLY, "gmac2_txck_mux_dly", 0, 2, + JHB100_PER2CLK_GMAC2_RMII_50, + JHB100_PER2CLK_GMAC2_TX_MUX), + JH71X0__MUX(JHB100_PER2CLK_GMAC3_TX_125_MUX, "gmac3_tx_125_mux", 0, 2, + JHB100_PER2CLK_GMAC3_SGMII_TX, + JHB100_PER2CLK_CFG_125), + JH71X0__MUX(JHB100_PER2CLK_GMAC3_RX_125_MUX, "gmac3_rx_125_mux", 0, 2, + JHB100_PER2CLK_GMAC3_SGMII_RX, + JHB100_PER2CLK_CFG_125), + JH71X0__DIV(JHB100_PER2CLK_GMAC3_TX_DIV, "gmac3_tx_div", 50, + JHB100_PER2CLK_GMAC3_TX_125_MUX), + JH71X0__DIV(JHB100_PER2CLK_GMAC3_RX_DIV, "gmac3_rx_div", 50, + JHB100_PER2CLK_GMAC3_RX_125_MUX), + JH71X0_GATE(JHB100_PER2CLK_SENSORS_PERIPH2, "sensors_periph2", 0, + JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_FAN_TACH_PCLK, "fan_tach_pclk", 0, + JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_TX_I, "ether0_rmiiandrgmii= _tx_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_TX_MUX), + JH71X0_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RX_I, "ether0_rmiiandrgmii= _rx_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_RX_MUX_DLY), + JH71X0_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_TX_180_I, "ether0_rmiiandr= gmii_tx_180_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_TX_180_BUF), + JH71X0_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RX_180_I, "ether0_rmiiandr= gmii_rx_180_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_RX_180_BUF), + JH71X0_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_PTP_REF_I, "ether0_rmiiand= rgmii_ptp_ref_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_50), + JH71X0_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RMII_I, "ether0_rmiiandrgm= ii_rmii_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_RMII_MUX_DLY), + JH71X0_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_CSR_I, "ether0_rmiiandrgmi= i_csr_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_ACLK_I, "ether0_rmiiandrgm= ii_aclk_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_300), + JH71X0_GATE(JHB100_PER2CLK_RMIIANDRGMII_IOMUX_GMAC2_TXCK, "rmiiandrgmii_i= omux_gmac2_txck", + CLK_IS_CRITICAL, JHB100_PER2CLK_GMAC2_TXCK_MUX_DLY), + JH71X0_GATE(JHB100_PER2CLK_ETHER1_SGMII_TX_I, "ether1_sgmii_tx_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC3_TX_DIV), + JH71X0_GATE(JHB100_PER2CLK_ETHER1_SGMII_RX_I, "ether1_sgmii_rx_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC3_RX_DIV), + JH71X0_GATE(JHB100_PER2CLK_ETHER1_SGMII_TX_125_I, "ether1_sgmii_tx_125_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC3_TX_125_MUX), + JH71X0_GATE(JHB100_PER2CLK_ETHER1_SGMII_RX_125_I, "ether1_sgmii_rx_125_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC3_RX_125_MUX), + JH71X0_GATE(JHB100_PER2CLK_ETHER1_SGMII_PTP_REF_I, "ether1_sgmii_ptp_ref_= i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_50), + JH71X0_GATE(JHB100_PER2CLK_ETHER1_SGMII_CSR_I, "ether1_sgmii_csr_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_ETHER1_SGMII_ACLK_I, "ether1_sgmii_aclk_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_300), + JH71X0_GATE(JHB100_PER2CLK_ETHER1_SGMII_PHY_PCLK_I, "ether1_sgmii_phy_pcl= k_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_ETHER1_SGMII_REF_25_I, "ether1_sgmii_ref_25_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_OSC), + JH71X0_GATE(JHB100_PER2CLK_MAIN_ICG_EN_CAN0, "main_icg_en_can0", 0, + JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_MAIN_ICG_EN_CAN1, "main_icg_en_can1", 0, + JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_MAIN_ICG_EN_DMAC_8CH, "main_icg_en_dmac_8ch", = 0, + JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_MAIN_ICG_EN_RTC_SCAN, "main_icg_en_rtc_scan", = CLK_IS_CRITICAL, + JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_MAIN_ICG_EN_ADC0, "main_icg_en_adc0", 0, + JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_MAIN_ICG_EN_ADC1, "main_icg_en_adc1", 0, + JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_MAIN_ICG_EN_GMAC2, "main_icg_en_gmac2", 0, + JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_MAIN_ICG_EN_GMAC3, "main_icg_en_gmac3", 0, + JHB100_PER2CLK_100), +}; + +static const struct jh71x0_crg_domain_info jhb100_per2crg_info =3D { + .clk_data =3D jhb100_per2crg_clk_data, + .num_clk =3D ARRAY_SIZE(jhb100_per2crg_clk_data), + .ext_clk =3D jhb100_per2_ext_clk, + .num_ext_clk =3D ARRAY_SIZE(jhb100_per2_ext_clk), + .rst_name =3D "jhb100-r-per2", + .power_domain =3D false, +}; + +static const struct of_device_id jhb100_per2crg_match[] =3D { + { + .compatible =3D "starfive,jhb100-per2crg", + .data =3D &jhb100_per2crg_info, + }, + { /* sentinel */ } +}; + +static struct platform_driver jhb100_per2crg_driver =3D { + .probe =3D jh71x0_crg_probe, + .driver =3D { + .name =3D "clk-starfive-jhb100-per2", + .of_match_table =3D jhb100_per2crg_match, + .suppress_bind_attrs =3D true, + }, +}; +builtin_platform_driver(jhb100_per2crg_driver); --=20 2.25.1 From nobody Wed Sep 30 16:18:44 2026 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2129.outbound.protection.partner.outlook.cn [139.219.146.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by 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R . 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charset="utf-8" Add bindings for the Peripheral-3 clock and reset generator (PER3CRG) on the JHB100 RISC-V SoC by StarFive Ltd. Signed-off-by: Changhuang Liang Reviewed-by: Rob Herring (Arm) --- .../clock/starfive,jhb100-per3crg.yaml | 76 +++++++++++++++++++ .../dt-bindings/clock/starfive,jhb100-crg.h | 35 +++++++++ .../dt-bindings/reset/starfive,jhb100-crg.h | 9 +++ 3 files changed, 120 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100= -per3crg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-per3cr= g.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-per3crg.ya= ml new file mode 100644 index 000000000000..2c3b9f4146b5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-per3crg.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jhb100-per3crg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 Peripheral-3 Clock and Reset Generator + +maintainers: + - Changhuang Liang + +properties: + compatible: + const: starfive,jhb100-per3crg + + reg: + maxItems: 1 + + clocks: + items: + - description: Non Coherent NOC Initiator + - description: Non Coherent NOC Target + - description: Configure 125MHz + - description: GMAC0 RMII Reference clock + - description: GMAC1 SGMII TX + - description: GMAC1 SGMII RX + - description: Main Oscillator (25 MHz) + + clock-names: + items: + - const: ncnoc_init + - const: ncnoc_targ + - const: cfg_125 + - const: gmac0_rmii_rclki + - const: gmac1_sgmii_tx + - const: gmac1_sgmii_rx + - const: osc + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@11c40000 { + compatible =3D "starfive,jhb100-per3crg"; + reg =3D <0x11c40000 0x1000>; + clocks =3D <&sys0crg 65>, + <&sys1crg 18>, + <&sys1crg 19>, + <&per3_gmac0_rmii_rclki>, + <&per3_gmac1_sgmii_tx>, + <&per3_gmac1_sgmii_rx>, + <&osc>; + clock-names =3D "ncnoc_init", "ncnoc_targ", "cfg_125", + "gmac0_rmii_rclki", "gmac1_sgmii_tx", + "gmac1_sgmii_rx", "osc"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-b= indings/clock/starfive,jhb100-crg.h index 2b2e148ce5ce..bdf7d628b381 100644 --- a/include/dt-bindings/clock/starfive,jhb100-crg.h +++ b/include/dt-bindings/clock/starfive,jhb100-crg.h @@ -504,4 +504,39 @@ #define JHB100_PER2CLK_MAIN_ICG_EN_GMAC2 69 #define JHB100_PER2CLK_MAIN_ICG_EN_GMAC3 70 =20 +/* PER3CRG clocks */ +#define JHB100_PER3CLK_300 0 +#define JHB100_PER3CLK_200 1 +#define JHB100_PER3CLK_GMAC1_PTP_REF 2 +#define JHB100_PER3CLK_GMAC1_TX_125_MUX 3 +#define JHB100_PER3CLK_GMAC1_TX 4 +#define JHB100_PER3CLK_GMAC1_RX_125_MUX 5 +#define JHB100_PER3CLK_GMAC1_RX 6 +#define JHB100_PER3CLK_GMAC0_PTP_REF 7 +#define JHB100_PER3CLK_GMAC0_RMII_PLL 8 +#define JHB100_PER3CLK_GMAC0_RMII_MUX 9 +#define JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2 10 + +#define JHB100_PER3CLK_ETHER0_RMII_CLK_TX_I 17 +#define JHB100_PER3CLK_ETHER0_RMII_CLK_RX_I 18 +#define JHB100_PER3CLK_ETHER0_RMII_CLK_PTP_REF_I 19 +#define JHB100_PER3CLK_ETHER0_RMII_CLK_RMII_I 20 +#define JHB100_PER3CLK_ETHER0_RMII_CLK_CSR_I 21 +#define JHB100_PER3CLK_ETHER0_RMII_ACLK_I 22 +#define JHB100_PER3CLK_GMAC0_RMII_RCLKO 23 +#define JHB100_PER3CLK_ETHER0_SGMII_CLK_TX_I 24 +#define JHB100_PER3CLK_ETHER0_SGMII_CLK_RX_I 25 +#define JHB100_PER3CLK_ETHER0_SGMII_CLK_TX_125_I 26 +#define JHB100_PER3CLK_ETHER0_SGMII_CLK_RX_125_I 27 +#define JHB100_PER3CLK_ETHER0_SGMII_CLK_PTP_REF_I 28 +#define JHB100_PER3CLK_ETHER0_SGMII_CLK_REF_25_I 29 +#define JHB100_PER3CLK_ETHER0_SGMII_CLK_CSR_I 30 +#define JHB100_PER3CLK_ETHER0_SGMII_ACLK_I 31 +#define JHB100_PER3CLK_ETHER0_SGMII_PHY_PCLK_I 32 +#define JHB100_PER3CLK_MAIN_ICG_EN_SENSORS_PERIPH3 33 +#define JHB100_PER3CLK_MAIN_ICG_EN_PECI0 34 +#define JHB100_PER3CLK_MAIN_ICG_EN_PECI1 35 +#define JHB100_PER3CLK_MAIN_ICG_EN_GMAC0 36 +#define JHB100_PER3CLK_MAIN_ICG_EN_GMAC1 37 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-b= indings/reset/starfive,jhb100-crg.h index 0965f3798397..872a4dd25beb 100644 --- a/include/dt-bindings/reset/starfive,jhb100-crg.h +++ b/include/dt-bindings/reset/starfive,jhb100-crg.h @@ -174,4 +174,13 @@ #define JHB100_PER2RST_ADC1_IOMUX_PRESETN 13 #define JHB100_PER2RST_MAIN_RSTN_PERIPH2_SENSORS 14 =20 +/* PER3CRG resets */ +#define JHB100_PER3RST_SYSREG_RSTN 0 +#define JHB100_PER3RST_MAIN_RSTN_GMAC0 1 +#define JHB100_PER3RST_MAIN_RSTN_GMAC1 2 +#define JHB100_PER3RST_MAIN_RSTN_PECI0 3 +#define JHB100_PER3RST_MAIN_RSTN_PECI1 4 +#define JHB100_PER3RST_MAIN_RSTN_PERIPH3_SENSORS 5 +#define JHB100_PER3RST_IOMUX_PRESETN 6 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */ --=20 2.25.1 From nobody Wed Sep 30 16:18:44 2026 Received: from CHN02-BJS-obe.outbound.protection.partner.outlook.cn (mail-bjschn02on2103.outbound.protection.partner.outlook.cn [139.219.17.103]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B926E4D8D97; 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charset="utf-8" Add driver for the StarFive JHB100 Peripheral-3 clock controller. Signed-off-by: Changhuang Liang --- drivers/clk/starfive/Kconfig | 10 ++ drivers/clk/starfive/Makefile | 1 + .../clk/starfive/clk-starfive-jhb100-per3.c | 132 ++++++++++++++++++ 3 files changed, 143 insertions(+) create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per3.c diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index 57a3838475e9..1c9dd5d47cb8 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -103,6 +103,16 @@ config CLK_STARFIVE_JHB100_PER2 Say yes here to support the peripheral-2 clock controller on the StarFive JHB100 SoC. =20 +config CLK_STARFIVE_JHB100_PER3 + bool "StarFive JHB100 peripheral-3 clock support" + depends on ARCH_STARFIVE || COMPILE_TEST + select CLK_STARFIVE_JH71X0 + select RESET_STARFIVE_JHB100 if RESET_CONTROLLER + default ARCH_STARFIVE + help + Say yes here to support the peripheral-3 clock controller + on the StarFive JHB100 SoC. + config CLK_STARFIVE_JHB100_SYS0 bool "StarFive JHB100 system-0 clock support" depends on ARCH_STARFIVE || COMPILE_TEST diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index ca9347d38023..2c4554c2e70e 100644 --- a/drivers/clk/starfive/Makefile +++ b/drivers/clk/starfive/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) +=3D clk-starfive-= jh7110-vout.o obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0) +=3D clk-starfive-jhb100-per0.o obj-$(CONFIG_CLK_STARFIVE_JHB100_PER1) +=3D clk-starfive-jhb100-per1.o obj-$(CONFIG_CLK_STARFIVE_JHB100_PER2) +=3D clk-starfive-jhb100-per2.o +obj-$(CONFIG_CLK_STARFIVE_JHB100_PER3) +=3D clk-starfive-jhb100-per3.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) +=3D clk-starfive-jhb100-sys0.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) +=3D clk-starfive-jhb100-sys1.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) +=3D clk-starfive-jhb100-sys2.o diff --git a/drivers/clk/starfive/clk-starfive-jhb100-per3.c b/drivers/clk/= starfive/clk-starfive-jhb100-per3.c new file mode 100644 index 000000000000..e5688c6efb50 --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jhb100-per3.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JHB100 Peripheral-3 Clock Driver + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * + * Author: Changhuang Liang + * + */ + +#include +#include + +#include "clk-starfive-jh71x0.h" + +#define JHB100_PER3CLK_NUM_CLKS (JHB100_PER3CLK_MAIN_ICG_EN_GMAC1 + 1) + +/* external clocks */ +#define JHB100_PER3CLK_NCNOC_INIT (JHB100_PER3CLK_NUM_CLKS + 0) +#define JHB100_PER3CLK_NCNOC_TARG (JHB100_PER3CLK_NUM_CLKS + 1) +#define JHB100_PER3CLK_CFG_125 (JHB100_PER3CLK_NUM_CLKS + 2) +#define JHB100_PER3CLK_GMAC0_RMII_RCLKI (JHB100_PER3CLK_NUM_CLKS + 3) +#define JHB100_PER3CLK_GMAC1_SGMII_TX (JHB100_PER3CLK_NUM_CLKS + 4) +#define JHB100_PER3CLK_GMAC1_SGMII_RX (JHB100_PER3CLK_NUM_CLKS + 5) +#define JHB100_PER3CLK_OSC (JHB100_PER3CLK_NUM_CLKS + 6) + +static const char * const jhb100_per3_ext_clk[] =3D { + "ncnoc_init", + "ncnoc_targ", + "cfg_125", + "gmac0_rmii_rclki", + "gmac1_sgmii_tx", + "gmac1_sgmii_rx", + "osc", +}; + +static const struct jh71x0_clk_data jhb100_per3crg_clk_data[] =3D { + JH71X0__DIV(JHB100_PER3CLK_300, "per3_300", 256, + JHB100_PER3CLK_NCNOC_INIT), + JH71X0__DIV(JHB100_PER3CLK_200, "per3_200", 256, + JHB100_PER3CLK_NCNOC_INIT), + JH71X0__DIV(JHB100_PER3CLK_GMAC1_PTP_REF, "gmac1_ptp_ref", 2, + JHB100_PER3CLK_NCNOC_TARG), + JH71X0__MUX(JHB100_PER3CLK_GMAC1_TX_125_MUX, "gmac1_tx_125_mux", 0, 2, + JHB100_PER3CLK_GMAC1_SGMII_TX, + JHB100_PER3CLK_CFG_125), + JH71X0__DIV(JHB100_PER3CLK_GMAC1_TX, "gmac1_tx", 50, + JHB100_PER3CLK_GMAC1_TX_125_MUX), + JH71X0__MUX(JHB100_PER3CLK_GMAC1_RX_125_MUX, "gmac1_rx_125_mux", 0, 2, + JHB100_PER3CLK_GMAC1_SGMII_RX, + JHB100_PER3CLK_CFG_125), + JH71X0__DIV(JHB100_PER3CLK_GMAC1_RX, "gmac1_rx", 50, + JHB100_PER3CLK_GMAC1_RX_125_MUX), + JH71X0__DIV(JHB100_PER3CLK_GMAC0_PTP_REF, "gmac0_ptp_ref", 2, + JHB100_PER3CLK_NCNOC_TARG), + JH71X0__DIV(JHB100_PER3CLK_GMAC0_RMII_PLL, "gmac0_rmii_pll", 2, + JHB100_PER3CLK_NCNOC_TARG), + JH71X0__MUX(JHB100_PER3CLK_GMAC0_RMII_MUX, "gmac0_rmii_mux", 0, 2, + JHB100_PER3CLK_GMAC0_RMII_PLL, + JHB100_PER3CLK_GMAC0_RMII_RCLKI), + JH71X0__DIV(JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2, "gmac0_rmii_mux_div2", 20, + JHB100_PER3CLK_GMAC0_RMII_MUX), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_TX_I, "ether0_rmii_clk_tx_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_RX_I, "ether0_rmii_clk_rx_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_PTP_REF_I, "ether0_rmii_clk_pt= p_ref_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_PTP_REF), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_RMII_I, "ether0_rmii_clk_rmii_= i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_MUX), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_CSR_I, "ether0_rmii_clk_csr_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_RMII_ACLK_I, "ether0_rmii_aclk_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_300), + JH71X0_GATE(JHB100_PER3CLK_GMAC0_RMII_RCLKO, "gmac0_rmii_rclko", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_PLL), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_TX_I, "ether0_sgmii_clk_tx_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_TX), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_RX_I, "ether0_sgmii_clk_rx_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_RX), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_TX_125_I, "ether0_sgmii_clk_t= x_125_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_TX_125_MUX), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_RX_125_I, "ether0_sgmii_clk_r= x_125_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_RX_125_MUX), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_PTP_REF_I, "ether0_sgmii_clk_= ptp_ref_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_PTP_REF), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_REF_25_I, "ether0_sgmii_clk_r= ef_25_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_OSC), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_CSR_I, "ether0_sgmii_clk_csr_= i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_SGMII_ACLK_I, "ether0_sgmii_aclk_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_300), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_SGMII_PHY_PCLK_I, "ether0_sgmii_phy_pcl= k_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER3CLK_MAIN_ICG_EN_SENSORS_PERIPH3, "main_icg_en_sens= ors_periph3", 0, + JHB100_PER3CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER3CLK_MAIN_ICG_EN_PECI0, "main_icg_en_peci0", 0, + JHB100_PER3CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER3CLK_MAIN_ICG_EN_PECI1, "main_icg_en_peci1", 0, + JHB100_PER3CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER3CLK_MAIN_ICG_EN_GMAC0, "main_icg_en_gmac0", + CLK_IS_CRITICAL, JHB100_PER3CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER3CLK_MAIN_ICG_EN_GMAC1, "main_icg_en_gmac1", + CLK_IS_CRITICAL, JHB100_PER3CLK_NCNOC_TARG), +}; + +static const struct jh71x0_crg_domain_info jhb100_per3crg_info =3D { + .clk_data =3D jhb100_per3crg_clk_data, + .num_clk =3D ARRAY_SIZE(jhb100_per3crg_clk_data), + .ext_clk =3D jhb100_per3_ext_clk, + .num_ext_clk =3D ARRAY_SIZE(jhb100_per3_ext_clk), + .rst_name =3D "jhb100-r-per3", + .power_domain =3D false, +}; + +static const struct of_device_id jhb100_per3crg_match[] =3D { + { + .compatible =3D "starfive,jhb100-per3crg", + .data =3D &jhb100_per3crg_info, + }, + { /* sentinel */ } +}; + +static struct platform_driver jhb100_per3crg_driver =3D { + .probe =3D jh71x0_crg_probe, + .driver =3D { + .name =3D "clk-starfive-jhb100-per3", + .of_match_table =3D jhb100_per3crg_match, + .suppress_bind_attrs =3D true, + }, +}; +builtin_platform_driver(jhb100_per3crg_driver); --=20 2.25.1 From nobody Wed Sep 30 16:18:44 2026 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2129.outbound.protection.partner.outlook.cn [139.219.146.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3D173B19C6; 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charset="utf-8" The reset IDs exposed to consumers of the StarFive JHB100 reset controllers do not map one-to-one to the hardware reset bits. Add struct jh71x0_reset_info, which describes the number of resets, the assert/status register offsets and, for discontiguous controllers, a table mapping reset IDs to hardware bits. Add reset_starfive_jh71x0_register_with_info() to register such a controller, and translate the reset ID in the update and status callbacks when a map is provided. Existing users of reset_starfive_jh71x0_register() are unaffected. Signed-off-by: Changhuang Liang --- .../reset/starfive/reset-starfive-jh71x0.c | 99 ++++++++++++++++--- .../reset/starfive/reset-starfive-jh71x0.h | 19 ++++ 2 files changed, 107 insertions(+), 11 deletions(-) diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset= /starfive/reset-starfive-jh71x0.c index 29ce3486752f..fd1c755a0017 100644 --- a/drivers/reset/starfive/reset-starfive-jh71x0.c +++ b/drivers/reset/starfive/reset-starfive-jh71x0.c @@ -14,6 +14,8 @@ =20 #include "reset-starfive-jh71x0.h" =20 +#define JH71X0_RESET_ID_INVALID ULONG_MAX + struct jh71x0_reset { struct reset_controller_dev rcdev; /* protect registers against concurrent read-modify-write */ @@ -21,6 +23,11 @@ struct jh71x0_reset { void __iomem *assert; void __iomem *status; const u32 *asserted; + + /* Only exists in reset controllers that use the + * reset_starfive_jh71x0_register_with_info helper. + */ + const struct jh71x0_reset_info *info; }; =20 static inline struct jh71x0_reset * @@ -29,19 +36,40 @@ jh71x0_reset_from(struct reset_controller_dev *rcdev) return container_of(rcdev, struct jh71x0_reset, rcdev); } =20 +static unsigned long +jh71x0_reset_id_to_hw_id(const struct jh71x0_reset_map *map, unsigned int = nr_resets, + unsigned long reset_id) +{ + for (u32 i =3D 0; i < nr_resets; i++) { + if (map[i].reset_id =3D=3D reset_id) + return map[i].hw_id; + } + + return JH71X0_RESET_ID_INVALID; +} + static int jh71x0_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { struct jh71x0_reset *data =3D jh71x0_reset_from(rcdev); - unsigned long offset =3D id / 32; - u32 mask =3D BIT(id % 32); - void __iomem *reg_assert =3D data->assert + offset * sizeof(u32); - void __iomem *reg_status =3D data->status + offset * sizeof(u32); - u32 done =3D data->asserted ? data->asserted[offset] & mask : 0; - u32 value; - unsigned long flags; + unsigned long offset, flags; + void __iomem *reg_assert; + void __iomem *reg_status; + u32 mask, done, value; int ret; =20 + if (data->info && data->info->discontiguous) { + id =3D jh71x0_reset_id_to_hw_id(data->info->map, data->info->nr_resets, = id); + if (id =3D=3D JH71X0_RESET_ID_INVALID) + return -EINVAL; + } + + offset =3D id / 32; + mask =3D BIT(id % 32); + reg_assert =3D data->assert + offset * sizeof(u32); + reg_status =3D data->status + offset * sizeof(u32); + done =3D data->asserted ? data->asserted[offset] & mask : 0; + if (!assert) done ^=3D mask; =20 @@ -89,10 +117,20 @@ static int jh71x0_reset_status(struct reset_controller= _dev *rcdev, unsigned long id) { struct jh71x0_reset *data =3D jh71x0_reset_from(rcdev); - unsigned long offset =3D id / 32; - u32 mask =3D BIT(id % 32); - void __iomem *reg_status =3D data->status + offset * sizeof(u32); - u32 value =3D readl(reg_status); + void __iomem *reg_status; + unsigned long offset; + u32 mask, value; + + if (data->info && data->info->discontiguous) { + id =3D jh71x0_reset_id_to_hw_id(data->info->map, data->info->nr_resets, = id); + if (id =3D=3D JH71X0_RESET_ID_INVALID) + return -EINVAL; + } + + offset =3D id / 32; + mask =3D BIT(id % 32); + reg_status =3D data->status + offset * sizeof(u32); + value =3D readl(reg_status); =20 if (!data->asserted) return !(value & mask); @@ -132,3 +170,42 @@ int reset_starfive_jh71x0_register(struct device *dev,= struct device_node *of_no return devm_reset_controller_register(dev, &data->rcdev); } EXPORT_SYMBOL_GPL(reset_starfive_jh71x0_register); + +int reset_starfive_jh71x0_register_with_info(struct device *dev, struct de= vice_node *of_node, + void __iomem *assert, void __iomem *status, + const u32 *asserted, + const struct jh71x0_reset_info *info, + struct module *owner) +{ + struct jh71x0_reset *data; + int ret; + + if (info->discontiguous && (!info->map || !info->nr_resets)) + return dev_err_probe(dev, -EINVAL, + "discontiguous controller without a valid ID map\n"); + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->rcdev.ops =3D &jh71x0_reset_ops; + data->rcdev.owner =3D owner; + data->rcdev.nr_resets =3D info->nr_resets; + data->rcdev.dev =3D dev; + data->rcdev.of_node =3D of_node; + + spin_lock_init(&data->lock); + data->assert =3D assert; + data->status =3D status; + data->asserted =3D asserted; + data->info =3D info; + + ret =3D devm_reset_controller_register(dev, &data->rcdev); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to register reset controller\n"); + + dev_info(dev, "Registered %u resets\n", data->rcdev.nr_resets); + + return 0; +} +EXPORT_SYMBOL_GPL(reset_starfive_jh71x0_register_with_info); diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset= /starfive/reset-starfive-jh71x0.h index db7d39a87f87..36f198139602 100644 --- a/drivers/reset/starfive/reset-starfive-jh71x0.h +++ b/drivers/reset/starfive/reset-starfive-jh71x0.h @@ -6,9 +6,28 @@ #ifndef __RESET_STARFIVE_JH71X0_H #define __RESET_STARFIVE_JH71X0_H =20 +struct jh71x0_reset_map { + unsigned long reset_id; + unsigned long hw_id; +}; + +struct jh71x0_reset_info { + unsigned int nr_resets; + unsigned int assert_offset; + unsigned int status_offset; + bool discontiguous; + const struct jh71x0_reset_map *map; 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charset="utf-8" Add auxiliary reset driver to support StarFive JHB100 SoC. Signed-off-by: Changhuang Liang --- MAINTAINERS | 6 + drivers/reset/starfive/Kconfig | 9 + drivers/reset/starfive/Makefile | 1 + .../reset/starfive/reset-starfive-jhb100.c | 302 ++++++++++++++++++ 4 files changed, 318 insertions(+) create mode 100644 drivers/reset/starfive/reset-starfive-jhb100.c diff --git a/MAINTAINERS b/MAINTAINERS index d22078bcf488..60ced2810e0d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -26236,6 +26236,12 @@ S: Supported F: Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-= intc.yaml F: drivers/irqchip/irq-starfive-jhb100-intc.c =20 +STARFIVE JHB100 RESET CONTROLLER DRIVERS +M: Changhuang Liang +S: Supported +F: drivers/reset/starfive/reset-starfive-jhb1* +F: include/dt-bindings/reset/starfive,jhb1*.h + STATIC BRANCH/CALL M: Peter Zijlstra M: Josh Poimboeuf diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig index d832339f61bc..84baefbaee14 100644 --- a/drivers/reset/starfive/Kconfig +++ b/drivers/reset/starfive/Kconfig @@ -19,3 +19,12 @@ config RESET_STARFIVE_JH7110 default ARCH_STARFIVE help This enables the reset controller driver for the StarFive JH7110 SoC. + +config RESET_STARFIVE_JHB100 + bool "StarFive JHB100 Reset Driver" + depends on CLK_STARFIVE_JH71X0 || COMPILE_TEST + select AUXILIARY_BUS + select RESET_STARFIVE_JH71X0 + default ARCH_STARFIVE + help + This enables the reset controller driver for the StarFive JHB100 SoC. diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makef= ile index 7a44b66fb9d5..d781103355d3 100644 --- a/drivers/reset/starfive/Makefile +++ b/drivers/reset/starfive/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_RESET_STARFIVE_JH71X0) +=3D reset-starfive-jh= 71x0.o =20 obj-$(CONFIG_RESET_STARFIVE_JH7100) +=3D reset-starfive-jh7100.o obj-$(CONFIG_RESET_STARFIVE_JH7110) +=3D reset-starfive-jh7110.o +obj-$(CONFIG_RESET_STARFIVE_JHB100) +=3D reset-starfive-jhb100.o diff --git a/drivers/reset/starfive/reset-starfive-jhb100.c b/drivers/reset= /starfive/reset-starfive-jhb100.c new file mode 100644 index 000000000000..87a93149609a --- /dev/null +++ b/drivers/reset/starfive/reset-starfive-jhb100.c @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Reset driver for the StarFive JHB100 SoC + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * + * Author: Changhuang Liang + */ + +#include +#include +#include + +#include "reset-starfive-jh71x0.h" + +#define NUM_RESETS(x) ((x) + 1) + +static const struct jh71x0_reset_map jhb100_sys0_map[] =3D { + { JHB100_SYS0RST_RESOURCE_ARB, 0 }, + { JHB100_SYS0RST_SYS0_IOMUX_PRESETN, 3 }, + { JHB100_SYS0RST_SYS0H_IOMUX_PRESETN, 4 }, + { JHB100_SYS0RST_RST_ADAPTOR_TIMEOUT_RSTN, 5 }, + { JHB100_SYS0RST_BMCPCIERP_RSTN_BUS, 14 }, + { JHB100_SYS0RST_BMCPCIERP_RSTN_CRG, 15 }, + { JHB100_SYS0RST_HOSTSS0_RSTN_BUS_ESPI, 16 }, + { JHB100_SYS0RST_HOSTSS0_RSTN_BUS_PCIE, 17 }, + { JHB100_SYS0RST_HOSTSS0_RSTN_CRG, 18 }, + { JHB100_SYS0RST_BMCPERIPH2_RSTN_CRG, 19 }, + { JHB100_SYS0RST_BMCPERIPH2_RSTN_BUS, 20 }, + { JHB100_SYS0RST_VCE_RSTN_CRG, 21 }, + { JHB100_SYS0RST_VCE_RSTN_BUS, 22 }, + { JHB100_SYS0RST_BMCUSB_RSTN_BUS, 23 }, + { JHB100_SYS0RST_BMCUSB_RSTN_CRG, 24 }, +}; + +static const struct jh71x0_reset_info jhb100_sys0_info =3D { + .nr_resets =3D ARRAY_SIZE(jhb100_sys0_map), + .assert_offset =3D 0x12c, + .status_offset =3D 0x130, + .discontiguous =3D true, + .map =3D jhb100_sys0_map, +}; + +static const struct jh71x0_reset_map jhb100_sys1_map[] =3D { + { JHB100_SYS1RST_SYS1_IOMUX_PRESETN, 1 }, + { JHB100_SYS1RST_MAIN_RSTN_CHIPTOP_SENSOR, 5 }, + { JHB100_SYS1RST_VOUT_RSTN_HOST0, 8 }, + { JHB100_SYS1RST_VOUT_RSTN_HOST1, 9 }, + { JHB100_SYS1RST_HOSTSS1_RSTN_BUS_ESPI, 10 }, + { JHB100_SYS1RST_HOSTSS1_RSTN_BUS_PCIE, 11 }, + { JHB100_SYS1RST_HOSTSS1_RSTN_CRG, 12 }, + { JHB100_SYS1RST_BMCPERIPH3_RSTN_CRG, 13 }, + { JHB100_SYS1RST_BMCPERIPH3_RSTN_BUS, 14 }, +}; + +static const struct jh71x0_reset_info jhb100_sys1_info =3D { + .nr_resets =3D ARRAY_SIZE(jhb100_sys1_map), + .assert_offset =3D 0x54, + .status_offset =3D 0x58, + .discontiguous =3D true, + .map =3D jhb100_sys1_map, +}; + +static const struct jh71x0_reset_map jhb100_sys2_map[] =3D { + { JHB100_SYS2RST_JTAG0_MST_WRAP_HRESETN, 2 }, + { JHB100_SYS2RST_JTAG0_MST_WRAP_APB_PRESETN, 3 }, + { JHB100_SYS2RST_JTAG1_MST_WRAP_HRESETN, 4 }, + { JHB100_SYS2RST_JTAG1_MST_WRAP_APB_PRESETN, 5 }, + { JHB100_SYS2RST_HUSBCMN_HOSTCMN_RSTN_BUS_NCNOC_INIT, 8 }, + { JHB100_SYS2RST_HUSBCMN_RSTN_HOSTCMN_CRG, 9 }, + { JHB100_SYS2RST_HUSBCMN_HOSTUSB0_RSTN_BUS_NCNOC_BMC_TARG, 10 }, + { JHB100_SYS2RST_HUSBCMN_HOSTUSB0_RSTN_BUS_NCNOC_HOST_TARG, 11 }, + { JHB100_SYS2RST_HUSBCMN_RSTN_BMC_CRG, 12 }, + { JHB100_SYS2RST_HUSBCMN_RSTN_HOSTUSB0_CRG, 13 }, + { JHB100_SYS2RST_HUSBCMN_HOSTUSB1_RSTN_BUS_NCNOC_BMC_TARG, 14 }, + { JHB100_SYS2RST_HUSBCMN_HOSTUSB1_RSTN_BUS_NCNOC_HOST_TARG, 15 }, + { JHB100_SYS2RST_HUSBCMN_RSTN_HOSTUSB1_CRG, 16 }, + { JHB100_SYS2RST_BMCPERIPH1_RSTN_CRG, 17 }, + { JHB100_SYS2RST_BMCPERIPH1_RSTN_BUS, 18 }, + { JHB100_SYS2RST_BMCPERIPH0_RSTN_CRG, 19 }, + { JHB100_SYS2RST_BMCPERIPH0_RSTN_BUS, 20 }, + { JHB100_SYS2RST_GPU0_RSTN_CRG, 21 }, + { JHB100_SYS2RST_GPU0_RSTN_BUS, 22 }, + { JHB100_SYS2RST_GPU0_HOST_PCIE_RST_N, 23 }, + { JHB100_SYS2RST_GPU1_RSTN_CRG, 24 }, + { JHB100_SYS2RST_GPU1_RSTN_BUS, 25 }, + { JHB100_SYS2RST_GPU1_HOST_PCIE_RST_N, 26 }, +}; +static const struct jh71x0_reset_info jhb100_sys2_info =3D { + .nr_resets =3D ARRAY_SIZE(jhb100_sys2_map), + .assert_offset =3D 0x88, + .status_offset =3D 0x8c, + .discontiguous =3D true, + .map =3D jhb100_sys2_map, +}; + +static const struct jh71x0_reset_map jhb100_per0_map[] =3D { + { JHB100_PER0RST_MAIN_RSTN_UART4, 1 }, + { JHB100_PER0RST_MAIN_RSTN_UART5, 2 }, + { JHB100_PER0RST_MAIN_RSTN_UART6, 3 }, + { JHB100_PER0RST_MAIN_RSTN_UART7, 4 }, + { JHB100_PER0RST_MAIN_RSTN_UART8, 5 }, + { JHB100_PER0RST_MAIN_RSTN_UART9, 6 }, + { JHB100_PER0RST_MAIN_RSTN_UART10, 7 }, + { JHB100_PER0RST_MAIN_RSTN_UART11, 8 }, + { JHB100_PER0RST_MAIN_RSTN_UART12, 9 }, + { JHB100_PER0RST_MAIN_RSTN_UART13, 10 }, + { JHB100_PER0RST_MAIN_RSTN_UART14, 11 }, + { JHB100_PER0RST_MAIN_RSTN_I2C0, 12 }, + { JHB100_PER0RST_MAIN_RSTN_I2C1, 13 }, + { JHB100_PER0RST_MAIN_RSTN_I2C2, 14 }, + { JHB100_PER0RST_MAIN_RSTN_I2C3, 15 }, + { JHB100_PER0RST_MAIN_RSTN_I2C4, 16 }, + { JHB100_PER0RST_MAIN_RSTN_I2C5, 17 }, + { JHB100_PER0RST_MAIN_RSTN_I2C6, 18 }, + { JHB100_PER0RST_MAIN_RSTN_I2C7, 19 }, + { JHB100_PER0RST_MAIN_RSTN_I2C8, 20 }, + { JHB100_PER0RST_MAIN_RSTN_I2C9, 21 }, + { JHB100_PER0RST_MAIN_RSTN_I2C10, 22 }, + { JHB100_PER0RST_MAIN_RSTN_I2C11, 23 }, + { JHB100_PER0RST_MAIN_RSTN_I2C12, 24 }, + { JHB100_PER0RST_MAIN_RSTN_I2C13, 25 }, + { JHB100_PER0RST_MAIN_RSTN_I2C14, 26 }, + { JHB100_PER0RST_MAIN_RSTN_I2C15, 27 }, + { JHB100_PER0RST_MAIN_RSTN_I3C0, 28 }, + { JHB100_PER0RST_MAIN_RSTN_I3C1, 29 }, + { JHB100_PER0RST_MAIN_RSTN_I3C2, 30 }, + { JHB100_PER0RST_MAIN_RSTN_I3C3, 31 }, + { JHB100_PER0RST_MAIN_RSTN_I3C4, 32 }, + { JHB100_PER0RST_MAIN_RSTN_I3C5, 33 }, + { JHB100_PER0RST_MAIN_RSTN_I3C6, 34 }, + { JHB100_PER0RST_MAIN_RSTN_I3C7, 35 }, + { JHB100_PER0RST_MAIN_RSTN_I3C8, 36 }, + { JHB100_PER0RST_MAIN_RSTN_I3C9, 37 }, + { JHB100_PER0RST_MAIN_RSTN_I3C10, 38 }, + { JHB100_PER0RST_MAIN_RSTN_I3C11, 39 }, + { JHB100_PER0RST_MAIN_RSTN_I3C12, 40 }, + { JHB100_PER0RST_MAIN_RSTN_I3C13, 41 }, + { JHB100_PER0RST_MAIN_RSTN_I3C14, 42 }, + { JHB100_PER0RST_MAIN_RSTN_I3C15, 43 }, + { JHB100_PER0RST_MAIN_RSTN_WDT0, 44 }, + { JHB100_PER0RST_MAIN_RSTN_WDT1, 45 }, + { JHB100_PER0RST_MAIN_RSTN_WDT2, 46 }, + { JHB100_PER0RST_MAIN_RSTN_WDT3, 47 }, + { JHB100_PER0RST_MAIN_RSTN_WDT4, 48 }, + { JHB100_PER0RST_MAIN_RSTN_DUALTIMER0, 49 }, + { JHB100_PER0RST_MAIN_RSTN_DUALTIMER1, 50 }, + { JHB100_PER0RST_MAIN_RSTN_DUALTIMER2, 51 }, + { JHB100_PER0RST_MAIN_RSTN_TRNG, 52 }, + { JHB100_PER0RST_MAIN_RSTN_DMAC0, 53 }, + { JHB100_PER0RST_MAIN_RSTN_DMAC1, 54 }, + { JHB100_PER0RST_MAIN_RSTN_DMAC2, 55 }, + { JHB100_PER0RST_MAIN_RSTN_LTPI0, 56 }, + { JHB100_PER0RST_MAIN_RSTN_LTPI1, 57 }, + { JHB100_PER0RST_MAIN_RSTN_SOL4, 58 }, + { JHB100_PER0RST_MAIN_RSTN_SOL5, 59 }, + { JHB100_PER0RST_MAIN_RSTN_SOL6, 60 }, + { JHB100_PER0RST_MAIN_RSTN_SOL7, 61 }, + { JHB100_PER0RST_MAIN_RSTN_SOL8, 62 }, + { JHB100_PER0RST_MAIN_RSTN_SOL9, 63 }, + { JHB100_PER0RST_MAIN_RSTN_SOL10, 64 }, + { JHB100_PER0RST_MAIN_RSTN_SOL11, 65 }, + { JHB100_PER0RST_MAIN_RSTN_SOL12, 66 }, + { JHB100_PER0RST_MAIN_RSTN_SOL13, 67 }, + { JHB100_PER0RST_MAIN_RSTN_SOL14, 68 }, + { JHB100_PER0RST_MAIN_RSTN_LDO0, 69 }, + { JHB100_PER0RST_MAIN_RSTN_LDO1, 70 }, + { JHB100_PER0RST_MAIN_RSTN_PERIPH0_SENSORS, 71 }, + { JHB100_PER0RST_MAIN_RSTN_DMAC0_SENSORS, 72 }, + { JHB100_PER0RST_SYSCON_PRESETN, 73 }, + { JHB100_PER0RST_GPIO_IOMUX_PRESETN, 74 }, + { JHB100_PER0RST_UART_MUX_REG_WRAP, 75 }, +}; + +static const struct jh71x0_reset_info jhb100_per0_info =3D { + .nr_resets =3D ARRAY_SIZE(jhb100_per0_map), + .assert_offset =3D 0x554, + .status_offset =3D 0x560, + .discontiguous =3D true, + .map =3D jhb100_per0_map, +}; + +static const struct jh71x0_reset_map jhb100_per1_map[] =3D { + { JHB100_PER1RST_IOMUX_PRESETN, 0 }, + { JHB100_PER1RST_SYSCON_PRESETN, 1 }, + { JHB100_PER1RST_MAIN_RSTN_SFC0, 2 }, + { JHB100_PER1RST_MAIN_RSTN_SFC1, 3 }, + { JHB100_PER1RST_MAIN_RSTN_SFC2, 4 }, + { JHB100_PER1RST_MAIN_RSTN_SPI0, 5 }, + { JHB100_PER1RST_MAIN_RSTN_PERIPH1_SENSORS, 6 }, + { JHB100_PER1RST_MAIN_RSTN_SGPIO0, 7 }, + { JHB100_PER1RST_MAIN_RSTN_SGPIO1, 8 }, + { JHB100_PER1RST_MAIN_RSTN_EMMC0, 9 }, + { JHB100_PER1RST_MAIN_RSTN_UFS, 11 }, + { JHB100_PER1RST_MAIN_RSTN_UFS_PHY, 12 }, + { JHB100_PER1RST_MAIN_RSTN_DMAC_SFC0, 13 }, + { JHB100_PER1RST_MAIN_RSTN_DMAC_SFC1, 14 }, + { JHB100_PER1RST_MAIN_RSTN_DMAC_SFC2, 15 }, + { JHB100_PER1RST_MAIN_RSTN_DMAC_SPI0, 16 }, + { JHB100_PER1RST_MAIN_RSTN_PERIPH1_RAS, 17 }, +}; + +static const struct jh71x0_reset_info jhb100_per1_info =3D { + .nr_resets =3D ARRAY_SIZE(jhb100_per1_map), + .assert_offset =3D 0x134, + .status_offset =3D 0x138, + .discontiguous =3D true, + .map =3D jhb100_per1_map, +}; + +static const struct jh71x0_reset_map jhb100_per2_map[] =3D { + { JHB100_PER2RST_IOMUX_PRESETN, 0 }, + { JHB100_PER2RST_POK_IOMUX_PRESETN, 1 }, + { JHB100_PER2RST_SYSREG_RSTN, 2 }, + { JHB100_PER2RST_MAIN_RSTN_CAN0, 3 }, + { JHB100_PER2RST_MAIN_RSTN_CAN1, 4 }, + { JHB100_PER2RST_FAN_TACH_PRESETN, 5 }, + { JHB100_PER2RST_MAIN_RSTN_GMAC2, 7 }, + { JHB100_PER2RST_MAIN_RSTN_GMAC3, 8 }, + { JHB100_PER2RST_MAIN_RSTN_DMAC_8CH, 9 }, + { JHB100_PER2RST_MAIN_RSTN_RTC, 10 }, + { JHB100_PER2RST_ADC0_PRESETN, 11 }, + { JHB100_PER2RST_ADC0_IOMUX_PRESETN, 12 }, + { JHB100_PER2RST_ADC1_PRESETN, 13 }, + { JHB100_PER2RST_ADC1_IOMUX_PRESETN, 14 }, + { JHB100_PER2RST_MAIN_RSTN_PERIPH2_SENSORS, 15 }, +}; + +static const struct jh71x0_reset_info jhb100_per2_info =3D { + .nr_resets =3D ARRAY_SIZE(jhb100_per2_map), + .assert_offset =3D 0x11c, + .status_offset =3D 0x120, + .discontiguous =3D true, + .map =3D jhb100_per2_map, +}; + +static const struct jh71x0_reset_info jhb100_per3_info =3D { + .nr_resets =3D NUM_RESETS(JHB100_PER3RST_IOMUX_PRESETN), + .assert_offset =3D 0x98, + .status_offset =3D 0x9c, + .discontiguous =3D false, +}; + +static int jhb100_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + const struct jh71x0_reset_info *info =3D + (const struct jh71x0_reset_info *)(id->driver_data); + struct jh71x0_reset_adev *rdev =3D to_jh71x0_reset_adev(adev); + void __iomem *base =3D rdev->base; + + if (!info || !base) + return -ENODEV; + + return reset_starfive_jh71x0_register_with_info(&adev->dev, adev->dev.par= ent->of_node, + base + info->assert_offset, + base + info->status_offset, + NULL, info, NULL); +} + +static const struct auxiliary_device_id jhb100_reset_ids[] =3D { + { + .name =3D "clk_starfive_jh71x0.jhb100-r-sys0", + .driver_data =3D (kernel_ulong_t)&jhb100_sys0_info, + }, + { + .name =3D "clk_starfive_jh71x0.jhb100-r-sys1", + .driver_data =3D (kernel_ulong_t)&jhb100_sys1_info, + }, + { + .name =3D "clk_starfive_jh71x0.jhb100-r-sys2", + .driver_data =3D (kernel_ulong_t)&jhb100_sys2_info, + }, + { + .name =3D "clk_starfive_jh71x0.jhb100-r-per0", + .driver_data =3D (kernel_ulong_t)&jhb100_per0_info, + }, + { + .name =3D "clk_starfive_jh71x0.jhb100-r-per1", + .driver_data =3D (kernel_ulong_t)&jhb100_per1_info, + }, + { + .name =3D "clk_starfive_jh71x0.jhb100-r-per2", + .driver_data =3D (kernel_ulong_t)&jhb100_per2_info, + }, + { + .name =3D "clk_starfive_jh71x0.jhb100-r-per3", + .driver_data =3D (kernel_ulong_t)&jhb100_per3_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(auxiliary, jhb100_reset_ids); + +static struct auxiliary_driver jhb100_reset_driver =3D { + .probe =3D jhb100_reset_probe, + .id_table =3D jhb100_reset_ids, +}; +module_auxiliary_driver(jhb100_reset_driver); + +MODULE_AUTHOR("Changhuang Liang "); +MODULE_DESCRIPTION("StarFive JHB100 reset driver"); +MODULE_LICENSE("GPL"); --=20 2.25.1 From nobody Wed Sep 30 16:18:44 2026 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2129.outbound.protection.partner.outlook.cn [139.219.146.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12C4A4F30E5; Wed, 30 Sep 2026 12:44:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=139.219.146.129 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790772290; cv=fail; b=I1Nem0Ip2hIQvWxFJ3yqHtJo3VZFV0Tk1DbkrzaIQg5D/jqaGPrSUDUSuSNtAU9WMokd+XJqQFLt3o/qlMTAukzs6e0z0rZ6MuKsC44vly+w9dbDbqPGCYSoYBIyvl8vn0kzQb16GiT15ykDSbtGoHMqN5wulYiMIEDXNcFLlYY= ARC-Message-Signature: i=2; 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Wed, 30 Sep 2026 12:44:12 +0000 Received: from ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn ([fe80::e7d4:256c:b066:850d]) by ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn ([fe80::e7d4:256c:b066:850d%4]) with mapi id 15.21.0451.026; Wed, 30 Sep 2026 12:44:12 +0000 From: Changhuang Liang To: Michael Turquette , Brian Masney , Jerome Brunet , Stephen Boyd , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Emil Renner Berthing , Kees Cook , "Gustavo A . R . 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charset="utf-8" Add clocks and resets nodes for JHB100 RISC-V BMC SoC. They contain sys0crg/sys1crg/sys2crg/per0crg/per1crg/per2crg/per3crg. Signed-off-by: Changhuang Liang --- arch/riscv/boot/dts/starfive/jhb100.dtsi | 198 ++++++++++++++++++++++- 1 file changed, 195 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts= /starfive/jhb100.dtsi index 14ab83ed4482..6b2863fd3fd3 100644 --- a/arch/riscv/boot/dts/starfive/jhb100.dtsi +++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi @@ -4,6 +4,8 @@ */ =20 /dts-v1/; +#include +#include =20 / { compatible =3D "starfive,jhb100"; @@ -262,12 +264,96 @@ pmu { <0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>; /* Event ID 34 */ }; =20 - clk_uart: clock-uart { - compatible =3D "fixed-clock"; /* Initial clock handler for UART */ + osc: clock-osc { + compatible =3D "fixed-clock"; #clock-cells =3D <0>; clock-frequency =3D <25000000>; }; =20 + pll0: clock-pll0 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <2400000000>; + }; + + pll1: clock-pll1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <1000000000>; + }; + + pll2: clock-pll2 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <903168000>; + }; + + pll4: clock-pll4 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <100700000>; + }; + + pll5: clock-pll5 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <100700000>; + }; + + pll6: clock-pll6 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <2400000000>; + }; + + pll7: clock-pll7 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <1950000000>; + }; + + per2_gmac2_rgmii_rx: clock-per2-gmac2-rgmii-rx { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + + per2_gmac2_rmii_ref: clock-per2-gmac2-rmii-ref { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <50000000>; + }; + + per2_gmac3_sgmii_tx: clock-per2-gmac3-sgmii-tx { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + + per2_gmac3_sgmii_rx: clock-per2-gmac3-sgmii-rx { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + + per3_gmac0_rmii_rclki: clock-per3-gmac0-rmii-rclki { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <50000000>; + }; + + per3_gmac1_sgmii_tx: clock-per3-gmac1-sgmii-tx { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + + per3_gmac1_sgmii_rx: clock-per3-gmac1-sgmii-rx { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + soc { compatible =3D "simple-bus"; interrupt-parent =3D <&plic>; @@ -310,8 +396,10 @@ bus_nioc: bus { uart6: serial@11982000 { compatible =3D "starfive,jhb100-uart", "snps,dw-apb-uart"; reg =3D <0x0 0x11982000 0x0 0x400>; - clocks =3D <&clk_uart>, <&clk_uart>; + clocks =3D <&per0crg JHB100_PER0CLK_SCLK_UART6>, + <&per0crg JHB100_PER0CLK_APB_UART6>; clock-names =3D "baudclk", "apb_pclk"; + resets =3D <&per0crg JHB100_PER0RST_MAIN_RSTN_UART6>; interrupt-parent =3D <&intc>; interrupts =3D <26>; reg-io-width =3D <4>; @@ -319,6 +407,110 @@ uart6: serial@11982000 { status =3D "disabled"; }; =20 + per0crg: clock-controller@11a08000 { + compatible =3D "starfive,jhb100-per0crg"; + reg =3D <0x0 0x11a08000 0x0 0x1000>; + clocks =3D <&osc>, <&pll6>, + <&sys0crg JHB100_SYS0CLK_BMCPER0_CFG_400>, + <&sys0crg JHB100_SYS0CLK_BMCPER0_CFG_800>, + <&sys0crg JHB100_SYS0CLK_BMCPER0_NCNOC_INIT>, + <&sys2crg JHB100_SYS2CLK_BMCPER0_NCNOC_TARG>; + clock-names =3D "osc", "pll6", "cfg_400", + "cfg_800", "ncnoc_init", + "ncnoc_targ"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + per1crg: clock-controller@11b40000 { + compatible =3D "starfive,jhb100-per1crg"; + reg =3D <0x0 0x11b40000 0x0 0x1000>; + clocks =3D <&pll7>, + <&sys0crg JHB100_SYS0CLK_BMCPER1_NCNOC_INIT>, + <&sys0crg JHB100_SYS0CLK_BMCPER1_CFG_800>, + <&sys2crg JHB100_SYS2CLK_BMCPER1_NCNOC_TARG>, + <&sys2crg JHB100_SYS2CLK_BMCPER1_CFG_143>; + clock-names =3D "pll7", "ncnoc_init", + "cfg_800", "ncnoc_targ", + "cfg_143"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + per2crg: clock-controller@11bc0000 { + compatible =3D "starfive,jhb100-per2crg"; + reg =3D <0x0 0x11bc0000 0x0 0x1000>; + clocks =3D <&sys0crg JHB100_SYS0CLK_BMCPER2_NCNOC_INIT>, + <&sys0crg JHB100_SYS0CLK_BMCPER2_CFG_400>, + <&sys0crg JHB100_SYS0CLK_BMCPER2_CFG_125>, + <&per2_gmac2_rgmii_rx>, + <&per2_gmac2_rmii_ref>, + <&per2_gmac3_sgmii_tx>, + <&per2_gmac3_sgmii_rx>, + <&osc>; + clock-names =3D "ncnoc_init", "cfg_400", "cfg_125", + "gmac2_rgmii_rx", + "gmac2_rmii_ref", + "gmac3_sgmii_tx", + "gmac3_sgmii_rx", + "osc"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + per3crg: clock-controller@11c40000 { + compatible =3D "starfive,jhb100-per3crg"; + reg =3D <0x0 0x11c40000 0x0 0x1000>; + clocks =3D <&sys0crg JHB100_SYS0CLK_BMCPER3_NCNOC_INIT>, + <&sys1crg JHB100_SYS1CLK_BMCPER3_NCNOC_TARG>, + <&sys1crg JHB100_SYS1CLK_BMCPER3_CFG_125>, + <&per3_gmac0_rmii_rclki>, + <&per3_gmac1_sgmii_tx>, + <&per3_gmac1_sgmii_rx>, + <&osc>; + clock-names =3D "ncnoc_init", "ncnoc_targ", "cfg_125", + "gmac0_rmii_rclki", + "gmac1_sgmii_tx", + "gmac1_sgmii_rx", + "osc"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + sys0crg: clock-controller@13000000 { + compatible =3D "starfive,jhb100-sys0crg"; + reg =3D <0x0 0x13000000 0x0 0x4000>; + clocks =3D <&osc>, <&pll0>, <&pll1>, + <&pll2>; + clock-names =3D "osc", "pll0", "pll1", "pll2"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + sys1crg: clock-controller@13004000 { + compatible =3D "starfive,jhb100-sys1crg"; + reg =3D <0x0 0x13004000 0x0 0x4000>; + clocks =3D <&osc>, <&pll0>, <&pll1>, + <&pll2>, <&pll4>, <&pll5>, + <&sys0crg JHB100_SYS0CLK_NPU_NCNOC_INIT>; + clock-names =3D "osc", "pll0", "pll1", "pll2", + "pll4", "pll5", "npu_ncnoc_init"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + sys2crg: clock-controller@13008000 { + compatible =3D "starfive,jhb100-sys2crg"; + reg =3D <0x0 0x13008000 0x0 0x4000>; + clocks =3D <&osc>, <&pll1>, + <&sys0crg JHB100_SYS0CLK_GPU0_NCNOC_INIT>, + <&sys0crg JHB100_SYS0CLK_GPU1_NCNOC_INIT>; + clock-names =3D "osc", "pll1", "gpu0_ncnoc_init", + "gpu1_ncnoc_init"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + intc: interrupt-controller@13220000 { compatible =3D "starfive,jhb100-intc"; reg =3D <0x0 0x13220000 0x0 0x80>; --=20 2.25.1