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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YL+RI/k3jrMmvBQtn0nuy42Ups9WVby3yMC1xHrlxZ6lYrDfumR/F2hKFfqUknyyffsrqIseEEjztEODug68+M0Okl721+G016drGcK7z9zcoCE3NSQp6AVyvA5sUrjILBhIqDndPnGbcQS1QZW4+uRcnknU2wizPbyfOSLrqUeDoxi5iSVnzEN8XQlY9KGMPvwUaFDvkE2A+sdJaJy5fxeV6LCrGvWrW5cFodWoyw3n4xtXJsLS3WDNh+X4JoW9gZRAnfVtT8fR+Plgre4ptiZU95C1TwYpeZe+E2Dj3/nJ/z028JFThch0Z6rKST2somQVTFOZMQScPt+6eHCi/a0p9Uo0+5bdK3iG/ifp/quU/ulUC8zPijwYTcRLvXXBKexspfQvUhW49wfAQ1dFPzQBwjrvXdMtWdX6rsKt79lYUJvTzRcUL0zidO+AgNtY X-OriginatorOrg: amdcloud.onmicrosoft.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2026 06:13:41.0669 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 41a8cf73-ca4e-4196-2f82-08df1eb9f95a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0002256F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5780 This commit introduces an EVT1 development-phase devicetree for the Facebook Anacapa BMC. It updates the top-level wrapper DTS to include the EVT1 hardware revision file. =C2=A0 A dedicated EVT1 DTS is added as the base revision for subsequent board variants. The EVT1 devicetree is derived from the original Anacapa devicetree and incorporates several cleanups and fixes: - Remove redundant vhub pinctrl-names - Use default SPI2 memory mapping - Fix dt-check-style strict violations Remove p3v3_bmc_aux lable to fix '[unused-lable]' warning. =C2=A0 The top-level aspeed-bmc-facebook-anacapa.dts now includes the EVT1 devicetree, allowing EVT2 and DVT revisions to inherit from a common baseline while preserving a single build target for Anacapa. Signed-off-by: Colin Huang --- .../aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi | 1127 ++++++++++++++++= ++++ .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 1077 +---------------= --- 2 files changed, 1128 insertions(+), 1076 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi= b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi new file mode 100644 index 000000000000..5f9cfeec39cb --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi @@ -0,0 +1,1127 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "aspeed-g6.dtsi" +#include +#include + +/ { + compatible =3D "facebook,anacapa-bmc", "aspeed,ast2600"; + model =3D "Facebook Anacapa BMC"; + + aliases { + i2c16 =3D &i2c0mux0ch0; + i2c17 =3D &i2c0mux0ch1; + i2c18 =3D &i2c0mux0ch2; + i2c19 =3D &i2c0mux0ch3; + i2c20 =3D &i2c1mux0ch0; + i2c21 =3D &i2c1mux0ch1; + i2c22 =3D &i2c1mux0ch2; + i2c23 =3D &i2c1mux0ch3; + i2c24 =3D &i2c4mux0ch0; + i2c25 =3D &i2c4mux0ch1; + i2c26 =3D &i2c4mux0ch2; + i2c27 =3D &i2c4mux0ch3; + i2c28 =3D &i2c4mux0ch4; + i2c29 =3D &i2c4mux0ch5; + i2c30 =3D &i2c4mux0ch6; + i2c31 =3D &i2c4mux0ch7; + i2c32 =3D &i2c8mux0ch0; + i2c33 =3D &i2c8mux0ch1; + i2c34 =3D &i2c8mux0ch2; + i2c35 =3D &i2c8mux0ch3; + i2c36 =3D &i2c10mux0ch0; + i2c37 =3D &i2c10mux0ch1; + i2c38 =3D &i2c10mux0ch2; + i2c39 =3D &i2c10mux0ch3; + i2c40 =3D &i2c10mux0ch4; + i2c41 =3D &i2c10mux0ch5; + i2c42 =3D &i2c10mux0ch6; + i2c43 =3D &i2c10mux0ch7; + i2c44 =3D &i2c11mux0ch0; + i2c45 =3D &i2c11mux0ch1; + i2c46 =3D &i2c11mux0ch2; + i2c47 =3D &i2c11mux0ch3; + i2c48 =3D &i2c11mux0ch4; + i2c49 =3D &i2c11mux0ch5; + i2c50 =3D &i2c11mux0ch6; + i2c51 =3D &i2c11mux0ch7; + i2c52 =3D &i2c13mux0ch0; + i2c53 =3D &i2c13mux0ch1; + i2c54 =3D &i2c13mux0ch2; + i2c55 =3D &i2c13mux0ch3; + i2c56 =3D &i2c13mux0ch4; + i2c57 =3D &i2c13mux0ch5; + i2c58 =3D &i2c13mux0ch6; + i2c59 =3D &i2c13mux0ch7; + serial0 =3D &uart1; + serial1 =3D &uart2; + serial2 =3D &uart3; + serial3 =3D &uart4; + serial4 =3D &uart5; + }; + + chosen { + stdout-path =3D "serial4:57600n8"; + }; + + iio-hwmon { + compatible =3D "iio-hwmon"; + io-channels =3D <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 2>; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + gpios =3D <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + label =3D "bmc_heartbeat_amber"; + linux,default-trigger =3D "heartbeat"; + }; + + led-1 { + default-state =3D "off"; + gpios =3D <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + label =3D "fp_id_amber"; + }; + }; + + memory@80000000 { + reg =3D <0x80000000 0x80000000>; + device_type =3D "memory"; + }; + + regulator-p3v3-bmc-aux { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "p3v3_bmc_aux"; + }; + + reserved-memory { + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + + gfx_memory: framebuffer { + compatible =3D "shared-dma-pool"; + alignment =3D <0x01000000>; + reusable; + size =3D <0x01000000>; + }; + + video_engine_memory: video { + compatible =3D "shared-dma-pool"; + alignment =3D <0x00100000>; + reusable; + size =3D <0x02c00000>; + }; + }; + + spi { + compatible =3D "spi-gpio"; + #address-cells =3D <1>; + cs-gpios =3D <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + + miso-gpios =3D <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; + mosi-gpios =3D <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + num-chipselects =3D <1>; + sck-gpios =3D <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + #size-cells =3D <0>; + + status =3D "okay"; + + tpm@0 { + compatible =3D "infineon,slb9670", "tcg,tpm_tis-spi"; + reg =3D <0>; + spi-max-frequency =3D <33000000>; + }; + }; +}; + +&adc0 { + pinctrl-0 =3D <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; + pinctrl-names =3D "default"; + aspeed,int-vref-microvolt =3D <2500000>; + + status =3D "okay"; +}; + +&adc1 { + pinctrl-0 =3D <&pinctrl_adc10_default>; + pinctrl-names =3D "default"; + aspeed,int-vref-microvolt =3D <2500000>; + + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&fmc { + status =3D "okay"; + + flash@0 { + label =3D "bmc"; + spi-max-frequency =3D <50000000>; + m25p,fast-read; + + status =3D "okay"; +#include "openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + label =3D "alt-bmc"; + spi-max-frequency =3D <50000000>; + m25p,fast-read; + + status =3D "okay"; + }; +}; + +&gfx { + memory-region =3D <&gfx_memory>; + + status =3D "okay"; +}; + +&gpio0 { + gpio-line-names =3D + + /*A0-A7*/ + "","","","","","","","", + + /*B0-B7*/ + "BATTERY_DETECT", "", "", "BMC_READY", + "", "FM_ID_LED", "", "", + + /*C0-C7*/ + "","","","","","","","", + + /*D0-D7*/ + "","","","","","","","", + + /*E0-E7*/ + "","","","","","","","", + + /*F0-F7*/ + "","","","","","","","", + + /*G0-G7*/ + "FM_MUX1_SEL", "", "", "", + "", "", "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N", + + /*H0-H7*/ + "","","","","","","","", + + /*I0-I7*/ + "", "", "", "", + "", "FLASH_WP_STATUS", "BMC_JTAG_MUX_SEL", "", + + /*J0-J7*/ + "","","","","","","","", + + /*K0-K7*/ + "","","","","","","","", + + /*L0-L7*/ + "","","","","","","","", + + /*M0-M7*/ + "", "BMC_FRU_WP", "", "", + "", "", "", "", + + /*N0-N7*/ + "LED_POSTCODE_0", "LED_POSTCODE_1", "LED_POSTCODE_2", "LED_POSTCODE_3", + "LED_POSTCODE_4", "LED_POSTCODE_5", "LED_POSTCODE_6", "LED_POSTCODE_7", + + /*O0-O7*/ + "","","","","","","","", + + /*P0-P7*/ + "PWR_BTN_BMC_BUF_N", "", "ID_RST_BTN_BMC_N", "", + "PWR_LED", "", "", "BMC_HEARTBEAT_N", + + /*Q0-Q7*/ + "","","","","","","","", + + /*R0-R7*/ + "","","","","","","","", + + /*S0-S7*/ + "", "", "SYS_BMC_PWRBTN_N", "", + "", "", "", "RUN_POWER_FAULT", + + /*T0-T7*/ + "","","","","","","","", + + /*U0-U7*/ + "","","","","","","","", + + /*V0-V7*/ + "","","","","","","","", + + /*W0-W7*/ + "","","","","","","","", + + /*X0-X7*/ + "","","","","","","","", + + /*Y0-Y7*/ + "","","","","","","","", + + /*Z0-Z7*/ + "SPI_BMC_TPM_CS2_N", "", "", "SPI_BMC_TPM_CLK", + "SPI_BMC_TPM_MOSI", "SPI_BMC_TPM_MISO", "", ""; +}; + +&gpio1 { + gpio-line-names =3D + /*18A0-18A7*/ + "","","","","","","","", + + /*18B0-18B7*/ + "","","","", + "FM_BOARD_BMC_REV_ID0", "FM_BOARD_BMC_REV_ID1", + "FM_BOARD_BMC_REV_ID2", "", + + /*18C0-18C7*/ + "","","","","","","","", + + /*18D0-18D7*/ + "","","","","","","","", + + /*18E0-18E3*/ + "FM_BMC_PROT_LS_EN", "AC_PWR_BMC_BTN_N", "", ""; +}; + +// L Bridge Board +&i2c0 { + status =3D "okay"; + + eeprom@50 { + compatible =3D "atmel,24c2048"; + reg =3D <0x50>; + pagesize =3D <128>; + }; + + i2c-mux@70 { + compatible =3D "nxp,pca9546"; + reg =3D <0x70>; + #address-cells =3D <1>; + i2c-mux-idle-disconnect; + #size-cells =3D <0>; + + i2c0mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c0mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c0mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c0mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// R Bridge Board +&i2c1 { + status =3D "okay"; + + eeprom@50 { + compatible =3D "atmel,24c2048"; + reg =3D <0x50>; + pagesize =3D <128>; + }; + + i2c-mux@70 { + compatible =3D "nxp,pca9546"; + reg =3D <0x70>; + #address-cells =3D <1>; + i2c-mux-idle-disconnect; + #size-cells =3D <0>; + + i2c1mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c1mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c1mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c1mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// MB - E1.S +&i2c4 { + status =3D "okay"; + + i2c-mux@70 { + compatible =3D "nxp,pca9548"; + reg =3D <0x70>; + #address-cells =3D <1>; + i2c-mux-idle-disconnect; + #size-cells =3D <0>; + + i2c4mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c4mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c4mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c4mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c4mux0ch4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c4mux0ch5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c4mux0ch6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c4mux0ch7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// AMC +&i2c5 { + status =3D "okay"; +}; + +// MB +&i2c6 { + status =3D "okay"; + + // HPM FRU + eeprom@50 { + compatible =3D "atmel,24c256"; + reg =3D <0x50>; + }; +}; + +// SCM +&i2c7 { + status =3D "okay"; +}; + +// MB - PDB +&i2c8 { + status =3D "okay"; + + i2c-mux@72 { + compatible =3D "nxp,pca9546"; + reg =3D <0x72>; + #address-cells =3D <1>; + i2c-mux-idle-disconnect; + #size-cells =3D <0>; + + i2c8mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@1f { + compatible =3D "ti,adc128d818"; + reg =3D <0x1f>; + ti,mode =3D /bits/ 8 <1>; + }; + + gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + #gpio-cells =3D <2>; + gpio-controller; + + gpio-line-names =3D + "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N", + "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP", + "RPDB_FAN_CT_FAN_FAIL_R_N", "", + "", "", + "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N", + "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N", + "RPDB_I2C_P12V_MB_VRM_ALERT_R_N", + "RPDB_I2C_P12V_STBY_VRM_ALERT_R_N", + "RPDB_PGD_P3V3_STBY_PWRGD_R", + "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; + interrupt-parent =3D <&sgpiom0>; + + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + }; + + gpio@24 { + compatible =3D "nxp,pca9555"; + reg =3D <0x24>; + #gpio-cells =3D <2>; + gpio-controller; + + gpio-line-names =3D + "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", + "RPDB_PWRGD_P50V_HSC4_SYS_R", + "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", + "RPDB_P50V_FAN1_R2_PG", "RPDB_P50V_FAN2_R2_PG", + "RPDB_P50V_FAN3_R2_PG", "RPDB_P50V_FAN4_R2_PG", + "", "RPDB_FAN1_PRSNT_N_R", + "", "RPDB_FAN2_PRSNT_N_R", + "RPDB_FAN3_PRSNT_N_R", "RPDB_FAN4_PRSNT_N_R", + "", ""; + interrupt-parent =3D <&sgpiom0>; + + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + }; + + // R-PDB FRU + eeprom@50 { + compatible =3D "atmel,24c128"; + reg =3D <0x50>; + }; + }; + + i2c8mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + #gpio-cells =3D <2>; + gpio-controller; + + gpio-line-names =3D + "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N", + "LPDB_I2C_TMP432_U29_ALERT_R_N","LPDB_GLOBAL_WP", + "LPDB_FAN_CT_FAN_FAIL_R_N","", + "","", + "LPDB_ALERT_P50V_HSC0_R_N","LPDB_ALERT_P50V_HSC1_R_N", + "LPDB_ALERT_P50V_HSC5_R_N","LPDB_I2C_P12V_SW_VRM_ALERT_R_N", + "LPDB_EAM0_PRSNT_MOS_N_R","LPDB_EAM1_PRSNT_MOS_N_R", + "LPDB_PWRGD_P50V_HSC5_SYS_R",""; + interrupt-parent =3D <&sgpiom0>; + + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + }; + + gpio@24 { + compatible =3D "nxp,pca9555"; + reg =3D <0x24>; + #gpio-cells =3D <2>; + gpio-controller; + + gpio-line-names =3D + "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG", + "LPDB_P50V_FAN3_R2_PG","LPDB_P50V_FAN4_R2_PG", + "LPDB_P50V_FAN5_R2_PG","LPDB_FAN1_PRSNT_N_R", + "LPDB_FAN2_PRSNT_N_R","LPDB_FAN3_PRSNT_N_R", + "LPDB_FAN4_PRSNT_N_R","LPDB_FAN5_PRSNT_N_R", + "","", + "","", + "",""; + interrupt-parent =3D <&sgpiom0>; + + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + }; + + // L-PDB FRU + eeprom@50 { + compatible =3D "atmel,24c128"; + reg =3D <0x50>; + }; + }; + + i2c8mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c8mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// SCM +&i2c9 { + status =3D "okay"; + + // SCM FRU + eeprom@50 { + compatible =3D "atmel,24c128"; + reg =3D <0x50>; + }; + + // BSM FRU + eeprom@56 { + compatible =3D "atmel,24c64"; + reg =3D <0x56>; + }; +}; + +// R Bridge Board +&i2c10 { + status =3D "okay"; + + i2c-mux@71 { + compatible =3D "nxp,pca9548"; + reg =3D <0x71>; + #address-cells =3D <1>; + i2c-mux-idle-disconnect; + #size-cells =3D <0>; + + i2c10mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c10mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c10mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c10mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c10mux0ch4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c10mux0ch5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + #gpio-cells =3D <2>; + gpio-controller; + + gpio-line-names =3D + "","", + "","RBB_CPLD_REFRESH_IN_PRGRS_R_L", + "RBB_EAM0_NIC_CBL_PRSNT_R_L","RBB_EAM1_NIC_CBL_PRSNT_R_L", + "RBB_AINIC_JTAG_MUX_R2_SEL","RBB_SPI_MUX0_R2_SEL", + "RBB_AINIC_PRSNT_R_L","RBB_AINIC_OE_R_N", + "RBB_AINIC_BOARD_R2_ID","RBB_RST_USB2_HUB_R_N", + "RBB_RST_FT4222_R_N","RBB_RST_MCP2210_R_N", + "",""; + }; + + // R Bridge Board FRU + eeprom@52 { + compatible =3D "atmel,24c256"; + reg =3D <0x52>; + }; + }; + + i2c10mux0ch6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c10mux0ch7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// L Bridge Board +&i2c11 { + status =3D "okay"; + + i2c-mux@71 { + compatible =3D "nxp,pca9548"; + reg =3D <0x71>; + #address-cells =3D <1>; + i2c-mux-idle-disconnect; + #size-cells =3D <0>; + + i2c11mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c11mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c11mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c11mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c11mux0ch4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c11mux0ch5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + #gpio-cells =3D <2>; + gpio-controller; + + gpio-line-names =3D + "","", + "","LBB_CPLD_REFRESH_IN_PRGRS_R_L", + "LBB_EAM0_NIC_CBL_PRSNT_R_L","LBB_EAM1_NIC_CBL_PRSNT_R_L", + "LBB_AINIC_JTAG_MUX_R2_SEL","LBB_SPI_MUX0_R2_SEL", + "LBB_AINIC_PRSNT_R_L","LBB_AINIC_OE_R_N", + "LBB_AINIC_BOARD_R2_ID","LBB_RST_USB2_HUB_R_N", + "LBB_RST_FT4222_R_N","LBB_RST_MCP2210_R_N", + "",""; + }; + + // L Bridge Board FRU + eeprom@52 { + compatible =3D "atmel,24c256"; + reg =3D <0x52>; + }; + }; + + i2c11mux0ch6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c11mux0ch7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// Debug Card +&i2c12 { + status =3D "okay"; +}; + +// MB +&i2c13 { + status =3D "okay"; + + i2c-mux@70 { + compatible =3D "nxp,pca9548"; + reg =3D <0x70>; + #address-cells =3D <1>; + i2c-mux-idle-disconnect; + #size-cells =3D <0>; + + i2c13mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c13mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c13mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c13mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@1f { + compatible =3D "ti,adc128d818"; + reg =3D <0x1f>; + ti,mode =3D /bits/ 8 <1>; + }; + }; + + i2c13mux0ch4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + // HPM BRD ID FRU + eeprom@51 { + compatible =3D "atmel,24c256"; + reg =3D <0x51>; + }; + }; + + i2c13mux0ch5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c13mux0ch6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c13mux0ch7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + nfc@28 { + compatible =3D "nxp,nxp-nci-i2c"; + reg =3D <0x28>; + + enable-gpios =3D <&sgpiom0 241 GPIO_ACTIVE_HIGH>; + interrupt-parent =3D <&sgpiom0>; + + interrupts =3D <156 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; +}; + +// SCM +&i2c14 { + status =3D "okay"; +}; + +&i2c15 { + status =3D "okay"; +}; + +&kcs2 { + aspeed,lpc-io-reg =3D <0xca8>; + + status =3D "okay"; +}; + +&kcs3 { + aspeed,lpc-io-reg =3D <0xca2>; + + status =3D "okay"; +}; + +&lpc_ctrl { + status =3D "okay"; +}; + +&mac2 { + pinctrl-0 =3D <&pinctrl_ncsi3_default>; + pinctrl-names =3D "default"; + use-ncsi; + + status =3D "okay"; +}; + +&sgpiom0 { + bus-frequency =3D <2000000>; + gpio-line-names =3D + /*in - out - in - out */ + /* A0-A7 line 0-15 */ + "", "FM_CPU0_SYS_RESET_N", "", "CPU0_KBRST_N", + "", "FM_CPU0_PROCHOT_trigger_N", "", "FM_CLR_CMOS_R_P0", + "", "Force_I3C_SEL", "", "SYSTEM_Force_Run_AC_Cycle", + "", "", "", "", + + /* B0-B7 line 16-31 */ + "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage_Manifold2", "", + "Channel5_leakage_EAM1", "", + "Channel6_leakage_CPU_DIMM", "", + "Channel7_leakage_EAM2", "", + + /* C0-C7 line 32-47 */ + "RSVD_RMC_GPIO3", "", "", "", + "", "", "", "", + "LEAK_DETECT_RMC_N", "JTAG_CPLD_TRST_R_N", "", "", + "", "", "", "", + + /* D0-D7 line 48-63 */ + "PWRGD_PDB_EAMHSC0_CPLD_PG_R", "", + "PWRGD_PDB_EAMHSC1_CPLD_PG_R", "", + "PWRGD_PDB_EAMHSC2_CPLD_PG_R", "", + "PWRGD_PDB_EAMHSC3_CPLD_PG_R", "", + "AMC_BRD_PRSNT_CPLD_L", "", "", "", + "", "", "", "", + + /* E0-E7 line 64-79 */ + "AMC_PDB_EAMHSC0_CPLD_EN_R", "", + "AMC_PDB_EAMHSC1_CPLD_EN_R", "", + "AMC_PDB_EAMHSC2_CPLD_EN_R", "", + "AMC_PDB_EAMHSC3_CPLD_EN_R", "", + "", "", "", "", + "", "", "", "", + + /* F0-F7 line 80-95 */ + "PWRGD_PVDDCR_CPU1_P0", "SGPIO_READY", + "PWRGD_PVDDCR_CPU0_P0", "", + "", "", "", "", + "", "", "", "", + + /* G0-G7 line 96-111 */ + "L_PRSNT_EDSFF0_N", "", + "L_PRSNT_EDSFF1_N", "", + "R_PRSNT_EDSFF2_N", "", + "R_PRSNT_EDSFF3_N", "", + "HPM_EDSFF_PG", "", + "PWRGD_CHEH_CPU0_FPGA", "", + "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD", + "", "", + + /* H0-H7 line 112-127 */ + "PWRGD_P3V3", "", + "P12V_DDR_IP_PWRGD_R", "", + "P12V_DDR_AH_PWRGD_R", "", + "PWRGD_P12V_VRM1_CPLD_PG_R", "", + "PWRGD_P12V_VRM0_CPLD_PG_R", "", + "PWRGD_PDB_HSC4_CPLD_PG_R", "", + "PWRGD_PVDD18_S5_P0_PG", "", + "PWRGD_PVDD33_S5_P0_PG", "", + + /* I0-I7 line 128-143 */ + "EAM0_BRD_PRSNT_R_L", "", + "EAM1_BRD_PRSNT_R_L", "", + "EAM2_BRD_PRSNT_R_L", "", + "EAM3_BRD_PRSNT_R_L", "", + "EAM0_CPU_MOD_PWR_GD_R", "", + "EAM1_CPU_MOD_PWR_GD_R", "", + "PRSNT_EDSFF_BOOT_N", "", + "EAM3_CPU_MOD_PWR_GD_R", "", + + /* J0-J7 line 144-159 */ + "PRSNT_L_BIRDGE_R", "", + "PRSNT_R_BIRDGE_R", "", + "BRIDGE_L_MAIN_PG_R", "", + "BRIDGE_R_MAIN_PG_R", "", + "BRIDGE_L_STBY_PG_R", "", + "BRIDGE_R_STBY_PG_R", "", + "", "", "", "", + + /* K0-K7 line 160-175 */ + "ADC_I2C_ALERT_N", "", + "TEMP_I2C_ALERT_R_L", "", + "CPU0_VR_SMB_ALERT_CPLD_N", "", + "COVER_INTRUDER_R_N", "", + "HANDLE_INTRUDER_CPLD_N", "", + "IRQ_MCIO_CPLD_WAKE_R_N", "", + "APML_CPU0_ALERT_R_N", "", + "PDB_ALERT_R_N", "", + + /* L0-L7 line 176-191 */ + "L_EDSFF0_PG", "", "L_EDSFF1_PG", "", + "R_EDSFF2_PG", "", "R_EDSFF3_PG", "", + "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "", + "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "", + + /* M0-M7 line 192-207 */ + "EAM0_SMERR_CPLD_R_L", "", + "EAM1_SMERR_CPLD_R_L", "", + "EAM2_SMERR_CPLD_R_L", "", + "EAM3_SMERR_CPLD_R_L", "", + "CPU0_SMERR_N_R", "", + "CPU0_NV_SAVE_N_R", "", + "PDB_PWR_LOSS_CPLD_N", "", + "IRQ_BMC_SMI_ACTIVE_R_N", "", + + /* N0-N7 line 208-223 */ + "AMCROT_BMC_S5_RDY_R", "", + "AMC_RDY_R", "", + "AMC_STBY_PGOOD_R", "", + "CPU_AMC_SLP_S5_R_L", "", + "AMC_CPU_EAMPG_R", "", + "", "", "", "", + + /* O0-O7 line 224-239 */ + "HPM_PWR_FAIL", "Port80_b0", + "FM_DIMM_IP_FAIL", "Port80_b1", + "FM_DIMM_AH_FAIL", "Port80_b2", + "AMC_THERMTRIP_ASSERT", "Port80_b3", + "CPU_THERMTRIP_ASSERT", "Port80_b4", + "PVDDCR_SOC_P0_OCP_L", "Port80_b5", + "CPLD_SGPIO_RDY", "Port80_b6", + "", "Port80_b7", + + /* P0-P7 line 240-255 */ + "CPU0_SLP_S5_N_R", "NFC_VEN", + "CPU0_SLP_S3_N_R", "", + "FM_CPU0_PWRGD", "", + "PWRGD_RMC", "", + "FM_RST_CPU0_RESET_N", "", + "FM_PWRGD_CPU0_PWROK", "", + "wS5_PWR_Ready", "", + "wS0_ON_N", "PWRGD_P1V0_AUX"; + + ngpios =3D <128>; + + status =3D "okay"; +}; + +// BIOS Flash +&spi2 { + pinctrl-0 =3D <&pinctrl_spi2_default>; + + pinctrl-names =3D "default"; + + status =3D "okay"; + + flash@0 { + compatible =3D "jedec,spi-nor"; + label =3D "pnor"; + spi-max-frequency =3D <12000000>; + spi-rx-bus-width =3D <2>; + spi-tx-bus-width =3D <2>; + + status =3D "okay"; + }; +}; + +// HOST BIOS Debug +&uart1 { + status =3D "okay"; +}; + +&uart3 { + status =3D "okay"; +}; + +&uart4 { + status =3D "okay"; +}; + +// BMC Debug Console +&uart5 { + status =3D "okay"; +}; + +&uart_routing { + status =3D "okay"; +}; + +&uhci { + status =3D "okay"; +}; + +&vhub { + status =3D "okay"; +}; + +&video { + memory-region =3D <&video_engine_memory>; + + status =3D "okay"; +}; + +&wdt1 { + pinctrl-0 =3D <&pinctrl_wdtrst1_default>; + pinctrl-names =3D "default"; + aspeed,ext-active-high; + aspeed,ext-pulse-duration =3D <256>; + aspeed,ext-push-pull; + aspeed,external-signal; + aspeed,reset-type =3D "soc"; + + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arc= h/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 1fddf3a5d138..5e76076bdcd4 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -1,1079 +1,4 @@ // SPDX-License-Identifier: GPL-2.0-or-later =20 /dts-v1/; -#include "aspeed-g6.dtsi" -#include -#include - -/ { - model =3D "Facebook Anacapa BMC"; - compatible =3D "facebook,anacapa-bmc", "aspeed,ast2600"; - - aliases { - serial0 =3D &uart1; - serial1 =3D &uart2; - serial2 =3D &uart3; - serial3 =3D &uart4; - serial4 =3D &uart5; - i2c16 =3D &i2c0mux0ch0; - i2c17 =3D &i2c0mux0ch1; - i2c18 =3D &i2c0mux0ch2; - i2c19 =3D &i2c0mux0ch3; - i2c20 =3D &i2c1mux0ch0; - i2c21 =3D &i2c1mux0ch1; - i2c22 =3D &i2c1mux0ch2; - i2c23 =3D &i2c1mux0ch3; - i2c24 =3D &i2c4mux0ch0; - i2c25 =3D &i2c4mux0ch1; - i2c26 =3D &i2c4mux0ch2; - i2c27 =3D &i2c4mux0ch3; - i2c28 =3D &i2c4mux0ch4; - i2c29 =3D &i2c4mux0ch5; - i2c30 =3D &i2c4mux0ch6; - i2c31 =3D &i2c4mux0ch7; - i2c32 =3D &i2c8mux0ch0; - i2c33 =3D &i2c8mux0ch1; - i2c34 =3D &i2c8mux0ch2; - i2c35 =3D &i2c8mux0ch3; - i2c36 =3D &i2c10mux0ch0; - i2c37 =3D &i2c10mux0ch1; - i2c38 =3D &i2c10mux0ch2; - i2c39 =3D &i2c10mux0ch3; - i2c40 =3D &i2c10mux0ch4; - i2c41 =3D &i2c10mux0ch5; - i2c42 =3D &i2c10mux0ch6; - i2c43 =3D &i2c10mux0ch7; - i2c44 =3D &i2c11mux0ch0; - i2c45 =3D &i2c11mux0ch1; - i2c46 =3D &i2c11mux0ch2; - i2c47 =3D &i2c11mux0ch3; - i2c48 =3D &i2c11mux0ch4; - i2c49 =3D &i2c11mux0ch5; - i2c50 =3D &i2c11mux0ch6; - i2c51 =3D &i2c11mux0ch7; - i2c52 =3D &i2c13mux0ch0; - i2c53 =3D &i2c13mux0ch1; - i2c54 =3D &i2c13mux0ch2; - i2c55 =3D &i2c13mux0ch3; - i2c56 =3D &i2c13mux0ch4; - i2c57 =3D &i2c13mux0ch5; - i2c58 =3D &i2c13mux0ch6; - i2c59 =3D &i2c13mux0ch7; - }; - - chosen { - stdout-path =3D "serial4:57600n8"; - }; - - iio-hwmon { - compatible =3D "iio-hwmon"; - io-channels =3D <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, - <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, - <&adc1 2>; - }; - - leds { - compatible =3D "gpio-leds"; - - led-0 { - label =3D "bmc_heartbeat_amber"; - gpios =3D <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; - linux,default-trigger =3D "heartbeat"; - }; - - led-1 { - label =3D "fp_id_amber"; - default-state =3D "off"; - gpios =3D <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; - }; - }; - - memory@80000000 { - device_type =3D "memory"; - reg =3D <0x80000000 0x80000000>; - }; - - reserved-memory { - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges; - - video_engine_memory: video { - size =3D <0x02c00000>; - alignment =3D <0x00100000>; - compatible =3D "shared-dma-pool"; - reusable; - }; - - gfx_memory: framebuffer { - size =3D <0x01000000>; - alignment =3D <0x01000000>; - compatible =3D "shared-dma-pool"; - reusable; - }; - }; - - p3v3_bmc_aux: regulator-p3v3-bmc-aux { - compatible =3D "regulator-fixed"; - regulator-name =3D "p3v3_bmc_aux"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - regulator-always-on; - }; - - spi_gpio: spi { - compatible =3D "spi-gpio"; - #address-cells =3D <1>; - #size-cells =3D <0>; - - sck-gpios =3D <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; - mosi-gpios =3D <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; - miso-gpios =3D <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; - cs-gpios =3D <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; - num-chipselects =3D <1>; - status =3D "okay"; - - tpm@0 { - compatible =3D "infineon,slb9670", "tcg,tpm_tis-spi"; - spi-max-frequency =3D <33000000>; - reg =3D <0>; - }; - }; -}; - -&adc0 { - aspeed,int-vref-microvolt =3D <2500000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_adc0_default &pinctrl_adc1_default - &pinctrl_adc2_default &pinctrl_adc3_default - &pinctrl_adc4_default &pinctrl_adc5_default - &pinctrl_adc6_default &pinctrl_adc7_default>; - status =3D "okay"; -}; - -&adc1 { - aspeed,int-vref-microvolt =3D <2500000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_adc10_default>; - status =3D "okay"; -}; - -&ehci1 { - status =3D "okay"; -}; - -&fmc { - status =3D "okay"; - - flash@0 { - status =3D "okay"; - m25p,fast-read; - label =3D "bmc"; - spi-max-frequency =3D <50000000>; -#include "openbmc-flash-layout-128.dtsi" - }; - - flash@1 { - status =3D "okay"; - m25p,fast-read; - label =3D "alt-bmc"; - spi-max-frequency =3D <50000000>; - }; -}; - -&gfx { - status =3D "okay"; - memory-region =3D <&gfx_memory>; -}; - -&gpio0 { - gpio-line-names =3D - - /*A0-A7*/ - "","","","","","","","", - - /*B0-B7*/ - "BATTERY_DETECT", "", "", "BMC_READY", - "", "FM_ID_LED", "", "", - - /*C0-C7*/ - "","","","","","","","", - - /*D0-D7*/ - "","","","","","","","", - - /*E0-E7*/ - "","","","","","","","", - - /*F0-F7*/ - "","","","","","","","", - - /*G0-G7*/ - "FM_MUX1_SEL", "", "", "", - "", "", "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N", - - /*H0-H7*/ - "","","","","","","","", - - /*I0-I7*/ - "", "", "", "", - "", "FLASH_WP_STATUS", "BMC_JTAG_MUX_SEL", "", - - /*J0-J7*/ - "","","","","","","","", - - /*K0-K7*/ - "","","","","","","","", - - /*L0-L7*/ - "","","","","","","","", - - /*M0-M7*/ - "", "BMC_FRU_WP", "", "", - "", "", "", "", - - /*N0-N7*/ - "LED_POSTCODE_0", "LED_POSTCODE_1", "LED_POSTCODE_2", "LED_POSTCODE_3", - "LED_POSTCODE_4", "LED_POSTCODE_5", "LED_POSTCODE_6", "LED_POSTCODE_7", - - /*O0-O7*/ - "","","","","","","","", - - /*P0-P7*/ - "PWR_BTN_BMC_BUF_N", "", "ID_RST_BTN_BMC_N", "", - "PWR_LED", "", "", "BMC_HEARTBEAT_N", - - /*Q0-Q7*/ - "","","","","","","","", - - /*R0-R7*/ - "","","","","","","","", - - /*S0-S7*/ - "", "", "SYS_BMC_PWRBTN_N", "", - "", "", "", "RUN_POWER_FAULT", - - /*T0-T7*/ - "","","","","","","","", - - /*U0-U7*/ - "","","","","","","","", - - /*V0-V7*/ - "","","","","","","","", - - /*W0-W7*/ - "","","","","","","","", - - /*X0-X7*/ - "","","","","","","","", - - /*Y0-Y7*/ - "","","","","","","","", - - /*Z0-Z7*/ - "SPI_BMC_TPM_CS2_N", "", "", "SPI_BMC_TPM_CLK", - "SPI_BMC_TPM_MOSI", "SPI_BMC_TPM_MISO", "", ""; -}; - -&gpio1 { - gpio-line-names =3D - /*18A0-18A7*/ - "","","","","","","","", - - /*18B0-18B7*/ - "","","","", - "FM_BOARD_BMC_REV_ID0", "FM_BOARD_BMC_REV_ID1", - "FM_BOARD_BMC_REV_ID2", "", - - /*18C0-18C7*/ - "","","","","","","","", - - /*18D0-18D7*/ - "","","","","","","","", - - /*18E0-18E3*/ - "FM_BMC_PROT_LS_EN", "AC_PWR_BMC_BTN_N", "", ""; -}; - -// L Bridge Board -&i2c0 { - status =3D "okay"; - - eeprom@50 { - compatible =3D "atmel,24c2048"; - reg =3D <0x50>; - pagesize =3D <128>; - }; - - i2c-mux@70 { - compatible =3D "nxp,pca9546"; - reg =3D <0x70>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c0mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c0mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c0mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c0mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// R Bridge Board -&i2c1 { - status =3D "okay"; - - eeprom@50 { - compatible =3D "atmel,24c2048"; - reg =3D <0x50>; - pagesize =3D <128>; - }; - - i2c-mux@70 { - compatible =3D "nxp,pca9546"; - reg =3D <0x70>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c1mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c1mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c1mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c1mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// MB - E1.S -&i2c4 { - status =3D "okay"; - - i2c-mux@70 { - compatible =3D "nxp,pca9548"; - reg =3D <0x70>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c4mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch4: i2c@4 { - reg =3D <4>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch5: i2c@5 { - reg =3D <5>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch6: i2c@6 { - reg =3D <6>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch7: i2c@7 { - reg =3D <7>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// AMC -&i2c5 { - status =3D "okay"; -}; - -// MB -&i2c6 { - status =3D "okay"; - - // HPM FRU - eeprom@50 { - compatible =3D "atmel,24c256"; - reg =3D <0x50>; - }; -}; - -// SCM -&i2c7 { - status =3D "okay"; - - -}; - -// MB - PDB -&i2c8 { - status =3D "okay"; - - i2c-mux@72 { - compatible =3D "nxp,pca9546"; - reg =3D <0x72>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c8mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - adc@1f { - compatible =3D "ti,adc128d818"; - reg =3D <0x1f>; - ti,mode =3D /bits/ 8 <1>; - }; - - gpio@22 { - compatible =3D "nxp,pca9555"; - reg =3D <0x22>; - gpio-controller; - #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; - - gpio-line-names =3D - "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N", - "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP", - "RPDB_FAN_CT_FAN_FAIL_R_N", "", - "", "", - "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N", - "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N", - "RPDB_I2C_P12V_MB_VRM_ALERT_R_N", - "RPDB_I2C_P12V_STBY_VRM_ALERT_R_N", - "RPDB_PGD_P3V3_STBY_PWRGD_R", - "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; - }; - - gpio@24 { - compatible =3D "nxp,pca9555"; - reg =3D <0x24>; - gpio-controller; - #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; - - gpio-line-names =3D - "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", - "RPDB_PWRGD_P50V_HSC4_SYS_R", - "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", - "RPDB_P50V_FAN1_R2_PG", "RPDB_P50V_FAN2_R2_PG", - "RPDB_P50V_FAN3_R2_PG", "RPDB_P50V_FAN4_R2_PG", - "", "RPDB_FAN1_PRSNT_N_R", - "", "RPDB_FAN2_PRSNT_N_R", - "RPDB_FAN3_PRSNT_N_R", "RPDB_FAN4_PRSNT_N_R", - "", ""; - }; - - // R-PDB FRU - eeprom@50 { - compatible =3D "atmel,24c128"; - reg =3D <0x50>; - }; - }; - i2c8mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - gpio@22 { - compatible =3D "nxp,pca9555"; - reg =3D <0x22>; - gpio-controller; - #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; - - gpio-line-names =3D - "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N", - "LPDB_I2C_TMP432_U29_ALERT_R_N","LPDB_GLOBAL_WP", - "LPDB_FAN_CT_FAN_FAIL_R_N","", - "","", - "LPDB_ALERT_P50V_HSC0_R_N","LPDB_ALERT_P50V_HSC1_R_N", - "LPDB_ALERT_P50V_HSC5_R_N","LPDB_I2C_P12V_SW_VRM_ALERT_R_N", - "LPDB_EAM0_PRSNT_MOS_N_R","LPDB_EAM1_PRSNT_MOS_N_R", - "LPDB_PWRGD_P50V_HSC5_SYS_R",""; - }; - - gpio@24 { - compatible =3D "nxp,pca9555"; - reg =3D <0x24>; - gpio-controller; - #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; - - gpio-line-names =3D - "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG", - "LPDB_P50V_FAN3_R2_PG","LPDB_P50V_FAN4_R2_PG", - "LPDB_P50V_FAN5_R2_PG","LPDB_FAN1_PRSNT_N_R", - "LPDB_FAN2_PRSNT_N_R","LPDB_FAN3_PRSNT_N_R", - "LPDB_FAN4_PRSNT_N_R","LPDB_FAN5_PRSNT_N_R", - "","", - "","", - "",""; - }; - - // L-PDB FRU - eeprom@50 { - compatible =3D "atmel,24c128"; - reg =3D <0x50>; - }; - }; - i2c8mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c8mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// SCM -&i2c9 { - status =3D "okay"; - - // SCM FRU - eeprom@50 { - compatible =3D "atmel,24c128"; - reg =3D <0x50>; - }; - - // BSM FRU - eeprom@56 { - compatible =3D "atmel,24c64"; - reg =3D <0x56>; - }; -}; - -// R Bridge Board -&i2c10 { - status =3D "okay"; - - i2c-mux@71 { - compatible =3D "nxp,pca9548"; - reg =3D <0x71>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c10mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch4: i2c@4 { - reg =3D <4>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch5: i2c@5 { - reg =3D <5>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - gpio@22 { - compatible =3D "nxp,pca9555"; - reg =3D <0x22>; - gpio-controller; - #gpio-cells =3D <2>; - - gpio-line-names =3D - "","", - "","RBB_CPLD_REFRESH_IN_PRGRS_R_L", - "RBB_EAM0_NIC_CBL_PRSNT_R_L","RBB_EAM1_NIC_CBL_PRSNT_R_L", - "RBB_AINIC_JTAG_MUX_R2_SEL","RBB_SPI_MUX0_R2_SEL", - "RBB_AINIC_PRSNT_R_L","RBB_AINIC_OE_R_N", - "RBB_AINIC_BOARD_R2_ID","RBB_RST_USB2_HUB_R_N", - "RBB_RST_FT4222_R_N","RBB_RST_MCP2210_R_N", - "",""; - }; - - // R Bridge Board FRU - eeprom@52 { - compatible =3D "atmel,24c256"; - reg =3D <0x52>; - }; - }; - i2c10mux0ch6: i2c@6 { - reg =3D <6>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch7: i2c@7 { - reg =3D <7>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// L Bridge Board -&i2c11 { - status =3D "okay"; - - i2c-mux@71 { - compatible =3D "nxp,pca9548"; - reg =3D <0x71>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c11mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch4: i2c@4 { - reg =3D <4>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch5: i2c@5 { - reg =3D <5>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - gpio@22 { - compatible =3D "nxp,pca9555"; - reg =3D <0x22>; - gpio-controller; - #gpio-cells =3D <2>; - - gpio-line-names =3D - "","", - "","LBB_CPLD_REFRESH_IN_PRGRS_R_L", - "LBB_EAM0_NIC_CBL_PRSNT_R_L","LBB_EAM1_NIC_CBL_PRSNT_R_L", - "LBB_AINIC_JTAG_MUX_R2_SEL","LBB_SPI_MUX0_R2_SEL", - "LBB_AINIC_PRSNT_R_L","LBB_AINIC_OE_R_N", - "LBB_AINIC_BOARD_R2_ID","LBB_RST_USB2_HUB_R_N", - "LBB_RST_FT4222_R_N","LBB_RST_MCP2210_R_N", - "",""; - }; - - // L Bridge Board FRU - eeprom@52 { - compatible =3D "atmel,24c256"; - reg =3D <0x52>; - }; - }; - i2c11mux0ch6: i2c@6 { - reg =3D <6>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch7: i2c@7 { - reg =3D <7>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// Debug Card -&i2c12 { - status =3D "okay"; -}; - -// MB -&i2c13 { - status =3D "okay"; - - i2c-mux@70 { - compatible =3D "nxp,pca9548"; - reg =3D <0x70>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c13mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c13mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c13mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c13mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - adc@1f { - compatible =3D "ti,adc128d818"; - reg =3D <0x1f>; - ti,mode =3D /bits/ 8 <1>; - }; - }; - i2c13mux0ch4: i2c@4 { - reg =3D <4>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - // HPM BRD ID FRU - eeprom@51 { - compatible =3D "atmel,24c256"; - reg =3D <0x51>; - }; - }; - i2c13mux0ch5: i2c@5 { - reg =3D <5>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c13mux0ch6: i2c@6 { - reg =3D <6>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c13mux0ch7: i2c@7 { - reg =3D <7>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - nfc@28 { - compatible =3D "nxp,nxp-nci-i2c"; - reg =3D <0x28>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <156 IRQ_TYPE_LEVEL_HIGH>; - - enable-gpios =3D <&sgpiom0 241 GPIO_ACTIVE_HIGH>; - }; - }; - }; -}; - -// SCM -&i2c14 { - status =3D "okay"; -}; - -&i2c15 { - status =3D "okay"; -}; - -&kcs2 { - aspeed,lpc-io-reg =3D <0xca8>; - status =3D "okay"; -}; - -&kcs3 { - aspeed,lpc-io-reg =3D <0xca2>; - status =3D "okay"; -}; - -&lpc_ctrl { - status =3D "okay"; -}; - -&mac2 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_ncsi3_default>; - use-ncsi; -}; - -&sgpiom0 { - ngpios =3D <128>; - bus-frequency =3D <2000000>; - gpio-line-names =3D - /*in - out - in - out */ - /* A0-A7 line 0-15 */ - "", "FM_CPU0_SYS_RESET_N", "", "CPU0_KBRST_N", - "", "FM_CPU0_PROCHOT_trigger_N", "", "FM_CLR_CMOS_R_P0", - "", "Force_I3C_SEL", "", "SYSTEM_Force_Run_AC_Cycle", - "", "", "", "", - - /* B0-B7 line 16-31 */ - "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", - "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", - "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", - "Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N", - "Channel4_leakage_Manifold2", "", - "Channel5_leakage_EAM1", "", - "Channel6_leakage_CPU_DIMM", "", - "Channel7_leakage_EAM2", "", - - /* C0-C7 line 32-47 */ - "RSVD_RMC_GPIO3", "", "", "", - "", "", "", "", - "LEAK_DETECT_RMC_N", "JTAG_CPLD_TRST_R_N", "", "", - "", "", "", "", - - /* D0-D7 line 48-63 */ - "PWRGD_PDB_EAMHSC0_CPLD_PG_R", "", - "PWRGD_PDB_EAMHSC1_CPLD_PG_R", "", - "PWRGD_PDB_EAMHSC2_CPLD_PG_R", "", - "PWRGD_PDB_EAMHSC3_CPLD_PG_R", "", - "AMC_BRD_PRSNT_CPLD_L", "", "", "", - "", "", "", "", - - /* E0-E7 line 64-79 */ - "AMC_PDB_EAMHSC0_CPLD_EN_R", "", - "AMC_PDB_EAMHSC1_CPLD_EN_R", "", - "AMC_PDB_EAMHSC2_CPLD_EN_R", "", - "AMC_PDB_EAMHSC3_CPLD_EN_R", "", - "", "", "", "", - "", "", "", "", - - /* F0-F7 line 80-95 */ - "PWRGD_PVDDCR_CPU1_P0", "SGPIO_READY", - "PWRGD_PVDDCR_CPU0_P0", "", - "", "", "", "", - "", "", "", "", - - /* G0-G7 line 96-111 */ - "L_PRSNT_EDSFF0_N", "", - "L_PRSNT_EDSFF1_N", "", - "R_PRSNT_EDSFF2_N", "", - "R_PRSNT_EDSFF3_N", "", - "HPM_EDSFF_PG", "", - "PWRGD_CHEH_CPU0_FPGA", "", - "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD", - "", "", - - /* H0-H7 line 112-127 */ - "PWRGD_P3V3", "", - "P12V_DDR_IP_PWRGD_R", "", - "P12V_DDR_AH_PWRGD_R", "", - "PWRGD_P12V_VRM1_CPLD_PG_R", "", - "PWRGD_P12V_VRM0_CPLD_PG_R", "", - "PWRGD_PDB_HSC4_CPLD_PG_R", "", - "PWRGD_PVDD18_S5_P0_PG", "", - "PWRGD_PVDD33_S5_P0_PG", "", - - /* I0-I7 line 128-143 */ - "EAM0_BRD_PRSNT_R_L", "", - "EAM1_BRD_PRSNT_R_L", "", - "EAM2_BRD_PRSNT_R_L", "", - "EAM3_BRD_PRSNT_R_L", "", - "EAM0_CPU_MOD_PWR_GD_R", "", - "EAM1_CPU_MOD_PWR_GD_R", "", - "PRSNT_EDSFF_BOOT_N", "", - "EAM3_CPU_MOD_PWR_GD_R", "", - - /* J0-J7 line 144-159 */ - "PRSNT_L_BIRDGE_R", "", - "PRSNT_R_BIRDGE_R", "", - "BRIDGE_L_MAIN_PG_R", "", - "BRIDGE_R_MAIN_PG_R", "", - "BRIDGE_L_STBY_PG_R", "", - "BRIDGE_R_STBY_PG_R", "", - "", "", "", "", - - /* K0-K7 line 160-175 */ - "ADC_I2C_ALERT_N", "", - "TEMP_I2C_ALERT_R_L", "", - "CPU0_VR_SMB_ALERT_CPLD_N", "", - "COVER_INTRUDER_R_N", "", - "HANDLE_INTRUDER_CPLD_N", "", - "IRQ_MCIO_CPLD_WAKE_R_N", "", - "APML_CPU0_ALERT_R_N", "", - "PDB_ALERT_R_N", "", - - /* L0-L7 line 176-191 */ - "L_EDSFF0_PG", "", "L_EDSFF1_PG", "", - "R_EDSFF2_PG", "", "R_EDSFF3_PG", "", - "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "", - "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "", - - /* M0-M7 line 192-207 */ - "EAM0_SMERR_CPLD_R_L", "", - "EAM1_SMERR_CPLD_R_L", "", - "EAM2_SMERR_CPLD_R_L", "", - "EAM3_SMERR_CPLD_R_L", "", - "CPU0_SMERR_N_R", "", - "CPU0_NV_SAVE_N_R", "", - "PDB_PWR_LOSS_CPLD_N", "", - "IRQ_BMC_SMI_ACTIVE_R_N", "", - - /* N0-N7 line 208-223 */ - "AMCROT_BMC_S5_RDY_R", "", - "AMC_RDY_R", "", - "AMC_STBY_PGOOD_R", "", - "CPU_AMC_SLP_S5_R_L", "", - "AMC_CPU_EAMPG_R", "", - "", "", "", "", - - /* O0-O7 line 224-239 */ - "HPM_PWR_FAIL", "Port80_b0", - "FM_DIMM_IP_FAIL", "Port80_b1", - "FM_DIMM_AH_FAIL", "Port80_b2", - "AMC_THERMTRIP_ASSERT", "Port80_b3", - "CPU_THERMTRIP_ASSERT", "Port80_b4", - "PVDDCR_SOC_P0_OCP_L", "Port80_b5", - "CPLD_SGPIO_RDY", "Port80_b6", - "", "Port80_b7", - - /* P0-P7 line 240-255 */ - "CPU0_SLP_S5_N_R", "NFC_VEN", - "CPU0_SLP_S3_N_R", "", - "FM_CPU0_PWRGD", "", - "PWRGD_RMC", "", - "FM_RST_CPU0_RESET_N", "", - "FM_PWRGD_CPU0_PWROK", "", - "wS5_PWR_Ready", "", - "wS0_ON_N", "PWRGD_P1V0_AUX"; - status =3D "okay"; -}; - -// BIOS Flash -&spi2 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_spi2_default>; - status =3D "okay"; - reg =3D <0x1e631000 0xc4>, <0x50000000 0x8000000>; - - flash@0 { - compatible =3D "jedec,spi-nor"; - label =3D "pnor"; - spi-max-frequency =3D <12000000>; - spi-tx-bus-width =3D <2>; - spi-rx-bus-width =3D <2>; - status =3D "okay"; - }; -}; - -// HOST BIOS Debug -&uart1 { - status =3D "okay"; -}; - -&uart3 { - status =3D "okay"; -}; - -&uart4 { - status =3D "okay"; -}; - -// BMC Debug Console -&uart5 { - status =3D "okay"; -}; - -&uart_routing { - status =3D "okay"; -}; - -&uhci { - status =3D "okay"; -}; - -&vhub { - status =3D "okay"; - pinctrl-names =3D "default"; -}; - -&video { - status =3D "okay"; - memory-region =3D <&video_engine_memory>; -}; - -&wdt1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_wdtrst1_default>; - aspeed,reset-type =3D "soc"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - aspeed,ext-pulse-duration =3D <256>; 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Wed, 30 Sep 2026 01:13:40 -0500 From: Colin Huang Date: Wed, 30 Sep 2026 14:10:10 +0800 Subject: [PATCH v9 02/15] ARM: dts: aspeed: anacapa: Add EVT2 devicetree inheriting EVT1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260930-anacapa-devlop-phase-devicetree-v9-2-f08aa0d7182d@gmail.com> References: <20260930-anacapa-devlop-phase-devicetree-v9-0-f08aa0d7182d@gmail.com> In-Reply-To: <20260930-anacapa-devlop-phase-devicetree-v9-0-f08aa0d7182d@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" , Ryan Chen , Billy Tsai CC: , , , , , Colin Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790748641; l=5680; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=bE1xb1OaXR8eZ6VfDKZkB+HVFJAwxHzocx20tKXED/U=; b=AkATOu+lyweaH/e28rI8aNILIkARnygHOA7A48BBiKDK0z27iXOwa4m709pjYft1Y8rPminqH 9lg7iDloP1nA4vEGVmaPhIoaFRtG7Z8DMItYl3Q8YQLyLh1rf8vzvTt X-Developer-Key: i=u8813345@gmail.com; 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Signed-off-by: Colin Huang --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi | 167 +++++++++++++++++= ++++ .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 2 +- 2 files changed, 168 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi= b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi new file mode 100644 index 000000000000..c43090618c4a --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "aspeed-bmc-facebook-anacapa-evt1.dtsi" + +&sgpiom0 { + gpio-line-names =3D + /*in - out */ + /* A0-A7 line 0-15 */ + "L_FNIC_FLT", "FM_CPU0_SYS_RESET_N", + "L_BNIC0_FLT", "CPU0_KBRST_N", + "L_BNIC1_FLT", "FM_CPU0_PROCHOT_trigger_N", + "L_BNIC2_FLT", "FM_CLR_CMOS_R_P0", + "L_BNIC3_FLT", "Force_I3C_SEL", + "L_RTM_SW_FLT", "SYSTEM_Force_Run_AC_Cycle", + "", "", + "", "", + + /* B0-B7 line 16-31 */ + "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel5_leakage_present_EAM1", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L", + "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L", + "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330", + "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331", + + /* C0-C7 line 32-47 */ + "RSVD_RMC_GPIO3", "RTM_MUX_L", + "LEAK_DETECT_RMC_N", "RTM_MUX_R", + "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N", + "Channel6_leakage_present_CPU_DIMM", "whdt_sel", + "", "JTAG_CPLD_TRST_R_N", + "", "", + "", "", + "", "", + + /* D0-D7 line 48-63 */ + "Channel0_leakage_present_EAM3", "", + "Channel1_leakage_present_EAM0", "", + "Channel2_leakage_present_Manifold1", "", + "Channel4_leakage_present_Manifold2", "", + "AMC_BRD_PRSNT_CPLD_L", "", + "Channel7_leakage_present_EAM2", "", + "", "", + "", "", + + /* E0-E7 line 64-79 */ + "L_PRSNT_B_FENIC_R2_N", "", + "L_PRSNT_B_BENIC0_R2_N", "", + "L_PRSNT_B_BENIC1_R2_N", "", + "L_PRSNT_B_BENIC2_R2_N", "", + "L_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* F0-F7 line 80-95 */ + "R_PRSNT_B_FENIC_R2_N", "SGPIO_READY", + "R_PRSNT_B_BENIC0_R2_N", "", + "R_PRSNT_B_BENIC1_R2_N", "", + "R_PRSNT_B_BENIC2_R2_N", "", + "R_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* G0-G7 line 96-111 */ + "L_PRSNT_EDSFF0_N", "", + "L_PRSNT_EDSFF1_N", "", + "R_PRSNT_EDSFF2_N", "", + "R_PRSNT_EDSFF3_N", "", + "HPM_EDSFF_PG", "", + "", "", + "", "FM_BMC_READY_PLD", + "PRSNT_NFC_BOARD_R", "", + + /* H0-H7 line 112-127 */ + "R_FNIC_FLT", "", + "R_BNIC0_FLT", "", + "R_BNIC1_FLT", "", + "R_BNIC2_FLT", "", + "R_BNIC3_FLT", "", + "R_RTM_SW_FLT", "", + "", "", + "", "", + + /* I0-I7 line 128-143 */ + "EAM0_BRD_PRSNT_R_L", "", + "EAM1_BRD_PRSNT_R_L", "", + "EAM2_BRD_PRSNT_R_L", "", + "EAM3_BRD_PRSNT_R_L", "", + "FM_TPM_PRSNT_R_N", "", + "PDB_L_PRSNT_R_N", "", + "PRSNT_EDSFF_BOOT_N", "", + "PRSNT_CPU0_N", "", + + /* J0-J7 line 144-159 */ + "PRSNT_L_BRIDGE_R", "", + "PRSNT_R_BRIDGE_R", "", + "BRIDGE_L_MAIN_PG_R", "", + "BRIDGE_R_MAIN_PG_R", "", + "BRIDGE_L_STBY_PG_R", "", + "BRIDGE_R_STBY_PG_R", "", + "IRQ_NFC_BOARD_R", "", + "RSMRST_N", "", + + /* K0-K7 line 160-175 */ + "ADC_I2C_ALERT_N", "", + "TEMP_I2C_ALERT_R_L", "", + "CPU0_VR_SMB_ALERT_CPLD_N", "", + "COVER_INTRUDER_R_N", "", + "HANDLE_INTRUDER_CPLD_N", "", + "IRQ_MCIO_CPLD_WAKE_R_N", "", + "APML_CPU0_ALERT_R_N", "", + "PDB_ALERT_R_N", "", + + /* L0-L7 line 176-191 */ + "L_EDSFF0_PG", "", + "L_EDSFF1_PG", "", + "R_EDSFF2_PG", "", + "R_EDSFF3_PG", "", + "HPM_CPLD_HEART_BIT", "", + "RBB_CPLD_HEART_BIT", "", + "LBB_CPLD_HEART_BIT", "", + "FM_BIOS_POST_CMPLT_R_N", "", + + /* M0-M7 line 192-207 */ + "EAM0_SMERR_CPLD_R_L", "", + "EAM1_SMERR_CPLD_R_L", "", + "EAM2_SMERR_CPLD_R_L", "", + "EAM3_SMERR_CPLD_R_L", "", + "CPU0_SMERR_N_R", "", + "CPU0_NV_SAVE_N_R", "", + "PDB_PWR_LOSS_CPLD_N", "", + "IRQ_BMC_SMI_ACTIVE_R_N", "", + + /* N0-N7 line 208-223 */ + "AMCROT_BMC_S5_RDY_R", "", + "AMC_RDY_R", "", + "AMC_STBY_PGOOD_R", "", + "CPU_AMC_SLP_S5_R_L", "", + "AMC_CPU_EAMPG_R", "", + "DIMM_PMIC_PG_TIMEOUT", "", + "EAM_MOD_PWR_GD_TIMEOUT", "", + "CPLD_AMC_STBY_PWR_EN", "", + + /* O0-O7 line 224-239 */ + "HPM_PWR_FAIL", "Port80_b0", + "FM_DIMM_IP_FAIL", "Port80_b1", + "FM_DIMM_AH_FAIL", "Port80_b2", + "AMC_THERMTRIP_ASSERT", "Port80_b3", + "CPU_THERMTRIP_ASSERT", "Port80_b4", + "PVDDCR_SOC_P0_OCP_L", "Port80_b5", + "CPLD_SGPIO_RDY", "Port80_b6", + "FM_MAIN_PWREN_RMC_EN_ISO", "Port80_b7", + + /* P0-P7 line 240-255 */ + "CPU0_SLP_S5_N_R", "NFC_VEN", + "CPU0_SLP_S3_N_R", "", + "FM_CPU0_PWRGD", "", + "PWRGD_RMC", "", + "FM_RST_CPU0_RESET_N", "RBB_CPLD_RISCV_RST", + "FM_PWRGD_CPU0_PWROK", "LBB_CPLD_RISCV_RST", + "AMC_FAIL", "HPM_CPLD_RISCV_RST", + "S0_ON", ""; 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Wed, 30 Sep 2026 01:13:46 -0500 Received: from [127.0.1.1] (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Wed, 30 Sep 2026 01:13:43 -0500 From: Colin Huang Date: Wed, 30 Sep 2026 14:10:11 +0800 Subject: [PATCH v9 03/15] ARM: dts: aspeed: anacapa: Add DVT devicetree inheriting EVT2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260930-anacapa-devlop-phase-devicetree-v9-3-f08aa0d7182d@gmail.com> References: <20260930-anacapa-devlop-phase-devicetree-v9-0-f08aa0d7182d@gmail.com> In-Reply-To: <20260930-anacapa-devlop-phase-devicetree-v9-0-f08aa0d7182d@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" , Ryan Chen , Billy Tsai CC: , , , , , Colin Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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Signed-off-by: Colin Huang --- .../aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi | 167 +++++++++++++++++= ++++ .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 2 +- 2 files changed, 168 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi new file mode 100644 index 000000000000..0509bc8bb9cd --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "aspeed-bmc-facebook-anacapa-evt2.dtsi" + +&sgpiom0 { + gpio-line-names =3D + /*in - out */ + /* A0-A7 line 0-15 */ + "L_FNIC_FLT", "FM_CPU0_SYS_RESET_N", + "L_BNIC0_FLT", "CPU0_KBRST_N", + "L_BNIC1_FLT", "FM_CPU0_PROCHOT_trigger_N", + "L_BNIC2_FLT", "FM_CLR_CMOS_R_P0", + "L_BNIC3_FLT", "Force_I3C_SEL", + "L_RTM_SW_FLT", "SYSTEM_Force_Run_AC_Cycle", + "", "", + "", "", + + /* B0-B7 line 16-31 */ + "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel5_leakage_present_EAM1", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L", + "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L", + "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330", + "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331", + + /* C0-C7 line 32-47 */ + "RSVD_RMC_GPIO3", "RTM_MUX_L", + "LEAK_DETECT_RMC_N", "RTM_MUX_R", + "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N", + "Channel6_leakage_present_CPU_DIMM", "whdt_sel", + "R_EAM0_NIC_CBL_PRSNT_L", "JTAG_CPLD_TRST_R_N", + "R_EAM1_NIC_CBL_PRSNT_L", "", + "L_EAM0_NIC_CBL_PRSNT_L", "", + "L_EAM1_NIC_CBL_PRSNT_L", "", + + /* D0-D7 line 48-63 */ + "Channel0_leakage_present_EAM3", "", + "Channel1_leakage_present_EAM0", "", + "Channel2_leakage_present_Manifold1", "", + "Channel4_leakage_present_Manifold2", "", + "AMC_BRD_PRSNT_CPLD_L", "", + "Channel7_leakage_present_EAM2", "", + "", "", + "", "", + + /* E0-E7 line 64-79 */ + "L_PRSNT_B_FENIC_R2_N", "", + "L_PRSNT_B_BENIC0_R2_N", "", + "L_PRSNT_B_BENIC1_R2_N", "", + "L_PRSNT_B_BENIC2_R2_N", "", + "L_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* F0-F7 line 80-95 */ + "R_PRSNT_B_FENIC_R2_N", "SGPIO_READY", + "R_PRSNT_B_BENIC0_R2_N", "", + "R_PRSNT_B_BENIC1_R2_N", "", + "R_PRSNT_B_BENIC2_R2_N", "", + "R_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* G0-G7 line 96-111 */ + "L_PRSNT_EDSFF0_N", "", + "L_PRSNT_EDSFF1_N", "", + "R_PRSNT_EDSFF2_N", "", + "R_PRSNT_EDSFF3_N", "", + "HPM_EDSFF_PG", "", + "", "", + "P12V_PWR_CABLE_PRSNT_L_R", "FM_BMC_READY_PLD", + "PRSNT_NFC_BOARD_R", "", + + /* H0-H7 line 112-127 */ + "R_FNIC_FLT", "", + "R_BNIC0_FLT", "", + "R_BNIC1_FLT", "", + "R_BNIC2_FLT", "", + "R_BNIC3_FLT", "", + "R_RTM_SW_FLT", "", + "RBB_Cable_Present", "", + "LBB_Cable_Present", "", + + /* I0-I7 line 128-143 */ + "EAM0_BRD_PRSNT_R_L", "", + "EAM1_BRD_PRSNT_R_L", "", + "EAM2_BRD_PRSNT_R_L", "", + "EAM3_BRD_PRSNT_R_L", "", + "FM_TPM_PRSNT_R_N", "", + "PDB_L_PRSNT_R_N", "", + "PRSNT_EDSFF_BOOT_N", "", + "PRSNT_CPU0_N", "", + + /* J0-J7 line 144-159 */ + "PRSNT_L_BRIDGE_R", "", + "PRSNT_R_BRIDGE_R", "", + "BRIDGE_L_MAIN_PG_R", "", + "BRIDGE_R_MAIN_PG_R", "", + "BRIDGE_L_STBY_PG_R", "", + "BRIDGE_R_STBY_PG_R", "", + "IRQ_NFC_BOARD_R", "", + "RSMRST_N", "", + + /* K0-K7 line 160-175 */ + "ADC_I2C_ALERT_N", "", + "TEMP_I2C_ALERT_R_L", "", + "CPU0_VR_SMB_ALERT_CPLD_N", "", + "COVER_INTRUDER_R_N", "", + "HANDLE_INTRUDER_CPLD_N", "", + "IRQ_MCIO_CPLD_WAKE_R_N", "", + "APML_CPU0_ALERT_R_N", "", + "PDB_ALERT_R_N", "", + + /* L0-L7 line 176-191 */ + "L_EDSFF0_PG", "", + "L_EDSFF1_PG", "", + "R_EDSFF2_PG", "", + "R_EDSFF3_PG", "", + "HPM_CPLD_HEART_BIT", "", + "RBB_CPLD_HEART_BIT", "", + "LBB_CPLD_HEART_BIT", "", + "FM_BIOS_POST_CMPLT_R_N", "", + + /* M0-M7 line 192-207 */ + "EAM0_SMERR_CPLD_R_L", "", + "EAM1_SMERR_CPLD_R_L", "", + "EAM2_SMERR_CPLD_R_L", "", + "EAM3_SMERR_CPLD_R_L", "", + "CPU0_SMERR_N_R", "", + "CPU0_NV_SAVE_N_R", "", + "PDB_PWR_LOSS_CPLD_N", "", + "IRQ_BMC_SMI_ACTIVE_R_N", "", + + /* N0-N7 line 208-223 */ + "AMCROT_BMC_S5_RDY_R", "", + "AMC_RDY_R", "", + "AMC_STBY_PGOOD_R", "", + "CPU_AMC_SLP_S5_R_L", "", + "AMC_CPU_EAMPG_R", "", + "DIMM_PMIC_PG_TIMEOUT", "", + "EAM_MOD_PWR_GD_TIMEOUT", "", + "CPLD_AMC_STBY_PWR_EN", "", + + /* O0-O7 line 224-239 */ + "HPM_PWR_FAIL", "Port80_b0", + "FM_DIMM_IP_FAIL", "Port80_b1", + "FM_DIMM_AH_FAIL", "Port80_b2", + "AMC_THERMTRIP_ASSERT", "Port80_b3", + "CPU_THERMTRIP_ASSERT", "Port80_b4", + "PVDDCR_SOC_P0_OCP_L", "Port80_b5", + "CPLD_SGPIO_RDY", "Port80_b6", + "FM_MAIN_PWREN_RMC_EN_ISO", "Port80_b7", + + /* P0-P7 line 240-255 */ + "CPU0_SLP_S5_N_R", "NFC_VEN", + "CPU0_SLP_S3_N_R", "", + "FM_CPU0_PWRGD", "", + "PWRGD_RMC", "", + "FM_RST_CPU0_RESET_N", "RBB_CPLD_RISCV_RST", + "FM_PWRGD_CPU0_PWROK", "LBB_CPLD_RISCV_RST", + "AMC_FAIL", "HPM_CPLD_RISCV_RST", + "S0_ON", ""; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arc= h/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 606dacb605c5..1eee0d84c0a8 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -1,4 +1,4 @@ // SPDX-License-Identifier: GPL-2.0-or-later =20 /dts-v1/; -#include "aspeed-bmc-facebook-anacapa-evt2.dtsi" +#include "aspeed-bmc-facebook-anacapa-dvt.dtsi" --=20 2.34.1 From nobody Fri Oct 2 04:27:52 2026 Received: from CY7PR03CU001.outbound.protection.outlook.com (mail-westcentralusazon11010029.outbound.protection.outlook.com [40.93.198.29]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE2D13B5E01; Wed, 30 Sep 2026 06:13:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.198.29 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; 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Signed-off-by: Colin Huang --- .../boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi | 14 ++++++++++= ++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi= b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi index c43090618c4a..8c4a03a82d44 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi @@ -2,6 +2,20 @@ =20 #include "aspeed-bmc-facebook-anacapa-evt1.dtsi" =20 +// SCM +&i2c9 { + // SCM FRU + // | DC-SCM Rev | Slave address of eeprom | + // |-------------------|--------------------------| + // | Rev B | 0x50 | + // | Rev C/D/E/F/above | 0x51 | + + eeprom@51 { + compatible =3D "atmel,24c128"; + reg =3D <0x51>; + }; +}; + &sgpiom0 { gpio-line-names =3D /*in - out */ --=20 2.34.1 From nobody Fri Oct 2 04:27:52 2026 Received: from BL2PR02CU003.outbound.protection.outlook.com (mail-eastusazon11011010.outbound.protection.outlook.com [52.101.52.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBCDE3B6C19; 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Signed-off-by: Carl Lee --- .../boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi | 13 +++++++++= ++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi= b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi index 8c4a03a82d44..a2392f684b80 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi @@ -16,6 +16,19 @@ eeprom@51 { }; }; =20 +// MB +&i2c13 { + i2c-mux@70 { + i2c@7 { + // NFC adaptor board FRU + eeprom@50 { + compatible =3D "atmel,24c128"; + reg =3D <0x50>; + }; + }; + }; +}; + &sgpiom0 { gpio-line-names =3D /*in - out */ --=20 2.34.1 From nobody Fri Oct 2 04:27:52 2026 Received: from BL0PR03CU003.outbound.protection.outlook.com (mail-eastusazon11012044.outbound.protection.outlook.com [52.101.53.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA5283B27DE; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0M5sv+s9VW1GDBlccm2wVkl+hDJXbyfjl6KPB7NC0dh3bQXPrUwHSf+kCbT3/PSuAHU5HZBnjuTGzCmA6ErgAj5/hzbiqHnZ1ZLxUDkq/9/nBehwR1rqBIaKqx3V3c/nHcf24Vs4fmZNmZ0xGZ2EKYhJfwgTEuXC1UwKXTUJfpqdhnWeOLj/7zX8YYSLzh+AHokI9RvzL/MspPaPLJ663lR/hlOHvSbGwt5zKK4i3lfNp9i2iyMUJcPXUtrV2vDbD9YY7+bsHzd1L21IRyVRGT98HSOQkMb8ban0N+4c49NAY9L1wHm1b1n8UGoNtHrQywsSPI4mADTHECQ6p8pdL0aEsDelghFb5dmmpK3i4EM+EerIpiezaMHTlRtpUCaw6bPhOnHa6QhDsQ9T/iDmqFYcE9TAq2GQqTRU0bDJQKv4GwTfh0hRBaTmSwGPsOdr X-OriginatorOrg: amdcloud.onmicrosoft.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2026 06:13:56.2382 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0598973c-c5c8-4efa-29f3-08df1eba0265 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022572.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPFCAFD069B8 From: Rex Fu Update the LPDB and RPDB fan GPIO line names to align with the platform fan numbering scheme. The LPDB fan GPIOs are named FAN0 through FAN4, while the RPDB fan GPIOs are named FAN5 through FAN8. This keeps the GPIO line names consistent with the fan inventory and platform-level fan numbering. Signed-off-by: Rex Fu --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi | 34 ++++++++++++++++++= ++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi= b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi index a2392f684b80..3ea5d67865d4 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi @@ -2,6 +2,40 @@ =20 #include "aspeed-bmc-facebook-anacapa-evt1.dtsi" =20 +// MB - PDB +&i2c8 { + i2c-mux@72 { + i2c@0 { + gpio@24 { + gpio-line-names =3D + "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", + "RPDB_PWRGD_P50V_HSC4_SYS_R", + "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", + "RPDB_P50V_FAN5_R2_PG", "RPDB_P50V_FAN6_R2_PG", + "RPDB_P50V_FAN7_R2_PG", "RPDB_P50V_FAN8_R2_PG", + "", "RPDB_FAN5_PRSNT_N_R", + "", "RPDB_FAN6_PRSNT_N_R", + "RPDB_FAN7_PRSNT_N_R", "RPDB_FAN8_PRSNT_N_R", + "", ""; + }; + }; + + i2c@1 { + gpio@24 { + gpio-line-names =3D + "LPDB_P50V_FAN0_R2_PG","LPDB_P50V_FAN1_R2_PG", + "LPDB_P50V_FAN2_R2_PG","LPDB_P50V_FAN3_R2_PG", + "LPDB_P50V_FAN4_R2_PG","LPDB_FAN0_PRSNT_N_R", + "LPDB_FAN1_PRSNT_N_R","LPDB_FAN2_PRSNT_N_R", + "LPDB_FAN3_PRSNT_N_R","LPDB_FAN4_PRSNT_N_R", + "","", + "","", + "",""; + }; + }; + }; +}; + // SCM &i2c9 { // SCM FRU --=20 2.34.1 From nobody Fri Oct 2 04:27:52 2026 Received: from BN1PR04CU002.outbound.protection.outlook.com (mail-eastus2azon11010049.outbound.protection.outlook.com [52.101.56.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D14B3B5318; Wed, 30 Sep 2026 06:14:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.56.49 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790748846; cv=fail; b=BrhwYGjWtUTTzqj7Aztc3KfVSJYzil4ayqUN7g2400pJpIIp8Xz+rYvS7MdisA4h1XhUIMqk1DBon90GRAYBokcRu1wxLbXuL9FuNVY9biK17gW17EFyEUVT+f4gJW7Xg89ZW7JQ4CJDcyWFOVeRlQpUxaLzdDcDwk1Ds0IowCk= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790748846; c=relaxed/simple; bh=LyHz4O0tDFwF0uGfs3TjpGYa/xx676dzfa9Z/b4rugQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; 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Wed, 30 Sep 2026 01:13:55 -0500 From: Colin Huang Date: Wed, 30 Sep 2026 14:10:15 +0800 Subject: [PATCH v9 07/15] ARM: dts: aspeed: anacapa: Enable MCTP and FRU for NIC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260930-anacapa-devlop-phase-devicetree-v9-7-f08aa0d7182d@gmail.com> References: <20260930-anacapa-devlop-phase-devicetree-v9-0-f08aa0d7182d@gmail.com> In-Reply-To: <20260930-anacapa-devlop-phase-devicetree-v9-0-f08aa0d7182d@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" , Ryan Chen , Billy Tsai CC: , , , , , Colin Huang , Andy Chung X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790748641; l=3254; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=xSybis4WnZ0wCCi5yNlS7U3ZxSjvjItq7krEUM0miaU=; b=iqYCebzbVOrsbMqhLQIXSXleFW0jMCj9ofppclxzNnC7wvw2uJcT8G7SjDgCVIzRmjc/yx4pY 1HqEoB2S4d7CU0iHP3hSxeU24uF6jF5BlgvvRdhGEkh+3d8EcjbVFD5 X-Developer-Key: i=u8813345@gmail.com; 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Also add EEPROM device for NIC FRU and reorder the I2C virtual bus index accroding to the system silkscreen index. Signed-off-by: Andy Chung --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi | 137 +++++++++++++++++= ++++ 1 file changed, 137 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi= b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi index 3ea5d67865d4..ab16e5ad5871 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi @@ -2,6 +2,25 @@ =20 #include "aspeed-bmc-facebook-anacapa-evt1.dtsi" =20 +&{/aliases} { + i2c36 =3D &i2c11mux0ch5; + i2c37 =3D &i2c11mux0ch6; + i2c38 =3D &i2c11mux0ch7; + i2c39 =3D &i2c11mux0ch0; + i2c40 =3D &i2c11mux0ch1; + i2c41 =3D &i2c11mux0ch2; + i2c42 =3D &i2c11mux0ch3; + i2c43 =3D &i2c11mux0ch4; + i2c44 =3D &i2c10mux0ch1; + i2c45 =3D &i2c10mux0ch2; + i2c46 =3D &i2c10mux0ch3; + i2c47 =3D &i2c10mux0ch4; + i2c48 =3D &i2c10mux0ch5; + i2c49 =3D &i2c10mux0ch6; + i2c50 =3D &i2c10mux0ch7; + i2c51 =3D &i2c10mux0ch0; +}; + // MB - PDB &i2c8 { i2c-mux@72 { @@ -50,6 +69,124 @@ eeprom@51 { }; }; =20 +// R Bridge Board +&i2c10 { + multi-master; + + mctp@10 { + compatible =3D "mctp-i2c-controller"; + reg =3D <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + i2c-mux@71 { + /delete-property/ i2c-mux-idle-disconnect; + + i2c10mux0ch1: i2c@1 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + + i2c10mux0ch2: i2c@2 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + + i2c10mux0ch3: i2c@3 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + + i2c10mux0ch4: i2c@4 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + }; +}; + +// L Bridge Board +&i2c11 { + multi-master; + + mctp@10 { + compatible =3D "mctp-i2c-controller"; + reg =3D <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + i2c-mux@71 { + /delete-property/ i2c-mux-idle-disconnect; + + i2c11mux0ch0: i2c@0 { + mctp-controller; + // FE NIC FRU + + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + + i2c11mux0ch1: i2c@1 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + + i2c11mux0ch2: i2c@2 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + + i2c11mux0ch3: i2c@3 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + + i2c11mux0ch4: i2c@4 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + }; +}; + // MB &i2c13 { i2c-mux@70 { --=20 2.34.1 From nobody Fri Oct 2 04:27:52 2026 Received: from CY7PR03CU001.outbound.protection.outlook.com (mail-westcentralusazon11010031.outbound.protection.outlook.com [40.93.198.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 271DC3AFD1F; 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The resistor values are required for accurate current and power measurement by the driver. These settings reflect the actual BOM used on EVT2, where different sense resistor values (150 uOhm and 250 uOhm) are populated across rails. Without this configuration, the reported readings would be incorrect. Signed-off-by: Peter Shen --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi | 42 ++++++++++++++++++= ++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi= b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi index ab16e5ad5871..5f849bd21fe0 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi @@ -37,6 +37,30 @@ gpio@24 { "RPDB_FAN7_PRSNT_N_R", "RPDB_FAN8_PRSNT_N_R", "", ""; }; + + power-monitor@42 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x42>; + shunt-resistor-micro-ohms =3D <150>; + }; + + power-monitor@43 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x43>; + shunt-resistor-micro-ohms =3D <150>; + }; + + power-monitor@44 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x44>; + shunt-resistor-micro-ohms =3D <250>; + }; + + power-monitor@45 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x45>; + shunt-resistor-micro-ohms =3D <250>; + }; }; =20 i2c@1 { @@ -51,6 +75,24 @@ gpio@24 { "","", "",""; }; + + power-monitor@40 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x40>; + shunt-resistor-micro-ohms =3D <150>; + }; + + power-monitor@41 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x41>; + shunt-resistor-micro-ohms =3D <150>; + }; + + power-monitor@45 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x45>; + shunt-resistor-micro-ohms =3D <250>; + }; }; }; }; --=20 2.34.1 From nobody Fri Oct 2 04:27:52 2026 Received: from BL2PR02CU003.outbound.protection.outlook.com (mail-eastusazon11011039.outbound.protection.outlook.com [52.101.52.39]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F3B43B6BEB; Wed, 30 Sep 2026 06:14:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.52.39 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790748852; cv=fail; b=TOJ/W+SQ5zjxn1MtDRkuJ+e8693hRkiL83MOSyDixUb/eisaD+lbkwPXwuRWzG66mYSB6WTqiorsTuRo30yTgRty903oL46L2GyJaxgWCdwsy+1I0PwUmed/68MLWV+PbBUcHXcbMHnwWv2aaJ+i2LbSPiQpw3KSdN3JVRs72u4= ARC-Message-Signature: i=2; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: P1Dnt3hNWewIwYyX5ALpoOXFaaFwnGBFj6BW6uxG3O8sTVrLenau1H+z/zPLUTW9IQzDAqxryWzHK8L0Dc7/5BWNSUnnEtHfMFhZRhdLsU4qxC6xXrLv1qiKhZ6ISrZSERL9SiMfGB+1KfhCeMHFnGhtXZYO9TNA4mKcL0uGd/NlQ8jHoWnooZY6hMPbVcXcb2wXw8q2w5cBPOndAnuO+ZZ5+GYvBCWITN9lDWrc4PX1mJ2Ll83qTBUuGPri/DBDHSFgxVhQSPLz3IJUx4sXx4ZOrY+nv+6/CU5f2kLt+sQa0t7+WzqSV6K+cjjWlcUfJ3g4WHF/Om/LDpbNpsWTY43Fd63825sjGjCMpuKFbv1QXpUGV11PGDWgnlMgGLuj0Cu2mAZtLhvtXL9BCR1M2sWLeIzAG6khN7cs86IIRKJj7zzZaeqCItlPgYWSo5ev X-OriginatorOrg: amdcloud.onmicrosoft.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2026 06:14:06.0126 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b43921ac-4022-4dd8-c0c5-08df1eba0837 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000A7FF.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB9551 From: Rex Fu Add PCA9554 GPIO expanders for PDB fuse monitor signals on the Anacapa DVT board. The patch adds GPIO expander definitions for both the left and right PDBs under the i2c8 multiplexer and updates the associated gpio-line-names to reflect the final signal assignments. Signed-off-by: Rex Fu --- .../aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi | 92 ++++++++++++++++++= ++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi index 0509bc8bb9cd..2fd7e46daa63 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi @@ -2,6 +2,98 @@ =20 #include "aspeed-bmc-facebook-anacapa-evt2.dtsi" =20 +// MB - PDB +&i2c8 { + i2c-mux@72 { + i2c@0 { + gpio@22 { + gpio-line-names =3D + "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TMP432_U8_ALERT_R_N", + "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP", + "RPDB_FAN_CT_FAN_FAIL_R_N", "RPDB_VERID_A0", + "RPDB_VERID_A1", "RPDB_VERID_A2", + "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N", + "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N", + "RPDB_P12V_MB_VRM_ALERT_R_N", + "RPDB_P12V_STBY_VRM_ALERT_R_N", + "RPDB_PGD_P3V3_STBY_PWRGD_R", + "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; + }; + + gpio@24 { + gpio-line-names =3D + "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", + "RPDB_PWRGD_P50V_HSC4_SYS_R", + "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", + "RPDB_P50V_FAN5_R2_PG", "RPDB_P50V_FAN6_R2_PG", + "RPDB_P50V_FAN7_R2_PG", "RPDB_P50V_FAN8_R2_PG", + "RPDB_SKU_ID0", "RPDB_FAN5_PRSNT_N_R", + "", "RPDB_FAN6_PRSNT_N_R", + "RPDB_FAN7_PRSNT_N_R", "RPDB_FAN8_PRSNT_N_R", + "", ""; + }; + + gpio@38 { + compatible =3D "nxp,pca9554"; + reg =3D <0x38>; + #gpio-cells =3D <2>; + gpio-controller; + + gpio-line-names =3D + "RPDB_P50V_FUSE2_TVS1", "RPDB_P50V_FUSE2_TVS2", + "RPDB_P50V_FUSE3_TVS1", "RPDB_P50V_FUSE3_TVS2", + "RPDB_P50V_FUSE4_TVS1", "", + "", ""; + + interrupt-parent =3D <&sgpiom0>; + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + i2c@1 { + gpio@22 { + gpio-line-names =3D + "LPDB_FAN_FULL_SPEED_R_N", "LPDB_I2C_TEMP75_U8_ALERT_R_N", + "LPDB_I2C_TMP432_U29_ALERT_R_N", "LPDB_GLOBAL_WP", + "LPDB_FAN_CT_FAN_FAIL_R_N", "LPDB_VERID_A0", + "LPDB_VERID_A1", "LPDB_VERID_A2", + "LPDB_ALERT_P50V_HSC0_R_N", "LPDB_ALERT_P50V_HSC1_R_N", + "LPDB_ALERT_P50V_HSC5_R_N", "LPDB_I2C_P12V_SW_VRM_ALERT_R_N", + "LPDB_EAM0_PRSNT_MOS_N_R", "LPDB_EAM1_PRSNT_MOS_N_R", + "LPDB_PWRGD_P50V_HSC5_SYS_R", "BARKLIP_PRSNT_N_R3"; + }; + + gpio@24 { + gpio-line-names =3D + "LPDB_P50V_FAN0_R2_PG", "LPDB_P50V_FAN1_R2_PG", + "LPDB_P50V_FAN2_R2_PG", "LPDB_P50V_FAN3_R2_PG", + "LPDB_P50V_FAN4_R2_PG", "LPDB_FAN0_PRSNT_N_R", + "LPDB_FAN1_PRSNT_N_R", "LPDB_FAN2_PRSNT_N_R", + "LPDB_FAN3_PRSNT_N_R", "LPDB_FAN4_PRSNT_N_R", + "LPDB_SKU_ID0", "", + "", "", + "", "LPDB_PG_P3V3_R"; + }; + + gpio@38 { + compatible =3D "nxp,pca9554"; + reg =3D <0x38>; + #gpio-cells =3D <2>; + gpio-controller; + + gpio-line-names =3D + "LPDB_P50V_FUSE0_TVS1", "LPDB_P50V_FUSE0_TVS2", + "LPDB_P50V_FUSE1_TVS1", "LPDB_P50V_FUSE1_TVS2", + "LPDB_P50V_FUSE5_TVS1", "", + "", ""; + + interrupt-parent =3D <&sgpiom0>; + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; +}; + &sgpiom0 { gpio-line-names =3D /*in - out */ --=20 2.34.1 From nobody Fri Oct 2 04:27:52 2026 Received: from BL0PR03CU003.outbound.protection.outlook.com (mail-eastusazon11012044.outbound.protection.outlook.com [52.101.53.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A50EC3B7B71; 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The channel number is enough to identify each leakage present signal. Signed-off-by: Rex Fu --- .../aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi | 28 +++++++++++-------= ---- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi index 2fd7e46daa63..3b3967b47980 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi @@ -108,32 +108,32 @@ &sgpiom0 { "", "", =20 /* B0-B7 line 16-31 */ - "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", - "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", - "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", - "Channel5_leakage_present_EAM1", "FM_CPU0_NMI_SYNC_FLOOD_N", - "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L", - "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L", - "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330", - "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331", + "Channel0_leakage", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel5_leakage_present", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage", "BMC_AINIC0_WP_R2_L", + "Channel5_leakage", "BMC_AINIC1_WP_R2_L", + "Channel6_leakage", "CPLD_BUF_R_AGPIO330", + "Channel7_leakage", "CPLD_BUF_R_AGPIO331", =20 /* C0-C7 line 32-47 */ "RSVD_RMC_GPIO3", "RTM_MUX_L", "LEAK_DETECT_RMC_N", "RTM_MUX_R", "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N", - "Channel6_leakage_present_CPU_DIMM", "whdt_sel", + "Channel6_leakage_present", "whdt_sel", "R_EAM0_NIC_CBL_PRSNT_L", "JTAG_CPLD_TRST_R_N", "R_EAM1_NIC_CBL_PRSNT_L", "", "L_EAM0_NIC_CBL_PRSNT_L", "", "L_EAM1_NIC_CBL_PRSNT_L", "", =20 /* D0-D7 line 48-63 */ - "Channel0_leakage_present_EAM3", "", - "Channel1_leakage_present_EAM0", "", - "Channel2_leakage_present_Manifold1", "", - "Channel4_leakage_present_Manifold2", "", + "Channel0_leakage_present", "", + "Channel1_leakage_present", "", + "Channel2_leakage_present", "", + "Channel4_leakage_present", "", "AMC_BRD_PRSNT_CPLD_L", "", - "Channel7_leakage_present_EAM2", "", + "Channel7_leakage_present", "", "", "", "", "", =20 --=20 2.34.1 From nobody Fri Oct 2 04:27:52 2026 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012070.outbound.protection.outlook.com [40.93.195.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0D543AFD1F; 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Signed-off-by: Rex Fu Signed-off-by: Colin Huang --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi= b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi index 5f9cfeec39cb..e429f7be46db 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi @@ -92,7 +92,7 @@ memory@80000000 { device_type =3D "memory"; }; =20 - regulator-p3v3-bmc-aux { + p3v3_bmc_aux: regulator-p3v3-bmc-aux { compatible =3D "regulator-fixed"; regulator-always-on; regulator-max-microvolt =3D <3300000>; @@ -170,6 +170,7 @@ &fmc { flash@0 { label =3D "bmc"; spi-max-frequency =3D <50000000>; + vcc-supply =3D <&p3v3_bmc_aux>; m25p,fast-read; =20 status =3D "okay"; @@ -179,6 +180,7 @@ flash@0 { flash@1 { label =3D "alt-bmc"; spi-max-frequency =3D <50000000>; + vcc-supply =3D <&p3v3_bmc_aux>; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: bfeBWN0j03lkyYGT8W99TZvn+Ww9wD3GL9Vxx2z+/ratG/oh47I727bb1vASadJqeRE061PDQr2t55jbfCI906n9Qv3zHr6yhOKm23WcXk8M7DZAxy6rR9v/J6jCgLMHPIFPxFxEdLEeIhUhZ6utBxikjojGMbmhvJhPt6bOv/PGbuaN4PV3aXnvdx0eY+PEJHs4HM74yDTT53+1YBAKj7zVdRgIl91UIeq8mO3Th8PFtl2BUvUcj8ezim/UcmzeXGWe2Vh92tV13ZmPilSlhqyF9FcGouvKrrlB05RiHAfEwyANFT9evbvcjsdsp3C4d5Jp22+rzV+/Cu7lfjGRkI0uvn3+ZytTsyM6s/KIbLq09HwwB1DFbP+RQNyrJAj9LayS7ng7cBU6mk8rUlJZLxOEjgDoAUz2oTQ3GAjsis6eNsniwHYJuI/iDqrpJ61l X-OriginatorOrg: amdcloud.onmicrosoft.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2026 06:14:15.5951 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e1d83bb4-8c4c-449c-9b08-08df1eba0dee X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0002256E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN5PR12MB9509 From: Carl Lee Add two NCT7363 fan-controller nodes on Anacapa I2C mux channels and define their PWM/tach channel mappings. This matches the fan-control hardware layout and allows the kernel to probe the correct fan-controller devices. Signed-off-by: Carl Lee --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi | 102 +++++++++++++++++= ++++ 1 file changed, 102 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi= b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi index 5f849bd21fe0..f546a7b5786a 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi @@ -25,6 +25,52 @@ &i2c8 { i2c-mux@72 { i2c@0 { + fanctl1: fan-controller@21 { + compatible =3D "nuvoton,nct7363"; + reg =3D <0x21>; + #pwm-cells =3D <2>; + + fan-0 { + pwms =3D <&fanctl1 6 40000>; + tach-ch =3D /bits/ 8 <0x00>; + }; + + fan-2 { + pwms =3D <&fanctl1 9 40000>; + tach-ch =3D /bits/ 8 <0x02>; + }; + + fan-3 { + pwms =3D <&fanctl1 9 40000>; + tach-ch =3D /bits/ 8 <0x03>; + }; + + fan-5 { + pwms =3D <&fanctl1 12 40000>; + tach-ch =3D /bits/ 8 <0x05>; + }; + + fan-6 { + pwms =3D <&fanctl1 12 40000>; + tach-ch =3D /bits/ 8 <0x06>; + }; + + fan-9 { + pwms =3D <&fanctl1 0 40000>; + tach-ch =3D /bits/ 8 <0x09>; + }; + + fan-10 { + pwms =3D <&fanctl1 0 40000>; + tach-ch =3D /bits/ 8 <0x0a>; + }; + + fan-15 { + pwms =3D <&fanctl1 6 40000>; + tach-ch =3D /bits/ 8 <0x0f>; + }; + }; + gpio@24 { gpio-line-names =3D "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", @@ -64,6 +110,62 @@ power-monitor@45 { }; =20 i2c@1 { + fanctl0: fan-controller@23 { + compatible =3D "nuvoton,nct7363"; + reg =3D <0x23>; + #pwm-cells =3D <2>; + + fan-0 { + pwms =3D <&fanctl0 6 40000>; + tach-ch =3D /bits/ 8 <0x00>; + }; + + fan-2 { + pwms =3D <&fanctl0 9 40000>; + tach-ch =3D /bits/ 8 <0x02>; + }; + + fan-3 { + pwms =3D <&fanctl0 9 40000>; + tach-ch =3D /bits/ 8 <0x03>; + }; + + fan-5 { + pwms =3D <&fanctl0 12 40000>; + tach-ch =3D /bits/ 8 <0x05>; + }; + + fan-6 { + pwms =3D <&fanctl0 12 40000>; + tach-ch =3D /bits/ 8 <0x06>; + }; + + fan-9 { + pwms =3D <&fanctl0 0 40000>; + tach-ch =3D /bits/ 8 <0x09>; + }; + + fan-10 { + pwms =3D <&fanctl0 0 40000>; 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Keeping these nodes may cause incorrect probing/binding attempts. Remove them to avoid address conflicts. Signed-off-by: Carl Lee --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi | 42 ------------------= ---- 1 file changed, 42 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi= b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi index f546a7b5786a..5c0d874fa24a 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi @@ -83,30 +83,6 @@ gpio@24 { "RPDB_FAN7_PRSNT_N_R", "RPDB_FAN8_PRSNT_N_R", "", ""; }; - - power-monitor@42 { - compatible =3D "lltc,ltc4287"; - reg =3D <0x42>; - shunt-resistor-micro-ohms =3D <150>; - }; - - power-monitor@43 { - compatible =3D "lltc,ltc4287"; - reg =3D <0x43>; - shunt-resistor-micro-ohms =3D <150>; - }; - - power-monitor@44 { - compatible =3D "lltc,ltc4287"; - reg =3D <0x44>; - shunt-resistor-micro-ohms =3D <250>; - }; - - power-monitor@45 { - compatible =3D "lltc,ltc4287"; - reg =3D <0x45>; - shunt-resistor-micro-ohms =3D <250>; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: X66szdslFrKaWv7M2HDqwyBZtuV/XblNte+UNrMh7FR45uX5UOiXIWmmdUxzNXSGrC5J1tG1n+yog8lIeeOuWZYFJwn1lF11dHjrIr6Jwep93TGulGJtksjbquCPvqkHZAMmfV4HCJs2H7/v3DS7ZW8yddNSdzawqVGylh1Z6AJSAIZJi82gojq9OKcHr41MHwwxtOotsvkI6AOL6GUhK+DrJUnWuY0QWpiOsY/aGj4+HPjpZC2SX1hg+PBmQwnUb7q3H08oSjRFdy6LB5rE2kY6jAlwJlFmBKfzUFCAZmtTVrXv52hD1RkFCkwJ24786ucQldCDExf/ZGxTFqVu/E0FOpzwuFBWDJDRx+7FacEOtz3Lp2GPXtIC6tdH/64X4qRT5CmxZYXNi10hhOA5L+uLNSLO7PqBZ80WM4nCsqWzkSX7ZInbZlD7ju0Cs/Ol X-OriginatorOrg: amdcloud.onmicrosoft.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2026 06:14:21.4997 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3f3e0884-ffd4-4245-9538-08df1eba1173 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022572.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS5PPF7B9F1F8E0 From: Rex Fu The CPLD definition for the EDSFF power status signals has changed from PG to FLT. Update the corresponding SGPIO line names to match the CPLD definition. Signed-off-by: Rex Fu --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi | 10 +++++-= ---- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi | 10 +++++-= ---- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi index 3b3967b47980..698308049c38 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi @@ -162,7 +162,7 @@ &sgpiom0 { "L_PRSNT_EDSFF1_N", "", "R_PRSNT_EDSFF2_N", "", "R_PRSNT_EDSFF3_N", "", - "HPM_EDSFF_PG", "", + "EDSFF_BOOT_FLT", "", "", "", "P12V_PWR_CABLE_PRSNT_L_R", "FM_BMC_READY_PLD", "PRSNT_NFC_BOARD_R", "", @@ -208,10 +208,10 @@ &sgpiom0 { "PDB_ALERT_R_N", "", =20 /* L0-L7 line 176-191 */ - "L_EDSFF0_PG", "", - "L_EDSFF1_PG", "", - "R_EDSFF2_PG", "", - "R_EDSFF3_PG", "", + "L_EDSFF0_FLT", "", + "L_EDSFF1_FLT", "", + "R_EDSFF2_FLT", "", + "R_EDSFF3_FLT", "", "HPM_CPLD_HEART_BIT", "", "RBB_CPLD_HEART_BIT", "", "LBB_CPLD_HEART_BIT", "", diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi= b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi index 5c0d874fa24a..766aa26b6cea 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi @@ -370,7 +370,7 @@ &sgpiom0 { "L_PRSNT_EDSFF1_N", "", "R_PRSNT_EDSFF2_N", "", "R_PRSNT_EDSFF3_N", "", - "HPM_EDSFF_PG", "", + "EDSFF_BOOT_FLT", "", "", "", "", "FM_BMC_READY_PLD", "PRSNT_NFC_BOARD_R", "", @@ -416,10 +416,10 @@ &sgpiom0 { "PDB_ALERT_R_N", "", =20 /* L0-L7 line 176-191 */ - "L_EDSFF0_PG", "", - "L_EDSFF1_PG", "", - "R_EDSFF2_PG", "", - "R_EDSFF3_PG", "", + "L_EDSFF0_FLT", "", + "L_EDSFF1_FLT", "", + "R_EDSFF2_FLT", "", + "R_EDSFF3_FLT", "", "HPM_CPLD_HEART_BIT", "", "RBB_CPLD_HEART_BIT", "", "LBB_CPLD_HEART_BIT", "", --=20 2.34.1 From nobody Fri Oct 2 04:27:52 2026 Received: from CO1PR03CU002.outbound.protection.outlook.com (mail-westus2azon11010036.outbound.protection.outlook.com [52.101.46.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BDB6438E5ED; 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Signed-off-by: Colin Huang --- .../aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi | 35 ++++++++++++++++++= ++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi= b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi index e429f7be46db..cd87ca27e18c 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi @@ -404,30 +404,65 @@ i2c4mux0ch0: i2c@0 { reg =3D <0>; #address-cells =3D <1>; #size-cells =3D <0>; + + // E1S_Boot FRU + eeprom@53 { + compatible =3D "atmel,24c02"; + reg =3D <0x53>; + pagesize =3D <16>; + }; }; =20 i2c4mux0ch1: i2c@1 { reg =3D <1>; #address-cells =3D <1>; #size-cells =3D <0>; + + // E1S_0 FRU + eeprom@53 { + compatible =3D "atmel,24c02"; + reg =3D <0x53>; + pagesize =3D <16>; + }; }; =20 i2c4mux0ch2: i2c@2 { reg =3D <2>; #address-cells =3D <1>; #size-cells =3D <0>; + + // E1S_1 FRU + eeprom@53 { + compatible =3D "atmel,24c02"; + reg =3D <0x53>; + pagesize =3D <16>; + }; }; =20 i2c4mux0ch3: i2c@3 { reg =3D <3>; #address-cells =3D <1>; #size-cells =3D <0>; + + // E1S_2 FRU + eeprom@53 { + compatible =3D "atmel,24c02"; + reg =3D <0x53>; + pagesize =3D <16>; + }; }; =20 i2c4mux0ch4: i2c@4 { reg =3D <4>; #address-cells =3D <1>; #size-cells =3D <0>; + + // E1S_3 FRU + eeprom@53 { + compatible =3D "atmel,24c02"; + reg =3D <0x53>; + pagesize =3D <16>; + }; }; =20 i2c4mux0ch5: i2c@5 { --=20 2.34.1