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Tue, 29 Sep 2026 05:25:54 -0700 (PDT) X-Received: by 2002:a05:6214:400b:b0:917:911c:74bf with SMTP id 6a1803df08f44-917911c78bbmr13631176d6.30.1790684753815; Tue, 29 Sep 2026 05:25:53 -0700 (PDT) Received: from QCOM-eG0v1AUPpu.na.qualcomm.com ([2a01:e0a:830:450:5c1f:3897:a4a1:99e1]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-9178d302482sm9103956d6.12.2026.09.29.05.25.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2026 05:25:53 -0700 (PDT) From: Loic Poulain Date: Tue, 29 Sep 2026 14:25:45 +0200 Subject: [PATCH v6 1/5] i2c: qcom-cci: Switch msm8953 to the CCI v2 timing/rate config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260929-cci-clk-fix-v6-1-62a268cccb0f@oss.qualcomm.com> References: <20260929-cci-clk-fix-v6-0-62a268cccb0f@oss.qualcomm.com> In-Reply-To: <20260929-cci-clk-fix-v6-0-62a268cccb0f@oss.qualcomm.com> To: Robert Foss , Andi Shyti , Wolfram Sang , Dmitry Baryshkov , Luca Weiss Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, vladimir.zapolskiy@linaro.org, konradybcio@kernel.org, stephan.gerhold@linaro.org, Loic Poulain , Konrad Dybcio X-Mailer: b4 0.14.2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI5MDA0OSBTYWx0ZWRfXxlEwv3i2+lgH DAVGRuDR1MfM17bDFx7U3YGksDauJ0m8bZd+9xEcjxkCbYlS66USqdiQsgHxr/+DzUOAg6Q1OBv F9PPtcOSHzHZ6D0A6w1Hxw9meHkeBkwrYowMbe1tmKeOU6w/9pICdRKgr6WPpoCkQ0pUzdE67KI J+HazUGqfBlyjyyfX47hIww9RcqnAeQKVLLL/mdt3w1xkCwP1QH9llVS4m28foHEXNomuEuR8aU Y1ZhsOyoHBvfkOXxNCsMGloSKiuxWuw1+1SexiMdeuU2/+ufRW3YkFDJ3w1nnrjGVJgh3xu52zR gIEn9yFg8DgV9w9Q18HgFR1aPPGkm5yuJyY60a32w49QJoc+TLnU1yJJd5AFi8D7pnH6FUT+Ci1 dDPpyJpyzLv2joHu0Rqw9TfMX8JPaPJQMTt3iUyxXKiblkYEO+1ShvKYzVLCPpWDUAsT1z4JDTe yDEF3+tlqHatKEbAsmQ== X-Proofpoint-GUID: BgjtRkkjqq9ZhmEqg2IFRJdZ1F7bApan X-Authority-Analysis: v=2.4 cv=VcVir1p9 c=1 sm=1 tr=0 ts=6abbae53 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=Y4CGMd7wAM7EkgizcVsA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: BgjtRkkjqq9ZhmEqg2IFRJdZ1F7bApan X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI5MDA0OSBTYWx0ZWRfX97c0NsGYmI/4 dhmnWz6Y68f633pexx6p5O1wloBd3eH5N9X0KyMyhydCY6RWNdMma0vPPSt9cIZSPbgg3nMubwH z0F6Gn+YVT4FbWzksK7vO6Q6X/P7mT4= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-29_04,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 spamscore=0 phishscore=0 malwarescore=0 adultscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609290049 The msm8953 CCI timing table is internally inconsistent. Its Standard and Fast timings match v1/v1.5, which are calibrated for a 19.2 MHz CCI clock, but its Fast+ timings are essentially the 'v2' values, which are calibrated for 37.5 MHz. Since all masters share a single CCI clock, no single rate can satisfy all three modes with the current table, and the DT assigns 19.2 MHz, so Fast+ timings are wrong. The msm8953 CCI is the same hardware version as msm8996/sdm630, which already use the cci_v2_data config (37.5 MHz). 37.5 MHz is supported by the msm8953 CCI RCG, so reuse cci_v2_data for msm8953 as well and drop the redundant, inconsistent standalone table. This makes all three I2C modes self-consistent under a single clock rate. Note this requires the CCI clock to run at 37.5 MHz, the driver selects and enforces the proper rate in following patches. Reviewed-by: Konrad Dybcio Reviewed-by: Vladimir Zapolskiy Signed-off-by: Loic Poulain --- drivers/i2c/busses/i2c-qcom-cci.c | 47 +----------------------------------= ---- 1 file changed, 1 insertion(+), 46 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qco= m-cci.c index bdeda3979c4814b5cdb463734b8361da7fffa879..0a216c4d08114f267c8441925e8= 811ca64f1a909 100644 --- a/drivers/i2c/busses/i2c-qcom-cci.c +++ b/drivers/i2c/busses/i2c-qcom-cci.c @@ -756,54 +756,9 @@ static const struct cci_data cci_v2_data =3D { }, }; =20 -static const struct cci_data cci_msm8953_data =3D { - .num_masters =3D 2, - .queue_size =3D { 64, 16 }, - .quirks =3D { - .max_write_len =3D 11, - .max_read_len =3D 12, - }, - .params[I2C_MODE_STANDARD] =3D { - .thigh =3D 78, - .tlow =3D 114, - .tsu_sto =3D 28, - .tsu_sta =3D 28, - .thd_dat =3D 10, - .thd_sta =3D 77, - .tbuf =3D 118, - .scl_stretch_en =3D 0, - .trdhld =3D 6, - .tsp =3D 1 - }, - .params[I2C_MODE_FAST] =3D { - .thigh =3D 20, - .tlow =3D 28, - .tsu_sto =3D 21, - .tsu_sta =3D 21, - .thd_dat =3D 13, - .thd_sta =3D 18, - .tbuf =3D 32, - .scl_stretch_en =3D 0, - .trdhld =3D 6, - .tsp =3D 3 - }, - .params[I2C_MODE_FAST_PLUS] =3D { - .thigh =3D 16, - .tlow =3D 22, - .tsu_sto =3D 17, - .tsu_sta =3D 18, - .thd_dat =3D 16, - .thd_sta =3D 15, - .tbuf =3D 19, - .scl_stretch_en =3D 1, - .trdhld =3D 3, - .tsp =3D 3 - }, -}; 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Tue, 29 Sep 2026 05:25:56 -0700 (PDT) X-Received: by 2002:a05:6214:2528:b0:914:4c57:510e with SMTP id 6a1803df08f44-9144c577f72mr184411926d6.19.1790684756033; Tue, 29 Sep 2026 05:25:56 -0700 (PDT) Received: from QCOM-eG0v1AUPpu.na.qualcomm.com ([2a01:e0a:830:450:5c1f:3897:a4a1:99e1]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-9178d302482sm9103956d6.12.2026.09.29.05.25.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2026 05:25:55 -0700 (PDT) From: Loic Poulain Date: Tue, 29 Sep 2026 14:25:46 +0200 Subject: [PATCH v6 2/5] i2c: qcom-cci: Support per-mode CCI clock rates Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260929-cci-clk-fix-v6-2-62a268cccb0f@oss.qualcomm.com> References: <20260929-cci-clk-fix-v6-0-62a268cccb0f@oss.qualcomm.com> In-Reply-To: <20260929-cci-clk-fix-v6-0-62a268cccb0f@oss.qualcomm.com> To: Robert Foss , Andi Shyti , Wolfram Sang , Dmitry Baryshkov , Luca Weiss Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, vladimir.zapolskiy@linaro.org, konradybcio@kernel.org, stephan.gerhold@linaro.org, Loic Poulain , Konrad Dybcio X-Mailer: b4 0.14.2 X-Proofpoint-ORIG-GUID: 2AtKieAyECg1OLiZnWeTeG9_UKaJVQeH X-Proofpoint-GUID: 2AtKieAyECg1OLiZnWeTeG9_UKaJVQeH X-Authority-Analysis: v=2.4 cv=Z+55j3RA c=1 sm=1 tr=0 ts=6abbae55 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=xxoTSpZZo30Qa_5IT24A:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI5MDA0OSBTYWx0ZWRfXx6QLFnm343nu DGmc5E5VkT8SjE4TZK+hl8CrKyX3ej+iKgViowQMWX4X0Kld9tYgMcUhmb4MA8VRb6Mu+MedW68 G2a/4b1C94f/anN9DgFdnZuqoClDxWIGADjPzbQZyNLbbgr/bWOzNZVjF9TqsoIElRRu6ofW8l4 GDAFiKHvlJrx3EoyFw9eI4Hr+pmEHpFzqeIz0DLVmXtIIMhuA3a29ed1JyDJ36kX/Mx8SJY1Oab pz26reTNodp8+fl/BMV64tWK4vwlGG68KOv/6+qbQq7Yw6iglVRpVxZalJbIsDHngNPXeCCYina Vwafce3bSUaDwN+kEYD+yilG0s7bOarKULsY2PSU0myt0TSSSFuadTPJCfQMrhyGoPGln6HZMX+ OyIyVd9qp7W1i3UfuFk1G9O7g2Ql11zOFQQzxygXaPZxAAdtN3V4CspmbIeKuQ8xDLP8protzry Zu/DCNgtRJJjoN8aIzA== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI5MDA0OSBTYWx0ZWRfXx3w907TK7inP JSrAcE83pAWy7c0FlqrNjC6cyHk69DA0PGlFBDJVf80t5se8yMSdQxQQhghsiOGuhNQleaEipNp XVdHawi4fgtPCxKF7INmMplv/PYj9qw= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-29_04,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 phishscore=0 bulkscore=0 malwarescore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609290049 The CCI hw_params timing values (thigh, tlow, etc.) are expressed in clock ticks and are only valid at the specific CCI clock rate they were calibrated for. Different I2C modes may be calibrated for different rates, and the single CCI clock is shared by all masters. Turn the timing table into a two-dimensional [rate][mode] matrix so a given rate can carry timing sets for each mode, and select the entry matching the currently running clock rate at init time. The existing per-variant values are moved under their calibrated rate (19.2 MHz for v1/v1.5, 37.5 MHz for v2), no timing values are changed. At this stage the driver only validates the running rate against the table, the timings are only valid at the exact rate they were calibrated for, so if the current rate has no matching entry for a master's mode, fail initialization rather than program incorrect timings. A following patch actively enforces the required rate so this becomes a safety net. Suggested-by: Vladimir Zapolskiy Reviewed-by: Konrad Dybcio Reviewed-by: Vladimir Zapolskiy Signed-off-by: Loic Poulain --- drivers/i2c/busses/i2c-qcom-cci.c | 74 +++++++++++++++++++++++++++++++----= ---- 1 file changed, 59 insertions(+), 15 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qco= m-cci.c index 0a216c4d08114f267c8441925e8811ca64f1a909..1092ce0371429ef64c7cc44cc23= a42ba4c135af5 100644 --- a/drivers/i2c/busses/i2c-qcom-cci.c +++ b/drivers/i2c/busses/i2c-qcom-cci.c @@ -82,6 +82,13 @@ enum { I2C_MODE_STANDARD, I2C_MODE_FAST, I2C_MODE_FAST_PLUS, + NUM_I2C_MODES, +}; + +enum { + CCI_CLK_RATE_19_2MHZ, + CCI_CLK_RATE_37_5MHZ, + NUM_CCI_CLK_RATES, }; =20 enum cci_i2c_queue_t { @@ -117,7 +124,7 @@ struct cci_data { unsigned int num_masters; struct i2c_adapter_quirks quirks; u16 queue_size[NUM_QUEUES]; - struct hw_params params[3]; + struct hw_params params[NUM_CCI_CLK_RATES][NUM_I2C_MODES]; }; =20 struct cci { @@ -127,6 +134,7 @@ struct cci { const struct cci_data *data; struct clk_bulk_data *clocks; int nclocks; + struct clk *cci_clk; struct cci_master master[NUM_MASTERS]; }; =20 @@ -225,7 +233,34 @@ static int cci_halt(struct cci *cci, u8 master_num) return 0; } =20 -static void cci_init(struct cci *cci) +static const unsigned long cci_clk_rates[NUM_CCI_CLK_RATES] =3D { + [CCI_CLK_RATE_19_2MHZ] =3D 19200000, + [CCI_CLK_RATE_37_5MHZ] =3D 37500000, +}; + +static int cci_clk_rate_idx(unsigned long rate) +{ + int i; + + for (i =3D 0; i < NUM_CCI_CLK_RATES; i++) + if (cci_clk_rates[i] =3D=3D rate) + return i; + + return -EINVAL; +} + +static const struct hw_params *cci_get_hw_params(struct cci *cci, int mode) +{ + unsigned long rate =3D clk_get_rate(cci->cci_clk); + int ri =3D cci_clk_rate_idx(rate); + + if (ri >=3D 0 && cci->data->params[ri][mode].thigh) + return &cci->data->params[ri][mode]; + + return NULL; +} + +static int cci_init(struct cci *cci) { u32 val =3D CCI_IRQ_MASK_0_I2C_M0_RD_DONE | CCI_IRQ_MASK_0_I2C_M0_Q0_REPORT | @@ -249,7 +284,12 @@ static void cci_init(struct cci *cci) if (!cci->master[i].cci) continue; =20 - hw =3D &cci->data->params[mode]; + hw =3D cci_get_hw_params(cci, mode); + if (!hw) { + dev_err(cci->dev, "no timing for mode %d at CCI clock %lu Hz\n", + mode, clk_get_rate(cci->cci_clk)); + return -EOPNOTSUPP; + } =20 val =3D hw->thigh << 16 | hw->tlow; writel(val, cci->base + CCI_I2C_Mm_SCL_CTL(i)); @@ -266,6 +306,8 @@ static void cci_init(struct cci *cci) val =3D hw->scl_stretch_en << 8 | hw->trdhld << 4 | hw->tsp; writel(val, cci->base + CCI_I2C_Mm_MISC_CTL(i)); } + + return 0; } =20 static int cci_reset(struct cci *cci) @@ -283,9 +325,7 @@ static int cci_reset(struct cci *cci) return -ETIMEDOUT; } =20 - cci_init(cci); - - return 0; + return cci_init(cci); } =20 static int cci_run_queue(struct cci *cci, u8 master, u8 queue) @@ -488,8 +528,7 @@ static int __maybe_unused cci_resume_runtime(struct dev= ice *dev) if (ret) return ret; =20 - cci_init(cci); - return 0; + return cci_init(cci); } =20 static const struct dev_pm_ops qcom_cci_pm =3D { @@ -570,6 +609,11 @@ static int cci_probe(struct platform_device *pdev) return dev_err_probe(dev, -EINVAL, "not enough clocks in DT\n"); cci->nclocks =3D ret; =20 + cci->cci_clk =3D devm_clk_get(dev, "cci"); + if (IS_ERR(cci->cci_clk)) + return dev_err_probe(dev, PTR_ERR(cci->cci_clk), + "failed to get CCI clock\n"); + ret =3D cci_enable_clocks(cci); if (ret < 0) return ret; @@ -652,7 +696,7 @@ static const struct cci_data cci_v1_data =3D { .max_write_len =3D 10, .max_read_len =3D 12, }, - .params[I2C_MODE_STANDARD] =3D { + .params[CCI_CLK_RATE_19_2MHZ][I2C_MODE_STANDARD] =3D { .thigh =3D 78, .tlow =3D 114, .tsu_sto =3D 28, @@ -664,7 +708,7 @@ static const struct cci_data cci_v1_data =3D { .trdhld =3D 6, .tsp =3D 1 }, - .params[I2C_MODE_FAST] =3D { + .params[CCI_CLK_RATE_19_2MHZ][I2C_MODE_FAST] =3D { .thigh =3D 20, .tlow =3D 28, .tsu_sto =3D 21, @@ -685,7 +729,7 @@ static const struct cci_data cci_v1_5_data =3D { .max_write_len =3D 10, .max_read_len =3D 12, }, - .params[I2C_MODE_STANDARD] =3D { + .params[CCI_CLK_RATE_19_2MHZ][I2C_MODE_STANDARD] =3D { .thigh =3D 78, .tlow =3D 114, .tsu_sto =3D 28, @@ -697,7 +741,7 @@ static const struct cci_data cci_v1_5_data =3D { .trdhld =3D 6, .tsp =3D 1 }, - .params[I2C_MODE_FAST] =3D { + .params[CCI_CLK_RATE_19_2MHZ][I2C_MODE_FAST] =3D { .thigh =3D 20, .tlow =3D 28, .tsu_sto =3D 21, @@ -718,7 +762,7 @@ static const struct cci_data cci_v2_data =3D { .max_write_len =3D 11, .max_read_len =3D 12, }, - .params[I2C_MODE_STANDARD] =3D { + .params[CCI_CLK_RATE_37_5MHZ][I2C_MODE_STANDARD] =3D { .thigh =3D 201, .tlow =3D 174, .tsu_sto =3D 204, @@ -730,7 +774,7 @@ static const struct cci_data cci_v2_data =3D { .trdhld =3D 6, .tsp =3D 3 }, - .params[I2C_MODE_FAST] =3D { + .params[CCI_CLK_RATE_37_5MHZ][I2C_MODE_FAST] =3D { .thigh =3D 38, .tlow =3D 56, .tsu_sto =3D 40, @@ -742,7 +786,7 @@ static const struct cci_data cci_v2_data =3D { .trdhld =3D 6, .tsp =3D 3 }, - .params[I2C_MODE_FAST_PLUS] =3D { + .params[CCI_CLK_RATE_37_5MHZ][I2C_MODE_FAST_PLUS] =3D { .thigh =3D 16, .tlow =3D 22, .tsu_sto =3D 17, --=20 2.34.1 From nobody Fri Oct 2 11:42:46 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4AFED5221CF for ; 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Tue, 29 Sep 2026 05:25:57 -0700 (PDT) Received: from QCOM-eG0v1AUPpu.na.qualcomm.com ([2a01:e0a:830:450:5c1f:3897:a4a1:99e1]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-9178d302482sm9103956d6.12.2026.09.29.05.25.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2026 05:25:57 -0700 (PDT) From: Loic Poulain Date: Tue, 29 Sep 2026 14:25:47 +0200 Subject: [PATCH v6 3/5] i2c: qcom-cci: Add 19.2 MHz timings for the v2 CCI Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260929-cci-clk-fix-v6-3-62a268cccb0f@oss.qualcomm.com> References: <20260929-cci-clk-fix-v6-0-62a268cccb0f@oss.qualcomm.com> In-Reply-To: <20260929-cci-clk-fix-v6-0-62a268cccb0f@oss.qualcomm.com> To: Robert Foss , Andi Shyti , Wolfram Sang , Dmitry Baryshkov , Luca Weiss Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, vladimir.zapolskiy@linaro.org, konradybcio@kernel.org, stephan.gerhold@linaro.org, Loic Poulain , Konrad Dybcio X-Mailer: b4 0.14.2 X-Authority-Analysis: v=2.4 cv=X9fHu2Te c=1 sm=1 tr=0 ts=6abbae57 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=butnsgrUGOw-u3YEFNkA:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: pLOiPKCAA5PuQgU7AGxtfeA9UMUV829j X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI5MDA0OSBTYWx0ZWRfX1d4qC2/0z2xK 6hCaTwByw3TeLgC9ESCIri2Tv4xlx9t7GSZIAf0Wo5S5Hh2JV89IpMV3KyFyhtpVAZCaZMjF/QC RKz2X1sse+kfPWc4uQfUiMtijDWUGU4= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI5MDA0OSBTYWx0ZWRfX++ZT3HVeBTqN B1l9GyKFDL2HSqZ4Plt6cNDedJcF1q8fyVUGIDB776j8clM5+cBuyvM7Y1LHTlpbCCB189grxgV GY1aQ0JKbxzHqMxFcUsBIQf79O7HCOIX0xu3rz1hQSQS9LDdcMtJLQ8nD1qKeOptAfAm5+JhD6q twFNMv8V0h2aoMC7wZYXE72Gpk0vgTf8Q96R2tCTTgeYkL+5yt+9u7fzolkRs+DdUwefW1vO33U nAvtXIMBm/DUilSAA/TyeZJ6crvDlgyx/M7WOCDWfwlc03XB8jLaqA4ip5cgiyu41/ncPktpc9u qTXeS/Ex/o/xpq6SW/rNkfml+n4kZuHiFOG4MM2eE7oFc1asdIY+6hkpjKAwb7DuryWYyzeznc6 NWqTtnyhnXTU8hVkJrKTccJ59TuPdNZUBfhSEdavjmgYVzNUjXedu+Mxplf3HkkHPwlgMc4ii36 JWtJMRA6LWzjX/lD6Og== X-Proofpoint-ORIG-GUID: pLOiPKCAA5PuQgU7AGxtfeA9UMUV829j X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-29_04,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 suspectscore=0 spamscore=0 bulkscore=0 impostorscore=0 phishscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609290049 The v2 CCI (msm8996/sdm630/msm8953/...) is normally clocked at 37.5 MHz, but its CCI clock can also be configured and run at 19.2 MHz. Add the Standard and Fast timing sets calibrated for 19.2 MHz so that a v2 controller left at that rate still has valid timings for those modes (Fast+ requires 37.5 MHz). The values mirror the v1/v1.5 19.2 MHz Standard/Fast timings, which share the same CCI clock rate. Note the "v1"/"v1.5"/"v2" labels are arbitrary driver-internal names for the cci_data configs, not actual CCI hardware version numbers (the real hw versions are e.g. v1.0.7 on msm8974, v1.4.0 on msm8996, v1.6.3 on sdm630/660, ...). They only distinguish the timing/mode configurations used by the driver, and will be subsequently removed. Reviewed-by: Konrad Dybcio Reviewed-by: Vladimir Zapolskiy Signed-off-by: Loic Poulain --- drivers/i2c/busses/i2c-qcom-cci.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qco= m-cci.c index 1092ce0371429ef64c7cc44cc23a42ba4c135af5..b6fa37a306758ec33ede6fcc39c= e4412b86d9a84 100644 --- a/drivers/i2c/busses/i2c-qcom-cci.c +++ b/drivers/i2c/busses/i2c-qcom-cci.c @@ -762,6 +762,30 @@ static const struct cci_data cci_v2_data =3D { .max_write_len =3D 11, .max_read_len =3D 12, }, + .params[CCI_CLK_RATE_19_2MHZ][I2C_MODE_STANDARD] =3D { + .thigh =3D 78, + .tlow =3D 114, + .tsu_sto =3D 28, + .tsu_sta =3D 28, + .thd_dat =3D 10, + .thd_sta =3D 77, + .tbuf =3D 118, + .scl_stretch_en =3D 0, + .trdhld =3D 6, + .tsp =3D 1 + }, + .params[CCI_CLK_RATE_19_2MHZ][I2C_MODE_FAST] =3D { + .thigh =3D 20, + .tlow =3D 28, + .tsu_sto =3D 21, + .tsu_sta =3D 21, + .thd_dat =3D 13, + .thd_sta =3D 18, + .tbuf =3D 32, + .scl_stretch_en =3D 0, + .trdhld =3D 6, + .tsp =3D 3 + }, .params[CCI_CLK_RATE_37_5MHZ][I2C_MODE_STANDARD] =3D { .thigh =3D 201, .tlow =3D 174, --=20 2.34.1 From nobody Fri Oct 2 11:42:46 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2AC9522EF6 for ; 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Only the set of supported modes differs between revisions. Move the timings into a single shared cci_hw_params[rate][mode] table and describe each variant's highest supported mode in cci_data with max_mode instead of duplicating the timing values. This removes the per-variant timing tables without any functional change. Suggested-by: Vladimir Zapolskiy Reviewed-by: Konrad Dybcio Reviewed-by: Vladimir Zapolskiy Signed-off-by: Loic Poulain --- drivers/i2c/busses/i2c-qcom-cci.c | 181 +++++++++++++++-------------------= ---- 1 file changed, 70 insertions(+), 111 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qco= m-cci.c index b6fa37a306758ec33ede6fcc39ce4412b86d9a84..21695c744502f7fb5d333f1272f= 3771e4d9d5508 100644 --- a/drivers/i2c/busses/i2c-qcom-cci.c +++ b/drivers/i2c/busses/i2c-qcom-cci.c @@ -124,7 +124,8 @@ struct cci_data { unsigned int num_masters; struct i2c_adapter_quirks quirks; u16 queue_size[NUM_QUEUES]; - struct hw_params params[NUM_CCI_CLK_RATES][NUM_I2C_MODES]; + /* Highest I2C mode supported by this variant. */ + u8 max_mode; }; =20 struct cci { @@ -249,13 +250,76 @@ static int cci_clk_rate_idx(unsigned long rate) return -EINVAL; } =20 +static const struct hw_params cci_hw_params[NUM_CCI_CLK_RATES][NUM_I2C_MOD= ES] =3D { + [CCI_CLK_RATE_19_2MHZ][I2C_MODE_STANDARD] =3D { + .thigh =3D 78, + .tlow =3D 114, + .tsu_sto =3D 28, + .tsu_sta =3D 28, + .thd_dat =3D 10, + .thd_sta =3D 77, + .tbuf =3D 118, + .scl_stretch_en =3D 0, + .trdhld =3D 6, + .tsp =3D 1 + }, + [CCI_CLK_RATE_19_2MHZ][I2C_MODE_FAST] =3D { + .thigh =3D 20, + .tlow =3D 28, + .tsu_sto =3D 21, + .tsu_sta =3D 21, + .thd_dat =3D 13, + .thd_sta =3D 18, + .tbuf =3D 32, + .scl_stretch_en =3D 0, + .trdhld =3D 6, + .tsp =3D 3 + }, + [CCI_CLK_RATE_37_5MHZ][I2C_MODE_STANDARD] =3D { + .thigh =3D 201, + .tlow =3D 174, + .tsu_sto =3D 204, + .tsu_sta =3D 231, + .thd_dat =3D 22, + .thd_sta =3D 162, + .tbuf =3D 227, + .scl_stretch_en =3D 0, + .trdhld =3D 6, + .tsp =3D 3 + }, + [CCI_CLK_RATE_37_5MHZ][I2C_MODE_FAST] =3D { + .thigh =3D 38, + .tlow =3D 56, + .tsu_sto =3D 40, + .tsu_sta =3D 40, + .thd_dat =3D 22, + .thd_sta =3D 35, + .tbuf =3D 62, + .scl_stretch_en =3D 0, + .trdhld =3D 6, + .tsp =3D 3 + }, + [CCI_CLK_RATE_37_5MHZ][I2C_MODE_FAST_PLUS] =3D { + .thigh =3D 16, + .tlow =3D 22, + .tsu_sto =3D 17, + .tsu_sta =3D 18, + .thd_dat =3D 16, + .thd_sta =3D 15, + .tbuf =3D 24, + .scl_stretch_en =3D 0, + .trdhld =3D 3, + .tsp =3D 3 + }, +}; + static const struct hw_params *cci_get_hw_params(struct cci *cci, int mode) { unsigned long rate =3D clk_get_rate(cci->cci_clk); int ri =3D cci_clk_rate_idx(rate); =20 - if (ri >=3D 0 && cci->data->params[ri][mode].thigh) - return &cci->data->params[ri][mode]; + if (ri >=3D 0 && mode <=3D cci->data->max_mode && cci_hw_params[ri][mode]= .thigh) + return &cci_hw_params[ri][mode]; =20 return NULL; } @@ -696,30 +760,7 @@ static const struct cci_data cci_v1_data =3D { .max_write_len =3D 10, .max_read_len =3D 12, }, - .params[CCI_CLK_RATE_19_2MHZ][I2C_MODE_STANDARD] =3D { - .thigh =3D 78, - .tlow =3D 114, - .tsu_sto =3D 28, - .tsu_sta =3D 28, - .thd_dat =3D 10, - .thd_sta =3D 77, - .tbuf =3D 118, - .scl_stretch_en =3D 0, - .trdhld =3D 6, - .tsp =3D 1 - }, - .params[CCI_CLK_RATE_19_2MHZ][I2C_MODE_FAST] =3D { - .thigh =3D 20, - .tlow =3D 28, - .tsu_sto =3D 21, - .tsu_sta =3D 21, - .thd_dat =3D 13, - .thd_sta =3D 18, - .tbuf =3D 32, - .scl_stretch_en =3D 0, - .trdhld =3D 6, - .tsp =3D 3 - }, + .max_mode =3D I2C_MODE_FAST, }; =20 static const struct cci_data cci_v1_5_data =3D { @@ -729,30 +770,7 @@ static const struct cci_data cci_v1_5_data =3D { .max_write_len =3D 10, .max_read_len =3D 12, }, - .params[CCI_CLK_RATE_19_2MHZ][I2C_MODE_STANDARD] =3D { - .thigh =3D 78, - .tlow =3D 114, - .tsu_sto =3D 28, - .tsu_sta =3D 28, - .thd_dat =3D 10, - .thd_sta =3D 77, - .tbuf =3D 118, - .scl_stretch_en =3D 0, - .trdhld =3D 6, - .tsp =3D 1 - }, - .params[CCI_CLK_RATE_19_2MHZ][I2C_MODE_FAST] =3D { - .thigh =3D 20, - .tlow =3D 28, - .tsu_sto =3D 21, - .tsu_sta =3D 21, - .thd_dat =3D 13, - .thd_sta =3D 18, - .tbuf =3D 32, - .scl_stretch_en =3D 0, - .trdhld =3D 6, - .tsp =3D 3 - }, + .max_mode =3D I2C_MODE_FAST, }; =20 static const struct cci_data cci_v2_data =3D { @@ -762,66 +780,7 @@ static const struct cci_data cci_v2_data =3D { .max_write_len =3D 11, .max_read_len =3D 12, }, - .params[CCI_CLK_RATE_19_2MHZ][I2C_MODE_STANDARD] =3D { - .thigh =3D 78, - .tlow =3D 114, - .tsu_sto =3D 28, - .tsu_sta =3D 28, - .thd_dat =3D 10, - .thd_sta =3D 77, - .tbuf =3D 118, - .scl_stretch_en =3D 0, - .trdhld =3D 6, - .tsp =3D 1 - }, - .params[CCI_CLK_RATE_19_2MHZ][I2C_MODE_FAST] =3D { - .thigh =3D 20, - .tlow =3D 28, - .tsu_sto =3D 21, - .tsu_sta =3D 21, - .thd_dat =3D 13, - .thd_sta =3D 18, - .tbuf =3D 32, - .scl_stretch_en =3D 0, - .trdhld =3D 6, - .tsp =3D 3 - }, - .params[CCI_CLK_RATE_37_5MHZ][I2C_MODE_STANDARD] =3D { - .thigh =3D 201, - .tlow =3D 174, - .tsu_sto =3D 204, - .tsu_sta =3D 231, - .thd_dat =3D 22, - .thd_sta =3D 162, - .tbuf =3D 227, - .scl_stretch_en =3D 0, - .trdhld =3D 6, - .tsp =3D 3 - }, - .params[CCI_CLK_RATE_37_5MHZ][I2C_MODE_FAST] =3D { - .thigh =3D 38, - .tlow =3D 56, - .tsu_sto =3D 40, - .tsu_sta =3D 40, - .thd_dat =3D 22, - .thd_sta =3D 35, - .tbuf =3D 62, - .scl_stretch_en =3D 0, - .trdhld =3D 6, - .tsp =3D 3 - }, - .params[CCI_CLK_RATE_37_5MHZ][I2C_MODE_FAST_PLUS] =3D { - .thigh =3D 16, - .tlow =3D 22, - .tsu_sto =3D 17, - .tsu_sta =3D 18, - .thd_dat =3D 16, - .thd_sta =3D 15, - .tbuf =3D 24, - .scl_stretch_en =3D 0, - .trdhld =3D 3, - .tsp =3D 3 - }, + .max_mode =3D I2C_MODE_FAST_PLUS, }; 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Tue, 29 Sep 2026 05:26:02 -0700 (PDT) X-Received: by 2002:a0c:e093:0:b0:915:eacb:cb94 with SMTP id 6a1803df08f44-915eacbcfa8mr100823696d6.6.1790684761954; Tue, 29 Sep 2026 05:26:01 -0700 (PDT) Received: from QCOM-eG0v1AUPpu.na.qualcomm.com ([2a01:e0a:830:450:5c1f:3897:a4a1:99e1]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-9178d302482sm9103956d6.12.2026.09.29.05.26.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2026 05:26:01 -0700 (PDT) From: Loic Poulain Date: Tue, 29 Sep 2026 14:25:49 +0200 Subject: [PATCH v6 5/5] i2c: qcom-cci: Enforce the required CCI clock rate Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260929-cci-clk-fix-v6-5-62a268cccb0f@oss.qualcomm.com> References: <20260929-cci-clk-fix-v6-0-62a268cccb0f@oss.qualcomm.com> In-Reply-To: <20260929-cci-clk-fix-v6-0-62a268cccb0f@oss.qualcomm.com> To: Robert Foss , Andi Shyti , Wolfram Sang , Dmitry Baryshkov , Luca Weiss Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, vladimir.zapolskiy@linaro.org, konradybcio@kernel.org, stephan.gerhold@linaro.org, Loic Poulain , Konrad Dybcio X-Mailer: b4 0.14.2 X-Proofpoint-ORIG-GUID: USewHd_J5xdaIU6NfxXQp0h_nDOpr38g X-Proofpoint-GUID: USewHd_J5xdaIU6NfxXQp0h_nDOpr38g X-Authority-Analysis: v=2.4 cv=Z+55j3RA c=1 sm=1 tr=0 ts=6abbae5b cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=raeIKTHvMkgTF1qzT8sA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI5MDA0OSBTYWx0ZWRfXwrVDGIW9CDh0 1S4vQ84DdOyfrF20EbbDVhaveb2xI2Yv3GnMb40Lpi8tBy/o7HGluthYuMLjD6fdRYm9rt73Rt3 DyMcIu7en+2UbRognDj49eI0qk8LWZUpNI8NMqmNP2+bUHI8r38Zbs1A7RsksdO7o4eBax5+MgD wojRYInW+C90U41Da4N75WL80CGKYhQEFhQEzHrizK9bGIf6LGk0OisSyuZEa6z/wKZNItFkf6f My2Vylh9PXbLygMNygL1OHWpZwhVcdUkKkiz9TszzECjYBSEGVqwzDvt0oNj+40pC8pt4qGRacp DTpPDsIy0FQBgr/3pL+lixiqN/dHYhurDQc1cHwatvMieNqINRO1tWluK4ZwtciDoR45w16VsAi +VZu4T+XNe2Kbd4qRQotbPT9hsebqrUJr1jluvMIls3FbN8CHoKsauXh8/W2ot4huOUds3G4XpC 1pP9fqISX/lu6ROFk3Q== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI5MDA0OSBTYWx0ZWRfXy+OUPydg5Yjs sCqb8s96PttRbtNUVOOfKT+0wIkmupqIzHRSITd//CV8BA7OgBM00Yc25DEoXljUaQ2oX7jLaU1 b33jE84dp5mXvsbenzAP9tUQ0uJVyLQ= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-29_04,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 phishscore=0 bulkscore=0 malwarescore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609290049 The CCI hw_params timing values are only valid at the specific clock rate they were calibrated for. A previous change made the driver select the timing set matching the currently running clock rate, but the rate itself was still left to the DT (assigned-clock-rates) or the bootloader, which is fragile: if no rate is enforced the timings may not match and violate the I2C specification. Actively drive the CCI clock to the rate required by the configured modes. The single CCI clock is shared by all masters, which may run in different modes, so cci_get_required_rate() picks the lowest rate that has a valid timing set for every active master's mode. This avoids clocking the bus faster than necessary while still satisfying every master (e.g. a Fast+ master forces 37.5 MHz). Apply the rate through the OPP framework so that boards describing an opp table also get the required power-domain/regulator votes for that rate. Boards without an OPP table simply fall back to plain clk_set_rate() behavior, so existing DTs keep working. Drop the now-redundant hw_params[].thigh check in cci_get_hw_params(), cci_get_required_rate() already rejects rates lacking a valid timing set for an active master's mode. Suggested-by: Konrad Dybcio Signed-off-by: Loic Poulain --- drivers/i2c/busses/Kconfig | 1 + drivers/i2c/busses/i2c-qcom-cci.c | 76 +++++++++++++++++++++++++++++++++++= +++- 2 files changed, 76 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index d7b89508311ffc6cbe1ccd302a6e84dfa83bf6fe..14eb7e802bc86a06b7ec0688580= 886880026cb0e 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -1050,6 +1050,7 @@ config I2C_PXA_SLAVE config I2C_QCOM_CCI tristate "Qualcomm Camera Control Interface" depends on ARCH_QCOM || COMPILE_TEST + select PM_OPP help If you say yes to this option, support will be included for the built-in camera control interface on the Qualcomm SoCs. diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qco= m-cci.c index 21695c744502f7fb5d333f1272f3771e4d9d5508..526a699eee147996b2756b47c0e= 6982678990be0 100644 --- a/drivers/i2c/busses/i2c-qcom-cci.c +++ b/drivers/i2c/busses/i2c-qcom-cci.c @@ -11,6 +11,7 @@ #include #include #include +#include =20 #define CCI_HW_VERSION 0x0 #define CCI_RESET_CMD 0x004 @@ -318,7 +319,7 @@ static const struct hw_params *cci_get_hw_params(struct= cci *cci, int mode) unsigned long rate =3D clk_get_rate(cci->cci_clk); int ri =3D cci_clk_rate_idx(rate); =20 - if (ri >=3D 0 && mode <=3D cci->data->max_mode && cci_hw_params[ri][mode]= .thigh) + if (ri >=3D 0 && mode <=3D cci->data->max_mode) return &cci_hw_params[ri][mode]; =20 return NULL; @@ -575,6 +576,66 @@ static void cci_disable_clocks(struct cci *cci) clk_bulk_disable_unprepare(cci->nclocks, cci->clocks); } =20 +/* + * The single CCI clock is shared by all masters, which may run in differe= nt + * modes. Pick the lowest rate that has a valid timing set for every active + * master's mode. + */ +static int cci_get_required_rate(struct cci *cci, unsigned long *rate) +{ + for (int ri =3D 0; ri < NUM_CCI_CLK_RATES; ri++) { + bool supported =3D true; + + for (int i =3D 0; i < cci->data->num_masters; i++) { + int mode =3D cci->master[i].mode; + + if (!cci->master[i].cci) + continue; + + if (mode > cci->data->max_mode || + !cci_hw_params[ri][mode].thigh) { + supported =3D false; + break; + } + } + + if (supported) { + *rate =3D cci_clk_rates[ri]; + return 0; + } + } + + return -EOPNOTSUPP; +} + +static int cci_set_core_rate(struct cci *cci) +{ + struct device *dev =3D cci->dev; + unsigned long rate; + int ret; + + ret =3D cci_get_required_rate(cci, &rate); + if (ret) { + dev_err(dev, "no CCI clock rate satisfies all masters\n"); + return ret; + } + + ret =3D dev_pm_opp_set_rate(dev, rate); + if (ret) { + dev_err(dev, "CCI clock could not be set to %lu Hz\n", rate); + return ret; + } + + /* + * Sanity: The hw_params timings are only valid at the exact + * expected rate, verify what landed on the hardware. + */ + if (clk_get_rate(cci->cci_clk) !=3D rate) + dev_warn(dev, "CCI clock is not at expected %lu Hz\n", rate); + + return 0; +} + static int __maybe_unused cci_suspend_runtime(struct device *dev) { struct cci *cci =3D dev_get_drvdata(dev); @@ -678,6 +739,19 @@ static int cci_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(cci->cci_clk), "failed to get CCI clock\n"); =20 + ret =3D devm_pm_opp_set_clkname(dev, "cci"); + if (ret) + return dev_err_probe(dev, ret, "failed to set CCI OPP clk\n"); + + /* OPP table is optional */ + ret =3D devm_pm_opp_of_add_table(dev); + if (ret && ret !=3D -ENODEV) + return dev_err_probe(dev, ret, "failed to add OPP table\n"); + + ret =3D cci_set_core_rate(cci); + if (ret) + return ret; + ret =3D cci_enable_clocks(cci); if (ret < 0) return ret; --=20 2.34.1