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[82.57.191.234]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-48af071532dsm1527706f8f.20.2026.09.28.12.45.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 12:45:54 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean , Matthias Brugger , AngeloGioacchino Del Regno , "Chester A. Unal" , Daniel Golle , Heiner Kallweit , Russell King , Simon Horman , Joris Vaisvila , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v24 01/10] dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch Date: Mon, 28 Sep 2026 21:45:00 +0200 Message-ID: <20260928194511.41878-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260928194511.41878-1-ansuelsmth@gmail.com> References: <20260928194511.41878-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document support for Airoha AN8855 5-port Gigabit Switch. It does expose the 5 Internal PHYs on the MDIO bus and each port can access the Switch register space by configuring the PHY page. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring (Arm) --- .../net/dsa/airoha,an8855-switch.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dsa/airoha,an8855= -switch.yaml diff --git a/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch= .yaml b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml new file mode 100644 index 000000000000..5ad9b9e13983 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/airoha,an8855-switch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN8855 Gigabit Switch + +maintainers: + - Christian Marangi + +description: > + Airoha AN8855 is a 5-port Gigabit Switch. + + It does expose the 5 Internal PHYs on the MDIO bus and each port + can access the Switch register space by configuring the PHY page. + +$ref: dsa.yaml#/$defs/ethernet-ports + +properties: + compatible: + const: airoha,an8855-switch + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + ethernet-switch { + compatible =3D "airoha,an8855-switch"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + label =3D "lan1"; + phy-mode =3D "internal"; + phy-handle =3D <&internal_phy1>; + }; + + port@1 { + reg =3D <1>; + label =3D "lan2"; + phy-mode =3D "internal"; + phy-handle =3D <&internal_phy2>; + }; + + port@2 { + reg =3D <2>; + label =3D "lan3"; + phy-mode =3D "internal"; + phy-handle =3D <&internal_phy3>; + }; + + port@3 { + reg =3D <3>; + label =3D "lan4"; + phy-mode =3D "internal"; + phy-handle =3D <&internal_phy4>; + }; + + port@4 { + reg =3D <4>; + label =3D "wan"; + phy-mode =3D "internal"; + phy-handle =3D <&internal_phy5>; + }; + + port@5 { + reg =3D <5>; + label =3D "cpu"; + ethernet =3D <&gmac0>; + phy-mode =3D "2500base-x"; + + fixed-link { + speed =3D <2500>; + full-duplex; + pause; + }; + }; + }; + }; --=20 2.55.0 From nobody Mon Sep 28 21:52:21 2026 Received: from mail-wr2-f12.google.com (mail-wr2-f12.google.com [74.125.225.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 522D34F5E1E for ; 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[82.57.191.234]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-48af071532dsm1527706f8f.20.2026.09.28.12.45.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 12:45:56 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean , Matthias Brugger , AngeloGioacchino Del Regno , "Chester A. Unal" , Daniel Golle , Heiner Kallweit , Russell King , Simon Horman , Joris Vaisvila , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v24 02/10] dt-bindings: net: Document support for AN8855 Switch Internal PHY Date: Mon, 28 Sep 2026 21:45:01 +0200 Message-ID: <20260928194511.41878-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260928194511.41878-1-ansuelsmth@gmail.com> References: <20260928194511.41878-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document support for AN8855 Switch Internal PHY. Airoha AN8855 is a 5-port Gigabit Switch that expose the Internal PHYs on the MDIO bus. Each PHY might need to be calibrated to correctly work with the use of the eFUSE provided by the Switch SoC. This can be enabled by defining in the PHY node the NVMEM cell properties. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring (Arm) --- .../bindings/net/airoha,an8855-phy.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/airoha,an8855-phy= .yaml diff --git a/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml b= /Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml new file mode 100644 index 000000000000..d2f86116badf --- /dev/null +++ b/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/airoha,an8855-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN8855 Switch Internal PHY + +maintainers: + - Christian Marangi + +description: > + Airoha AN8855 is a 5-port Gigabit Switch that expose the Internal + PHYs on the MDIO bus. + + Each PHY might need to be calibrated to correctly work with the + use of the eFUSE provided by the Switch SoC. + +allOf: + - $ref: ethernet-phy.yaml# + +select: + properties: + compatible: + contains: + enum: + - ethernet-phy-idc0ff.0410 + required: + - compatible + +properties: + reg: + maxItems: 1 + + nvmem-cells: + items: + - description: phandle to SoC eFUSE tx_a + - description: phandle to SoC eFUSE tx_b + - description: phandle to SoC eFUSE tx_c + - description: phandle to SoC eFUSE tx_d + + nvmem-cell-names: + items: + - const: tx_a + - const: tx_b + - const: tx_c + - const: tx_d + +required: + - compatible + - reg + +dependentRequired: + nvmem-cells: [ nvmem-cell-names ] + +unevaluatedProperties: false + +examples: + - | + mdio { + #address-cells =3D <1>; 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[82.57.191.234]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-48af071532dsm1527706f8f.20.2026.09.28.12.45.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 12:45:59 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean , Matthias Brugger , AngeloGioacchino Del Regno , "Chester A. Unal" , Daniel Golle , Heiner Kallweit , Russell King , Simon Horman , Joris Vaisvila , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v24 03/10] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC Date: Mon, 28 Sep 2026 21:45:02 +0200 Message-ID: <20260928194511.41878-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260928194511.41878-1-ansuelsmth@gmail.com> References: <20260928194511.41878-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document support for Airoha AN8855 Switch SoC. This SoC expose various peripherals like an Ethernet Switch, a NVMEM provider and Ethernet PHYs. It does also support i2c and timers but those are not currently supported/used. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring (Arm) --- .../bindings/mfd/airoha,an8855.yaml | 176 ++++++++++++++++++ 1 file changed, 176 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/airoha,an8855.yaml diff --git a/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml b/Doc= umentation/devicetree/bindings/mfd/airoha,an8855.yaml new file mode 100644 index 000000000000..48127e956c96 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml @@ -0,0 +1,176 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/airoha,an8855.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN8855 Switch SoC + +maintainers: + - Christian Marangi + +description: > + Airoha AN8855 Switch is a SoC that expose various peripherals like an + Ethernet Switch, a NVMEM provider and Ethernet PHYs. + + It does also support i2c and timers but those are not currently + supported/used. + +properties: + compatible: + const: airoha,an8855 + + reg: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + efuse: + type: object + $ref: /schemas/nvmem/airoha,an8855-efuse.yaml + description: EFUSE exposed by the Airoha AN8855 SoC + + ethernet-switch: + type: object + $ref: /schemas/net/dsa/airoha,an8855-switch.yaml + description: Switch exposed by the Airoha AN8855 SoC + + mdio: + type: object + $ref: /schemas/net/mdio.yaml# + description: MDIO exposed by the Airoha AN8855 SoC + unevaluatedProperties: false + +required: + - compatible + - reg + - mdio + - ethernet-switch + +additionalProperties: false + +examples: + - | + #include + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + soc@1 { + compatible =3D "airoha,an8855"; + reg =3D <1>; + + reset-gpios =3D <&pio 39 GPIO_ACTIVE_HIGH>; + + efuse { + compatible =3D "airoha,an8855-efuse"; + + #nvmem-cell-cells =3D <0>; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + shift_sel_port0_tx_a: shift-sel-port0-tx-a@c { + reg =3D <0xc 0x4>; + }; + + shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 { + reg =3D <0x10 0x4>; + }; + + shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 { + reg =3D <0x14 0x4>; + }; + + shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 { + reg =3D <0x18 0x4>; + }; + + shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c { + reg =3D <0x1c 0x4>; + }; + + shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 { + reg =3D <0x20 0x4>; + }; + + shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 { + reg =3D <0x24 0x4>; + }; + + shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 { + reg =3D <0x28 0x4>; + }; + }; + }; + + ethernet-switch { + compatible =3D "airoha,an8855-switch"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + label =3D "lan1"; + phy-mode =3D "internal"; + phy-handle =3D <&internal_phy1>; + }; + + port@1 { + reg =3D <1>; + label =3D "lan2"; + phy-mode =3D "internal"; + phy-handle =3D <&internal_phy2>; + }; + + port@5 { + reg =3D <5>; + label =3D "cpu"; + ethernet =3D <&gmac0>; + phy-mode =3D "2500base-x"; + + fixed-link { + speed =3D <2500>; + full-duplex; + pause; + }; + }; + }; + }; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + internal_phy1: ethernet-phy@1 { + compatible =3D "ethernet-phy-idc0ff.0410", + "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + + nvmem-cells =3D <&shift_sel_port0_tx_a>, + <&shift_sel_port0_tx_b>, + <&shift_sel_port0_tx_c>, + <&shift_sel_port0_tx_d>; + nvmem-cell-names =3D "tx_a", "tx_b", "tx_c", "tx_d"; + }; + + internal_phy2: ethernet-phy@2 { + compatible =3D "ethernet-phy-idc0ff.0410", + "ethernet-phy-ieee802.3-c22"; + reg =3D <2>; + + nvmem-cells =3D <&shift_sel_port1_tx_a>, + <&shift_sel_port1_tx_b>, + <&shift_sel_port1_tx_c>, + <&shift_sel_port1_tx_d>; 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[82.57.191.234]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-48af071532dsm1527706f8f.20.2026.09.28.12.46.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 12:46:02 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean , Matthias Brugger , AngeloGioacchino Del Regno , "Chester A. Unal" , Daniel Golle , Heiner Kallweit , Russell King , Simon Horman , Joris Vaisvila , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v24 04/10] mfd: an8855: Add support for Airoha AN8855 Switch Date: Mon, 28 Sep 2026 21:45:03 +0200 Message-ID: <20260928194511.41878-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260928194511.41878-1-ansuelsmth@gmail.com> References: <20260928194511.41878-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for Airoha AN8855 Switch that provide support for a DSA switch and a NVMEM provider. Also make use of the mdio-regmap driver and register a regmap for each internal PHY of the switch. This is needed to handle the double usage of the PHYs as both PHY and Switch accessor. Signed-off-by: Christian Marangi --- drivers/mfd/Kconfig | 14 + drivers/mfd/Makefile | 1 + drivers/mfd/airoha-an8855.c | 579 ++++++++++++++++++++++++++++++++++++ 3 files changed, 594 insertions(+) create mode 100644 drivers/mfd/airoha-an8855.c diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index e4fd4572472f..afbdcec0fce8 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -54,6 +54,20 @@ config MFD_ALTERA_SYSMGR using regmap_mmio accesses for ARM32 parts and SMC calls to EL3 for ARM64 parts. =20 +config MFD_AIROHA_AN8855 + tristate "Airoha AN8855 Switch Core" + select MFD_CORE + select REGMAP + select PHYLIB + select MDIO_REGMAP + depends on NETDEVICES && OF + help + Support for the Airoha AN8855 Switch Core. This is an SoC + that provides various peripherals, to count, i2c, an Ethrnet + Switch, a CPU timer, GPIO, eFUSE. + + Currently it provides a DSA switch and a NVMEM provider. + config MFD_ACT8945A tristate "Active-semi ACT8945A" select MFD_CORE diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 72d3944b0ad8..484127dba2ad 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_MFD_88PM860X) +=3D 88pm860x.o obj-$(CONFIG_MFD_88PM800) +=3D 88pm800.o 88pm80x.o obj-$(CONFIG_MFD_88PM805) +=3D 88pm805.o 88pm80x.o obj-$(CONFIG_MFD_88PM886_PMIC) +=3D 88pm886.o +obj-$(CONFIG_MFD_AIROHA_AN8855) +=3D airoha-an8855.o obj-$(CONFIG_MFD_ACT8945A) +=3D act8945a.o obj-$(CONFIG_MFD_SM501) +=3D sm501.o obj-$(CONFIG_ARCH_BCM2835) +=3D bcm2835-pm.o diff --git a/drivers/mfd/airoha-an8855.c b/drivers/mfd/airoha-an8855.c new file mode 100644 index 000000000000..cd5791ef436d --- /dev/null +++ b/drivers/mfd/airoha-an8855.c @@ -0,0 +1,579 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Core driver for Airoha AN8855 Switch + * + * Copyright (C) 2024 Christian Marangi + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Register for HW trap status */ +#define AN8855_HWTRAP 0x1000009c + +/* + * Register of the Switch ID + * (called Project ID in Documentation) + */ +#define AN8855_CREV 0x10005000 +#define AN8855_ID 0x8855 /* Switch ID */ + +/* Register for GPHY Power Down + * Used to Toggle the Gigabit PHY power and enable them. + */ +#define AN8855_RG_GPHY_AFE_PWD 0x1028c840 + +/* MII Registers */ +#define AN8855_PHY_SELECT_PAGE 0x1f +#define AN8855_PHY_PAGE GENMASK(2, 0) +#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0) +#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1) +#define AN8855_PHY_PAGE_EXTENDED_4 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x4) + +/* MII Registers Page 4 */ +#define AN8855_PBUS_MODE 0x10 +#define AN8855_PBUS_MODE_ADDR_FIXED 0x0 +#define AN8855_PBUS_MODE_ADDR_INCR BIT(15) +#define AN8855_PBUS_WR_ADDR_HIGH 0x11 +#define AN8855_PBUS_WR_ADDR_LOW 0x12 +#define AN8855_PBUS_WR_DATA_HIGH 0x13 +#define AN8855_PBUS_WR_DATA_LOW 0x14 +#define AN8855_PBUS_RD_ADDR_HIGH 0x15 +#define AN8855_PBUS_RD_ADDR_LOW 0x16 +#define AN8855_PBUS_RD_DATA_HIGH 0x17 +#define AN8855_PBUS_RD_DATA_LOW 0x18 + +#define AN8855_MAX_PHY_PORT 5 + +struct an8855_core_priv { + struct mii_bus *bus; + struct mii_bus *phy_bus; + unsigned int switch_addr; + u16 current_page; +}; + +struct an8855_phy_priv { + u8 addr; + struct an8855_core_priv *core; +}; + +struct an8855_phy_bus { + struct mii_bus *bus; + struct fwnode_handle *node; + u8 addr; +}; + +static const struct mfd_cell an8855_cells[] =3D { + MFD_CELL_OF("an8855-efuse", NULL, NULL, 0, 0, + "airoha,an8855-efuse"), + MFD_CELL_OF("an8855-switch", NULL, NULL, 0, 0, + "airoha,an8855-switch"), +}; + +static int an8855_mii_set_page(struct an8855_core_priv *priv, u8 addr, + u8 page) __must_hold(&priv->bus->mdio_lock) +{ + struct mii_bus *bus =3D priv->bus; + int ret; + + ret =3D __mdiobus_write(bus, addr, AN8855_PHY_SELECT_PAGE, page); + if (ret) { + dev_err_ratelimited(&bus->dev, "failed to set mii page\n"); + return ret; + } + + /* Cache current page if next MII read/write is for Switch page */ + priv->current_page =3D page; + return 0; +} + +static int an8855_mii_read32(struct mii_bus *bus, u8 phy_id, u32 reg, + u32 *val) __must_hold(&bus->mdio_lock) +{ + int lo, hi, ret; + + ret =3D __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE, + AN8855_PBUS_MODE_ADDR_FIXED); + if (ret) + goto err; + + ret =3D __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_HIGH, + upper_16_bits(reg)); + if (ret) + goto err; + + ret =3D __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_LOW, + lower_16_bits(reg)); + if (ret) + goto err; + + hi =3D __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_HIGH); + if (hi < 0) { + ret =3D hi; + goto err; + } + + lo =3D __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_LOW); + if (lo < 0) { + ret =3D lo; + goto err; + } + + *val =3D ((u32)hi << 16) | lo; + + return 0; +err: + dev_err_ratelimited(&bus->dev, "failed to read register\n"); + return ret; +} + +/* + * Protect concurrent access to phy page if switch address also + * expose a PHY. + */ +static void an8855_regmap_lock(struct an8855_core_priv *priv) +{ + if (priv->phy_bus) + mutex_lock(&priv->phy_bus->mdio_lock); + mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); +} + +static void an8855_regmap_unlock(struct an8855_core_priv *priv) +{ + mutex_unlock(&priv->bus->mdio_lock); + if (priv->phy_bus) + mutex_unlock(&priv->phy_bus->mdio_lock); +} + +static int an8855_regmap_read(void *ctx, uint32_t reg, uint32_t *val) +{ + struct an8855_core_priv *priv =3D ctx; + struct mii_bus *bus =3D priv->bus; + u16 addr =3D priv->switch_addr; + int ret; + + an8855_regmap_lock(priv); + ret =3D an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4); + if (ret < 0) + goto exit; + + ret =3D an8855_mii_read32(bus, addr, reg, val); + +exit: + an8855_regmap_unlock(priv); + + return ret < 0 ? ret : 0; +} + +static int an8855_mii_write32(struct mii_bus *bus, u8 phy_id, u32 reg, + u32 val) __must_hold(&bus->mdio_lock) +{ + int ret; + + ret =3D __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE, + AN8855_PBUS_MODE_ADDR_FIXED); + if (ret) + goto err; + + ret =3D __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_HIGH, + upper_16_bits(reg)); + if (ret) + goto err; + ret =3D __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_LOW, + lower_16_bits(reg)); + if (ret) + goto err; + + ret =3D __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_HIGH, + upper_16_bits(val)); + if (ret) + goto err; + + ret =3D __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_LOW, + lower_16_bits(val)); + if (ret) + goto err; + + return 0; +err: + dev_err_ratelimited(&bus->dev, + "failed to write an8855 register\n"); + return ret; +} + +static int an8855_regmap_write(void *ctx, uint32_t reg, uint32_t val) +{ + struct an8855_core_priv *priv =3D ctx; + struct mii_bus *bus =3D priv->bus; + u16 addr =3D priv->switch_addr; + int ret; + + an8855_regmap_lock(priv); + ret =3D an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4); + if (ret) + goto exit; + + ret =3D an8855_mii_write32(bus, addr, reg, val); + +exit: + an8855_regmap_unlock(priv); + + return ret < 0 ? ret : 0; +} + +static int an8855_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mas= k, + uint32_t write_val) +{ + struct an8855_core_priv *priv =3D ctx; + struct mii_bus *bus =3D priv->bus; + u16 addr =3D priv->switch_addr; + u32 val; + int ret; + + an8855_regmap_lock(priv); + ret =3D an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4); + if (ret) + goto exit; + + ret =3D an8855_mii_read32(bus, addr, reg, &val); + if (ret < 0) + goto exit; + + val &=3D ~mask; + val |=3D write_val & mask; + ret =3D an8855_mii_write32(bus, addr, reg, val); + +exit: + an8855_regmap_unlock(priv); + + return ret < 0 ? ret : 0; +} + +static const struct regmap_range an8855_readable_ranges[] =3D { + regmap_reg_range(0x10000000, 0x10000fff), /* SCU */ + regmap_reg_range(0x10001000, 0x10001fff), /* RBUS */ + regmap_reg_range(0x10002000, 0x10002fff), /* MCU */ + regmap_reg_range(0x10005000, 0x10005fff), /* SYS SCU */ + regmap_reg_range(0x10007000, 0x10007fff), /* I2C Slave */ + regmap_reg_range(0x10008000, 0x10008fff), /* I2C Master */ + regmap_reg_range(0x10009000, 0x10009fff), /* PDMA */ + regmap_reg_range(0x1000a100, 0x1000a2ff), /* General Purpose Timer */ + regmap_reg_range(0x1000a200, 0x1000a2ff), /* GPU timer */ + regmap_reg_range(0x1000a300, 0x1000a3ff), /* GPIO */ + regmap_reg_range(0x1000a400, 0x1000a5ff), /* EFUSE */ + regmap_reg_range(0x1000c000, 0x1000cfff), /* GDMP CSR */ + regmap_reg_range(0x10010000, 0x1001ffff), /* GDMP SRAM */ + regmap_reg_range(0x10200000, 0x10203fff), /* Switch - ARL Global */ + regmap_reg_range(0x10204000, 0x10207fff), /* Switch - BMU */ + regmap_reg_range(0x10208000, 0x1020bfff), /* Switch - ARL Port */ + regmap_reg_range(0x1020c000, 0x1020cfff), /* Switch - SCH */ + regmap_reg_range(0x10210000, 0x10213fff), /* Switch - MAC */ + regmap_reg_range(0x10214000, 0x10217fff), /* Switch - MIB */ + regmap_reg_range(0x10218000, 0x1021bfff), /* Switch - Port Control */ + regmap_reg_range(0x1021c000, 0x1021ffff), /* Switch - TOP */ + regmap_reg_range(0x10220000, 0x1022ffff), /* SerDes */ + regmap_reg_range(0x10286000, 0x10286fff), /* RG Batcher */ + regmap_reg_range(0x1028c000, 0x1028ffff), /* ETHER_SYS */ + regmap_reg_range(0x30000000, 0x37ffffff), /* I2C EEPROM */ + regmap_reg_range(0x38000000, 0x3fffffff), /* BOOT_ROM */ + regmap_reg_range(0xa0000000, 0xbfffffff), /* GPHY */ +}; + +static const struct regmap_access_table an8855_readable_table =3D { + .yes_ranges =3D an8855_readable_ranges, + .n_yes_ranges =3D ARRAY_SIZE(an8855_readable_ranges), +}; + +static const struct regmap_config an8855_regmap_config =3D { + .name =3D "switch", + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D 0xbfffffff, + .reg_read =3D an8855_regmap_read, + .reg_write =3D an8855_regmap_write, + .reg_update_bits =3D an8855_regmap_update_bits, + .disable_locking =3D true, + .rd_table =3D &an8855_readable_table, +}; + +static int an8855_regmap_phy_reset_page(struct an8855_core_priv *priv, + int phy) __must_hold(&priv->bus->mdio_lock) +{ + /* Check PHY page only for addr shared with switch */ + if (phy !=3D priv->switch_addr) + return 0; + + /* Don't restore page if it's not set to Switch page */ + if (priv->current_page !=3D AN8855_PHY_PAGE_EXTENDED_4) + return 0; + + /* + * Restore page to 0, PHY might change page right after but that + * will be ignored as it won't be a switch page. + */ + return an8855_mii_set_page(priv, phy, AN8855_PHY_PAGE_STANDARD); +} + +static int an8855_regmap_phy_read(void *ctx, uint32_t reg, uint32_t *val) +{ + struct an8855_phy_priv *priv =3D ctx; + struct an8855_core_priv *core_priv; + u32 addr =3D priv->addr; + struct mii_bus *bus; + int ret; + + core_priv =3D priv->core; + bus =3D core_priv->bus; + + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + ret =3D an8855_regmap_phy_reset_page(core_priv, addr); + if (ret) + goto exit; + + ret =3D __mdiobus_read(bus, addr, reg); + if (ret >=3D 0) + *val =3D ret; + +exit: + mutex_unlock(&bus->mdio_lock); + + return ret < 0 ? ret : 0; +} + +static int an8855_regmap_phy_write(void *ctx, uint32_t reg, uint32_t val) +{ + struct an8855_phy_priv *priv =3D ctx; + struct an8855_core_priv *core_priv; + u32 addr =3D priv->addr; + struct mii_bus *bus; + int ret; + + core_priv =3D priv->core; + bus =3D core_priv->bus; + + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + ret =3D an8855_regmap_phy_reset_page(core_priv, addr); + if (ret) + goto exit; + + ret =3D __mdiobus_write(bus, addr, reg, val); + +exit: + mutex_unlock(&bus->mdio_lock); + + return ret; +} + +static const struct regmap_config an8855_phy_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 16, + .reg_read =3D an8855_regmap_phy_read, + .reg_write =3D an8855_regmap_phy_write, + .disable_locking =3D true, + .max_register =3D 0x1f, +}; + +static int an8855_read_switch_id(struct device *dev, struct regmap *regmap) +{ + u32 id; + int ret; + + ret =3D regmap_read(regmap, AN8855_CREV, &id); + if (ret) + return ret; + + if (id !=3D AN8855_ID) { + dev_err(dev, "Detected Switch ID %x but %x was expected\n", + id, AN8855_ID); + return -ENODEV; + } + + return 0; +} + +static int an8855_phy_bus_register(struct device *dev, struct an8855_core_= priv *priv, + struct device_node *phy_np, + struct an8855_phy_bus *phy_bus_info) +{ + struct mdio_regmap_config mrc =3D { }; + struct an8855_phy_priv *phy_priv; + struct regmap *regmap; + u32 addr, phy_offset; + struct mii_bus *bus; + int ret; + + ret =3D of_property_read_u32(phy_np, "reg", &addr); + if (ret) + return ret; + + phy_offset =3D addr - priv->switch_addr; + if (phy_offset >=3D AN8855_MAX_PHY_PORT) + return -EINVAL; + + phy_priv =3D devm_kzalloc(dev, sizeof(*phy_priv), GFP_KERNEL); + if (!phy_priv) + return -ENOMEM; + + phy_priv->addr =3D addr; + phy_priv->core =3D priv; + + regmap =3D devm_regmap_init(dev, NULL, phy_priv, &an8855_phy_regmap_confi= g); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), + "phy%d regmap initialization failed\n", + addr); + + mrc.regmap =3D regmap; + mrc.parent =3D dev; + mrc.valid_addr =3D addr; + snprintf(mrc.name, MII_BUS_ID_SIZE, "%s-phy%u", dev_name(dev), addr); + + bus =3D devm_mdio_regmap_register(dev, &mrc); + if (IS_ERR(bus)) + return PTR_ERR(bus); + + if (addr =3D=3D priv->switch_addr) + priv->phy_bus =3D bus; + + phy_bus_info->bus =3D bus; + phy_bus_info->addr =3D addr; + phy_bus_info->node =3D fwnode_handle_get(of_fwnode_handle(phy_np)); + + return 0; +} + +static int an8855_mdio_register(struct device *dev, struct an8855_core_pri= v *priv, + struct an8855_phy_bus *phy_bus_infos) +{ + struct device_node *mdio_np; + int ret =3D 0; + int i =3D 0; + + mdio_np =3D of_get_child_by_name(dev->of_node, "mdio"); + if (!mdio_np) + return -ENODEV; + + for_each_available_child_of_node_scoped(mdio_np, phy_np) { + if (i >=3D AN8855_MAX_PHY_PORT) { + ret =3D -EINVAL; + goto exit; + } + + ret =3D an8855_phy_bus_register(dev, priv, phy_np, + &phy_bus_infos[i]); + if (ret) + goto exit; + + i++; + } + +exit: + of_node_put(mdio_np); + if (ret) { + while (i--) + fwnode_handle_put(phy_bus_infos[i].node); + + return ret; + } + + return i; +} + +static int an8855_core_probe(struct mdio_device *mdiodev) +{ + struct an8855_phy_bus phy_bus_infos[AN8855_MAX_PHY_PORT] =3D { }; + struct device *dev =3D &mdiodev->dev; + struct an8855_core_priv *priv; + struct regmap *regmap; + int num_phys; + int i, ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->bus =3D mdiodev->bus; + priv->switch_addr =3D mdiodev->addr; + /* No DMA for mdiobus, mute warning for DMA mask not set */ + dev->dma_mask =3D &dev->coherent_dma_mask; + + /* Register virtual MDIO for each PHY */ + num_phys =3D an8855_mdio_register(dev, priv, phy_bus_infos); + if (num_phys < 0) + return num_phys; + + regmap =3D devm_regmap_init(dev, NULL, priv, &an8855_regmap_config); + if (IS_ERR(regmap)) { + ret =3D PTR_ERR(regmap); + dev_err_probe(dev, ret, "regmap initialization failed\n"); + goto err_put_fwnodes; + } + + /* Reset PHY page for switch address */ + mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); + ret =3D an8855_mii_set_page(priv, priv->switch_addr, + AN8855_PHY_PAGE_STANDARD); + mutex_unlock(&priv->bus->mdio_lock); + if (ret) + goto err_put_fwnodes; + + ret =3D an8855_read_switch_id(dev, regmap); + if (ret) + goto err_put_fwnodes; + + /* Release global PHY power down */ + ret =3D regmap_write(regmap, AN8855_RG_GPHY_AFE_PWD, 0x0); + if (ret) + goto err_put_fwnodes; + + /* Register PHYs */ + for (i =3D 0; i < num_phys; i++) { + ret =3D fwnode_mdiobus_register_phy(phy_bus_infos[i].bus, + phy_bus_infos[i].node, + phy_bus_infos[i].addr); + fwnode_handle_put(phy_bus_infos[i].node); + phy_bus_infos[i].node =3D NULL; + + if (ret) + goto err_put_fwnodes; + } + + return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, an8855_cells, + ARRAY_SIZE(an8855_cells), NULL, 0, + NULL); + +err_put_fwnodes: + for (i =3D 0; i < num_phys; i++) + if (phy_bus_infos[i].node) + fwnode_handle_put(phy_bus_infos[i].node); + + return ret; +} + +static const struct of_device_id an8855_core_of_match[] =3D { + { .compatible =3D "airoha,an8855" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, an8855_core_of_match); + +static struct mdio_driver an8855_core_driver =3D { + .probe =3D an8855_core_probe, + .mdiodrv.driver =3D { + .name =3D "an8855", + .of_match_table =3D an8855_core_of_match, + }, +}; +mdio_module_driver(an8855_core_driver); + +MODULE_AUTHOR("Christian Marangi "); +MODULE_DESCRIPTION("Driver for Airoha AN8855"); +MODULE_LICENSE("GPL"); --=20 2.55.0 From nobody Mon Sep 28 21:52:21 2026 Received: from mail-wm2-f12.google.com (mail-wm2-f12.google.com [74.125.225.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 589494F5E15 for ; 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[82.57.191.234]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-48af071532dsm1527706f8f.20.2026.09.28.12.46.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 12:46:04 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean , Matthias Brugger , AngeloGioacchino Del Regno , "Chester A. Unal" , Daniel Golle , Heiner Kallweit , Russell King , Simon Horman , Joris Vaisvila , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andrew Lunn Subject: [PATCH net-next v24 05/10] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY Date: Mon, 28 Sep 2026 21:45:04 +0200 Message-ID: <20260928194511.41878-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260928194511.41878-1-ansuelsmth@gmail.com> References: <20260928194511.41878-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for Airoha AN8855 Internal Switch Gigabit PHY. This is a simple PHY driver to configure and calibrate the PHY for the AN8855 Switch with the use of NVMEM cells. Signed-off-by: Christian Marangi Reviewed-by: Andrew Lunn --- drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/air_an8855.c | 275 +++++++++++++++++++++++++++++++++++ 3 files changed, 282 insertions(+) create mode 100644 drivers/net/phy/air_an8855.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index d3835597e379..eca2ce135c86 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -96,6 +96,12 @@ config AIR_AN8801_PHY help Currently supports the Airoha AN8801R PHY. =20 +config AIR_AN8855_PHY + tristate "Airoha AN8855 Internal Gigabit PHY" + depends on NVMEM || !NVMEM + help + Currently supports the internal Airoha AN8855 Switch PHY. + config AIR_EN8811H_PHY tristate "Airoha EN8811H 2.5 Gigabit PHY" select AIR_NET_PHYLIB diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 579066a638f0..d5c633db0742 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_ADIN_PHY) +=3D adin.o obj-$(CONFIG_ADIN1100_PHY) +=3D adin1100.o obj-$(CONFIG_ADIN1140_PHY) +=3D adin1140-phy.o obj-$(CONFIG_AIR_AN8801_PHY) +=3D air_an8801.o +obj-$(CONFIG_AIR_AN8855_PHY) +=3D air_an8855.o obj-$(CONFIG_AIR_EN8811H_PHY) +=3D air_en8811h.o obj-$(CONFIG_AIR_NET_PHYLIB) +=3D air_phy_lib.o obj-$(CONFIG_AMD_PHY) +=3D amd.o diff --git a/drivers/net/phy/air_an8855.c b/drivers/net/phy/air_an8855.c new file mode 100644 index 000000000000..bc22256fd5f9 --- /dev/null +++ b/drivers/net/phy/air_an8855.c @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Christian Marangi + */ + +#include +#include +#include +#include +#include + +#define AN8855_PHY_SELECT_PAGE 0x1f +#define AN8855_PHY_PAGE GENMASK(2, 0) +#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0) +#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x= 1) + +/* MII Registers Page 1 */ +#define AN8855_PHY_EXT_REG_14 0x14 +#define AN8855_PHY_EN_DOWN_SHIFT BIT(4) + +/* R50 Calibration regs in MDIO_MMD_VEND1 */ +#define AN8855_PHY_R50OHM_RSEL_TX_AB 0x174 +#define AN8855_PHY_R50OHM_RSEL_TX_A_EN BIT(15) +#define AN8855_PHY_R50OHM_RSEL_TX_A GENMASK(14, 8) +#define AN8855_PHY_R50OHM_RSEL_TX_B_EN BIT(7) +#define AN8855_PHY_R50OHM_RSEL_TX_B GENMASK(6, 0) +#define AN8855_PHY_R50OHM_RSEL_TX_CD 0x175 +#define AN8855_PHY_R50OHM_RSEL_TX_C_EN BIT(15) +#define AN8855_PHY_R50OHM_RSEL_TX_C GENMASK(14, 8) +#define AN8855_PHY_R50OHM_RSEL_TX_D_EN BIT(7) +#define AN8855_PHY_R50OHM_RSEL_TX_D GENMASK(6, 0) + +#define AN8855_SWITCH_EFUSE_R50O GENMASK(30, 24) + +/* PHY TX PAIR DELAY SELECT Register */ +#define AN8855_PHY_TX_PAIR_DLY_SEL_GBE 0x013 +#define AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_A_GBE GENMASK(14, 12) +#define AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_B_GBE GENMASK(10, 8) +#define AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_C_GBE GENMASK(6, 4) +#define AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_D_GBE GENMASK(2, 0) +/* PHY ADC Register */ +#define AN8855_PHY_RXADC_CTRL 0x0d8 +#define AN8855_PHY_RG_AD_SAMPLE_PHSEL_A BIT(12) +#define AN8855_PHY_RG_AD_SAMPLE_PHSEL_B BIT(8) +#define AN8855_PHY_RG_AD_SAMPLE_PHSEL_C BIT(4) +#define AN8855_PHY_RG_AD_SAMPLE_PHSEL_D BIT(0) +#define AN8855_PHY_RXADC_REV_0 0x0d9 +#define AN8855_PHY_RG_AD_RESERVE0_A GENMASK(15, 8) +#define AN8855_PHY_RG_AD_RESERVE0_B GENMASK(7, 0) +#define AN8855_PHY_RXADC_REV_1 0x0da +#define AN8855_PHY_RG_AD_RESERVE0_C GENMASK(15, 8) +#define AN8855_PHY_RG_AD_RESERVE0_D GENMASK(7, 0) + +#define AN8855_PHY_ID 0xc0ff0410 + +struct air_an8855_priv { + bool needs_calibration; + u8 calibration_data[4]; +}; + +static const u8 dsa_r50ohm_table[] =3D { + 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, + 127, 127, 127, 127, 127, 127, 127, 126, 122, 117, + 112, 109, 104, 101, 97, 94, 90, 88, 84, 80, + 78, 74, 72, 68, 66, 64, 61, 58, 56, 53, + 51, 48, 47, 44, 42, 40, 38, 36, 34, 32, + 31, 28, 27, 24, 24, 22, 20, 18, 16, 16, + 14, 12, 11, 9 +}; + +static int an8855_get_r50ohm_val(struct device *dev, const char *calib_nam= e, + u8 *dest) +{ + u32 shift_sel, val; + int ret; + int i; + + ret =3D nvmem_cell_read_u32(dev, calib_name, &val); + if (ret) + return ret; + + shift_sel =3D FIELD_GET(AN8855_SWITCH_EFUSE_R50O, val); + for (i =3D 0; i < ARRAY_SIZE(dsa_r50ohm_table); i++) + if (dsa_r50ohm_table[i] =3D=3D shift_sel) + break; + + if (i < 8 || i >=3D ARRAY_SIZE(dsa_r50ohm_table)) + *dest =3D dsa_r50ohm_table[25]; + else + *dest =3D dsa_r50ohm_table[i - 8]; + + return 0; +} + +static int an8855_probe(struct phy_device *phydev) +{ + struct device *dev =3D &phydev->mdio.dev; + struct air_an8855_priv *priv; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->needs_calibration =3D of_property_present(dev->of_node, + "nvmem-cells"); + + if (priv->needs_calibration) { + int ret; + + ret =3D an8855_get_r50ohm_val(dev, "tx_a", &priv->calibration_data[0]); + if (ret) + return ret; + + ret =3D an8855_get_r50ohm_val(dev, "tx_b", &priv->calibration_data[1]); + if (ret) + return ret; + + ret =3D an8855_get_r50ohm_val(dev, "tx_c", &priv->calibration_data[2]); + if (ret) + return ret; + + ret =3D an8855_get_r50ohm_val(dev, "tx_d", &priv->calibration_data[3]); + if (ret) + return ret; + } + + phydev->priv =3D priv; + + return 0; +} + +static int an8855_get_downshift(struct phy_device *phydev, u8 *data) +{ + int val; + + val =3D phy_read_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1, AN8855_PHY_EXT= _REG_14); + if (val < 0) + return val; + + *data =3D val & AN8855_PHY_EN_DOWN_SHIFT ? DOWNSHIFT_DEV_DEFAULT_COUNT : + DOWNSHIFT_DEV_DISABLE; + + return 0; +} + +static int an8855_set_downshift(struct phy_device *phydev, u8 cnt) +{ + u16 ds =3D cnt !=3D DOWNSHIFT_DEV_DISABLE ? AN8855_PHY_EN_DOWN_SHIFT : 0; + + return phy_modify_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1, + AN8855_PHY_EXT_REG_14, AN8855_PHY_EN_DOWN_SHIFT, + ds); +} + +static int an8855_config_init(struct phy_device *phydev) +{ + struct air_an8855_priv *priv =3D phydev->priv; + int ret; + + /* Enable HW auto downshift */ + ret =3D an8855_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT); + if (ret) + return ret; + + if (priv->needs_calibration) { + ret =3D phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R50OHM_RSEL_TX= _AB, + AN8855_PHY_R50OHM_RSEL_TX_A_EN | AN8855_PHY_R50OHM_RSEL_TX_A | + AN8855_PHY_R50OHM_RSEL_TX_B_EN | AN8855_PHY_R50OHM_RSEL_TX_B, + AN8855_PHY_R50OHM_RSEL_TX_A_EN | + FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_A, + priv->calibration_data[0]) | + AN8855_PHY_R50OHM_RSEL_TX_B_EN | + FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_B, + priv->calibration_data[1])); + if (ret) + return ret; + ret =3D phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R50OHM_RSEL_TX= _CD, + AN8855_PHY_R50OHM_RSEL_TX_C_EN | AN8855_PHY_R50OHM_RSEL_TX_C | + AN8855_PHY_R50OHM_RSEL_TX_D_EN | AN8855_PHY_R50OHM_RSEL_TX_D, + AN8855_PHY_R50OHM_RSEL_TX_C_EN | + FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_C, + priv->calibration_data[2]) | + AN8855_PHY_R50OHM_RSEL_TX_D_EN | + FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_D, + priv->calibration_data[3])); + if (ret) + return ret; + } + + /* Apply values to reduce signal noise */ + ret =3D phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_TX_PAIR_DLY_SEL= _GBE, + AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_A_GBE | + AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_C_GBE, + FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_A_GBE, 0x4) | + FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_C_GBE, 0x4)); + if (ret) + return ret; + ret =3D phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_CTRL, + AN8855_PHY_RG_AD_SAMPLE_PHSEL_A | + AN8855_PHY_RG_AD_SAMPLE_PHSEL_C); + if (ret) + return ret; + ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_0, + FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_A, 0x1)); + if (ret) + return ret; + ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_1, + FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_C, 0x1)); + if (ret) + return ret; + + return 0; +} + +static int an8855_get_tunable(struct phy_device *phydev, + struct ethtool_tunable *tuna, void *data) +{ + switch (tuna->id) { + case ETHTOOL_PHY_DOWNSHIFT: + return an8855_get_downshift(phydev, data); + default: + return -EOPNOTSUPP; + } +} + +static int an8855_set_tunable(struct phy_device *phydev, + struct ethtool_tunable *tuna, const void *data) +{ + switch (tuna->id) { + case ETHTOOL_PHY_DOWNSHIFT: + return an8855_set_downshift(phydev, *(const u8 *)data); + default: + return -EOPNOTSUPP; + } +} + +static int an8855_read_page(struct phy_device *phydev) +{ + return __phy_read(phydev, AN8855_PHY_SELECT_PAGE); +} + +static int an8855_write_page(struct phy_device *phydev, int page) +{ + return __phy_write(phydev, AN8855_PHY_SELECT_PAGE, page); +} + +static struct phy_driver an8855_driver[] =3D { +{ + PHY_ID_MATCH_EXACT(AN8855_PHY_ID), + .name =3D "Airoha AN8855 internal PHY", + /* PHY_GBIT_FEATURES */ + .flags =3D PHY_IS_INTERNAL, + .probe =3D an8855_probe, + .config_init =3D an8855_config_init, + .soft_reset =3D genphy_soft_reset, + .get_tunable =3D an8855_get_tunable, + .set_tunable =3D an8855_set_tunable, + .suspend =3D genphy_suspend, + .resume =3D genphy_resume, + .read_page =3D an8855_read_page, + .write_page =3D an8855_write_page, +}, }; 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[82.57.191.234]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-48af071532dsm1527706f8f.20.2026.09.28.12.46.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 12:46:07 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean , Matthias Brugger , AngeloGioacchino Del Regno , "Chester A. Unal" , Daniel Golle , Heiner Kallweit , Russell King , Simon Horman , Joris Vaisvila , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andrew Lunn Subject: [PATCH net-next v24 06/10] net: dsa: tag_mtk: add Airoha variant usage of this TAG Date: Mon, 28 Sep 2026 21:45:05 +0200 Message-ID: <20260928194511.41878-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260928194511.41878-1-ansuelsmth@gmail.com> References: <20260928194511.41878-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add variant of the MTK TAG for Airoha Switch and comments about difference between Airoha AN8855 and Mediatek tag bitmap. Airoha AN8855 doesn't support controlling SA learning and Leaky VLAN from tag. Although these bits are not used (and even not defined for Leaky VLAN), it's worth to add comments for these difference to prevent any kind of regression in the future if ever these bits will be used. Rework the makefile, config and tag driver to better report to external tool (like libpcap) the usage of this variant with a dedicated "Airoha" name. Signed-off-by: Christian Marangi Reviewed-by: Andrew Lunn --- include/net/dsa.h | 2 ++ net/dsa/Kconfig | 11 +++++++++++ net/dsa/Makefile | 2 +- net/dsa/tag_mtk.c | 36 +++++++++++++++++++++++++++++++++--- 4 files changed, 47 insertions(+), 4 deletions(-) diff --git a/include/net/dsa.h b/include/net/dsa.h index 5d12191b6f6f..9824c63ad50b 100644 --- a/include/net/dsa.h +++ b/include/net/dsa.h @@ -62,6 +62,7 @@ struct tc_action; #define DSA_TAG_PROTO_KSZ8463_VALUE 34 #define DSA_TAG_PROTO_MT7628_VALUE 35 #define DSA_TAG_PROTO_KS8995_VALUE 36 +#define DSA_TAG_PROTO_AIROHA_VALUE 37 =20 enum dsa_tag_protocol { DSA_TAG_PROTO_NONE =3D DSA_TAG_PROTO_NONE_VALUE, @@ -76,6 +77,7 @@ enum dsa_tag_protocol { DSA_TAG_PROTO_KSZ9893 =3D DSA_TAG_PROTO_KSZ9893_VALUE, DSA_TAG_PROTO_LAN9303 =3D DSA_TAG_PROTO_LAN9303_VALUE, DSA_TAG_PROTO_MTK =3D DSA_TAG_PROTO_MTK_VALUE, + DSA_TAG_PROTO_AIROHA =3D DSA_TAG_PROTO_AIROHA_VALUE, DSA_TAG_PROTO_QCA =3D DSA_TAG_PROTO_QCA_VALUE, DSA_TAG_PROTO_TRAILER =3D DSA_TAG_PROTO_TRAILER_VALUE, DSA_TAG_PROTO_8021Q =3D DSA_TAG_PROTO_8021Q_VALUE, diff --git a/net/dsa/Kconfig b/net/dsa/Kconfig index 4f44bf3ede23..28a249f04a43 100644 --- a/net/dsa/Kconfig +++ b/net/dsa/Kconfig @@ -24,6 +24,13 @@ config NET_DSA_TAG_NONE Say Y or M if you want to enable support for switches which don't tag frames over the CPU port. =20 +config NET_DSA_TAG_AIROHA + tristate "Tag driver for Airoha switches" + select NET_DSA_TAG_MTK_COMMON + help + Say Y or M if you want to enable support for tagging frames for + Airoha switches. + config NET_DSA_TAG_AR9331 tristate "Tag driver for Atheros AR9331 SoC with built-in switch" help @@ -104,8 +111,12 @@ config NET_DSA_TAG_MT7628 Say Y or M if you want to enable support for tagging frames for the switch embedded in the MT7628 SoC. =20 +config NET_DSA_TAG_MTK_COMMON + tristate + config NET_DSA_TAG_MTK tristate "Tag driver for Mediatek switches" + select NET_DSA_TAG_MTK_COMMON help Say Y or M if you want to enable support for tagging frames for Mediatek switches. diff --git a/net/dsa/Makefile b/net/dsa/Makefile index 1f9cc30e9988..7ccaa528a989 100644 --- a/net/dsa/Makefile +++ b/net/dsa/Makefile @@ -29,7 +29,7 @@ obj-$(CONFIG_NET_DSA_TAG_KS8995) +=3D tag_ks8995.o obj-$(CONFIG_NET_DSA_TAG_KSZ) +=3D tag_ksz.o obj-$(CONFIG_NET_DSA_TAG_LAN9303) +=3D tag_lan9303.o obj-$(CONFIG_NET_DSA_TAG_MT7628) +=3D tag_mt7628.o -obj-$(CONFIG_NET_DSA_TAG_MTK) +=3D tag_mtk.o +obj-$(CONFIG_NET_DSA_TAG_MTK_COMMON) +=3D tag_mtk.o obj-$(CONFIG_NET_DSA_TAG_MXL_862XX) +=3D tag_mxl862xx.o obj-$(CONFIG_NET_DSA_TAG_MXL_GSW1XX) +=3D tag_mxl-gsw1xx.o obj-$(CONFIG_NET_DSA_TAG_NETC) +=3D tag_netc.o diff --git a/net/dsa/tag_mtk.c b/net/dsa/tag_mtk.c index c7dc7731675e..f8087d768da6 100644 --- a/net/dsa/tag_mtk.c +++ b/net/dsa/tag_mtk.c @@ -11,6 +11,7 @@ #include "tag.h" =20 #define MTK_NAME "mtk" +#define AIROHA_NAME "airoha" =20 #define MTK_HDR_LEN 4 #define MTK_HDR_XMIT_UNTAGGED 0 @@ -18,6 +19,9 @@ #define MTK_HDR_XMIT_TAGGED_TPID_88A8 2 #define MTK_HDR_RECV_SOURCE_PORT_MASK GENMASK(2, 0) #define MTK_HDR_XMIT_DP_BIT_MASK GENMASK(5, 0) +/* AN8855 doesn't support SA_DIS and Leaky VLAN + * control in tag as these bits doesn't exist. + */ #define MTK_HDR_XMIT_SA_DIS BIT(6) =20 static struct sk_buff *mtk_tag_xmit(struct sk_buff *skb, @@ -99,6 +103,7 @@ static struct sk_buff *mtk_tag_rcv(struct sk_buff *skb, = struct net_device *dev) return skb; } =20 +#if IS_ENABLED(CONFIG_NET_DSA_TAG_MTK) static const struct dsa_device_ops mtk_netdev_ops =3D { .name =3D MTK_NAME, .proto =3D DSA_TAG_PROTO_MTK, @@ -107,8 +112,33 @@ static const struct dsa_device_ops mtk_netdev_ops =3D { .needed_headroom =3D MTK_HDR_LEN, }; =20 -MODULE_DESCRIPTION("DSA tag driver for Mediatek switches"); -MODULE_LICENSE("GPL"); +DSA_TAG_DRIVER(mtk_netdev_ops); MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_MTK, MTK_NAME); +#endif =20 -module_dsa_tag_driver(mtk_netdev_ops); +#if IS_ENABLED(CONFIG_NET_DSA_TAG_AIROHA) +static const struct dsa_device_ops airoha_netdev_ops =3D { + .name =3D AIROHA_NAME, + .proto =3D DSA_TAG_PROTO_AIROHA, + .xmit =3D mtk_tag_xmit, + .rcv =3D mtk_tag_rcv, + .needed_headroom =3D MTK_HDR_LEN, +}; + +DSA_TAG_DRIVER(airoha_netdev_ops); +MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_AIROHA, AIROHA_NAME); +#endif + +static struct dsa_tag_driver *dsa_tag_driver_array[] =3D { +#if IS_ENABLED(CONFIG_NET_DSA_TAG_MTK) + &DSA_TAG_DRIVER_NAME(mtk_netdev_ops), +#endif +#if IS_ENABLED(CONFIG_NET_DSA_TAG_AIROHA) + &DSA_TAG_DRIVER_NAME(airoha_netdev_ops), +#endif +}; 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[82.57.191.234]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-48af071532dsm1527706f8f.20.2026.09.28.12.46.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 12:46:09 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean , Matthias Brugger , AngeloGioacchino Del Regno , "Chester A. Unal" , Daniel Golle , Heiner Kallweit , Russell King , Simon Horman , Joris Vaisvila , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andrew Lunn Subject: [PATCH net-next v24 07/10] MAINTAINERS: add myself as maintainer for Airoha AN8855 Switch Date: Mon, 28 Sep 2026 21:45:06 +0200 Message-ID: <20260928194511.41878-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260928194511.41878-1-ansuelsmth@gmail.com> References: <20260928194511.41878-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add myself as maintainer for AN8855 DSA driver and all the related subdriver (mfd, mdio, phy, nvmem) Signed-off-by: Christian Marangi Reviewed-by: Andrew Lunn --- MAINTAINERS | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 6de1ff058db6..59e6385b2c50 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -759,6 +759,22 @@ S: Maintained F: Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml F: drivers/net/ethernet/airoha/ =20 +AIROHA AN8855 DSA DRIVER +M: Christian Marangi +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) +L: netdev@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/mfd/airoha,an8855.yaml +F: Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml +F: Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml +F: Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml +F: drivers/mfd/airoha-an8855.c +F: drivers/net/dsa/mediatek/an8855.c +F: drivers/net/dsa/mediatek/an8855.h +F: drivers/net/phy/air_an8855.c +F: drivers/nvmem/an8855-efuse.c + AIROHA PCIE PHY DRIVER M: Lorenzo Bianconi L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) --=20 2.55.0 From nobody Mon Sep 28 21:52:21 2026 Received: from mail-wr2-f12.google.com (mail-wr2-f12.google.com [74.125.225.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70B574FC8C6 for ; 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[82.57.191.234]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-48af071532dsm1527706f8f.20.2026.09.28.12.46.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 12:46:11 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean , Matthias Brugger , AngeloGioacchino Del Regno , "Chester A. Unal" , Daniel Golle , Heiner Kallweit , Russell King , Simon Horman , Joris Vaisvila , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v24 08/10] net: dsa: move mediatek DSA driver in dedicated directory Date: Mon, 28 Sep 2026 21:45:07 +0200 Message-ID: <20260928194511.41878-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260928194511.41878-1-ansuelsmth@gmail.com> References: <20260928194511.41878-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To tidy things up and better organize DSA drivers, move the Mediatek related driver to the dedicated Vendor directory. MAINTAINERS file is updated accordingly to reference the new location. Signed-off-by: Christian Marangi --- MAINTAINERS | 6 +-- drivers/net/dsa/Kconfig | 45 +------------------- drivers/net/dsa/Makefile | 5 +-- drivers/net/dsa/mediatek/Kconfig | 45 ++++++++++++++++++++ drivers/net/dsa/mediatek/Makefile | 5 +++ drivers/net/dsa/{ =3D> mediatek}/mt7530-mdio.c | 0 drivers/net/dsa/{ =3D> mediatek}/mt7530-mmio.c | 0 drivers/net/dsa/{ =3D> mediatek}/mt7530.c | 0 drivers/net/dsa/{ =3D> mediatek}/mt7530.h | 0 drivers/net/dsa/{ =3D> mediatek}/mt7628.c | 0 10 files changed, 55 insertions(+), 51 deletions(-) create mode 100644 drivers/net/dsa/mediatek/Kconfig create mode 100644 drivers/net/dsa/mediatek/Makefile rename drivers/net/dsa/{ =3D> mediatek}/mt7530-mdio.c (100%) rename drivers/net/dsa/{ =3D> mediatek}/mt7530-mmio.c (100%) rename drivers/net/dsa/{ =3D> mediatek}/mt7530.c (100%) rename drivers/net/dsa/{ =3D> mediatek}/mt7530.h (100%) rename drivers/net/dsa/{ =3D> mediatek}/mt7628.c (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 59e6385b2c50..ff8c5dda07b5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16839,9 +16839,9 @@ M: Chester A. Unal M: Daniel Golle L: netdev@vger.kernel.org S: Maintained -F: drivers/net/dsa/mt7530-mdio.c -F: drivers/net/dsa/mt7530-mmio.c -F: drivers/net/dsa/mt7530.* +F: drivers/net/dsa/mediatek/mt7530-mdio.c +F: drivers/net/dsa/mediatek/mt7530-mmio.c +F: drivers/net/dsa/mediatek/mt7530.* F: net/dsa/tag_mtk.c =20 MEDIATEK T7XX 5G WWAN MODEM DRIVER diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig index fe8cd5338fda..ffc26eb3e899 100644 --- a/drivers/net/dsa/Kconfig +++ b/drivers/net/dsa/Kconfig @@ -28,50 +28,7 @@ source "drivers/net/dsa/hirschmann/Kconfig" =20 source "drivers/net/dsa/lantiq/Kconfig" =20 -config NET_DSA_MT7530 - tristate "MediaTek MT7530 and MT7531 Ethernet switch support" - select NET_DSA_TAG_MTK - select REGMAP_IRQ - imply NET_DSA_MT7530_MDIO - imply NET_DSA_MT7530_MMIO - help - This enables support for the MediaTek MT7530 and MT7531 Ethernet - switch chips. Multi-chip module MT7530 in MT7621AT, MT7621DAT, - MT7621ST and MT7623AI SoCs, and built-in switch in MT7988 SoC are - supported as well. - -config NET_DSA_MT7530_MDIO - tristate "MediaTek MT7530 MDIO interface driver" - depends on NET_DSA_MT7530 - select MEDIATEK_GE_PHY - select PCS_MTK_LYNXI - help - This enables support for the MediaTek MT7530 and MT7531 switch - chips which are connected via MDIO, as well as multi-chip - module MT7530 which can be found in the MT7621AT, MT7621DAT, - MT7621ST and MT7623AI SoCs. - -config NET_DSA_MT7530_MMIO - tristate "MediaTek MT7530 MMIO interface driver" - depends on NET_DSA_MT7530 - depends on HAS_IOMEM - imply MEDIATEK_GE_SOC_PHY - help - This enables support for the built-in Ethernet switch found - in the MediaTek MT7988 SoC. - The switch is a similar design as MT7531, but the switch registers - are directly mapped into the SoCs register space rather than being - accessible via MDIO. - -config NET_DSA_MT7628 - tristate "MediaTek MT7628 Embedded Ethernet switch support" - depends on HAS_IOMEM && (SOC_MT7620 || COMPILE_TEST) - select NET_DSA_TAG_MT7628 - select MEDIATEK_FE_SOC_PHY - select REGMAP_MMIO - help - This enables support for the built-in Ethernet switch found - in the MT7628 SoC. +source "drivers/net/dsa/mediatek/Kconfig" =20 config NET_DSA_MV88E6060 tristate "Marvell 88E6060 ethernet switch chip support" diff --git a/drivers/net/dsa/Makefile b/drivers/net/dsa/Makefile index 7e637d56b35c..ee4784a9839b 100644 --- a/drivers/net/dsa/Makefile +++ b/drivers/net/dsa/Makefile @@ -2,10 +2,6 @@ obj-$(CONFIG_NET_DSA_BCM_SF2) +=3D bcm-sf2.o bcm-sf2-objs :=3D bcm_sf2.o bcm_sf2_cfp.o obj-$(CONFIG_NET_DSA_LOOP) +=3D dsa_loop.o -obj-$(CONFIG_NET_DSA_MT7530) +=3D mt7530.o -obj-$(CONFIG_NET_DSA_MT7530_MDIO) +=3D mt7530-mdio.o -obj-$(CONFIG_NET_DSA_MT7530_MMIO) +=3D mt7530-mmio.o -obj-$(CONFIG_NET_DSA_MT7628) +=3D mt7628.o obj-$(CONFIG_NET_DSA_MV88E6060) +=3D mv88e6060.o obj-$(CONFIG_NET_DSA_RZN1_A5PSW) +=3D rzn1_a5psw.o obj-$(CONFIG_NET_DSA_SMSC_LAN9303) +=3D lan9303-core.o @@ -17,6 +13,7 @@ obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX_SPI) +=3D vitesse-vs= c73xx-spi.o obj-y +=3D b53/ obj-y +=3D hirschmann/ obj-y +=3D lantiq/ +obj-y +=3D mediatek/ obj-y +=3D microchip/ obj-y +=3D motorcomm/ obj-y +=3D mv88e6xxx/ diff --git a/drivers/net/dsa/mediatek/Kconfig b/drivers/net/dsa/mediatek/Kc= onfig new file mode 100644 index 000000000000..ef62481662fd --- /dev/null +++ b/drivers/net/dsa/mediatek/Kconfig @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only +config NET_DSA_MT7530 + tristate "MediaTek MT7530 and MT7531 Ethernet switch support" + select NET_DSA_TAG_MTK + select REGMAP_IRQ + imply NET_DSA_MT7530_MDIO + imply NET_DSA_MT7530_MMIO + help + This enables support for the MediaTek MT7530 and MT7531 Ethernet + switch chips. Multi-chip module MT7530 in MT7621AT, MT7621DAT, + MT7621ST and MT7623AI SoCs, and built-in switch in MT7988 SoC are + supported as well. + +config NET_DSA_MT7530_MDIO + tristate "MediaTek MT7530 MDIO interface driver" + depends on NET_DSA_MT7530 + select MEDIATEK_GE_PHY + select PCS_MTK_LYNXI + help + This enables support for the MediaTek MT7530 and MT7531 switch + chips which are connected via MDIO, as well as multi-chip + module MT7530 which can be found in the MT7621AT, MT7621DAT, + MT7621ST and MT7623AI SoCs. + +config NET_DSA_MT7530_MMIO + tristate "MediaTek MT7530 MMIO interface driver" + depends on NET_DSA_MT7530 + depends on HAS_IOMEM + imply MEDIATEK_GE_SOC_PHY + help + This enables support for the built-in Ethernet switch found + in the MediaTek MT7988 SoC. + The switch is a similar design as MT7531, but the switch registers + are directly mapped into the SoCs register space rather than being + accessible via MDIO. + +config NET_DSA_MT7628 + tristate "MediaTek MT7628 Embedded Ethernet switch support" + depends on HAS_IOMEM && (SOC_MT7620 || COMPILE_TEST) + select NET_DSA_TAG_MT7628 + select MEDIATEK_FE_SOC_PHY + select REGMAP_MMIO + help + This enables support for the built-in Ethernet switch found + in the MT7628 SoC. diff --git a/drivers/net/dsa/mediatek/Makefile b/drivers/net/dsa/mediatek/M= akefile new file mode 100644 index 000000000000..0ed6e11f292e --- /dev/null +++ b/drivers/net/dsa/mediatek/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_NET_DSA_MT7530) +=3D mt7530.o +obj-$(CONFIG_NET_DSA_MT7530_MDIO) +=3D mt7530-mdio.o +obj-$(CONFIG_NET_DSA_MT7530_MMIO) +=3D mt7530-mmio.o +obj-$(CONFIG_NET_DSA_MT7628) +=3D mt7628.o diff --git a/drivers/net/dsa/mt7530-mdio.c b/drivers/net/dsa/mediatek/mt753= 0-mdio.c similarity index 100% rename from drivers/net/dsa/mt7530-mdio.c rename to drivers/net/dsa/mediatek/mt7530-mdio.c diff --git a/drivers/net/dsa/mt7530-mmio.c b/drivers/net/dsa/mediatek/mt753= 0-mmio.c similarity index 100% rename from drivers/net/dsa/mt7530-mmio.c rename to drivers/net/dsa/mediatek/mt7530-mmio.c diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mediatek/mt7530.c similarity index 100% rename from drivers/net/dsa/mt7530.c rename to drivers/net/dsa/mediatek/mt7530.c diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mediatek/mt7530.h similarity index 100% rename from drivers/net/dsa/mt7530.h rename to drivers/net/dsa/mediatek/mt7530.h diff --git a/drivers/net/dsa/mt7628.c b/drivers/net/dsa/mediatek/mt7628.c similarity index 100% rename from drivers/net/dsa/mt7628.c rename to drivers/net/dsa/mediatek/mt7628.c --=20 2.55.0 From nobody Mon Sep 28 21:52:21 2026 Received: from mail-wr2-f12.google.com (mail-wr2-f12.google.com [74.125.225.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C93644F55C3 for ; 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[82.57.191.234]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-48af071532dsm1527706f8f.20.2026.09.28.12.46.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 12:46:14 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean , Matthias Brugger , AngeloGioacchino Del Regno , "Chester A. Unal" , Daniel Golle , Heiner Kallweit , Russell King , Simon Horman , Joris Vaisvila , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andrew Lunn Subject: [PATCH net-next v24 09/10] net: dsa: mt7530: generalize and move common function to lib module Date: Mon, 28 Sep 2026 21:45:08 +0200 Message-ID: <20260928194511.41878-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260928194511.41878-1-ansuelsmth@gmail.com> References: <20260928194511.41878-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation of support of DSA Switch from Airoha, create a mt7530 library module and move there all the common function. Function are generalized to use the reg_field regmap API but still apply the same exact logic. Every function is renamed to mt7530_lib prefix to better identify it. Minimum modification are needed to the register header and common enum and macro are moved to the mt7530 library header to permit reuse. A library struct is introduced with everything required for the common functions. The generalization and the introduction of reg_field regmap API have the side effect of permitting to clean the mirror functions that required special handling for MT7530 and MT7531 based switch that had different registers. This is done by declaring a common MT7530 reg_field and a specific one in the Switch match table. No behaviour change is expected by this change as it's just a code move and reimplementation. Reviewed-by: Andrew Lunn Signed-off-by: Christian Marangi --- drivers/net/dsa/mediatek/Kconfig | 4 + drivers/net/dsa/mediatek/Makefile | 1 + drivers/net/dsa/mediatek/mt7530-lib.c | 1128 +++++++++++++++++++ drivers/net/dsa/mediatek/mt7530-lib.h | 391 +++++++ drivers/net/dsa/mediatek/mt7530-mdio.c | 4 + drivers/net/dsa/mediatek/mt7530-mmio.c | 4 + drivers/net/dsa/mediatek/mt7530.c | 1366 ++++++------------------ drivers/net/dsa/mediatek/mt7530.h | 256 ++--- 8 files changed, 1912 insertions(+), 1242 deletions(-) create mode 100644 drivers/net/dsa/mediatek/mt7530-lib.c create mode 100644 drivers/net/dsa/mediatek/mt7530-lib.h diff --git a/drivers/net/dsa/mediatek/Kconfig b/drivers/net/dsa/mediatek/Kc= onfig index ef62481662fd..7b48300dca0c 100644 --- a/drivers/net/dsa/mediatek/Kconfig +++ b/drivers/net/dsa/mediatek/Kconfig @@ -1,6 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-only +config NET_DSA_MT7530_LIB + tristate + config NET_DSA_MT7530 tristate "MediaTek MT7530 and MT7531 Ethernet switch support" + select NET_DSA_MT7530_LIB select NET_DSA_TAG_MTK select REGMAP_IRQ imply NET_DSA_MT7530_MDIO diff --git a/drivers/net/dsa/mediatek/Makefile b/drivers/net/dsa/mediatek/M= akefile index 0ed6e11f292e..b2c0693dbb58 100644 --- a/drivers/net/dsa/mediatek/Makefile +++ b/drivers/net/dsa/mediatek/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_NET_DSA_MT7530) +=3D mt7530.o +obj-$(CONFIG_NET_DSA_MT7530_LIB) +=3D mt7530-lib.o obj-$(CONFIG_NET_DSA_MT7530_MDIO) +=3D mt7530-mdio.o obj-$(CONFIG_NET_DSA_MT7530_MMIO) +=3D mt7530-mmio.o obj-$(CONFIG_NET_DSA_MT7628) +=3D mt7628.o diff --git a/drivers/net/dsa/mediatek/mt7530-lib.c b/drivers/net/dsa/mediat= ek/mt7530-lib.c new file mode 100644 index 000000000000..098dd45d3ee9 --- /dev/null +++ b/drivers/net/dsa/mediatek/mt7530-lib.c @@ -0,0 +1,1128 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include + +#include "mt7530-lib.h" + +void mt7530_lib_mib_reset(struct mt7530_lib_priv *priv) +{ + regmap_field_write(priv->fields[MT7530_CCR_MIB_ENABLE], 0); + regmap_field_write(priv->fields[MT7530_CCR_RX_OCT_CNT_GOOD], 1); + regmap_field_write(priv->fields[MT7530_CCR_RX_OCT_CNT_BAD], 1); + regmap_field_write(priv->fields[MT7530_CCR_TX_OCT_CNT_GOOD], 1); + regmap_field_write(priv->fields[MT7530_CCR_TX_OCT_CNT_BAD], 1); + regmap_field_write(priv->fields[MT7530_CCR_MIB_ENABLE], 1); +} +EXPORT_SYMBOL_GPL(mt7530_lib_mib_reset); + +/* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer = (DLL) + * of the Open Systems Interconnection basic reference model (OSI/RM) are + * described; the medium access control (MAC) and logical link control (LL= C) + * sublayers. The MAC sublayer is the one facing the physical layer. + * + * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A + * Bridge component comprises a MAC Relay Entity for interconnecting the P= orts + * of the Bridge, at least two Ports, and higher layer entities with at le= ast a + * Spanning Tree Protocol Entity included. + * + * Each Bridge Port also functions as an end station and shall provide the= MAC + * Service to an LLC Entity. Each instance of the MAC Service is provided = to a + * distinct LLC Entity that supports protocol identification, multiplexing= , and + * demultiplexing, for protocol data unit (PDU) transmission and reception= by + * one or more higher layer entities. + * + * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the= LLC + * Entity associated with each Bridge Port is modeled as being directly + * connected to the attached Local Area Network (LAN). + * + * On the switch with CPU port architecture, CPU port functions as Managem= ent + * Port, and the Management Port functionality is provided by software whi= ch + * functions as an end station. Software is connected to an IEEE 802 LAN t= hat is + * wholly contained within the system that incorporates the Bridge. Softwa= re + * provides access to the LLC Entity associated with each Bridge Port by t= he + * value of the source port field on the special tag on the frame received= by + * software. + * + * We call frames that carry control information to determine the active + * topology and current extent of each Virtual Local Area Network (VLAN), = i.e., + * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registr= ation + * Protocol Data Units (MVRPDUs), and frames from other link constrained + * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) = and + * Link Layer Discovery Protocol (LLDP), link-local frames. They are not + * forwarded by a Bridge. Permanently configured entries in the filtering + * database (FDB) ensure that such frames are discarded by the Forwarding + * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail: + * + * Each of the reserved MAC addresses specified in Table 8-1 + * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shal= l be + * permanently configured in the FDB in C-VLAN components and ERs. + * + * Each of the reserved MAC addresses specified in Table 8-2 + * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently + * configured in the FDB in S-VLAN components. + * + * Each of the reserved MAC addresses specified in Table 8-3 + * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the F= DB in + * TPMR components. + * + * The FDB entries for reserved MAC addresses shall specify filtering for = all + * Bridge Ports and all VIDs. Management shall not provide the capability = to + * modify or remove entries for reserved MAC addresses. + * + * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scop= e of + * propagation of PDUs within a Bridged Network, as follows: + * + * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address th= at no + * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN) + * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forwar= d. + * PDUs transmitted using this destination address, or any other address= es + * that appear in Table 8-1, Table 8-2, and Table 8-3 + * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), c= an + * therefore travel no further than those stations that can be reached v= ia a + * single individual LAN from the originating station. + * + * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an + * address that no conformant S-VLAN component, C-VLAN component, or MAC + * Bridge can forward; however, this address is relayed by a TPMR compon= ent. + * PDUs using this destination address, or any of the other addresses th= at + * appear in both Table 8-1 and Table 8-2 but not in Table 8-3 + * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relay= ed by + * any TPMRs but will propagate no further than the nearest S-VLAN compo= nent, + * C-VLAN component, or MAC Bridge. + * + * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an a= ddress + * that no conformant C-VLAN component, MAC Bridge can forward; however,= it is + * relayed by TPMR components and S-VLAN components. PDUs using this + * destination address, or any of the other addresses that appear in Tab= le 8-1 + * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D= ,0F]), + * will be relayed by TPMR components and S-VLAN components but will pro= pagate + * no further than the nearest C-VLAN component or MAC Bridge. + * + * Because the LLC Entity associated with each Bridge Port is provided via= CPU + * port, we must not filter these frames but forward them to CPU port. + * + * In a Bridge, the transmission Port is majorly decided by ingress and eg= ress + * rules, FDB, and spanning tree Port State functions of the Forwarding Pr= ocess. + * For link-local frames, only CPU port should be designated as destinatio= n port + * in the FDB, and the other functions of the Forwarding Process must not + * interfere with the decision of the transmission Port. We call this proc= ess + * trapping frames to CPU port. + * + * Therefore, on the switch with CPU port architecture, link-local frames = must + * be trapped to CPU port, and certain link-local frames received by a Por= t of a + * Bridge comprising a TPMR component or an S-VLAN component must be exclu= ded + * from it. + * + * A Bridge of the switch with CPU port architecture cannot comprise a Two= -Port + * MAC Relay (TPMR) component as a TPMR component supports only a subset o= f the + * functionality of a MAC Bridge. A Bridge comprising two Ports (Managemen= t Port + * doesn't count) of this architecture will either function as a standard = MAC + * Bridge or a standard VLAN Bridge. + * + * Therefore, a Bridge of this architecture can only comprise S-VLAN compo= nents, + * C-VLAN components, or MAC Bridge components. Since there's no TPMR comp= onent, + * we don't need to relay PDUs using the destination addresses specified o= n the + * Nearest non-TPMR section, and the proportion of the Nearest Customer Br= idge + * section where they must be relayed by TPMR components. + * + * One option to trap link-local frames to CPU port is to add static FDB e= ntries + * with CPU port designated as destination port. However, because that + * Independent VLAN Learning (IVL) is being used on every VID, each entry = only + * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC + * Bridge component or a C-VLAN component, there would have to be 16 times= 4096 + * entries. This switch intellectual property can only hold a maximum of 2= 048 + * entries. Using this option, there also isn't a mechanism to prevent + * link-local frames from being discarded when the spanning tree Port Stat= e of + * the reception Port is discarding. + * + * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RG= AC4 + * registers. Whilst this applies to every VID, it doesn't contain all of = the + * reserved MAC addresses without affecting the remaining Standard Group M= AC + * Addresses. The REV_UN frame tag utilised using the RGAC4 register cover= s the + * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination + * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF + * destination addresses which may be relayed by MAC Bridges or VLAN Bridg= es. + * The latter option provides better but not complete conformance. + * + * This switch intellectual property also does not provide a mechanism to = trap + * link-local frames with specific destination addresses to CPU port by Br= idge, + * to conform to the filtering rules for the distinct Bridge components. + * + * Therefore, regardless of the type of the Bridge component, link-local f= rames + * with these destination addresses will be trapped to CPU port: + * + * 01-80-C2-00-00-[00,01,02,03,0E] + * + * In a Bridge comprising a MAC Bridge component or a C-VLAN component: + * + * Link-local frames with these destination addresses won't be trapped t= o CPU + * port which won't conform to IEEE Std 802.1Q-2022: + * + * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] + * + * In a Bridge comprising an S-VLAN component: + * + * Link-local frames with these destination addresses will be trapped to= CPU + * port which won't conform to IEEE Std 802.1Q-2022: + * + * 01-80-C2-00-00-00 + * + * Link-local frames with these destination addresses won't be trapped t= o CPU + * port which won't conform to IEEE Std 802.1Q-2022: + * + * 01-80-C2-00-00-[04,05,06,07,08,09,0A] + * + * To trap link-local frames to CPU port as conformant as this switch + * intellectual property can allow, link-local frames are made to be regar= ded as + * Bridge Protocol Data Units (BPDUs). This is because this switch intelle= ctual + * property only lets the frames regarded as BPDUs bypass the spanning tre= e Port + * State function of the Forwarding Process. + * + * The only remaining interference is the ingress rules. When the receptio= n Port + * has no PVID assigned on software, VLAN-untagged frames won't be allowed= in. + * There doesn't seem to be a mechanism on the switch intellectual propert= y to + * have link-local frames bypass this function of the Forwarding Process. + */ +void mt7530_lib_trap_frames(struct mt7530_lib_priv *priv) +{ + /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress + * them with the EG_TAG attribute set to disabled (system default) + * so that any VLAN tags in the frame are not modified by the + * switch egress VLAN tag processing. This preserves VLAN tags + * for reception on VLAN sub-interfaces. + */ + regmap_field_write(priv->fields[MT7530_BPDU_EG_TAG], + MT7530_VLAN_EG_DISABLED); + regmap_field_write(priv->fields[MT7530_BPDU_PORT_FW], + TO_CPU_FW_CPU_ONLY); + regmap_field_write(priv->fields[MT7530_PAE_BPDU_FR], 1); + regmap_field_write(priv->fields[MT7530_PAE_EG_TAG], + MT7530_VLAN_EG_DISABLED); + regmap_field_write(priv->fields[MT7530_PAE_PORT_FW], + TO_CPU_FW_CPU_ONLY); + + /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and + * egress them with EG_TAG disabled. + */ + regmap_field_write(priv->fields[MT7530_R01_BPDU_FR], 1); + regmap_field_write(priv->fields[MT7530_R01_EG_TAG], + MT7530_VLAN_EG_DISABLED); + regmap_field_write(priv->fields[MT7530_R01_PORT_FW], + TO_CPU_FW_CPU_ONLY); + regmap_field_write(priv->fields[MT7530_R02_BPDU_FR], 1); + regmap_field_write(priv->fields[MT7530_R02_EG_TAG], + MT7530_VLAN_EG_DISABLED); + regmap_field_write(priv->fields[MT7530_R02_PORT_FW], + TO_CPU_FW_CPU_ONLY); + + /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and + * egress them with EG_TAG disabled. + */ + regmap_field_write(priv->fields[MT7530_R03_BPDU_FR], 1); + regmap_field_write(priv->fields[MT7530_R03_EG_TAG], + MT7530_VLAN_EG_DISABLED); + regmap_field_write(priv->fields[MT7530_R03_PORT_FW], + TO_CPU_FW_CPU_ONLY); + regmap_field_write(priv->fields[MT7530_R0E_BPDU_FR], 1); + regmap_field_write(priv->fields[MT7530_R0E_EG_TAG], + MT7530_VLAN_EG_DISABLED); + regmap_field_write(priv->fields[MT7530_R0E_PORT_FW], + TO_CPU_FW_CPU_ONLY); +} +EXPORT_SYMBOL_GPL(mt7530_lib_trap_frames); + +static void mt7530_update_port_member(struct mt7530_lib_priv *priv, int po= rt, + const struct net_device *bridge_dev, + bool join) __must_hold(priv->reg_mutex) +{ + struct dsa_port *dp =3D dsa_to_port(priv->ds, port), *other_dp; + struct mt7530_port *p =3D &priv->ports[port], *other_p; + struct dsa_port *cpu_dp =3D dp->cpu_dp; + u32 port_bitmap =3D BIT(cpu_dp->index); + int other_port; + bool isolated; + + dsa_switch_for_each_user_port(other_dp, priv->ds) { + other_port =3D other_dp->index; + other_p =3D &priv->ports[other_port]; + + if (dp =3D=3D other_dp) + continue; + + /* Add/remove this port to/from the port matrix of the other + * ports in the same bridge. If the port is disabled, port + * matrix is kept and not being setup until the port becomes + * enabled. + */ + if (!dsa_port_offloads_bridge_dev(other_dp, bridge_dev)) + continue; + + isolated =3D p->isolated && other_p->isolated; + + if (join && !isolated) { + other_p->pm |=3D BIT(port); + port_bitmap |=3D BIT(other_port); + } else { + other_p->pm &=3D ~BIT(port); + } + + if (other_p->enable) + regmap_fields_write(priv->fields[MT7530_PCR_MATRIX], + other_port, other_p->pm); + } + + /* Add/remove the all other ports to this port matrix. For !join + * (leaving the bridge), only the CPU port will remain in the port matrix + * of this port. + */ + p->pm =3D port_bitmap; + if (priv->ports[port].enable) + regmap_fields_write(priv->fields[MT7530_PCR_MATRIX], + port, port_bitmap); +} + +void mt7530_lib_read_port_stats(struct regmap_field *low, + struct regmap_field *high, + int port, uint64_t *data) +{ + u32 val =3D 0; + + regmap_fields_read(low, port, &val); + *data =3D val; + + if (high) { + val =3D 0; + regmap_fields_read(high, port, &val); + *data |=3D (u64)val << 32; + } +} +EXPORT_SYMBOL_GPL(mt7530_lib_read_port_stats); + +void mt7530_lib_get_eth_mac_stats(struct mt7530_lib_priv *priv, int port, + struct ethtool_eth_mac_stats *mac_stats) +{ + /* MIB counter doesn't provide a FramesTransmittedOK but instead + * provide stats for Unicast, Broadcast and Multicast frames separately. + * To simulate a global frame counter, read Unicast and addition Multicast + * and Broadcast later + */ + mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_UNICAST], NULL, por= t, + &mac_stats->FramesTransmittedOK); + + mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_SINGLE_COLLISION], = NULL, port, + &mac_stats->SingleCollisionFrames); + + mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_MULTIPLE_COLLISION]= , NULL, port, + &mac_stats->MultipleCollisionFrames); + + mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_UNICAST], NULL, por= t, + &mac_stats->FramesReceivedOK); + + mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_BYTES_LOW], + priv->fields[MT7530_MIB_TX_BYTES_HIGH], port, + &mac_stats->OctetsTransmittedOK); + + mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_ALIGN_ERR], NULL, p= ort, + &mac_stats->AlignmentErrors); + + mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_DEFERRED], NULL, po= rt, + &mac_stats->FramesWithDeferredXmissions); + + mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_LATE_COLLISION], NU= LL, port, + &mac_stats->LateCollisions); + + mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_EXCESSIVE_COLLISION= ], NULL, port, + &mac_stats->FramesAbortedDueToXSColls); + + mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_BYTES_LOW], + priv->fields[MT7530_MIB_RX_BYTES_HIGH], port, + &mac_stats->OctetsReceivedOK); + + mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_MULTICAST], NULL, p= ort, + &mac_stats->MulticastFramesXmittedOK); + mac_stats->FramesTransmittedOK +=3D mac_stats->MulticastFramesXmittedOK; + mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_BROADCAST], NULL, p= ort, + &mac_stats->BroadcastFramesXmittedOK); + mac_stats->FramesTransmittedOK +=3D mac_stats->BroadcastFramesXmittedOK; + + mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_MULTICAST], NULL, p= ort, + &mac_stats->MulticastFramesReceivedOK); + mac_stats->FramesReceivedOK +=3D mac_stats->MulticastFramesReceivedOK; + mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_BROADCAST], NULL, p= ort, + &mac_stats->BroadcastFramesReceivedOK); + mac_stats->FramesReceivedOK +=3D mac_stats->BroadcastFramesReceivedOK; +} +EXPORT_SYMBOL_GPL(mt7530_lib_get_eth_mac_stats); + +void mt7530_lib_get_rmon_stats(struct mt7530_lib_priv *priv, int port, + struct ethtool_rmon_stats *rmon_stats, + const struct ethtool_rmon_hist_range **ranges, + const struct mt7530_rmon_hist *ranges_info) +{ + int i; + + mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_UNDER_SIZE_ERR], NU= LL, port, + &rmon_stats->undersize_pkts); + mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_OVER_SZ_ERR], NULL,= port, + &rmon_stats->oversize_pkts); + mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_FRAG_ERR], NULL, po= rt, + &rmon_stats->fragments); + mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_JABBER_ERR], NULL, = port, + &rmon_stats->jabbers); + + for (i =3D 0; i < ranges_info->num_ranges; i++) { + unsigned int field =3D ranges_info->ranges_fields[i]; + unsigned int field_tx =3D ranges_info->ranges_tx_fields[i]; + + mt7530_lib_read_port_stats(priv->fields[field], NULL, port, + &rmon_stats->hist[i]); + mt7530_lib_read_port_stats(priv->fields[field_tx], NULL, port, + &rmon_stats->hist_tx[i]); + } + + *ranges =3D ranges_info->ranges; +} +EXPORT_SYMBOL_GPL(mt7530_lib_get_rmon_stats); + +void mt7530_lib_get_eth_ctrl_stats(struct mt7530_lib_priv *priv, int port, + struct ethtool_eth_ctrl_stats *ctrl_stats) +{ + mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_PAUSE], NULL, port, + &ctrl_stats->MACControlFramesTransmitted); + mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_PAUSE], NULL, port, + &ctrl_stats->MACControlFramesReceived); +} +EXPORT_SYMBOL_GPL(mt7530_lib_get_eth_ctrl_stats); + +int mt7530_lib_fdb_cmd(struct mt7530_lib_priv *priv, enum mt7530_fdb_cmd c= md, + u32 mat, u32 *rsp) +{ + u32 val; + int ret; + + ret =3D regmap_field_write(priv->fields[MT7530_ATC_MAT], mat); + if (ret) + return ret; + + ret =3D regmap_field_write(priv->fields[MT7530_ATC_CMD], cmd); + if (ret) + return ret; + + ret =3D regmap_field_write(priv->fields[MT7530_ATC_BUSY], 1); + if (ret) + return ret; + + ret =3D regmap_field_read_poll_timeout(priv->fields[MT7530_ATC_BUSY], + val, !val, 20, 20000); + if (ret < 0) { + dev_err(priv->dev, "reset timeout\n"); + return ret; + } + + regmap_field_read(priv->fields[MT7530_ATC_INVALID], &val); + if (cmd =3D=3D MT7530_FDB_READ && val) + return -EINVAL; + + if (rsp) + regmap_field_read(priv->fields[__MT7530_ATC], rsp); + + return 0; +} +EXPORT_SYMBOL_GPL(mt7530_lib_fdb_cmd); + +static void mt7530_lib_fdb_write(struct mt7530_lib_priv *priv, u16 vid, + u8 port_mask, const u8 *mac, + u8 aging, u8 type) +{ + /* Clear ATWD registers from previous access */ + regmap_field_write(priv->fields[__MT7530_ATWD1], 0); + regmap_field_write(priv->fields[__MT7530_ATWD2], 0); + regmap_field_write(priv->fields[__MT7530_ATWD3], 0); + + regmap_field_write(priv->fields[MT7530_ATWD_CVID], vid); + regmap_field_write(priv->fields[MT7530_ATWD_IVL], 1); + regmap_field_write(priv->fields[MT7530_ATWD_FID], FID_BRIDGED); + regmap_field_write(priv->fields[MT7530_ATWD_AGE_TIMER], aging); + regmap_field_write(priv->fields[MT7530_ATWD_PORT_MAP], port_mask); + /* STATIC_ENT indicate that entry is static wouldn't + * be aged out and STATIC_EMP specified as erasing an + * entry + */ + regmap_field_write(priv->fields[MT7530_ATWD_ENT_STATUS], type); + regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_5], mac[5]); + regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_4], mac[4]); + regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_3], mac[3]); + regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_2], mac[2]); + regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_1], mac[1]); + regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_0], mac[0]); +} + +void mt7530_lib_fdb_read(struct mt7530_lib_priv *priv, struct mt7530_fdb *= fdb) +{ + u32 val =3D 0; + + regmap_field_read(priv->fields[MT7530_ATRD_CVID], &val); + fdb->vid =3D val; + regmap_field_read(priv->fields[MT7530_ATRD_AGE_TIMER], &val); + fdb->aging =3D val; + regmap_field_read(priv->fields[MT7530_ATRD_PORT_MAP], &val); + fdb->port_mask =3D val; + regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_5], &val); + fdb->mac[5] =3D val; + regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_4], &val); + fdb->mac[4] =3D val; + regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_3], &val); + fdb->mac[3] =3D val; + regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_2], &val); + fdb->mac[2] =3D val; + regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_1], &val); + fdb->mac[1] =3D val; + regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_0], &val); + fdb->mac[0] =3D val; + regmap_field_read(priv->fields[MT7530_ATRD_ENT_STATUS], &val); + fdb->noarp =3D val =3D=3D STATIC_ENT; +} +EXPORT_SYMBOL_GPL(mt7530_lib_fdb_read); + +void mt7530_lib_port_fast_age(struct mt7530_lib_priv *priv, int port) +{ + mutex_lock(priv->reg_mutex); + + /* Flush all non-static MAC address entries */ + mt7530_lib_fdb_cmd(priv, MT7530_FDB_FLUSH, + ATC_MAT_NON_STATIC_MAC, NULL); + + mutex_unlock(priv->reg_mutex); +} +EXPORT_SYMBOL_GPL(mt7530_lib_port_fast_age); + +int mt7530_lib_port_fdb_add(struct mt7530_lib_priv *priv, int port, + const unsigned char *addr, u16 vid, + struct dsa_db db) +{ + u8 port_mask =3D BIT(port); + int ret; + + mutex_lock(priv->reg_mutex); + mt7530_lib_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); + ret =3D mt7530_lib_fdb_cmd(priv, MT7530_FDB_WRITE, + ATC_MAT_MACTAB, NULL); + mutex_unlock(priv->reg_mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(mt7530_lib_port_fdb_add); + +int mt7530_lib_port_fdb_del(struct mt7530_lib_priv *priv, int port, + const unsigned char *addr, u16 vid, + struct dsa_db db) +{ + u8 port_mask =3D BIT(port); + int ret; + + mutex_lock(priv->reg_mutex); + mt7530_lib_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); + ret =3D mt7530_lib_fdb_cmd(priv, MT7530_FDB_WRITE, + ATC_MAT_MACTAB, NULL); + mutex_unlock(priv->reg_mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(mt7530_lib_port_fdb_del); + +int mt7530_lib_port_mdb_add(struct mt7530_lib_priv *priv, int port, + const struct switchdev_obj_port_mdb *mdb, + struct dsa_db db) +{ + const u8 *addr =3D mdb->addr; + u16 vid =3D mdb->vid; + u8 port_mask =3D 0; + u32 val; + int ret; + + mutex_lock(priv->reg_mutex); + + mt7530_lib_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); + if (!mt7530_lib_fdb_cmd(priv, MT7530_FDB_READ, + ATC_MAT_MACTAB, NULL)) { + regmap_field_read(priv->fields[MT7530_ATRD_PORT_MAP], + &val); + port_mask =3D val; + } + + port_mask |=3D BIT(port); + mt7530_lib_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); + ret =3D mt7530_lib_fdb_cmd(priv, MT7530_FDB_WRITE, + ATC_MAT_MACTAB, NULL); + + mutex_unlock(priv->reg_mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(mt7530_lib_port_mdb_add); + +int mt7530_lib_port_mdb_del(struct mt7530_lib_priv *priv, int port, + const struct switchdev_obj_port_mdb *mdb, + struct dsa_db db) +{ + const u8 *addr =3D mdb->addr; + u16 vid =3D mdb->vid; + u8 port_mask =3D 0; + u32 val; + int ret; + + mutex_lock(priv->reg_mutex); + + mt7530_lib_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); + if (!mt7530_lib_fdb_cmd(priv, MT7530_FDB_READ, + ATC_MAT_MACTAB, NULL)) { + regmap_field_read(priv->fields[MT7530_ATRD_PORT_MAP], + &val); + port_mask =3D val; + } + + port_mask &=3D ~BIT(port); + mt7530_lib_fdb_write(priv, vid, port_mask, addr, -1, + port_mask ? STATIC_ENT : STATIC_EMP); + ret =3D mt7530_lib_fdb_cmd(priv, MT7530_FDB_WRITE, + ATC_MAT_MACTAB, NULL); + + mutex_unlock(priv->reg_mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(mt7530_lib_port_mdb_del); + +int mt7530_lib_port_mirror_add(struct mt7530_lib_priv *priv, int port, + struct dsa_mall_mirror_tc_entry *mirror, + bool ingress, struct netlink_ext_ack *extack) +{ + u32 monitor_port, val =3D 0; + int ret; + + /* Check for existent entry */ + if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) + return -EEXIST; + + regmap_field_read(priv->fields[MT7530_MIRROR_EN], &val); + ret =3D regmap_field_read(priv->fields[MT7530_MIRROR_PORT], &monitor_port= ); + if (ret) + return ret; + + /* MT7530 only supports one monitor port */ + if (val && monitor_port !=3D mirror->to_local_port) + return -EEXIST; + + regmap_field_write(priv->fields[MT7530_MIRROR_PORT], + mirror->to_local_port); + regmap_field_write(priv->fields[MT7530_MIRROR_EN], 1); + + if (ingress) { + regmap_fields_write(priv->fields[MT7530_PCR_PORT_RX_MIR], port, 1); + priv->mirror_rx |=3D BIT(port); + } else { + regmap_fields_write(priv->fields[MT7530_PCR_PORT_TX_MIR], port, 1); + priv->mirror_tx |=3D BIT(port); + } + + return 0; +} +EXPORT_SYMBOL_GPL(mt7530_lib_port_mirror_add); + +void mt7530_lib_port_mirror_del(struct mt7530_lib_priv *priv, int port, + struct dsa_mall_mirror_tc_entry *mirror) +{ + if (mirror->ingress) { + regmap_fields_write(priv->fields[MT7530_PCR_PORT_RX_MIR], port, 0); + priv->mirror_rx &=3D ~BIT(port); + } else { + regmap_fields_write(priv->fields[MT7530_PCR_PORT_TX_MIR], port, 0); + priv->mirror_tx &=3D ~BIT(port); + } + + if (!priv->mirror_rx && !priv->mirror_tx) + regmap_field_write(priv->fields[MT7530_MIRROR_EN], 0); +} +EXPORT_SYMBOL_GPL(mt7530_lib_port_mirror_del); + +int mt7530_lib_port_change_mtu(struct mt7530_lib_priv *priv, int port, int= new_mtu) +{ + int length; + + /* When a new MTU is set, DSA always set the CPU port's MTU to the + * largest MTU of the user ports. Because the switch only has a global + * RX length register, only allowing CPU port here is enough. + */ + if (!dsa_is_cpu_port(priv->ds, port)) + return 0; + + /* RX length also includes Ethernet header, MTK tag, and FCS length */ + length =3D new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; + if (length <=3D 1522) { + regmap_field_write(priv->fields[MT7530_GMACCR_MAX_RX_PKT_LEN], + MAX_RX_PKT_LEN_1522); + } else if (length <=3D 1536) { + regmap_field_write(priv->fields[MT7530_GMACCR_MAX_RX_PKT_LEN], + MAX_RX_PKT_LEN_1536); + } else if (length <=3D 1552) { + regmap_field_write(priv->fields[MT7530_GMACCR_MAX_RX_PKT_LEN], + MAX_RX_PKT_LEN_1552); + } else { + regmap_field_write(priv->fields[MT7530_GMACCR_MAX_RX_JUMBO], + DIV_ROUND_UP(length, 1024)); + regmap_field_write(priv->fields[MT7530_GMACCR_MAX_RX_PKT_LEN], + MAX_RX_PKT_LEN_JUMBO); + } + + return 0; +} +EXPORT_SYMBOL_GPL(mt7530_lib_port_change_mtu); + +void mt7530_lib_stp_state_set(struct mt7530_lib_priv *priv, int port, u8 s= tate) +{ + u32 stp_state; + + switch (state) { + case BR_STATE_DISABLED: + stp_state =3D MT7530_STP_DISABLED; + break; + case BR_STATE_BLOCKING: + stp_state =3D MT7530_STP_BLOCKING; + break; + case BR_STATE_LISTENING: + stp_state =3D MT7530_STP_LISTENING; + break; + case BR_STATE_LEARNING: + stp_state =3D MT7530_STP_LEARNING; + break; + case BR_STATE_FORWARDING: + default: + stp_state =3D MT7530_STP_FORWARDING; + break; + } + + regmap_fields_update_bits(priv->fields[MT7530_SSP_FID_PST], + port, FID_PST_MASK(FID_BRIDGED), + FID_PST(FID_BRIDGED, stp_state)); +} +EXPORT_SYMBOL_GPL(mt7530_lib_stp_state_set); + +int mt7530_lib_port_bridge_flags(struct mt7530_lib_priv *priv, int port, + struct switchdev_brport_flags flags, + struct netlink_ext_ack *extack) +{ + struct dsa_switch *ds =3D priv->ds; + + if (flags.mask & BR_LEARNING) + regmap_fields_write(priv->fields[MT7530_PSC_SA_DIS], + port, !(flags.val & BR_LEARNING)); + + if (flags.mask & BR_FLOOD) + regmap_field_update_bits(priv->fields[MT7530_UNU_FFP], + BIT(port), + flags.val & BR_FLOOD ? BIT(port) : 0); + + if (flags.mask & BR_MCAST_FLOOD) + regmap_field_update_bits(priv->fields[MT7530_UNM_FFP], + BIT(port), + flags.val & BR_MCAST_FLOOD ? BIT(port) : 0); + + if (flags.mask & BR_BCAST_FLOOD) + regmap_field_update_bits(priv->fields[MT7530_BC_FFP], + BIT(port), + flags.val & BR_BCAST_FLOOD ? BIT(port) : 0); + + if (flags.mask & BR_ISOLATED) { + struct dsa_port *dp =3D dsa_to_port(ds, port); + struct net_device *bridge_dev =3D dsa_port_bridge_dev_get(dp); + + priv->ports[port].isolated =3D !!(flags.val & BR_ISOLATED); + + mutex_lock(priv->reg_mutex); + mt7530_update_port_member(priv, port, bridge_dev, true); + mutex_unlock(priv->reg_mutex); + } + + return 0; +} +EXPORT_SYMBOL_GPL(mt7530_lib_port_bridge_flags); + +int mt7530_lib_port_bridge_join(struct mt7530_lib_priv *priv, int port, + struct dsa_bridge bridge, bool *tx_fwd_offload, + struct netlink_ext_ack *extack) +{ + mutex_lock(priv->reg_mutex); + + mt7530_update_port_member(priv, port, bridge.dev, true); + + /* Set to fallback mode for independent VLAN learning */ + regmap_fields_write(priv->fields[MT7530_PCR_PORT_VLAN], + port, MT7530_PORT_FALLBACK_MODE); + + mutex_unlock(priv->reg_mutex); + + return 0; +} +EXPORT_SYMBOL_GPL(mt7530_lib_port_bridge_join); + +void mt7530_lib_port_bridge_leave(struct mt7530_lib_priv *priv, int port, + struct dsa_bridge bridge) +{ + mutex_lock(priv->reg_mutex); + + mt7530_update_port_member(priv, port, bridge.dev, false); + + /* When a port is removed from the bridge, the port would be set up + * back to the default as is at initial boot which is a VLAN-unaware + * port. + */ + regmap_fields_write(priv->fields[MT7530_PCR_PORT_VLAN], + port, MT7530_PORT_MATRIX_MODE); + + mutex_unlock(priv->reg_mutex); +} +EXPORT_SYMBOL_GPL(mt7530_lib_port_bridge_leave); + +static void mt7530_port_set_vlan_unaware(struct mt7530_lib_priv *priv, int= port) +{ + struct dsa_switch *ds =3D priv->ds; + bool all_user_ports_removed =3D true; + int i; + + /* This is called after .port_bridge_leave when leaving a VLAN-aware + * bridge. Don't set standalone ports to fallback mode. + */ + if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) + regmap_fields_write(priv->fields[MT7530_PCR_PORT_VLAN], + port, MT7530_PORT_FALLBACK_MODE); + + regmap_fields_write(priv->fields[MT7530_PVC_VLAN_ATTR], + port, MT7530_VLAN_TRANSPARENT); + regmap_fields_write(priv->fields[MT7530_PVC_EG_TAG], + port, MT7530_VLAN_EG_CONSISTENT); + regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM], + port, MT7530_VLAN_ACC_ALL); + + regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID], + port, G0_PORT_VID_DEF); + + for (i =3D 0; i < priv->ds->num_ports; i++) { + if (i =3D=3D port) + continue; + if (dsa_is_user_port(ds, i) && + dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { + all_user_ports_removed =3D false; + break; + } + } + + /* CPU port also does the same thing until all user ports belonging to + * the CPU port get out of VLAN filtering mode. + */ + if (all_user_ports_removed) { + mutex_lock(priv->reg_mutex); + mt7530_lib_setup_vlan0(priv); + mutex_unlock(priv->reg_mutex); + } +} + +static void mt7530_port_set_vlan_aware(struct mt7530_lib_priv *priv, int p= ort) +{ + struct dsa_switch *ds =3D priv->ds; + + /* Trapped into security mode allows packet forwarding through VLAN + * table lookup. + */ + if (dsa_is_user_port(ds, port)) { + regmap_fields_write(priv->fields[MT7530_PCR_PORT_VLAN], + port, MT7530_PORT_SECURITY_MODE); + regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID], + port, priv->ports[port].pvid); + + /* Only accept tagged frames if PVID is not set */ + if (!priv->ports[port].pvid) + regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM], + port, MT7530_VLAN_ACC_TAGGED); + + /* Set the port as a user port which is to be able to recognize + * VID from incoming packets before fetching entry within the + * VLAN table. + */ + regmap_fields_write(priv->fields[MT7530_PVC_VLAN_ATTR], + port, MT7530_VLAN_USER); + regmap_fields_write(priv->fields[MT7530_PVC_EG_TAG], + port, MT7530_VLAN_EG_DISABLED); + } else { + /* Also set CPU ports to the "user" VLAN port attribute, to + * allow VLAN classification, but keep the EG_TAG attribute as + * "consistent" (i.o.w. don't change its value) for packets + * received by the switch from the CPU, so that tagged packets + * are forwarded to user ports as tagged, and untagged as + * untagged. + */ + regmap_fields_write(priv->fields[MT7530_PVC_VLAN_ATTR], + port, MT7530_VLAN_USER); + } +} + +int mt7530_lib_port_vlan_filtering(struct mt7530_lib_priv *priv, int port,= bool vlan_filtering, + struct netlink_ext_ack *extack) +{ + struct dsa_switch *ds =3D priv->ds; + struct dsa_port *cpu_dp, *dp; + + dp =3D dsa_to_port(ds, port); + cpu_dp =3D dp->cpu_dp; + + if (vlan_filtering) { + /* The port is being kept as VLAN-unaware port when bridge is + * set up with vlan_filtering not being set, Otherwise, the + * port and the corresponding CPU port is required the setup + * for becoming a VLAN-aware port. + */ + mt7530_port_set_vlan_aware(priv, port); + mt7530_port_set_vlan_aware(priv, cpu_dp->index); + } else { + mt7530_port_set_vlan_unaware(priv, port); + } + + return 0; +} +EXPORT_SYMBOL_GPL(mt7530_lib_port_vlan_filtering); + +static int mt7530_vlan_cmd(struct mt7530_lib_priv *priv, enum mt7530_vlan_= cmd cmd, + u16 vid) +{ + u32 val; + int ret; + + ret =3D regmap_field_write(priv->fields[MT7530_VTCR_FUNC], cmd); + if (ret) + return ret; + + ret =3D regmap_field_write(priv->fields[MT7530_VTCR_VID], vid); + if (ret) + return ret; + + ret =3D regmap_field_write(priv->fields[MT7530_VTCR_BUSY], 1); + if (ret) + return ret; + + ret =3D regmap_field_read_poll_timeout(priv->fields[MT7530_VTCR_BUSY], + val, !val, 20, 20000); + if (ret < 0) { + dev_err(priv->dev, "poll timeout\n"); + return ret; + } + + regmap_field_read(priv->fields[MT7530_VTCR_INVALID], &val); + if (val) { + dev_err(priv->dev, "read VTCR invalid\n"); + return -EINVAL; + } + + return 0; +} + +static void mt7530_hw_vlan_add(struct mt7530_lib_priv *priv, + struct mt7530_hw_vlan_entry *entry) +{ + struct dsa_port *dp =3D dsa_to_port(priv->ds, entry->port); + u8 new_members; + u32 val; + + new_members =3D entry->old_members | BIT(entry->port); + + /* Validate the entry with independent learning, create egress tag per + * VLAN and joining the port as one of the port members. + */ + regmap_field_write(priv->fields[MT7530_VAWD_IVL_MAC], 1); + regmap_field_write(priv->fields[MT7530_VAWD_VTAG_EN], 1); + regmap_field_write(priv->fields[MT7530_VAWD_PORT_MEM], + new_members); + regmap_field_write(priv->fields[MT7530_VAWD_FID], + FID_BRIDGED); + regmap_field_write(priv->fields[MT7530_VAWD_VLAN_VALID], 1); + + /* Decide whether adding tag or not for those outgoing packets from the + * port inside the VLAN. + * CPU port is always taken as a tagged port for serving more than one + * VLANs across and also being applied with egress type stack mode for + * that VLAN tags would be appended after hardware special tag used as + * DSA tag. + */ + if (dsa_port_is_cpu(dp)) + val =3D MT7530_VLAN_EGRESS_STACK; + else if (entry->untagged) + val =3D MT7530_VLAN_EGRESS_UNTAG; + else + val =3D MT7530_VLAN_EGRESS_TAG; + regmap_field_update_bits(priv->fields[MT7530_VAWD_ETAG], + ETAG_CTRL_P_MASK(entry->port), + ETAG_CTRL_P(entry->port, val)); +} + +static void mt7530_hw_vlan_del(struct mt7530_lib_priv *priv, + struct mt7530_hw_vlan_entry *entry) +{ + u8 new_members; + u32 val; + + new_members =3D entry->old_members & ~BIT(entry->port); + + regmap_field_read(priv->fields[MT7530_VAWD_VLAN_VALID], &val); + if (!val) { + dev_err(priv->dev, + "Cannot be deleted due to invalid entry\n"); + return; + } + + if (new_members) { + regmap_field_write(priv->fields[MT7530_VAWD_IVL_MAC], 1); + regmap_field_write(priv->fields[MT7530_VAWD_VTAG_EN], 1); + regmap_field_write(priv->fields[MT7530_VAWD_PORT_MEM], + new_members); + regmap_field_write(priv->fields[MT7530_VAWD_VLAN_VALID], 1); + } else { + regmap_field_write(priv->fields[__MT7530_VAWD1], 0); + regmap_field_write(priv->fields[__MT7530_VAWD2], 0); + } +} + +static void mt7530_hw_vlan_update(struct mt7530_lib_priv *priv, u16 vid, + struct mt7530_hw_vlan_entry *entry, + mt7530_vlan_op vlan_op) +{ + u32 val =3D 0; + + /* Fetch entry */ + mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); + + regmap_field_read(priv->fields[MT7530_VAWD_PORT_MEM], &val); + entry->old_members =3D val; + + /* Manipulate entry */ + vlan_op(priv, entry); + + /* Flush result to hardware */ + mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); +} + +int mt7530_lib_port_vlan_add(struct mt7530_lib_priv *priv, int port, + const struct switchdev_obj_port_vlan *vlan, + struct netlink_ext_ack *extack) +{ + bool untagged =3D vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; + bool pvid =3D vlan->flags & BRIDGE_VLAN_INFO_PVID; + struct mt7530_hw_vlan_entry new_entry; + struct dsa_switch *ds =3D priv->ds; + + mutex_lock(priv->reg_mutex); + + /* VID 0 is managed exclusively by mt7530_lib_setup_vlan0() for + * VLAN-unaware bridge operation. Don't let the bridge overwrite + * its EG_CON flag with VTAG_EN and corrupt PORT_MEM. + */ + if (vlan->vid =3D=3D 0) + goto skip_vlan_table; + + mt7530_hw_vlan_entry_init(&new_entry, port, untagged); + mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); + +skip_vlan_table: + + if (pvid) { + priv->ports[port].pvid =3D vlan->vid; + + /* Accept all frames if PVID is set */ + regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM], + port, MT7530_VLAN_ACC_ALL); + + /* Only configure PVID if VLAN filtering is enabled */ + if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) + regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID], + port, vlan->vid); + } else if (vlan->vid && priv->ports[port].pvid =3D=3D vlan->vid) { + /* This VLAN is overwritten without PVID, so unset it */ + priv->ports[port].pvid =3D G0_PORT_VID_DEF; + + /* Only accept tagged frames if the port is VLAN-aware */ + if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) + regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM], + port, MT7530_VLAN_ACC_TAGGED); + + regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID], + port, G0_PORT_VID_DEF); + } + + mutex_unlock(priv->reg_mutex); + + return 0; +} +EXPORT_SYMBOL_GPL(mt7530_lib_port_vlan_add); + +int mt7530_lib_port_vlan_del(struct mt7530_lib_priv *priv, int port, + const struct switchdev_obj_port_vlan *vlan) +{ + struct mt7530_hw_vlan_entry target_entry; + struct dsa_switch *ds =3D priv->ds; + + mutex_lock(priv->reg_mutex); + + /* VID 0 is managed exclusively by mt7530_lib_setup_vlan0(). */ + if (vlan->vid =3D=3D 0) + goto skip_vlan_table; + + mt7530_hw_vlan_entry_init(&target_entry, port, 0); + mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, + mt7530_hw_vlan_del); + +skip_vlan_table: + /* PVID is being restored to the default whenever the PVID port + * is being removed from the VLAN. + */ + if (priv->ports[port].pvid =3D=3D vlan->vid) { + priv->ports[port].pvid =3D G0_PORT_VID_DEF; + + /* Only accept tagged frames if the port is VLAN-aware */ + if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) + regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM], + port, MT7530_VLAN_ACC_TAGGED); + + regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID], + port, G0_PORT_VID_DEF); + } + + mutex_unlock(priv->reg_mutex); + + return 0; +} +EXPORT_SYMBOL_GPL(mt7530_lib_port_vlan_del); + +int mt7530_lib_setup_vlan0(struct mt7530_lib_priv *priv) +{ + /* Clear VAWD registers from previous access */ + regmap_field_write(priv->fields[__MT7530_VAWD1], 0); + regmap_field_write(priv->fields[__MT7530_VAWD2], 0); + + regmap_field_write(priv->fields[MT7530_VAWD_IVL_MAC], 1); + regmap_field_write(priv->fields[MT7530_VAWD_VTAG_EN], 0); + regmap_field_write(priv->fields[MT7530_VAWD_EG_CON], 1); + regmap_field_write(priv->fields[MT7530_VAWD_PORT_MEM], + MT7530_ALL_MEMBERS); + regmap_field_write(priv->fields[MT7530_VAWD_FID], + FID_BRIDGED); + regmap_field_write(priv->fields[MT7530_VAWD_VLAN_VALID], 1); + regmap_field_write(priv->fields[__MT7530_VAWD2], 0); + + return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); +} +EXPORT_SYMBOL_GPL(mt7530_lib_setup_vlan0); + +MODULE_AUTHOR("Christian Marangi "); +MODULE_DESCRIPTION("Library Driver for Mediatek MT7530 Based Switch"); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/dsa/mediatek/mt7530-lib.h b/drivers/net/dsa/mediat= ek/mt7530-lib.h new file mode 100644 index 000000000000..da2ee781f7e6 --- /dev/null +++ b/drivers/net/dsa/mediatek/mt7530-lib.h @@ -0,0 +1,391 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __MT7530_LIB_H +#define __MT7530_LIB_H + +#define G0_PORT_VID_DEF 0 +#define MT7530_ALL_MEMBERS 0xff + +#define MTK_HDR_LEN 4 +#define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN) + +/* MT7530_ATA1 */ +#define STATIC_EMP 0 +#define STATIC_ENT 3 + +#define ATC_MAT_MACTAB 0 +#define ATC_MAT_NON_STATIC_MAC 4 + +enum mt7530_fdb_cmd { + MT7530_FDB_READ =3D 0, + MT7530_FDB_WRITE =3D 1, + MT7530_FDB_FLUSH =3D 2, + MT7530_FDB_START =3D 4, + MT7530_FDB_NEXT =3D 5, +}; + +enum mt7530_max_rx_pkt_len { + MAX_RX_PKT_LEN_1522 =3D 0, + MAX_RX_PKT_LEN_1536 =3D 1, + MAX_RX_PKT_LEN_1552 =3D 2, + MAX_RX_PKT_LEN_JUMBO =3D 3, +}; + +#define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2)) +#define FID_PST_MASK(fid) FID_PST(fid, 0x3) + +enum mt7530_stp_state { + MT7530_STP_DISABLED =3D 0, + MT7530_STP_BLOCKING =3D 1, + MT7530_STP_LISTENING =3D 1, + MT7530_STP_LEARNING =3D 2, + MT7530_STP_FORWARDING =3D 3 +}; + +/* Egress Tag Control */ +#define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1)) +#define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3) + +enum mt753x_to_cpu_fw { + TO_CPU_FW_SYSTEM_DEFAULT, + TO_CPU_FW_CPU_EXCLUDE =3D 4, + TO_CPU_FW_CPU_INCLUDE =3D 5, + TO_CPU_FW_CPU_ONLY =3D 6, + TO_CPU_FW_DROP =3D 7, +}; + +enum mt7530_port_mode { + /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */ + MT7530_PORT_MATRIX_MODE =3D 0, + + /* Fallback Mode: Forward received frames with ingress ports that do + * not belong to the VLAN member. Frames whose VID is not listed on + * the VLAN table are forwarded by the PCR_MATRIX members. + */ + MT7530_PORT_FALLBACK_MODE =3D 1, + + /* Security Mode: Discard any frame due to ingress membership + * violation or VID missed on the VLAN table. + */ + MT7530_PORT_SECURITY_MODE =3D 3, +}; + +enum mt7530_vlan_port_acc_frm { + MT7530_VLAN_ACC_ALL =3D 0, + MT7530_VLAN_ACC_TAGGED =3D 1, + MT7530_VLAN_ACC_UNTAGGED =3D 2, +}; + +enum mt7530_vlan_port_eg_tag { + MT7530_VLAN_EG_DISABLED =3D 0, + MT7530_VLAN_EG_CONSISTENT =3D 1, + MT7530_VLAN_EG_UNTAGGED =3D 4, +}; + +enum mt7530_vlan_port_attr { + MT7530_VLAN_USER =3D 0, + MT7530_VLAN_TRANSPARENT =3D 3, +}; + +enum mt7530_fid { + FID_STANDALONE =3D 0, + FID_BRIDGED =3D 1, +}; + +enum mt7530_vlan_egress_attr { + MT7530_VLAN_EGRESS_UNTAG =3D 0, + MT7530_VLAN_EGRESS_TAG =3D 2, + MT7530_VLAN_EGRESS_STACK =3D 3, +}; + +enum mt7530_vlan_cmd { + /* Read/Write the specified VID entry from VAWD register based + * on VID. + */ + MT7530_VTCR_RD_VID =3D 0, + MT7530_VTCR_WR_VID =3D 1, +}; + +enum mt7530_regmap_field { + MT7530_MIRROR_EN, + MT7530_MIRROR_PORT, + + MT7530_UNU_FFP, + MT7530_UNM_FFP, + MT7530_BC_FFP, + + MT7530_CCR_MIB_ENABLE, + MT7530_CCR_RX_OCT_CNT_GOOD, + MT7530_CCR_RX_OCT_CNT_BAD, + MT7530_CCR_TX_OCT_CNT_GOOD, + MT7530_CCR_TX_OCT_CNT_BAD, + + MT7530_BPDU_EG_TAG, + MT7530_BPDU_PORT_FW, + MT7530_PAE_BPDU_FR, + MT7530_PAE_EG_TAG, + MT7530_PAE_PORT_FW, + MT7530_R01_BPDU_FR, + MT7530_R01_EG_TAG, + MT7530_R01_PORT_FW, + MT7530_R02_BPDU_FR, + MT7530_R02_EG_TAG, + MT7530_R02_PORT_FW, + MT7530_R03_BPDU_FR, + MT7530_R03_EG_TAG, + MT7530_R03_PORT_FW, + MT7530_R0E_BPDU_FR, + MT7530_R0E_EG_TAG, + MT7530_R0E_PORT_FW, + + MT7530_VAWD_IVL_MAC, + MT7530_VAWD_EG_CON, + MT7530_VAWD_VTAG_EN, + MT7530_VAWD_PORT_MEM, + MT7530_VAWD_FID, + MT7530_VAWD_VLAN_VALID, + __MT7530_VAWD1, + + MT7530_VAWD_ETAG, + __MT7530_VAWD2, + + MT7530_VTCR_BUSY, + MT7530_VTCR_FUNC, + MT7530_VTCR_VID, + MT7530_VTCR_INVALID, + + MT7530_ATWD_CVID, + MT7530_ATWD_IVL, + MT7530_ATWD_FID, + MT7530_ATWD_AGE_TIMER, + MT7530_ATWD_PORT_MAP, + MT7530_ATWD_ENT_STATUS, + MT7530_ATWD_MAC_BYTE_5, + MT7530_ATWD_MAC_BYTE_4, + MT7530_ATWD_MAC_BYTE_3, + MT7530_ATWD_MAC_BYTE_2, + MT7530_ATWD_MAC_BYTE_1, + MT7530_ATWD_MAC_BYTE_0, + + __MT7530_ATWD1, + __MT7530_ATWD2, + __MT7530_ATWD3, + + MT7530_ATRD_CVID, + MT7530_ATRD_AGE_TIMER, + MT7530_ATRD_PORT_MAP, + MT7530_ATRD_ENT_STATUS, + MT7530_ATRD_MAC_BYTE_5, + MT7530_ATRD_MAC_BYTE_4, + MT7530_ATRD_MAC_BYTE_3, + MT7530_ATRD_MAC_BYTE_2, + MT7530_ATRD_MAC_BYTE_1, + MT7530_ATRD_MAC_BYTE_0, + + MT7530_ATC_BUSY, + MT7530_ATC_MAT, + MT7530_ATC_INVALID, + MT7530_ATC_CMD, + __MT7530_ATC, + + MT7530_SSP_FID_PST, + + MT7530_PCR_PORT_TX_MIR, + MT7530_PCR_PORT_RX_MIR, + MT7530_PCR_PORT_VLAN, + MT7530_PCR_MATRIX, + + MT7530_PSC_SA_DIS, + + MT7530_PVC_EG_TAG, + MT7530_PVC_VLAN_ATTR, + MT7530_PVC_ACC_FRM, + + MT7530_PPBV1_G0_PORT_VID, + + MT7530_GMACCR_MAX_RX_JUMBO, + MT7530_GMACCR_MAX_RX_PKT_LEN, + + MT7530_MIB_TX_DROP, + MT7530_MIB_TX_CRC_ERR, + MT7530_MIB_TX_UNICAST, + MT7530_MIB_TX_MULTICAST, + MT7530_MIB_TX_BROADCAST, + MT7530_MIB_TX_COLLISION, + MT7530_MIB_TX_SINGLE_COLLISION, + MT7530_MIB_TX_MULTIPLE_COLLISION, + MT7530_MIB_TX_DEFERRED, + MT7530_MIB_TX_LATE_COLLISION, + MT7530_MIB_TX_EXCESSIVE_COLLISION, + MT7530_MIB_TX_PAUSE, + MT7530_MIB_TX_PKT_SZ_64, + MT7530_MIB_TX_PKT_SZ_65_TO_127, + MT7530_MIB_TX_PKT_SZ_128_TO_255, + MT7530_MIB_TX_PKT_SZ_256_TO_511, + MT7530_MIB_TX_PKT_SZ_512_TO_1023, + MT7530_MIB_TX_PKT_SZ_1024_TO_MAX, + MT7530_MIB_TX_BYTES_LOW, + MT7530_MIB_TX_BYTES_HIGH, + MT7530_MIB_RX_DROP, + MT7530_MIB_RX_FILTERING, + MT7530_MIB_RX_UNICAST, + MT7530_MIB_RX_MULTICAST, + MT7530_MIB_RX_BROADCAST, + MT7530_MIB_RX_ALIGN_ERR, + MT7530_MIB_RX_CRC_ERR, + MT7530_MIB_RX_UNDER_SIZE_ERR, + MT7530_MIB_RX_FRAG_ERR, + MT7530_MIB_RX_OVER_SZ_ERR, + MT7530_MIB_RX_JABBER_ERR, + MT7530_MIB_RX_PAUSE, + MT7530_MIB_RX_PKT_SZ_64, + MT7530_MIB_RX_PKT_SZ_65_TO_127, + MT7530_MIB_RX_PKT_SZ_128_TO_255, + MT7530_MIB_RX_PKT_SZ_256_TO_511, + MT7530_MIB_RX_PKT_SZ_512_TO_1023, + MT7530_MIB_RX_PKT_SZ_1024_TO_MAX, + MT7530_MIB_RX_BYTES_LOW, + MT7530_MIB_RX_BYTES_HIGH, + MT7530_MIB_RX_CTRL_DROP, + MT7530_MIB_RX_INGRESS_DROP, + MT7530_MIB_RX_ARL_DROP, + + MT7530_FIELD_MAX, +}; + +struct mt7530_fdb { + u16 vid; + u8 port_mask; + u8 aging; + u8 mac[6]; + bool noarp; +}; + +struct mt7530_hw_vlan_entry { + int port; + u8 old_members; + bool untagged; +}; + +static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *= e, + int port, bool untagged) +{ + e->port =3D port; + e->untagged =3D untagged; +} + +#define MIB_DESC(_fl, _fh, _n) \ + { \ + .field_low =3D (_fl), \ + .field_high =3D (_fh), \ + .name =3D (_n), \ + } + +struct mt7530_mib_desc { + int field_low; + int field_high; + const char *name; +}; + +struct mt7530_rmon_hist { + unsigned int *ranges_fields; + unsigned int *ranges_tx_fields; + const struct ethtool_rmon_hist_range *ranges; + unsigned int num_ranges; +}; + +struct mt7530_reg_field { + unsigned int id; + const struct reg_field field; +}; + +/* struct mt7530_port - This is the main data structure for holding the st= ate + * of the port. + * @enable: The status used for show port is enabled or not. + * @pm: The matrix used to show all connections with the port. + * @pvid: The VLAN specified is to be considered a PVID at ingress. Any + * untagged frames will be assigned to the related VLAN. + * @sgmii_pcs: Pointer to PCS instance for SerDes ports + * @stats: Cached port statistics for MDIO-connected switches + */ +struct mt7530_port { + bool enable; + bool isolated; + u32 pm; + u16 pvid; + struct phylink_pcs *sgmii_pcs; + struct rtnl_link_stats64 stats; +}; + +struct mt7530_lib_priv { + struct device *dev; + struct dsa_switch *ds; + struct regmap *regmap; + struct regmap_field *fields[MT7530_FIELD_MAX]; + + u8 mirror_rx; + u8 mirror_tx; + + struct mt7530_port *ports; + struct mutex *reg_mutex; +}; + +typedef void (*mt7530_vlan_op)(struct mt7530_lib_priv *, + struct mt7530_hw_vlan_entry *); + +void mt7530_lib_mib_reset(struct mt7530_lib_priv *priv); +void mt7530_lib_trap_frames(struct mt7530_lib_priv *priv); + +void mt7530_lib_read_port_stats(struct regmap_field *low, + struct regmap_field *high, + int port, uint64_t *data); +void mt7530_lib_get_eth_mac_stats(struct mt7530_lib_priv *priv, int port, + struct ethtool_eth_mac_stats *mac_stats); +void mt7530_lib_get_rmon_stats(struct mt7530_lib_priv *priv, int port, + struct ethtool_rmon_stats *rmon_stats, + const struct ethtool_rmon_hist_range **ranges, + const struct mt7530_rmon_hist *ranges_info); +void mt7530_lib_get_eth_ctrl_stats(struct mt7530_lib_priv *priv, int port, + struct ethtool_eth_ctrl_stats *ctrl_stats); +int mt7530_lib_fdb_cmd(struct mt7530_lib_priv *priv, enum mt7530_fdb_cmd c= md, + u32 mat, u32 *rsp); +void mt7530_lib_fdb_read(struct mt7530_lib_priv *priv, struct mt7530_fdb *= fdb); +void mt7530_lib_port_fast_age(struct mt7530_lib_priv *priv, int port); +int mt7530_lib_port_fdb_add(struct mt7530_lib_priv *priv, int port, + const unsigned char *addr, u16 vid, + struct dsa_db db); +int mt7530_lib_port_fdb_del(struct mt7530_lib_priv *priv, int port, + const unsigned char *addr, u16 vid, + struct dsa_db db); +int mt7530_lib_port_mdb_add(struct mt7530_lib_priv *priv, int port, + const struct switchdev_obj_port_mdb *mdb, + struct dsa_db db); +int mt7530_lib_port_mdb_del(struct mt7530_lib_priv *priv, int port, + const struct switchdev_obj_port_mdb *mdb, + struct dsa_db db); +void mt7530_lib_port_mirror_del(struct mt7530_lib_priv *priv, int port, + struct dsa_mall_mirror_tc_entry *mirror); +int mt7530_lib_port_mirror_add(struct mt7530_lib_priv *priv, int port, + struct dsa_mall_mirror_tc_entry *mirror, + bool ingress, struct netlink_ext_ack *extack); +int mt7530_lib_port_change_mtu(struct mt7530_lib_priv *priv, int port, int= new_mtu); +void mt7530_lib_stp_state_set(struct mt7530_lib_priv *priv, int port, u8 s= tate); +int mt7530_lib_port_bridge_flags(struct mt7530_lib_priv *priv, int port, + struct switchdev_brport_flags flags, + struct netlink_ext_ack *extack); +int mt7530_lib_port_bridge_join(struct mt7530_lib_priv *priv, int port, + struct dsa_bridge bridge, bool *tx_fwd_offload, + struct netlink_ext_ack *extack); +void mt7530_lib_port_bridge_leave(struct mt7530_lib_priv *priv, int port, + struct dsa_bridge bridge); +int mt7530_lib_port_vlan_filtering(struct mt7530_lib_priv *priv, int port,= bool vlan_filtering, + struct netlink_ext_ack *extack); +int mt7530_lib_port_vlan_add(struct mt7530_lib_priv *priv, int port, + const struct switchdev_obj_port_vlan *vlan, + struct netlink_ext_ack *extack); +int mt7530_lib_port_vlan_del(struct mt7530_lib_priv *priv, int port, + const struct switchdev_obj_port_vlan *vlan); + +int mt7530_lib_setup_vlan0(struct mt7530_lib_priv *priv); + +#endif /* __MT7530_LIB_H */ + diff --git a/drivers/net/dsa/mediatek/mt7530-mdio.c b/drivers/net/dsa/media= tek/mt7530-mdio.c index 0be107dc6759..e823a9b1422f 100644 --- a/drivers/net/dsa/mediatek/mt7530-mdio.c +++ b/drivers/net/dsa/mediatek/mt7530-mdio.c @@ -218,6 +218,10 @@ mt7530_probe(struct mdio_device *mdiodev) if (IS_ERR(priv->regmap)) return PTR_ERR(priv->regmap); =20 + ret =3D mt7530_setup_lib_priv(priv); + if (ret) + return ret; + if (priv->id =3D=3D ID_MT7531) priv->create_sgmii =3D mt7531_create_sgmii; =20 diff --git a/drivers/net/dsa/mediatek/mt7530-mmio.c b/drivers/net/dsa/media= tek/mt7530-mmio.c index cf3bdb23a2d5..2dcb2bb545b9 100644 --- a/drivers/net/dsa/mediatek/mt7530-mmio.c +++ b/drivers/net/dsa/mediatek/mt7530-mmio.c @@ -61,6 +61,10 @@ mt7988_probe(struct platform_device *pdev) if (IS_ERR(priv->regmap)) return PTR_ERR(priv->regmap); =20 + ret =3D mt7530_setup_lib_priv(priv); + if (ret) + return ret; + return dsa_register_switch(priv->ds); } =20 diff --git a/drivers/net/dsa/mediatek/mt7530.c b/drivers/net/dsa/mediatek/m= t7530.c index 50e80585d558..d0f2691a44a0 100644 --- a/drivers/net/dsa/mediatek/mt7530.c +++ b/drivers/net/dsa/mediatek/mt7530.c @@ -24,10 +24,163 @@ #include =20 #include "mt7530.h" +#include "mt7530-lib.h" =20 #define MT7530_STATS_POLL_INTERVAL (1 * HZ) #define MT7530_STATS_RATE_LIMIT (HZ / 10) =20 +static const struct mt7530_reg_field mt753x_fields[] =3D { + { MT7530_BC_FFP, REG_FIELD(MT753X_MFC, 24, 31) }, + { MT7530_UNM_FFP, REG_FIELD(MT753X_MFC, 16, 23) }, + { MT7530_UNU_FFP, REG_FIELD(MT753X_MFC, 8, 15) }, + + { MT7530_CCR_MIB_ENABLE, REG_FIELD(MT7530_MIB_CCR, 31, 31) }, + { MT7530_CCR_RX_OCT_CNT_GOOD, REG_FIELD(MT7530_MIB_CCR, 7, 7) }, + { MT7530_CCR_RX_OCT_CNT_BAD, REG_FIELD(MT7530_MIB_CCR, 6, 6) }, + { MT7530_CCR_TX_OCT_CNT_GOOD, REG_FIELD(MT7530_MIB_CCR, 5, 5) }, + { MT7530_CCR_TX_OCT_CNT_BAD, REG_FIELD(MT7530_MIB_CCR, 4, 4) }, + + { MT7530_BPDU_EG_TAG, REG_FIELD(MT753X_BPC, 6, 8) }, + { MT7530_BPDU_PORT_FW, REG_FIELD(MT753X_BPC, 0, 2) }, + { MT7530_PAE_BPDU_FR, REG_FIELD(MT753X_BPC, 25, 25) }, + { MT7530_PAE_EG_TAG, REG_FIELD(MT753X_BPC, 22, 24) }, + { MT7530_PAE_PORT_FW, REG_FIELD(MT753X_BPC, 16, 18) }, + { MT7530_R01_BPDU_FR, REG_FIELD(MT753X_RGAC1, 9, 9) }, + { MT7530_R01_EG_TAG, REG_FIELD(MT753X_RGAC1, 6, 8) }, + { MT7530_R01_PORT_FW, REG_FIELD(MT753X_RGAC1, 0, 2) }, + { MT7530_R02_BPDU_FR, REG_FIELD(MT753X_RGAC1, 25, 25) }, + { MT7530_R02_EG_TAG, REG_FIELD(MT753X_RGAC1, 22, 24) }, + { MT7530_R02_PORT_FW, REG_FIELD(MT753X_RGAC1, 16, 18) }, + { MT7530_R03_BPDU_FR, REG_FIELD(MT753X_RGAC2, 9, 9) }, + { MT7530_R03_EG_TAG, REG_FIELD(MT753X_RGAC2, 6, 8) }, + { MT7530_R03_PORT_FW, REG_FIELD(MT753X_RGAC2, 0, 2) }, + { MT7530_R0E_BPDU_FR, REG_FIELD(MT753X_RGAC2, 25, 25) }, + { MT7530_R0E_EG_TAG, REG_FIELD(MT753X_RGAC2, 22, 24) }, + { MT7530_R0E_PORT_FW, REG_FIELD(MT753X_RGAC2, 16, 18) }, + + { MT7530_VAWD_IVL_MAC, REG_FIELD(MT7530_VAWD1, 30, 30) }, + { MT7530_VAWD_EG_CON, REG_FIELD(MT7530_VAWD1, 29, 29) }, + { MT7530_VAWD_VTAG_EN, REG_FIELD(MT7530_VAWD1, 28, 28) }, + { MT7530_VAWD_PORT_MEM, REG_FIELD(MT7530_VAWD1, 16, 23) }, + { MT7530_VAWD_FID, REG_FIELD(MT7530_VAWD1, 1, 3) }, + { MT7530_VAWD_VLAN_VALID, REG_FIELD(MT7530_VAWD1, 0, 0) }, + { __MT7530_VAWD1, REG_FIELD(MT7530_VAWD1, 0, 31) }, + + { MT7530_VAWD_ETAG, REG_FIELD(MT7530_VAWD2, 0, 15) }, + { __MT7530_VAWD2, REG_FIELD(MT7530_VAWD2, 0, 31) }, + + { MT7530_VTCR_BUSY, REG_FIELD(MT7530_VTCR, 31, 31) }, + { MT7530_VTCR_INVALID, REG_FIELD(MT7530_VTCR, 16, 16) }, + { MT7530_VTCR_FUNC, REG_FIELD(MT7530_VTCR, 12, 15) }, + { MT7530_VTCR_VID, REG_FIELD(MT7530_VTCR, 0, 11) }, + + { MT7530_ATWD_CVID, REG_FIELD(MT7530_ATA2, 0, 11), }, + { MT7530_ATWD_IVL, REG_FIELD(MT7530_ATA2, 15, 15), }, + { MT7530_ATWD_FID, REG_FIELD(MT7530_ATA2, 12, 14), }, + { MT7530_ATWD_AGE_TIMER, REG_FIELD(MT7530_ATWD, 24, 31), }, + { MT7530_ATWD_PORT_MAP, REG_FIELD(MT7530_ATWD, 4, 11), }, + { MT7530_ATWD_ENT_STATUS, REG_FIELD(MT7530_ATWD, 2, 3), }, + { MT7530_ATWD_MAC_BYTE_5, REG_FIELD(MT7530_ATA2, 16, 23), }, + { MT7530_ATWD_MAC_BYTE_4, REG_FIELD(MT7530_ATA2, 24, 31), }, + { MT7530_ATWD_MAC_BYTE_3, REG_FIELD(MT7530_ATA1, 0, 7), }, + { MT7530_ATWD_MAC_BYTE_2, REG_FIELD(MT7530_ATA1, 8, 15), }, + { MT7530_ATWD_MAC_BYTE_1, REG_FIELD(MT7530_ATA1, 16, 23), }, + { MT7530_ATWD_MAC_BYTE_0, REG_FIELD(MT7530_ATA1, 24, 31), }, + + { __MT7530_ATWD1, REG_FIELD(MT7530_ATWD, 0, 31), }, + { __MT7530_ATWD2, REG_FIELD(MT7530_ATA1, 0, 31), }, + { __MT7530_ATWD3, REG_FIELD(MT7530_ATA2, 0, 31), }, + + { MT7530_ATRD_CVID, REG_FIELD(MT7530_TSRA2, 0, 11), }, + { MT7530_ATRD_AGE_TIMER, REG_FIELD(MT7530_ATRD, 24, 31), }, + { MT7530_ATRD_PORT_MAP, REG_FIELD(MT7530_ATRD, 4, 11), }, + { MT7530_ATRD_ENT_STATUS, REG_FIELD(MT7530_ATRD, 2, 3), }, + { MT7530_ATRD_MAC_BYTE_5, REG_FIELD(MT7530_TSRA2, 16, 23), }, + { MT7530_ATRD_MAC_BYTE_4, REG_FIELD(MT7530_TSRA2, 24, 31), }, + { MT7530_ATRD_MAC_BYTE_3, REG_FIELD(MT7530_TSRA1, 0, 7), }, + { MT7530_ATRD_MAC_BYTE_2, REG_FIELD(MT7530_TSRA1, 8, 15), }, + { MT7530_ATRD_MAC_BYTE_1, REG_FIELD(MT7530_TSRA1, 16, 23), }, + { MT7530_ATRD_MAC_BYTE_0, REG_FIELD(MT7530_TSRA1, 24, 31), }, + + { MT7530_ATC_BUSY, REG_FIELD(MT7530_ATC, 15, 15), }, + { MT7530_ATC_INVALID, REG_FIELD(MT7530_ATC, 12, 12), }, + { MT7530_ATC_MAT, REG_FIELD(MT7530_ATC, 8, 11), }, + { MT7530_ATC_CMD, REG_FIELD(MT7530_ATC, 0, 2), }, + { __MT7530_ATC, REG_FIELD(MT7530_ATC, 0, 31), }, + + { MT7530_SSP_FID_PST, REG_FIELD_ID(MT7530_SSP, 0, 15, MT7530_NUM_PORTS, 0= x100) }, + + { MT7530_PCR_PORT_TX_MIR, REG_FIELD_ID(MT7530_PCR, 9, 9, MT7530_NUM_PORTS= , 0x100) }, + { MT7530_PCR_PORT_RX_MIR, REG_FIELD_ID(MT7530_PCR, 8, 8, MT7530_NUM_PORTS= , 0x100) }, + { MT7530_PCR_PORT_VLAN, REG_FIELD_ID(MT7530_PCR, 0, 1, MT7530_NUM_PORTS, = 0x100) }, + { MT7530_PCR_MATRIX, REG_FIELD_ID(MT7530_PCR, 16, 23, MT7530_NUM_PORTS, 0= x100) }, + + { MT7530_PSC_SA_DIS, REG_FIELD_ID(MT7530_PSC, 4, 4, MT7530_NUM_PORTS, 0x1= 00) }, + + { MT7530_PVC_EG_TAG, REG_FIELD_ID(MT7530_PVC, 8, 10, MT7530_NUM_PORTS, 0x= 100) }, + { MT7530_PVC_VLAN_ATTR, REG_FIELD_ID(MT7530_PVC, 6, 7, MT7530_NUM_PORTS, = 0x100) }, + { MT7530_PVC_ACC_FRM, REG_FIELD_ID(MT7530_PVC, 0, 1, MT7530_NUM_PORTS, 0x= 100) }, + + { MT7530_PPBV1_G0_PORT_VID, REG_FIELD_ID(MT7530_PPBV1, 0, 11, MT7530_NUM_= PORTS, 0x100) }, + + { MT7530_GMACCR_MAX_RX_JUMBO, REG_FIELD(MT7530_GMACCR, 2, 5) }, + { MT7530_GMACCR_MAX_RX_PKT_LEN, REG_FIELD(MT7530_GMACCR, 0, 1) }, + + { MT7530_MIB_TX_DROP, REG_FIELD_ID(MT7530_PORT_MIB_TX_DROP, 0, 31, MT7530= _NUM_PORTS, 0x100) }, + { MT7530_MIB_TX_CRC_ERR, REG_FIELD_ID(MT7530_PORT_MIB_TX_CRC_ERR, 0, 31, = MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_TX_UNICAST, REG_FIELD_ID(MT7530_PORT_MIB_TX_UNICAST, 0, 31, = MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_TX_MULTICAST, REG_FIELD_ID(MT7530_PORT_MIB_TX_MULTICAST, 0, = 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_TX_BROADCAST, REG_FIELD_ID(MT7530_PORT_MIB_TX_BROADCAST, 0, = 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_TX_COLLISION, REG_FIELD_ID(MT7530_PORT_MIB_TX_COLLISION, 0, = 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_TX_SINGLE_COLLISION, REG_FIELD_ID(MT7530_PORT_MIB_TX_SINGLE_= COLLISION, 0, 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_TX_MULTIPLE_COLLISION, REG_FIELD_ID(MT7530_PORT_MIB_TX_MULTI= PLE_COLLISION, 0, 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_TX_DEFERRED, REG_FIELD_ID(MT7530_PORT_MIB_TX_DEFERRED, 0, 31= , MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_TX_LATE_COLLISION, REG_FIELD_ID(MT7530_PORT_MIB_TX_LATE_COLL= ISION, 0, 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_TX_EXCESSIVE_COLLISION, REG_FIELD_ID(MT7530_PORT_MIB_TX_EXCE= SSIVE_COLLISION, 0, 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_TX_PAUSE, REG_FIELD_ID(MT7530_PORT_MIB_TX_PAUSE, 0, 31, MT75= 30_NUM_PORTS, 0x100) }, + { MT7530_MIB_TX_PKT_SZ_64, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ_64, 0, = 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_TX_PKT_SZ_65_TO_127, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ_= 65_TO_127, 0, 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_TX_PKT_SZ_128_TO_255, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ= _128_TO_255, 0, 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_TX_PKT_SZ_256_TO_511, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ= _256_TO_511, 0, 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_TX_PKT_SZ_512_TO_1023, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_S= Z_512_TO_1023, 0, 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_TX_PKT_SZ_1024_TO_MAX, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_S= Z_1024_TO_MAX, 0, 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_TX_BYTES_LOW, REG_FIELD_ID(MT7530_PORT_MIB_TX_BYTES_LOW, 0, = 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_TX_BYTES_HIGH, REG_FIELD_ID(MT7530_PORT_MIB_TX_BYTES_HIGH, 0= , 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_DROP, REG_FIELD_ID(MT7530_PORT_MIB_RX_DROP, 0, 31, MT7530= _NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_FILTERING, REG_FIELD_ID(MT7530_PORT_MIB_RX_FILTERING, 0, = 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_UNICAST, REG_FIELD_ID(MT7530_PORT_MIB_RX_UNICAST, 0, 31, = MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_MULTICAST, REG_FIELD_ID(MT7530_PORT_MIB_RX_MULTICAST, 0, = 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_BROADCAST, REG_FIELD_ID(MT7530_PORT_MIB_RX_BROADCAST, 0, = 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_ALIGN_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_ALIGN_ERR, 0, = 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_CRC_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_CRC_ERR, 0, 31, = MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_UNDER_SIZE_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_UNDER_SIZ= E_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_FRAG_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_FRAG_ERR, 0, 31= , MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_OVER_SZ_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_OVER_SZ_ERR,= 0, 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_JABBER_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_JABBER_ERR, 0= , 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_PAUSE, REG_FIELD_ID(MT7530_PORT_MIB_RX_PAUSE, 0, 31, MT75= 30_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_PKT_SZ_64, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ_64, 0, = 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_PKT_SZ_65_TO_127, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ_= 65_TO_127, 0, 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_PKT_SZ_128_TO_255, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ= _128_TO_255, 0, 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_PKT_SZ_256_TO_511, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ= _256_TO_511, 0, 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_PKT_SZ_512_TO_1023, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_S= Z_512_TO_1023, 0, 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_PKT_SZ_1024_TO_MAX, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_S= Z_1024_TO_MAX, 0, 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_BYTES_LOW, REG_FIELD_ID(MT7530_PORT_MIB_RX_BYTES_LOW, 0, = 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_BYTES_HIGH, REG_FIELD_ID(MT7530_PORT_MIB_RX_BYTES_HIGH, 0= , 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_CTRL_DROP, REG_FIELD_ID(MT7530_PORT_MIB_RX_CTRL_DROP, 0, = 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_INGRESS_DROP, REG_FIELD_ID(MT7530_PORT_MIB_RX_INGRESS_DRO= P, 0, 31, MT7530_NUM_PORTS, 0x100) }, + { MT7530_MIB_RX_ARL_DROP, REG_FIELD_ID(MT7530_PORT_MIB_RX_ARL_DROP, 0, 31= , MT7530_NUM_PORTS, 0x100) }, +}; + +static const struct mt7530_reg_field mt7530_fields[] =3D { + { MT7530_MIRROR_EN, REG_FIELD(MT753X_MFC, 3, 3) }, + { MT7530_MIRROR_PORT, REG_FIELD(MT753X_MFC, 0, 2) }, +}; + +static const struct mt7530_reg_field mt7531_fields[] =3D { + { MT7530_MIRROR_EN, REG_FIELD(MT7531_CFC, 19, 19) }, + { MT7530_MIRROR_PORT, REG_FIELD(MT7531_CFC, 16, 18) }, +}; + static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) { return container_of(pcs, struct mt753x_pcs, pcs); @@ -35,15 +188,15 @@ static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phy= link_pcs *pcs) =20 /* String, offset, and register size in bytes if different from 4 bytes */ static const struct mt7530_mib_desc mt7530_mib[] =3D { - MIB_DESC(1, MT7530_PORT_MIB_TX_DROP, "TxDrop"), - MIB_DESC(1, MT7530_PORT_MIB_TX_CRC_ERR, "TxCrcErr"), - MIB_DESC(1, MT7530_PORT_MIB_TX_COLLISION, "TxCollision"), - MIB_DESC(1, MT7530_PORT_MIB_RX_DROP, "RxDrop"), - MIB_DESC(1, MT7530_PORT_MIB_RX_FILTERING, "RxFiltering"), - MIB_DESC(1, MT7530_PORT_MIB_RX_CRC_ERR, "RxCrcErr"), - MIB_DESC(1, MT7530_PORT_MIB_RX_CTRL_DROP, "RxCtrlDrop"), - MIB_DESC(1, MT7530_PORT_MIB_RX_INGRESS_DROP, "RxIngressDrop"), - MIB_DESC(1, MT7530_PORT_MIB_RX_ARL_DROP, "RxArlDrop"), + MIB_DESC(MT7530_MIB_TX_DROP, -1, "TxDrop"), + MIB_DESC(MT7530_MIB_TX_CRC_ERR, -1, "TxCrcErr"), + MIB_DESC(MT7530_MIB_TX_COLLISION, -1, "TxCollision"), + MIB_DESC(MT7530_MIB_RX_DROP, -1, "RxDrop"), + MIB_DESC(MT7530_MIB_RX_FILTERING, -1, "RxFiltering"), + MIB_DESC(MT7530_MIB_RX_CRC_ERR, -1, "RxCrcErr"), + MIB_DESC(MT7530_MIB_RX_CTRL_DROP, -1, "RxCtrlDrop"), + MIB_DESC(MT7530_MIB_RX_INGRESS_DROP, -1, "RxIngressDrop"), + MIB_DESC(MT7530_MIB_RX_ARL_DROP, -1, "RxArlDrop"), }; =20 static void @@ -154,115 +307,11 @@ core_clear(struct mt7530_priv *priv, u32 reg, u32 va= l) core_rmw(priv, reg, val, 0); } =20 -static int -mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) -{ - u32 val; - int ret; - - /* Set the command operating upon the MAC address entries */ - val =3D ATC_BUSY | ATC_MAT(0) | cmd; - ret =3D regmap_write(priv->regmap, MT7530_ATC, val); - if (ret) - return ret; - - ret =3D regmap_read_poll_timeout(priv->regmap, MT7530_ATC, val, - !(val & ATC_BUSY), 20, 20000); - if (!ret) - ret =3D regmap_read(priv->regmap, MT7530_ATC, &val); - - if (ret < 0) { - dev_err(priv->dev, "reset timeout\n"); - return ret; - } - - /* Additional sanity for read command if the specified - * entry is invalid - */ - if ((cmd =3D=3D MT7530_FDB_READ) && (val & ATC_INVALID)) - return -EINVAL; - - if (rsp) - *rsp =3D val; - - return 0; -} - static void mt7530_port_fast_age(struct dsa_switch *ds, int port) { struct mt7530_priv *priv =3D ds->priv; - u32 val; - int ret; - - mutex_lock(&priv->reg_mutex); - - /* Flush all non-static MAC address entries */ - val =3D ATC_BUSY | ATC_MAT_NON_STATIC_MAC | MT7530_FDB_FLUSH; - ret =3D regmap_write(priv->regmap, MT7530_ATC, val); - if (!ret) - ret =3D regmap_read_poll_timeout(priv->regmap, MT7530_ATC, val, - !(val & ATC_BUSY), 20, 20000); - if (ret < 0) - dev_err(priv->dev, "fast age failed: %d\n", ret); - - mutex_unlock(&priv->reg_mutex); -} - -static void -mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) -{ - u32 reg[3]; - int i; - - /* Read from ARL table into an array */ - for (i =3D 0; i < 3; i++) { - regmap_read(priv->regmap, MT7530_TSRA1 + (i * 4), - ®[i]); - - dev_dbg(priv->dev, "%s(%d) reg[%d]=3D0x%x\n", - __func__, __LINE__, i, reg[i]); - } =20 - fdb->vid =3D FIELD_GET(CVID_MASK, reg[1]); - fdb->aging =3D FIELD_GET(AGE_TIMER_MASK, reg[2]); - fdb->port_mask =3D FIELD_GET(PORT_MAP_MASK, reg[2]); - fdb->mac[0] =3D FIELD_GET(MAC_BYTE_0_MASK, reg[0]); - fdb->mac[1] =3D FIELD_GET(MAC_BYTE_1_MASK, reg[0]); - fdb->mac[2] =3D FIELD_GET(MAC_BYTE_2_MASK, reg[0]); - fdb->mac[3] =3D FIELD_GET(MAC_BYTE_3_MASK, reg[0]); - fdb->mac[4] =3D FIELD_GET(MAC_BYTE_4_MASK, reg[1]); - fdb->mac[5] =3D FIELD_GET(MAC_BYTE_5_MASK, reg[1]); - fdb->noarp =3D FIELD_GET(ENT_STATUS_MASK, reg[2]) =3D=3D STATIC_ENT; -} - -static void -mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, - u8 port_mask, const u8 *mac, - u8 aging, u8 type) -{ - u32 reg[3] =3D { 0 }; - int i; - - reg[1] |=3D FIELD_PREP(CVID_MASK, vid); - reg[1] |=3D ATA2_IVL; - reg[1] |=3D ATA2_FID(FID_BRIDGED); - reg[2] |=3D FIELD_PREP(AGE_TIMER_MASK, aging); - reg[2] |=3D FIELD_PREP(PORT_MAP_MASK, port_mask); - /* STATIC_ENT indicate that entry is static wouldn't - * be aged out and STATIC_EMP specified as erasing an - * entry - */ - reg[2] |=3D FIELD_PREP(ENT_STATUS_MASK, type); - reg[1] |=3D FIELD_PREP(MAC_BYTE_5_MASK, mac[5]); - reg[1] |=3D FIELD_PREP(MAC_BYTE_4_MASK, mac[4]); - reg[0] |=3D FIELD_PREP(MAC_BYTE_3_MASK, mac[3]); - reg[0] |=3D FIELD_PREP(MAC_BYTE_2_MASK, mac[2]); - reg[0] |=3D FIELD_PREP(MAC_BYTE_1_MASK, mac[1]); - reg[0] |=3D FIELD_PREP(MAC_BYTE_0_MASK, mac[0]); - - /* Write array into the ARL table */ - for (i =3D 0; i < 3; i++) - regmap_write(priv->regmap, MT7530_ATA1 + (i * 4), reg[i]); + mt7530_lib_port_fast_age(&priv->lib_priv, port); } =20 /* Set up switch core clock for MT7530 */ @@ -449,15 +498,6 @@ mt7531_pll_setup(struct mt7530_priv *priv) usleep_range(25, 35); } =20 -static void -mt7530_mib_reset(struct dsa_switch *ds) -{ - struct mt7530_priv *priv =3D ds->priv; - - regmap_write(priv->regmap, MT7530_MIB_CCR, CCR_MIB_FLUSH); - regmap_write(priv->regmap, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); -} - static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int reg= num) { return mdiobus_read_nested(priv->bus, port, regnum); @@ -702,34 +742,25 @@ mt7530_get_strings(struct dsa_switch *ds, int port, u= 32 stringset, ethtool_puts(&data, mt7530_mib[i].name); } =20 -static void -mt7530_read_port_stats(struct mt7530_priv *priv, int port, - u32 offset, u8 size, uint64_t *data) -{ - u32 val, reg =3D MT7530_PORT_MIB_COUNTER(port) + offset; - - regmap_read(priv->regmap, reg, &val); - *data =3D val; - - if (size =3D=3D 2) { - regmap_read(priv->regmap, reg + 4, &val); - *data |=3D (u64)val << 32; - } -} - static void mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) { struct mt7530_priv *priv =3D ds->priv; const struct mt7530_mib_desc *mib; + struct mt7530_lib_priv *lib_priv; int i; =20 + lib_priv =3D &priv->lib_priv; for (i =3D 0; i < ARRAY_SIZE(mt7530_mib); i++) { + struct regmap_field *high =3D NULL; mib =3D &mt7530_mib[i]; =20 - mt7530_read_port_stats(priv, port, mib->offset, mib->size, - data + i); + if (mib->field_high !=3D -1) + high =3D lib_priv->fields[mib->field_high]; + + mt7530_lib_read_port_stats(lib_priv->fields[mib->field_low], + high, port, data + i); } } =20 @@ -747,54 +778,7 @@ static void mt7530_get_eth_mac_stats(struct dsa_switch= *ds, int port, { struct mt7530_priv *priv =3D ds->priv; =20 - /* MIB counter doesn't provide a FramesTransmittedOK but instead - * provide stats for Unicast, Broadcast and Multicast frames separately. - * To simulate a global frame counter, read Unicast and addition Multicast - * and Broadcast later - */ - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1, - &mac_stats->FramesTransmittedOK); - - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_SINGLE_COLLISION, 1, - &mac_stats->SingleCollisionFrames); - - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTIPLE_COLLISION,= 1, - &mac_stats->MultipleCollisionFrames); - - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1, - &mac_stats->FramesReceivedOK); - - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2, - &mac_stats->OctetsTransmittedOK); - - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_ALIGN_ERR, 1, - &mac_stats->AlignmentErrors); - - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DEFERRED, 1, - &mac_stats->FramesWithDeferredXmissions); - - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_LATE_COLLISION, 1, - &mac_stats->LateCollisions); - - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION= , 1, - &mac_stats->FramesAbortedDueToXSColls); - - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2, - &mac_stats->OctetsReceivedOK); - - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1, - &mac_stats->MulticastFramesXmittedOK); - mac_stats->FramesTransmittedOK +=3D mac_stats->MulticastFramesXmittedOK; - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1, - &mac_stats->BroadcastFramesXmittedOK); - mac_stats->FramesTransmittedOK +=3D mac_stats->BroadcastFramesXmittedOK; - - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1, - &mac_stats->MulticastFramesReceivedOK); - mac_stats->FramesReceivedOK +=3D mac_stats->MulticastFramesReceivedOK; - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1, - &mac_stats->BroadcastFramesReceivedOK); - mac_stats->FramesReceivedOK +=3D mac_stats->BroadcastFramesReceivedOK; + return mt7530_lib_get_eth_mac_stats(&priv->lib_priv, port, mac_stats); } =20 static const struct ethtool_rmon_hist_range mt7530_rmon_ranges[] =3D { @@ -807,53 +791,41 @@ static const struct ethtool_rmon_hist_range mt7530_rm= on_ranges[] =3D { {} }; =20 +static const struct mt7530_rmon_hist mt7530_rmon_hist_info =3D { + .ranges_fields =3D (unsigned int []){ + MT7530_MIB_RX_PKT_SZ_64, + MT7530_MIB_RX_PKT_SZ_65_TO_127, + MT7530_MIB_RX_PKT_SZ_128_TO_255, + MT7530_MIB_RX_PKT_SZ_256_TO_511, + MT7530_MIB_RX_PKT_SZ_512_TO_1023, + MT7530_MIB_RX_PKT_SZ_1024_TO_MAX, + }, + .ranges_tx_fields =3D (unsigned int []){ + MT7530_MIB_TX_PKT_SZ_64, + MT7530_MIB_TX_PKT_SZ_65_TO_127, + MT7530_MIB_TX_PKT_SZ_128_TO_255, + MT7530_MIB_TX_PKT_SZ_256_TO_511, + MT7530_MIB_TX_PKT_SZ_512_TO_1023, + MT7530_MIB_TX_PKT_SZ_1024_TO_MAX, + }, + .ranges =3D mt7530_rmon_ranges, + .num_ranges =3D ARRAY_SIZE(mt7530_rmon_ranges) - 1, +}; + static void mt7530_get_rmon_stats(struct dsa_switch *ds, int port, struct ethtool_rmon_stats *rmon_stats, const struct ethtool_rmon_hist_range **ranges) { struct mt7530_priv *priv =3D ds->priv; =20 - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNDER_SIZE_ERR, 1, - &rmon_stats->undersize_pkts); - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_OVER_SZ_ERR, 1, - &rmon_stats->oversize_pkts); - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_FRAG_ERR, 1, - &rmon_stats->fragments); - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_JABBER_ERR, 1, - &rmon_stats->jabbers); - - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_64, 1, - &rmon_stats->hist[0]); - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127, 1, - &rmon_stats->hist[1]); - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255, = 1, - &rmon_stats->hist[2]); - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511, = 1, - &rmon_stats->hist[3]); - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023,= 1, - &rmon_stats->hist[4]); - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX,= 1, - &rmon_stats->hist[5]); - - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_64, 1, - &rmon_stats->hist_tx[0]); - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127, 1, - &rmon_stats->hist_tx[1]); - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255, = 1, - &rmon_stats->hist_tx[2]); - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511, = 1, - &rmon_stats->hist_tx[3]); - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023,= 1, - &rmon_stats->hist_tx[4]); - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX,= 1, - &rmon_stats->hist_tx[5]); - - *ranges =3D mt7530_rmon_ranges; + return mt7530_lib_get_rmon_stats(&priv->lib_priv, port, rmon_stats, range= s, + &mt7530_rmon_hist_info); } =20 static void mt7530_read_port_stats64(struct mt7530_priv *priv, int port, struct rtnl_link_stats64 *storage) { + struct mt7530_lib_priv *lib_priv =3D &priv->lib_priv; uint64_t data; =20 /* MIB counter doesn't provide a FramesTransmittedOK but instead @@ -861,38 +833,40 @@ static void mt7530_read_port_stats64(struct mt7530_pr= iv *priv, int port, * To simulate a global frame counter, read Unicast and addition Multicast * and Broadcast later */ - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1, - &storage->rx_packets); - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1, - &storage->multicast); + mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_RX_UNICAST], + NULL, port, &storage->rx_packets); + mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_RX_MULTICAST], + NULL, port, &storage->multicast); storage->rx_packets +=3D storage->multicast; - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1, - &data); + mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_RX_BROADCAST], + NULL, port, &data); storage->rx_packets +=3D data; =20 - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1, - &storage->tx_packets); - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1, - &data); + mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_TX_UNICAST], + NULL, port, &storage->tx_packets); + mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_TX_MULTICAST], + NULL, port, &data); storage->tx_packets +=3D data; - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1, - &data); + mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_TX_BROADCAST], + NULL, port, &data); storage->tx_packets +=3D data; =20 - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2, - &storage->rx_bytes); + mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_RX_BYTES_LOW], + lib_priv->fields[MT7530_MIB_RX_BYTES_HIGH], port, + &storage->rx_bytes); =20 - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2, - &storage->tx_bytes); + mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_TX_BYTES_LOW], + lib_priv->fields[MT7530_MIB_TX_BYTES_HIGH], port, + &storage->tx_bytes); =20 - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_DROP, 1, - &storage->rx_dropped); + mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_RX_DROP], + NULL, port, &storage->rx_dropped); =20 - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DROP, 1, - &storage->tx_dropped); + mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_TX_DROP], + NULL, port, &storage->tx_dropped); =20 - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_CRC_ERR, 1, - &storage->rx_crc_errors); + mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_RX_CRC_ERR], + NULL, port, &storage->rx_crc_errors); } =20 static void mt7530_stats_refresh(struct mt7530_priv *priv) @@ -948,11 +922,7 @@ static void mt7530_get_eth_ctrl_stats(struct dsa_switc= h *ds, int port, { struct mt7530_priv *priv =3D ds->priv; =20 - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PAUSE, 1, - &ctrl_stats->MACControlFramesTransmitted); - - mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PAUSE, 1, - &ctrl_stats->MACControlFramesReceived); + mt7530_lib_get_eth_ctrl_stats(&priv->lib_priv, port, ctrl_stats); } =20 static int @@ -1073,214 +1043,6 @@ static void mt7530_setup_port5(struct dsa_switch *d= s, phy_interface_t interface) mutex_unlock(&priv->reg_mutex); } =20 -/* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer = (DLL) - * of the Open Systems Interconnection basic reference model (OSI/RM) are - * described; the medium access control (MAC) and logical link control (LL= C) - * sublayers. The MAC sublayer is the one facing the physical layer. - * - * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A - * Bridge component comprises a MAC Relay Entity for interconnecting the P= orts - * of the Bridge, at least two Ports, and higher layer entities with at le= ast a - * Spanning Tree Protocol Entity included. - * - * Each Bridge Port also functions as an end station and shall provide the= MAC - * Service to an LLC Entity. Each instance of the MAC Service is provided = to a - * distinct LLC Entity that supports protocol identification, multiplexing= , and - * demultiplexing, for protocol data unit (PDU) transmission and reception= by - * one or more higher layer entities. - * - * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the= LLC - * Entity associated with each Bridge Port is modeled as being directly - * connected to the attached Local Area Network (LAN). - * - * On the switch with CPU port architecture, CPU port functions as Managem= ent - * Port, and the Management Port functionality is provided by software whi= ch - * functions as an end station. Software is connected to an IEEE 802 LAN t= hat is - * wholly contained within the system that incorporates the Bridge. Softwa= re - * provides access to the LLC Entity associated with each Bridge Port by t= he - * value of the source port field on the special tag on the frame received= by - * software. - * - * We call frames that carry control information to determine the active - * topology and current extent of each Virtual Local Area Network (VLAN), = i.e., - * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registr= ation - * Protocol Data Units (MVRPDUs), and frames from other link constrained - * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) = and - * Link Layer Discovery Protocol (LLDP), link-local frames. They are not - * forwarded by a Bridge. Permanently configured entries in the filtering - * database (FDB) ensure that such frames are discarded by the Forwarding - * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail: - * - * Each of the reserved MAC addresses specified in Table 8-1 - * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shal= l be - * permanently configured in the FDB in C-VLAN components and ERs. - * - * Each of the reserved MAC addresses specified in Table 8-2 - * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently - * configured in the FDB in S-VLAN components. - * - * Each of the reserved MAC addresses specified in Table 8-3 - * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the F= DB in - * TPMR components. - * - * The FDB entries for reserved MAC addresses shall specify filtering for = all - * Bridge Ports and all VIDs. Management shall not provide the capability = to - * modify or remove entries for reserved MAC addresses. - * - * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scop= e of - * propagation of PDUs within a Bridged Network, as follows: - * - * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address th= at no - * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN) - * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forwar= d. - * PDUs transmitted using this destination address, or any other address= es - * that appear in Table 8-1, Table 8-2, and Table 8-3 - * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), c= an - * therefore travel no further than those stations that can be reached v= ia a - * single individual LAN from the originating station. - * - * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an - * address that no conformant S-VLAN component, C-VLAN component, or MAC - * Bridge can forward; however, this address is relayed by a TPMR compon= ent. - * PDUs using this destination address, or any of the other addresses th= at - * appear in both Table 8-1 and Table 8-2 but not in Table 8-3 - * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relay= ed by - * any TPMRs but will propagate no further than the nearest S-VLAN compo= nent, - * C-VLAN component, or MAC Bridge. - * - * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an a= ddress - * that no conformant C-VLAN component, MAC Bridge can forward; however,= it is - * relayed by TPMR components and S-VLAN components. PDUs using this - * destination address, or any of the other addresses that appear in Tab= le 8-1 - * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D= ,0F]), - * will be relayed by TPMR components and S-VLAN components but will pro= pagate - * no further than the nearest C-VLAN component or MAC Bridge. - * - * Because the LLC Entity associated with each Bridge Port is provided via= CPU - * port, we must not filter these frames but forward them to CPU port. - * - * In a Bridge, the transmission Port is majorly decided by ingress and eg= ress - * rules, FDB, and spanning tree Port State functions of the Forwarding Pr= ocess. - * For link-local frames, only CPU port should be designated as destinatio= n port - * in the FDB, and the other functions of the Forwarding Process must not - * interfere with the decision of the transmission Port. We call this proc= ess - * trapping frames to CPU port. - * - * Therefore, on the switch with CPU port architecture, link-local frames = must - * be trapped to CPU port, and certain link-local frames received by a Por= t of a - * Bridge comprising a TPMR component or an S-VLAN component must be exclu= ded - * from it. - * - * A Bridge of the switch with CPU port architecture cannot comprise a Two= -Port - * MAC Relay (TPMR) component as a TPMR component supports only a subset o= f the - * functionality of a MAC Bridge. A Bridge comprising two Ports (Managemen= t Port - * doesn't count) of this architecture will either function as a standard = MAC - * Bridge or a standard VLAN Bridge. - * - * Therefore, a Bridge of this architecture can only comprise S-VLAN compo= nents, - * C-VLAN components, or MAC Bridge components. Since there's no TPMR comp= onent, - * we don't need to relay PDUs using the destination addresses specified o= n the - * Nearest non-TPMR section, and the proportion of the Nearest Customer Br= idge - * section where they must be relayed by TPMR components. - * - * One option to trap link-local frames to CPU port is to add static FDB e= ntries - * with CPU port designated as destination port. However, because that - * Independent VLAN Learning (IVL) is being used on every VID, each entry = only - * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC - * Bridge component or a C-VLAN component, there would have to be 16 times= 4096 - * entries. This switch intellectual property can only hold a maximum of 2= 048 - * entries. Using this option, there also isn't a mechanism to prevent - * link-local frames from being discarded when the spanning tree Port Stat= e of - * the reception Port is discarding. - * - * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RG= AC4 - * registers. Whilst this applies to every VID, it doesn't contain all of = the - * reserved MAC addresses without affecting the remaining Standard Group M= AC - * Addresses. The REV_UN frame tag utilised using the RGAC4 register cover= s the - * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination - * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF - * destination addresses which may be relayed by MAC Bridges or VLAN Bridg= es. - * The latter option provides better but not complete conformance. - * - * This switch intellectual property also does not provide a mechanism to = trap - * link-local frames with specific destination addresses to CPU port by Br= idge, - * to conform to the filtering rules for the distinct Bridge components. - * - * Therefore, regardless of the type of the Bridge component, link-local f= rames - * with these destination addresses will be trapped to CPU port: - * - * 01-80-C2-00-00-[00,01,02,03,0E] - * - * In a Bridge comprising a MAC Bridge component or a C-VLAN component: - * - * Link-local frames with these destination addresses won't be trapped t= o CPU - * port which won't conform to IEEE Std 802.1Q-2022: - * - * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] - * - * In a Bridge comprising an S-VLAN component: - * - * Link-local frames with these destination addresses will be trapped to= CPU - * port which won't conform to IEEE Std 802.1Q-2022: - * - * 01-80-C2-00-00-00 - * - * Link-local frames with these destination addresses won't be trapped t= o CPU - * port which won't conform to IEEE Std 802.1Q-2022: - * - * 01-80-C2-00-00-[04,05,06,07,08,09,0A] - * - * To trap link-local frames to CPU port as conformant as this switch - * intellectual property can allow, link-local frames are made to be regar= ded as - * Bridge Protocol Data Units (BPDUs). This is because this switch intelle= ctual - * property only lets the frames regarded as BPDUs bypass the spanning tre= e Port - * State function of the Forwarding Process. - * - * The only remaining interference is the ingress rules. When the receptio= n Port - * has no PVID assigned on software, VLAN-untagged frames won't be allowed= in. - * There doesn't seem to be a mechanism on the switch intellectual propert= y to - * have link-local frames bypass this function of the Forwarding Process. - */ -static void -mt753x_trap_frames(struct mt7530_priv *priv) -{ - /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress - * them with the EG_TAG attribute set to disabled (system default) - * so that any VLAN tags in the frame are not modified by the - * switch egress VLAN tag processing. This preserves VLAN tags - * for reception on VLAN sub-interfaces. - */ - regmap_update_bits(priv->regmap, MT753X_BPC, - PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK | - BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK, - PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_DISABLED) | - PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) | - BPDU_EG_TAG(MT7530_VLAN_EG_DISABLED) | - TO_CPU_FW_CPU_ONLY); - - /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and - * egress them with EG_TAG disabled. - */ - regmap_update_bits(priv->regmap, MT753X_RGAC1, - R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK | - R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK, - R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_DISABLED) | - R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR | - R01_EG_TAG(MT7530_VLAN_EG_DISABLED) | - TO_CPU_FW_CPU_ONLY); - - /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and - * egress them with EG_TAG disabled. - */ - regmap_update_bits(priv->regmap, MT753X_RGAC2, - R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK | - R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK, - R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_DISABLED) | - R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR | - R03_EG_TAG(MT7530_VLAN_EG_DISABLED) | - TO_CPU_FW_CPU_ONLY); -} - static void mt753x_cpu_port_enable(struct dsa_switch *ds, int port) { @@ -1329,11 +1091,11 @@ mt7530_port_enable(struct dsa_switch *ds, int port, if (dsa_port_is_user(dp)) { struct dsa_port *cpu_dp =3D dp->cpu_dp; =20 - priv->ports[port].pm |=3D PCR_MATRIX(BIT(cpu_dp->index)); + priv->ports[port].pm |=3D BIT(cpu_dp->index); } priv->ports[port].enable =3D true; regmap_update_bits(priv->regmap, MT7530_PCR_P(port), PCR_MATRIX_MASK, - priv->ports[port].pm); + PCR_MATRIX(priv->ports[port].pm)); =20 mutex_unlock(&priv->reg_mutex); =20 @@ -1378,36 +1140,8 @@ static int mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) { struct mt7530_priv *priv =3D ds->priv; - int length; - u32 val; - - /* When a new MTU is set, DSA always set the CPU port's MTU to the - * largest MTU of the user ports. Because the switch only has a global - * RX length register, only allowing CPU port here is enough. - */ - if (!dsa_is_cpu_port(ds, port)) - return 0; - - regmap_read(priv->regmap, MT7530_GMACCR, &val); - val &=3D ~MAX_RX_PKT_LEN_MASK; - - /* RX length also includes Ethernet header, MTK tag, and FCS length */ - length =3D new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; - if (length <=3D 1522) { - val |=3D MAX_RX_PKT_LEN_1522; - } else if (length <=3D 1536) { - val |=3D MAX_RX_PKT_LEN_1536; - } else if (length <=3D 1552) { - val |=3D MAX_RX_PKT_LEN_1552; - } else { - val &=3D ~MAX_RX_JUMBO_MASK; - val |=3D MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); - val |=3D MAX_RX_PKT_LEN_JUMBO; - } - - regmap_write(priv->regmap, MT7530_GMACCR, val); =20 - return 0; + return mt7530_lib_port_change_mtu(&priv->lib_priv, port, new_mtu); } =20 static int @@ -1420,81 +1154,8 @@ static void mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) { struct mt7530_priv *priv =3D ds->priv; - u32 stp_state; =20 - switch (state) { - case BR_STATE_DISABLED: - stp_state =3D MT7530_STP_DISABLED; - break; - case BR_STATE_BLOCKING: - stp_state =3D MT7530_STP_BLOCKING; - break; - case BR_STATE_LISTENING: - stp_state =3D MT7530_STP_LISTENING; - break; - case BR_STATE_LEARNING: - stp_state =3D MT7530_STP_LEARNING; - break; - case BR_STATE_FORWARDING: - default: - stp_state =3D MT7530_STP_FORWARDING; - break; - } - - regmap_update_bits(priv->regmap, MT7530_SSP_P(port), - FID_PST_MASK(FID_BRIDGED), - FID_PST(FID_BRIDGED, stp_state)); -} - -static void mt7530_update_port_member(struct mt7530_priv *priv, int port, - const struct net_device *bridge_dev, - bool join) __must_hold(&priv->reg_mutex) -{ - struct dsa_port *dp =3D dsa_to_port(priv->ds, port), *other_dp; - struct mt7530_port *p =3D &priv->ports[port], *other_p; - struct dsa_port *cpu_dp =3D dp->cpu_dp; - u32 port_bitmap =3D BIT(cpu_dp->index); - int other_port; - bool isolated; - - dsa_switch_for_each_user_port(other_dp, priv->ds) { - other_port =3D other_dp->index; - other_p =3D &priv->ports[other_port]; - - if (dp =3D=3D other_dp) - continue; - - /* Add/remove this port to/from the port matrix of the other - * ports in the same bridge. If the port is disabled, port - * matrix is kept and not being setup until the port becomes - * enabled. - */ - if (!dsa_port_offloads_bridge_dev(other_dp, bridge_dev)) - continue; - - isolated =3D p->isolated && other_p->isolated; - - if (join && !isolated) { - other_p->pm |=3D PCR_MATRIX(BIT(port)); - port_bitmap |=3D BIT(other_port); - } else { - other_p->pm &=3D ~PCR_MATRIX(BIT(port)); - } - - if (other_p->enable) - regmap_update_bits(priv->regmap, - MT7530_PCR_P(other_port), - PCR_MATRIX_MASK, other_p->pm); - } - - /* Add/remove the all other ports to this port matrix. For !join - * (leaving the bridge), only the CPU port will remain in the port matrix - * of this port. - */ - p->pm =3D PCR_MATRIX(port_bitmap); - if (priv->ports[port].enable) - regmap_update_bits(priv->regmap, MT7530_PCR_P(port), - PCR_MATRIX_MASK, p->pm); + mt7530_lib_stp_state_set(&priv->lib_priv, port, state); } =20 static int @@ -1516,37 +1177,8 @@ mt7530_port_bridge_flags(struct dsa_switch *ds, int = port, { struct mt7530_priv *priv =3D ds->priv; =20 - if (flags.mask & BR_LEARNING) - regmap_update_bits(priv->regmap, MT7530_PSC_P(port), SA_DIS, - flags.val & BR_LEARNING ? 0 : SA_DIS); - - if (flags.mask & BR_FLOOD) - regmap_update_bits(priv->regmap, MT753X_MFC, - UNU_FFP(BIT(port)), - flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); - - if (flags.mask & BR_MCAST_FLOOD) - regmap_update_bits(priv->regmap, MT753X_MFC, - UNM_FFP(BIT(port)), - flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); - - if (flags.mask & BR_BCAST_FLOOD) - regmap_update_bits(priv->regmap, MT753X_MFC, - BC_FFP(BIT(port)), - flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); - - if (flags.mask & BR_ISOLATED) { - struct dsa_port *dp =3D dsa_to_port(ds, port); - struct net_device *bridge_dev =3D dsa_port_bridge_dev_get(dp); - - priv->ports[port].isolated =3D !!(flags.val & BR_ISOLATED); - - mutex_lock(&priv->reg_mutex); - mt7530_update_port_member(priv, port, bridge_dev, true); - mutex_unlock(&priv->reg_mutex); - } - - return 0; + return mt7530_lib_port_bridge_flags(&priv->lib_priv, port, flags, + extack); } =20 static int @@ -1556,151 +1188,8 @@ mt7530_port_bridge_join(struct dsa_switch *ds, int = port, { struct mt7530_priv *priv =3D ds->priv; =20 - mutex_lock(&priv->reg_mutex); - - mt7530_update_port_member(priv, port, bridge.dev, true); - - /* Set to fallback mode for independent VLAN learning */ - regmap_update_bits(priv->regmap, MT7530_PCR_P(port), - PCR_PORT_VLAN_MASK, MT7530_PORT_FALLBACK_MODE); - - mutex_unlock(&priv->reg_mutex); - - return 0; -} - -static int -mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vi= d) -{ - u32 val; - int ret; - - val =3D VTCR_BUSY | VTCR_FUNC(cmd) | VTCR_VID(vid); - ret =3D regmap_write(priv->regmap, MT7530_VTCR, val); - if (ret) - return ret; - - ret =3D regmap_read_poll_timeout(priv->regmap, MT7530_VTCR, val, - !(val & VTCR_BUSY), 20, 20000); - if (!ret) - ret =3D regmap_read(priv->regmap, MT7530_VTCR, &val); - - if (ret < 0) { - dev_err(priv->dev, "poll timeout\n"); - return ret; - } - - if (val & VTCR_INVALID) { - dev_err(priv->dev, "read VTCR invalid\n"); - return -EINVAL; - } - - return 0; -} - -static int -mt7530_setup_vlan0(struct mt7530_priv *priv) -{ - u32 val; - - /* Validate the entry with independent learning, keep the original - * ingress tag attribute. - */ - val =3D IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED= ) | - VLAN_VALID; - regmap_write(priv->regmap, MT7530_VAWD1, val); - regmap_write(priv->regmap, MT7530_VAWD2, 0); - - return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); -} - -static void -mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) -{ - struct mt7530_priv *priv =3D ds->priv; - bool all_user_ports_removed =3D true; - int i; - - /* This is called after .port_bridge_leave when leaving a VLAN-aware - * bridge. Don't set standalone ports to fallback mode. - */ - if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) - regmap_update_bits(priv->regmap, MT7530_PCR_P(port), - PCR_PORT_VLAN_MASK, - MT7530_PORT_FALLBACK_MODE); - - regmap_update_bits(priv->regmap, MT7530_PVC_P(port), - VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, - VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | - PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | - MT7530_VLAN_ACC_ALL); - - /* Set PVID to 0 */ - regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port), - G0_PORT_VID_MASK, G0_PORT_VID_DEF); - - for (i =3D 0; i < priv->ds->num_ports; i++) { - if (i =3D=3D port) - continue; - if (dsa_is_user_port(ds, i) && - dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { - all_user_ports_removed =3D false; - break; - } - } - - /* CPU port also does the same thing until all user ports belonging to - * the CPU port get out of VLAN filtering mode. - */ - if (all_user_ports_removed) { - mutex_lock(&priv->reg_mutex); - mt7530_setup_vlan0(priv); - mutex_unlock(&priv->reg_mutex); - } -} - -static void -mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) -{ - struct mt7530_priv *priv =3D ds->priv; - - /* Trapped into security mode allows packet forwarding through VLAN - * table lookup. - */ - if (dsa_is_user_port(ds, port)) { - regmap_update_bits(priv->regmap, MT7530_PCR_P(port), - PCR_PORT_VLAN_MASK, - MT7530_PORT_SECURITY_MODE); - regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port), - G0_PORT_VID_MASK, - G0_PORT_VID(priv->ports[port].pvid)); - - /* Only accept tagged frames if PVID is not set */ - if (!priv->ports[port].pvid) - regmap_update_bits(priv->regmap, MT7530_PVC_P(port), - ACC_FRM_MASK, - MT7530_VLAN_ACC_TAGGED); - - /* Set the port as a user port which is to be able to recognize - * VID from incoming packets before fetching entry within the - * VLAN table. - */ - regmap_update_bits(priv->regmap, MT7530_PVC_P(port), - VLAN_ATTR_MASK | PVC_EG_TAG_MASK, - VLAN_ATTR(MT7530_VLAN_USER) | - PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); - } else { - /* Also set CPU ports to the "user" VLAN port attribute, to - * allow VLAN classification, but keep the EG_TAG attribute as - * "consistent" (i.o.w. don't change its value) for packets - * received by the switch from the CPU, so that tagged packets - * are forwarded to user ports as tagged, and untagged as - * untagged. - */ - regmap_update_bits(priv->regmap, MT7530_PVC_P(port), - VLAN_ATTR_MASK, - VLAN_ATTR(MT7530_VLAN_USER)); - } + return mt7530_lib_port_bridge_join(&priv->lib_priv, port, bridge, + tx_fwd_offload, extack); } =20 static void @@ -1709,18 +1198,7 @@ mt7530_port_bridge_leave(struct dsa_switch *ds, int = port, { struct mt7530_priv *priv =3D ds->priv; =20 - mutex_lock(&priv->reg_mutex); - - mt7530_update_port_member(priv, port, bridge.dev, false); - - /* When a port is removed from the bridge, the port would be set up - * back to the default as is at initial boot which is a VLAN-unaware - * port. - */ - regmap_update_bits(priv->regmap, MT7530_PCR_P(port), - PCR_PORT_VLAN_MASK, MT7530_PORT_MATRIX_MODE); - - mutex_unlock(&priv->reg_mutex); + return mt7530_lib_port_bridge_leave(&priv->lib_priv, port, bridge); } =20 static int @@ -1729,15 +1207,8 @@ mt7530_port_fdb_add(struct dsa_switch *ds, int port, struct dsa_db db) { struct mt7530_priv *priv =3D ds->priv; - int ret; - u8 port_mask =3D BIT(port); - - mutex_lock(&priv->reg_mutex); - mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); - ret =3D mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); - mutex_unlock(&priv->reg_mutex); =20 - return ret; + return mt7530_lib_port_fdb_add(&priv->lib_priv, port, addr, vid, db); } =20 static int @@ -1746,15 +1217,8 @@ mt7530_port_fdb_del(struct dsa_switch *ds, int port, struct dsa_db db) { struct mt7530_priv *priv =3D ds->priv; - int ret; - u8 port_mask =3D BIT(port); =20 - mutex_lock(&priv->reg_mutex); - mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); - ret =3D mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); - mutex_unlock(&priv->reg_mutex); - - return ret; + return mt7530_lib_port_fdb_del(&priv->lib_priv, port, addr, vid, db); } =20 static int @@ -1769,13 +1233,14 @@ mt7530_port_fdb_dump(struct dsa_switch *ds, int por= t, =20 mutex_lock(&priv->reg_mutex); =20 - ret =3D mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); + ret =3D mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_START, + ATC_MAT_MACTAB, &rsp); if (ret < 0) goto err; =20 do { if (rsp & ATC_SRCH_HIT) { - mt7530_fdb_read(priv, &_fdb); + mt7530_lib_fdb_read(&priv->lib_priv, &_fdb); if (_fdb.port_mask & BIT(port)) { ret =3D cb(_fdb.mac, _fdb.vid, _fdb.noarp, data); @@ -1785,7 +1250,8 @@ mt7530_port_fdb_dump(struct dsa_switch *ds, int port, } } while (--cnt && !(rsp & ATC_SRCH_END) && - !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); + !mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_NEXT, + ATC_MAT_MACTAB, &rsp)); err: mutex_unlock(&priv->reg_mutex); =20 @@ -1798,27 +1264,8 @@ mt7530_port_mdb_add(struct dsa_switch *ds, int port, struct dsa_db db) { struct mt7530_priv *priv =3D ds->priv; - const u8 *addr =3D mdb->addr; - u16 vid =3D mdb->vid; - u8 port_mask =3D 0; - u32 val; - int ret; - - mutex_lock(&priv->reg_mutex); - - mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); - if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) { - regmap_read(priv->regmap, MT7530_ATRD, &val); - port_mask =3D FIELD_GET(PORT_MAP_MASK, val); - } - - port_mask |=3D BIT(port); - mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); - ret =3D mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); - - mutex_unlock(&priv->reg_mutex); =20 - return ret; + return mt7530_lib_port_mdb_add(&priv->lib_priv, port, mdb, db); } =20 static int @@ -1827,132 +1274,19 @@ mt7530_port_mdb_del(struct dsa_switch *ds, int por= t, struct dsa_db db) { struct mt7530_priv *priv =3D ds->priv; - const u8 *addr =3D mdb->addr; - u16 vid =3D mdb->vid; - u8 port_mask =3D 0; - u32 val; - int ret; - - mutex_lock(&priv->reg_mutex); =20 - mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); - if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) { - regmap_read(priv->regmap, MT7530_ATRD, &val); - port_mask =3D FIELD_GET(PORT_MAP_MASK, val); - } - - port_mask &=3D ~BIT(port); - mt7530_fdb_write(priv, vid, port_mask, addr, -1, - port_mask ? STATIC_ENT : STATIC_EMP); - ret =3D mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); - - mutex_unlock(&priv->reg_mutex); - - return ret; + return mt7530_lib_port_mdb_del(&priv->lib_priv, port, mdb, db); } =20 static int mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filt= ering, struct netlink_ext_ack *extack) { - struct dsa_port *dp =3D dsa_to_port(ds, port); - struct dsa_port *cpu_dp =3D dp->cpu_dp; - - if (vlan_filtering) { - /* The port is being kept as VLAN-unaware port when bridge is - * set up with vlan_filtering not being set, Otherwise, the - * port and the corresponding CPU port is required the setup - * for becoming a VLAN-aware port. - */ - mt7530_port_set_vlan_aware(ds, port); - mt7530_port_set_vlan_aware(ds, cpu_dp->index); - } else { - mt7530_port_set_vlan_unaware(ds, port); - } - - return 0; -} - -static void -mt7530_hw_vlan_add(struct mt7530_priv *priv, - struct mt7530_hw_vlan_entry *entry) -{ - struct dsa_port *dp =3D dsa_to_port(priv->ds, entry->port); - u8 new_members; - u32 val; - - new_members =3D entry->old_members | BIT(entry->port); - - /* Validate the entry with independent learning, create egress tag per - * VLAN and joining the port as one of the port members. - */ - val =3D IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | - VLAN_VALID; - regmap_write(priv->regmap, MT7530_VAWD1, val); - - /* Decide whether adding tag or not for those outgoing packets from the - * port inside the VLAN. - * CPU port is always taken as a tagged port for serving more than one - * VLANs across and also being applied with egress type stack mode for - * that VLAN tags would be appended after hardware special tag used as - * DSA tag. - */ - if (dsa_port_is_cpu(dp)) - val =3D MT7530_VLAN_EGRESS_STACK; - else if (entry->untagged) - val =3D MT7530_VLAN_EGRESS_UNTAG; - else - val =3D MT7530_VLAN_EGRESS_TAG; - regmap_update_bits(priv->regmap, MT7530_VAWD2, - ETAG_CTRL_P_MASK(entry->port), - ETAG_CTRL_P(entry->port, val)); -} - -static void -mt7530_hw_vlan_del(struct mt7530_priv *priv, - struct mt7530_hw_vlan_entry *entry) -{ - u8 new_members; - u32 val; - - new_members =3D entry->old_members & ~BIT(entry->port); - - regmap_read(priv->regmap, MT7530_VAWD1, &val); - if (!(val & VLAN_VALID)) { - dev_err(priv->dev, - "Cannot be deleted due to invalid entry\n"); - return; - } - - if (new_members) { - val =3D IVL_MAC | VTAG_EN | PORT_MEM(new_members) | - VLAN_VALID; - regmap_write(priv->regmap, MT7530_VAWD1, val); - } else { - regmap_write(priv->regmap, MT7530_VAWD1, 0); - regmap_write(priv->regmap, MT7530_VAWD2, 0); - } -} - -static void -mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, - struct mt7530_hw_vlan_entry *entry, - mt7530_vlan_op vlan_op) -{ - u32 val; - - /* Fetch entry */ - mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); - - regmap_read(priv->regmap, MT7530_VAWD1, &val); - - entry->old_members =3D FIELD_GET(PORT_MEM_MASK, val); - - /* Manipulate entry */ - vlan_op(priv, entry); + struct mt7530_priv *priv =3D ds->priv; =20 - /* Flush result to hardware */ - mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); + return mt7530_lib_port_vlan_filtering(&priv->lib_priv, port, + vlan_filtering, + extack); } =20 static int @@ -1960,94 +1294,18 @@ mt7530_port_vlan_add(struct dsa_switch *ds, int por= t, const struct switchdev_obj_port_vlan *vlan, struct netlink_ext_ack *extack) { - bool untagged =3D vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; - bool pvid =3D vlan->flags & BRIDGE_VLAN_INFO_PVID; - struct mt7530_hw_vlan_entry new_entry; struct mt7530_priv *priv =3D ds->priv; =20 - mutex_lock(&priv->reg_mutex); - - /* VID 0 is managed exclusively by mt7530_setup_vlan0() for - * VLAN-unaware bridge operation. Don't let the bridge overwrite - * its EG_CON flag with VTAG_EN and corrupt PORT_MEM. - */ - if (vlan->vid =3D=3D 0) - goto skip_vlan_table; - - mt7530_hw_vlan_entry_init(&new_entry, port, untagged); - mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); - -skip_vlan_table: - - if (pvid) { - priv->ports[port].pvid =3D vlan->vid; - - /* Accept all frames if PVID is set */ - regmap_update_bits(priv->regmap, MT7530_PVC_P(port), - ACC_FRM_MASK, MT7530_VLAN_ACC_ALL); - - /* Only configure PVID if VLAN filtering is enabled */ - if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) - regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port), - G0_PORT_VID_MASK, - G0_PORT_VID(vlan->vid)); - } else if (vlan->vid && priv->ports[port].pvid =3D=3D vlan->vid) { - /* This VLAN is overwritten without PVID, so unset it */ - priv->ports[port].pvid =3D G0_PORT_VID_DEF; - - /* Only accept tagged frames if the port is VLAN-aware */ - if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) - regmap_update_bits(priv->regmap, MT7530_PVC_P(port), - ACC_FRM_MASK, - MT7530_VLAN_ACC_TAGGED); - - regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port), - G0_PORT_VID_MASK, G0_PORT_VID_DEF); - } - - mutex_unlock(&priv->reg_mutex); - - return 0; + return mt7530_lib_port_vlan_add(&priv->lib_priv, port, vlan, extack); } =20 static int mt7530_port_vlan_del(struct dsa_switch *ds, int port, const struct switchdev_obj_port_vlan *vlan) { - struct mt7530_hw_vlan_entry target_entry; struct mt7530_priv *priv =3D ds->priv; =20 - mutex_lock(&priv->reg_mutex); - - /* VID 0 is managed exclusively by mt7530_setup_vlan0(). */ - if (vlan->vid =3D=3D 0) - goto skip_vlan_table; - - mt7530_hw_vlan_entry_init(&target_entry, port, 0); - mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, - mt7530_hw_vlan_del); - -skip_vlan_table: - /* PVID is being restored to the default whenever the PVID port - * is being removed from the VLAN. - */ - if (priv->ports[port].pvid =3D=3D vlan->vid) { - priv->ports[port].pvid =3D G0_PORT_VID_DEF; - - /* Only accept tagged frames if the port is VLAN-aware */ - if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) - regmap_update_bits(priv->regmap, MT7530_PVC_P(port), - ACC_FRM_MASK, - MT7530_VLAN_ACC_TAGGED); - - regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port), - G0_PORT_VID_MASK, G0_PORT_VID_DEF); - } - - - mutex_unlock(&priv->reg_mutex); - - return 0; + return mt7530_lib_port_vlan_del(&priv->lib_priv, port, vlan); } =20 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, @@ -2055,60 +1313,16 @@ static int mt753x_port_mirror_add(struct dsa_switch= *ds, int port, bool ingress, struct netlink_ext_ack *extack) { struct mt7530_priv *priv =3D ds->priv; - int monitor_port; - u32 val; - - /* Check for existent entry */ - if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) - return -EEXIST; - - regmap_read(priv->regmap, MT753X_MIRROR_REG(priv->id), &val); - - /* MT7530 only supports one monitor port */ - monitor_port =3D MT753X_MIRROR_PORT_GET(priv->id, val); - if (val & MT753X_MIRROR_EN(priv->id) && - monitor_port !=3D mirror->to_local_port) - return -EEXIST; - - val |=3D MT753X_MIRROR_EN(priv->id); - val &=3D ~MT753X_MIRROR_PORT_MASK(priv->id); - val |=3D MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port); - regmap_write(priv->regmap, MT753X_MIRROR_REG(priv->id), val); =20 - regmap_read(priv->regmap, MT7530_PCR_P(port), &val); - if (ingress) { - val |=3D PORT_RX_MIR; - priv->mirror_rx |=3D BIT(port); - } else { - val |=3D PORT_TX_MIR; - priv->mirror_tx |=3D BIT(port); - } - regmap_write(priv->regmap, MT7530_PCR_P(port), val); - - return 0; + return mt7530_lib_port_mirror_add(&priv->lib_priv, port, mirror, ingress,= extack); } =20 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, struct dsa_mall_mirror_tc_entry *mirror) { struct mt7530_priv *priv =3D ds->priv; - u32 val; =20 - regmap_read(priv->regmap, MT7530_PCR_P(port), &val); - if (mirror->ingress) { - val &=3D ~PORT_RX_MIR; - priv->mirror_rx &=3D ~BIT(port); - } else { - val &=3D ~PORT_TX_MIR; - priv->mirror_tx &=3D ~BIT(port); - } - regmap_write(priv->regmap, MT7530_PCR_P(port), val); - - if (!priv->mirror_rx && !priv->mirror_tx) { - regmap_read(priv->regmap, MT753X_MIRROR_REG(priv->id), &val); - val &=3D ~MT753X_MIRROR_EN(priv->id); - regmap_write(priv->regmap, MT753X_MIRROR_REG(priv->id), val); - } + mt7530_lib_port_mirror_del(&priv->lib_priv, port, mirror); } =20 static enum dsa_tag_protocol @@ -2492,10 +1706,10 @@ mt7530_setup(struct dsa_switch *ds) if ((val & MT7530_XTAL_MASK) =3D=3D MT7530_XTAL_40MHZ) mt7530_pll_setup(priv); =20 - mt753x_trap_frames(priv); + mt7530_lib_trap_frames(&priv->lib_priv); =20 /* Enable and reset MIB counters */ - mt7530_mib_reset(ds); + mt7530_lib_mib_reset(&priv->lib_priv); =20 for (i =3D 0; i < priv->ds->num_ports; i++) { /* Clear link settings and enable force mode to force link down @@ -2519,7 +1733,8 @@ mt7530_setup(struct dsa_switch *ds) =20 /* Set default PVID to 0 on all user ports */ regmap_update_bits(priv->regmap, MT7530_PPBV1_P(i), - G0_PORT_VID_MASK, G0_PORT_VID_DEF); + G0_PORT_VID_MASK, + G0_PORT_VID(G0_PORT_VID_DEF)); } /* Enable consistent egress tag */ regmap_update_bits(priv->regmap, MT7530_PVC_P(i), @@ -2531,7 +1746,7 @@ mt7530_setup(struct dsa_switch *ds) regmap_set_bits(priv->regmap, MT753X_AGC, LOCAL_EN); =20 /* Setup VLAN ID 0 for VLAN-unaware bridges */ - ret =3D mt7530_setup_vlan0(priv); + ret =3D mt7530_lib_setup_vlan0(&priv->lib_priv); if (ret) return ret; =20 @@ -2590,7 +1805,8 @@ mt7530_setup(struct dsa_switch *ds) #endif /* CONFIG_GPIOLIB */ =20 /* Flush the FDB table */ - ret =3D mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); + ret =3D mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_FLUSH, + ATC_MAT_MACTAB, NULL); if (ret < 0) return ret; =20 @@ -2609,10 +1825,10 @@ mt7531_setup_common(struct dsa_switch *ds) ds->ageing_time_min =3D 2 * 1000; ds->ageing_time_max =3D (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1) * 1000; =20 - mt753x_trap_frames(priv); + mt7530_lib_trap_frames(&priv->lib_priv); =20 /* Enable and reset MIB counters */ - mt7530_mib_reset(ds); + mt7530_lib_mib_reset(&priv->lib_priv); =20 /* Disable flooding on all ports */ regmap_clear_bits(priv->regmap, MT753X_MFC, @@ -2643,7 +1859,8 @@ mt7531_setup_common(struct dsa_switch *ds) =20 /* Set default PVID to 0 on all user ports */ regmap_update_bits(priv->regmap, MT7530_PPBV1_P(i), - G0_PORT_VID_MASK, G0_PORT_VID_DEF); + G0_PORT_VID_MASK, + G0_PORT_VID(G0_PORT_VID_DEF)); } =20 /* Enable consistent egress tag */ @@ -2661,12 +1878,13 @@ mt7531_setup_common(struct dsa_switch *ds) CPORT_SW2FE_STAG_EN | CPORT_FE2SW_STAG_EN); =20 /* Flush the FDB table */ - ret =3D mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); + ret =3D mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_FLUSH, + ATC_MAT_MACTAB, NULL); if (ret < 0) return ret; =20 /* Setup VLAN ID 0 for VLAN-unaware bridges */ - return mt7530_setup_vlan0(priv); + return mt7530_lib_setup_vlan0(&priv->lib_priv); } =20 static int @@ -3281,11 +2499,12 @@ mt753x_port_change_conduit(struct dsa_switch *ds, i= nt port, mutex_lock(&priv->reg_mutex); =20 /* dp->cpu_dp still points to the old CPU port */ - priv->ports[port].pm &=3D ~PCR_MATRIX(BIT(dp->cpu_dp->index)); - priv->ports[port].pm |=3D PCR_MATRIX(BIT(new_cpu_dp->index)); + priv->ports[port].pm &=3D ~BIT(dp->cpu_dp->index); + priv->ports[port].pm |=3D BIT(new_cpu_dp->index); if (priv->ports[port].enable) regmap_update_bits(priv->regmap, MT7530_PCR_P(port), - PCR_MATRIX_MASK, priv->ports[port].pm); + PCR_MATRIX_MASK, + PCR_MATRIX(priv->ports[port].pm)); =20 mutex_unlock(&priv->reg_mutex); =20 @@ -3456,6 +2675,8 @@ static const struct phylink_mac_ops mt753x_phylink_ma= c_ops =3D { const struct mt753x_info mt753x_table[] =3D { [ID_MT7621] =3D { .id =3D ID_MT7621, + .reg_fields =3D mt7530_fields, + .num_reg_fields =3D ARRAY_SIZE(mt7530_fields), .pcs_ops =3D &mt7530_pcs_ops, .sw_setup =3D mt7530_setup, .phy_read_c22 =3D mt7530_phy_read_c22, @@ -3467,6 +2688,8 @@ const struct mt753x_info mt753x_table[] =3D { }, [ID_MT7530] =3D { .id =3D ID_MT7530, + .reg_fields =3D mt7530_fields, + .num_reg_fields =3D ARRAY_SIZE(mt7530_fields), .pcs_ops =3D &mt7530_pcs_ops, .sw_setup =3D mt7530_setup, .phy_read_c22 =3D mt7530_phy_read_c22, @@ -3478,6 +2701,8 @@ const struct mt753x_info mt753x_table[] =3D { }, [ID_MT7531] =3D { .id =3D ID_MT7531, + .reg_fields =3D mt7531_fields, + .num_reg_fields =3D ARRAY_SIZE(mt7531_fields), .pcs_ops =3D &mt7530_pcs_ops, .sw_setup =3D mt7531_setup, .phy_read_c22 =3D mt7531_ind_c22_phy_read, @@ -3489,6 +2714,8 @@ const struct mt753x_info mt753x_table[] =3D { }, [ID_MT7988] =3D { .id =3D ID_MT7988, + .reg_fields =3D mt7531_fields, + .num_reg_fields =3D ARRAY_SIZE(mt7531_fields), .pcs_ops =3D &mt7530_pcs_ops, .sw_setup =3D mt7988_setup, .phy_read_c22 =3D mt7531_ind_c22_phy_read, @@ -3499,6 +2726,8 @@ const struct mt753x_info mt753x_table[] =3D { }, [ID_EN7581] =3D { .id =3D ID_EN7581, + .reg_fields =3D mt7531_fields, + .num_reg_fields =3D ARRAY_SIZE(mt7531_fields), .pcs_ops =3D &mt7530_pcs_ops, .sw_setup =3D mt7988_setup, .phy_read_c22 =3D mt7531_ind_c22_phy_read, @@ -3509,6 +2738,8 @@ const struct mt753x_info mt753x_table[] =3D { }, [ID_AN7583] =3D { .id =3D ID_AN7583, + .reg_fields =3D mt7531_fields, + .num_reg_fields =3D ARRAY_SIZE(mt7531_fields), .pcs_ops =3D &mt7530_pcs_ops, .sw_setup =3D mt7988_setup, .phy_read_c22 =3D mt7531_ind_c22_phy_read, @@ -3519,6 +2750,8 @@ const struct mt753x_info mt753x_table[] =3D { }, [ID_EN7528] =3D { .id =3D ID_EN7528, + .reg_fields =3D mt7531_fields, + .num_reg_fields =3D ARRAY_SIZE(mt7531_fields), .pcs_ops =3D &mt7530_pcs_ops, .sw_setup =3D mt7988_setup, .phy_read_c22 =3D mt7531_ind_c22_phy_read, @@ -3573,6 +2806,47 @@ mt7530_remove_common(struct mt7530_priv *priv) } EXPORT_SYMBOL_GPL(mt7530_remove_common); =20 +int mt7530_setup_lib_priv(struct mt7530_priv *priv) +{ + struct mt7530_lib_priv *lib_priv =3D &priv->lib_priv; + int i; + + lib_priv->dev =3D priv->dev; + lib_priv->ds =3D priv->ds; + lib_priv->regmap =3D priv->regmap; + lib_priv->ports =3D priv->ports; + lib_priv->reg_mutex =3D &priv->reg_mutex; + + for (i =3D 0; i < ARRAY_SIZE(mt753x_fields); i++) { + const struct mt7530_reg_field *reg_field; + struct regmap_field *field; + + reg_field =3D &mt753x_fields[i]; + field =3D devm_regmap_field_alloc(priv->dev, priv->regmap, + reg_field->field); + if (IS_ERR(field)) + return PTR_ERR(field); + + lib_priv->fields[reg_field->id] =3D field; + } + + for (i =3D 0; i < priv->info->num_reg_fields; i++) { + const struct mt7530_reg_field *reg_field; + struct regmap_field *field; + + reg_field =3D &priv->info->reg_fields[i]; + field =3D devm_regmap_field_alloc(priv->dev, priv->regmap, + reg_field->field); + if (IS_ERR(field)) + return PTR_ERR(field); + + lib_priv->fields[reg_field->id] =3D field; + } + + return 0; +} +EXPORT_SYMBOL_GPL(mt7530_setup_lib_priv); + MODULE_AUTHOR("Sean Wang "); MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); MODULE_LICENSE("GPL"); diff --git a/drivers/net/dsa/mediatek/mt7530.h b/drivers/net/dsa/mediatek/m= t7530.h index 2bbbe617b52e..50a12e10893d 100644 --- a/drivers/net/dsa/mediatek/mt7530.h +++ b/drivers/net/dsa/mediatek/mt7530.h @@ -7,14 +7,11 @@ #define __MT7530_H =20 #include +#include "mt7530-lib.h" =20 #define MT7530_NUM_PORTS 7 #define MT7530_NUM_PHYS 5 #define MT7530_NUM_FDB_RECORDS 2048 -#define MT7530_ALL_MEMBERS 0xff - -#define MTK_HDR_LEN 4 -#define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN) =20 enum mt753x_id { ID_MT7530 =3D 0, @@ -135,18 +132,8 @@ enum mt753x_id { #define R03_EG_TAG(x) FIELD_PREP(R03_EG_TAG_MASK, x) #define R03_PORT_FW_MASK GENMASK(2, 0) =20 -enum mt753x_to_cpu_fw { - TO_CPU_FW_SYSTEM_DEFAULT, - TO_CPU_FW_CPU_EXCLUDE =3D 4, - TO_CPU_FW_CPU_INCLUDE =3D 5, - TO_CPU_FW_CPU_ONLY =3D 6, - TO_CPU_FW_DROP =3D 7, -}; - /* Registers for address table access */ #define MT7530_ATA1 0x74 -#define STATIC_EMP 0 -#define STATIC_ENT 3 #define MT7530_ATA2 0x78 #define ATA2_IVL BIT(15) #define ATA2_FID_MASK GENMASK(14, 12) @@ -165,16 +152,6 @@ enum mt753x_to_cpu_fw { #define ATC_INVALID BIT(12) #define ATC_MAT_MASK GENMASK(11, 8) #define ATC_MAT(x) FIELD_PREP(ATC_MAT_MASK, x) -#define ATC_MAT_MACTAB ATC_MAT(0) -#define ATC_MAT_NON_STATIC_MAC ATC_MAT(4) - -enum mt7530_fdb_cmd { - MT7530_FDB_READ =3D 0, - MT7530_FDB_WRITE =3D 1, - MT7530_FDB_FLUSH =3D 2, - MT7530_FDB_START =3D 4, - MT7530_FDB_NEXT =3D 5, -}; =20 /* Registers for table search read address */ #define MT7530_TSRA1 0x84 @@ -202,14 +179,6 @@ enum mt7530_fdb_cmd { #define VTCR_VID_MASK GENMASK(11, 0) #define VTCR_VID(x) FIELD_PREP(VTCR_VID_MASK, x) =20 -enum mt7530_vlan_cmd { - /* Read/Write the specified VID entry from VAWD register based - * on VID. - */ - MT7530_VTCR_RD_VID =3D 0, - MT7530_VTCR_WR_VID =3D 1, -}; - /* Register for setup vlan and acl write data */ #define MT7530_VAWD1 0x94 #define PORT_STAG BIT(31) @@ -228,21 +197,7 @@ enum mt7530_vlan_cmd { /* VLAN Entry Valid */ #define VLAN_VALID BIT(0) =20 -enum mt7530_fid { - FID_STANDALONE =3D 0, - FID_BRIDGED =3D 1, -}; - #define MT7530_VAWD2 0x98 -/* Egress Tag Control */ -#define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1)) -#define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3) - -enum mt7530_vlan_egress_attr { - MT7530_VLAN_EGRESS_UNTAG =3D 0, - MT7530_VLAN_EGRESS_TAG =3D 2, - MT7530_VLAN_EGRESS_STACK =3D 3, -}; =20 /* Register for address age control */ #define MT7530_AAC 0xa0 @@ -270,40 +225,16 @@ enum mt7530_vlan_egress_attr { #define EGR_BC_CRC_IPG_PREAMBLE 0x18 /* crc + ipg + preamble */ =20 /* Register for port STP state control */ -#define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100)) -#define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2)) -#define FID_PST_MASK(fid) FID_PST(fid, 0x3) - -enum mt7530_stp_state { - MT7530_STP_DISABLED =3D 0, - MT7530_STP_BLOCKING =3D 1, - MT7530_STP_LISTENING =3D 1, - MT7530_STP_LEARNING =3D 2, - MT7530_STP_FORWARDING =3D 3 -}; +#define MT7530_SSP 0x2000 +#define MT7530_SSP_P(x) (MT7530_SSP + ((x) * 0x100)) =20 /* Register for port control */ -#define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100)) +#define MT7530_PCR 0x2004 +#define MT7530_PCR_P(x) (MT7530_PCR + ((x) * 0x100)) #define PORT_TX_MIR BIT(9) #define PORT_RX_MIR BIT(8) #define PCR_PORT_VLAN_MASK GENMASK(1, 0) =20 -enum mt7530_port_mode { - /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */ - MT7530_PORT_MATRIX_MODE =3D 0, - - /* Fallback Mode: Forward received frames with ingress ports that do - * not belong to the VLAN member. Frames whose VID is not listed on - * the VLAN table are forwarded by the PCR_MATRIX members. - */ - MT7530_PORT_FALLBACK_MODE =3D 1, - - /* Security Mode: Discard any frame due to ingress membership - * violation or VID missed on the VLAN table. - */ - MT7530_PORT_SECURITY_MODE =3D 3, -}; - #define PCR_MATRIX_MASK GENMASK(23, 16) #define PCR_MATRIX(x) FIELD_PREP(PCR_MATRIX_MASK, x) #define PORT_PRI_MASK GENMASK(26, 24) @@ -313,11 +244,13 @@ enum mt7530_port_mode { #define PCR_MATRIX_CLR PCR_MATRIX(0) =20 /* Register for port security control */ -#define MT7530_PSC_P(x) (0x200c + ((x) * 0x100)) +#define MT7530_PSC 0x200c +#define MT7530_PSC_P(x) (MT7530_PSC + ((x) * 0x100)) #define SA_DIS BIT(4) =20 /* Register for port vlan control */ -#define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100)) +#define MT7530_PVC 0x2010 +#define MT7530_PVC_P(x) (MT7530_PVC + ((x) * 0x100)) #define PORT_SPEC_TAG BIT(5) #define PVC_EG_TAG_MASK GENMASK(10, 8) #define PVC_EG_TAG(x) FIELD_PREP(PVC_EG_TAG_MASK, x) @@ -325,31 +258,14 @@ enum mt7530_port_mode { #define VLAN_ATTR(x) FIELD_PREP(VLAN_ATTR_MASK, x) #define ACC_FRM_MASK GENMASK(1, 0) =20 -enum mt7530_vlan_port_eg_tag { - MT7530_VLAN_EG_DISABLED =3D 0, - MT7530_VLAN_EG_CONSISTENT =3D 1, - MT7530_VLAN_EG_UNTAGGED =3D 4, -}; - -enum mt7530_vlan_port_attr { - MT7530_VLAN_USER =3D 0, - MT7530_VLAN_TRANSPARENT =3D 3, -}; - -enum mt7530_vlan_port_acc_frm { - MT7530_VLAN_ACC_ALL =3D 0, - MT7530_VLAN_ACC_TAGGED =3D 1, - MT7530_VLAN_ACC_UNTAGGED =3D 2, -}; - #define STAG_VPID_MASK GENMASK(31, 16) #define STAG_VPID(x) FIELD_PREP(STAG_VPID_MASK, x) =20 /* Register for port port-and-protocol based vlan 1 control */ +#define MT7530_PPBV1 0x2014 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100)) #define G0_PORT_VID_MASK GENMASK(11, 0) #define G0_PORT_VID(x) FIELD_PREP(G0_PORT_VID_MASK, x) -#define G0_PORT_VID_DEF G0_PORT_VID(0) =20 /* Register for port MAC control register */ #define MT753X_PMCR_P(x) (0x3000 + ((x) * 0x100)) @@ -427,55 +343,54 @@ enum mt7530_vlan_port_acc_frm { #define MAX_RX_JUMBO_MASK GENMASK(5, 2) #define MAX_RX_JUMBO(x) FIELD_PREP(MAX_RX_JUMBO_MASK, x) #define MAX_RX_PKT_LEN_MASK GENMASK(1, 0) -#define MAX_RX_PKT_LEN_1522 0x0 -#define MAX_RX_PKT_LEN_1536 0x1 -#define MAX_RX_PKT_LEN_1552 0x2 -#define MAX_RX_PKT_LEN_JUMBO 0x3 =20 /* Register for MIB */ -#define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100) +#define MT7530_MIB_COUNTER 0x4000 +#define MT7530_PORT_MIB_COUNTER(x) (MT7530_MIB_COUNTER + (x) * 0x100) /* Each define is an offset of MT7530_PORT_MIB_COUNTER */ -#define MT7530_PORT_MIB_TX_DROP 0x00 -#define MT7530_PORT_MIB_TX_CRC_ERR 0x04 -#define MT7530_PORT_MIB_TX_UNICAST 0x08 -#define MT7530_PORT_MIB_TX_MULTICAST 0x0c -#define MT7530_PORT_MIB_TX_BROADCAST 0x10 -#define MT7530_PORT_MIB_TX_COLLISION 0x14 -#define MT7530_PORT_MIB_TX_SINGLE_COLLISION 0x18 -#define MT7530_PORT_MIB_TX_MULTIPLE_COLLISION 0x1c -#define MT7530_PORT_MIB_TX_DEFERRED 0x20 -#define MT7530_PORT_MIB_TX_LATE_COLLISION 0x24 -#define MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION 0x28 -#define MT7530_PORT_MIB_TX_PAUSE 0x2c -#define MT7530_PORT_MIB_TX_PKT_SZ_64 0x30 -#define MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127 0x34 -#define MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255 0x38 -#define MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511 0x3c -#define MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023 0x40 -#define MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX 0x44 -#define MT7530_PORT_MIB_TX_BYTES 0x48 /* 64 bytes */ -#define MT7530_PORT_MIB_RX_DROP 0x60 -#define MT7530_PORT_MIB_RX_FILTERING 0x64 -#define MT7530_PORT_MIB_RX_UNICAST 0x68 -#define MT7530_PORT_MIB_RX_MULTICAST 0x6c -#define MT7530_PORT_MIB_RX_BROADCAST 0x70 -#define MT7530_PORT_MIB_RX_ALIGN_ERR 0x74 -#define MT7530_PORT_MIB_RX_CRC_ERR 0x78 -#define MT7530_PORT_MIB_RX_UNDER_SIZE_ERR 0x7c -#define MT7530_PORT_MIB_RX_FRAG_ERR 0x80 -#define MT7530_PORT_MIB_RX_OVER_SZ_ERR 0x84 -#define MT7530_PORT_MIB_RX_JABBER_ERR 0x88 -#define MT7530_PORT_MIB_RX_PAUSE 0x8c -#define MT7530_PORT_MIB_RX_PKT_SZ_64 0x90 -#define MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127 0x94 -#define MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255 0x98 -#define MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511 0x9c -#define MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023 0xa0 -#define MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX 0xa4 -#define MT7530_PORT_MIB_RX_BYTES 0xa8 /* 64 bytes */ -#define MT7530_PORT_MIB_RX_CTRL_DROP 0xb0 -#define MT7530_PORT_MIB_RX_INGRESS_DROP 0xb4 -#define MT7530_PORT_MIB_RX_ARL_DROP 0xb8 +#define MT7530_PORT_MIB_TX_DROP (MT7530_MIB_COUNTER + 0x00) +#define MT7530_PORT_MIB_TX_CRC_ERR (MT7530_MIB_COUNTER + 0x04) +#define MT7530_PORT_MIB_TX_UNICAST (MT7530_MIB_COUNTER + 0x08) +#define MT7530_PORT_MIB_TX_MULTICAST (MT7530_MIB_COUNTER + 0x0c) +#define MT7530_PORT_MIB_TX_BROADCAST (MT7530_MIB_COUNTER + 0x10) +#define MT7530_PORT_MIB_TX_COLLISION (MT7530_MIB_COUNTER + 0x14) +#define MT7530_PORT_MIB_TX_SINGLE_COLLISION (MT7530_MIB_COUNTER + 0x18) +#define MT7530_PORT_MIB_TX_MULTIPLE_COLLISION (MT7530_MIB_COUNTER + 0x1c) +#define MT7530_PORT_MIB_TX_DEFERRED (MT7530_MIB_COUNTER + 0x20) +#define MT7530_PORT_MIB_TX_LATE_COLLISION (MT7530_MIB_COUNTER + 0x24) +#define MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION (MT7530_MIB_COUNTER + 0x2= 8) +#define MT7530_PORT_MIB_TX_PAUSE (MT7530_MIB_COUNTER + 0x2c) +#define MT7530_PORT_MIB_TX_PKT_SZ_64 (MT7530_MIB_COUNTER + 0x30) +#define MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127 (MT7530_MIB_COUNTER + 0x34) +#define MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255 (MT7530_MIB_COUNTER + 0x38) +#define MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511 (MT7530_MIB_COUNTER + 0x3c) +#define MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023 (MT7530_MIB_COUNTER + 0x40) +#define MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX (MT7530_MIB_COUNTER + 0x44) +#define MT7530_PORT_MIB_TX_BYTES_LOW (MT7530_MIB_COUNTER + 0x48) /* 64 b= ytes */ +#define MT7530_PORT_MIB_TX_BYTES_HIGH (MT7530_MIB_COUNTER + 0x4c) +#define MT7530_PORT_MIB_RX_DROP (MT7530_MIB_COUNTER + 0x60) +#define MT7530_PORT_MIB_RX_FILTERING (MT7530_MIB_COUNTER + 0x64) +#define MT7530_PORT_MIB_RX_UNICAST (MT7530_MIB_COUNTER + 0x68) +#define MT7530_PORT_MIB_RX_MULTICAST (MT7530_MIB_COUNTER + 0x6c) +#define MT7530_PORT_MIB_RX_BROADCAST (MT7530_MIB_COUNTER + 0x70) +#define MT7530_PORT_MIB_RX_ALIGN_ERR (MT7530_MIB_COUNTER + 0x74) +#define MT7530_PORT_MIB_RX_CRC_ERR (MT7530_MIB_COUNTER + 0x78) +#define MT7530_PORT_MIB_RX_UNDER_SIZE_ERR (MT7530_MIB_COUNTER + 0x7c) +#define MT7530_PORT_MIB_RX_FRAG_ERR (MT7530_MIB_COUNTER + 0x80) +#define MT7530_PORT_MIB_RX_OVER_SZ_ERR (MT7530_MIB_COUNTER + 0x84) +#define MT7530_PORT_MIB_RX_JABBER_ERR (MT7530_MIB_COUNTER + 0x88) +#define MT7530_PORT_MIB_RX_PAUSE (MT7530_MIB_COUNTER + 0x8c) +#define MT7530_PORT_MIB_RX_PKT_SZ_64 (MT7530_MIB_COUNTER + 0x90) +#define MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127 (MT7530_MIB_COUNTER + 0x94) +#define MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255 (MT7530_MIB_COUNTER + 0x98) +#define MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511 (MT7530_MIB_COUNTER + 0x9c) +#define MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023 (MT7530_MIB_COUNTER + 0xa0) +#define MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX (MT7530_MIB_COUNTER + 0xa4) +#define MT7530_PORT_MIB_RX_BYTES_LOW (MT7530_MIB_COUNTER + 0xa8) /* 64 b= ytes */ +#define MT7530_PORT_MIB_RX_BYTES_HIGH (MT7530_MIB_COUNTER + 0xac) +#define MT7530_PORT_MIB_RX_CTRL_DROP (MT7530_MIB_COUNTER + 0xb0) +#define MT7530_PORT_MIB_RX_INGRESS_DROP (MT7530_MIB_COUNTER + 0xb4) +#define MT7530_PORT_MIB_RX_ARL_DROP (MT7530_MIB_COUNTER + 0xb8) #define MT7530_MIB_CCR 0x4fe0 #define CCR_MIB_ENABLE BIT(31) #define CCR_RX_OCT_CNT_GOOD BIT(7) @@ -794,45 +709,6 @@ enum mt7531_xtal_fsel { #define REG_GSWCK_EN BIT(0) #define REG_TRGMIICK_EN BIT(1) =20 -#define MIB_DESC(_s, _o, _n) \ - { \ - .size =3D (_s), \ - .offset =3D (_o), \ - .name =3D (_n), \ - } - -struct mt7530_mib_desc { - unsigned int size; - unsigned int offset; - const char *name; -}; - -struct mt7530_fdb { - u16 vid; - u8 port_mask; - u8 aging; - u8 mac[6]; - bool noarp; -}; - -/* struct mt7530_port - This is the main data structure for holding the st= ate - * of the port. - * @enable: The status used for show port is enabled or not. - * @pm: The matrix used to show all connections with the port. - * @pvid: The VLAN specified is to be considered a PVID at ingress. Any - * untagged frames will be assigned to the related VLAN. - * @sgmii_pcs: Pointer to PCS instance for SerDes ports - * @stats: Cached port statistics for MDIO-connected switches - */ -struct mt7530_port { - bool enable; - bool isolated; - u32 pm; - u16 pvid; - struct phylink_pcs *sgmii_pcs; - struct rtnl_link_stats64 stats; -}; - /* Port 5 mode definitions of the MT7530 switch */ enum mt7530_p5_mode { GMAC5, @@ -864,6 +740,9 @@ struct mt753x_pcs { struct mt753x_info { enum mt753x_id id; =20 + const struct mt7530_reg_field *reg_fields; + unsigned int num_reg_fields; + const struct phylink_pcs_ops *pcs_ops; =20 int (*sw_setup)(struct dsa_switch *ds); @@ -921,8 +800,6 @@ struct mt7530_priv { bool mcm; enum mt7530_p5_mode p5_mode; bool p5_sgmii; - u8 mirror_rx; - u8 mirror_tx; struct mt7530_port ports[MT7530_NUM_PORTS]; struct mt753x_pcs pcs[MT7530_NUM_PORTS]; /* protect among processes for registers access*/ @@ -934,24 +811,10 @@ struct mt7530_priv { spinlock_t stats_lock; /* protects cached stats counters */ struct delayed_work stats_work; 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[82.57.191.234]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-48af071532dsm1527706f8f.20.2026.09.28.12.46.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 12:46:17 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean , Matthias Brugger , AngeloGioacchino Del Regno , "Chester A. Unal" , Daniel Golle , Heiner Kallweit , Russell King , Simon Horman , Joris Vaisvila , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andrew Lunn Subject: [PATCH net-next v24 10/10] net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver Date: Mon, 28 Sep 2026 21:45:09 +0200 Message-ID: <20260928194511.41878-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260928194511.41878-1-ansuelsmth@gmail.com> References: <20260928194511.41878-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Airoha AN8855 5-Port Gigabit DSA switch. Switch can support 10M, 100M, 1Gb, 2.5G and 5G Ethernet Speed but 5G is currently error out as it's not currently supported as requires additional configuration for the PCS. Reviewed-by: Andrew Lunn Signed-off-by: Christian Marangi --- drivers/net/dsa/mediatek/Kconfig | 10 + drivers/net/dsa/mediatek/Makefile | 1 + drivers/net/dsa/mediatek/an8855.c | 1741 +++++++++++++++++++++++++ drivers/net/dsa/mediatek/an8855.h | 755 +++++++++++ drivers/net/dsa/mediatek/mt7530-lib.c | 68 +- drivers/net/dsa/mediatek/mt7530-lib.h | 22 + 6 files changed, 2577 insertions(+), 20 deletions(-) create mode 100644 drivers/net/dsa/mediatek/an8855.c create mode 100644 drivers/net/dsa/mediatek/an8855.h diff --git a/drivers/net/dsa/mediatek/Kconfig b/drivers/net/dsa/mediatek/Kc= onfig index 7b48300dca0c..2799e78a8651 100644 --- a/drivers/net/dsa/mediatek/Kconfig +++ b/drivers/net/dsa/mediatek/Kconfig @@ -1,4 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only +config NET_DSA_AN8855 + tristate "Airoha AN8855 Ethernet switch support" + depends on MFD_AIROHA_AN8855 || COMPILE_TEST + depends on NET_DSA + select NET_DSA_MT7530_LIB + select NET_DSA_TAG_AIROHA + help + This enables support for the Ethernet switch inside the + Airoha AN8855 chip. + config NET_DSA_MT7530_LIB tristate =20 diff --git a/drivers/net/dsa/mediatek/Makefile b/drivers/net/dsa/mediatek/M= akefile index b2c0693dbb58..60e5f5cd0901 100644 --- a/drivers/net/dsa/mediatek/Makefile +++ b/drivers/net/dsa/mediatek/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_NET_DSA_AN8855) +=3D an8855.o obj-$(CONFIG_NET_DSA_MT7530) +=3D mt7530.o obj-$(CONFIG_NET_DSA_MT7530_LIB) +=3D mt7530-lib.o obj-$(CONFIG_NET_DSA_MT7530_MDIO) +=3D mt7530-mdio.o diff --git a/drivers/net/dsa/mediatek/an8855.c b/drivers/net/dsa/mediatek/a= n8855.c new file mode 100644 index 000000000000..b4b02b7cb6eb --- /dev/null +++ b/drivers/net/dsa/mediatek/an8855.c @@ -0,0 +1,1741 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Airoha AN8855 DSA Switch driver + * Copyright (C) 2023 Min Yao + * Copyright (C) 2024 Christian Marangi + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "an8855.h" +#include "mt7530-lib.h" + +static const struct mt7530_reg_field an8855_fields[] =3D { + { MT7530_BC_FFP, REG_FIELD(AN8855_BCF, 0, 7) }, + { MT7530_UNM_FFP, REG_FIELD(AN8855_UNMF, 0, 7) }, + { MT7530_UNU_FFP, REG_FIELD(AN8855_UNUF, 0, 7) }, + + { MT7530_CCR_MIB_ENABLE, REG_FIELD(AN8855_MIB_CCR, 31, 31) }, + { MT7530_CCR_RX_OCT_CNT_GOOD, REG_FIELD(AN8855_MIB_CCR, 7, 7) }, + { MT7530_CCR_RX_OCT_CNT_BAD, REG_FIELD(AN8855_MIB_CCR, 6, 6) }, + { MT7530_CCR_TX_OCT_CNT_GOOD, REG_FIELD(AN8855_MIB_CCR, 5, 5) }, + { MT7530_CCR_TX_OCT_CNT_BAD, REG_FIELD(AN8855_MIB_CCR, 4, 4) }, + + { MT7530_BPDU_EG_TAG, REG_FIELD(AN8855_BPC, 9, 11) }, + { MT7530_BPDU_PORT_FW, REG_FIELD(AN8855_BPC, 0, 2) }, + { MT7530_PAE_BPDU_FR, REG_FIELD(AN8855_PAC, 28, 28) }, + { MT7530_PAE_EG_TAG, REG_FIELD(AN8855_PAC, 25, 27) }, + { MT7530_PAE_PORT_FW, REG_FIELD(AN8855_PAC, 16, 18) }, + { MT7530_R01_BPDU_FR, REG_FIELD(AN8855_RGAC1, 12, 12) }, + { MT7530_R01_EG_TAG, REG_FIELD(AN8855_RGAC1, 9, 11) }, + { MT7530_R01_PORT_FW, REG_FIELD(AN8855_RGAC1, 0, 2) }, + { MT7530_R02_BPDU_FR, REG_FIELD(AN8855_RGAC1, 28, 28) }, + { MT7530_R02_EG_TAG, REG_FIELD(AN8855_RGAC1, 25, 27) }, + { MT7530_R02_PORT_FW, REG_FIELD(AN8855_RGAC1, 16, 18) }, + { MT7530_R03_BPDU_FR, REG_FIELD(AN8855_RGAC2, 12, 12) }, + { MT7530_R03_EG_TAG, REG_FIELD(AN8855_RGAC2, 9, 11) }, + { MT7530_R03_PORT_FW, REG_FIELD(AN8855_RGAC2, 0, 2) }, + { MT7530_R0E_BPDU_FR, REG_FIELD(AN8855_RGAC2, 28, 28) }, + { MT7530_R0E_EG_TAG, REG_FIELD(AN8855_RGAC2, 25, 27) }, + { MT7530_R0E_PORT_FW, REG_FIELD(AN8855_RGAC2, 16, 18) }, + + { MT7530_VAWD_IVL_MAC, REG_FIELD(AN8855_VAWD0, 5, 5) }, + { MT7530_VAWD_EG_CON, REG_FIELD(AN8855_VAWD0, 11, 11) }, + { MT7530_VAWD_VTAG_EN, REG_FIELD(AN8855_VAWD0, 10, 10) }, + { MT7530_VAWD_PORT_MEM, REG_FIELD(AN8855_VAWD0, 26, 31) }, + { MT7530_VAWD_FID, REG_FIELD(AN8855_VAWD0, 1, 4) }, + { MT7530_VAWD_VLAN_VALID, REG_FIELD(AN8855_VAWD0, 0, 0) }, + { __MT7530_VAWD1, REG_FIELD(AN8855_VAWD0, 0, 31) }, + + { MT7530_VAWD_ETAG, REG_FIELD(AN8855_VAWD0, 12, 23) }, + { __MT7530_VAWD2, REG_FIELD(AN8855_VAWD1, 0, 31) }, + + { MT7530_VTCR_BUSY, REG_FIELD(AN8855_VTCR, 31, 31) }, + { MT7530_VTCR_FUNC, REG_FIELD(AN8855_VTCR, 12, 15) }, + { MT7530_VTCR_VID, REG_FIELD(AN8855_VTCR, 0, 11) }, + + { MT7530_ATWD_CVID, REG_FIELD(AN8855_ATWD, 16, 27), }, + { MT7530_ATWD_IVL, REG_FIELD(AN8855_ATWD, 15, 15), }, + { MT7530_ATWD_FID, REG_FIELD(AN8855_ATWD, 28, 31), }, + { MT7530_ATWD_AGE_TIMER, REG_FIELD(AN8855_ATA2, 0, 8), }, + { MT7530_ATWD_PORT_MAP, REG_FIELD(AN8855_ATWD2, 0, 7), }, + { AN8855_ATWD_TYPE, REG_FIELD(AN8855_ATA2, 9, 9), }, + { AN8855_ATWD_VLD, REG_FIELD(AN8855_ATWD, 0, 0), }, + { MT7530_ATWD_MAC_BYTE_5, REG_FIELD(AN8855_ATA2, 16, 23), }, + { MT7530_ATWD_MAC_BYTE_4, REG_FIELD(AN8855_ATA2, 24, 31), }, + { MT7530_ATWD_MAC_BYTE_3, REG_FIELD(AN8855_ATA1, 0, 7), }, + { MT7530_ATWD_MAC_BYTE_2, REG_FIELD(AN8855_ATA1, 8, 15), }, + { MT7530_ATWD_MAC_BYTE_1, REG_FIELD(AN8855_ATA1, 16, 23), }, + { MT7530_ATWD_MAC_BYTE_0, REG_FIELD(AN8855_ATA1, 24, 31), }, + + { __MT7530_ATWD1, REG_FIELD(AN8855_ATWD, 0, 31), }, + { __MT7530_ATWD2, REG_FIELD(AN8855_ATWD2, 0, 31), }, + { __MT7530_ATWD3, REG_FIELD(AN8855_ATA1, 0, 31), }, + { __MT7530_ATWD4, REG_FIELD(AN8855_ATA2, 0, 31), }, + + { MT7530_ATRD_CVID, REG_FIELD(AN8855_ATRD0, 10, 21), }, + { MT7530_ATRD_AGE_TIMER, REG_FIELD(AN8855_ATRD1, 3, 11), }, + { MT7530_ATRD_PORT_MAP, REG_FIELD(AN8855_ATRD3, 0, 7), }, + { AN8855_ATRD_ARP, REG_FIELD(AN8855_ATRD0, 1, 2), }, + { MT7530_ATRD_MAC_BYTE_5, REG_FIELD(AN8855_ATRD1, 16, 23), }, + { MT7530_ATRD_MAC_BYTE_4, REG_FIELD(AN8855_ATRD1, 24, 31), }, + { MT7530_ATRD_MAC_BYTE_3, REG_FIELD(AN8855_ATRD2, 0, 7), }, + { MT7530_ATRD_MAC_BYTE_2, REG_FIELD(AN8855_ATRD2, 8, 15), }, + { MT7530_ATRD_MAC_BYTE_1, REG_FIELD(AN8855_ATRD2, 16, 23), }, + { MT7530_ATRD_MAC_BYTE_0, REG_FIELD(AN8855_ATRD2, 24, 31), }, + + { MT7530_ATC_BUSY, REG_FIELD(AN8855_ATC, 31, 31), }, + { MT7530_ATC_MAT, REG_FIELD(AN8855_ATC, 7, 11), }, + { MT7530_ATC_CMD, REG_FIELD(AN8855_ATC, 0, 2), }, + { __MT7530_ATC, REG_FIELD(AN8855_ATC, 0, 31), }, + + { MT7530_MIRROR_EN, REG_FIELD(AN8855_MIR, 7, 7) }, + { MT7530_MIRROR_PORT, REG_FIELD(AN8855_MIR, 0, 4) }, + + { MT7530_SSP_FID_PST, REG_FIELD_ID(AN8855_SSP, 0, 15, AN8855_NUM_PORTS, 0= x200) }, + + { MT7530_PCR_PORT_TX_MIR, REG_FIELD_ID(AN8855_PCR, 20, 20, AN8855_NUM_POR= TS, 0x200) }, + { MT7530_PCR_PORT_RX_MIR, REG_FIELD_ID(AN8855_PCR, 16, 16, AN8855_NUM_POR= TS, 0x200) }, + { MT7530_PCR_PORT_VLAN, REG_FIELD_ID(AN8855_PCR, 0, 1, AN8855_NUM_PORTS, = 0x200) }, + + { MT7530_PCR_MATRIX, REG_FIELD_ID(AN8855_PORTMATRIX, 0, 5, AN8855_NUM_POR= TS, 0x200) }, + + { MT7530_PSC_SA_DIS, REG_FIELD_ID(AN8855_PSC, 4, 4, AN8855_NUM_PORTS, 0x2= 00) }, + + { MT7530_PVC_EG_TAG, REG_FIELD_ID(AN8855_PVC, 8, 10, AN8855_NUM_PORTS, 0x= 200) }, + { MT7530_PVC_VLAN_ATTR, REG_FIELD_ID(AN8855_PVC, 6, 7, AN8855_NUM_PORTS, = 0x200) }, + { MT7530_PVC_ACC_FRM, REG_FIELD_ID(AN8855_PVC, 0, 1, AN8855_NUM_PORTS, 0x= 200) }, + + { MT7530_PPBV1_G0_PORT_VID, REG_FIELD_ID(AN8855_PPBV1, 0, 11, AN8855_NUM_= PORTS, 0x200) }, + { AN8855_PVID_G0_PORT_VID, REG_FIELD_ID(AN8855_PVID, 0, 11, AN8855_NUM_PO= RTS, 0x200) }, + + { MT7530_GMACCR_MAX_RX_JUMBO, REG_FIELD(AN8855_GMACCR, 4, 7) }, + { MT7530_GMACCR_MAX_RX_PKT_LEN, REG_FIELD(AN8855_GMACCR, 0, 1) }, + + { MT7530_MIB_TX_DROP, REG_FIELD_ID(AN8855_PORT_MIB_TX_DROP, 0, 31, AN8855= _NUM_PORTS, 0x200) }, + { MT7530_MIB_TX_CRC_ERR, REG_FIELD_ID(AN8855_PORT_MIB_TX_CRC_ERR, 0, 31, = AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_TX_UNICAST, REG_FIELD_ID(AN8855_PORT_MIB_TX_UNICAST, 0, 31, = AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_TX_MULTICAST, REG_FIELD_ID(AN8855_PORT_MIB_TX_MULTICAST, 0, = 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_TX_BROADCAST, REG_FIELD_ID(AN8855_PORT_MIB_TX_BROADCAST, 0, = 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_TX_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_COLLISION, 0, = 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_TX_SINGLE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_SINGLE_= COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_TX_MULTIPLE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_MULTI= PLE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_TX_DEFERRED, REG_FIELD_ID(AN8855_PORT_MIB_TX_DEFERRED, 0, 31= , AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_TX_LATE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_LATE_COLL= ISION, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_TX_EXCESSIVE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_EXCE= SSIVE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_TX_PAUSE, REG_FIELD_ID(AN8855_PORT_MIB_TX_PAUSE, 0, 31, AN88= 55_NUM_PORTS, 0x200) }, + { MT7530_MIB_TX_PKT_SZ_64, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_64, 0, = 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_TX_PKT_SZ_65_TO_127, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_= 65_TO_127, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_TX_PKT_SZ_128_TO_255, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ= _128_TO_255, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_TX_PKT_SZ_256_TO_511, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ= _256_TO_511, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_TX_PKT_SZ_512_TO_1023, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_S= Z_512_TO_1023, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { AN8855_MIB_TX_PKT_SZ_1024_TO_1518, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_= SZ_1024_TO_1518, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { AN8855_MIB_TX_PKT_SZ_1519_TO_MAX, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_S= Z_1519_TO_MAX, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_TX_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_TX_BYTES_LOW, 0, = 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_TX_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_TX_BYTES_HIGH, 0= , 31, AN8855_NUM_PORTS, 0x200) }, + { AN8855_MIB_TX_OVERSIZE_DROP, REG_FIELD_ID(AN8855_PORT_MIB_TX_OVERSIZE_D= ROP, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { AN8855_MIB_TX_BAD_PKT_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_TX_BAD_PK= T_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { AN8855_MIB_TX_BAD_PKT_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_TX_BAD_P= KT_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_DROP, 0, 31, AN8855= _NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_FILTERING, REG_FIELD_ID(AN8855_PORT_MIB_RX_FILTERING, 0, = 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_UNICAST, REG_FIELD_ID(AN8855_PORT_MIB_RX_UNICAST, 0, 31, = AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_MULTICAST, REG_FIELD_ID(AN8855_PORT_MIB_RX_MULTICAST, 0, = 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_BROADCAST, REG_FIELD_ID(AN8855_PORT_MIB_RX_BROADCAST, 0, = 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_ALIGN_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_ALIGN_ERR, 0, = 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_CRC_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_CRC_ERR, 0, 31, = AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_UNDER_SIZE_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_UNDER_SIZ= E_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_FRAG_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_FRAG_ERR, 0, 31= , AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_OVER_SZ_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_OVER_SZ_ERR,= 0, 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_JABBER_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_JABBER_ERR, 0= , 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_PAUSE, REG_FIELD_ID(AN8855_PORT_MIB_RX_PAUSE, 0, 31, AN88= 55_NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_PKT_SZ_64, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_64, 0, = 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_PKT_SZ_65_TO_127, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_= 65_TO_127, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_PKT_SZ_128_TO_255, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ= _128_TO_255, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_PKT_SZ_256_TO_511, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ= _256_TO_511, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_PKT_SZ_512_TO_1023, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_S= Z_512_TO_1023, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { AN8855_MIB_RX_PKT_SZ_1024_TO_1518, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_= SZ_1024_TO_1518, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { AN8855_MIB_RX_PKT_SZ_1519_TO_MAX, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_S= Z_1519_TO_MAX, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_RX_BYTES_LOW, 0, = 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_RX_BYTES_HIGH, 0= , 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_CTRL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_CTRL_DROP, 0, = 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_INGRESS_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_INGRESS_DRO= P, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { MT7530_MIB_RX_ARL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_ARL_DROP, 0, 31= , AN8855_NUM_PORTS, 0x200) }, + { AN8855_MIB_FLOW_CONTROL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_FLOW_CONTROL= _DROP, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { AN8855_MIB_WRED_DROP, REG_FIELD_ID(AN8855_PORT_MIB_WRED_DROP, 0, 31, AN= 8855_NUM_PORTS, 0x200) }, + { AN8855_MIB_MIRROR_DROP, REG_FIELD_ID(AN8855_PORT_MIB_MIRROR_DROP, 0, 31= , AN8855_NUM_PORTS, 0x200) }, + { AN8855_MIB_RX_BAD_PKT_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_RX_BAD_PK= T_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { AN8855_MIB_RX_BAD_PKT_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_RX_BAD_P= KT_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { AN8855_MIB_RXS_FLOW_SAMPLING_PKT_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RXS= _FLOW_SAMPLING_PKT_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { AN8855_MIB_RXS_FLOW_TOTAL_PKT_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RXS_FL= OW_TOTAL_PKT_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) }, + { AN8855_MIB_PORT_CONTROL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_PORT_CONTROL= _DROP, 0, 31, AN8855_NUM_PORTS, 0x200) }, +}; + +static const struct mt7530_mib_desc an8855_mib[] =3D { + MIB_DESC(MT7530_MIB_TX_DROP, -1, "TxDrop"), + MIB_DESC(MT7530_MIB_TX_CRC_ERR, -1, "TxCrcErr"), + MIB_DESC(MT7530_MIB_TX_COLLISION, -1, "TxCollision"), + MIB_DESC(AN8855_MIB_TX_OVERSIZE_DROP, -1, "TxOversizeDrop"), + MIB_DESC(AN8855_MIB_TX_BAD_PKT_BYTES_LOW, + AN8855_MIB_TX_BAD_PKT_BYTES_HIGH, "TxBadPktBytes"), + MIB_DESC(MT7530_MIB_RX_DROP, -1, "RxDrop"), + MIB_DESC(MT7530_MIB_RX_FILTERING, -1, "RxFiltering"), + MIB_DESC(MT7530_MIB_RX_CRC_ERR, -1, "RxCrcErr"), + MIB_DESC(MT7530_MIB_RX_CTRL_DROP, -1, "RxCtrlDrop"), + MIB_DESC(MT7530_MIB_RX_INGRESS_DROP, -1, "RxIngressDrop"), + MIB_DESC(MT7530_MIB_RX_ARL_DROP, -1, "RxArlDrop"), + MIB_DESC(AN8855_MIB_FLOW_CONTROL_DROP, -1, "FlowControlDrop"), + MIB_DESC(AN8855_MIB_WRED_DROP, -1, "WredDrop"), + MIB_DESC(AN8855_MIB_MIRROR_DROP, -1, "MirrorDrop"), + MIB_DESC(AN8855_MIB_RX_BAD_PKT_BYTES_LOW, + AN8855_MIB_RX_BAD_PKT_BYTES_HIGH, "RxBadPktBytes"), + MIB_DESC(AN8855_MIB_RXS_FLOW_SAMPLING_PKT_DROP, -1, "RxsFlowSamplingPktDr= op"), + MIB_DESC(AN8855_MIB_RXS_FLOW_TOTAL_PKT_DROP, -1, "RxsFlowTotalPktDrop"), + MIB_DESC(AN8855_MIB_PORT_CONTROL_DROP, -1, "PortControlDrop"), +}; + +static void +an8855_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) +{ + struct dsa_port *dp =3D dsa_to_port(ds, port); + struct an8855_priv *priv =3D ds->priv; + bool learning =3D false; + int ret; + + mt7530_lib_stp_state_set(&priv->lib_priv, port, state); + + switch (state) { + case BR_STATE_LEARNING: + case BR_STATE_FORWARDING: + learning =3D dp->learning; + fallthrough; + default: + break; + } + + ret =3D regmap_update_bits(priv->regmap, AN8855_PSC_P(port), AN8855_SA_DI= S, + learning ? 0 : AN8855_SA_DIS); + if (ret) + dev_err(priv->ds->dev, "failed to update learn reg: %d\n", ret); +} + +static void an8855_port_fast_age(struct dsa_switch *ds, int port) +{ + struct an8855_priv *priv =3D ds->priv; + int ret; + + mutex_lock(&priv->reg_mutex); + + /* Set to clean Dynamic entry */ + ret =3D regmap_write(priv->regmap, AN8855_ATA2, AN8855_ATA2_TYPE); + if (ret) { + dev_err(priv->ds->dev, "failed to update ATA2 reg: %d\n", ret); + goto exit; + } + + /* Set Port */ + ret =3D regmap_write(priv->regmap, AN8855_ATWD2, + FIELD_PREP(AN8855_ATWD2_PORT, BIT(port))); + if (ret) { + dev_err(priv->ds->dev, "failed to update ATWD2 reg: %d\n", ret); + goto exit; + } + + /* Flush Dynamic entry at port */ + ret =3D mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_FLUSH, + AN8855_FDB_MAT_MAC_TYPE_PORT, NULL); + if (ret) + dev_err(priv->ds->dev, "failed to send FDB cmd: %d\n", ret); + +exit: + mutex_unlock(&priv->reg_mutex); +} + +static int an8855_port_pre_bridge_flags(struct dsa_switch *ds, int port, + struct switchdev_brport_flags flags, + struct netlink_ext_ack *extack) +{ + if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | + BR_BCAST_FLOOD | BR_ISOLATED)) + return -EINVAL; + + return 0; +} + +static int an8855_port_bridge_flags(struct dsa_switch *ds, int port, + struct switchdev_brport_flags flags, + struct netlink_ext_ack *extack) +{ + struct an8855_priv *priv =3D ds->priv; + + return mt7530_lib_port_bridge_flags(&priv->lib_priv, port, flags, + extack); +} + +static int an8855_set_ageing_time(struct dsa_switch *ds, unsigned int msec= s) +{ + struct an8855_priv *priv =3D ds->priv; + u32 age_count, age_unit, val; + + /* Convert msec in AN8855_L2_AGING_MS_CONSTANT counter */ + val =3D msecs / AN8855_L2_AGING_MS_CONSTANT; + + /* Derive the count unit */ + age_unit =3D DIV_ROUND_UP(val, FIELD_MAX(AN8855_AGE_CNT) + 1) - 1; + if (age_unit > FIELD_MAX(AN8855_AGE_UNIT)) + age_unit =3D FIELD_MAX(AN8855_AGE_UNIT); + + /* Get the count in unit, age_unit is always incremented by 1 internally = */ + age_count =3D DIV_ROUND_UP(val, age_unit + 1) - 1; + + return regmap_update_bits(priv->regmap, AN8855_AAC, + AN8855_AGE_CNT | AN8855_AGE_UNIT, + FIELD_PREP(AN8855_AGE_CNT, age_count) | + FIELD_PREP(AN8855_AGE_UNIT, age_unit)); +} + +static int an8855_port_bridge_join(struct dsa_switch *ds, int port, + struct dsa_bridge bridge, + bool *tx_fwd_offload, + struct netlink_ext_ack *extack) +{ + struct an8855_priv *priv =3D ds->priv; + + return mt7530_lib_port_bridge_join(&priv->lib_priv, port, bridge, + tx_fwd_offload, extack); +} + +static void an8855_port_bridge_leave(struct dsa_switch *ds, int port, + struct dsa_bridge bridge) +{ + struct an8855_priv *priv =3D ds->priv; + + return mt7530_lib_port_bridge_leave(&priv->lib_priv, port, bridge); +} + +static int an8855_port_fdb_add(struct dsa_switch *ds, int port, + const unsigned char *addr, u16 vid, + struct dsa_db db) +{ + struct an8855_priv *priv =3D ds->priv; + + return mt7530_lib_port_fdb_add(&priv->lib_priv, port, addr, vid, db); +} + +static int an8855_port_fdb_del(struct dsa_switch *ds, int port, + const unsigned char *addr, u16 vid, + struct dsa_db db) +{ + struct an8855_priv *priv =3D ds->priv; + + return mt7530_lib_port_fdb_del(&priv->lib_priv, port, addr, vid, db); +} + +static int an8855_port_fdb_dump(struct dsa_switch *ds, int port, + dsa_fdb_dump_cb_t *cb, void *data) +{ + struct an8855_priv *priv =3D ds->priv; + int banks, count =3D 0; + u32 rsp; + int ret; + int i; + + mutex_lock(&priv->reg_mutex); + + /* Load search port */ + ret =3D regmap_write(priv->regmap, AN8855_ATWD2, + FIELD_PREP(AN8855_ATWD2_PORT, BIT(port))); + if (ret) + goto exit; + ret =3D mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_START, + AN8855_FDB_MAT_MAC_PORT, &rsp); + if (ret < 0) + goto exit; + + do { + /* From response get the number of banks to read, exit if 0 */ + banks =3D FIELD_GET(AN8855_ATC_HIT, rsp); + if (!banks) + break; + + /* Each banks have 4 entry */ + for (i =3D 0; i < 4; i++) { + struct mt7530_fdb _fdb =3D { }; + + count++; + + /* Check if bank is present */ + if (!(banks & BIT(i))) + continue; + + /* Select bank entry index */ + ret =3D regmap_write(priv->regmap, AN8855_ATRDS, + FIELD_PREP(AN8855_ATRD_SEL, i)); + if (ret) + break; + /* wait 1ms for the bank entry to be filled */ + usleep_range(1000, 1500); + mt7530_lib_fdb_read(&priv->lib_priv, &_fdb); + + ret =3D cb(_fdb.mac, _fdb.vid, _fdb.noarp, data); + if (ret < 0) + break; + } + + /* Stop if reached max FDB number */ + if (ret < 0 || count >=3D AN8855_NUM_FDB_RECORDS) + break; + + /* Read next bank */ + ret =3D mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_NEXT, + AN8855_FDB_MAT_MAC_PORT, &rsp); + if (ret < 0) + break; + } while (true); + +exit: + mutex_unlock(&priv->reg_mutex); + return ret; +} + +static int an8855_port_vlan_filtering(struct dsa_switch *ds, int port, + bool vlan_filtering, + struct netlink_ext_ack *extack) +{ + struct an8855_priv *priv =3D ds->priv; + + return mt7530_lib_port_vlan_filtering(&priv->lib_priv, port, + vlan_filtering, + extack); +} + +static int an8855_port_vlan_add(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan, + struct netlink_ext_ack *extack) +{ + struct an8855_priv *priv =3D ds->priv; + + return mt7530_lib_port_vlan_add(&priv->lib_priv, port, vlan, extack); +} + +static int an8855_port_vlan_del(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan) +{ + struct an8855_priv *priv =3D ds->priv; + + return mt7530_lib_port_vlan_del(&priv->lib_priv, port, vlan); +} + +static int an8855_port_mdb_add(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_mdb *mdb, + struct dsa_db db) +{ + struct an8855_priv *priv =3D ds->priv; + + return mt7530_lib_port_mdb_add(&priv->lib_priv, port, mdb, db); +} + +static int an8855_port_mdb_del(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_mdb *mdb, + struct dsa_db db) +{ + struct an8855_priv *priv =3D ds->priv; + + return mt7530_lib_port_mdb_del(&priv->lib_priv, port, mdb, db); +} + +static int an8855_port_change_mtu(struct dsa_switch *ds, int port, + int new_mtu) +{ + struct an8855_priv *priv =3D ds->priv; + + return mt7530_lib_port_change_mtu(&priv->lib_priv, port, new_mtu); +} + +static int an8855_port_max_mtu(struct dsa_switch *ds, int port) +{ + return AN8855_MAX_MTU; +} + +static void an8855_get_strings(struct dsa_switch *ds, int port, + u32 stringset, uint8_t *data) +{ + int i; + + if (stringset !=3D ETH_SS_STATS) + return; + + for (i =3D 0; i < ARRAY_SIZE(an8855_mib); i++) + ethtool_puts(&data, an8855_mib[i].name); +} + +static void an8855_get_ethtool_stats(struct dsa_switch *ds, int port, + uint64_t *data) +{ + struct an8855_priv *priv =3D ds->priv; + const struct mt7530_mib_desc *mib; + struct mt7530_lib_priv *lib_priv; + int i; + + lib_priv =3D &priv->lib_priv; + for (i =3D 0; i < ARRAY_SIZE(an8855_mib); i++) { + struct regmap_field *high =3D NULL; + + mib =3D &an8855_mib[i]; + if (mib->field_high !=3D -1) + high =3D lib_priv->fields[mib->field_high]; + + mt7530_lib_read_port_stats(lib_priv->fields[mib->field_low], + high, port, data + i); + } +} + +static int an8855_get_sset_count(struct dsa_switch *ds, int port, + int sset) +{ + if (sset !=3D ETH_SS_STATS) + return -EOPNOTSUPP; + + return ARRAY_SIZE(an8855_mib); +} + +static void an8855_get_eth_mac_stats(struct dsa_switch *ds, int port, + struct ethtool_eth_mac_stats *mac_stats) +{ + struct an8855_priv *priv =3D ds->priv; + + return mt7530_lib_get_eth_mac_stats(&priv->lib_priv, port, mac_stats); +} + +static const struct ethtool_rmon_hist_range an8855_rmon_ranges[] =3D { + { 0, 64 }, + { 65, 127 }, + { 128, 255 }, + { 256, 511 }, + { 512, 1023 }, + { 1024, 1518 }, + { 1519, AN8855_MAX_MTU }, + {} +}; + +static const struct mt7530_rmon_hist an8855_rmon_hist_info =3D { + .ranges_fields =3D (unsigned int []){ + MT7530_MIB_RX_PKT_SZ_64, + MT7530_MIB_RX_PKT_SZ_65_TO_127, + MT7530_MIB_RX_PKT_SZ_128_TO_255, + MT7530_MIB_RX_PKT_SZ_256_TO_511, + MT7530_MIB_RX_PKT_SZ_512_TO_1023, + AN8855_MIB_RX_PKT_SZ_1024_TO_1518, + AN8855_MIB_RX_PKT_SZ_1519_TO_MAX, + }, + .ranges_tx_fields =3D (unsigned int []){ + MT7530_MIB_TX_PKT_SZ_64, + MT7530_MIB_TX_PKT_SZ_65_TO_127, + MT7530_MIB_TX_PKT_SZ_128_TO_255, + MT7530_MIB_TX_PKT_SZ_256_TO_511, + MT7530_MIB_TX_PKT_SZ_512_TO_1023, + AN8855_MIB_TX_PKT_SZ_1024_TO_1518, + AN8855_MIB_TX_PKT_SZ_1519_TO_MAX, + }, + .ranges =3D an8855_rmon_ranges, + .num_ranges =3D ARRAY_SIZE(an8855_rmon_ranges) - 1, +}; + +static void an8855_get_rmon_stats(struct dsa_switch *ds, int port, + struct ethtool_rmon_stats *rmon_stats, + const struct ethtool_rmon_hist_range **ranges) +{ + struct an8855_priv *priv =3D ds->priv; + + return mt7530_lib_get_rmon_stats(&priv->lib_priv, port, rmon_stats, range= s, + &an8855_rmon_hist_info); +} + +static void an8855_get_eth_ctrl_stats(struct dsa_switch *ds, int port, + struct ethtool_eth_ctrl_stats *ctrl_stats) +{ + struct an8855_priv *priv =3D ds->priv; + + mt7530_lib_get_eth_ctrl_stats(&priv->lib_priv, port, ctrl_stats); +} + +static int an8855_port_mirror_add(struct dsa_switch *ds, int port, + struct dsa_mall_mirror_tc_entry *mirror, + bool ingress, + struct netlink_ext_ack *extack) +{ + struct an8855_priv *priv =3D ds->priv; + + return mt7530_lib_port_mirror_add(&priv->lib_priv, port, mirror, ingress,= extack); +} + +static void an8855_port_mirror_del(struct dsa_switch *ds, int port, + struct dsa_mall_mirror_tc_entry *mirror) +{ + struct an8855_priv *priv =3D ds->priv; + + mt7530_lib_port_mirror_del(&priv->lib_priv, port, mirror); +} + +static int an8855_port_enable(struct dsa_switch *ds, int port, + struct phy_device *phy) +{ + struct an8855_priv *priv =3D ds->priv; + int ret; + + mutex_lock(&priv->reg_mutex); + priv->ports[port].enable =3D true; + ret =3D regmap_set_bits(priv->regmap, AN8855_PMCR_P(port), + AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN); + mutex_unlock(&priv->reg_mutex); + + return ret; +} + +static void an8855_port_disable(struct dsa_switch *ds, int port) +{ + struct an8855_priv *priv =3D ds->priv; + int ret; + + mutex_lock(&priv->reg_mutex); + priv->ports[port].enable =3D false; + ret =3D regmap_clear_bits(priv->regmap, AN8855_PMCR_P(port), + AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN); + mutex_unlock(&priv->reg_mutex); + if (ret) + dev_err(priv->ds->dev, "failed to disable port: %d\n", ret); +} + +static int an8855_set_mac_eee(struct dsa_switch *ds, int port, + struct ethtool_keee *e) +{ + if (e->tx_lpi_timer > 0xFFF) + return -EINVAL; + + return 0; +} + +static enum dsa_tag_protocol an8855_get_tag_protocol(struct dsa_switch *ds, + int port, + enum dsa_tag_protocol mp) +{ + return DSA_TAG_PROTO_AIROHA; +} + +static int an8855_setup(struct dsa_switch *ds) +{ + struct an8855_priv *priv =3D ds->priv; + struct dsa_port *dp; + int ret; + + /* Enable and reset MIB counters */ + mt7530_lib_mib_reset(&priv->lib_priv); + + dsa_switch_for_each_user_port(dp, ds) { + /* Disable MAC by default on all user ports */ + an8855_port_disable(ds, dp->index); + + /* Individual user ports get connected to CPU port only */ + ret =3D regmap_write(priv->regmap, AN8855_PORTMATRIX_P(dp->index), + FIELD_PREP(AN8855_PORTMATRIX_MASK, BIT(AN8855_CPU_PORT))); + if (ret) + return ret; + + /* Disable Broadcast Forward on user ports */ + ret =3D regmap_clear_bits(priv->regmap, AN8855_BCF, BIT(dp->index)); + if (ret) + return ret; + + /* Disable Unknown Unicast Forward on user ports */ + ret =3D regmap_clear_bits(priv->regmap, AN8855_UNUF, BIT(dp->index)); + if (ret) + return ret; + + /* Disable Unknown Multicast Forward on user ports */ + ret =3D regmap_clear_bits(priv->regmap, AN8855_UNMF, BIT(dp->index)); + if (ret) + return ret; + + ret =3D regmap_clear_bits(priv->regmap, AN8855_UNIPMF, BIT(dp->index)); + if (ret) + return ret; + + /* Set default PVID to on all user ports */ + mt7530_port_set_pvid(&priv->lib_priv, dp->index, AN8855_PORT_VID_DEFAULT= ); + } + + /* Enable Airoha header mode on the cpu port */ + ret =3D regmap_write(priv->regmap, AN8855_PVC_P(AN8855_CPU_PORT), + AN8855_PORT_SPEC_REPLACE_MODE | AN8855_PORT_SPEC_TAG); + if (ret) + return ret; + + /* Unknown multicast frame forwarding to the cpu port */ + ret =3D regmap_write(priv->regmap, AN8855_UNMF, BIT(AN8855_CPU_PORT)); + if (ret) + return ret; + + /* Set CPU port number */ + ret =3D regmap_update_bits(priv->regmap, AN8855_MFC, + AN8855_CPU_EN | AN8855_CPU_PORT_IDX, + AN8855_CPU_EN | + FIELD_PREP(AN8855_CPU_PORT_IDX, AN8855_CPU_PORT)); + if (ret) + return ret; + + /* CPU port gets connected to all user ports of + * the switch. + */ + ret =3D regmap_write(priv->regmap, AN8855_PORTMATRIX_P(AN8855_CPU_PORT), + FIELD_PREP(AN8855_PORTMATRIX_MASK, dsa_user_ports(ds))); + if (ret) + return ret; + + /* CPU port is set to fallback mode to let untagged + * frames pass through. + */ + ret =3D regmap_update_bits(priv->regmap, AN8855_PCR_P(AN8855_CPU_PORT), + AN8855_PORT_VLAN, + FIELD_PREP(AN8855_PORT_VLAN, AN8855_PORT_FALLBACK_MODE)); + if (ret) + return ret; + + /* Enable Broadcast Forward on CPU port */ + ret =3D regmap_set_bits(priv->regmap, AN8855_BCF, BIT(AN8855_CPU_PORT)); + if (ret) + return ret; + + /* Enable Unknown Unicast Forward on CPU port */ + ret =3D regmap_set_bits(priv->regmap, AN8855_UNUF, BIT(AN8855_CPU_PORT)); + if (ret) + return ret; + + /* Enable Unknown Multicast Forward on CPU port */ + ret =3D regmap_set_bits(priv->regmap, AN8855_UNMF, BIT(AN8855_CPU_PORT)); + if (ret) + return ret; + + ret =3D regmap_set_bits(priv->regmap, AN8855_UNIPMF, BIT(AN8855_CPU_PORT)= ); + if (ret) + return ret; + + /* Setup Trap special frame to CPU rules */ + mt7530_lib_trap_frames(&priv->lib_priv); + + dsa_switch_for_each_port(dp, ds) { + /* Disable Learning on all ports. + * Learning on CPU is disabled for fdb isolation and handled by + * assisted_learning_on_cpu_port. + */ + ret =3D regmap_set_bits(priv->regmap, AN8855_PSC_P(dp->index), + AN8855_SA_DIS); + if (ret) + return ret; + + /* Enable consistent egress tag (for VLAN unware VLAN-passthrough) */ + ret =3D regmap_update_bits(priv->regmap, AN8855_PVC_P(dp->index), + AN8855_PVC_EG_TAG, + FIELD_PREP(AN8855_PVC_EG_TAG, AN8855_VLAN_EG_CONSISTENT)); + if (ret) + return ret; + } + + /* Setup VLAN for Default PVID */ + ret =3D mt7530_lib_setup_vlan0(&priv->lib_priv); + if (ret) + return ret; + + ret =3D regmap_clear_bits(priv->regmap, AN8855_CKGCR, + AN8855_CKG_LNKDN_GLB_STOP | AN8855_CKG_LNKDN_PORT_STOP); + if (ret) + return ret; + + /* Flush the FDB table */ + ret =3D mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_FLUSH, + AN8855_FDB_MAT_ALL, NULL); + if (ret < 0) + return ret; + + /* Set min a max ageing value supported */ + ds->ageing_time_min =3D AN8855_L2_AGING_MS_CONSTANT; + ds->ageing_time_max =3D FIELD_MAX(AN8855_AGE_CNT) * + FIELD_MAX(AN8855_AGE_UNIT) * + AN8855_L2_AGING_MS_CONSTANT; + + /* User reported problem with WiFi roaming and + * ethernet port. Enabling assisted learning fix + * the issue. + */ + ds->assisted_learning_on_cpu_port =3D true; + + return 0; +} + +static struct phylink_pcs *an8855_phylink_mac_select_pcs(struct phylink_co= nfig *config, + phy_interface_t interface) +{ + struct dsa_port *dp =3D dsa_phylink_to_port(config); + struct an8855_priv *priv =3D dp->ds->priv; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_2500BASEX: + return &priv->pcs; + default: + return NULL; + } +} + +static void an8855_phylink_mac_config(struct phylink_config *config, + unsigned int mode, + const struct phylink_link_state *state) +{ + struct dsa_port *dp =3D dsa_phylink_to_port(config); + struct dsa_switch *ds =3D dp->ds; + struct an8855_priv *priv; + int port =3D dp->index; + + priv =3D ds->priv; + + /* Nothing to configure for internal ports */ + if (port !=3D 5) + return; + + mutex_lock(&priv->reg_mutex); + regmap_update_bits(priv->regmap, AN8855_PMCR_P(port), + AN8855_PMCR_IFG_XMIT | AN8855_PMCR_MAC_MODE | + AN8855_PMCR_BACKOFF_EN | AN8855_PMCR_BACKPR_EN, + FIELD_PREP(AN8855_PMCR_IFG_XMIT, 0x1) | + AN8855_PMCR_MAC_MODE | AN8855_PMCR_BACKOFF_EN | + AN8855_PMCR_BACKPR_EN); + mutex_unlock(&priv->reg_mutex); +} + +static void an8855_phylink_get_caps(struct dsa_switch *ds, int port, + struct phylink_config *config) +{ + struct an8855_priv *priv =3D ds->priv; + u32 reg =3D 0; + int ret; + + switch (port) { + case 0: + case 1: + case 2: + case 3: + case 4: + __set_bit(PHY_INTERFACE_MODE_GMII, + config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + config->supported_interfaces); + break; + case 5: + phy_interface_set_rgmii(config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_SGMII, + config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_2500BASEX, + config->supported_interfaces); + break; + } + + config->mac_capabilities =3D MAC_ASYM_PAUSE | MAC_SYM_PAUSE | + MAC_10 | MAC_100 | MAC_1000FD | MAC_2500FD; + + ret =3D regmap_read(priv->regmap, AN8855_CKGCR, ®); + if (ret) + dev_err(ds->dev, "failed to read EEE LPI timer\n"); + + memcpy(config->lpi_interfaces, config->supported_interfaces, + sizeof(config->lpi_interfaces)); + config->lpi_capabilities =3D MAC_100FD | MAC_1000FD; + /* Global LPI TXIDLE Threshold, default 60ms (unit 2us) */ + config->lpi_timer_default =3D FIELD_GET(AN8855_LPI_TXIDLE_THD_MASK, reg) * + AN8855_TX_LPI_UNIT; + + config->eee_enabled_default =3D true; +} + +static void an8855_phylink_mac_link_down(struct phylink_config *config, + unsigned int mode, + phy_interface_t interface) +{ + struct dsa_port *dp =3D dsa_phylink_to_port(config); + struct an8855_priv *priv =3D dp->ds->priv; + + mutex_lock(&priv->reg_mutex); + + /* With autoneg just disable TX/RX else also force link down */ + if (phylink_autoneg_inband(mode)) { + regmap_clear_bits(priv->regmap, AN8855_PMCR_P(dp->index), + AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN); + } else { + regmap_update_bits(priv->regmap, AN8855_PMCR_P(dp->index), + AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN | + AN8855_PMCR_FORCE_MODE | AN8855_PMCR_FORCE_LNK, + AN8855_PMCR_FORCE_MODE); + } + + mutex_unlock(&priv->reg_mutex); +} + +static void an8855_phylink_mac_link_up(struct phylink_config *config, + struct phy_device *phydev, unsigned int mode, + phy_interface_t interface, int speed, + int duplex, bool tx_pause, bool rx_pause) +{ + struct dsa_port *dp =3D dsa_phylink_to_port(config); + struct an8855_priv *priv =3D dp->ds->priv; + int port =3D dp->index; + u32 reg =3D 0; + + mutex_lock(&priv->reg_mutex); + + regmap_read(priv->regmap, AN8855_PMCR_P(port), ®); + if (phylink_autoneg_inband(mode)) { + reg &=3D ~AN8855_PMCR_FORCE_MODE; + } else { + reg |=3D AN8855_PMCR_FORCE_MODE | AN8855_PMCR_FORCE_LNK; + + reg &=3D ~AN8855_PMCR_FORCE_SPEED; + switch (speed) { + case SPEED_10: + reg |=3D AN8855_PMCR_FORCE_SPEED_10; + break; + case SPEED_100: + reg |=3D AN8855_PMCR_FORCE_SPEED_100; + break; + case SPEED_1000: + reg |=3D AN8855_PMCR_FORCE_SPEED_1000; + break; + case SPEED_2500: + reg |=3D AN8855_PMCR_FORCE_SPEED_2500; + break; + case SPEED_5000: + dev_err(priv->ds->dev, "Missing support for 5G speed. Aborting...\n"); + goto exit; + } + + reg &=3D ~AN8855_PMCR_FORCE_FDX; + if (duplex =3D=3D DUPLEX_FULL) + reg |=3D AN8855_PMCR_FORCE_FDX; + + reg &=3D ~AN8855_PMCR_RX_FC_EN; + if (rx_pause || dsa_port_is_cpu(dp)) + reg |=3D AN8855_PMCR_RX_FC_EN; + + reg &=3D ~AN8855_PMCR_TX_FC_EN; + if (tx_pause || dsa_port_is_cpu(dp)) + reg |=3D AN8855_PMCR_TX_FC_EN; + } + + reg |=3D AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN; + + regmap_write(priv->regmap, AN8855_PMCR_P(port), reg); + +exit: + mutex_unlock(&priv->reg_mutex); +} + +static void an8855_phylink_mac_disable_tx_lpi(struct phylink_config *confi= g) +{ + struct dsa_port *dp =3D dsa_phylink_to_port(config); + struct an8855_priv *priv =3D dp->ds->priv; + int port =3D dp->index; + int ret; + + mutex_lock(&priv->reg_mutex); + priv->tx_lpi_timer_ports[port] =3D 0; + ret =3D regmap_clear_bits(priv->regmap, AN8855_PMCR_P(port), + AN8855_PMCR_FORCE_EEE1G | + AN8855_PMCR_FORCE_EEE100); + mutex_unlock(&priv->reg_mutex); + if (ret) + dev_err(dp->ds->dev, "failed to disable EEE for port %d\n", + port); + + ret =3D regmap_clear_bits(priv->regmap, AN8855_PMEEECR_P(port), + AN8855_LPI_MODE_EN); + if (ret) + dev_err(dp->ds->dev, "failed to disable LPI for port %d\n", + port); +} + +static int an8855_phylink_mac_enable_tx_lpi(struct phylink_config *config, + u32 timer, bool tx_clock_stop) +{ + struct an8855_priv *priv; + struct dsa_switch *ds; + struct dsa_port *dp; + int port; + u32 val; + int ret; + + dp =3D dsa_phylink_to_port(config); + port =3D dp->index; + ds =3D dp->ds; + priv =3D ds->priv; + + /* TX LPI timer is global, find the highest timer + * across all port. + * If requested timer is 0, set to enter LPI immediately + * for the single port. + */ + if (timer) { + int i; + + /* Save requested timer and search the highest one */ + mutex_lock(&priv->reg_mutex); + priv->tx_lpi_timer_ports[port] =3D timer; + for (i =3D 0; i < AN8855_NUM_PORTS; i++) { + if (!priv->ports[i].enable) + continue; + + if (i =3D=3D port) + continue; + + if (timer < priv->tx_lpi_timer_ports[i]) + timer =3D priv->tx_lpi_timer_ports[i]; + } + + timer /=3D AN8855_TX_LPI_UNIT; + if (FIELD_FIT(AN8855_LPI_TXIDLE_THD_MASK, timer)) + val =3D FIELD_PREP(AN8855_LPI_TXIDLE_THD_MASK, timer); + else + val =3D AN8855_LPI_TXIDLE_THD_MASK; + + ret =3D regmap_update_bits(priv->regmap, AN8855_CKGCR, + AN8855_LPI_TXIDLE_THD_MASK, val); + mutex_unlock(&priv->reg_mutex); + if (ret) { + dev_err(dp->ds->dev, "failed to set global LPI timer\n"); + return ret; + } + } else { + ret =3D regmap_set_bits(priv->regmap, AN8855_PMEEECR_P(port), + AN8855_LPI_MODE_EN); + if (ret) { + dev_err(dp->ds->dev, "failed to enable LPI for port %d\n", + port); + return ret; + } + } + + mutex_lock(&priv->reg_mutex); + ret =3D regmap_set_bits(priv->regmap, AN8855_PMCR_P(port), + AN8855_PMCR_FORCE_EEE1G | + AN8855_PMCR_FORCE_EEE100); + mutex_unlock(&priv->reg_mutex); + if (ret) + dev_err(dp->ds->dev, "failed to enable EEE for port %d\n", + port); + + return ret; +} + +static unsigned int an8855_pcs_inband_caps(struct phylink_pcs *pcs, + phy_interface_t interface) +{ + /* SGMII can be configured to use inband with AN result */ + if (interface =3D=3D PHY_INTERFACE_MODE_SGMII) + return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; + + /* inband is not supported in 2500-baseX and must be disabled */ + return LINK_INBAND_DISABLE; +} + +static void an8855_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg= _mode, + struct phylink_link_state *state) +{ + struct an8855_priv *priv =3D container_of(pcs, struct an8855_priv, pcs); + u32 val; + int ret; + + ret =3D regmap_read(priv->regmap, AN8855_PMSR_P(AN8855_CPU_PORT), &val); + if (ret < 0) { + state->link =3D false; + return; + } + + state->link =3D !!(val & AN8855_PMSR_LNK); + state->an_complete =3D state->link; + state->duplex =3D (val & AN8855_PMSR_DPX) ? DUPLEX_FULL : + DUPLEX_HALF; + + switch (val & AN8855_PMSR_SPEED) { + case AN8855_PMSR_SPEED_10: + state->speed =3D SPEED_10; + break; + case AN8855_PMSR_SPEED_100: + state->speed =3D SPEED_100; + break; + case AN8855_PMSR_SPEED_1000: + state->speed =3D SPEED_1000; + break; + case AN8855_PMSR_SPEED_2500: + state->speed =3D SPEED_2500; + break; + case AN8855_PMSR_SPEED_5000: + dev_err(priv->ds->dev, "Switch doesn't support 5G speed. Setting Unknown= .\n"); + fallthrough; + default: + state->speed =3D SPEED_UNKNOWN; + break; + } + + if (val & AN8855_PMSR_RX_FC) + state->pause |=3D MLO_PAUSE_RX; + if (val & AN8855_PMSR_TX_FC) + state->pause |=3D MLO_PAUSE_TX; +} + +static int an8855_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mod= e, + phy_interface_t interface, + const unsigned long *advertising, + bool permit_pause_to_mac) +{ + struct an8855_priv *priv =3D container_of(pcs, struct an8855_priv, pcs); + u32 val; + int ret; + + /* TX FIR - improve TX EYE */ + ret =3D regmap_update_bits(priv->regmap, AN8855_INTF_CTRL_10, + AN8855_RG_DA_QP_TX_FIR_C2_SEL | + AN8855_RG_DA_QP_TX_FIR_C2_FORCE | + AN8855_RG_DA_QP_TX_FIR_C1_SEL | + AN8855_RG_DA_QP_TX_FIR_C1_FORCE, + AN8855_RG_DA_QP_TX_FIR_C2_SEL | + FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C2_FORCE, 0x4) | + AN8855_RG_DA_QP_TX_FIR_C1_SEL | + FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C1_FORCE, 0x0)); + if (ret) + return ret; + + if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) + val =3D 0x0; + else + val =3D 0xd; + ret =3D regmap_update_bits(priv->regmap, AN8855_INTF_CTRL_11, + AN8855_RG_DA_QP_TX_FIR_C0B_SEL | + AN8855_RG_DA_QP_TX_FIR_C0B_FORCE, + AN8855_RG_DA_QP_TX_FIR_C0B_SEL | + FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C0B_FORCE, val)); + if (ret) + return ret; + + /* RX CDR - improve RX Jitter Tolerance */ + if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) + val =3D 0x5; + else + val =3D 0x6; + ret =3D regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_BOT_LIM, + AN8855_RG_QP_CDR_LPF_KP_GAIN | + AN8855_RG_QP_CDR_LPF_KI_GAIN, + FIELD_PREP(AN8855_RG_QP_CDR_LPF_KP_GAIN, val) | + FIELD_PREP(AN8855_RG_QP_CDR_LPF_KI_GAIN, val)); + if (ret) + return ret; + + /* PLL */ + if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) + val =3D 0x1; + else + val =3D 0x0; + ret =3D regmap_update_bits(priv->regmap, AN8855_QP_DIG_MODE_CTRL_1, + AN8855_RG_TPHY_SPEED, + FIELD_PREP(AN8855_RG_TPHY_SPEED, val)); + if (ret) + return ret; + + /* PLL - LPF */ + ret =3D regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2, + AN8855_RG_DA_QP_PLL_RICO_SEL_INTF | + AN8855_RG_DA_QP_PLL_FBKSEL_INTF | + AN8855_RG_DA_QP_PLL_BR_INTF | + AN8855_RG_DA_QP_PLL_BPD_INTF | + AN8855_RG_DA_QP_PLL_BPA_INTF | + AN8855_RG_DA_QP_PLL_BC_INTF, + AN8855_RG_DA_QP_PLL_RICO_SEL_INTF | + FIELD_PREP(AN8855_RG_DA_QP_PLL_FBKSEL_INTF, 0x0) | + FIELD_PREP(AN8855_RG_DA_QP_PLL_BR_INTF, 0x3) | + FIELD_PREP(AN8855_RG_DA_QP_PLL_BPD_INTF, 0x0) | + FIELD_PREP(AN8855_RG_DA_QP_PLL_BPA_INTF, 0x5) | + FIELD_PREP(AN8855_RG_DA_QP_PLL_BC_INTF, 0x1)); + if (ret) + return ret; + + /* PLL - ICO */ + ret =3D regmap_set_bits(priv->regmap, AN8855_PLL_CTRL_4, + AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF); + if (ret) + return ret; + ret =3D regmap_clear_bits(priv->regmap, AN8855_PLL_CTRL_2, + AN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF); + if (ret) + return ret; + + /* PLL - CHP */ + if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) + val =3D 0x6; + else + val =3D 0x4; + ret =3D regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2, + AN8855_RG_DA_QP_PLL_IR_INTF, + FIELD_PREP(AN8855_RG_DA_QP_PLL_IR_INTF, val)); + if (ret) + return ret; + + /* PLL - PFD */ + ret =3D regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2, + AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF | + AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF | + AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF, + FIELD_PREP(AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF, 0x1) | + FIELD_PREP(AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF, 0x1)); + if (ret) + return ret; + + /* PLL - POSTDIV */ + ret =3D regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2, + AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF | + AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF | + AN8855_RG_DA_QP_PLL_PCK_SEL_INTF, + AN8855_RG_DA_QP_PLL_PCK_SEL_INTF); + if (ret) + return ret; + + /* PLL - SDM */ + ret =3D regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2, + AN8855_RG_DA_QP_PLL_SDM_HREN_INTF, + FIELD_PREP(AN8855_RG_DA_QP_PLL_SDM_HREN_INTF, 0x0)); + if (ret) + return ret; + ret =3D regmap_clear_bits(priv->regmap, AN8855_PLL_CTRL_2, + AN8855_RG_DA_QP_PLL_SDM_IFM_INTF); + if (ret) + return ret; + + ret =3D regmap_update_bits(priv->regmap, AN8855_SS_LCPLL_PWCTL_SETTING_2, + AN8855_RG_NCPO_ANA_MSB, + FIELD_PREP(AN8855_RG_NCPO_ANA_MSB, 0x1)); + if (ret) + return ret; + + if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) + val =3D 0x7a000000; + else + val =3D 0x48000000; + ret =3D regmap_write(priv->regmap, AN8855_SS_LCPLL_TDC_FLT_2, + FIELD_PREP(AN8855_RG_LCPLL_NCPO_VALUE, val)); + if (ret) + return ret; + ret =3D regmap_write(priv->regmap, AN8855_SS_LCPLL_TDC_PCW_1, + FIELD_PREP(AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON, val)); + if (ret) + return ret; + + ret =3D regmap_clear_bits(priv->regmap, AN8855_SS_LCPLL_TDC_FLT_5, + AN8855_RG_LCPLL_NCPO_CHG); + if (ret) + return ret; + ret =3D regmap_clear_bits(priv->regmap, AN8855_PLL_CK_CTRL_0, + AN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF); + if (ret) + return ret; + + /* PLL - SS */ + ret =3D regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_3, + AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF, + FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF, 0x0)); + if (ret) + return ret; + ret =3D regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_4, + AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF, + FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF, 0x0)); + if (ret) + return ret; + ret =3D regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_3, + AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF, + FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF, 0x0)); + if (ret) + return ret; + + /* PLL - TDC */ + ret =3D regmap_clear_bits(priv->regmap, AN8855_PLL_CK_CTRL_0, + AN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF); + if (ret) + return ret; + + ret =3D regmap_set_bits(priv->regmap, AN8855_RG_QP_PLL_SDM_ORD, + AN8855_RG_QP_PLL_SSC_TRI_EN); + if (ret) + return ret; + ret =3D regmap_set_bits(priv->regmap, AN8855_RG_QP_PLL_SDM_ORD, + AN8855_RG_QP_PLL_SSC_PHASE_INI); + if (ret) + return ret; + + ret =3D regmap_update_bits(priv->regmap, AN8855_RG_QP_RX_DAC_EN, + AN8855_RG_QP_SIGDET_HF, + FIELD_PREP(AN8855_RG_QP_SIGDET_HF, 0x2)); + if (ret) + return ret; + + /* TCL Disable (only for Co-SIM) */ + ret =3D regmap_clear_bits(priv->regmap, AN8855_PON_RXFEDIG_CTRL_0, + AN8855_RG_QP_EQ_RX500M_CK_SEL); + if (ret) + return ret; + + /* TX Init */ + if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) + val =3D 0x4; + else + val =3D 0x0; + ret =3D regmap_update_bits(priv->regmap, AN8855_RG_QP_TX_MODE, + AN8855_RG_QP_TX_RESERVE | + AN8855_RG_QP_TX_MODE_16B_EN, + FIELD_PREP(AN8855_RG_QP_TX_RESERVE, val)); + if (ret) + return ret; + + /* RX Control/Init */ + ret =3D regmap_set_bits(priv->regmap, AN8855_RG_QP_RXAFE_RESERVE, + AN8855_RG_QP_CDR_PD_10B_EN); + if (ret) + return ret; + + if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) + val =3D 0x1; + else + val =3D 0x2; + ret =3D regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_MJV_LIM, + AN8855_RG_QP_CDR_LPF_RATIO, + FIELD_PREP(AN8855_RG_QP_CDR_LPF_RATIO, val)); + if (ret) + return ret; + + ret =3D regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_SETVALUE, + AN8855_RG_QP_CDR_PR_BUF_IN_SR | + AN8855_RG_QP_CDR_PR_BETA_SEL, + FIELD_PREP(AN8855_RG_QP_CDR_PR_BUF_IN_SR, 0x6) | + FIELD_PREP(AN8855_RG_QP_CDR_PR_BETA_SEL, 0x1)); + if (ret) + return ret; + + if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) + val =3D 0xf; + else + val =3D 0xc; + ret =3D regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_CKREF_DIV1, + AN8855_RG_QP_CDR_PR_DAC_BAND, + FIELD_PREP(AN8855_RG_QP_CDR_PR_DAC_BAND, val)); + if (ret) + return ret; + + ret =3D regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_KBAND_DIV_PC= IE, + AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE | + AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK, + FIELD_PREP(AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK, 0x19)); + if (ret) + return ret; + + ret =3D regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_FORCE_IBANDLPF_= R_OFF, + AN8855_RG_QP_CDR_PHYCK_SEL | + AN8855_RG_QP_CDR_PHYCK_RSTB | + AN8855_RG_QP_CDR_PHYCK_DIV, + FIELD_PREP(AN8855_RG_QP_CDR_PHYCK_SEL, 0x2) | + FIELD_PREP(AN8855_RG_QP_CDR_PHYCK_DIV, 0x21)); + if (ret) + return ret; + + ret =3D regmap_clear_bits(priv->regmap, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCI= E, + AN8855_RG_QP_CDR_PR_XFICK_EN); + if (ret) + return ret; + + ret =3D regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_CKREF_DIV1, + AN8855_RG_QP_CDR_PR_KBAND_DIV, + FIELD_PREP(AN8855_RG_QP_CDR_PR_KBAND_DIV, 0x4)); + if (ret) + return ret; + + ret =3D regmap_update_bits(priv->regmap, AN8855_RX_CTRL_26, + AN8855_RG_QP_EQ_RETRAIN_ONLY_EN | + AN8855_RG_LINK_NE_EN | + AN8855_RG_LINK_ERRO_EN, + AN8855_RG_QP_EQ_RETRAIN_ONLY_EN | + AN8855_RG_LINK_ERRO_EN); + if (ret) + return ret; + + ret =3D regmap_update_bits(priv->regmap, AN8855_RX_DLY_0, + AN8855_RG_QP_RX_SAOSC_EN_H_DLY | + AN8855_RG_QP_RX_PI_CAL_EN_H_DLY, + FIELD_PREP(AN8855_RG_QP_RX_SAOSC_EN_H_DLY, 0x3f) | + FIELD_PREP(AN8855_RG_QP_RX_PI_CAL_EN_H_DLY, 0x6f)); + if (ret) + return ret; + + ret =3D regmap_update_bits(priv->regmap, AN8855_RX_CTRL_42, + AN8855_RG_QP_EQ_EN_DLY, + FIELD_PREP(AN8855_RG_QP_EQ_EN_DLY, 0x150)); + if (ret) + return ret; + + ret =3D regmap_update_bits(priv->regmap, AN8855_RX_CTRL_2, + AN8855_RG_QP_RX_EQ_EN_H_DLY, + FIELD_PREP(AN8855_RG_QP_RX_EQ_EN_H_DLY, 0x150)); + if (ret) + return ret; + + ret =3D regmap_update_bits(priv->regmap, AN8855_PON_RXFEDIG_CTRL_9, + AN8855_RG_QP_EQ_LEQOSC_DLYCNT, + FIELD_PREP(AN8855_RG_QP_EQ_LEQOSC_DLYCNT, 0x1)); + if (ret) + return ret; + + ret =3D regmap_update_bits(priv->regmap, AN8855_RX_CTRL_8, + AN8855_RG_DA_QP_SAOSC_DONE_TIME | + AN8855_RG_DA_QP_LEQOS_EN_TIME, + FIELD_PREP(AN8855_RG_DA_QP_SAOSC_DONE_TIME, 0x200) | + FIELD_PREP(AN8855_RG_DA_QP_LEQOS_EN_TIME, 0xfff)); + if (ret) + return ret; + + /* Frequency meter */ + if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) + val =3D 0x10; + else + val =3D 0x28; + ret =3D regmap_update_bits(priv->regmap, AN8855_RX_CTRL_5, + AN8855_RG_FREDET_CHK_CYCLE, + FIELD_PREP(AN8855_RG_FREDET_CHK_CYCLE, val)); + if (ret) + return ret; + + ret =3D regmap_update_bits(priv->regmap, AN8855_RX_CTRL_6, + AN8855_RG_FREDET_GOLDEN_CYCLE, + FIELD_PREP(AN8855_RG_FREDET_GOLDEN_CYCLE, 0x64)); + if (ret) + return ret; + + ret =3D regmap_update_bits(priv->regmap, AN8855_RX_CTRL_7, + AN8855_RG_FREDET_TOLERATE_CYCLE, + FIELD_PREP(AN8855_RG_FREDET_TOLERATE_CYCLE, 0x2710)); + if (ret) + return ret; + + ret =3D regmap_set_bits(priv->regmap, AN8855_PLL_CTRL_0, + AN8855_RG_PHYA_AUTO_INIT); + if (ret) + return ret; + + /* PCS Init */ + if (interface =3D=3D PHY_INTERFACE_MODE_SGMII && + neg_mode =3D=3D PHYLINK_PCS_NEG_INBAND_DISABLED) { + ret =3D regmap_clear_bits(priv->regmap, AN8855_QP_DIG_MODE_CTRL_0, + AN8855_RG_SGMII_MODE | AN8855_RG_SGMII_AN_EN); + if (ret) + return ret; + } + + ret =3D regmap_clear_bits(priv->regmap, AN8855_RG_HSGMII_PCS_CTROL_1, + AN8855_RG_TBI_10B_MODE); + if (ret) + return ret; + + if (neg_mode =3D=3D PHYLINK_PCS_NEG_INBAND_ENABLED) { + /* Set AN Ability - Interrupt */ + ret =3D regmap_set_bits(priv->regmap, AN8855_SGMII_REG_AN_FORCE_CL37, + AN8855_RG_FORCE_AN_DONE); + if (ret) + return ret; + + ret =3D regmap_update_bits(priv->regmap, AN8855_SGMII_REG_AN_13, + AN8855_SGMII_REMOTE_FAULT_DIS | + AN8855_SGMII_IF_MODE, + AN8855_SGMII_REMOTE_FAULT_DIS | + FIELD_PREP(AN8855_SGMII_IF_MODE, 0xb)); + if (ret) + return ret; + } + + /* Rate Adaption - GMII path config. */ + if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) { + ret =3D regmap_clear_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0, + AN8855_RG_P0_DIS_MII_MODE); + if (ret) + return ret; + } else { + if (neg_mode =3D=3D PHYLINK_PCS_NEG_INBAND_ENABLED) { + ret =3D regmap_set_bits(priv->regmap, AN8855_MII_RA_AN_ENABLE, + AN8855_RG_P0_RA_AN_EN); + if (ret) + return ret; + } else { + ret =3D regmap_update_bits(priv->regmap, AN8855_RG_AN_SGMII_MODE_FORCE, + AN8855_RG_FORCE_CUR_SGMII_MODE | + AN8855_RG_FORCE_CUR_SGMII_SEL, + AN8855_RG_FORCE_CUR_SGMII_SEL); + if (ret) + return ret; + + ret =3D regmap_clear_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0, + AN8855_RG_P0_MII_RA_RX_EN | + AN8855_RG_P0_MII_RA_TX_EN | + AN8855_RG_P0_MII_RA_RX_MODE | + AN8855_RG_P0_MII_RA_TX_MODE); + if (ret) + return ret; + } + + ret =3D regmap_set_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0, + AN8855_RG_P0_MII_MODE); + if (ret) + return ret; + } + + ret =3D regmap_set_bits(priv->regmap, AN8855_RG_RATE_ADAPT_CTRL_0, + AN8855_RG_RATE_ADAPT_RX_BYPASS | + AN8855_RG_RATE_ADAPT_TX_BYPASS | + AN8855_RG_RATE_ADAPT_RX_EN | + AN8855_RG_RATE_ADAPT_TX_EN); + if (ret) + return ret; + + /* Disable AN if not in autoneg */ + ret =3D regmap_update_bits(priv->regmap, AN8855_SGMII_REG_AN0, BMCR_ANENA= BLE, + neg_mode =3D=3D PHYLINK_PCS_NEG_INBAND_ENABLED ? BMCR_ANENABLE : + 0); + if (ret) + return ret; + + if (interface =3D=3D PHY_INTERFACE_MODE_SGMII) { + /* Follow SDK init flow with restarting AN after AN enable */ + if (neg_mode =3D=3D PHYLINK_PCS_NEG_INBAND_ENABLED) { + ret =3D regmap_set_bits(priv->regmap, AN8855_SGMII_REG_AN0, + BMCR_ANRESTART); + if (ret) + return ret; + } else { + ret =3D regmap_set_bits(priv->regmap, AN8855_PHY_RX_FORCE_CTRL_0, + AN8855_RG_FORCE_TXC_SEL); + if (ret) + return ret; + } + } + + /* Force Speed with fixed-link or 2500base-x as doesn't support aneg */ + if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX || + neg_mode !=3D PHYLINK_PCS_NEG_INBAND_ENABLED) { + if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) + val =3D AN8855_RG_LINK_MODE_P0_SPEED_2500; + else + val =3D AN8855_RG_LINK_MODE_P0_SPEED_1000; + ret =3D regmap_update_bits(priv->regmap, AN8855_SGMII_STS_CTRL_0, + AN8855_RG_LINK_MODE_P0 | + AN8855_RG_FORCE_SPD_MODE_P0, + val | AN8855_RG_FORCE_SPD_MODE_P0); + if (ret) + return ret; + } + + /* bypass flow control to MAC */ + ret =3D regmap_write(priv->regmap, AN8855_MSG_RX_LIK_STS_0, + AN8855_RG_DPX_STS_P3 | AN8855_RG_DPX_STS_P2 | + AN8855_RG_DPX_STS_P1 | AN8855_RG_TXFC_STS_P0 | + AN8855_RG_RXFC_STS_P0 | AN8855_RG_DPX_STS_P0); + if (ret) + return ret; + ret =3D regmap_write(priv->regmap, AN8855_MSG_RX_LIK_STS_2, + AN8855_RG_RXFC_AN_BYPASS_P3 | + AN8855_RG_RXFC_AN_BYPASS_P2 | + AN8855_RG_RXFC_AN_BYPASS_P1 | + AN8855_RG_TXFC_AN_BYPASS_P3 | + AN8855_RG_TXFC_AN_BYPASS_P2 | + AN8855_RG_TXFC_AN_BYPASS_P1 | + AN8855_RG_DPX_AN_BYPASS_P3 | + AN8855_RG_DPX_AN_BYPASS_P2 | + AN8855_RG_DPX_AN_BYPASS_P1 | + AN8855_RG_DPX_AN_BYPASS_P0); + if (ret) + return ret; + + return 0; +} + +static void an8855_pcs_an_restart(struct phylink_pcs *pcs) +{ +} + +static const struct phylink_pcs_ops an8855_pcs_ops =3D { + .pcs_inband_caps =3D an8855_pcs_inband_caps, + .pcs_get_state =3D an8855_pcs_get_state, + .pcs_config =3D an8855_pcs_config, + .pcs_an_restart =3D an8855_pcs_an_restart, +}; + +static const struct phylink_mac_ops an8855_phylink_mac_ops =3D { + .mac_select_pcs =3D an8855_phylink_mac_select_pcs, + .mac_config =3D an8855_phylink_mac_config, + .mac_link_down =3D an8855_phylink_mac_link_down, + .mac_link_up =3D an8855_phylink_mac_link_up, + .mac_disable_tx_lpi =3D an8855_phylink_mac_disable_tx_lpi, + .mac_enable_tx_lpi =3D an8855_phylink_mac_enable_tx_lpi, +}; + +static const struct dsa_switch_ops an8855_switch_ops =3D { + .get_tag_protocol =3D an8855_get_tag_protocol, + .setup =3D an8855_setup, + .phylink_get_caps =3D an8855_phylink_get_caps, + .get_strings =3D an8855_get_strings, + .get_ethtool_stats =3D an8855_get_ethtool_stats, + .get_sset_count =3D an8855_get_sset_count, + .get_eth_mac_stats =3D an8855_get_eth_mac_stats, + .get_eth_ctrl_stats =3D an8855_get_eth_ctrl_stats, + .get_rmon_stats =3D an8855_get_rmon_stats, + .port_enable =3D an8855_port_enable, + .port_disable =3D an8855_port_disable, + .set_ageing_time =3D an8855_set_ageing_time, + .port_bridge_join =3D an8855_port_bridge_join, + .port_bridge_leave =3D an8855_port_bridge_leave, + .port_fast_age =3D an8855_port_fast_age, + .port_stp_state_set =3D an8855_port_stp_state_set, + .port_pre_bridge_flags =3D an8855_port_pre_bridge_flags, + .port_bridge_flags =3D an8855_port_bridge_flags, + .port_vlan_filtering =3D an8855_port_vlan_filtering, + .port_vlan_add =3D an8855_port_vlan_add, + .port_vlan_del =3D an8855_port_vlan_del, + .port_fdb_add =3D an8855_port_fdb_add, + .port_fdb_del =3D an8855_port_fdb_del, + .port_fdb_dump =3D an8855_port_fdb_dump, + .port_mdb_add =3D an8855_port_mdb_add, + .port_mdb_del =3D an8855_port_mdb_del, + .port_change_mtu =3D an8855_port_change_mtu, + .port_max_mtu =3D an8855_port_max_mtu, + .port_mirror_add =3D an8855_port_mirror_add, + .port_mirror_del =3D an8855_port_mirror_del, + .support_eee =3D dsa_supports_eee, + .set_mac_eee =3D an8855_set_mac_eee, +}; + +static int an8855_setup_lib_priv(struct an8855_priv *priv) +{ + struct mt7530_lib_priv *lib_priv =3D &priv->lib_priv; + int i; + + lib_priv->dev =3D priv->ds->dev; + lib_priv->ds =3D priv->ds; + lib_priv->regmap =3D priv->regmap; + lib_priv->ports =3D priv->ports; + lib_priv->reg_mutex =3D &priv->reg_mutex; + + for (i =3D 0; i < ARRAY_SIZE(an8855_fields); i++) { + const struct mt7530_reg_field *reg_field; + struct regmap_field *field; + + reg_field =3D &an8855_fields[i]; + field =3D devm_regmap_field_alloc(priv->ds->dev, priv->regmap, + reg_field->field); + if (IS_ERR(field)) + return PTR_ERR(field); + + lib_priv->fields[reg_field->id] =3D field; + } + + return 0; +} + +static int an8855_switch_probe(struct platform_device *pdev) +{ + struct an8855_priv *priv; + int ret; + + priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + /* Get regmap from MFD */ + priv->regmap =3D dev_get_regmap(pdev->dev.parent, NULL); + if (!priv->regmap) + return -ENOENT; + + priv->ds =3D devm_kzalloc(&pdev->dev, sizeof(*priv->ds), GFP_KERNEL); + if (!priv->ds) + return -ENOMEM; + + priv->ds->dev =3D &pdev->dev; + priv->ds->num_ports =3D AN8855_NUM_PORTS; + priv->ds->priv =3D priv; + priv->ds->ops =3D &an8855_switch_ops; + ret =3D devm_mutex_init(&pdev->dev, &priv->reg_mutex); + if (ret) + return ret; + priv->ds->phylink_mac_ops =3D &an8855_phylink_mac_ops; + + priv->pcs.ops =3D &an8855_pcs_ops; + priv->pcs.poll =3D true; + + ret =3D an8855_setup_lib_priv(priv); + if (ret) + return ret; + + dev_set_drvdata(&pdev->dev, priv); + + return dsa_register_switch(priv->ds); +} + +static void an8855_switch_remove(struct platform_device *pdev) +{ + struct an8855_priv *priv =3D dev_get_drvdata(&pdev->dev); + + if (!priv) + return; + + dsa_unregister_switch(priv->ds); + + dev_set_drvdata(&pdev->dev, NULL); +} + +static void an8855_switch_shutdown(struct platform_device *pdev) +{ + struct an8855_priv *priv =3D dev_get_drvdata(&pdev->dev); + + if (!priv) + return; + + dsa_switch_shutdown(priv->ds); + + dev_set_drvdata(&pdev->dev, NULL); +} + +static const struct of_device_id an8855_switch_of_match[] =3D { + { .compatible =3D "airoha,an8855-switch" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, an8855_switch_of_match); + +static struct platform_driver an8855_switch_driver =3D { + .probe =3D an8855_switch_probe, + .remove =3D an8855_switch_remove, + .shutdown =3D an8855_switch_shutdown, + .driver =3D { + .name =3D "an8855-switch", + .of_match_table =3D an8855_switch_of_match, + }, +}; +module_platform_driver(an8855_switch_driver); + +MODULE_AUTHOR("Min Yao "); +MODULE_AUTHOR("Christian Marangi "); +MODULE_DESCRIPTION("Driver for Airoha AN8855 Switch"); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/dsa/mediatek/an8855.h b/drivers/net/dsa/mediatek/a= n8855.h new file mode 100644 index 000000000000..85003e568450 --- /dev/null +++ b/drivers/net/dsa/mediatek/an8855.h @@ -0,0 +1,755 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 Min Yao + * Copyright (C) 2024 Christian Marangi + */ + +#ifndef __AN8855_H +#define __AN8855_H + +#include + +#include "mt7530-lib.h" + +#define AN8855_NUM_PORTS 6 +#define AN8855_CPU_PORT 5 +#define AN8855_NUM_FDB_RECORDS 2048 +#define AN8855_GPHY_SMI_ADDR_DEFAULT 1 +#define AN8855_PORT_VID_DEFAULT 0 + +#define MTK_TAG_LEN 4 +#define AN8855_MAX_MTU (15360 - ETH_HLEN - ETH_FCS_LEN - MTK_TAG_LEN) + +#define AN8855_L2_AGING_MS_CONSTANT 1024 + +#define AN8855_TX_LPI_UNIT 2 /* us */ + +/* AN8855_SCU 0x10000000 */ +#define AN8855_RG_GPIO_LED_MODE 0x10000054 +#define AN8855_RG_GPIO_LED_SEL(i) (0x10000000 + (0x0058 + ((i) * 4))) +#define AN8855_RG_INTB_MODE 0x10000080 +#define AN8855_RG_RGMII_TXCK_C 0x100001d0 + +#define AN8855_PKG_SEL 0x10000094 +#define AN8855_PAG_SEL_AN8855H 0x2 + +#define AN8855_RG_GPIO_L_INV 0x10000010 +#define AN8855_RG_GPIO_CTRL 0x1000a300 +#define AN8855_RG_GPIO_DATA 0x1000a304 +#define AN8855_RG_GPIO_OE 0x1000a314 + +/* Register for system reset */ +#define AN8855_RST_CTRL 0x100050c0 +#define AN8855_SYS_CTRL_SYS_RST BIT(31) + +#define AN8855_INT_MASK 0x100050f0 +#define AN8855_INT_SYS BIT(15) + +#define AN8855_RG_CLK_CPU_ICG 0x10005034 +#define AN8855_MCU_ENABLE BIT(3) + +#define AN8855_RG_TIMER_CTL 0x1000a100 +#define AN8855_WDOG_ENABLE BIT(25) + +#define AN8855_RG_GDMP_RAM 0x10010000 + +/* Registers to mac forward control for unknown frames */ +#define AN8855_MFC 0x10200010 +#define AN8855_CPU_EN BIT(15) +#define AN8855_CPU_PORT_IDX GENMASK(12, 8) + +#define AN8855_PAC 0x10200024 +#define AN8855_TAG_PAE_MANG_FR BIT(30) +#define AN8855_TAG_PAE_BPDU_FR BIT(28) +#define AN8855_TAG_PAE_EG_TAG GENMASK(27, 25) +#define AN8855_TAG_PAE_LKY_VLAN BIT(24) +#define AN8855_TAG_PAE_PRI_HIGH BIT(23) +#define AN8855_TAG_PAE_MIR GENMASK(20, 19) +#define AN8855_TAG_PAE_PORT_FW GENMASK(18, 16) +#define AN8855_PAE_MANG_FR BIT(14) +#define AN8855_PAE_BPDU_FR BIT(12) +#define AN8855_PAE_EG_TAG GENMASK(11, 9) +#define AN8855_PAE_LKY_VLAN BIT(8) +#define AN8855_PAE_PRI_HIGH BIT(7) +#define AN8855_PAE_MIR GENMASK(4, 3) +#define AN8855_PAE_PORT_FW GENMASK(2, 0) + +#define AN8855_RGAC1 0x10200028 +#define AN8855_R02_MANG_FR BIT(30) +#define AN8855_R02_BPDU_FR BIT(28) +#define AN8855_R02_EG_TAG GENMASK(27, 25) +#define AN8855_R02_LKY_VLAN BIT(24) +#define AN8855_R02_PRI_HIGH BIT(23) +#define AN8855_R02_MIR GENMASK(20, 19) +#define AN8855_R02_PORT_FW GENMASK(18, 16) +#define AN8855_R01_MANG_FR BIT(14) +#define AN8855_R01_BPDU_FR BIT(12) +#define AN8855_R01_EG_TAG GENMASK(11, 9) +#define AN8855_R01_LKY_VLAN BIT(8) +#define AN8855_R01_PRI_HIGH BIT(7) +#define AN8855_R01_MIR GENMASK(4, 3) +#define AN8855_R01_PORT_FW GENMASK(2, 0) + +#define AN8855_RGAC2 0x1020002c +#define AN8855_R0E_MANG_FR BIT(30) +#define AN8855_R0E_BPDU_FR BIT(28) +#define AN8855_R0E_EG_TAG GENMASK(27, 25) +#define AN8855_R0E_LKY_VLAN BIT(24) +#define AN8855_R0E_PRI_HIGH BIT(23) +#define AN8855_R0E_MIR GENMASK(20, 19) +#define AN8855_R0E_PORT_FW GENMASK(18, 16) +#define AN8855_R03_MANG_FR BIT(14) +#define AN8855_R03_BPDU_FR BIT(12) +#define AN8855_R03_EG_TAG GENMASK(11, 9) +#define AN8855_R03_LKY_VLAN BIT(8) +#define AN8855_R03_PRI_HIGH BIT(7) +#define AN8855_R03_MIR GENMASK(4, 3) +#define AN8855_R03_PORT_FW GENMASK(2, 0) + +#define AN8855_AAC 0x102000a0 +#define AN8855_MAC_AUTO_FLUSH BIT(28) +/* Control Address Table Age time. + * (AN8855_AGE_CNT + 1) * ( AN8855_AGE_UNIT + 1 ) * AN8855_L2_AGING_MS_CON= STANT + */ +#define AN8855_AGE_CNT GENMASK(20, 12) +/* Value in seconds. Value is always incremented of 1 */ +#define AN8855_AGE_UNIT GENMASK(10, 0) + +/* Registers for ARL Unknown Unicast Forward control */ +#define AN8855_UNUF 0x102000b4 + +/* Registers for ARL Unknown Multicast Forward control */ +#define AN8855_UNMF 0x102000b8 + +/* Registers for ARL Broadcast forward control */ +#define AN8855_BCF 0x102000bc + +/* Registers for port address age disable */ +#define AN8855_AGDIS 0x102000c0 + +/* Registers for mirror port control */ +#define AN8855_MIR 0x102000cc +#define AN8855_MIRROR_EN BIT(7) +#define AN8855_MIRROR_PORT GENMASK(4, 0) + +/* Registers for BPDU and PAE frame control*/ +#define AN8855_BPC 0x102000d0 +#define AN8855_BPDU_MANG_FR BIT(14) +#define AN8855_BPDU_BPDU_FR BIT(12) +#define AN8855_BPDU_EG_TAG GENMASK(11, 9) +#define AN8855_BPDU_LKY_VLAN BIT(8) +#define AN8855_BPDU_PRI_HIGH BIT(7) +#define AN8855_BPDU_MIR GENMASK(4, 3) +#define AN8855_BPDU_PORT_FW GENMASK(2, 0) + +/* Registers for IP Unknown Multicast Forward control */ +#define AN8855_UNIPMF 0x102000dc + +enum an8855_bpdu_port_fw { + AN8855_BPDU_FOLLOW_MFC =3D 0, + AN8855_BPDU_CPU_EXCLUDE =3D 4, + AN8855_BPDU_CPU_INCLUDE =3D 5, + AN8855_BPDU_CPU_ONLY =3D 6, + AN8855_BPDU_DROP =3D 7, +}; + +/* Register for address table control */ +#define AN8855_ATC 0x10200300 +#define AN8855_ATC_BUSY BIT(31) +#define AN8855_ATC_HASH GENMASK(24, 16) +#define AN8855_ATC_HIT GENMASK(15, 12) +#define AN8855_ATC_MAT_MASK GENMASK(11, 7) +#define AN8855_ATC_MAT(x) FIELD_PREP(AN8855_ATC_MAT_MASK, x) +#define AN8855_ATC_SAT GENMASK(5, 4) +#define AN8855_ATC_CMD GENMASK(2, 0) + +enum an8855_fdb_mat_cmds { + AN8855_FDB_MAT_ALL =3D 0, + AN8855_FDB_MAT_MAC, /* All MAC address */ + AN8855_FDB_MAT_DYNAMIC_MAC, /* All Dynamic MAC address */ + AN8855_FDB_MAT_STATIC_MAC, /* All Static Mac Address */ + AN8855_FDB_MAT_DIP, /* All DIP/GA address */ + AN8855_FDB_MAT_DIP_IPV4, /* All DIP/GA IPv4 address */ + AN8855_FDB_MAT_DIP_IPV6, /* All DIP/GA IPv6 address */ + AN8855_FDB_MAT_DIP_SIP, /* All DIP_SIP address */ + AN8855_FDB_MAT_DIP_SIP_IPV4, /* All DIP_SIP IPv4 address */ + AN8855_FDB_MAT_DIP_SIP_IPV6, /* All DIP_SIP IPv6 address */ + AN8855_FDB_MAT_MAC_CVID, /* All MAC address with CVID */ + AN8855_FDB_MAT_MAC_FID, /* All MAC address with Filter ID */ + AN8855_FDB_MAT_MAC_PORT, /* All MAC address with port */ + AN8855_FDB_MAT_DIP_SIP_DIP_IPV4, /* All DIP_SIP address with DIP_IPV4 */ + AN8855_FDB_MAT_DIP_SIP_SIP_IPV4, /* All DIP_SIP address with SIP_IPV4 */ + AN8855_FDB_MAT_DIP_SIP_DIP_IPV6, /* All DIP_SIP address with DIP_IPV6 */ + AN8855_FDB_MAT_DIP_SIP_SIP_IPV6, /* All DIP_SIP address with SIP_IPV6 */ + /* All MAC address with MAC type (dynamic or static) with CVID */ + AN8855_FDB_MAT_MAC_TYPE_CVID, + /* All MAC address with MAC type (dynamic or static) with Filter ID */ + AN8855_FDB_MAT_MAC_TYPE_FID, + /* All MAC address with MAC type (dynamic or static) with port */ + AN8855_FDB_MAT_MAC_TYPE_PORT, +}; + +/* Registers for address table access */ +#define AN8855_ATA1 0x10200304 +#define AN8855_ATA1_MAC0 GENMASK(31, 24) +#define AN8855_ATA1_MAC1 GENMASK(23, 16) +#define AN8855_ATA1_MAC2 GENMASK(15, 8) +#define AN8855_ATA1_MAC3 GENMASK(7, 0) +#define AN8855_ATA2 0x10200308 +#define AN8855_ATA2_MAC4 GENMASK(31, 24) +#define AN8855_ATA2_MAC5 GENMASK(23, 16) +#define AN8855_ATA2_UNAUTH BIT(10) +#define AN8855_ATA2_TYPE BIT(9) /* 1: dynamic, 0: static */ +#define AN8855_ATA2_AGE GENMASK(8, 0) + +/* Register for address table write data */ +#define AN8855_ATWD 0x10200324 +#define AN8855_ATWD_FID GENMASK(31, 28) +#define AN8855_ATWD_VID GENMASK(27, 16) +#define AN8855_ATWD_IVL BIT(15) +#define AN8855_ATWD_EG_TAG GENMASK(14, 12) +#define AN8855_ATWD_SA_MIR GENMASK(9, 8) +#define AN8855_ATWD_SA_FWD GENMASK(7, 5) +#define AN8855_ATWD_UPRI GENMASK(4, 2) +#define AN8855_ATWD_LEAKY BIT(1) +#define AN8855_ATWD_VLD_MASK BIT(0) /* vid LOAD */ +#define AN8855_ATWD2 0x10200328 +#define AN8855_ATWD2_PORT GENMASK(7, 0) + +/* Registers for table search read address */ +#define AN8855_ATRDS 0x10200330 +#define AN8855_ATRD_SEL GENMASK(1, 0) +#define AN8855_ATRD0 0x10200334 +#define AN8855_ATRD0_FID GENMASK(28, 25) +#define AN8855_ATRD0_VID GENMASK(21, 10) +#define AN8855_ATRD0_IVL BIT(9) +#define AN8855_ATRD0_TYPE GENMASK(4, 3) +#define AN8855_ATRD0_ARP GENMASK(2, 1) +#define AN8855_ATRD0_LIVE BIT(0) +#define AN8855_ATRD1 0x10200338 +#define AN8855_ATRD1_MAC4 GENMASK(31, 24) +#define AN8855_ATRD1_MAC5 GENMASK(23, 16) +#define AN8855_ATRD1_AGING GENMASK(11, 3) +#define AN8855_ATRD2 0x1020033c +#define AN8855_ATRD2_MAC0 GENMASK(31, 24) +#define AN8855_ATRD2_MAC1 GENMASK(23, 16) +#define AN8855_ATRD2_MAC2 GENMASK(15, 8) +#define AN8855_ATRD2_MAC3 GENMASK(7, 0) +#define AN8855_ATRD3 0x10200340 +#define AN8855_ATRD3_PORTMASK GENMASK(7, 0) + +enum an8855_fdb_type { + AN8855_MAC_TB_TY_MAC =3D 0, + AN8855_MAC_TB_TY_DIP =3D 1, + AN8855_MAC_TB_TY_DIP_SIP =3D 2, +}; + +/* Register for vlan table control */ +#define AN8855_VTCR 0x10200600 +#define AN8855_VTCR_BUSY BIT(31) +#define AN8855_VTCR_FUNC GENMASK(15, 12) +#define AN8855_VTCR_VID GENMASK(11, 0) + +enum an8855_vlan_cmd { + /* Read/Write the specified VID entry from VAWD register based + * on VID. + */ + AN8855_VTCR_RD_VID =3D 0, + AN8855_VTCR_WR_VID =3D 1, +}; + +/* Register for setup vlan write data */ +#define AN8855_VAWD0 0x10200604 +/* VLAN Member Control */ +#define AN8855_VA0_PORT GENMASK(31, 26) +/* Egress Tag Control */ +#define AN8855_VA0_ETAG GENMASK(23, 12) +#define AN8855_VA0_ETAG_PORT GENMASK(13, 12) +#define AN8855_VA0_ETAG_PORT_SHIFT(port) ((port) * 2) +#define AN8855_VA0_ETAG_PORT_MASK(port) (AN8855_VA0_ETAG_PORT << \ + AN8855_VA0_ETAG_PORT_SHIFT(port)) +#define AN8855_VA0_ETAG_PORT_VAL(port, val) (FIELD_PREP(AN8855_VA0_ETAG_= PORT, (val)) << \ + AN8855_VA0_ETAG_PORT_SHIFT(port)) +#define AN8855_VA0_EG_CON BIT(11) +#define AN8855_VA0_VTAG_EN BIT(10) /* Per VLAN Egress Tag Control */ +#define AN8855_VA0_IVL_MAC BIT(5) /* Independent VLAN Learning */ +#define AN8855_VA0_FID GENMASK(4, 1) +#define AN8855_VA0_VLAN_VALID BIT(0) /* VLAN Entry Valid */ +#define AN8855_VAWD1 0x10200608 +#define AN8855_VA1_PORT_STAG BIT(1) + +enum an8855_fid { + AN8855_FID_STANDALONE =3D 0, + AN8855_FID_BRIDGED =3D 1, +}; + +/* Same register field of VAWD0 */ +#define AN8855_VARD0 0x10200618 + +enum an8855_vlan_egress_attr { + AN8855_VLAN_EGRESS_UNTAG =3D 0, + AN8855_VLAN_EGRESS_TAG =3D 2, + AN8855_VLAN_EGRESS_STACK =3D 3, +}; + +/* Register for port STP state control */ +#define AN8855_SSP 0x10208000 +#define AN8855_SSP_P(x) (AN8855_SSP + ((x) * 0x200)) +/* Up to 16 FID supported, each with the same mask */ +#define AN8855_FID_PST GENMASK(1, 0) +#define AN8855_FID_PST_SHIFT(fid) (2 * (fid)) +#define AN8855_FID_PST_MASK(fid) (AN8855_FID_PST << \ + AN8855_FID_PST_SHIFT(fid)) +#define AN8855_FID_PST_VAL(fid, val) (FIELD_PREP(AN8855_FID_PST, (val)) = << \ + AN8855_FID_PST_SHIFT(fid)) + +enum an8855_stp_state { + AN8855_STP_DISABLED =3D 0, + AN8855_STP_BLOCKING =3D 1, + AN8855_STP_LISTENING =3D AN8855_STP_BLOCKING, + AN8855_STP_LEARNING =3D 2, + AN8855_STP_FORWARDING =3D 3 +}; + +/* Register for port control */ +#define AN8855_PCR 0x10208004 +#define AN8855_PCR_P(x) (AN8855_PCR + ((x) * 0x200)) +#define AN8855_EG_TAG GENMASK(29, 28) +#define AN8855_PORT_PRI GENMASK(26, 24) +#define AN8855_PORT_TX_MIR BIT(20) +#define AN8855_PORT_RX_MIR BIT(16) +#define AN8855_PORT_VLAN GENMASK(1, 0) + +enum an8855_port_mode { + /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */ + AN8855_PORT_MATRIX_MODE =3D 0, + + /* Fallback Mode: Forward received frames with ingress ports that do + * not belong to the VLAN member. Frames whose VID is not listed on + * the VLAN table are forwarded by the PCR_MATRIX members. + */ + AN8855_PORT_FALLBACK_MODE =3D 1, + + /* Check Mode: Forward received frames whose ingress do not + * belong to the VLAN member. Discard frames if VID ismiddes on the + * VLAN table. + */ + AN8855_PORT_CHECK_MODE =3D 2, + + /* Security Mode: Discard any frame due to ingress membership + * violation or VID missed on the VLAN table. + */ + AN8855_PORT_SECURITY_MODE =3D 3, +}; + +/* Register for port security control */ +#define AN8855_PSC 0x1020800c +#define AN8855_PSC_P(x) (AN8855_PSC + ((x) * 0x200)) +#define AN8855_SA_DIS BIT(4) + +/* Register for port vlan control */ +#define AN8855_PVC 0x10208010 +#define AN8855_PVC_P(x) (AN8855_PVC + ((x) * 0x200)) +#define AN8855_PORT_SPEC_REPLACE_MODE BIT(11) +#define AN8855_PVC_EG_TAG GENMASK(10, 8) +#define AN8855_VLAN_ATTR GENMASK(7, 6) +#define AN8855_PORT_SPEC_TAG BIT(5) +#define AN8855_ACC_FRM GENMASK(1, 0) + +enum an8855_vlan_port_eg_tag { + AN8855_VLAN_EG_DISABLED =3D 0, + AN8855_VLAN_EG_CONSISTENT =3D 1, + AN8855_VLAN_EG_UNTAGGED =3D 4, + AN8855_VLAN_EG_SWAP =3D 5, + AN8855_VLAN_EG_TAGGED =3D 6, + AN8855_VLAN_EG_STACK =3D 7, +}; + +enum an8855_vlan_port_attr { + AN8855_VLAN_USER =3D 0, + AN8855_VLAN_STACK =3D 1, + AN8855_VLAN_TRANSPARENT =3D 3, +}; + +enum an8855_vlan_port_acc_frm { + AN8855_VLAN_ACC_ALL =3D 0, + AN8855_VLAN_ACC_TAGGED =3D 1, + AN8855_VLAN_ACC_UNTAGGED =3D 2, +}; + +#define AN8855_PPBV1 0x10208014 +#define AN8855_PPBV1_P(x) (AN8855_PPBV1 + ((x) * 0x200)) +#define AN8855_PPBV_G0_PORT_VID GENMASK(11, 0) + +#define AN8855_PORTMATRIX 0x10208044 +#define AN8855_PORTMATRIX_P(x) (AN8855_PORTMATRIX + ((x) * 0x200)) +#define AN8855_PORTMATRIX_MASK GENMASK(5, 0) +/* Port matrix without the CPU port that should never be removed */ +#define AN8855_USER_PORTMATRIX GENMASK(4, 0) + +/* Register for port PVID */ +#define AN8855_PVID 0x10208048 +#define AN8855_PVID_P(x) (AN8855_PVID + ((x) * 0x200)) +#define AN8855_G0_PORT_VID GENMASK(11, 0) + +/* Register for port MAC control register */ +#define AN8855_PMCR_P(x) (0x10210000 + ((x) * 0x200)) +#define AN8855_PMCR_FORCE_MODE BIT(31) +#define AN8855_PMCR_FORCE_SPEED GENMASK(30, 28) +#define AN8855_PMCR_FORCE_SPEED_5000 FIELD_PREP_CONST(AN8855_PMCR_FORCE_= SPEED, 0x4) +#define AN8855_PMCR_FORCE_SPEED_2500 FIELD_PREP_CONST(AN8855_PMCR_FORCE_= SPEED, 0x3) +#define AN8855_PMCR_FORCE_SPEED_1000 FIELD_PREP_CONST(AN8855_PMCR_FORCE_= SPEED, 0x2) +#define AN8855_PMCR_FORCE_SPEED_100 FIELD_PREP_CONST(AN8855_PMCR_FORCE_S= PEED, 0x1) +#define AN8855_PMCR_FORCE_SPEED_10 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SP= EED, 0x0) +#define AN8855_PMCR_FORCE_FDX BIT(25) +#define AN8855_PMCR_FORCE_LNK BIT(24) +#define AN8855_PMCR_IFG_XMIT GENMASK(21, 20) +#define AN8855_PMCR_EXT_PHY BIT(19) +#define AN8855_PMCR_MAC_MODE BIT(18) +#define AN8855_PMCR_TX_EN BIT(16) +#define AN8855_PMCR_RX_EN BIT(15) +#define AN8855_PMCR_BACKOFF_EN BIT(12) +#define AN8855_PMCR_BACKPR_EN BIT(11) +#define AN8855_PMCR_FORCE_EEE5G BIT(9) +#define AN8855_PMCR_FORCE_EEE2P5G BIT(8) +#define AN8855_PMCR_FORCE_EEE1G BIT(7) +#define AN8855_PMCR_FORCE_EEE100 BIT(6) +#define AN8855_PMCR_RX_FC_EN BIT(5) +#define AN8855_PMCR_TX_FC_EN BIT(4) + +#define AN8855_PMSR_P(x) (0x10210010 + (x) * 0x200) +#define AN8855_PMSR_SPEED GENMASK(30, 28) +#define AN8855_PMSR_SPEED_5000 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x4) +#define AN8855_PMSR_SPEED_2500 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x3) +#define AN8855_PMSR_SPEED_1000 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x2) +#define AN8855_PMSR_SPEED_100 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x1) +#define AN8855_PMSR_SPEED_10 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x0) +#define AN8855_PMSR_DPX BIT(25) +#define AN8855_PMSR_LNK BIT(24) +#define AN8855_PMSR_EEE1G BIT(7) +#define AN8855_PMSR_EEE100M BIT(6) +#define AN8855_PMSR_RX_FC BIT(5) +#define AN8855_PMSR_TX_FC BIT(4) + +#define AN8855_PMEEECR_P(x) (0x10210004 + (x) * 0x200) +#define AN8855_LPI_MODE_EN BIT(31) +#define AN8855_WAKEUP_TIME_2500 GENMASK(23, 16) +#define AN8855_WAKEUP_TIME_1000 GENMASK(15, 8) +#define AN8855_WAKEUP_TIME_100 GENMASK(7, 0) +#define AN8855_PMEEECR2_P(x) (0x10210008 + (x) * 0x200) +#define AN8855_WAKEUP_TIME_5000 GENMASK(7, 0) + +#define AN8855_GMACCR 0x10213e00 +#define AN8855_MAX_RX_JUMBO GENMASK(7, 4) +/* 2K for 0x0, 0x1, 0x2 */ +#define AN8855_MAX_RX_JUMBO_2K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x0) +#define AN8855_MAX_RX_JUMBO_3K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x3) +#define AN8855_MAX_RX_JUMBO_4K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x4) +#define AN8855_MAX_RX_JUMBO_5K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x5) +#define AN8855_MAX_RX_JUMBO_6K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x6) +#define AN8855_MAX_RX_JUMBO_7K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x7) +#define AN8855_MAX_RX_JUMBO_8K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x8) +#define AN8855_MAX_RX_JUMBO_9K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x9) +#define AN8855_MAX_RX_JUMBO_12K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x= a) +#define AN8855_MAX_RX_JUMBO_15K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x= b) +#define AN8855_MAX_RX_JUMBO_16K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x= c) +#define AN8855_MAX_RX_PKT_LEN GENMASK(1, 0) +#define AN8855_MAX_RX_PKT_1518_1522 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_L= EN, 0x0) +#define AN8855_MAX_RX_PKT_1536 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0= x1) +#define AN8855_MAX_RX_PKT_1552 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0= x2) +#define AN8855_MAX_RX_PKT_JUMBO FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, = 0x3) + +#define AN8855_CKGCR 0x10213e1c +#define AN8855_LPI_TXIDLE_THD_MASK GENMASK(31, 14) +#define AN8855_CKG_LNKDN_PORT_STOP BIT(1) +#define AN8855_CKG_LNKDN_GLB_STOP BIT(0) + +/* Register for MIB */ +#define AN8855_MIB_COUNTER 0x10214000 +#define AN8855_PORT_MIB_COUNTER(x) (AN8855_MIB_COUNTER + (x) * 0x200) +/* Each define is an offset of AN8855_PORT_MIB_COUNTER */ +#define AN8855_PORT_MIB_TX_DROP (AN8855_MIB_COUNTER + 0x00) +#define AN8855_PORT_MIB_TX_CRC_ERR (AN8855_MIB_COUNTER + 0x04) +#define AN8855_PORT_MIB_TX_UNICAST (AN8855_MIB_COUNTER + 0x08) +#define AN8855_PORT_MIB_TX_MULTICAST (AN8855_MIB_COUNTER + 0x0c) +#define AN8855_PORT_MIB_TX_BROADCAST (AN8855_MIB_COUNTER + 0x10) +#define AN8855_PORT_MIB_TX_COLLISION (AN8855_MIB_COUNTER + 0x14) +#define AN8855_PORT_MIB_TX_SINGLE_COLLISION (AN8855_MIB_COUNTER + 0x18) +#define AN8855_PORT_MIB_TX_MULTIPLE_COLLISION (AN8855_MIB_COUNTER + 0x1c) +#define AN8855_PORT_MIB_TX_DEFERRED (AN8855_MIB_COUNTER + 0x20) +#define AN8855_PORT_MIB_TX_LATE_COLLISION (AN8855_MIB_COUNTER + 0x24) +#define AN8855_PORT_MIB_TX_EXCESSIVE_COLLISION (AN8855_MIB_COUNTER + 0x2= 8) +#define AN8855_PORT_MIB_TX_PAUSE (AN8855_MIB_COUNTER + 0x2c) +#define AN8855_PORT_MIB_TX_PKT_SZ_64 (AN8855_MIB_COUNTER + 0x30) +#define AN8855_PORT_MIB_TX_PKT_SZ_65_TO_127 (AN8855_MIB_COUNTER + 0x34) +#define AN8855_PORT_MIB_TX_PKT_SZ_128_TO_255 (AN8855_MIB_COUNTER + 0x38) +#define AN8855_PORT_MIB_TX_PKT_SZ_256_TO_511 (AN8855_MIB_COUNTER + 0x3c) +#define AN8855_PORT_MIB_TX_PKT_SZ_512_TO_1023 (AN8855_MIB_COUNTER + 0x40) +#define AN8855_PORT_MIB_TX_PKT_SZ_1024_TO_1518 (AN8855_MIB_COUNTER + 0x4= 4) +#define AN8855_PORT_MIB_TX_PKT_SZ_1519_TO_MAX (AN8855_MIB_COUNTER + 0x48) +#define AN8855_PORT_MIB_TX_BYTES_LOW (AN8855_MIB_COUNTER + 0x4c) /* 64 b= ytes */ +#define AN8855_PORT_MIB_TX_BYTES_HIGH (AN8855_MIB_COUNTER + 0x50) +#define AN8855_PORT_MIB_TX_OVERSIZE_DROP (AN8855_MIB_COUNTER + 0x54) +#define AN8855_PORT_MIB_TX_BAD_PKT_BYTES_LOW (AN8855_MIB_COUNTER + 0x58)= /* 64 bytes */ +#define AN8855_PORT_MIB_TX_BAD_PKT_BYTES_HIGH (AN8855_MIB_COUNTER + 0x5c) +#define AN8855_PORT_MIB_RX_DROP (AN8855_MIB_COUNTER + 0x80) +#define AN8855_PORT_MIB_RX_FILTERING (AN8855_MIB_COUNTER + 0x84) +#define AN8855_PORT_MIB_RX_UNICAST (AN8855_MIB_COUNTER + 0x88) +#define AN8855_PORT_MIB_RX_MULTICAST (AN8855_MIB_COUNTER + 0x8c) +#define AN8855_PORT_MIB_RX_BROADCAST (AN8855_MIB_COUNTER + 0x90) +#define AN8855_PORT_MIB_RX_ALIGN_ERR (AN8855_MIB_COUNTER + 0x94) +#define AN8855_PORT_MIB_RX_CRC_ERR (AN8855_MIB_COUNTER + 0x98) +#define AN8855_PORT_MIB_RX_UNDER_SIZE_ERR (AN8855_MIB_COUNTER + 0x9c) +#define AN8855_PORT_MIB_RX_FRAG_ERR (AN8855_MIB_COUNTER + 0xa0) +#define AN8855_PORT_MIB_RX_OVER_SZ_ERR (AN8855_MIB_COUNTER + 0xa4) +#define AN8855_PORT_MIB_RX_JABBER_ERR (AN8855_MIB_COUNTER + 0xa8) +#define AN8855_PORT_MIB_RX_PAUSE (AN8855_MIB_COUNTER + 0xac) +#define AN8855_PORT_MIB_RX_PKT_SZ_64 (AN8855_MIB_COUNTER + 0xb0) +#define AN8855_PORT_MIB_RX_PKT_SZ_65_TO_127 (AN8855_MIB_COUNTER + 0xb4) +#define AN8855_PORT_MIB_RX_PKT_SZ_128_TO_255 (AN8855_MIB_COUNTER + 0xb8) +#define AN8855_PORT_MIB_RX_PKT_SZ_256_TO_511 (AN8855_MIB_COUNTER + 0xbc) +#define AN8855_PORT_MIB_RX_PKT_SZ_512_TO_1023 (AN8855_MIB_COUNTER + 0xc0) +#define AN8855_PORT_MIB_RX_PKT_SZ_1024_TO_1518 (AN8855_MIB_COUNTER + 0xc= 4) +#define AN8855_PORT_MIB_RX_PKT_SZ_1519_TO_MAX (AN8855_MIB_COUNTER + 0xc8) +#define AN8855_PORT_MIB_RX_BYTES_LOW (AN8855_MIB_COUNTER + 0xcc) /* 64 b= ytes */ +#define AN8855_PORT_MIB_RX_BYTES_HIGH (AN8855_MIB_COUNTER + 0xd0) +#define AN8855_PORT_MIB_RX_CTRL_DROP (AN8855_MIB_COUNTER + 0xd4) +#define AN8855_PORT_MIB_RX_INGRESS_DROP (AN8855_MIB_COUNTER + 0xd8) +#define AN8855_PORT_MIB_RX_ARL_DROP (AN8855_MIB_COUNTER + 0xdc) +#define AN8855_PORT_MIB_FLOW_CONTROL_DROP (AN8855_MIB_COUNTER + 0xe0) +#define AN8855_PORT_MIB_WRED_DROP (AN8855_MIB_COUNTER + 0xe4) +#define AN8855_PORT_MIB_MIRROR_DROP (AN8855_MIB_COUNTER + 0xe8) +#define AN8855_PORT_MIB_RX_BAD_PKT_BYTES_LOW (AN8855_MIB_COUNTER + 0xec)= /* 64 bytes */ +#define AN8855_PORT_MIB_RX_BAD_PKT_BYTES_HIGH (AN8855_MIB_COUNTER + 0xf0) +#define AN8855_PORT_MIB_RXS_FLOW_SAMPLING_PKT_DROP (AN8855_MIB_COUNTER += 0xf4) +#define AN8855_PORT_MIB_RXS_FLOW_TOTAL_PKT_DROP (AN8855_MIB_COUNTER + 0x= f8) +#define AN8855_PORT_MIB_PORT_CONTROL_DROP (AN8855_MIB_COUNTER + 0xfc) +#define AN8855_MIB_CCR 0x10213e30 +#define AN8855_CCR_MIB_ENABLE BIT(31) +#define AN8855_CCR_RX_OCT_CNT_GOOD BIT(7) +#define AN8855_CCR_RX_OCT_CNT_BAD BIT(6) +#define AN8855_CCR_TX_OCT_CNT_GOOD BIT(5) +#define AN8855_CCR_TX_OCT_CNT_BAD BIT(4) +#define AN8855_CCR_RX_OCT_CNT_GOOD_2 BIT(3) +#define AN8855_CCR_RX_OCT_CNT_BAD_2 BIT(2) +#define AN8855_CCR_TX_OCT_CNT_GOOD_2 BIT(1) +#define AN8855_CCR_TX_OCT_CNT_BAD_2 BIT(0) +#define AN8855_CCR_MIB_ACTIVATE (AN8855_CCR_MIB_ENABLE | \ + AN8855_CCR_RX_OCT_CNT_GOOD | \ + AN8855_CCR_RX_OCT_CNT_BAD | \ + AN8855_CCR_TX_OCT_CNT_GOOD | \ + AN8855_CCR_TX_OCT_CNT_BAD | \ + AN8855_CCR_RX_OCT_CNT_BAD_2 | \ + AN8855_CCR_TX_OCT_CNT_BAD_2) +#define AN8855_MIB_CLR 0x10213e34 +#define AN8855_MIB_PORT6_CLR BIT(6) +#define AN8855_MIB_PORT5_CLR BIT(5) +#define AN8855_MIB_PORT4_CLR BIT(4) +#define AN8855_MIB_PORT3_CLR BIT(3) +#define AN8855_MIB_PORT2_CLR BIT(2) +#define AN8855_MIB_PORT1_CLR BIT(1) +#define AN8855_MIB_PORT0_CLR BIT(0) + +/* HSGMII/SGMII Configuration register */ +/* AN8855_HSGMII_AN_CSR_BASE 0x10220000 */ +#define AN8855_SGMII_REG_AN0 0x10220000 +/* AN8855_SGMII_AN_ENABLE BMCR_ANENABLE */ +/* AN8855_SGMII_AN_RESTART BMCR_ANRESTART */ +#define AN8855_SGMII_REG_AN_13 0x10220034 +#define AN8855_SGMII_REMOTE_FAULT_DIS BIT(8) +#define AN8855_SGMII_IF_MODE GENMASK(5, 0) +#define AN8855_SGMII_REG_AN_FORCE_CL37 0x10220060 +#define AN8855_RG_FORCE_AN_DONE BIT(0) + +/* AN8855_HSGMII_CSR_PCS_BASE 0x10220000 */ +#define AN8855_RG_HSGMII_PCS_CTROL_1 0x10220a00 +#define AN8855_RG_TBI_10B_MODE BIT(30) +#define AN8855_RG_AN_SGMII_MODE_FORCE 0x10220a24 +#define AN8855_RG_FORCE_CUR_SGMII_MODE GENMASK(5, 4) +#define AN8855_RG_FORCE_CUR_SGMII_SEL BIT(0) + +/* AN8855_MULTI_SGMII_CSR_BASE 0x10224000 */ +#define AN8855_SGMII_STS_CTRL_0 0x10224018 +#define AN8855_RG_LINK_MODE_P0 GENMASK(5, 4) +#define AN8855_RG_LINK_MODE_P0_SPEED_2500 FIELD_PREP_CONST(AN8855_RG_LIN= K_MODE_P0, 0x3) +#define AN8855_RG_LINK_MODE_P0_SPEED_1000 FIELD_PREP_CONST(AN8855_RG_LIN= K_MODE_P0, 0x2) +#define AN8855_RG_LINK_MODE_P0_SPEED_100 FIELD_PREP_CONST(AN8855_RG_LINK= _MODE_P0, 0x1) +#define AN8855_RG_LINK_MODE_P0_SPEED_10 FIELD_PREP_CONST(AN8855_RG_LINK_= MODE_P0, 0x0) +#define AN8855_RG_FORCE_SPD_MODE_P0 BIT(2) +#define AN8855_MSG_RX_CTRL_0 0x10224100 +#define AN8855_MSG_RX_LIK_STS_0 0x10224514 +#define AN8855_RG_DPX_STS_P3 BIT(24) +#define AN8855_RG_DPX_STS_P2 BIT(16) +#define AN8855_RG_EEE1G_STS_P1 BIT(12) +#define AN8855_RG_DPX_STS_P1 BIT(8) +#define AN8855_RG_TXFC_STS_P0 BIT(2) +#define AN8855_RG_RXFC_STS_P0 BIT(1) +#define AN8855_RG_DPX_STS_P0 BIT(0) +#define AN8855_MSG_RX_LIK_STS_2 0x1022451c +#define AN8855_RG_RXFC_AN_BYPASS_P3 BIT(11) +#define AN8855_RG_RXFC_AN_BYPASS_P2 BIT(10) +#define AN8855_RG_RXFC_AN_BYPASS_P1 BIT(9) +#define AN8855_RG_TXFC_AN_BYPASS_P3 BIT(7) +#define AN8855_RG_TXFC_AN_BYPASS_P2 BIT(6) +#define AN8855_RG_TXFC_AN_BYPASS_P1 BIT(5) +#define AN8855_RG_DPX_AN_BYPASS_P3 BIT(3) +#define AN8855_RG_DPX_AN_BYPASS_P2 BIT(2) +#define AN8855_RG_DPX_AN_BYPASS_P1 BIT(1) +#define AN8855_RG_DPX_AN_BYPASS_P0 BIT(0) +#define AN8855_PHY_RX_FORCE_CTRL_0 0x10224520 +#define AN8855_RG_FORCE_TXC_SEL BIT(4) + +/* AN8855_XFI_CSR_PCS_BASE 0x10225000 */ +#define AN8855_RG_USXGMII_AN_CONTROL_0 0x10225bf8 + +/* AN8855_MULTI_PHY_RA_CSR_BASE 0x10226000 */ +#define AN8855_RG_RATE_ADAPT_CTRL_0 0x10226000 +#define AN8855_RG_RATE_ADAPT_RX_BYPASS BIT(27) +#define AN8855_RG_RATE_ADAPT_TX_BYPASS BIT(26) +#define AN8855_RG_RATE_ADAPT_RX_EN BIT(4) +#define AN8855_RG_RATE_ADAPT_TX_EN BIT(0) +#define AN8855_RATE_ADP_P0_CTRL_0 0x10226100 +#define AN8855_RG_P0_DIS_MII_MODE BIT(31) +#define AN8855_RG_P0_MII_MODE BIT(28) +#define AN8855_RG_P0_MII_RA_RX_EN BIT(3) +#define AN8855_RG_P0_MII_RA_TX_EN BIT(2) +#define AN8855_RG_P0_MII_RA_RX_MODE BIT(1) +#define AN8855_RG_P0_MII_RA_TX_MODE BIT(0) +#define AN8855_MII_RA_AN_ENABLE 0x10226300 +#define AN8855_RG_P0_RA_AN_EN BIT(0) + +/* AN8855_QP_DIG_CSR_BASE 0x1022a000 */ +#define AN8855_QP_CK_RST_CTRL_4 0x1022a310 +#define AN8855_QP_DIG_MODE_CTRL_0 0x1022a324 +#define AN8855_RG_SGMII_MODE GENMASK(5, 4) +#define AN8855_RG_SGMII_AN_EN BIT(0) +#define AN8855_QP_DIG_MODE_CTRL_1 0x1022a330 +#define AN8855_RG_TPHY_SPEED GENMASK(3, 2) + +/* AN8855_SERDES_WRAPPER_BASE 0x1022c000 */ +#define AN8855_USGMII_CTRL_0 0x1022c000 + +/* AN8855_QP_PMA_TOP_BASE 0x1022e000 */ +#define AN8855_PON_RXFEDIG_CTRL_0 0x1022e100 +#define AN8855_RG_QP_EQ_RX500M_CK_SEL BIT(12) +#define AN8855_PON_RXFEDIG_CTRL_9 0x1022e124 +#define AN8855_RG_QP_EQ_LEQOSC_DLYCNT GENMASK(2, 0) + +#define AN8855_SS_LCPLL_PWCTL_SETTING_2 0x1022e208 +#define AN8855_RG_NCPO_ANA_MSB GENMASK(17, 16) +#define AN8855_SS_LCPLL_TDC_FLT_2 0x1022e230 +#define AN8855_RG_LCPLL_NCPO_VALUE GENMASK(30, 0) +#define AN8855_SS_LCPLL_TDC_FLT_5 0x1022e23c +#define AN8855_RG_LCPLL_NCPO_CHG BIT(24) +#define AN8855_SS_LCPLL_TDC_PCW_1 0x1022e248 +#define AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON GENMASK(30, 0) +#define AN8855_INTF_CTRL_8 0x1022e320 +#define AN8855_INTF_CTRL_9 0x1022e324 +#define AN8855_INTF_CTRL_10 0x1022e328 +#define AN8855_RG_DA_QP_TX_FIR_C2_SEL BIT(29) +#define AN8855_RG_DA_QP_TX_FIR_C2_FORCE GENMASK(28, 24) +#define AN8855_RG_DA_QP_TX_FIR_C1_SEL BIT(21) +#define AN8855_RG_DA_QP_TX_FIR_C1_FORCE GENMASK(20, 16) +#define AN8855_INTF_CTRL_11 0x1022e32c +#define AN8855_RG_DA_QP_TX_FIR_C0B_SEL BIT(6) +#define AN8855_RG_DA_QP_TX_FIR_C0B_FORCE GENMASK(5, 0) +#define AN8855_PLL_CTRL_0 0x1022e400 +#define AN8855_RG_PHYA_AUTO_INIT BIT(0) +#define AN8855_PLL_CTRL_2 0x1022e408 +#define AN8855_RG_DA_QP_PLL_SDM_IFM_INTF BIT(30) +#define AN8855_RG_DA_QP_PLL_RICO_SEL_INTF BIT(29) +#define AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF BIT(28) +#define AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF BIT(27) +#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF BIT(26) +#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF GENMASK(25, 24) +#define AN8855_RG_DA_QP_PLL_PCK_SEL_INTF BIT(22) +#define AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF GENMASK(21, 20) +#define AN8855_RG_DA_QP_PLL_IR_INTF GENMASK(19, 16) +#define AN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF BIT(14) +#define AN8855_RG_DA_QP_PLL_FBKSEL_INTF GENMASK(13, 12) +#define AN8855_RG_DA_QP_PLL_BR_INTF GENMASK(10, 8) +#define AN8855_RG_DA_QP_PLL_BPD_INTF GENMASK(7, 6) +#define AN8855_RG_DA_QP_PLL_BPA_INTF GENMASK(4, 2) +#define AN8855_RG_DA_QP_PLL_BC_INTF GENMASK(1, 0) +#define AN8855_PLL_CTRL_3 0x1022e40c +#define AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF GENMASK(31, 16) +#define AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF GENMASK(15, 0) +#define AN8855_PLL_CTRL_4 0x1022e410 +#define AN8855_RG_DA_QP_PLL_SDM_HREN_INTF GENMASK(4, 3) +#define AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF BIT(2) +#define AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF GENMASK(1, 0) +#define AN8855_PLL_CK_CTRL_0 0x1022e414 +#define AN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF BIT(9) +#define AN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF BIT(8) +#define AN8855_RX_DLY_0 0x1022e614 +#define AN8855_RG_QP_RX_SAOSC_EN_H_DLY GENMASK(13, 8) +#define AN8855_RG_QP_RX_PI_CAL_EN_H_DLY GENMASK(7, 0) +#define AN8855_RX_CTRL_2 0x1022e630 +#define AN8855_RG_QP_RX_EQ_EN_H_DLY GENMASK(28, 16) +#define AN8855_RX_CTRL_5 0x1022e63c +#define AN8855_RG_FREDET_CHK_CYCLE GENMASK(29, 10) +#define AN8855_RX_CTRL_6 0x1022e640 +#define AN8855_RG_FREDET_GOLDEN_CYCLE GENMASK(19, 0) +#define AN8855_RX_CTRL_7 0x1022e644 +#define AN8855_RG_FREDET_TOLERATE_CYCLE GENMASK(19, 0) +#define AN8855_RX_CTRL_8 0x1022e648 +#define AN8855_RG_DA_QP_SAOSC_DONE_TIME GENMASK(27, 16) +#define AN8855_RG_DA_QP_LEQOS_EN_TIME GENMASK(14, 0) +#define AN8855_RX_CTRL_26 0x1022e690 +#define AN8855_RG_QP_EQ_RETRAIN_ONLY_EN BIT(26) +#define AN8855_RG_LINK_NE_EN BIT(24) +#define AN8855_RG_LINK_ERRO_EN BIT(23) +#define AN8855_RX_CTRL_42 0x1022e6d0 +#define AN8855_RG_QP_EQ_EN_DLY GENMASK(12, 0) + +/* AN8855_QP_ANA_CSR_BASE 0x1022f000 */ +#define AN8855_RG_QP_RX_DAC_EN 0x1022f000 +#define AN8855_RG_QP_SIGDET_HF GENMASK(17, 16) +#define AN8855_RG_QP_RXAFE_RESERVE 0x1022f004 +#define AN8855_RG_QP_CDR_PD_10B_EN BIT(11) +#define AN8855_RG_QP_CDR_LPF_BOT_LIM 0x1022f008 +#define AN8855_RG_QP_CDR_LPF_KP_GAIN GENMASK(26, 24) +#define AN8855_RG_QP_CDR_LPF_KI_GAIN GENMASK(22, 20) +#define AN8855_RG_QP_CDR_LPF_MJV_LIM 0x1022f00c +#define AN8855_RG_QP_CDR_LPF_RATIO GENMASK(5, 4) +#define AN8855_RG_QP_CDR_LPF_SETVALUE 0x1022f014 +#define AN8855_RG_QP_CDR_PR_BUF_IN_SR GENMASK(31, 29) +#define AN8855_RG_QP_CDR_PR_BETA_SEL GENMASK(28, 25) +#define AN8855_RG_QP_CDR_PR_CKREF_DIV1 0x1022f018 +#define AN8855_RG_QP_CDR_PR_KBAND_DIV GENMASK(26, 24) +#define AN8855_RG_QP_CDR_PR_DAC_BAND GENMASK(12, 8) +#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE 0x1022f01c +#define AN8855_RG_QP_CDR_PR_XFICK_EN BIT(30) +#define AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE BIT(6) +#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK GENMASK(5, 0) +#define AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF 0x1022f020 +#define AN8855_RG_QP_CDR_PHYCK_SEL GENMASK(17, 16) +#define AN8855_RG_QP_CDR_PHYCK_RSTB BIT(13) +#define AN8855_RG_QP_CDR_PHYCK_DIV GENMASK(12, 6) +#define AN8855_RG_QP_TX_MODE 0x1022f028 +#define AN8855_RG_QP_TX_RESERVE GENMASK(31, 16) +#define AN8855_RG_QP_TX_MODE_16B_EN BIT(0) +#define AN8855_RG_QP_PLL_IPLL_DIG_PWR_SEL 0x1022f03c +#define AN8855_RG_QP_PLL_SDM_ORD 0x1022f040 +#define AN8855_RG_QP_PLL_SSC_PHASE_INI BIT(4) +#define AN8855_RG_QP_PLL_SSC_TRI_EN BIT(3) + +/* AN8855_ETHER_SYS_BASE 0x1028c800 */ +#define AN8855_RG_GPHY_AFE_PWD 0x1028c840 +#define AN8855_RG_GPHY_SMI_ADDR 0x1028c848 + +struct an8855_priv { + struct dsa_switch *ds; + struct regmap *regmap; + /* Protect ATU or VLAN table access */ + struct mutex reg_mutex; + + struct phylink_pcs pcs; + + struct mt7530_port ports[AN8855_NUM_PORTS]; + u32 tx_lpi_timer_ports[AN8855_NUM_PORTS]; + + struct mt7530_lib_priv lib_priv; +}; + +#endif /* __AN8855_H */ diff --git a/drivers/net/dsa/mediatek/mt7530-lib.c b/drivers/net/dsa/mediat= ek/mt7530-lib.c index 098dd45d3ee9..432576803332 100644 --- a/drivers/net/dsa/mediatek/mt7530-lib.c +++ b/drivers/net/dsa/mediatek/mt7530-lib.c @@ -423,9 +423,11 @@ int mt7530_lib_fdb_cmd(struct mt7530_lib_priv *priv, e= num mt7530_fdb_cmd cmd, return ret; } =20 - regmap_field_read(priv->fields[MT7530_ATC_INVALID], &val); - if (cmd =3D=3D MT7530_FDB_READ && val) - return -EINVAL; + if (priv->fields[MT7530_ATC_INVALID]) { + regmap_field_read(priv->fields[MT7530_ATC_INVALID], &val); + if (cmd =3D=3D MT7530_FDB_READ && val) + return -EINVAL; + } =20 if (rsp) regmap_field_read(priv->fields[__MT7530_ATC], rsp); @@ -442,6 +444,8 @@ static void mt7530_lib_fdb_write(struct mt7530_lib_priv= *priv, u16 vid, regmap_field_write(priv->fields[__MT7530_ATWD1], 0); regmap_field_write(priv->fields[__MT7530_ATWD2], 0); regmap_field_write(priv->fields[__MT7530_ATWD3], 0); + if (priv->fields[__MT7530_ATWD4]) + regmap_field_write(priv->fields[__MT7530_ATWD4], 0); =20 regmap_field_write(priv->fields[MT7530_ATWD_CVID], vid); regmap_field_write(priv->fields[MT7530_ATWD_IVL], 1); @@ -452,7 +456,17 @@ static void mt7530_lib_fdb_write(struct mt7530_lib_pri= v *priv, u16 vid, * be aged out and STATIC_EMP specified as erasing an * entry */ - regmap_field_write(priv->fields[MT7530_ATWD_ENT_STATUS], type); + if (priv->fields[MT7530_ATWD_ENT_STATUS]) + regmap_field_write(priv->fields[MT7530_ATWD_ENT_STATUS], type); + if (priv->fields[AN8855_ATWD_TYPE]) { + /* Default to static entry (0) */ + regmap_field_write(priv->fields[AN8855_ATWD_TYPE], 0); + } + if (priv->fields[AN8855_ATWD_VLD]) { + /* Load entry if STATIC_ENT */ + regmap_field_write(priv->fields[AN8855_ATWD_VLD], + type =3D=3D STATIC_ENT); + } regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_5], mac[5]); regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_4], mac[4]); regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_3], mac[3]); @@ -483,8 +497,14 @@ void mt7530_lib_fdb_read(struct mt7530_lib_priv *priv,= struct mt7530_fdb *fdb) fdb->mac[1] =3D val; regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_0], &val); fdb->mac[0] =3D val; - regmap_field_read(priv->fields[MT7530_ATRD_ENT_STATUS], &val); - fdb->noarp =3D val =3D=3D STATIC_ENT; + if (priv->fields[MT7530_ATRD_ENT_STATUS]) { + regmap_field_read(priv->fields[MT7530_ATRD_ENT_STATUS], &val); + fdb->noarp =3D val =3D=3D STATIC_ENT; + } + if (priv->fields[AN8855_ATRD_ARP]) { + regmap_field_read(priv->fields[AN8855_ATRD_ARP], &val); + fdb->noarp =3D !!val; + } } EXPORT_SYMBOL_GPL(mt7530_lib_fdb_read); =20 @@ -787,6 +807,17 @@ void mt7530_lib_port_bridge_leave(struct mt7530_lib_pr= iv *priv, int port, } EXPORT_SYMBOL_GPL(mt7530_lib_port_bridge_leave); =20 +void mt7530_port_set_pvid(struct mt7530_lib_priv *priv, int port, + u16 pvid) +{ + regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID], + port, pvid); + if (priv->fields[AN8855_PVID_G0_PORT_VID]) + regmap_fields_write(priv->fields[AN8855_PVID_G0_PORT_VID], + port, pvid); +} +EXPORT_SYMBOL_GPL(mt7530_port_set_pvid); + static void mt7530_port_set_vlan_unaware(struct mt7530_lib_priv *priv, int= port) { struct dsa_switch *ds =3D priv->ds; @@ -807,8 +838,7 @@ static void mt7530_port_set_vlan_unaware(struct mt7530_= lib_priv *priv, int port) regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM], port, MT7530_VLAN_ACC_ALL); =20 - regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID], - port, G0_PORT_VID_DEF); + mt7530_port_set_pvid(priv, port, G0_PORT_VID_DEF); =20 for (i =3D 0; i < priv->ds->num_ports; i++) { if (i =3D=3D port) @@ -840,8 +870,7 @@ static void mt7530_port_set_vlan_aware(struct mt7530_li= b_priv *priv, int port) if (dsa_is_user_port(ds, port)) { regmap_fields_write(priv->fields[MT7530_PCR_PORT_VLAN], port, MT7530_PORT_SECURITY_MODE); - regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID], - port, priv->ports[port].pvid); + mt7530_port_set_pvid(priv, port, priv->ports[port].pvid); =20 /* Only accept tagged frames if PVID is not set */ if (!priv->ports[port].pvid) @@ -919,10 +948,12 @@ static int mt7530_vlan_cmd(struct mt7530_lib_priv *pr= iv, enum mt7530_vlan_cmd cm return ret; } =20 - regmap_field_read(priv->fields[MT7530_VTCR_INVALID], &val); - if (val) { - dev_err(priv->dev, "read VTCR invalid\n"); - return -EINVAL; + if (priv->fields[MT7530_VTCR_INVALID]) { + regmap_field_read(priv->fields[MT7530_VTCR_INVALID], &val); + if (val) { + dev_err(priv->dev, "read VTCR invalid\n"); + return -EINVAL; + } } =20 return 0; @@ -1044,8 +1075,7 @@ int mt7530_lib_port_vlan_add(struct mt7530_lib_priv *= priv, int port, =20 /* Only configure PVID if VLAN filtering is enabled */ if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) - regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID], - port, vlan->vid); + mt7530_port_set_pvid(priv, port, vlan->vid); } else if (vlan->vid && priv->ports[port].pvid =3D=3D vlan->vid) { /* This VLAN is overwritten without PVID, so unset it */ priv->ports[port].pvid =3D G0_PORT_VID_DEF; @@ -1055,8 +1085,7 @@ int mt7530_lib_port_vlan_add(struct mt7530_lib_priv *= priv, int port, regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM], port, MT7530_VLAN_ACC_TAGGED); =20 - regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID], - port, G0_PORT_VID_DEF); + mt7530_port_set_pvid(priv, port, G0_PORT_VID_DEF); } =20 mutex_unlock(priv->reg_mutex); @@ -1093,8 +1122,7 @@ int mt7530_lib_port_vlan_del(struct mt7530_lib_priv *= priv, int port, regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM], port, MT7530_VLAN_ACC_TAGGED); =20 - regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID], - port, G0_PORT_VID_DEF); + mt7530_port_set_pvid(priv, port, G0_PORT_VID_DEF); } =20 mutex_unlock(priv->reg_mutex); diff --git a/drivers/net/dsa/mediatek/mt7530-lib.h b/drivers/net/dsa/mediat= ek/mt7530-lib.h index da2ee781f7e6..1465eb49f4cb 100644 --- a/drivers/net/dsa/mediatek/mt7530-lib.h +++ b/drivers/net/dsa/mediatek/mt7530-lib.h @@ -159,6 +159,8 @@ enum mt7530_regmap_field { MT7530_ATWD_AGE_TIMER, MT7530_ATWD_PORT_MAP, MT7530_ATWD_ENT_STATUS, + AN8855_ATWD_TYPE, + AN8855_ATWD_VLD, MT7530_ATWD_MAC_BYTE_5, MT7530_ATWD_MAC_BYTE_4, MT7530_ATWD_MAC_BYTE_3, @@ -169,11 +171,13 @@ enum mt7530_regmap_field { __MT7530_ATWD1, __MT7530_ATWD2, __MT7530_ATWD3, + __MT7530_ATWD4, =20 MT7530_ATRD_CVID, MT7530_ATRD_AGE_TIMER, MT7530_ATRD_PORT_MAP, MT7530_ATRD_ENT_STATUS, + AN8855_ATRD_ARP, MT7530_ATRD_MAC_BYTE_5, MT7530_ATRD_MAC_BYTE_4, MT7530_ATRD_MAC_BYTE_3, @@ -201,6 +205,7 @@ enum mt7530_regmap_field { MT7530_PVC_ACC_FRM, =20 MT7530_PPBV1_G0_PORT_VID, + AN8855_PVID_G0_PORT_VID, =20 MT7530_GMACCR_MAX_RX_JUMBO, MT7530_GMACCR_MAX_RX_PKT_LEN, @@ -223,8 +228,13 @@ enum mt7530_regmap_field { MT7530_MIB_TX_PKT_SZ_256_TO_511, MT7530_MIB_TX_PKT_SZ_512_TO_1023, MT7530_MIB_TX_PKT_SZ_1024_TO_MAX, + AN8855_MIB_TX_PKT_SZ_1024_TO_1518, + AN8855_MIB_TX_PKT_SZ_1519_TO_MAX, MT7530_MIB_TX_BYTES_LOW, MT7530_MIB_TX_BYTES_HIGH, + AN8855_MIB_TX_OVERSIZE_DROP, + AN8855_MIB_TX_BAD_PKT_BYTES_LOW, + AN8855_MIB_TX_BAD_PKT_BYTES_HIGH, MT7530_MIB_RX_DROP, MT7530_MIB_RX_FILTERING, MT7530_MIB_RX_UNICAST, @@ -243,11 +253,21 @@ enum mt7530_regmap_field { MT7530_MIB_RX_PKT_SZ_256_TO_511, MT7530_MIB_RX_PKT_SZ_512_TO_1023, MT7530_MIB_RX_PKT_SZ_1024_TO_MAX, + AN8855_MIB_RX_PKT_SZ_1024_TO_1518, + AN8855_MIB_RX_PKT_SZ_1519_TO_MAX, MT7530_MIB_RX_BYTES_LOW, MT7530_MIB_RX_BYTES_HIGH, MT7530_MIB_RX_CTRL_DROP, MT7530_MIB_RX_INGRESS_DROP, MT7530_MIB_RX_ARL_DROP, + AN8855_MIB_FLOW_CONTROL_DROP, + AN8855_MIB_WRED_DROP, + AN8855_MIB_MIRROR_DROP, + AN8855_MIB_RX_BAD_PKT_BYTES_LOW, + AN8855_MIB_RX_BAD_PKT_BYTES_HIGH, + AN8855_MIB_RXS_FLOW_SAMPLING_PKT_DROP, + AN8855_MIB_RXS_FLOW_TOTAL_PKT_DROP, + AN8855_MIB_PORT_CONTROL_DROP, =20 MT7530_FIELD_MAX, }; @@ -385,6 +405,8 @@ int mt7530_lib_port_vlan_add(struct mt7530_lib_priv *pr= iv, int port, int mt7530_lib_port_vlan_del(struct mt7530_lib_priv *priv, int port, const struct switchdev_obj_port_vlan *vlan); =20 +void mt7530_port_set_pvid(struct mt7530_lib_priv *priv, int port, + u16 pvid); int mt7530_lib_setup_vlan0(struct mt7530_lib_priv *priv); =20 #endif /* __MT7530_LIB_H */ --=20 2.55.0