From nobody Tue Sep 29 01:19:59 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26B5A451984; Mon, 28 Sep 2026 07:05:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790579108; cv=none; b=Kz0OxNomVXLlH2nHxO8rBWOtP+0rzYH52CeoqLUDxDqRlbpHR/RHyl8VMm4I2UHK4FZAVyB2GcdofRnDrY1I4JWY0a4vI6KBzE/Ec99FKrs/yspkGjQ3KOPPPMoI4w9iSDEuH5xNu4m6CS9sdzlaCk+ORlNaDSWmk+eupiGg5Q8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790579108; c=relaxed/simple; bh=asXPlzA7QIDHdtrr35/fv75lpza8r1s5+y9QDxEQODg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BhOPMmlWCt7cJRnZlyzIYPU0uyaoUVni/w8mRIJyLVgwj00UyqDL2QBaWgyNteP2Gs6kuRoCVsQab0Mu1OnuGNCe7jLB35TlTR7andDW5YDsyxgCRAQZrkVUy7eMI4dmbST0dkAyScY4lKwce+2X+Y5MxGDGh7wlXZSXaqRcTDI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realsil.com.cn; spf=pass smtp.mailfrom=realsil.com.cn; dkim=pass (2048-bit key) header.d=realsil.com.cn header.i=@realsil.com.cn header.b=UY7towOn; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realsil.com.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realsil.com.cn Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realsil.com.cn header.i=@realsil.com.cn header.b="UY7towOn" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 68S74PmuC217875, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realsil.com.cn; s=dkim; t=1790579066; bh=6hgB1DO70FWHWklgzOCrY48uKctpThzV7m6dvh7UrQg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=UY7towOnUwVCYQeFGn1W5T8UpLvEtSc4fzmYpiMbN4Bb2iUKuyM+oHH7JjokPRGzl Ck9ae0Pxu3dslpTZzA9reotP/iqoEFDA6R1MlME0Mtkb8N3XOfoF18gXuH1qrh2r6F aLBCPKZt+MUfBAkte2HVhRlgDaiAftH1hGcaofG5XAsGHVnMWvG4wGxUaP+ci/MaDm ITREM7ji4YdjTHxvf6szNAQ2zMmmnC/RmIqo7adlahNGluDfT8wk2iACrUb4h7PaNk LQleO0klUOis0Uct5vaZFcVQPWtkTJlRTPT84A0b0uzg/WVs0CJS54kOaY7c7xWxfj RS4F3JkdBhcQg== Received: from RS-EX-MBS2.realsil.com.cn ([172.29.17.102]) by rtits2.realtek.com.tw (8.15.2/3.29/5.94) with ESMTPS id 68S74PmuC217875 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 28 Sep 2026 15:04:25 +0800 Received: from RS-EX-MBS2.realsil.com.cn (172.29.17.102) by RS-EX-MBS2.realsil.com.cn (172.29.17.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Mon, 28 Sep 2026 15:04:25 +0800 Received: from 172.29.37.154 (172.29.37.152) by RS-EX-MBS2.realsil.com.cn (172.29.17.102) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Mon, 28 Sep 2026 15:04:25 +0800 From: javen To: , , , , , , , CC: , , Javen Xu Subject: [PATCH net-next v15 1/7] r8169: prepare for multi irqs and napi Date: Mon, 28 Sep 2026 15:04:17 +0800 Message-ID: <20260928070423.202-2-javen_xu@realsil.com.cn> X-Mailer: git-send-email 2.50.1.windows.1 In-Reply-To: <20260928070423.202-1-javen_xu@realsil.com.cn> References: <20260928070423.202-1-javen_xu@realsil.com.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Javen Xu This patch converts the single struct napi_struct into a dynamically allocated array indexed by IRQ. This is a preparation step for adding RSS support. Currently, irq_nvecs and num_rx_rings are still hard-coded to 1, so there is no functional change. Signed-off-by: Javen Xu --- Changes in v2: - remove some unused definitions, such as index, name in rtl8169_irq - remove array imr and isr - remove min_irq_nvecs and max_irq_nvecs, replaced with help function get_min_irq_nvecs and get_max_irq_nvecs - alloc irq by flags, instead of PCI_IRQ_ALL_TYPES Changes in v3: - add enum rtl_isr_version to replace macro definition - remove struct rtl8169_napi, use napi_struct array instead and alloc memory for this array dynamically - remove struct rtl8169_irq Changes in v4: - change retval to ret in rtl8169_set_real_num_queue() - reverse xmas tree in rtl8169_poll() and rtl8169_interrupt() - remove tp->hw_supp_isr_ver Changes in v5: - rtl8169_request_irq(), when failed, only free irqs which are allocated - remove rss_support, simplied napi init, call r8169_init_napi() directly - remove rtl_isr_version, INTR_VEC_MAP_MASK, INTR_VEC_MAP_STATUS, R8169_MAX_MSIX_VEC, rss_enable, recheck_desc_ownbit - rtl_software_parameter_initialize() this function will be expanded in next patch, so i want to remain it here. Changes in v6: - Fix netpoll crash - Fix use-after-free during driver unload by registering a devm action for netif_napi_del() - remove tp->irq Changes in v7: - pass NAPI as arg to rtl_rx() - use netif_set_real_num_queues to replace rtl8169_set_real_num_queues - replace rtl_software_parameter_initialize with rtl_setup_rx_params Changes in v8: - no changes Changes in v9: - no changes Changes in v10: - no changes Changes in v11: - no changes Changes in v12: - no changes Changes in v13: - Fix sleep-in-atomic bug in netpoll by passing 0 to rtl8169_interrupt() - call netif_napi_set_irq() to properly associate NAPI with IRQ vector - Fix print format for unsigned int tp->irq_nvecs from %d to %u Changes in v14: - modify commit message and patch title - fall back to request_irq() + pci_irq_vector() instead of pci_request_irq() to avoid dropping IRQF_NO_THREAD flag for MSI/MSI-X - add phylink_destory() in NAPI kcalloc failure path Changes in v15: - no changes --- drivers/net/ethernet/realtek/r8169_main.c | 165 ++++++++++++++++++---- 1 file changed, 136 insertions(+), 29 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethern= et/realtek/r8169_main.c index 5415ff62a286..a8214c48a775 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -761,7 +761,6 @@ struct rtl8169_private { struct pci_dev *pci_dev; struct net_device *dev; struct phy_device *phydev; - struct napi_struct napi; enum mac_version mac_version; enum rtl_dash_type dash_type; enum rtl_sfp_mode sfp_mode; @@ -774,10 +773,12 @@ struct rtl8169_private { dma_addr_t RxPhyAddr; struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ + struct napi_struct *rtl8169_napi; + unsigned int num_rx_rings; u16 cp_cmd; u16 tx_lpi_timer; u32 irq_mask; - int irq; + unsigned int irq_nvecs; struct clk *clk; int speed; =20 @@ -2769,6 +2770,11 @@ static void rtl_hw_reset(struct rtl8169_private *tp) rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); } =20 +static void rtl_setup_rx_params(struct rtl8169_private *tp) +{ + tp->num_rx_rings =3D 1; +} + static void rtl_request_firmware(struct rtl8169_private *tp) { struct rtl_fw *rtl_fw; @@ -4431,9 +4437,21 @@ static void rtl8169_tx_clear(struct rtl8169_private = *tp) netdev_reset_queue(tp->dev); } =20 +static void rtl8169_napi_disable(struct rtl8169_private *tp) +{ + for (int i =3D 0; i < tp->irq_nvecs; i++) + napi_disable(&tp->rtl8169_napi[i]); +} + +static void rtl8169_napi_enable(struct rtl8169_private *tp) +{ + for (int i =3D 0; i < tp->irq_nvecs; i++) + napi_enable(&tp->rtl8169_napi[i]); +} + static void rtl8169_cleanup(struct rtl8169_private *tp) { - napi_disable(&tp->napi); + rtl8169_napi_disable(tp); =20 /* Give a racing hard_start_xmit a few cycles to complete. */ synchronize_net(); @@ -4479,7 +4497,7 @@ static void rtl_reset_work(struct rtl8169_private *tp) for (i =3D 0; i < NUM_RX_DESC; i++) rtl8169_mark_to_asic(tp->RxDescArray + i); =20 - napi_enable(&tp->napi); + rtl8169_napi_enable(tp); rtl_hw_start(tp); } =20 @@ -4933,7 +4951,8 @@ static inline void rtl8169_rx_csum(struct sk_buff *sk= b, u32 opts1) skb_checksum_none_assert(skb); } =20 -static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int = budget) +static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, + int budget, struct napi_struct *napi) { struct device *d =3D tp_to_dev(tp); int count; @@ -4985,7 +5004,7 @@ static int rtl_rx(struct net_device *dev, struct rtl8= 169_private *tp, int budget goto release_descriptor; } =20 - skb =3D napi_alloc_skb(&tp->napi, pkt_size); + skb =3D napi_alloc_skb(napi, pkt_size); if (unlikely(!skb)) { dev->stats.rx_dropped++; goto release_descriptor; @@ -5009,7 +5028,7 @@ static int rtl_rx(struct net_device *dev, struct rtl8= 169_private *tp, int budget if (skb->pkt_type =3D=3D PACKET_MULTICAST) dev->stats.multicast++; =20 - napi_gro_receive(&tp->napi, skb); + napi_gro_receive(napi, skb); =20 dev_sw_netstats_rx_add(dev, pkt_size); release_descriptor: @@ -5021,8 +5040,12 @@ static int rtl_rx(struct net_device *dev, struct rtl= 8169_private *tp, int budget =20 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) { - struct rtl8169_private *tp =3D dev_instance; - u32 status =3D rtl_get_events(tp); + struct napi_struct *napi =3D dev_instance; + struct rtl8169_private *tp; + u32 status; + + tp =3D netdev_priv(napi->dev); + status =3D rtl_get_events(tp); =20 if ((status & 0xffff) =3D=3D 0xffff || !(status & tp->irq_mask)) return IRQ_NONE; @@ -5043,13 +5066,55 @@ static irqreturn_t rtl8169_interrupt(int irq, void = *dev_instance) } =20 rtl_irq_disable(tp); - napi_schedule(&tp->napi); + napi_schedule(napi); out: rtl_ack_events(tp, status); =20 return IRQ_HANDLED; } =20 +static void rtl8169_free_irq(struct rtl8169_private *tp) +{ + struct pci_dev *pdev =3D tp->pci_dev; + int i, irq; + + for (i =3D 0; i < tp->irq_nvecs; i++) { + struct napi_struct *napi =3D &tp->rtl8169_napi[i]; + + irq =3D pci_irq_vector(pdev, i); + free_irq(irq, napi); + } +} + +static int rtl8169_request_irq(struct rtl8169_private *tp) +{ + struct pci_dev *pdev =3D tp->pci_dev; + struct net_device *dev =3D tp->dev; + struct napi_struct *napi; + unsigned long irqflags; + int i, rc, irq; + + irqflags =3D pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; + + for (i =3D 0; i < tp->irq_nvecs; i++) { + napi =3D &tp->rtl8169_napi[i]; + irq =3D pci_irq_vector(pdev, i); + + rc =3D request_irq(irq, rtl8169_interrupt, irqflags, + dev->name, napi); + if (rc) + goto free_irq; + } + return 0; + +free_irq: + while (--i >=3D 0) { + irq =3D pci_irq_vector(pdev, i); + free_irq(irq, &tp->rtl8169_napi[i]); + } + return rc; +} + static void rtl_task(struct work_struct *work) { struct rtl8169_private *tp =3D @@ -5084,13 +5149,13 @@ static void rtl_task(struct work_struct *work) =20 static int rtl8169_poll(struct napi_struct *napi, int budget) { - struct rtl8169_private *tp =3D container_of(napi, struct rtl8169_private,= napi); - struct net_device *dev =3D tp->dev; - int work_done; + struct rtl8169_private *tp =3D netdev_priv(napi->dev); + struct net_device *dev =3D napi->dev; + int work_done =3D 0; =20 rtl_tx(dev, tp, budget); =20 - work_done =3D rtl_rx(dev, tp, budget); + work_done =3D rtl_rx(dev, tp, budget, napi); =20 if (work_done < budget && napi_complete_done(napi, work_done)) rtl_irq_enable(tp); @@ -5175,7 +5240,7 @@ static void rtl8169_up(struct rtl8169_private *tp) if (tp->phydev) rtl8169_init_phy(tp); =20 - napi_enable(&tp->napi); + rtl8169_napi_enable(tp); enable_work(&tp->wk.work); rtl_reset_work(tp); } @@ -5192,7 +5257,7 @@ static int rtl8169_close(struct net_device *dev) rtl8169_down(tp); rtl8169_rx_clear(tp); =20 - free_irq(tp->irq, tp); + rtl8169_free_irq(tp); =20 phylink_disconnect_phy(tp->phylink); =20 @@ -5213,7 +5278,8 @@ static void rtl8169_netpoll(struct net_device *dev) { struct rtl8169_private *tp =3D netdev_priv(dev); =20 - rtl8169_interrupt(tp->irq, tp); + for (int i =3D 0; i < tp->irq_nvecs; i++) + rtl8169_interrupt(0, &tp->rtl8169_napi[i]); } #endif =20 @@ -5221,7 +5287,6 @@ static int rtl_open(struct net_device *dev) { struct rtl8169_private *tp =3D netdev_priv(dev); struct pci_dev *pdev =3D tp->pci_dev; - unsigned long irqflags; int retval =3D -ENOMEM; =20 pm_runtime_get_sync(&pdev->dev); @@ -5246,8 +5311,7 @@ static int rtl_open(struct net_device *dev) =20 rtl_request_firmware(tp); =20 - irqflags =3D pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; - retval =3D request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, t= p); + retval =3D rtl8169_request_irq(tp); if (retval < 0) goto err_release_fw_2; =20 @@ -5266,7 +5330,7 @@ static int rtl_open(struct net_device *dev) return retval; =20 err_free_irq: - free_irq(tp->irq, tp); + rtl8169_free_irq(tp); err_release_fw_2: rtl_release_firmware(tp); rtl8169_rx_clear(tp); @@ -5419,6 +5483,14 @@ static void rtl_shutdown(struct pci_dev *pdev) pci_prepare_to_sleep(pdev); } =20 +static void r8169_free_napi(struct rtl8169_private *tp) +{ + for (int i =3D 0; i < tp->irq_nvecs; i++) + netif_napi_del(&tp->rtl8169_napi[i]); + + kfree(tp->rtl8169_napi); +} + static void rtl_remove_one(struct pci_dev *pdev) { struct rtl8169_private *tp =3D pci_get_drvdata(pdev); @@ -5432,6 +5504,7 @@ static void rtl_remove_one(struct pci_dev *pdev) r8169_remove_leds(tp->leds); =20 unregister_netdev(tp->dev); + r8169_free_napi(tp); phylink_destroy(tp->phylink); =20 if (tp->dash_type !=3D RTL_DASH_NONE) @@ -5473,7 +5546,9 @@ static void rtl_set_irq_mask(struct rtl8169_private *= tp) =20 static int rtl_alloc_irq(struct rtl8169_private *tp) { + struct pci_dev *pdev =3D tp->pci_dev; unsigned int flags; + int nvecs; =20 switch (tp->mac_version) { case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: @@ -5489,7 +5564,14 @@ static int rtl_alloc_irq(struct rtl8169_private *tp) break; } =20 - return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); + nvecs =3D pci_alloc_irq_vectors(pdev, 1, 1, flags); + + if (nvecs < 0) + return nvecs; + + tp->irq_nvecs =3D nvecs; + + return 0; } =20 static void rtl_read_mac_address(struct rtl8169_private *tp, @@ -6005,6 +6087,15 @@ static int rtl_init_phylink(struct rtl8169_private *= tp) return 0; } =20 +static void r8169_init_napi(struct rtl8169_private *tp) +{ + for (int i =3D 0; i < tp->irq_nvecs; i++) { + netif_napi_add(tp->dev, &tp->rtl8169_napi[i], rtl8169_poll); + netif_napi_set_irq(&tp->rtl8169_napi[i], + pci_irq_vector(tp->pci_dev, i)); + } +} + static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *= ent) { const struct rtl_chip_info *chip; @@ -6105,12 +6196,12 @@ static int rtl_init_one(struct pci_dev *pdev, const= struct pci_device_id *ent) =20 rtl_hw_reset(tp); =20 + rtl_setup_rx_params(tp); + rc =3D rtl_alloc_irq(tp); if (rc < 0) return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); =20 - tp->irq =3D pci_irq_vector(pdev, 0); - INIT_WORK(&tp->wk.work, rtl_task); disable_work(&tp->wk.work); =20 @@ -6118,8 +6209,6 @@ static int rtl_init_one(struct pci_dev *pdev, const s= truct pci_device_id *ent) =20 dev->ethtool_ops =3D &rtl8169_ethtool_ops; =20 - netif_napi_add(dev, &tp->napi, rtl8169_poll); - dev->hw_features =3D NETIF_F_IP_CSUM | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; dev->vlan_features =3D NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; @@ -6180,6 +6269,10 @@ static int rtl_init_one(struct pci_dev *pdev, const = struct pci_device_id *ent) if (jumbo_max) dev->max_mtu =3D jumbo_max; =20 + rc =3D netif_set_real_num_queues(tp->dev, 1, tp->num_rx_rings); + if (rc < 0) + return dev_err_probe(&pdev->dev, rc, "set tx/rx num failure\n"); + rtl_set_irq_mask(tp); =20 tp->counters =3D dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), @@ -6202,10 +6295,19 @@ static int rtl_init_one(struct pci_dev *pdev, const= struct pci_device_id *ent) } } =20 + tp->rtl8169_napi =3D kcalloc(tp->irq_nvecs, sizeof(struct napi_struct), + GFP_KERNEL); + if (!tp->rtl8169_napi) { + phylink_destroy(tp->phylink); + return -ENOMEM; + } + + r8169_init_napi(tp); + rc =3D register_netdev(dev); if (rc) { phylink_destroy(tp->phylink); - return rc; + goto err_free_napi; } =20 if (IS_ENABLED(CONFIG_R8169_LEDS)) { @@ -6215,8 +6317,9 @@ static int rtl_init_one(struct pci_dev *pdev, const s= truct pci_device_id *ent) tp->leds =3D rtl8168_init_leds(dev); } =20 - netdev_info(dev, "%s, %pM, %sXID %x, IRQ %d\n", - chip->name, dev->dev_addr, ext_xid_str, xid, tp->irq); + netdev_info(dev, "%s, %pM, %sXID %x, IRQ %d (%u total)\n", + chip->name, dev->dev_addr, ext_xid_str, xid, + pci_irq_vector(pdev, 0), tp->irq_nvecs); =20 if (jumbo_max) netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]= \n", @@ -6236,6 +6339,10 @@ static int rtl_init_one(struct pci_dev *pdev, const = struct pci_device_id *ent) pm_runtime_put_sync(&pdev->dev); =20 return 0; + +err_free_napi: + r8169_free_napi(tp); + return rc; } =20 static struct pci_driver rtl8169_pci_driver =3D { --=20 2.43.0 From nobody Tue Sep 29 01:19:59 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F5DF455171; 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Mon, 28 Sep 2026 15:04:26 +0800 Received: from RS-EX-MBS2.realsil.com.cn (172.29.17.102) by RS-EX-MBS2.realsil.com.cn (172.29.17.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Mon, 28 Sep 2026 15:04:25 +0800 Received: from 172.29.37.154 (172.29.37.152) by RS-EX-MBS2.realsil.com.cn (172.29.17.102) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Mon, 28 Sep 2026 15:04:25 +0800 From: javen To: , , , , , , , CC: , , Javen Xu Subject: [PATCH net-next v15 2/7] r8169: refactor RX path to prepare for multi-queue Date: Mon, 28 Sep 2026 15:04:18 +0800 Message-ID: <20260928070423.202-3-javen_xu@realsil.com.cn> X-Mailer: git-send-email 2.50.1.windows.1 In-Reply-To: <20260928070423.202-1-javen_xu@realsil.com.cn> References: <20260928070423.202-1-javen_xu@realsil.com.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Javen Xu This patch is a preparatory refactoring of the RX path. It introduces struct rtl8169_rx_ring and turns the previously embedded RX state in rtl8169_private into a per-queue array. While the netdev allocation is changed to devm_alloc_etherdev_mqs() with up to 8 RX queues, the actual number of active RX rings (num_rx_rings) is currently kept at 1. The actual multi-queue operation and RSS enablement will be introduced in subsequent patches. Signed-off-by: Javen Xu --- Changes in v2: - sort some registers by its number - remove some unused definitions, like RX_DESC_RING_TYPE_MAX - change recheck_desc_ownbit type - remove rdsar_reg in rx_ring struct - opts1 are different in rx_desc and rx_desc_rss, move the judgement to Patch 5/7 Changes in v3: - remove ring->rx_desc_alloc_size, use constant instead Changes in v4: - change rdsar_reg type to unsigned int - follow reverse xmas tree, in rtl_set_rx_tx_desc_registers(), rtl8169_alloc_rx_data(), rtl8169_alloc_rx_desc(), rtl8169_free_rx_desc() - add comments on LED_CTRL, remove helper function Changes in v5: - modify rtl8169_init_ring(), do rx clear when failed - add definition R8169_MAX_TX_QUEUES 1 Changes in v6: - Restore the secondary Rx error filter when NETIF_F_RXFALL is enabled in rtl_rx() Changes in v7: - remove code associated with recheck_desc_ownbit Changes in v8: - remove le64_to_cpu() for addr, rx get addr from rx_desc_phy_addr Changes in v9: - remove R8127_MAX_RX_QUEUES - remvoe rx_desc_ring_type to the following patch - Fix loop bound in init_ring_indexes - Restore checksum API Changes in v10: - alloc rtl8169_rx_ring struct according to the num_rx_ring dynamically Changes in v11: - leak rx_ring array on driver removal Changes in v12: - no changes Changes in v13: - remove unused dirty_rx Changes in v14: - REvert R8169_RX_RING_BYTES padding changes. It will be split into a bugfix patch. - Fix phylink memory in rtl_init_one() by implementing a proper goto unwind laber (err_destory_phylink) for memory allocation failures. =20 Changes in v15: - no changes --- drivers/net/ethernet/realtek/r8169_main.c | 244 +++++++++++++++++----- 1 file changed, 186 insertions(+), 58 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethern= et/realtek/r8169_main.c index a8214c48a775..7a2e7ce56e48 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -74,9 +74,13 @@ #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) + #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) +#define R8169_MAX_RX_QUEUES 8 +#define R8169_DEFAULT_RX_QUEUES 1 +#define R8169_MAX_TX_QUEUES 1 =20 #define OCP_STD_PHY_BASE 0xa400 =20 @@ -463,6 +467,7 @@ enum rtl8125_registers { TxPoll_8125 =3D 0x90, LEDSEL3 =3D 0x96, MAC0_BKP =3D 0x19e0, + RDSAR_Q1_LOW =3D 0x4000, RSS_CTRL_8125 =3D 0x4500, Q_NUM_CTRL_8125 =3D 0x4800, EEE_TXIDLE_TIMER_8125 =3D 0x6048, @@ -750,6 +755,14 @@ enum rtl_dash_type { RTL_DASH_25_BP, }; =20 +struct rtl8169_rx_ring { + u32 cur_rx; + struct RxDesc *rx_desc_array; + dma_addr_t rx_desc_phy_addr[NUM_RX_DESC]; + dma_addr_t rx_phy_addr; + struct page *rx_databuff[NUM_RX_DESC]; +}; + enum rtl_sfp_mode { RTL_SFP_NONE, RTL_SFP_8168_AF, @@ -764,20 +777,18 @@ struct rtl8169_private { enum mac_version mac_version; enum rtl_dash_type dash_type; enum rtl_sfp_mode sfp_mode; - u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ u32 dirty_tx; struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ - struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ dma_addr_t TxPhyAddr; - dma_addr_t RxPhyAddr; - struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ struct napi_struct *rtl8169_napi; + struct rtl8169_rx_ring *rx_ring; unsigned int num_rx_rings; u16 cp_cmd; u16 tx_lpi_timer; u32 irq_mask; + unsigned int hw_supp_num_rx_queues; unsigned int irq_nvecs; struct clk *clk; int speed; @@ -2718,9 +2729,25 @@ static void rtl_init_rxcfg(struct rtl8169_private *t= p) } } =20 +static void rtl8169_rx_desc_init(struct rtl8169_private *tp) +{ + for (int i =3D 0; i < tp->num_rx_rings; i++) { + struct rtl8169_rx_ring *ring =3D &tp->rx_ring[i]; + + memset(ring->rx_desc_array, 0x0, R8169_RX_RING_BYTES); + } +} + static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) { - tp->dirty_tx =3D tp->cur_tx =3D tp->cur_rx =3D 0; + tp->dirty_tx =3D 0; + tp->cur_tx =3D 0; + + for (int i =3D 0; i < tp->num_rx_rings; i++) { + struct rtl8169_rx_ring *ring =3D &tp->rx_ring[i]; + + ring->cur_rx =3D 0; + } } =20 static void rtl_jumbo_config(struct rtl8169_private *tp) @@ -2773,6 +2800,14 @@ static void rtl_hw_reset(struct rtl8169_private *tp) static void rtl_setup_rx_params(struct rtl8169_private *tp) { tp->num_rx_rings =3D 1; + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_80: + tp->hw_supp_num_rx_queues =3D R8169_MAX_RX_QUEUES; + break; + default: + tp->hw_supp_num_rx_queues =3D R8169_DEFAULT_RX_QUEUES; + break; + } } =20 static void rtl_request_firmware(struct rtl8169_private *tp) @@ -2899,6 +2934,8 @@ static void rtl_set_rx_max_size(struct rtl8169_privat= e *tp) =20 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) { + struct rtl8169_rx_ring *ring =3D &tp->rx_ring[0]; + /* * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh * register to be written before TxDescAddrLow to work. @@ -2906,8 +2943,18 @@ static void rtl_set_rx_tx_desc_registers(struct rtl8= 169_private *tp) */ RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); - RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); - RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); + RTL_W32(tp, RxDescAddrHigh, ((u64)ring->rx_phy_addr) >> 32); + RTL_W32(tp, RxDescAddrLow, + ((u64)ring->rx_phy_addr) & DMA_BIT_MASK(32)); + + for (int i =3D 1; i < tp->num_rx_rings; i++) { + unsigned int rdsar_reg =3D RDSAR_Q1_LOW + (i - 1) * 8; + struct rtl8169_rx_ring *ring =3D &tp->rx_ring[i]; + + RTL_W32(tp, rdsar_reg + 4, ((u64)ring->rx_phy_addr >> 32)); + RTL_W32(tp, rdsar_reg, + ((u64)ring->rx_phy_addr) & DMA_BIT_MASK(32)); + } } =20 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) @@ -4330,8 +4377,9 @@ static void rtl8169_mark_to_asic(struct RxDesc *desc) } =20 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, - struct RxDesc *desc) + struct rtl8169_rx_ring *ring, unsigned int index) { + struct RxDesc *desc =3D ring->rx_desc_array + index; struct device *d =3D tp_to_dev(tp); int node =3D dev_to_node(d); dma_addr_t mapping; @@ -4349,55 +4397,107 @@ static struct page *rtl8169_alloc_rx_data(struct r= tl8169_private *tp, } =20 desc->addr =3D cpu_to_le64(mapping); + ring->rx_desc_phy_addr[index] =3D mapping; rtl8169_mark_to_asic(desc); =20 return data; } =20 -static void rtl8169_rx_clear(struct rtl8169_private *tp) +static void rtl8169_rx_clear(struct rtl8169_private *tp, + struct rtl8169_rx_ring *ring) { int i; =20 - for (i =3D 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { + for (i =3D 0; i < NUM_RX_DESC && ring->rx_databuff[i]; i++) { dma_unmap_page(tp_to_dev(tp), - le64_to_cpu(tp->RxDescArray[i].addr), + ring->rx_desc_phy_addr[i], R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); - __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); - tp->Rx_databuff[i] =3D NULL; - tp->RxDescArray[i].addr =3D 0; - tp->RxDescArray[i].opts1 =3D 0; + __free_pages(ring->rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); + ring->rx_databuff[i] =3D NULL; + ring->rx_desc_phy_addr[i] =3D 0; + ring->rx_desc_array[i].addr =3D 0; + ring->rx_desc_array[i].opts1 =3D 0; } } =20 -static int rtl8169_rx_fill(struct rtl8169_private *tp) +static int rtl8169_rx_fill(struct rtl8169_private *tp, struct rtl8169_rx_r= ing *ring) { int i; =20 for (i =3D 0; i < NUM_RX_DESC; i++) { struct page *data; =20 - data =3D rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); + data =3D rtl8169_alloc_rx_data(tp, ring, i); if (!data) { - rtl8169_rx_clear(tp); + rtl8169_rx_clear(tp, ring); return -ENOMEM; } - tp->Rx_databuff[i] =3D data; + ring->rx_databuff[i] =3D data; } =20 /* mark as last descriptor in the ring */ - tp->RxDescArray[NUM_RX_DESC - 1].opts1 |=3D cpu_to_le32(RingEnd); + ring->rx_desc_array[NUM_RX_DESC - 1].opts1 |=3D cpu_to_le32(RingEnd); =20 return 0; } =20 +static int rtl8169_alloc_rx_desc(struct rtl8169_private *tp) +{ + struct pci_dev *pdev =3D tp->pci_dev; + struct rtl8169_rx_ring *ring; + + for (int i =3D 0; i < tp->num_rx_rings; i++) { + ring =3D &tp->rx_ring[i]; + ring->rx_desc_array =3D dma_alloc_coherent(&pdev->dev, + R8169_RX_RING_BYTES, + &ring->rx_phy_addr, + GFP_KERNEL); + if (!ring->rx_desc_array) + return -ENOMEM; + } + return 0; +} + +static void rtl8169_free_rx_desc(struct rtl8169_private *tp) +{ + struct pci_dev *pdev =3D tp->pci_dev; + struct rtl8169_rx_ring *ring; + + for (int i =3D 0; i < tp->num_rx_rings; i++) { + ring =3D &tp->rx_ring[i]; + if (ring->rx_desc_array) { + dma_free_coherent(&pdev->dev, + R8169_RX_RING_BYTES, + ring->rx_desc_array, + ring->rx_phy_addr); + ring->rx_desc_array =3D NULL; + } + } +} + static int rtl8169_init_ring(struct rtl8169_private *tp) { + int i, ret; + rtl8169_init_ring_indexes(tp); + rtl8169_rx_desc_init(tp); =20 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); - memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); =20 - return rtl8169_rx_fill(tp); + for (i =3D 0; i < tp->num_rx_rings; i++) { + struct rtl8169_rx_ring *ring =3D &tp->rx_ring[i]; + + memset(ring->rx_databuff, 0, sizeof(ring->rx_databuff)); + ret =3D rtl8169_rx_fill(tp, ring); + if (ret < 0) + goto err_clear; + } + return 0; + +err_clear: + while (--i >=3D 0) + rtl8169_rx_clear(tp, &tp->rx_ring[i]); + return ret; } =20 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int = entry) @@ -4486,16 +4586,23 @@ static void rtl8169_cleanup(struct rtl8169_private = *tp) rtl8169_init_ring_indexes(tp); } =20 -static void rtl_reset_work(struct rtl8169_private *tp) +static void rtl8169_rx_desc_reset(struct rtl8169_private *tp) { - int i; + for (int i =3D 0; i < tp->num_rx_rings; i++) { + struct rtl8169_rx_ring *ring =3D &tp->rx_ring[i]; + + for (int j =3D 0; j < NUM_RX_DESC; j++) + rtl8169_mark_to_asic(ring->rx_desc_array + j); + } +} =20 +static void rtl_reset_work(struct rtl8169_private *tp) +{ netif_stop_queue(tp->dev); =20 rtl8169_cleanup(tp); =20 - for (i =3D 0; i < NUM_RX_DESC; i++) - rtl8169_mark_to_asic(tp->RxDescArray + i); + rtl8169_rx_desc_reset(tp); =20 rtl8169_napi_enable(tp); rtl_hw_start(tp); @@ -4941,7 +5048,8 @@ static inline int rtl8169_fragmented_frame(u32 status) return (status & (FirstFrag | LastFrag)) !=3D (FirstFrag | LastFrag); } =20 -static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) +static inline void rtl8169_rx_csum(struct sk_buff *skb, + u32 opts1) { u32 status =3D opts1 & (RxProtoMask | RxCSFailMask); =20 @@ -4951,15 +5059,30 @@ static inline void rtl8169_rx_csum(struct sk_buff *= skb, u32 opts1) skb_checksum_none_assert(skb); } =20 +static bool rtl8169_check_rx_desc_error(struct net_device *dev, + struct rtl8169_private *tp, + u32 status) +{ + if (unlikely(status & RxRES)) { + if (status & (RxRWT | RxRUNT)) + dev->stats.rx_length_errors++; + if (status & RxCRC) + dev->stats.rx_crc_errors++; + return true; + } + return false; +} + static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, - int budget, struct napi_struct *napi) + struct rtl8169_rx_ring *ring, int budget, + struct napi_struct *napi) { struct device *d =3D tp_to_dev(tp); int count; =20 - for (count =3D 0; count < budget; count++, tp->cur_rx++) { - unsigned int pkt_size, entry =3D tp->cur_rx % NUM_RX_DESC; - struct RxDesc *desc =3D tp->RxDescArray + entry; + for (count =3D 0; count < budget; count++, ring->cur_rx++) { + unsigned int pkt_size, entry =3D ring->cur_rx % NUM_RX_DESC; + struct RxDesc *desc =3D ring->rx_desc_array + entry; struct sk_buff *skb; const void *rx_buf; dma_addr_t addr; @@ -4975,15 +5098,11 @@ static int rtl_rx(struct net_device *dev, struct rt= l8169_private *tp, */ dma_rmb(); =20 - if (unlikely(status & RxRES)) { + if (rtl8169_check_rx_desc_error(dev, tp, status)) { if (net_ratelimit()) netdev_warn(dev, "Rx ERROR. status =3D %08x\n", status); dev->stats.rx_errors++; - if (status & (RxRWT | RxRUNT)) - dev->stats.rx_length_errors++; - if (status & RxCRC) - dev->stats.rx_crc_errors++; =20 if (!(dev->features & NETIF_F_RXALL)) goto release_descriptor; @@ -5010,8 +5129,8 @@ static int rtl_rx(struct net_device *dev, struct rtl8= 169_private *tp, goto release_descriptor; } =20 - addr =3D le64_to_cpu(desc->addr); - rx_buf =3D page_address(tp->Rx_databuff[entry]); + addr =3D ring->rx_desc_phy_addr[entry]; + rx_buf =3D page_address(ring->rx_databuff[entry]); =20 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); prefetch(rx_buf); @@ -5155,7 +5274,8 @@ static int rtl8169_poll(struct napi_struct *napi, int= budget) =20 rtl_tx(dev, tp, budget); =20 - work_done =3D rtl_rx(dev, tp, budget, napi); + /* rtl8169_poll() is used only when there is a single RX ring. */ + work_done =3D rtl_rx(dev, tp, &tp->rx_ring[0], budget, napi); =20 if (work_done < budget && napi_complete_done(napi, work_done)) rtl_irq_enable(tp); @@ -5255,18 +5375,17 @@ static int rtl8169_close(struct net_device *dev) phylink_stop(tp->phylink); netif_stop_queue(dev); rtl8169_down(tp); - rtl8169_rx_clear(tp); + for (int i =3D 0; i < tp->num_rx_rings; i++) + rtl8169_rx_clear(tp, &tp->rx_ring[i]); =20 rtl8169_free_irq(tp); =20 phylink_disconnect_phy(tp->phylink); =20 - dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, - tp->RxPhyAddr); dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, tp->TxPhyAddr); tp->TxDescArray =3D NULL; - tp->RxDescArray =3D NULL; + rtl8169_free_rx_desc(tp); =20 pm_runtime_put_sync(&pdev->dev); =20 @@ -5300,10 +5419,8 @@ static int rtl_open(struct net_device *dev) if (!tp->TxDescArray) goto out; =20 - tp->RxDescArray =3D dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, - &tp->RxPhyAddr, GFP_KERNEL); - if (!tp->RxDescArray) - goto err_free_tx_0; + if (rtl8169_alloc_rx_desc(tp) < 0) + goto err_free_rx_1; =20 retval =3D rtl8169_init_ring(tp); if (retval < 0) @@ -5333,12 +5450,10 @@ static int rtl_open(struct net_device *dev) rtl8169_free_irq(tp); err_release_fw_2: rtl_release_firmware(tp); - rtl8169_rx_clear(tp); + for (int i =3D 0; i < tp->num_rx_rings; i++) + rtl8169_rx_clear(tp, &tp->rx_ring[i]); err_free_rx_1: - dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, - tp->RxPhyAddr); - tp->RxDescArray =3D NULL; -err_free_tx_0: + rtl8169_free_rx_desc(tp); dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, tp->TxPhyAddr); tp->TxDescArray =3D NULL; @@ -5505,6 +5620,7 @@ static void rtl_remove_one(struct pci_dev *pdev) =20 unregister_netdev(tp->dev); r8169_free_napi(tp); + kfree(tp->rx_ring); phylink_destroy(tp->phylink); =20 if (tp->dash_type !=3D RTL_DASH_NONE) @@ -6106,7 +6222,10 @@ static int rtl_init_one(struct pci_dev *pdev, const = struct pci_device_id *ent) u32 txconfig; u32 xid; =20 - dev =3D devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); + dev =3D devm_alloc_etherdev_mqs(&pdev->dev, sizeof(*tp), + R8169_MAX_TX_QUEUES, + R8169_MAX_RX_QUEUES); + if (!dev) return -ENOMEM; =20 @@ -6295,20 +6414,25 @@ static int rtl_init_one(struct pci_dev *pdev, const= struct pci_device_id *ent) } } =20 + tp->rx_ring =3D kcalloc(tp->num_rx_rings, sizeof(struct rtl8169_rx_ring), + GFP_KERNEL); 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Mon, 28 Sep 2026 15:04:26 +0800 Received: from RS-EX-MBS2.realsil.com.cn (172.29.17.102) by RS-EX-MBS2.realsil.com.cn (172.29.17.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Mon, 28 Sep 2026 15:04:26 +0800 Received: from 172.29.37.154 (172.29.37.152) by RS-EX-MBS2.realsil.com.cn (172.29.17.102) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Mon, 28 Sep 2026 15:04:26 +0800 From: javen To: , , , , , , , CC: , , Javen Xu Subject: [PATCH net-next v15 3/7] r8169: add support for new interrupt mapping Date: Mon, 28 Sep 2026 15:04:19 +0800 Message-ID: <20260928070423.202-4-javen_xu@realsil.com.cn> X-Mailer: git-send-email 2.50.1.windows.1 In-Reply-To: <20260928070423.202-1-javen_xu@realsil.com.cn> References: <20260928070423.202-1-javen_xu@realsil.com.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Javen Xu To support RSS, the number of hardware interrupt bits should match the interrupt of software. So we add support for new interrupt mapping here. ISR_VEC_MAP_REG is the hardware register to indicate interrupt status. IMR_SET_VEC_MAP_REG is interrupt mask which is set to enable irq. Signed-off-by: Javen Xu --- Changes in v2: - no changes Changes in v3: - init index in napi_struct and get message_id from index - move rtl8169_disable_hw_interrupt_msix directly before the call to napi_schedule() - change the condition in rtl8169_request_irq when RTL_VEC_MAP_ENABLE enabled, use rtl8169_interrupt_msix Changes in v4: - remove flag tp->feature, replace tp->features & RTL_VEC_MAP_ENABLE with tp->irq_nvecs > 1, they are equivalent. - follow reverse xmas tree, in rtl8169_interrupt_msix(), rtl8169_poll_msix_rx(), rtl8169_poll_msix_tx(), rtl8169_poll_msix_other() - use napi->index in rtl8169_poll_msix_other() - add a comment to describe RTL8127 MSI-X vector layout - simplify r8169_init_napi() Changes in v5: - replace magic number in rtl8169_poll_msix_tx() Changes in v6: - when irq_nvecs <=3D 1, use register IntrMask_8125, else using vec map - fix irq sequence in rtl8169_interrupt_msix(), disable interrupts before clean it - remove dead code in rtl8169_poll_msix_tx() Changes in v7: - remove recheck_desc_ownbit - change return value of rtl_tx - remove message_id which only used once Changes in v8: - fix rtl8169_netpoll() - remove tx_done Changes in v9: - change the way of getting message_id of napi Changes in v10: - no changes Changes in v11: - add comment on rtl8169_poll_msix_tx, only use 1 tx - remove napi for other. Separate napi only for datapath, control path like linkchg is handled in interrupt function, which will not call napi any more. Changes in v12: - no changes Changes in v13: - only request IRQs and napi for active vectors(0~7 rx, 8 tx) Changes in v14: - fix tp->phydev null pointer issue when the nic is fiber mode Changes in v15: - use new API netif_napi_add_tx() for tx queue - add a budget !=3D 0 check before calling napi_complete_done() - refactor NAPI init, enable, disable, delete and rtl8169_netpoll() to only iterate over actually active rx and tx ring --- drivers/net/ethernet/realtek/r8169_main.c | 244 ++++++++++++++++++---- 1 file changed, 209 insertions(+), 35 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethern= et/realtek/r8169_main.c index 7a2e7ce56e48..605154d9a151 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -471,8 +471,12 @@ enum rtl8125_registers { RSS_CTRL_8125 =3D 0x4500, Q_NUM_CTRL_8125 =3D 0x4800, EEE_TXIDLE_TIMER_8125 =3D 0x6048, + IMR_CLEAR_VEC_MAP_REG =3D 0x0d00, + ISR_VEC_MAP_REG =3D 0x0d04, + IMR_SET_VEC_MAP_REG =3D 0x0d0c, }; =20 +#define MSIX_ID_VEC_MAP_LINKCHG 29 #define LEDSEL_MASK_8125 0x23f =20 #define RX_VLAN_INNER_8125 BIT(22) @@ -603,6 +607,9 @@ enum rtl_register_content { =20 /* magic enable v2 */ MagicPacket_v2 =3D (1 << 16), /* Wake up when receives a Magic Packet */ +#define ISRIMR_LINKCHG BIT(29) +#define ISRIMR_TOK_Q0 BIT(8) +#define ISRIMR_ROK_Q0 BIT(0) }; =20 enum rtl_desc_bit { @@ -1770,26 +1777,38 @@ static u32 rtl_get_events(struct rtl8169_private *t= p) =20 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) { - if (rtl_is_8125(tp)) - RTL_W32(tp, IntrStatus_8125, bits); - else + if (rtl_is_8125(tp)) { + if (tp->irq_nvecs > 1) + RTL_W32(tp, ISR_VEC_MAP_REG, bits); + else + RTL_W32(tp, IntrStatus_8125, bits); + } else { RTL_W16(tp, IntrStatus, bits); + } } =20 static void rtl_irq_disable(struct rtl8169_private *tp) { - if (rtl_is_8125(tp)) - RTL_W32(tp, IntrMask_8125, 0); - else + if (rtl_is_8125(tp)) { + if (tp->irq_nvecs > 1) + RTL_W32(tp, IMR_CLEAR_VEC_MAP_REG, 0xffffffff); + else + RTL_W32(tp, IntrMask_8125, 0); + } else { RTL_W16(tp, IntrMask, 0); + } } =20 static void rtl_irq_enable(struct rtl8169_private *tp) { - if (rtl_is_8125(tp)) - RTL_W32(tp, IntrMask_8125, tp->irq_mask); - else + if (rtl_is_8125(tp)) { + if (tp->irq_nvecs > 1) + RTL_W32(tp, IMR_SET_VEC_MAP_REG, tp->irq_mask); + else + RTL_W32(tp, IntrMask_8125, tp->irq_mask); + } else { RTL_W16(tp, IntrMask, tp->irq_mask); + } } =20 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) @@ -4539,14 +4558,24 @@ static void rtl8169_tx_clear(struct rtl8169_private= *tp) =20 static void rtl8169_napi_disable(struct rtl8169_private *tp) { - for (int i =3D 0; i < tp->irq_nvecs; i++) - napi_disable(&tp->rtl8169_napi[i]); + if (tp->irq_nvecs > 1) { + for (int i =3D 0; i < tp->num_rx_rings; i++) + napi_disable(&tp->rtl8169_napi[i]); + napi_disable(&tp->rtl8169_napi[R8169_MAX_RX_QUEUES]); + } else { + napi_disable(&tp->rtl8169_napi[0]); + } } =20 static void rtl8169_napi_enable(struct rtl8169_private *tp) { - for (int i =3D 0; i < tp->irq_nvecs; i++) - napi_enable(&tp->rtl8169_napi[i]); + if (tp->irq_nvecs > 1) { + for (int i =3D 0; i < tp->num_rx_rings; i++) + napi_enable(&tp->rtl8169_napi[i]); + napi_enable(&tp->rtl8169_napi[R8169_MAX_RX_QUEUES]); + } else { + napi_enable(&tp->rtl8169_napi[0]); + } } =20 static void rtl8169_cleanup(struct rtl8169_private *tp) @@ -5192,19 +5221,81 @@ static irqreturn_t rtl8169_interrupt(int irq, void = *dev_instance) return IRQ_HANDLED; } =20 -static void rtl8169_free_irq(struct rtl8169_private *tp) +static void rtl8169_free_one_irq(struct rtl8169_private *tp, int i) { struct pci_dev *pdev =3D tp->pci_dev; - int i, irq; + struct napi_struct *napi; + int irq; =20 - for (i =3D 0; i < tp->irq_nvecs; i++) { - struct napi_struct *napi =3D &tp->rtl8169_napi[i]; + irq =3D pci_irq_vector(pdev, i); + napi =3D &tp->rtl8169_napi[i]; =20 - irq =3D pci_irq_vector(pdev, i); + if (tp->irq_nvecs > 1) { + if (i <=3D R8169_MAX_RX_QUEUES) + free_irq(irq, napi); + else if (i =3D=3D MSIX_ID_VEC_MAP_LINKCHG) + free_irq(irq, tp); + } else { free_irq(irq, napi); } } =20 +static void rtl8169_free_irq(struct rtl8169_private *tp) +{ + int i; + + for (i =3D 0; i < tp->irq_nvecs; i++) + rtl8169_free_one_irq(tp, i); +} + +static void rtl8169_disable_hw_interrupt_msix(struct rtl8169_private *tp, + int message_id) +{ + RTL_W32(tp, IMR_CLEAR_VEC_MAP_REG, BIT(message_id)); +} + +static void rtl8169_clear_hw_isr(struct rtl8169_private *tp, int message_i= d) +{ + RTL_W32(tp, ISR_VEC_MAP_REG, BIT(message_id)); +} + +static void rtl8169_enable_hw_interrupt_msix(struct rtl8169_private *tp, + int message_id) +{ + RTL_W32(tp, IMR_SET_VEC_MAP_REG, BIT(message_id)); +} + +static irqreturn_t rtl8169_interrupt_msix(int irq, void *dev_instance) +{ + struct napi_struct *napi =3D dev_instance; + struct net_device *dev =3D napi->dev; + struct rtl8169_private *tp; + int message_id; + + tp =3D netdev_priv(dev); + message_id =3D napi - tp->rtl8169_napi; + + rtl8169_disable_hw_interrupt_msix(tp, message_id); + rtl8169_clear_hw_isr(tp, message_id); + + napi_schedule(napi); + + return IRQ_HANDLED; +} + +static irqreturn_t rtl8169_interrupt_other(int irq, void *dev_instance) +{ + struct rtl8169_private *tp =3D dev_instance; + + rtl8169_clear_hw_isr(tp, MSIX_ID_VEC_MAP_LINKCHG); + if (tp->phydev) + phy_mac_interrupt(tp->phydev); + else if (tp->sfp_mode) + phylink_mac_change(tp->phylink, + !!(RTL_R8(tp, PHYstatus) & LinkStatus)); + return IRQ_HANDLED; +} + static int rtl8169_request_irq(struct rtl8169_private *tp) { struct pci_dev *pdev =3D tp->pci_dev; @@ -5219,18 +5310,28 @@ static int rtl8169_request_irq(struct rtl8169_priva= te *tp) napi =3D &tp->rtl8169_napi[i]; irq =3D pci_irq_vector(pdev, i); =20 - rc =3D request_irq(irq, rtl8169_interrupt, irqflags, - dev->name, napi); + if (tp->irq_nvecs > 1) { + /* RX: 0~7, TX: 8*/ + if (i <=3D R8169_MAX_RX_QUEUES) + rc =3D request_irq(irq, rtl8169_interrupt_msix, + irqflags, dev->name, napi); + else if (i =3D=3D MSIX_ID_VEC_MAP_LINKCHG) + rc =3D request_irq(irq, rtl8169_interrupt_other, + irqflags, dev->name, tp); + else + continue; + } else { + rc =3D request_irq(irq, rtl8169_interrupt, + irqflags, dev->name, napi); + } if (rc) goto free_irq; } return 0; =20 free_irq: - while (--i >=3D 0) { - irq =3D pci_irq_vector(pdev, i); - free_irq(irq, &tp->rtl8169_napi[i]); - } + while (--i >=3D 0) + rtl8169_free_one_irq(tp, i); return rc; } =20 @@ -5397,8 +5498,13 @@ static void rtl8169_netpoll(struct net_device *dev) { struct rtl8169_private *tp =3D netdev_priv(dev); =20 - for (int i =3D 0; i < tp->irq_nvecs; i++) - rtl8169_interrupt(0, &tp->rtl8169_napi[i]); + if (tp->irq_nvecs > 1) { + for (int i =3D 0; i < tp->num_rx_rings; i++) + rtl8169_interrupt_msix(0, &tp->rtl8169_napi[i]); + rtl8169_interrupt_msix(0, &tp->rtl8169_napi[R8169_MAX_RX_QUEUES]); + } else { + rtl8169_interrupt(0, &tp->rtl8169_napi[0]); + } } #endif =20 @@ -5600,8 +5706,13 @@ static void rtl_shutdown(struct pci_dev *pdev) =20 static void r8169_free_napi(struct rtl8169_private *tp) { - for (int i =3D 0; i < tp->irq_nvecs; i++) - netif_napi_del(&tp->rtl8169_napi[i]); + if (tp->irq_nvecs > 1) { + for (int i =3D 0; i < tp->num_rx_rings; i++) + netif_napi_del(&tp->rtl8169_napi[i]); + netif_napi_del(&tp->rtl8169_napi[R8169_MAX_RX_QUEUES]); + } else { + netif_napi_del(&tp->rtl8169_napi[0]); + } =20 kfree(tp->rtl8169_napi); } @@ -5654,10 +5765,16 @@ static const struct net_device_ops rtl_netdev_ops = =3D { =20 static void rtl_set_irq_mask(struct rtl8169_private *tp) { - tp->irq_mask =3D RxOK | RxErr | TxOK | TxErr | LinkChg; + if (tp->irq_nvecs > 1) { + tp->irq_mask =3D ISRIMR_LINKCHG | ISRIMR_TOK_Q0; + for (int i =3D 0; i < tp->num_rx_rings; i++) + tp->irq_mask |=3D ISRIMR_ROK_Q0 << i; + } else { + tp->irq_mask =3D RxOK | RxErr | TxOK | TxErr | LinkChg; =20 - if (tp->mac_version <=3D RTL_GIGA_MAC_VER_06) - tp->irq_mask |=3D SYSErr | RxFIFOOver; + if (tp->mac_version <=3D RTL_GIGA_MAC_VER_06) + tp->irq_mask |=3D SYSErr | RxFIFOOver; + } } =20 static int rtl_alloc_irq(struct rtl8169_private *tp) @@ -6203,12 +6320,69 @@ static int rtl_init_phylink(struct rtl8169_private = *tp) return 0; } =20 +static int rtl8169_poll_msix_rx(struct napi_struct *napi, int budget) +{ + struct net_device *dev =3D napi->dev; + struct rtl8169_private *tp; + int work_done =3D 0; + int message_id; + + tp =3D netdev_priv(dev); + message_id =3D napi - tp->rtl8169_napi; + + if (message_id < tp->num_rx_rings) + work_done +=3D rtl_rx(dev, tp, &tp->rx_ring[message_id], + budget, napi); + + if (work_done < budget && napi_complete_done(napi, work_done)) + rtl8169_enable_hw_interrupt_msix(tp, message_id); + + return work_done; +} + +static int rtl8169_poll_msix_tx(struct napi_struct *napi, int budget) +{ + struct net_device *dev =3D napi->dev; + struct rtl8169_private *tp; + + tp =3D netdev_priv(dev); + + /* Currently r8169 only supports a single Tx ring. + * Therefore, we don't need a per-ring Tx processing loop here. + */ + rtl_tx(dev, tp, budget); + + if (budget && napi_complete_done(napi, 0)) + rtl8169_enable_hw_interrupt_msix(tp, (int)(napi - tp->rtl8169_napi)); + + return 0; +} + +/* RTL8127 MSI-X vector layout: + * Vectors 0 .. (MAX_RXQ - 1) : Rx Queues + * Vectors MAX_RXQ .. (MAX_RXQ + MAX_TXQ - 1) : Tx Queues + * NAPI is only allocated for data path + */ static void r8169_init_napi(struct rtl8169_private *tp) { - for (int i =3D 0; i < tp->irq_nvecs; i++) { - netif_napi_add(tp->dev, &tp->rtl8169_napi[i], rtl8169_poll); - netif_napi_set_irq(&tp->rtl8169_napi[i], - pci_irq_vector(tp->pci_dev, i)); + int i; + + if (tp->irq_nvecs > 1) { + for (i =3D 0; i < tp->num_rx_rings; i++) { + netif_napi_add(tp->dev, &tp->rtl8169_napi[i], + rtl8169_poll_msix_rx); + netif_napi_set_irq(&tp->rtl8169_napi[i], + pci_irq_vector(tp->pci_dev, i)); + } + netif_napi_add_tx(tp->dev, + &tp->rtl8169_napi[R8169_MAX_RX_QUEUES], + rtl8169_poll_msix_tx); + netif_napi_set_irq(&tp->rtl8169_napi[R8169_MAX_RX_QUEUES], + pci_irq_vector(tp->pci_dev, R8169_MAX_RX_QUEUES)); + } else { + netif_napi_add(tp->dev, &tp->rtl8169_napi[0], rtl8169_poll); + netif_napi_set_irq(&tp->rtl8169_napi[0], + pci_irq_vector(tp->pci_dev, 0)); } } =20 --=20 2.43.0 From nobody Tue Sep 29 01:19:59 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27C89410D15; Mon, 28 Sep 2026 07:05:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790579107; cv=none; b=ANonhc3vGcORyyGOzoTUpeob7zDgfqKac6B7mfyFLaV8uaFdxNWd1SqVwIZIeWxZG+1wqKmG2rPr8WyeP2d42zd5i/THL8Uzifs6WZhNAqpHyzD1oXMX/qftVaFz74INvBA4yHqgFzMMcl4JEpE2wTIxn9DjEErL38u7bJwKXRE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790579107; c=relaxed/simple; bh=XMuu0V891oFPLsGjdeHY7ZpNAepD+dEjwAfGvrEdyEU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=L9QVNf1CDgF3WyoR+F3fk3K/3v/bGsf87bsHB+tRTs5AlCYF2r7D/v9RVyRKHXCocqRieNaidI9Dv7wcq5zWZf0dCNu4FRZsuRHraUvNiPljmxoR0NCZbgEE1ZHH5zZKJ7LBABlDoBPQaHvLKxktpd4osg6iC1Hvdb54mriX+Lc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realsil.com.cn; spf=pass smtp.mailfrom=realsil.com.cn; dkim=pass (2048-bit key) header.d=realsil.com.cn header.i=@realsil.com.cn header.b=YM6pEt5m; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realsil.com.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realsil.com.cn Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realsil.com.cn header.i=@realsil.com.cn header.b="YM6pEt5m" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 68S74QmuC217875, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realsil.com.cn; s=dkim; t=1790579067; bh=d7PC6cIWJaHzXi3qAvWRHTNupDWQF/tqkkdpj7QfcG8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=YM6pEt5mWzGpkI2nzItKD0FpumbEZ9tWTKwNxajOGitf+QvmS/VuwWTlXIB61P3ad D0lDSV5T68OGFWZ02jLcvTdolmE/MZlNYy8BpwvU/jldtfVKRpvOMBTEJL8w5Ve/BR u+2STvVV28KmlLaoXTSZG4KOueyYraho03zibOLk4z2uUjYgUCa2Rzm+XaXMW/8QIo XULxWexH5fT4KPxnZeUUZRb/KI0haKEi3usjO1AkQ5hqoVj7TYt6r+itXRmdUDtwqO tl3IxnbvklGqaLsPHAA2Txjvoj7u0DV8+fuY8b1XPbAY1yLTqtekiHE0sJqoKDwsxw DhmkTX8N/w2XQ== Received: from RS-EX-MBS2.realsil.com.cn ([172.29.17.102]) by rtits2.realtek.com.tw (8.15.2/3.29/5.94) with ESMTPS id 68S74QmuC217875 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 28 Sep 2026 15:04:26 +0800 Received: from RS-EX-MBS2.realsil.com.cn (172.29.17.102) by RS-EX-MBS2.realsil.com.cn (172.29.17.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Mon, 28 Sep 2026 15:04:26 +0800 Received: from 172.29.37.154 (172.29.37.152) by RS-EX-MBS2.realsil.com.cn (172.29.17.102) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Mon, 28 Sep 2026 15:04:26 +0800 From: javen To: , , , , , , , CC: , , Javen Xu Subject: [PATCH net-next v15 4/7] r8169: enable new interrupt mapping Date: Mon, 28 Sep 2026 15:04:20 +0800 Message-ID: <20260928070423.202-5-javen_xu@realsil.com.cn> X-Mailer: git-send-email 2.50.1.windows.1 In-Reply-To: <20260928070423.202-1-javen_xu@realsil.com.cn> References: <20260928070423.202-1-javen_xu@realsil.com.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Javen Xu This patch enables new interrupt mapping for RTL8127 and add error pkts counter per ring. Signed-off-by: Javen Xu --- Changes in v2: - no changes Changes in v3: - no changes Changes in v4: - no changes Changes in v5: - no changes Changes in v6: - no changes Changes in v7: - no changes Changes in v8: - no changes Changes in v9: - no changes Changes in v10: - no changes Changes in v11: - add error pkts counter per ring Changes in v12: - drop unrelated change in rtl8169_init_ring() Changes in v13: - no changes Changes in v14: - no changes Changes in v15: - no changes --- drivers/net/ethernet/realtek/r8169_main.c | 78 +++++++++++++++++++---- 1 file changed, 67 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethern= et/realtek/r8169_main.c index 605154d9a151..127594665289 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include =20 @@ -768,6 +769,15 @@ struct rtl8169_rx_ring { dma_addr_t rx_desc_phy_addr[NUM_RX_DESC]; dma_addr_t rx_phy_addr; struct page *rx_databuff[NUM_RX_DESC]; + + struct { + u64 rx_errors; + u64 rx_dropped; + u64 rx_length_errors; + u64 rx_crc_errors; + u64 multicast; + struct u64_stats_sync syncp; + } stats; }; =20 enum rtl_sfp_mode { @@ -4084,6 +4094,15 @@ DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); } =20 +static void rtl8169_hw_enable_vec_mapping(struct rtl8169_private *tp) +{ + u8 tmp; + + tmp =3D RTL_R8(tp, INT_CFG0_8125); + tmp |=3D INT_CFG0_ENABLE_8125; + RTL_W8(tp, INT_CFG0_8125, tmp); +} + static void rtl_hw_start_8125_common(struct rtl8169_private *tp) { rtl_pcie_state_l2l3_disable(tp); @@ -4092,6 +4111,9 @@ static void rtl_hw_start_8125_common(struct rtl8169_p= rivate *tp) RTL_W32(tp, RSS_CTRL_8125, 0); RTL_W16(tp, Q_NUM_CTRL_8125, 0); =20 + if (tp->irq_nvecs > 1) + rtl8169_hw_enable_vec_mapping(tp); + /* disable UPS */ r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); =20 @@ -5088,15 +5110,16 @@ static inline void rtl8169_rx_csum(struct sk_buff *= skb, skb_checksum_none_assert(skb); } =20 -static bool rtl8169_check_rx_desc_error(struct net_device *dev, - struct rtl8169_private *tp, +static bool rtl8169_check_rx_desc_error(struct rtl8169_rx_ring *ring, u32 status) { if (unlikely(status & RxRES)) { + u64_stats_update_begin(&ring->stats.syncp); if (status & (RxRWT | RxRUNT)) - dev->stats.rx_length_errors++; + ring->stats.rx_length_errors++; if (status & RxCRC) - dev->stats.rx_crc_errors++; + ring->stats.rx_crc_errors++; + u64_stats_update_end(&ring->stats.syncp); return true; } return false; @@ -5127,11 +5150,13 @@ static int rtl_rx(struct net_device *dev, struct rt= l8169_private *tp, */ dma_rmb(); =20 - if (rtl8169_check_rx_desc_error(dev, tp, status)) { + if (rtl8169_check_rx_desc_error(ring, status)) { if (net_ratelimit()) netdev_warn(dev, "Rx ERROR. status =3D %08x\n", status); - dev->stats.rx_errors++; + u64_stats_update_begin(&ring->stats.syncp); + ring->stats.rx_errors++; + u64_stats_update_end(&ring->stats.syncp); =20 if (!(dev->features & NETIF_F_RXALL)) goto release_descriptor; @@ -5147,14 +5172,18 @@ static int rtl_rx(struct net_device *dev, struct rt= l8169_private *tp, * They are seen as a symptom of over-mtu sized frames. */ if (unlikely(rtl8169_fragmented_frame(status))) { - dev->stats.rx_dropped++; - dev->stats.rx_length_errors++; + u64_stats_update_begin(&ring->stats.syncp); + ring->stats.rx_dropped++; + ring->stats.rx_length_errors++; + u64_stats_update_end(&ring->stats.syncp); goto release_descriptor; } =20 skb =3D napi_alloc_skb(napi, pkt_size); if (unlikely(!skb)) { - dev->stats.rx_dropped++; + u64_stats_update_begin(&ring->stats.syncp); + ring->stats.rx_dropped++; + u64_stats_update_end(&ring->stats.syncp); goto release_descriptor; } =20 @@ -5173,8 +5202,11 @@ static int rtl_rx(struct net_device *dev, struct rtl= 8169_private *tp, =20 rtl8169_rx_vlan_tag(desc, skb); =20 - if (skb->pkt_type =3D=3D PACKET_MULTICAST) - dev->stats.multicast++; + if (skb->pkt_type =3D=3D PACKET_MULTICAST) { + u64_stats_update_begin(&ring->stats.syncp); + ring->stats.multicast++; + u64_stats_update_end(&ring->stats.syncp); + } =20 napi_gro_receive(napi, skb); =20 @@ -5578,6 +5610,27 @@ rtl8169_get_stats64(struct net_device *dev, struct r= tnl_link_stats64 *stats) netdev_stats_to_stats64(stats, &dev->stats); dev_fetch_sw_netstats(stats, dev->tstats); =20 + for (int i =3D 0; i < tp->num_rx_rings; i++) { + u64 errors, dropped, length_errors, crc_errors, multicast; + struct rtl8169_rx_ring *ring =3D &tp->rx_ring[i]; + unsigned int start; + + do { + start =3D u64_stats_fetch_begin(&ring->stats.syncp); + errors =3D ring->stats.rx_errors; + dropped =3D ring->stats.rx_dropped; + length_errors =3D ring->stats.rx_length_errors; + crc_errors =3D ring->stats.rx_crc_errors; + multicast =3D ring->stats.multicast; + } while (u64_stats_fetch_retry(&ring->stats.syncp, start)); + + stats->rx_errors +=3D errors; + stats->rx_dropped +=3D dropped; + stats->rx_length_errors +=3D length_errors; + stats->rx_crc_errors +=3D crc_errors; + stats->multicast +=3D multicast; + } + /* * Fetch additional counter values missing in stats collected by driver * from tally counters. @@ -6595,6 +6648,9 @@ static int rtl_init_one(struct pci_dev *pdev, const s= truct pci_device_id *ent) goto err_destory_phylink; } =20 + for (int i =3D 0; i < tp->num_rx_rings; i++) + u64_stats_init(&tp->rx_ring[i].stats.syncp); + tp->rtl8169_napi =3D kcalloc(tp->irq_nvecs, sizeof(struct napi_struct), GFP_KERNEL); if (!tp->rtl8169_napi) { --=20 2.43.0 From nobody Tue Sep 29 01:19:59 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27EBB4446FA; Mon, 28 Sep 2026 07:05:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790579108; cv=none; b=UC6bMgtR/q6fndlmJ+z3any1LTrdsyOw6tCKN8e26hjrQq4e3LDvhFs6jQeVaxTR5wRm6udBfqA1W8fmAFXuvcWchVKYQimWeaDJo8sWCccMy7rdxZFcjrExo5UW4tloIW9egI2cHu4Ganl9PZXUtd9Hcl5mYBCKekFLyyR6oyg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790579108; c=relaxed/simple; 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Mon, 28 Sep 2026 15:04:26 +0800 Received: from 172.29.37.154 (172.29.37.152) by RS-EX-MBS2.realsil.com.cn (172.29.17.102) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Mon, 28 Sep 2026 15:04:26 +0800 From: javen To: , , , , , , , CC: , , Javen Xu Subject: [PATCH net-next v15 5/7] r8169: add support and enable rss Date: Mon, 28 Sep 2026 15:04:21 +0800 Message-ID: <20260928070423.202-6-javen_xu@realsil.com.cn> X-Mailer: git-send-email 2.50.1.windows.1 In-Reply-To: <20260928070423.202-1-javen_xu@realsil.com.cn> References: <20260928070423.202-1-javen_xu@realsil.com.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Javen Xu This patch adds support and enable rss for RTL8127. Signed-off-by: Javen Xu --- Changes in v2: - some changes moved from Patch 2/7 Changes in v3: - add struct rtl8169_rss_data. Allocate it dynamically when needed. - define rss_key as an u32 array - replace some magic bit numbers in rtl8169_set_rss_hash_opt() and rtl8125_set_rx_q_num() - use union to combine different rx descriptor, refactor struct RxDesc - remove dead code from rtl8169_double_check_rss_support() Changes in v4: - rename macro definition, e.g R8127_MAX_IRQ to R8127_MAX_NUM_IRQVEC - change hw_supp_indir_tbl_entries type to unsigned int - change init_rx_desc_type type to enum - remove rtl_check_rss_support(), add helper function rtl_hw_support_rss() - remove hw_curr_isr_ver, use irq_nvecs to judge whether we should enable vector interrupt mapping, use tp->num_rx_ring to judge whether we should enable rss - remove function rtl8169_double_check_rss_support(), use rtl8169_set_rx_ring_num() to set num_rx_ring according to tp->irq_nvecs Changes in v5: - no changes Changes in v6: - change rss_queue_num type from u8 to unsigned int - fix rx desc clear in rtl8169_rx_clear() for different desc type - clamping num_rx_ring with rounddown_pow_of_two() Changes in v7: - remove unused macro - change unfixed type in rtl8169_store_reta Changes in v8: - refill desc->addr when rx_desc reset - rtl8169_set_channels fixed in patch 7/7 Changes in v9: - remove rtl8169_set_desc_dma_addr, only set desc dma addr for RX_DESC_TYPE_RSS desc Changes in v10: - Change rss_key to u8 array and write rss_key_reg as u32 values. Use get_unaligned_le32() to keep behavior consistent on big-endian and little-endian Changes in v11: - fix compilation error by adding block in switch default case - fix concurrency bug on updating global dev->stats by using per-queue stat - fix packet drop logic to properlly handle fatal errors when rss is enable - use get_unaligned_le32() uniformly in rtl8169_store_reta() - fix coding style issues - add comment on pci_alloc_irq_vectors() call Changes in v12: - add support for UDP rss Changes in v13: - no changes Changes in v14: - fix an integer underflow in rtl_rx() when handling extremely small RUNT packets with RXALL enabled. - remove redundant macro definition such as RX_RUNT_RSS/RX_CRC_RSS =20 Changes in v15: - Add a comment to clarify that the RxRWT (over-length) error is omitted for it is not supported by this desc type - Increase the minimum packet size check to ETH_HLEN + ETH_FCS_LEN - Add skb_record_rx_queue() in rtl_rx() to ensure correct RPS behavior - Add a fallback dev_info log when MSI-X vector allocation fails to meet 30-vector requerement --- drivers/net/ethernet/realtek/r8169_main.c | 415 ++++++++++++++++++++-- 1 file changed, 377 insertions(+), 38 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethern= et/realtek/r8169_main.c index 127594665289..1024cf4596b9 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -82,6 +82,19 @@ #define R8169_MAX_RX_QUEUES 8 #define R8169_DEFAULT_RX_QUEUES 1 #define R8169_MAX_TX_QUEUES 1 +#define R8127_MAX_NUM_IRQVEC 32 +#define R8127_MIN_NUM_IRQVEC 30 +#define R8169_IRQ_DEFAULT 1 +#define RTL_RSS_KEY_SIZE 40 +#define RSS_CPU_NUM_MASK GENMASK(18, 16) +#define RSS_HASH_MASK GENMASK(10, 8) +#define RTL_MAX_INDIRECTION_TABLE_ENTRIES 128 +#define RXS_RSS_UDP BIT(27) +#define RXS_RSS_IPV4 BIT(28) +#define RXS_RSS_IPV6 BIT(29) +#define RXS_RSS_TCP BIT(30) +#define RXS_RSS_L3_TYPE_MASK (RXS_RSS_IPV4 | RXS_RSS_IPV6) +#define RXS_RSS_L4_TYPE_MASK (RXS_RSS_TCP | RXS_RSS_UDP) =20 #define OCP_STD_PHY_BASE 0xa400 =20 @@ -506,6 +519,9 @@ enum rtl_register_content { RxRUNT =3D (1 << 20), RxCRC =3D (1 << 19), =20 + RXRUNT_RSS =3D (1 << 21), + RXCRC_RSS =3D (1 << 20), + /* ChipCmdBits */ StopReq =3D 0x80, CmdReset =3D 0x10, @@ -611,6 +627,20 @@ enum rtl_register_content { #define ISRIMR_LINKCHG BIT(29) #define ISRIMR_TOK_Q0 BIT(8) #define ISRIMR_ROK_Q0 BIT(0) +#define RTL_DESC_TYPE_CTRL 0xd8 +#define RSS_KEY_REG 0x4600 +#define RSS_INDIRECTION_TBL_REG 0x4700 +#define RSS_CTRL_TCP_IPV4_SUPP BIT(0) +#define RTL_DESC_TYPE_RSS BIT(1) +#define RSS_CTRL_IPV4_SUPP BIT(1) +#define RSS_CTRL_TCP_IPV6_SUPP BIT(2) +#define RSS_CTRL_IPV6_SUPP BIT(3) +#define RSS_CTRL_IPV6_EXT_SUPP BIT(4) +#define RSS_CTRL_TCP_IPV6_EXT_SUPP BIT(5) +#define RSS_CTRL_UDP_IPV4_SUPP BIT(11) +#define RSS_CTRL_UDP_IPV6_SUPP BIT(12) +#define RX_RES_RSS BIT(22) +#define RTL_RX_Q_NUM_MASK GENMASK(4, 2) }; =20 enum rtl_desc_bit { @@ -668,6 +698,11 @@ enum rtl_rx_desc_bit { #define RxProtoIP (PID1 | PID0) #define RxProtoMask RxProtoIP =20 +#define RX_UDPT_DESC_RSS BIT(19) +#define RX_TCPT_DESC_RSS BIT(18) +#define RX_UDPF_DESC_RSS BIT(16) /* UDP/IP checksum failed */ +#define RX_TCPF_DESC_RSS BIT(15) /* TCP/IP checksum failed */ + IPFail =3D (1 << 16), /* IP checksum failed */ UDPFail =3D (1 << 15), /* UDP/IP checksum failed */ TCPFail =3D (1 << 14), /* TCP/IP checksum failed */ @@ -689,9 +724,27 @@ struct TxDesc { }; =20 struct RxDesc { - __le32 opts1; - __le32 opts2; - __le64 addr; + union { + /* RX_DESC_TYPE_DEFAULT */ + struct { + __le32 opts1; + __le32 opts2; + __le64 addr; + }; + + /* RX_DESC_TYPE_RSS */ + struct { + union { + __le64 rss_addr; + struct { + __le32 rss_info; + __le32 rss_result; + } rss_dword; + }; + __le32 rss_opts2; + __le32 rss_opts1; + }; + }; }; =20 struct ring_info { @@ -763,6 +816,11 @@ enum rtl_dash_type { RTL_DASH_25_BP, }; =20 +enum rx_desc_type { + RX_DESC_TYPE_DEFAULT, + RX_DESC_TYPE_RSS, +}; + struct rtl8169_rx_ring { u32 cur_rx; struct RxDesc *rx_desc_array; @@ -786,6 +844,12 @@ enum rtl_sfp_mode { RTL_SFP_8127_ATF, }; =20 +struct rtl8169_rss_data { + u8 rss_key[RTL_RSS_KEY_SIZE]; + u8 rss_indir_tbl[RTL_MAX_INDIRECTION_TABLE_ENTRIES]; + unsigned int hw_supp_indir_tbl_entries; +}; + struct rtl8169_private { void __iomem *mmio_addr; /* memory map physical address */ struct pci_dev *pci_dev; @@ -806,7 +870,9 @@ struct rtl8169_private { u16 tx_lpi_timer; u32 irq_mask; unsigned int hw_supp_num_rx_queues; + struct rtl8169_rss_data *rss_data; unsigned int irq_nvecs; + enum rx_desc_type init_rx_desc_type; struct clk *clk; int speed; =20 @@ -1721,6 +1787,11 @@ static enum rtl_sfp_mode rtl_get_sfp_mode(struct rtl= 8169_private *tp) return RTL_SFP_NONE; } =20 +static bool rtl_hw_support_rss(struct rtl8169_private *tp) +{ + return tp->mac_version =3D=3D RTL_GIGA_MAC_VER_80; +} + static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) { switch (tp->mac_version) { @@ -2020,9 +2091,20 @@ static inline u32 rtl8169_tx_vlan_tag(struct sk_buff= *skb) TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; } =20 -static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) +static void rtl8169_rx_vlan_tag(struct rtl8169_private *tp, + struct RxDesc *desc, + struct sk_buff *skb) { - u32 opts2 =3D le32_to_cpu(desc->opts2); + u32 opts2; + + switch (tp->init_rx_desc_type) { + case RX_DESC_TYPE_RSS: + opts2 =3D le32_to_cpu(desc->rss_opts2); + break; + default: + opts2 =3D le32_to_cpu(desc->opts2); + break; + } =20 if (opts2 & RxVlanTag) __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); @@ -2826,17 +2908,27 @@ static void rtl_hw_reset(struct rtl8169_private *tp) rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); } =20 +static void rtl8169_init_rss(struct rtl8169_private *tp) +{ + for (int i =3D 0; i < tp->rss_data->hw_supp_indir_tbl_entries; i++) + tp->rss_data->rss_indir_tbl[i] =3D ethtool_rxfh_indir_default(i, tp->num= _rx_rings); + + netdev_rss_key_fill(tp->rss_data->rss_key, RTL_RSS_KEY_SIZE); +} + static void rtl_setup_rx_params(struct rtl8169_private *tp) { tp->num_rx_rings =3D 1; switch (tp->mac_version) { case RTL_GIGA_MAC_VER_80: tp->hw_supp_num_rx_queues =3D R8169_MAX_RX_QUEUES; + tp->rss_data->hw_supp_indir_tbl_entries =3D RTL_MAX_INDIRECTION_TABLE_EN= TRIES; break; default: tp->hw_supp_num_rx_queues =3D R8169_DEFAULT_RX_QUEUES; break; } + tp->init_rx_desc_type =3D RX_DESC_TYPE_DEFAULT; } =20 static void rtl_request_firmware(struct rtl8169_private *tp) @@ -2961,6 +3053,58 @@ static void rtl_set_rx_max_size(struct rtl8169_priva= te *tp) RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); } =20 +static void rtl8169_store_rss_key(struct rtl8169_private *tp) +{ + u8 *rss_key =3D tp->rss_data->rss_key; + const u16 rss_key_reg =3D RSS_KEY_REG; + + /* Write RSS key to HW */ + for (int i =3D 0; i < RTL_RSS_KEY_SIZE; i +=3D sizeof(u32)) + RTL_W32(tp, rss_key_reg + i, get_unaligned_le32(rss_key + i)); +} + +static void rtl8169_store_reta(struct rtl8169_private *tp) +{ + u8 *indir_tbl =3D tp->rss_data->rss_indir_tbl; + unsigned int i; + + /* Write redirection table to HW */ + for (i =3D 0; i < tp->rss_data->hw_supp_indir_tbl_entries; i +=3D 4) { + u32 reta =3D get_unaligned_le32(&indir_tbl[i]); + + RTL_W32(tp, RSS_INDIRECTION_TBL_REG + i, reta); + } +} + +static void rtl8169_set_rss_hash_opt(struct rtl8169_private *tp) +{ + u32 rss_ctrl; + + rss_ctrl =3D FIELD_PREP(RSS_CPU_NUM_MASK, ilog2(tp->num_rx_rings)); + + /* Perform hash on these packet types */ + rss_ctrl |=3D RSS_CTRL_TCP_IPV4_SUPP | + RSS_CTRL_IPV4_SUPP | + RSS_CTRL_IPV6_SUPP | + RSS_CTRL_IPV6_EXT_SUPP | + RSS_CTRL_TCP_IPV6_SUPP | + RSS_CTRL_TCP_IPV6_EXT_SUPP | + RSS_CTRL_UDP_IPV4_SUPP | + RSS_CTRL_UDP_IPV6_SUPP; + + rss_ctrl |=3D FIELD_PREP(RSS_HASH_MASK, + ilog2(tp->rss_data->hw_supp_indir_tbl_entries)); + + RTL_W32(tp, RSS_CTRL_8125, rss_ctrl); +} + +static void rtl_set_rss_config(struct rtl8169_private *tp) +{ + rtl8169_set_rss_hash_opt(tp); + rtl8169_store_reta(tp); + rtl8169_store_rss_key(tp); +} + static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) { struct rtl8169_rx_ring *ring =3D &tp->rx_ring[0]; @@ -4094,6 +4238,18 @@ DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); } =20 +static void rtl8125_set_rx_q_num(struct rtl8169_private *tp) +{ + u16 rx_q_num; + u16 q_ctrl; + + rx_q_num =3D ilog2(tp->num_rx_rings); + q_ctrl =3D RTL_R16(tp, Q_NUM_CTRL_8125); + q_ctrl &=3D ~RTL_RX_Q_NUM_MASK; + q_ctrl |=3D FIELD_PREP(RTL_RX_Q_NUM_MASK, rx_q_num); + RTL_W16(tp, Q_NUM_CTRL_8125, q_ctrl); +} + static void rtl8169_hw_enable_vec_mapping(struct rtl8169_private *tp) { u8 tmp; @@ -4133,6 +4289,13 @@ static void rtl_hw_start_8125_common(struct rtl8169_= private *tp) tp->mac_version =3D=3D RTL_GIGA_MAC_VER_80) RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); =20 + /* enable rx descriptor type v4 and set queue num for rss */ + if (tp->num_rx_rings > 1) { + rtl8125_set_rx_q_num(tp); + RTL_W8(tp, RTL_DESC_TYPE_CTRL, + RTL_R8(tp, RTL_DESC_TYPE_CTRL) | RTL_DESC_TYPE_RSS); + } + if (tp->mac_version =3D=3D RTL_GIGA_MAC_VER_80) r8168_mac_ocp_modify(tp, 0xe614, 0x0f00, 0x0f00); else if (tp->mac_version =3D=3D RTL_GIGA_MAC_VER_70) @@ -4369,6 +4532,12 @@ static void rtl_hw_start(struct rtl8169_private *tp) rtl_hw_aspm_clkreq_enable(tp, true); rtl_set_rx_max_size(tp); rtl_set_rx_tx_desc_registers(tp); + if (rtl_is_8125(tp)) { + if (tp->num_rx_rings > 1) + rtl_set_rss_config(tp); + else + RTL_W32(tp, RSS_CTRL_8125, 0x00); + } rtl_lock_config_regs(tp); =20 rtl_jumbo_config(tp); @@ -4407,14 +4576,26 @@ static int rtl8169_change_mtu(struct net_device *de= v, int new_mtu) return 0; } =20 -static void rtl8169_mark_to_asic(struct RxDesc *desc) +static void rtl8169_mark_to_asic(struct rtl8169_private *tp, struct RxDesc= *desc) { - u32 eor =3D le32_to_cpu(desc->opts1) & RingEnd; + u32 eor; =20 - desc->opts2 =3D 0; - /* Force memory writes to complete before releasing descriptor */ - dma_wmb(); - WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); + switch (tp->init_rx_desc_type) { + case RX_DESC_TYPE_RSS: + eor =3D le32_to_cpu(desc->rss_opts1) & RingEnd; + desc->rss_opts2 =3D cpu_to_le32(0); + /* Force memory writes to complete before releasing descriptor */ + dma_wmb(); + WRITE_ONCE(desc->rss_opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZ= E)); + break; + default: + eor =3D le32_to_cpu(desc->opts1) & RingEnd; + desc->opts2 =3D cpu_to_le32(0); + /* Force memory writes to complete before releasing descriptor */ + dma_wmb(); + WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); + break; + } } =20 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, @@ -4437,9 +4618,12 @@ static struct page *rtl8169_alloc_rx_data(struct rtl= 8169_private *tp, return NULL; } =20 - desc->addr =3D cpu_to_le64(mapping); ring->rx_desc_phy_addr[index] =3D mapping; - rtl8169_mark_to_asic(desc); + if (tp->init_rx_desc_type =3D=3D RX_DESC_TYPE_RSS) + desc->rss_addr =3D cpu_to_le64(mapping); + else + desc->addr =3D cpu_to_le64(mapping); + rtl8169_mark_to_asic(tp, desc); =20 return data; } @@ -4456,8 +4640,25 @@ static void rtl8169_rx_clear(struct rtl8169_private = *tp, __free_pages(ring->rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); ring->rx_databuff[i] =3D NULL; ring->rx_desc_phy_addr[i] =3D 0; - ring->rx_desc_array[i].addr =3D 0; - ring->rx_desc_array[i].opts1 =3D 0; + if (tp->init_rx_desc_type =3D=3D RX_DESC_TYPE_RSS) { + ring->rx_desc_array[i].rss_addr =3D 0; + ring->rx_desc_array[i].rss_opts1 =3D 0; + } else { + ring->rx_desc_array[i].addr =3D 0; + ring->rx_desc_array[i].opts1 =3D 0; + } + } +} + +static void rtl8169_mark_as_last_descriptor(struct rtl8169_private *tp, st= ruct RxDesc *desc) +{ + switch (tp->init_rx_desc_type) { + case RX_DESC_TYPE_RSS: + desc->rss_opts1 |=3D cpu_to_le32(RingEnd); + break; + default: + desc->opts1 |=3D cpu_to_le32(RingEnd); + break; } } =20 @@ -4477,7 +4678,7 @@ static int rtl8169_rx_fill(struct rtl8169_private *tp= , struct rtl8169_rx_ring *r } =20 /* mark as last descriptor in the ring */ - ring->rx_desc_array[NUM_RX_DESC - 1].opts1 |=3D cpu_to_le32(RingEnd); + rtl8169_mark_as_last_descriptor(tp, &ring->rx_desc_array[NUM_RX_DESC - 1]= ); =20 return 0; } @@ -4642,8 +4843,13 @@ static void rtl8169_rx_desc_reset(struct rtl8169_pri= vate *tp) for (int i =3D 0; i < tp->num_rx_rings; i++) { struct rtl8169_rx_ring *ring =3D &tp->rx_ring[i]; =20 - for (int j =3D 0; j < NUM_RX_DESC; j++) - rtl8169_mark_to_asic(ring->rx_desc_array + j); + for (int j =3D 0; j < NUM_RX_DESC; j++) { + dma_addr_t phy_addr =3D ring->rx_desc_phy_addr[j]; + + if (tp->init_rx_desc_type =3D=3D RX_DESC_TYPE_RSS) + ring->rx_desc_array[j].rss_addr =3D cpu_to_le64(phy_addr); + rtl8169_mark_to_asic(tp, ring->rx_desc_array + j); + } } } =20 @@ -5099,28 +5305,95 @@ static inline int rtl8169_fragmented_frame(u32 stat= us) return (status & (FirstFrag | LastFrag)) !=3D (FirstFrag | LastFrag); } =20 -static inline void rtl8169_rx_csum(struct sk_buff *skb, - u32 opts1) +static void rtl8169_rx_hash(struct rtl8169_private *tp, + struct RxDesc *desc, + struct sk_buff *skb) { - u32 status =3D opts1 & (RxProtoMask | RxCSFailMask); + u32 rss_header_info; + u32 hash_val; + + if (!(tp->dev->features & NETIF_F_RXHASH)) + return; + + rss_header_info =3D le32_to_cpu(desc->rss_dword.rss_info); + + if (!(rss_header_info & RXS_RSS_L3_TYPE_MASK)) + return; + + hash_val =3D le32_to_cpu(desc->rss_dword.rss_result); + + skb_set_hash(skb, hash_val, + (RXS_RSS_L4_TYPE_MASK & rss_header_info) ? + PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); +} + +static void rtl8169_rx_csum(struct rtl8169_private *tp, + struct sk_buff *skb, + u32 opts1) +{ + bool csum_ok =3D false; + + switch (tp->init_rx_desc_type) { + case RX_DESC_TYPE_RSS: + if (((opts1 & RX_TCPT_DESC_RSS) && !(opts1 & RX_TCPF_DESC_RSS)) || + ((opts1 & RX_UDPT_DESC_RSS) && !(opts1 & RX_UDPF_DESC_RSS))) + csum_ok =3D true; + break; + default: { + u32 status =3D opts1 & (RxProtoMask | RxCSFailMask); + + if (status =3D=3D RxProtoTCP || status =3D=3D RxProtoUDP) + csum_ok =3D true; + break; + } + } =20 - if (status =3D=3D RxProtoTCP || status =3D=3D RxProtoUDP) + if (csum_ok) skb->ip_summed =3D CHECKSUM_UNNECESSARY; else skb_checksum_none_assert(skb); } =20 +static __le32 rtl8169_rx_desc_opts1(struct rtl8169_private *tp, struct RxD= esc *desc) +{ + switch (tp->init_rx_desc_type) { + case RX_DESC_TYPE_RSS: + return READ_ONCE(desc->rss_opts1); + default: + return READ_ONCE(desc->opts1); + } +} + static bool rtl8169_check_rx_desc_error(struct rtl8169_rx_ring *ring, + struct rtl8169_private *tp, u32 status) { - if (unlikely(status & RxRES)) { - u64_stats_update_begin(&ring->stats.syncp); - if (status & (RxRWT | RxRUNT)) - ring->stats.rx_length_errors++; - if (status & RxCRC) - ring->stats.rx_crc_errors++; - u64_stats_update_end(&ring->stats.syncp); - return true; + switch (tp->init_rx_desc_type) { + case RX_DESC_TYPE_RSS: + if (unlikely(status & RX_RES_RSS)) { + u64_stats_update_begin(&ring->stats.syncp); + + /* Note: The RTL8127 RSS descriptor layout does not have + * an RxRWT (Receive Watchdog Timer / over-length) bit. + */ + if (status & RXRUNT_RSS) + ring->stats.rx_length_errors++; + if (status & RXCRC_RSS) + ring->stats.rx_crc_errors++; + u64_stats_update_end(&ring->stats.syncp); + return true; + } + break; + default: + if (unlikely(status & RxRES)) { + u64_stats_update_begin(&ring->stats.syncp); + if (status & (RxRWT | RxRUNT)) + ring->stats.rx_length_errors++; + if (status & RxCRC) + ring->stats.rx_crc_errors++; + u64_stats_update_end(&ring->stats.syncp); + return true; + } } return false; } @@ -5140,7 +5413,7 @@ static int rtl_rx(struct net_device *dev, struct rtl8= 169_private *tp, dma_addr_t addr; u32 status; =20 - status =3D le32_to_cpu(READ_ONCE(desc->opts1)); + status =3D le32_to_cpu(rtl8169_rx_desc_opts1(tp, desc)); if (status & DescOwn) break; =20 @@ -5150,7 +5423,7 @@ static int rtl_rx(struct net_device *dev, struct rtl8= 169_private *tp, */ dma_rmb(); =20 - if (rtl8169_check_rx_desc_error(ring, status)) { + if (rtl8169_check_rx_desc_error(ring, tp, status)) { if (net_ratelimit()) netdev_warn(dev, "Rx ERROR. status =3D %08x\n", status); @@ -5160,11 +5433,21 @@ static int rtl_rx(struct net_device *dev, struct rt= l8169_private *tp, =20 if (!(dev->features & NETIF_F_RXALL)) goto release_descriptor; - else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) - goto release_descriptor; + + if (tp->init_rx_desc_type =3D=3D RX_DESC_TYPE_DEFAULT) { + if (status & RxRWT || !(status & (RxRUNT | RxCRC))) + goto release_descriptor; + } else { + if (!(status & (RXRUNT_RSS | RXCRC_RSS))) + goto release_descriptor; + } } =20 pkt_size =3D status & GENMASK(13, 0); + + if (unlikely(pkt_size < ETH_HLEN + ETH_FCS_LEN)) + goto release_descriptor; + if (likely(!(dev->features & NETIF_F_RXFCS))) pkt_size -=3D ETH_FCS_LEN; =20 @@ -5197,10 +5480,14 @@ static int rtl_rx(struct net_device *dev, struct rt= l8169_private *tp, skb->len =3D pkt_size; dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); =20 - rtl8169_rx_csum(skb, status); + if (tp->num_rx_rings > 1) { + rtl8169_rx_hash(tp, desc, skb); + skb_record_rx_queue(skb, ring - tp->rx_ring); + } + rtl8169_rx_csum(tp, skb, status); skb->protocol =3D eth_type_trans(skb, dev); =20 - rtl8169_rx_vlan_tag(desc, skb); + rtl8169_rx_vlan_tag(tp, desc, skb); =20 if (skb->pkt_type =3D=3D PACKET_MULTICAST) { u64_stats_update_begin(&ring->stats.syncp); @@ -5212,7 +5499,9 @@ static int rtl_rx(struct net_device *dev, struct rtl8= 169_private *tp, =20 dev_sw_netstats_rx_add(dev, pkt_size); release_descriptor: - rtl8169_mark_to_asic(desc); + if (tp->init_rx_desc_type =3D=3D RX_DESC_TYPE_RSS) + desc->rss_addr =3D cpu_to_le64(ring->rx_desc_phy_addr[entry]); + rtl8169_mark_to_asic(tp, desc); } =20 return count; @@ -5830,6 +6119,32 @@ static void rtl_set_irq_mask(struct rtl8169_private = *tp) } } =20 +static int get_max_irq_nvecs(struct rtl8169_private *tp) +{ + if (tp->mac_version =3D=3D RTL_GIGA_MAC_VER_80) + return R8127_MAX_NUM_IRQVEC; + return R8169_IRQ_DEFAULT; +} + +static int get_min_irq_nvecs(struct rtl8169_private *tp) +{ + if (tp->mac_version =3D=3D RTL_GIGA_MAC_VER_80) + return R8127_MIN_NUM_IRQVEC; + return R8169_IRQ_DEFAULT; +} + +static void rtl8169_set_rx_ring_num(struct rtl8169_private *tp) +{ + if (tp->irq_nvecs >=3D get_min_irq_nvecs(tp)) { + unsigned int rss_queue_num =3D netif_get_num_default_rss_queues(); + + tp->num_rx_rings =3D rounddown_pow_of_two(min(rss_queue_num, + tp->hw_supp_num_rx_queues)); + if (tp->num_rx_rings >=3D 2) + tp->init_rx_desc_type =3D RX_DESC_TYPE_RSS; + } +} + static int rtl_alloc_irq(struct rtl8169_private *tp) { struct pci_dev *pdev =3D tp->pci_dev; @@ -5850,7 +6165,14 @@ static int rtl_alloc_irq(struct rtl8169_private *tp) break; } =20 - nvecs =3D pci_alloc_irq_vectors(pdev, 1, 1, flags); + nvecs =3D pci_alloc_irq_vectors(pdev, get_min_irq_nvecs(tp), + get_max_irq_nvecs(tp), flags); + + if (nvecs < 0) { + dev_info(&pdev->dev, "Failed to allocate %d MSI-X vectors.\n", + get_min_irq_nvecs(tp)); + nvecs =3D pci_alloc_irq_vectors(pdev, 1, 1, flags); + } =20 if (nvecs < 0) return nvecs; @@ -6528,6 +6850,13 @@ static int rtl_init_one(struct pci_dev *pdev, const = struct pci_device_id *ent) tp->dash_type =3D rtl_get_dash_type(tp); tp->dash_enabled =3D rtl_dash_is_enabled(tp); =20 + if (rtl_hw_support_rss(tp)) { + tp->rss_data =3D devm_kzalloc(&pdev->dev, sizeof(*tp->rss_data), + GFP_KERNEL); + if (!tp->rss_data) + return -ENOMEM; + } + tp->cp_cmd =3D RTL_R16(tp, CPlusCmd) & CPCMD_MASK; =20 if (sizeof(dma_addr_t) > 4 && tp->mac_version >=3D RTL_GIGA_MAC_VER_18 && @@ -6548,6 +6877,11 @@ static int rtl_init_one(struct pci_dev *pdev, const = struct pci_device_id *ent) if (rc < 0) return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); =20 + rtl8169_set_rx_ring_num(tp); + + if (rtl_hw_support_rss(tp)) + rtl8169_init_rss(tp); + INIT_WORK(&tp->wk.work, rtl_task); disable_work(&tp->wk.work); =20 @@ -6560,6 +6894,11 @@ static int rtl_init_one(struct pci_dev *pdev, const = struct pci_device_id *ent) dev->vlan_features =3D NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; dev->priv_flags |=3D IFF_LIVE_ADDR_CHANGE; =20 + if (rtl_hw_support_rss(tp) && tp->num_rx_rings > 1) { + dev->hw_features |=3D NETIF_F_RXHASH; + dev->features |=3D NETIF_F_RXHASH; + } + /* * Pretend we are using VLANs; This bypasses a nasty bug where * Interrupts stop flowing on high load on 8110SCd controllers. --=20 2.43.0 From nobody Tue Sep 29 01:19:59 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5501F1DDC37; Mon, 28 Sep 2026 07:05:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" From: Javen Xu The patch moves the rtl8169_ethtool_ops definition further down in r8169_main.c so that subsequent additions of rtl8169_get_channels and rtl8169_set_channels can be referenced from the ops struct without needing forward declarations. Signed-off-by: Javen Xu --- Changes in v2: - no changes Changes in v3: - no changes Changes in v4: - no changes Changes in v5: - no changes Changes in v6: - modify commit message Changes in v7: - no changes Changes in v8: - no changes Changes in v9: - no changes Changes in v10: - no changes Changes in v11: - no changes Changes in v12: - no changes Changes in v13: - no changes Changes in v14: - no changes =20 Changes in v15: - no changes --- drivers/net/ethernet/realtek/r8169_main.c | 56 +++++++++++------------ 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethern= et/realtek/r8169_main.c index 1024cf4596b9..f14178f41801 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -2637,34 +2637,6 @@ static int rtl8169_nway_reset(struct net_device *dev) return phylink_ethtool_nway_reset(tp->phylink); } =20 -static const struct ethtool_ops rtl8169_ethtool_ops =3D { - .supported_coalesce_params =3D ETHTOOL_COALESCE_USECS | - ETHTOOL_COALESCE_MAX_FRAMES, - .get_drvinfo =3D rtl8169_get_drvinfo, - .get_regs_len =3D rtl8169_get_regs_len, - .get_link =3D ethtool_op_get_link, - .get_coalesce =3D rtl_get_coalesce, - .set_coalesce =3D rtl_set_coalesce, - .get_regs =3D rtl8169_get_regs, - .get_wol =3D rtl8169_get_wol, - .set_wol =3D rtl8169_set_wol, - .get_strings =3D rtl8169_get_strings, - .get_sset_count =3D rtl8169_get_sset_count, - .get_ethtool_stats =3D rtl8169_get_ethtool_stats, - .get_ts_info =3D ethtool_op_get_ts_info, - .nway_reset =3D rtl8169_nway_reset, - .get_eee =3D rtl8169_get_eee, - .set_eee =3D rtl8169_set_eee, - .get_link_ksettings =3D rtl8169_get_link_ksettings, - .set_link_ksettings =3D rtl8169_set_link_ksettings, - .get_ringparam =3D rtl8169_get_ringparam, - .get_pause_stats =3D rtl8169_get_pause_stats, - .get_pauseparam =3D rtl8169_get_pauseparam, - .set_pauseparam =3D rtl8169_set_pauseparam, - .get_eth_mac_stats =3D rtl8169_get_eth_mac_stats, - .get_eth_ctrl_stats =3D rtl8169_get_eth_ctrl_stats, -}; - static const struct rtl_chip_info *rtl8169_get_chip_version(u32 xid, bool = gmii) { /* Chips combining a 1Gbps MAC with a 100Mbps PHY */ @@ -6761,6 +6733,34 @@ static void r8169_init_napi(struct rtl8169_private *= tp) } } =20 +static const struct ethtool_ops rtl8169_ethtool_ops =3D { + .supported_coalesce_params =3D ETHTOOL_COALESCE_USECS | + ETHTOOL_COALESCE_MAX_FRAMES, + .get_drvinfo =3D rtl8169_get_drvinfo, + .get_regs_len =3D rtl8169_get_regs_len, + .get_link =3D ethtool_op_get_link, + .get_coalesce =3D rtl_get_coalesce, + .set_coalesce =3D rtl_set_coalesce, + .get_regs =3D rtl8169_get_regs, + .get_wol =3D rtl8169_get_wol, + .set_wol =3D rtl8169_set_wol, + .get_strings =3D rtl8169_get_strings, + .get_sset_count =3D rtl8169_get_sset_count, + .get_ethtool_stats =3D rtl8169_get_ethtool_stats, + .get_ts_info =3D ethtool_op_get_ts_info, + .nway_reset =3D rtl8169_nway_reset, + .get_eee =3D rtl8169_get_eee, + .set_eee =3D rtl8169_set_eee, + .get_link_ksettings =3D rtl8169_get_link_ksettings, + .set_link_ksettings =3D rtl8169_set_link_ksettings, + .get_ringparam =3D rtl8169_get_ringparam, + .get_pause_stats =3D rtl8169_get_pause_stats, + .get_pauseparam =3D rtl8169_get_pauseparam, + .set_pauseparam =3D rtl8169_set_pauseparam, + .get_eth_mac_stats =3D rtl8169_get_eth_mac_stats, + .get_eth_ctrl_stats =3D rtl8169_get_eth_ctrl_stats, +}; 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Mon, 28 Sep 2026 15:04:27 +0800 From: javen To: , , , , , , , CC: , , Javen Xu Subject: [PATCH net-next v15 7/7] r8169: add get_channel support for ethtool Date: Mon, 28 Sep 2026 15:04:23 +0800 Message-ID: <20260928070423.202-8-javen_xu@realsil.com.cn> X-Mailer: git-send-email 2.50.1.windows.1 In-Reply-To: <20260928070423.202-1-javen_xu@realsil.com.cn> References: <20260928070423.202-1-javen_xu@realsil.com.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Javen Xu Add get_channel support for ethtool. Signed-off-by: Javen Xu --- Changes in v11: - new file, no change Changes in v12: - no changes Changes in v13: - no changes Changes in v14: - no changes =20 Changes in v15: - no changes --- drivers/net/ethernet/realtek/r8169_main.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethern= et/realtek/r8169_main.c index f14178f41801..7c27254218cc 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -6733,6 +6733,22 @@ static void r8169_init_napi(struct rtl8169_private *= tp) } } =20 +static void rtl8169_get_channels(struct net_device *dev, + struct ethtool_channels *ch) +{ + struct rtl8169_private *tp =3D netdev_priv(dev); + + if (tp->irq_nvecs > 1) { + ch->max_rx =3D tp->hw_supp_num_rx_queues; + ch->max_tx =3D 1; + ch->rx_count =3D tp->num_rx_rings; + ch->tx_count =3D 1; + } else { + ch->max_combined =3D 1; + ch->combined_count =3D 1; + } +} + static const struct ethtool_ops rtl8169_ethtool_ops =3D { .supported_coalesce_params =3D ETHTOOL_COALESCE_USECS | ETHTOOL_COALESCE_MAX_FRAMES, @@ -6751,6 +6767,7 @@ static const struct ethtool_ops rtl8169_ethtool_ops = =3D { .nway_reset =3D rtl8169_nway_reset, .get_eee =3D rtl8169_get_eee, .set_eee =3D rtl8169_set_eee, + .get_channels =3D rtl8169_get_channels, .get_link_ksettings =3D rtl8169_get_link_ksettings, .set_link_ksettings =3D rtl8169_set_link_ksettings, .get_ringparam =3D rtl8169_get_ringparam, --=20 2.43.0