From nobody Tue Sep 29 08:26:17 2026 Received: from mx0b-0002e601.pphosted.com (mx0b-0002e601.pphosted.com [148.163.154.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1499C30594F; Mon, 28 Sep 2026 02:58:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.154.28 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564327; cv=fail; b=jxQ8l4xczkVig42m8D0J6SUXH+yDqKK76gztDUMqTJxFN1ZVZMzod13do451HD5TIWVx9nlicAk82CeNAbCU6I06e7qUm2NYB5DpC/wjRvrLW1poH4GZhTFgdcAuJGBD1ceOnLxb5bS7g2ABqdMF4wvCj0NQPJw1t6j9cPc91ts= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564327; c=relaxed/simple; bh=Yb68ywnxktAOqzC7HH9iP2aGbIV1+15VbDByTdOE3mE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LGYqgkocKBpRLvWkXgqAVwFNLpnU6hZJOTXtYiWAvFcJ/SzvQWOX0dw07GPwG3/iyv808AtIv2K6w5cwjC6NGCVn3nfhaxKt/gw1N1AUgrLH6uFB/RIrKileKhipYkB5wjRjoozJR65zrmJiA1GPvVsGiUo6p0vzdXQ9ZbLh+XE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=NseRCowA; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=mjdY4k33; arc=fail smtp.client-ip=148.163.154.28 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="NseRCowA"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="mjdY4k33" Received: from pps.filterd (m0374955.ppops.net [127.0.0.1]) by mx0b-0002e601.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68RMIQXK2806212; Sun, 27 Sep 2026 21:58:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=MQ7P50QmbBfwGmZaR3Z/gNisrqNUd3IhQuygJr1B3 UY=; b=NseRCowAPitS1+Zgpvotjh9smq89eu2npkNVVFnevyRI+C2D2nn0k76fE s0JiHJ/W1+ffmGsXB1cZlteeQcTJnCt8F99W9ejtimXLZPQ75TPybTzu0wzvYJ2F MFylFjrYN1bcp4QPzdZKD3rdvZocdsgx7pPYSr5agH+tkCz5PCArgKwZwyZR8Qa8 S+CKAbzywksjQxO4y7ZuIi+mD9n9446/TulWQEgy8ciNEtwRiKbcS7ZpIlDx62UH cURXv9YxYINTqRICV0mv+/luZqIjeFDpccTmDER8KK0H1TZIFdeo7kLRJaRu6acx R4RWkjkSfcDwGBzU5plcrqSB7Pykg== Received: from byapr05cu005.outbound.protection.outlook.com (mail-westusazon11010056.outbound.protection.outlook.com [52.101.85.56]) by mx0b-0002e601.pphosted.com (PPS) with ESMTPS id 4gxwe5kfnp-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Sun, 27 Sep 2026 21:58:36 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Nc704lb8oGKduUhkNf8pNrYDLOxbc8PpWsQqEcTRN6o1fgEAIg15A3NoIwGZpgf2Sn4SwCkliiMou5qlRTVxYoB7yCtMVEG2O7az2E3hRdPRCdjQYzIkpZFt6dBSBPh4yOMYCTXPxVyZaGT3GHV4rlCQlqlKV45fc1w/tTr14hsZhswRT2UmJx60JtBgWSC4xjuC3jwXrowRVewee/+YhlDf6a4jg9jU7kBIhY0YxBtWvTDnE6uk1fjfP74g9CBSIDo5ctHVvDskxyEC+mwx9k9XvbtTgc9CsUp26e4PqBU12Fd6YwBZuRB1H7IZZdQFBA6FaPGV4totE0GYUDV5hA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MQ7P50QmbBfwGmZaR3Z/gNisrqNUd3IhQuygJr1B3UY=; b=ahUGolDDKN+ihKOMBsJXFVpGslnYNf1Y4tsBwLIr6YgFfyVi5PnqKb6GXKrXme0Pc5edwm3FD7nxym5zSphxHAlvrb3VCZNCCLo3wc7lMY2q20dljjOvoRIf8oqNu6qY5V8n4A9sA86rVOFL8VYHlzgysWr4zDECR3aJqtI44O25nySwo/C1Ulbi6a5gcKvkf0L+9W02tcYTIxr2x0ExhGtfCnN3nfoEGbbBE40HWJDihIV0wcKdo6mcQ1EtwZ25um6cG6abSHcxXRU0BQw61d7NP/wbamEja8J0cL7bNzX9oHKjdTpD9r8EWqJgAz8tce2dgAQd+D2oQbC1GhfTrw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.21.194) smtp.rcpttodomain=nxp.com smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MQ7P50QmbBfwGmZaR3Z/gNisrqNUd3IhQuygJr1B3UY=; b=mjdY4k33FwQ1MsMOA7eFssy90CAEe3COMCq1P6no8x0AmlP6a6lolIkRphCuDARcUnlrxcx3hLTlw064heiV2a352njbZWn97rh9xkhWdgEXCvDDx2S9wi0wIK1f8v018qGbbvI4Ikvw4I6W0uB0DQx55gI9nmFPB0R0LPU/aYY= Received: from DS1P220CA0010.NAMP220.PROD.OUTLOOK.COM (2603:10b6:8:455::16) by CY5PR10MB6238.namprd10.prod.outlook.com (2603:10b6:930:42::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.451.18; Mon, 28 Sep 2026 02:58:33 +0000 Received: from DS2PEPF000061C2.namprd02.prod.outlook.com (2603:10b6:8:455:cafe::f) by DS1P220CA0010.outlook.office365.com (2603:10b6:8:455::16) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.451.23 via Frontend Transport; Mon, 28 Sep 2026 02:58:33 +0000 X-MS-Exchange-Authentication-Results: mx.microsoft.com 1; spf=pass (sender IP is 198.47.21.194) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.21.194 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.21.194; helo=flwvzet200.ext.ti.com; pr=C Received: from flwvzet200.ext.ti.com (198.47.21.194) by DS2PEPF000061C2.mail.protection.outlook.com (10.167.23.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Mon, 28 Sep 2026 02:58:32 +0000 Received: from DFLE209.ent.ti.com (10.64.6.67) by flwvzet200.ext.ti.com (10.248.192.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:02 -0500 Received: from DFLE210.ent.ti.com (10.64.6.68) by DFLE209.ent.ti.com (10.64.6.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:02 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE210.ent.ti.com (10.64.6.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45 via Frontend Transport; Sun, 27 Sep 2026 21:58:02 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [10.24.51.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 68S2vqq82256662; Sun, 27 Sep 2026 21:57:58 -0500 From: Sai Sree Kartheek Adivi To: , , , , , , , , , , , , , CC: , Subject: [PATCH v10 01/19] dmaengine: ti: k3-udma: Fix sporadic crash on AM62x Date: Mon, 28 Sep 2026 08:26:07 +0530 Message-ID: <20260928025749.1055383-2-s-adivi@ti.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260928025749.1055383-1-s-adivi@ti.com> References: <20260928025749.1055383-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF000061C2:EE_|CY5PR10MB6238:EE_ X-MS-Office365-Filtering-Correlation-Id: 08327734-46ca-44f6-d551-08df1d0c6187 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700016|82310400026|23010399003|1800799024|10067099003|56012099006|18002099003|22082099003|921020; X-Microsoft-Antispam-Message-Info: Geo6Y7CeHirC3MzSB0As+slScrbMz0nNtAYrWVpg/XKUg/MKrQDyDXNtYSWH2QPf96RfO2dnEq7W0UYxsrHzi+7F3+eFtYRIOLwRHsdtSYqoLdzhix3p7lrrmmHoxbVXXCCWJMonWEwJwgnC7tLlTTMvSsxpXfue9aeaBm2rIXbAq3Y853kUMQPlA32mSpGYKOfzzSTuIVjzZi6/ZpVTzhQ1YRRHRngg4iMLEkL/yaG5SGD2DQO+83N79r1NlFW1HL7H9dhW3zZ0jhP2fmxaofBHMRYDDiE2xuYdB/eXqUs/QpBb3h4acRNoGGxkYPb5DUo9nOl7ZnA7P5Gt7DOArzHT/n2K0SLFjaruefe8Z+bRaymMEaQvxUrdUyFyDp+YmVL31ARR3G16zaZu1RaxLcp4+8v19p6mLc5W28cewYWWxGfeTjXDae+aYaALdLDoICsBFpDWDztx++uFH90okDBAXR53jKSmJ0cVT0dbanFId/v24U6lCS62uDx52kLIBCAKfrByEFT30URiPrGAw4UGi4rbK2L7+21z73qEA6xlw0e6PSWwbDhllPOrVFSYAHVWBTuo7NPas8AhjoeP98GIIDxqVYn1cziUR7PYVHD2vXTWk4TJsbudE7WGOrZISDth6GPwEL64BbYkMoWDDmIuw8xUH9jb58ABp62YoAwWjTqagwJcXByvRVJeIhOPdY3DaNJdg3kPWmob8G07lWw48M0NQo8dx2vIsC0xapvmjbppwYPHfOZOL6rwJrwo X-Forefront-Antispam-Report: CIP:198.47.21.194;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:flwvzet200.ext.ti.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700016)(82310400026)(23010399003)(1800799024)(10067099003)(56012099006)(18002099003)(22082099003)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: FgzqKzOZ6n8g9Q+fqOeYBS7eyHgxMzQjkaeJwA5ouAB5Bo5bOSh1rDmLVZcCB8pBjkcD6+NmFI6TnLhRnf5ETmVl8DqMzG+1PyGKeBPcSEW66z2z3EWstjIUb325DY0+uKtxHoHFwZENeXEwKAnsQTeUVOThWIaQbmWfJQJTNyccc2hbWzCbU/7DlpV8HfoE/plauQ9BMxsK6zy7kvnbB9BfDZEhyNs56YFZdQ4a5JaCIuCxRrrVpFLbHJWCgQg4P26zNqWlvCEsl4+yYPSDE/VitzA3Gvalvse1iGnhWHIREWLaxUcMSEoO2ZQacbVNPk+2J7lmlb0zEq7f0kBxlfwGzShW4D42cdwMK1/gvRQbQF43Gp17c5nQXUqCbUKy3LvxwGWIhaBocmAnou2K2nTYAyGXgeoDBhAsCdXEVOkrStWN7xbwBpLqTxEKBc+F X-Exchange-RoutingPolicyChecked: HJBnT8vh0dHPzliUsC9smnC8K0C5TDnmhKBEzDYDUN96eEM5jjsyOolTTXygQHV0L4XfUAflOhSBlcAlKE0hQjwgRSeqDX/uaBkUSiL2Nm1qgXvekfr7cWEcBEhWvYUHjZU3rZoT70fPRWEHPyqF2Eq4Vg+BGXWXpMaPR8otVPn0LTy17RZtJ/fTFMG09QInPeo40O2S4AH/mRCKM/U3WQna4bG318QkKZt4E4TAxA0bERGQACk8e81BEDgo0t4E+sJcB3weqgUGSvZyQ5unuw3lihkAmINw2ce3am/VC8thUaRjDSHLBqD9zUEcJhCFgUHyPN8uBYbDd7YFw8long== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 02:58:32.1952 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 08327734-46ca-44f6-d551-08df1d0c6187 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF000061C2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR10MB6238 X-Authority-Analysis: v=2.4 cv=aeP0Dhot c=1 sm=1 tr=0 ts=6ab9d7dc cx=c_pps a=CnS1ju6qDdjTg6bRefQovg==:117 a=iwqwCZQqcuTv3JOpYdM7/Q==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=VdqzKS8jKosA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=fPAWb5peG099m5CrUpKH:22 a=sozttTNsAAAA:8 a=YS4YLeW4SzYDQNh2yKMA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX+qpSk79nFZBw y51Vf9OWvqAJPJSoeFAevm69V96wLnBRg6ZV9urnDiLgGj1j87lunXQNuyCWw8K0lXfUCAV8Nmq dj1twfqFsyHXDc8eIln09SG3YG1HTYqeg2oG61c2PtUZmcerCKZrUiwN6RLjBg6rXA851BlCrSQ HV3KxEoExTaxb+BQw67rVmScmTH3fM+iJbmLgTl//cXYdRXsSkcgCAUQRIu/Pfwl5ex9tbfcaYl Svyhog18QuWFjUgq860sspjqMZ4UuY13PDE/uWK8+Trpl/ZrY1lp9ib3NPneu5vJSrmqAfadkzM FnzuJY0c/r/548LBBb5dOQMg2uAICAR2xv9EZtcQ9jSM2b2tyVUFBHDbnZ2q3v7GQYkXVYlqW4W 0GtX7ncGlmbyh5CdkFFigW2O5fymrUm+30nYj2MN4wLyQhUSr9IoaJZHTu7pzyKe2FeidBkXCPK evbP67gMMb+qkAryXfg== X-Proofpoint-ORIG-GUID: E8yyCNbGfJxiuwDUoykaOcIB4nmQDpKp X-Proofpoint-GUID: E8yyCNbGfJxiuwDUoykaOcIB4nmQDpKp X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX5lU8KVy9eRns JhJEvxEcwm1At0KulJkFlfJYqP1/WSxNBN2Xl9l/KFrZPITb+PrqZtqtF975YEGhjCDEi6xiTF6 xh++UU/MjgBzZp+dWQMLv5YQDQJSZ2k= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 phishscore=0 spamscore=0 clxscore=1015 adultscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280011 Content-Type: text/plain; charset="utf-8" From: Vignesh Raghavendra ring_init_data is declared on stack and thus can contain garbage which can lead to k3_ringacc_dmarings use junk address for ringrt base leading to below crash during ring pop [ 1.998239] cadence-qspi fc40000.spi: couldn't determine phase-detect-se= lector [ 2.532106] Unable to handle kernel paging request at virtual address ff= ff800081a84b98 [ 2.540051] Mem abort info: [...] [ 2.629987] Workqueue: events_unbound deferred_probe_work_func [ 2.635832] pstate: 800000c5 (Nzcv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE= =3D--) [ 2.642787] pc : k3_ringacc_ring_pop+0x48/0x94 [ 2.647234] lr : udma_pop_from_ring+0x7c/0xb4 [...] [ 2.726250] Call trace: [ 2.728691] k3_ringacc_ring_pop+0x48/0x94 [ 2.732786] udma_ring_irq_handler+0x34/0x218 [ 2.737141] __handle_irq_event_percpu+0x60/0x14c [ 2.741846] handle_irq_event+0x4c/0xa8 Fix this by explicitly initializing the variable to 0. Fixes: 017794739702 ("dmaengine: ti: k3-udma: Initial support for K3 BCDMA") Signed-off-by: Vignesh Raghavendra --- drivers/dma/ti/k3-udma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 78a67cb9d6e00..8457644cb9132 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -5484,7 +5484,7 @@ static int udma_probe(struct platform_device *pdev) if (ud->match_data->type =3D=3D DMA_TYPE_UDMA) { ud->ringacc =3D of_k3_ringacc_get_by_phandle(dev->of_node, "ti,ringacc"); } else { - struct k3_ringacc_init_data ring_init_data; + struct k3_ringacc_init_data ring_init_data =3D { 0 }; =20 ring_init_data.tisci =3D ud->tisci_rm.tisci; ring_init_data.tisci_dev_id =3D ud->tisci_rm.tisci_dev_id; --=20 2.54.0 From nobody Tue Sep 29 08:26:17 2026 Received: from mx0b-0002e601.pphosted.com (mx0b-0002e601.pphosted.com [148.163.154.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C623370D5C; Mon, 28 Sep 2026 02:58:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.154.28 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564341; cv=fail; b=qez3S2YljaZwTMRrJieaKvDyeRmI7Hm8Dv9fJtUi6uHQDIaaUzHbKaiibx4TGA4/8j706+gu0lC2RzAmXsMIgjwz4aNJpNUdJwknVgGLCxBJ7rpG+Ey24MZz90YqSdL/Vh59S5ajV4dPYIcQDMCPmm2P0n/bBjGcGH3hoIqG+zM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564341; c=relaxed/simple; bh=ShSg+QoaLIO4hbZSZgkMejppZjWjSKbs1QKIYiTDSh8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=paAbT6ahnHtUNqfF1g7eXMPqOyFoWELs+PPWnIAMIC6jEa1sOCaA9yvR0IFyNi/ApGFMqOQ9rBuq7hYAD2voSLUdelxh5N6ChrATNkqIQpJR9/n1vAPVTaiX31eSWXZ9viRwH9M5/FNDG4B7YsQX19tPcdMAW6ulo6B7zadpWLE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=gvFjLf+T; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=vZ0MSFY7; arc=fail smtp.client-ip=148.163.154.28 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="gvFjLf+T"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="vZ0MSFY7" Received: from pps.filterd (m0374955.ppops.net [127.0.0.1]) by mx0b-0002e601.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68RK4U2j2807666; Sun, 27 Sep 2026 21:58:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=rCQNGoXps1QncXA4n5E9I2k+f6PXY4YgK3IBMNZjt Ug=; b=gvFjLf+TU8Dh2Tx/VLLbX5Cxn3+LXaFxlgegv0O8e1KLoGw9tbg9GscGw SEeiSxHylMfYUANbuakKCmv2TemXmvP0L0OpIQgc1Xs19kiUcm9RmM9iHAm/0V9Q 2EIBCYJDl4MtH8wxNTZ9TCwxKO+Wcz93PaZuNAUByhAMxDUWo1qeT6MMOCTDs9UA ipllmV2BMVfPQ59a78WUB04cF/uQxSUAmJI0uSfJoxZSojEUMS1uXFXY1o0w2GeU fi1UNzXII0VJWmgkLUfYzIvzqavJzdRXLEruZZf1dOXIO8gMIrn9tNBTD1oBjhkY 4pin+Lj1s8cGZLTkNutHHxceTqgKQ== Received: from ph7pr06cu001.outbound.protection.outlook.com (mail-westus3azon11010002.outbound.protection.outlook.com [52.101.201.2]) by mx0b-0002e601.pphosted.com (PPS) with ESMTPS id 4gxwe5kfpk-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Sun, 27 Sep 2026 21:58:51 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=PlFZjRP4j2vlyIE00r8Bn9UwEHrC98oey3yAjjJCYvOh17zy0RR9wUZtVOhhdsIX3I+6pktDp4gZNAB07OxcIzxkyO3cWdVt3AXGhnjna8pZ4wtGMvz5KofuCahclgp3vuSeM7B7WNtTWfX2EesA90tnIyCWXvo7GhxwmkVDHFqKnu3ZCoxXdLhs8mM6hO3gt6CTggICf3OJImtEMPdV1yrOj10RPi4Znjo3vLdqAAnOnWij50BrACYPINqmq4Sk3da4ai3+pJ/99tOC1fpNEz39UG2NYkii2X+aoKRYIZEwsii3MKiEcq7ctNwr97eDRMvAZit5cNiSeS83tfiWxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=rCQNGoXps1QncXA4n5E9I2k+f6PXY4YgK3IBMNZjtUg=; b=K6kKk32bbP40shhFq9RjqT8I15qsC90HX8rS4HWhnEc2/mYjC02tU+0HJ2LebAENY9pIuLO+kZ5iHh6eX+tlCPCRYIanx5e3Rg7UYFWrDzrbqElm7WFp4XSPd4+Ext/qXFw+FfsOixCKAR8EkgPPNXuC2a6muKm3p7NWj59mGuFaQQZuoWle9dwBlCU2SiFjFLA9w/nYQRd/KqB8FvooIQH3P1p6Q9kpClspBdIQ/kGQ7ZbOxhEZXFOgIk/jZAqkSp0wYaQfIZFJapYm/pLVOBnEzh/5eYaO5LR/nc31Wlp3g3NNTsi1GWCsZWGohL27xg/qRrw+zJ5bFG+T4dR7pA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.21.195) smtp.rcpttodomain=nxp.com smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=rCQNGoXps1QncXA4n5E9I2k+f6PXY4YgK3IBMNZjtUg=; b=vZ0MSFY7fGP7JVWMVryRP5SIBEwhQUQB5pNRUe3eEoUPVpSm3M900g0j0OPTFvRmP/7g5g6kyHAam00dnz7sA53uuJJ/32HeY/ANGhYTN+XTtBdP5AuqHcHkj06QONVviANlBY03gvuBPbXtHzKG11T3mEoQAMe5q/jCG87tJ4Y= Received: from CH0PR03CA0187.namprd03.prod.outlook.com (2603:10b6:610:e4::12) by CY8PR10MB6609.namprd10.prod.outlook.com (2603:10b6:930:57::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.6; Mon, 28 Sep 2026 02:58:48 +0000 Received: from CH3PEPF00000018.namprd21.prod.outlook.com (2603:10b6:610:e4:cafe::22) by CH0PR03CA0187.outlook.office365.com (2603:10b6:610:e4::12) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.451.23 via Frontend Transport; Mon, 28 Sep 2026 02:58:47 +0000 X-MS-Exchange-Authentication-Results: mx.microsoft.com 1; spf=pass (sender IP is 198.47.21.195) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.21.195 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.21.195; helo=flwvzet201.ext.ti.com; pr=C Received: from flwvzet201.ext.ti.com (198.47.21.195) by CH3PEPF00000018.mail.protection.outlook.com (10.167.244.123) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.496.3 via Frontend Transport; Mon, 28 Sep 2026 02:58:46 +0000 Received: from DFLE213.ent.ti.com (10.64.6.71) by flwvzet201.ext.ti.com (10.248.192.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:07 -0500 Received: from DFLE215.ent.ti.com (10.64.6.73) by DFLE213.ent.ti.com (10.64.6.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:07 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE215.ent.ti.com (10.64.6.73) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45 via Frontend Transport; Sun, 27 Sep 2026 21:58:07 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [10.24.51.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 68S2vqq92256662; Sun, 27 Sep 2026 21:58:02 -0500 From: Sai Sree Kartheek Adivi To: , , , , , , , , , , , , , CC: , Subject: [PATCH v10 02/19] dmaengine: ti: k3-udma: move macros to header file Date: Mon, 28 Sep 2026 08:26:08 +0530 Message-ID: <20260928025749.1055383-3-s-adivi@ti.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260928025749.1055383-1-s-adivi@ti.com> References: <20260928025749.1055383-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000018:EE_|CY8PR10MB6609:EE_ X-MS-Office365-Filtering-Correlation-Id: 1ca298c0-2f55-4b50-fd25-08df1d0c6a55 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|7416014|82310400026|376014|1800799024|36860700016|921020|10067099003|56012099006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: qDMCiUSA4uxhUU8FHsebj8FlOZVTPb2bdhnUNNYPpRRaHOdeLd4YipIWABQkeDf259WX3Zi1lcFEj7OxjssLlfnXjeWUmafyvRUbI8VhJRcRgYJOj3vL9FQhDhhxeVIJLw4Of36hdQBP8nZbVUgEtsFRMA1b6fwheDIDSqsWFRcbYHO4R3ipZh/95c0gS5dOSSnIRO2yMhNXt1K+AwdSLF4/R22fcxMOEoZ1dWo4Efgmnx3riqAx8WVQrw/8b/7roIGalD9U10xsfbIPs/lk7mOsjCi3qCgeku39WtUDhSGhsgYKgU9DVDuVI4EmZ72i3UM4iGFzKm3mlGaGamyBxAF0mL8MsFvKGG5nhMvyuH6g2J66N5bJ9V7DcLHWLYNW0h9uhChb4ccdW0XCmhp7iwHaSFAot+7pfj+8/8gvnQiFRI8njbGzd0Xd/puhSTuRxCCph7lcmLCDs30LazudCBgeg1CsuKBr6I//G0cMNUDyboMRx/7Xen3fK4QTtNm79lsd/lEvMtmxzEraLxhr7+lkF0cQLrTCn3NFVhqBr7zT1E8e4yJeBe/+cbdxHKLisHwHszYsWgHr6GGwmNS1C0Se8+QY1AigGryT8Fp1tOCYMc28JIzFiw0D7E/Mhe3xL05RcbsjQTt1IBbpGg4FmeWV3+F4DLUyzqrCWGADj5uab5eHg4GhbCDujyi17hRwmVDQuBp0K9ILxySaGxkGp6lJDD/ps7KoTOXD6XBh8shDiDZc7PZ9F7xlddMTDiNu X-Forefront-Antispam-Report: CIP:198.47.21.195;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:flwvzet201.ext.ti.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230040)(23010399003)(7416014)(82310400026)(376014)(1800799024)(36860700016)(921020)(10067099003)(56012099006)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: tL2GnH3CmHg7uWdjYo5RGApmOSWkOyELGeMh0b7XPqr3+kNPcKLcE5hGgI40Ymig8qn1Tn6l0wEVZAHrS+PL1JVdSPxDEoxEUxapvycTpP94oq2glMDZ/VsFQCPtqEqCgomLovO08HusjoSGna7QctO+6GZVzZJm9b5VJmN5tHzJPyDWOePZbe0drLWE0yf3zS/tEYZNky+ToPm2Iyz4KcFq4AE4PpNAD8RYJFnwDOIHnQllhnjGeOTneupAef263L3qShKtrrxL9J1NR5y5jh1/crk58NAxv9/tHFHLypyb01Y3BsO/3dFKLJQmCRh6R8u6j0HSzGSI2sBYC+PGSIm8jUGhVjeYsoRYzcjPBG4rJl3kNwzXf0OMc5xLSZbViEsMYSDRzQMIUn/Ftv0/Ur/smKuFU5z133DZLBsFJMzOiDVBGLMZMX5uQBPtksDX X-Exchange-RoutingPolicyChecked: xLHoZK+njNOenMDcMPpGgnjnj05ctr4emKMH9fgJyq2/+vVu0qah6ZY5yqM7BDTOUhj5qrfwimHi3bH+qqnwQlhqa1nP0aKxEMOoJoE+UQdfjhgbsfL6p1Jx17BjCBFtQbB2r6DU+3ROTEvssz6WuQMTNXgAAETu35QrgDqiWJHt+ajUPbvE0guycYKw8jKzvMIk8eUy1J+HUk/5/KiJZSEzJGHadYxlbeogVgWEBh38flZa0MGD0qec7X9v/bmlzG3PUxgpSnYZYcyftb3FQm4/LJQSkXl55UHISdE962AwytdEfvU5nI768wWE94arPN7KwCU1pTUUEwfTM7E57w== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 02:58:46.9797 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1ca298c0-2f55-4b50-fd25-08df1d0c6a55 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000018.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR10MB6609 X-Authority-Analysis: v=2.4 cv=aeP0Dhot c=1 sm=1 tr=0 ts=6ab9d7eb cx=c_pps a=N6h9FcIU3O7PIE8+NyeJww==:117 a=tJyPKKxUohctrY4NYmUjkA==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=VdqzKS8jKosA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=fPAWb5peG099m5CrUpKH:22 a=8AirrxEcAAAA:8 a=sozttTNsAAAA:8 a=u0Ry9gnqgf_Ls9jc7UwA:9 a=ST-jHhOKWsTCqRlWije3:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX1Iqz53IGzAmB k/8gnmmQVkL125pHyqWmLtKZGd5bwd2CgJbSxHqRwUpcy05K5l4mOm/9YQZQ4FSl+1EQOdQh2KX Sz4MpKBaTsl6AkhwFXXqebKFAeqigupKqOxPNBpw3jz3FxvTvyE+CwZTY1Uy6y2YMZ64Bx8dMbb i+5lpoQ2pRsZml40HxmUgs5oayCv7j+3drqgopAxceB8+GCVd9RrBdFF4ihnjl2NFZWlXuztK1L hd38unY/Wv5zbvVPYBudVKhne89xwne+/1TThXU1IKI0OPUsWbaAl/q0DMKT23/PyvHuIdY2u8X SEF0jg/mZQTochinivHSxEvMZ/3K/FvzSvX7qnJyxiv1TaubM7MXRq4oMkHesOHnbW2IuPw/GXu l0hu0+M7QMGOa+l2nxHmHSewTg2B3wyFnxEl8/g/shhXe2sgg8eaDK6NAyDU6ZYUN3q8DK5peiZ GRcy+XxIa0dFvvsSInw== X-Proofpoint-ORIG-GUID: pnbyBLeq6YCL-_oednsLMPVLVtQGr9Oj X-Proofpoint-GUID: pnbyBLeq6YCL-_oednsLMPVLVtQGr9Oj X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX14HGvE2HtYUG ROzohr3w2mOUJ22yV5hBdmQc5H14CdQg3khNcFNGkt0R+s49A+xCljgnFwYuX//2hc5PnfcoglM PktzQOOVZUWywqvzxPwbuFZTaPoLZlM= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 phishscore=0 spamscore=0 clxscore=1015 adultscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280011 Content-Type: text/plain; charset="utf-8" Move macros defined in k3-udma.c to k3-udma.h for better separation and reuse. Reviewed-by: Frank Li Signed-off-by: Sai Sree Kartheek Adivi --- drivers/dma/ti/k3-udma.c | 62 --------------------------------------- drivers/dma/ti/k3-udma.h | 63 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+), 62 deletions(-) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 8457644cb9132..a1b99097a94ad 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -39,21 +39,6 @@ struct udma_static_tr { u16 bstcnt; /* RPSTR1 */ }; =20 -#define K3_UDMA_MAX_RFLOWS 1024 -#define K3_UDMA_DEFAULT_RING_SIZE 16 - -/* How SRC/DST tag should be updated by UDMA in the descriptor's Word 3 */ -#define UDMA_RFLOW_SRCTAG_NONE 0 -#define UDMA_RFLOW_SRCTAG_CFG_TAG 1 -#define UDMA_RFLOW_SRCTAG_FLOW_ID 2 -#define UDMA_RFLOW_SRCTAG_SRC_TAG 4 - -#define UDMA_RFLOW_DSTTAG_NONE 0 -#define UDMA_RFLOW_DSTTAG_CFG_TAG 1 -#define UDMA_RFLOW_DSTTAG_FLOW_ID 2 -#define UDMA_RFLOW_DSTTAG_DST_TAG_LO 4 -#define UDMA_RFLOW_DSTTAG_DST_TAG_HI 5 - struct udma_chan; =20 enum k3_dma_type { @@ -118,15 +103,6 @@ struct udma_oes_offsets { u32 pktdma_rchan_flow; }; =20 -#define UDMA_FLAG_PDMA_ACC32 BIT(0) -#define UDMA_FLAG_PDMA_BURST BIT(1) -#define UDMA_FLAG_TDTYPE BIT(2) -#define UDMA_FLAG_BURST_SIZE BIT(3) -#define UDMA_FLAGS_J7_CLASS (UDMA_FLAG_PDMA_ACC32 | \ - UDMA_FLAG_PDMA_BURST | \ - UDMA_FLAG_TDTYPE | \ - UDMA_FLAG_BURST_SIZE) - struct udma_match_data { enum k3_dma_type type; u32 psil_base; @@ -1837,38 +1813,6 @@ static int udma_alloc_rx_resources(struct udma_chan = *uc) return ret; } =20 -#define TISCI_BCDMA_BCHAN_VALID_PARAMS ( \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID) - -#define TISCI_BCDMA_TCHAN_VALID_PARAMS ( \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID) - -#define TISCI_BCDMA_RCHAN_VALID_PARAMS ( \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID) - -#define TISCI_UDMA_TCHAN_VALID_PARAMS ( \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID) - -#define TISCI_UDMA_RCHAN_VALID_PARAMS ( \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID) - static int udma_tisci_m2m_channel_config(struct udma_chan *uc) { struct udma_dev *ud =3D uc->ud; @@ -5398,12 +5342,6 @@ static enum dmaengine_alignment udma_get_copy_align(= struct udma_dev *ud) } } =20 -#define TI_UDMAC_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ - BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ - BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ - BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ - BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) - static int udma_probe(struct platform_device *pdev) { struct device_node *navss_node =3D pdev->dev.parent->of_node; diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h index 9062a237cd167..750720cd06911 100644 --- a/drivers/dma/ti/k3-udma.h +++ b/drivers/dma/ti/k3-udma.h @@ -97,6 +97,69 @@ /* Address Space Select */ #define K3_ADDRESS_ASEL_SHIFT 48 =20 +#define K3_UDMA_MAX_RFLOWS 1024 +#define K3_UDMA_DEFAULT_RING_SIZE 16 + +/* How SRC/DST tag should be updated by UDMA in the descriptor's Word 3 */ +#define UDMA_RFLOW_SRCTAG_NONE 0 +#define UDMA_RFLOW_SRCTAG_CFG_TAG 1 +#define UDMA_RFLOW_SRCTAG_FLOW_ID 2 +#define UDMA_RFLOW_SRCTAG_SRC_TAG 4 + +#define UDMA_RFLOW_DSTTAG_NONE 0 +#define UDMA_RFLOW_DSTTAG_CFG_TAG 1 +#define UDMA_RFLOW_DSTTAG_FLOW_ID 2 +#define UDMA_RFLOW_DSTTAG_DST_TAG_LO 4 +#define UDMA_RFLOW_DSTTAG_DST_TAG_HI 5 + +#define UDMA_FLAG_PDMA_ACC32 BIT(0) +#define UDMA_FLAG_PDMA_BURST BIT(1) +#define UDMA_FLAG_TDTYPE BIT(2) +#define UDMA_FLAG_BURST_SIZE BIT(3) +#define UDMA_FLAGS_J7_CLASS (UDMA_FLAG_PDMA_ACC32 | \ + UDMA_FLAG_PDMA_BURST | \ + UDMA_FLAG_TDTYPE | \ + UDMA_FLAG_BURST_SIZE) + +#define TI_UDMAC_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) + +/* TI_SCI Params */ +#define TISCI_BCDMA_BCHAN_VALID_PARAMS ( \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID) + +#define TISCI_BCDMA_TCHAN_VALID_PARAMS ( \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID) + +#define TISCI_BCDMA_RCHAN_VALID_PARAMS ( \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID) + +#define TISCI_UDMA_TCHAN_VALID_PARAMS ( \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID) + +#define TISCI_UDMA_RCHAN_VALID_PARAMS ( \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID) + struct udma_dev; struct udma_tchan; struct udma_rchan; --=20 2.54.0 From nobody Tue Sep 29 08:26:17 2026 Received: from mx0b-0002e601.pphosted.com (mx0b-0002e601.pphosted.com [148.163.154.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED8A31A6823; Mon, 28 Sep 2026 02:58:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.154.28 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564320; cv=fail; b=R/c33XSvi/lp345vSR0Tvo5Q9mKroo373XN/nwA+PiOsS9ck5ul9g/pZLm5cXiI1eYvvrfdYLftXEmnP5TF5SlSskrQb9c+XG53Sde4DA4IlznUW8OR/bgiGMxixnJhTNbVz1PnwiNZXqd29eXaL67DD0Oc9+o0o0V75c2AnEBA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564320; c=relaxed/simple; bh=esamlki0UYmjV9wiiAEwdi6WfqFJ5zWWdkJtfFlvfMQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Fq6f5RZ0h2EtYYgbr2oFlibIWB+tQ2HaN+dsZ62CRF7m7JKoD72TZJnBVdwPlA0rUI+OeIMisCwKkm7a4AnEBRBbevCrw/XpF9qD3UwmLPTEAgrD8fafBxRbQBPqLoDOqFTUbOFBQn++aMQzCIC50Zj3R1kk8k51nHIDKxM0Qxo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=qck3/H+G; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=uTr7Z+08; arc=fail smtp.client-ip=148.163.154.28 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="qck3/H+G"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="uTr7Z+08" Received: from pps.filterd (m0374956.ppops.net [127.0.0.1]) by mx0b-0002e601.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68RKA6tp2283027; Sun, 27 Sep 2026 21:58:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=Do6VpRERv3DJbrCpEoWH/pWMVQkTxe4yStDn/yrac /M=; b=qck3/H+G6rGHl/3w9Q8Y+CL2XlGPleYkclnsRD+ghNNpojUA9bKhU3h5B Hus09KF3cAhCC4v3GW5nOWMdFKTe6luwqsyKiv6R5UyC63kmBnPTLZowdvTCfZqs X3xCGyXUI8v+OfZ+WTufjigzsbIEc5caEuy8JxhKuNXqviDMv5e8mIeAF/aLRbaU YUT8ajfcvQ41OQLrD/fkfgFcxz+zSCfo58TVBqcVIVCoS16QnZisZuywhPrFuoNq Q9eZYzjXWVA6ofXffKm9EXOY5GYofsNlbd3Lx9VtNHSWIJX6sZVV1grwhdvrJl9T fweSQbjbTrrUGWmjdY8seHxS+9tug== Received: from ch1pr05cu001.outbound.protection.outlook.com (mail-northcentralusazon11010018.outbound.protection.outlook.com [52.101.193.18]) by mx0b-0002e601.pphosted.com (PPS) with ESMTPS id 4gxw6nufvf-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Sun, 27 Sep 2026 21:58:27 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=a0WJTRJo3n1GkuOZ76+LG34M5/Sy9XOBztad7n+NQm2mlqH98/udy5dfSWRVcZEwVhwkWIYnFIKz2jdmqJ1Nle3rlZqNEptRikwXDVBCBcldYPvBXUbNPbTk/kiF5iXnBPSsoh8NRWzePumF6qLmxjrb6+HgoHBr+LHO4lq48eG7eG+A5oEDZqosuEtiF9Ej5iJLLBl3hUerXs1v4aBaLFSP/wOzX7epG1OH+Vcfe2SyP4TPwriSm2NACOCG/wSSJuXNB5+ncejC3WOvbInOddP8jIB7i+YpPR24JuuHOg/1stpwI/Q6ulh0Q5Z0J1+nHUDFU3ibUyqnPB+3p/77rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Do6VpRERv3DJbrCpEoWH/pWMVQkTxe4yStDn/yrac/M=; b=UaLIWJuP4N0FRcu2ebROF2O23oAQwjj8XFhfgY88FitWSxxq0HHq7KC9O5nbs175WWejyMcjbQhwXJMrhuTMxBuUgt1vNK4zlR5Xq2ECxzoAuY4i20AkbbAk8q8e/jayLfN9WwLfe0TwwAnrjKky5TYrS2zXqfh5uGs5JZiWfI7SD3ewtJH0d1jbhttK7u8Bwb0tjwDibdIcviAN/bd47Z+aR0oLdHLYA/nVPtmBkmOM3nDsDCiazHDfApbo/ML4rRowifPTu3QVmfAJPcOUmAgjsqKNXkiyjxEbRgjhXfPkUTYEzT3bOrP09q9ykJ4MRw7tprjcjIbWVuBY2PZH8Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.23.195) smtp.rcpttodomain=nxp.com smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Do6VpRERv3DJbrCpEoWH/pWMVQkTxe4yStDn/yrac/M=; b=uTr7Z+08qHMFS3ZqwsiRIhgADYA3X25wr5SQQUlvqr4hHANfKC3diS0TGvi2ui5TrNzCcvLmhsawP/lsBcDe7OnHZryzVEm4oLaIzMbUEVMduu7Qd2Jh6l9dEsvgzb0anGT/0Uyd/Z6J1TPJWHCpGJwsZeivoZMFYHzRbQ4m404= Received: from SJ0PR13CA0029.namprd13.prod.outlook.com (2603:10b6:a03:2c0::34) by CH3PR10MB7744.namprd10.prod.outlook.com (2603:10b6:610:1ba::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.451.19; Mon, 28 Sep 2026 02:58:24 +0000 Received: from SJ5PEPF000001EB.namprd05.prod.outlook.com (2603:10b6:a03:2c0:cafe::d) by SJ0PR13CA0029.outlook.office365.com (2603:10b6:a03:2c0::34) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.472.11 via Frontend Transport; Mon, 28 Sep 2026 02:58:24 +0000 X-MS-Exchange-Authentication-Results: mx.microsoft.com 1; spf=pass (sender IP is 198.47.23.195) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.23.195 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.23.195; helo=lewvzet201.ext.ti.com; pr=C Received: from lewvzet201.ext.ti.com (198.47.23.195) by SJ5PEPF000001EB.mail.protection.outlook.com (10.167.242.199) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Mon, 28 Sep 2026 02:58:24 +0000 Received: from DLEE201.ent.ti.com (157.170.170.76) by lewvzet201.ext.ti.com (10.4.14.104) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:11 -0500 Received: from DLEE205.ent.ti.com (157.170.170.85) by DLEE201.ent.ti.com (157.170.170.76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:11 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE205.ent.ti.com (157.170.170.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45 via Frontend Transport; Sun, 27 Sep 2026 21:58:11 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [10.24.51.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 68S2vqqA2256662; Sun, 27 Sep 2026 21:58:07 -0500 From: Sai Sree Kartheek Adivi To: , , , , , , , , , , , , , CC: , Subject: [PATCH v10 03/19] dmaengine: ti: k3-udma: move structs and enums to header file Date: Mon, 28 Sep 2026 08:26:09 +0530 Message-ID: <20260928025749.1055383-4-s-adivi@ti.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260928025749.1055383-1-s-adivi@ti.com> References: <20260928025749.1055383-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001EB:EE_|CH3PR10MB7744:EE_ X-MS-Office365-Filtering-Correlation-Id: 8960f510-1c1e-4511-bdc7-08df1d0c5cc1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|1800799024|23010399003|7416014|376014|56012099006|10067099003|3023799007|6133799003|22082099003|18002099003|921020; X-Microsoft-Antispam-Message-Info: mpIIyrew0txkSNI646qYAANR/euNDfF+H6ofrt+PqYCDQm63keDmhWTTwrRP4nqMMvv974f4I1M+zZpg9wR0+Rz8uk9lvVS22+gkbQRq/JrZwNwgaaOUN3J7ygTBqcWsxMsEpBylT88KziufaLpRK8/eZqQC6MYjR9NlxzO6uMMtS8yKxoYyU4nNuE1y5lV/goGSZVDH0QK4dhFqxd+TYJk7KjhTupVlpL9skf+R+LZuD2yKC+oRNUj0QgtYoTwJZ8vKaGrHgzSEiIK0Zu8Wuktb+d2qcukHNUb/4QkcHfEkuMfmrzrYIkAScYXsxXAdl2aMimpXPK3C/nblDTiBYBjlw20CU7zzXr/k67LmJVCBG7mGYznxQKculEIMIOqJnD0uhv3R0LCbGkyHJnA/vzCcBqfoXmkWLQhkm0RcKoP3wQf2/PCbz9s49+MROQ5p7pewVPWBlZeD/qkZBBMBf/GscInJrtXXdRUSiJE9a0p4PKfXWLfTgDD3bZXmwcPc+FfKTX6EOFEH0chddE8T/nrRnS5ds2/4HpKjb1CxWCTNalcztul8dL3s/5thJgut3TGgqs0WhEEvgX12kpkO6fUiF8Dxjgly7gDltSbWEtOHZkrpy1sFmL28sTzF9j8U3IgUum0L9zZQcglzh+yvYQOB9NyPccu+U5LZPAinv06PLA+x1dkOOoDnAKx5CTO0JPwRj+2cJn1pQmLpZmphs7KBlz+A6rtIoDLg0OfX7Zy4zKT5/4//Y9Sai65U5qFy X-Forefront-Antispam-Report: CIP:198.47.23.195;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:lewvzet201.ext.ti.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(1800799024)(23010399003)(7416014)(376014)(56012099006)(10067099003)(3023799007)(6133799003)(22082099003)(18002099003)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: E/fTG07Ta3sJ1IWmOIerDrf/qS3H+qeUyrh3Z62tKS20t/onUIAkXKHBi1BUsbtwPZAtMbp0BHO8jDsmcJzXOg65+mF9W6brbv6QP6gKkRITbv42pWFvWBkxC5OtDGxKt/9S3zYF5Q8Iydo20mnkNnAXw1pAvGSnQ1Tjdid/GKO65fLyaGjum5vVlFZTGd8ODu1LEuey1RGUo4lk0K/EtYNqFXa7RCdQoACYEgN77ctwHrTXFU+1Qgy81oZR5InkWwX8M+FNTSv+Mkg5QAOAJTgTtHUZ35VqsKF+vcx3R+8NeMUESMahMyzjPmj6csz+FufyUNfjZUqCQpLt5p8Mk2fBToyIDgObp0Hnw4XkzeykS9fKjM0z/KJy9Smkx89g0ChTy/LvD3OcjN9sAlr8UHNg0n6q5bJJYXJoQuUcHSH8882lHC9v2SAodIXuFRdV X-Exchange-RoutingPolicyChecked: Z/nfFzfpVvCB+G93JRG+0uZ08dJ/b1vgJnTxntZxYkHkZvA+gmd/6uKePVWokcABiteh7jeH1LzolISDOwJ+GRrCLU8iMu3WeHoe+vLz599IeNO42ARvGMXwtQQw7+ejHaAqYS+nwYza/ST8F5UggTS/8f2Twh5BZCGEkC1Ac0RsXpgQjHZHpKSLGkAmCvrpw0mRCgpcdBYg0zLGTteFrtx/pT6ERDtnYmnFfSnFacirFA7r1gYDSDETsirk1XkQL3GLOqh8q/o3/1u2jPl90pBnKlu03cRAWUSjuN4M8rEYXY/gGdGjLy36KV7U1Bdc/o/+pYK9JiQFPrtZeoyQHw== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 02:58:24.1525 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8960f510-1c1e-4511-bdc7-08df1d0c5cc1 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001EB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR10MB7744 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX+bLtXlq+nhlm 6FSpedz7+tt6z9+zgQPRkaYa7RMpcraaiHbyVOT2dJHucDLVuLgPmJyW25qNwe4z/KfM3PRtP/z ftHdmJOMnrwMUH1UT6Ybh4bx44TznOs= X-Authority-Analysis: v=2.4 cv=dbkVTnXe c=1 sm=1 tr=0 ts=6ab9d7d3 cx=c_pps a=A0DLv2vQdyrz0cYTEbm3ig==:117 a=f+v6EHfkeJbVwR46tk4DMg==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=VdqzKS8jKosA:10 a=s63m1ICgrNkA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=jwouBfj2j3NM8CExmVVE:22 a=sozttTNsAAAA:8 a=8AirrxEcAAAA:8 a=1JpllqVW-1LRWXCuGuAA:9 a=ST-jHhOKWsTCqRlWije3:22 X-Proofpoint-ORIG-GUID: NTuSQY56sbIqs-O903dsuQHcnpWxmjlp X-Proofpoint-GUID: NTuSQY56sbIqs-O903dsuQHcnpWxmjlp X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX0KJNqXj8qQv/ ZreUV1RwnH8ci7MREAUMkMG3TWknsn8tppPvpRIUJtDcBfOI37r0JhQTiLn77VLjyqOLG+QwMRt ygWL7By3D74gyboE+KB/zLdXHPQzbPJWS+i4r5nJDwza6wn0UNalkhT77/HDQkN5X6M9cITlSfy ec6vWrx+G8/UqnNQl6cCgE4HauAyN9WvzmsSsEi59BgK2LK9zGJHN7LRniathIQgLssla6ipjz3 mfJIlu/SkHUN/fAoA39YfjpUK82u2GifNPOC5ezb/qYvX7EW7Ne1oHq+R7dC4p6zNXH94pqE+B4 soWats/HDaMPXa+xwWBUCnWd22IKxiwGbuJ1DQoYQaVH9pSCNDC5/wORqEzv2+7fnVocF2fIrzQ 7Heni8mzSpqZUJ4Xv5z5XewBsV0sljqRO8tnGc5wSYY1GUSBwc5HEI54sncr/dicAKaatyf39I3 Q+n7MnqPRNdUsEyWzMg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 impostorscore=0 adultscore=0 bulkscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280011 Content-Type: text/plain; charset="utf-8" Move struct and enum definitions in k3-udma.c to k3-udma.h header file for better separation and reuse. Signed-off-by: Sai Sree Kartheek Adivi Reviewed-by: Frank Li --- drivers/dma/ti/k3-udma.c | 259 +------------------------------------- drivers/dma/ti/k3-udma.h | 265 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 266 insertions(+), 258 deletions(-) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index a1b99097a94ad..d7c153c5321ea 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -24,8 +24,8 @@ #include #include #include -#include #include +#include #include #include =20 @@ -33,28 +33,6 @@ #include "k3-udma.h" #include "k3-psil-priv.h" =20 -struct udma_static_tr { - u8 elsize; /* RPSTR0 */ - u16 elcnt; /* RPSTR0 */ - u16 bstcnt; /* RPSTR1 */ -}; - -struct udma_chan; - -enum k3_dma_type { - DMA_TYPE_UDMA =3D 0, - DMA_TYPE_BCDMA, - DMA_TYPE_PKTDMA, -}; - -enum udma_mmr { - MMR_GCFG =3D 0, - MMR_BCHANRT, - MMR_RCHANRT, - MMR_TCHANRT, - MMR_LAST, -}; - static const char * const mmr_names[] =3D { [MMR_GCFG] =3D "gcfg", [MMR_BCHANRT] =3D "bchanrt", @@ -62,234 +40,6 @@ static const char * const mmr_names[] =3D { [MMR_TCHANRT] =3D "tchanrt", }; =20 -struct udma_tchan { - void __iomem *reg_rt; - - int id; - struct k3_ring *t_ring; /* Transmit ring */ - struct k3_ring *tc_ring; /* Transmit Completion ring */ - int tflow_id; /* applicable only for PKTDMA */ - -}; - -#define udma_bchan udma_tchan - -struct udma_rflow { - int id; - struct k3_ring *fd_ring; /* Free Descriptor ring */ - struct k3_ring *r_ring; /* Receive ring */ -}; - -struct udma_rchan { - void __iomem *reg_rt; - - int id; -}; - -struct udma_oes_offsets { - /* K3 UDMA Output Event Offset */ - u32 udma_rchan; - - /* BCDMA Output Event Offsets */ - u32 bcdma_bchan_data; - u32 bcdma_bchan_ring; - u32 bcdma_tchan_data; - u32 bcdma_tchan_ring; - u32 bcdma_rchan_data; - u32 bcdma_rchan_ring; - - /* PKTDMA Output Event Offsets */ - u32 pktdma_tchan_flow; - u32 pktdma_rchan_flow; -}; - -struct udma_match_data { - enum k3_dma_type type; - u32 psil_base; - bool enable_memcpy_support; - u32 flags; - u32 statictr_z_mask; - u8 burst_size[3]; - struct udma_soc_data *soc_data; -}; - -struct udma_soc_data { - struct udma_oes_offsets oes; - u32 bcdma_trigger_event_offset; -}; - -struct udma_hwdesc { - size_t cppi5_desc_size; - void *cppi5_desc_vaddr; - dma_addr_t cppi5_desc_paddr; - - /* TR descriptor internal pointers */ - void *tr_req_base; - struct cppi5_tr_resp_t *tr_resp_base; -}; - -struct udma_rx_flush { - struct udma_hwdesc hwdescs[2]; - - size_t buffer_size; - void *buffer_vaddr; - dma_addr_t buffer_paddr; -}; - -struct udma_tpl { - u8 levels; - u32 start_idx[3]; -}; - -struct udma_dev { - struct dma_device ddev; - struct device *dev; - void __iomem *mmrs[MMR_LAST]; - const struct udma_match_data *match_data; - const struct udma_soc_data *soc_data; - - struct udma_tpl bchan_tpl; - struct udma_tpl tchan_tpl; - struct udma_tpl rchan_tpl; - - size_t desc_align; /* alignment to use for descriptors */ - - struct udma_tisci_rm tisci_rm; - - struct k3_ringacc *ringacc; - - struct work_struct purge_work; - struct list_head desc_to_purge; - spinlock_t lock; - - struct udma_rx_flush rx_flush; - - int bchan_cnt; - int tchan_cnt; - int echan_cnt; - int rchan_cnt; - int rflow_cnt; - int tflow_cnt; - unsigned long *bchan_map; - unsigned long *tchan_map; - unsigned long *rchan_map; - unsigned long *rflow_gp_map; - unsigned long *rflow_gp_map_allocated; - unsigned long *rflow_in_use; - unsigned long *tflow_map; - - struct udma_bchan *bchans; - struct udma_tchan *tchans; - struct udma_rchan *rchans; - struct udma_rflow *rflows; - - struct udma_chan *channels; - u32 psil_base; - u32 atype; - u32 asel; -}; - -struct udma_desc { - struct virt_dma_desc vd; - - bool terminated; - - enum dma_transfer_direction dir; - - struct udma_static_tr static_tr; - u32 residue; - - unsigned int sglen; - unsigned int desc_idx; /* Only used for cyclic in packet mode */ - unsigned int tr_idx; - - u32 metadata_size; - void *metadata; /* pointer to provided metadata buffer (EPIP, PSdata) */ - - unsigned int hwdesc_count; - struct udma_hwdesc hwdesc[]; -}; - -enum udma_chan_state { - UDMA_CHAN_IS_IDLE =3D 0, /* not active, no teardown is in progress */ - UDMA_CHAN_IS_ACTIVE, /* Normal operation */ - UDMA_CHAN_IS_TERMINATING, /* channel is being terminated */ -}; - -struct udma_tx_drain { - struct delayed_work work; - ktime_t tstamp; - u32 residue; -}; - -struct udma_chan_config { - bool pkt_mode; /* TR or packet */ - bool needs_epib; /* EPIB is needed for the communication or not */ - u32 psd_size; /* size of Protocol Specific Data */ - u32 metadata_size; /* (needs_epib ? 16:0) + psd_size */ - u32 hdesc_size; /* Size of a packet descriptor in packet mode */ - bool notdpkt; /* Suppress sending TDC packet */ - int remote_thread_id; - u32 atype; - u32 asel; - u32 src_thread; - u32 dst_thread; - enum psil_endpoint_type ep_type; - bool enable_acc32; - bool enable_burst; - enum udma_tp_level channel_tpl; /* Channel Throughput Level */ - - u32 tr_trigger_type; - unsigned long tx_flags; - - /* PKDMA mapped channel */ - int mapped_channel_id; - /* PKTDMA default tflow or rflow for mapped channel */ - int default_flow_id; - - enum dma_transfer_direction dir; -}; - -struct udma_chan { - struct virt_dma_chan vc; - struct dma_slave_config cfg; - struct udma_dev *ud; - struct device *dma_dev; - struct udma_desc *desc; - struct udma_desc *terminated_desc; - struct udma_static_tr static_tr; - char *name; - - struct udma_bchan *bchan; - struct udma_tchan *tchan; - struct udma_rchan *rchan; - struct udma_rflow *rflow; - - bool psil_paired; - - int irq_num_ring; - int irq_num_udma; - - bool cyclic; - bool paused; - - enum udma_chan_state state; - struct completion teardown_completed; - - struct udma_tx_drain tx_drain; - - /* Channel configuration parameters */ - struct udma_chan_config config; - /* Channel configuration parameters (backup) */ - struct udma_chan_config backup_config; - - /* dmapool for packet mode descriptors */ - bool use_dma_pool; - struct dma_pool *hdesc_pool; - - u32 id; -}; - static inline struct udma_dev *to_udma_dev(struct dma_device *d) { return container_of(d, struct udma_dev, ddev); @@ -4073,13 +3823,6 @@ static struct platform_driver udma_driver; static struct platform_driver bcdma_driver; static struct platform_driver pktdma_driver; =20 -struct udma_filter_param { - int remote_thread_id; - u32 atype; - u32 asel; - u32 tr_trigger_type; -}; - static bool udma_dma_filter_fn(struct dma_chan *chan, void *param) { struct udma_chan_config *ucc; diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h index 750720cd06911..11d08adb0d69f 100644 --- a/drivers/dma/ti/k3-udma.h +++ b/drivers/dma/ti/k3-udma.h @@ -6,7 +6,16 @@ #ifndef K3_UDMA_H_ #define K3_UDMA_H_ =20 +#include #include +#include +#include +#include +#include +#include + +#include "../virt-dma.h" +#include "k3-psil-priv.h" =20 /* Global registers */ #define UDMA_REV_REG 0x0 @@ -164,6 +173,7 @@ struct udma_dev; struct udma_tchan; struct udma_rchan; struct udma_rflow; +struct udma_chan; =20 enum udma_rm_range { RM_RANGE_BCHAN =3D 0, @@ -186,6 +196,261 @@ struct udma_tisci_rm { struct ti_sci_resource *rm_ranges[RM_RANGE_LAST]; }; =20 +struct udma_static_tr { + u8 elsize; /* RPSTR0 */ + u16 elcnt; /* RPSTR0 */ + u16 bstcnt; /* RPSTR1 */ +}; + +enum k3_dma_type { + DMA_TYPE_UDMA =3D 0, + DMA_TYPE_BCDMA, + DMA_TYPE_PKTDMA, +}; + +enum udma_mmr { + MMR_GCFG =3D 0, + MMR_BCHANRT, + MMR_RCHANRT, + MMR_TCHANRT, + MMR_LAST, +}; + +struct udma_filter_param { + int remote_thread_id; + u32 atype; + u32 asel; + u32 tr_trigger_type; +}; + +struct udma_tchan { + void __iomem *reg_rt; + + int id; + struct k3_ring *t_ring; /* Transmit ring */ + struct k3_ring *tc_ring; /* Transmit Completion ring */ + int tflow_id; /* applicable only for PKTDMA */ + +}; + +#define udma_bchan udma_tchan + +struct udma_rflow { + int id; + struct k3_ring *fd_ring; /* Free Descriptor ring */ + struct k3_ring *r_ring; /* Receive ring */ +}; + +struct udma_rchan { + void __iomem *reg_rt; + + int id; +}; + +struct udma_oes_offsets { + /* K3 UDMA Output Event Offset */ + u32 udma_rchan; + + /* BCDMA Output Event Offsets */ + u32 bcdma_bchan_data; + u32 bcdma_bchan_ring; + u32 bcdma_tchan_data; + u32 bcdma_tchan_ring; + u32 bcdma_rchan_data; + u32 bcdma_rchan_ring; + + /* PKTDMA Output Event Offsets */ + u32 pktdma_tchan_flow; + u32 pktdma_rchan_flow; +}; + +struct udma_match_data { + enum k3_dma_type type; + u32 psil_base; + bool enable_memcpy_support; + u32 flags; + u32 statictr_z_mask; + u8 burst_size[3]; + struct udma_soc_data *soc_data; +}; + +struct udma_soc_data { + struct udma_oes_offsets oes; + u32 bcdma_trigger_event_offset; +}; + +struct udma_hwdesc { + size_t cppi5_desc_size; + void *cppi5_desc_vaddr; + dma_addr_t cppi5_desc_paddr; + + /* TR descriptor internal pointers */ + void *tr_req_base; + struct cppi5_tr_resp_t *tr_resp_base; +}; + +struct udma_rx_flush { + struct udma_hwdesc hwdescs[2]; + + size_t buffer_size; + void *buffer_vaddr; + dma_addr_t buffer_paddr; +}; + +struct udma_tpl { + u8 levels; + u32 start_idx[3]; +}; + +struct udma_dev { + struct dma_device ddev; + struct device *dev; + void __iomem *mmrs[MMR_LAST]; + const struct udma_match_data *match_data; + const struct udma_soc_data *soc_data; + + struct udma_tpl bchan_tpl; + struct udma_tpl tchan_tpl; + struct udma_tpl rchan_tpl; + + size_t desc_align; /* alignment to use for descriptors */ + + struct udma_tisci_rm tisci_rm; + + struct k3_ringacc *ringacc; + + struct work_struct purge_work; + struct list_head desc_to_purge; + spinlock_t lock; + + struct udma_rx_flush rx_flush; + + int bchan_cnt; + int tchan_cnt; + int echan_cnt; + int rchan_cnt; + int rflow_cnt; + int tflow_cnt; + unsigned long *bchan_map; + unsigned long *tchan_map; + unsigned long *rchan_map; + unsigned long *rflow_gp_map; + unsigned long *rflow_gp_map_allocated; + unsigned long *rflow_in_use; + unsigned long *tflow_map; + + struct udma_bchan *bchans; + struct udma_tchan *tchans; + struct udma_rchan *rchans; + struct udma_rflow *rflows; + + struct udma_chan *channels; + u32 psil_base; + u32 atype; + u32 asel; +}; + +struct udma_desc { + struct virt_dma_desc vd; + + bool terminated; + + enum dma_transfer_direction dir; + + struct udma_static_tr static_tr; + u32 residue; + + unsigned int sglen; + unsigned int desc_idx; /* Only used for cyclic in packet mode */ + unsigned int tr_idx; + + u32 metadata_size; + void *metadata; /* pointer to provided metadata buffer (EPIP, PSdata) */ + + unsigned int hwdesc_count; + struct udma_hwdesc hwdesc[]; +}; + +enum udma_chan_state { + UDMA_CHAN_IS_IDLE =3D 0, /* not active, no teardown is in progress */ + UDMA_CHAN_IS_ACTIVE, /* Normal operation */ + UDMA_CHAN_IS_TERMINATING, /* channel is being terminated */ +}; + +struct udma_tx_drain { + struct delayed_work work; + ktime_t tstamp; + u32 residue; +}; + +struct udma_chan_config { + bool pkt_mode; /* TR or packet */ + bool needs_epib; /* EPIB is needed for the communication or not */ + u32 psd_size; /* size of Protocol Specific Data */ + u32 metadata_size; /* (needs_epib ? 16:0) + psd_size */ + u32 hdesc_size; /* Size of a packet descriptor in packet mode */ + bool notdpkt; /* Suppress sending TDC packet */ + int remote_thread_id; + u32 atype; + u32 asel; + u32 src_thread; + u32 dst_thread; + enum psil_endpoint_type ep_type; + bool enable_acc32; + bool enable_burst; + enum udma_tp_level channel_tpl; /* Channel Throughput Level */ + + u32 tr_trigger_type; + unsigned long tx_flags; + + /* PKDMA mapped channel */ + int mapped_channel_id; + /* PKTDMA default tflow or rflow for mapped channel */ + int default_flow_id; + + enum dma_transfer_direction dir; +}; + +struct udma_chan { + struct virt_dma_chan vc; + struct dma_slave_config cfg; + struct udma_dev *ud; + struct device *dma_dev; + struct udma_desc *desc; + struct udma_desc *terminated_desc; + struct udma_static_tr static_tr; + char *name; + + struct udma_bchan *bchan; + struct udma_tchan *tchan; + struct udma_rchan *rchan; + struct udma_rflow *rflow; + + bool psil_paired; + + int irq_num_ring; + int irq_num_udma; + + bool cyclic; + bool paused; + + enum udma_chan_state state; + struct completion teardown_completed; + + struct udma_tx_drain tx_drain; + + /* Channel configuration parameters */ + struct udma_chan_config config; + /* Channel configuration parameters (backup) */ + struct udma_chan_config backup_config; + + /* dmapool for packet mode descriptors */ + bool use_dma_pool; + struct dma_pool *hdesc_pool; + + u32 id; +}; + /* Direct access to UDMA low lever resources for the glue layer */ int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thr= ead); int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread, --=20 2.54.0 From nobody Tue Sep 29 08:26:17 2026 Received: from mx0a-0002e601.pphosted.com (mx0a-0002e601.pphosted.com [148.163.150.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04D6636DA1A; Mon, 28 Sep 2026 02:58:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.150.75 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564335; cv=fail; b=DLOTSEILCoplPGWvv+NWiydLEAXBGQfxkJsd6+Kd/2E0BrBJRwZw3C8Ntyb6686uSRi0Oou+v20t5bD6llkmtKRjWxx8VfjCjaDWr9aUyC2BIEUBSaJJjgevaH1McQ3BLC5v1f8Nui7BzbrtV7GtQ9dHf6gR+ljRqf8V/U1dKHw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564335; c=relaxed/simple; bh=Eme2xSy2VfiQ7P4WARJMbEdhgm1AaojTY0SLTbQoBzw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QlXLpJEwNoPAz93VjlQiMkWEV1mMd4J8sTC98P0ewJpo+b4STIMRIRCV3Jh5aa9rs/ZKzYCajucnN3dbMRI+coOb1ABl7tMdSGt6KQBaA7qEFuffV8ixIFNF64bg6a3NIBKDV+OMS57IvkolMxCCTI+76xBpIzl0sinbk5x7KCg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=Ubtn3YvS; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=uJ0vNmSl; arc=fail smtp.client-ip=148.163.150.75 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="Ubtn3YvS"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="uJ0vNmSl" Received: from pps.filterd (m0384305.ppops.net [127.0.0.1]) by m0384305.ppops.net (8.18.1.11/8.18.1.11) with ESMTP id 68S0RoKm3706315; Sun, 27 Sep 2026 21:58:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=ufS10IuV4rNPlv4A6/SND55bzkb9Kt7l4TDzuRCVL A4=; b=Ubtn3YvSJNHooT1huh8xSqH9y/kZ7SnPpEjwGhQ/+ssFhCT43CBEoZ60E IxaVZiW3XPh7LqlOYvcKFwTldJeJY2+IzTQ/pCKnbUTlpwaNFcNHIxT+/la0L9Hv fBBHhQET5vsPcfDxllseqpsFsi6uvknry9E8FveLCTa7QwfggQJ9bu4FS8k1HwFu xoUgcBMxsL+lOgbNevOcBt83T9jXkVKNhNpGRMdpbd3dcrY4cT5dykOGQHlBjdnR vSxzyOlVS4HW00S2QX+F2eklo2FGREpTlPVfRedNh3z1ANA2FEWfWKTT0x0GhnxN cq+fx0rdjeuXPzNXedI4U6QaeZu5A== Received: from sn4pr2101cu001.outbound.protection.outlook.com (mail-southcentralusazon11012015.outbound.protection.outlook.com [40.93.195.15]) by m0384305.ppops.net (PPS) with ESMTPS id 4gy00nb1q8-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Sun, 27 Sep 2026 21:58:47 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ZFjnVJqcAIUQY+0WgNI6DNneBwzRBJoViOo5ZVrfwmsqVZQN4C5AkIbE2ueDSHgeWZlJZzwTJt/5/HTQ5RzeY1iYFf4xmYNv0WZYD1QOkporUPg1WRZMQWoTgCgMAjxlllmsoF0j0U+gsoRXgOvRtGXVz+t1pWClthjDkzfHE9LQQVz2up4uxj1ajIkIMASlOpr3bW5NK/Ujo/nRhw1tQLW3XtTDQ2KTZT9JxPoqgeWdMKV+6OwK+gQ1scsUD/wrKQxh94cfFLGKFrWAPLD7KQeGHbQTzESLQFc+8GQQZj3Iro3WQhZIPcOo7F388Oj/SMgWENam2iQouSGCyGre9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ufS10IuV4rNPlv4A6/SND55bzkb9Kt7l4TDzuRCVLA4=; b=LAK4OOGZiV60j8tJdpJGmELAsoNK9fy8rfAS4L2vUNn4ppT9K0HwyZgWCrBlEZs7TUZHgEn4nLsU0jp3y6evcU6ry0oT4qqWueGil3S1oJW9w0RtyMgS/fa6WPvqqbp9lrFlpTHsOoym3a9qFJqX9o/bjBUI9l1BvnS44Jc/eCBCGeH22gHzHeEhh1lc4tnSuIx64y5RNJUbnmK8lQcvtbBkOdMFUa8m7GtRR15ymtvKCr4NCBsV/Chk2S7BpbQkRWUfw6/a9LcplOUy5OhGDJ2qonBdL/56xxPPs+4DySsTp4R/RpGnsu3uSCKS0hspwAW6uuXMX1wzzs6Aat0LWQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.21.194) smtp.rcpttodomain=nxp.com smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ufS10IuV4rNPlv4A6/SND55bzkb9Kt7l4TDzuRCVLA4=; b=uJ0vNmSlmZZOt4r4QRn5d6zoVZ6KM4mUkfU9NcT8LoeB4b8p6JdjBECMAQWTejKTH2ubyI1RJJmYAZVIru60VdSqZy3F4QzsvsF6KwxrbkeVBzcb2TWYKgijt33fBxHLvmnzjnjianGhGS2JMFeHqj/Y8JwBTLHQAYZzu5KaScg= Received: from CH0PR03CA0206.namprd03.prod.outlook.com (2603:10b6:610:e4::31) by CH2PR10MB4230.namprd10.prod.outlook.com (2603:10b6:610:a5::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.451.21; Mon, 28 Sep 2026 02:58:44 +0000 Received: from DS2PEPF000061C1.namprd02.prod.outlook.com (2603:10b6:610:e4:cafe::4f) by CH0PR03CA0206.outlook.office365.com (2603:10b6:610:e4::31) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.451.24 via Frontend Transport; Mon, 28 Sep 2026 02:58:43 +0000 X-MS-Exchange-Authentication-Results: mx.microsoft.com 1; spf=pass (sender IP is 198.47.21.194) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.21.194 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.21.194; helo=flwvzet200.ext.ti.com; pr=C Received: from flwvzet200.ext.ti.com (198.47.21.194) by DS2PEPF000061C1.mail.protection.outlook.com (10.167.23.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Mon, 28 Sep 2026 02:58:43 +0000 Received: from DFLE202.ent.ti.com (10.64.6.60) by flwvzet200.ext.ti.com (10.248.192.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:16 -0500 Received: from DFLE200.ent.ti.com (10.64.6.58) by DFLE202.ent.ti.com (10.64.6.60) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:16 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE200.ent.ti.com (10.64.6.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45 via Frontend Transport; Sun, 27 Sep 2026 21:58:16 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [10.24.51.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 68S2vqqB2256662; Sun, 27 Sep 2026 21:58:12 -0500 From: Sai Sree Kartheek Adivi To: , , , , , , , , , , , , , CC: , Subject: [PATCH v10 04/19] dmaengine: ti: k3-udma: move static inline helper functions to header file Date: Mon, 28 Sep 2026 08:26:10 +0530 Message-ID: <20260928025749.1055383-5-s-adivi@ti.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260928025749.1055383-1-s-adivi@ti.com> References: <20260928025749.1055383-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF000061C1:EE_|CH2PR10MB4230:EE_ X-MS-Office365-Filtering-Correlation-Id: 478422c5-b489-47ac-2e75-08df1d0c681f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|82310400026|23010399003|36860700016|921020|6133799003|10067099003|56012099006|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: iej6hfG1bG2GLFotbdaRVcf8DMajUBV6lq6DzjvWvQOYF1Zswi07IvMJF5Cl0tdPDQtjVdPGyTF8VIQtZe4hEc1RCKNqfSIUaeOz6T/9Pu2mUDtvhcWgJQ7znzKFrQuL8hKQs69ymmbUWt5kgMRzdc6Yx1hHIjOE2Y0xzV+KuytdBfdQEbJFDVqDvZogKwbc0r5HVLk3qxZU/NCklBLTkL9Y8Td4YdyxNsF73S0UeraF6pSOqg4khIqLEvRn507XMz/X/8E5AL9HuRoSKHx35pgkhIVuthat8dp5KreKCsDrFq86giJ7rQ83VJLA5qYtOIMfg/bWj5FPeiw1Q028t9CYyxo0GBYtTAC3n00wdcoR0Zu9WwwNN50KAqJ6+9ePxW/wzFo1ecG5pvgkQ8rWc6BlB6ugtykTY5D8RPha3twF1uPvIAuE3tGNtalmYv0Y+PPkgTm5yBxgoNqug/ZKN1LN/mQ6txH1YtgiyreNGXdMATXZQotrExahPQut9eq7tqkIAFKQhKiygM31zoQ0HoWsNNE7douLF7GC9/uNH6DHBfOR18WJbZR055HUlSXfQN28dEpLltEa46uhCNpwL8jWQaDC9mFY6kiJYgVrP1c2G8E6yaMAG7bXAnip5edmFq8o7/ku3LpKvzEBJVd7Picu0jJctfhJHk56E0Nlaea+0fPKfmKN/GThouZrGq1eQw+5e73bnjJxfBuD1zzfsaCtBotb8J4Kxc0zSWMuQK3Xwugbje9gIblabpnyYDoE X-Forefront-Antispam-Report: CIP:198.47.21.194;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:flwvzet200.ext.ti.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(82310400026)(23010399003)(36860700016)(921020)(6133799003)(10067099003)(56012099006)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: RU1GiAKsIVSKHlGDZRnyurpZZHwnr8vb9nAgpzVtLNRI7qxLivALNc4UAaXpg6KkYFdzgwTBz0hmilFiGnBGXUfxAE4HpY88lagbZaRYVApQ+JBu9DXoj8wbaEpdBxllbePgNUWXOOu3RUNQpQ3pMYA28NbtdVJ19outt8pY1Lbib05SJo/8B5ivGWmXRp8hxP8BbW2bNwxEKaBvhZKxj/SHGKS02+MWlY+5e1YM+Mlw1k16d460A9MoNYbYd3CHlmtIFLxzTZU/nkpKzh765TrECar9T4S5nersTlKug1g8DO3pfsS8P5HVIDyk9ekGbv/3oM+pf2lXqPGnSFHAX9FnIOs4Tz0mnVPS1FYdVwGyZojftxNhAFZi+6fMIUsAjliV3gcXCCO0+NpIjKDh+4mDlpKcU07j8DOoLuiq4SHuATCKjxH44DWuBk0g5LMl X-Exchange-RoutingPolicyChecked: GgDUsI2ATHXkAv8Q9zAIAGUoXpjwVD/Zc1PEG48SdMI6BYUfKnxzeOlmUgtqSijo83yltE0h8ylTjvwcxK4iZBrhOfNAndNopeR9zDTlQWBQHqUsRCQbIDCawCXtF1GKtmYNIvc//su8E7ggC3HuLG2MMEeFVoigPVmidNgu4gBXLYu+ipsY9UrgEX/n2KAPdjJcx2arPRK8m6Ew0DwEExXC1meg+Jf2NBzk9i7iJ9OcnjAbtyJKqcpL1gxtp+KzGFNgsb5umqXXpjqipGY9yXZzOgVjW/wpH18Av3Noh3gYWOqjpThM7XkXjzpzN8VOZPRDYh5zCUO6fD5QuJTFzQ== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 02:58:43.2627 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 478422c5-b489-47ac-2e75-08df1d0c681f X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF000061C1.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR10MB4230 X-Proofpoint-GUID: VnOoTO83XJT08V7jHPFUgSUQo9l87lH5 X-Authority-Analysis: v=2.4 cv=fKysTpae c=1 sm=1 tr=0 ts=6ab9d7e7 cx=c_pps a=OAmo50eV21M7Ophgg7+Z+Q==:117 a=iwqwCZQqcuTv3JOpYdM7/Q==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=VdqzKS8jKosA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=taLDd7a_hP9WKsMzeGRc:22 a=8AirrxEcAAAA:8 a=sozttTNsAAAA:8 a=grpEhN_aSmkWsCgVS3MA:9 a=ST-jHhOKWsTCqRlWije3:22 X-Proofpoint-ORIG-GUID: VnOoTO83XJT08V7jHPFUgSUQo9l87lH5 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX4KNsJ0ZPNG3h RrGUQqMKhu3H/Z/MGAIfw+yWJaiU/TB7pDQcZ0QtrCZkp941yGi6VGH05fYt/gu8ZpqMfVbeJkz lM6sNwbOosbSYRZueArsJVw6mAjH7pM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfXzf0CjbJ9r1wC y58WmZA3ZkzHVcEmRlsMHUnBG6WuBpVaQRUJY1x1uu8dpIX/gM5OBvQ0ScD44dTbk7Hwbk00QdU /0KdaYzzP7WpbGvOHewoEmSHka5Cx8qnWlEFsNJXQM+OPhvQFRRJxLuuWq5/RYvXtZ3wnLF2jOE Me+1Ez39gJ8KnMeMDeMqaT0N/NnKyItLEZAOt1qtvMQBP4vmMUVFYBimzOEJj91RiYHoS6I5x1J g8ow3D4OWEcsA/BDm2FrdO0QF8/Dm7jDs9TbUr8EgfJFoNH8mRGLghdfLY9jkwzyFSZc9YtVUjY X69G39QczBWJ9CncsSrUYINuKLyXWj8ryFQBcpRIVRqoWJ861wezXED8TYnyWjldk+a8h/l/NKo xKww+cPplD1W8O41FlyKTNNJLi3Yy1E/uL7C2vJss/KsWwvWk6TcZ5HCVP9LKZhooFHnqrNB8Cu DpaafUZmcoc0oVFcdfw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 spamscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 adultscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280011 Content-Type: text/plain; charset="utf-8" Move static inline helper functions in k3-udma.c to k3-udma.h header file for better separation and reuse. Reviewed-by: Frank Li Signed-off-by: Sai Sree Kartheek Adivi --- drivers/dma/ti/k3-udma.c | 108 -------------------------------------- drivers/dma/ti/k3-udma.h | 109 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 109 insertions(+), 108 deletions(-) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index d7c153c5321ea..5336ec9fe79ce 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -40,91 +40,6 @@ static const char * const mmr_names[] =3D { [MMR_TCHANRT] =3D "tchanrt", }; =20 -static inline struct udma_dev *to_udma_dev(struct dma_device *d) -{ - return container_of(d, struct udma_dev, ddev); -} - -static inline struct udma_chan *to_udma_chan(struct dma_chan *c) -{ - return container_of(c, struct udma_chan, vc.chan); -} - -static inline struct udma_desc *to_udma_desc(struct dma_async_tx_descripto= r *t) -{ - return container_of(t, struct udma_desc, vd.tx); -} - -/* Generic register access functions */ -static inline u32 udma_read(void __iomem *base, int reg) -{ - return readl(base + reg); -} - -static inline void udma_write(void __iomem *base, int reg, u32 val) -{ - writel(val, base + reg); -} - -static inline void udma_update_bits(void __iomem *base, int reg, - u32 mask, u32 val) -{ - u32 tmp, orig; - - orig =3D readl(base + reg); - tmp =3D orig & ~mask; - tmp |=3D (val & mask); - - if (tmp !=3D orig) - writel(tmp, base + reg); -} - -/* TCHANRT */ -static inline u32 udma_tchanrt_read(struct udma_chan *uc, int reg) -{ - if (!uc->tchan) - return 0; - return udma_read(uc->tchan->reg_rt, reg); -} - -static inline void udma_tchanrt_write(struct udma_chan *uc, int reg, u32 v= al) -{ - if (!uc->tchan) - return; - udma_write(uc->tchan->reg_rt, reg, val); -} - -static inline void udma_tchanrt_update_bits(struct udma_chan *uc, int reg, - u32 mask, u32 val) -{ - if (!uc->tchan) - return; - udma_update_bits(uc->tchan->reg_rt, reg, mask, val); -} - -/* RCHANRT */ -static inline u32 udma_rchanrt_read(struct udma_chan *uc, int reg) -{ - if (!uc->rchan) - return 0; - return udma_read(uc->rchan->reg_rt, reg); -} - -static inline void udma_rchanrt_write(struct udma_chan *uc, int reg, u32 v= al) -{ - if (!uc->rchan) - return; - udma_write(uc->rchan->reg_rt, reg, val); -} - -static inline void udma_rchanrt_update_bits(struct udma_chan *uc, int reg, - u32 mask, u32 val) -{ - if (!uc->rchan) - return; - udma_update_bits(uc->rchan->reg_rt, reg, mask, val); -} - static int navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_th= read) { struct udma_tisci_rm *tisci_rm =3D &ud->tisci_rm; @@ -216,17 +131,6 @@ static void udma_dump_chan_stdata(struct udma_chan *uc) } } =20 -static inline dma_addr_t udma_curr_cppi5_desc_paddr(struct udma_desc *d, - int idx) -{ - return d->hwdesc[idx].cppi5_desc_paddr; -} - -static inline void *udma_curr_cppi5_desc_vaddr(struct udma_desc *d, int id= x) -{ - return d->hwdesc[idx].cppi5_desc_vaddr; -} - static struct udma_desc *udma_udma_desc_from_paddr(struct udma_chan *uc, dma_addr_t paddr) { @@ -369,11 +273,6 @@ static bool udma_is_chan_paused(struct udma_chan *uc) return false; } =20 -static inline dma_addr_t udma_get_rx_flush_hwdesc_paddr(struct udma_chan *= uc) -{ - return uc->ud->rx_flush.hwdescs[uc->config.pkt_mode].cppi5_desc_paddr; -} - static int udma_push_to_ring(struct udma_chan *uc, int idx) { struct udma_desc *d =3D uc->desc; @@ -775,13 +674,6 @@ static void udma_cyclic_packet_elapsed(struct udma_cha= n *uc) d->desc_idx =3D (d->desc_idx + 1) % d->sglen; } =20 -static inline void udma_fetch_epib(struct udma_chan *uc, struct udma_desc = *d) -{ - struct cppi5_host_desc_t *h_desc =3D d->hwdesc[0].cppi5_desc_vaddr; - - memcpy(d->metadata, h_desc->epib, d->metadata_size); -} - static bool udma_is_desc_really_done(struct udma_chan *uc, struct udma_des= c *d) { u32 peer_bcnt, bcnt; diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h index 11d08adb0d69f..54e1757c3de38 100644 --- a/drivers/dma/ti/k3-udma.h +++ b/drivers/dma/ti/k3-udma.h @@ -451,6 +451,115 @@ struct udma_chan { u32 id; }; =20 +/* K3 UDMA helper functions */ +static inline struct udma_dev *to_udma_dev(struct dma_device *d) +{ + return container_of(d, struct udma_dev, ddev); +} + +static inline struct udma_chan *to_udma_chan(struct dma_chan *c) +{ + return container_of(c, struct udma_chan, vc.chan); +} + +static inline struct udma_desc *to_udma_desc(struct dma_async_tx_descripto= r *t) +{ + return container_of(t, struct udma_desc, vd.tx); +} + +/* Generic register access functions */ +static inline u32 udma_read(void __iomem *base, int reg) +{ + return readl(base + reg); +} + +static inline void udma_write(void __iomem *base, int reg, u32 val) +{ + writel(val, base + reg); +} + +static inline void udma_update_bits(void __iomem *base, int reg, + u32 mask, u32 val) +{ + u32 tmp, orig; + + orig =3D readl(base + reg); + tmp =3D orig & ~mask; + tmp |=3D (val & mask); + + if (tmp !=3D orig) + writel(tmp, base + reg); +} + +/* TCHANRT */ +static inline u32 udma_tchanrt_read(struct udma_chan *uc, int reg) +{ + if (!uc->tchan) + return 0; + return udma_read(uc->tchan->reg_rt, reg); +} + +static inline void udma_tchanrt_write(struct udma_chan *uc, int reg, u32 v= al) +{ + if (!uc->tchan) + return; + udma_write(uc->tchan->reg_rt, reg, val); +} + +static inline void udma_tchanrt_update_bits(struct udma_chan *uc, int reg, + u32 mask, u32 val) +{ + if (!uc->tchan) + return; + udma_update_bits(uc->tchan->reg_rt, reg, mask, val); +} + +/* RCHANRT */ +static inline u32 udma_rchanrt_read(struct udma_chan *uc, int reg) +{ + if (!uc->rchan) + return 0; + return udma_read(uc->rchan->reg_rt, reg); +} + +static inline void udma_rchanrt_write(struct udma_chan *uc, int reg, u32 v= al) +{ + if (!uc->rchan) + return; + udma_write(uc->rchan->reg_rt, reg, val); +} + +static inline void udma_rchanrt_update_bits(struct udma_chan *uc, int reg, + u32 mask, u32 val) +{ + if (!uc->rchan) + return; + udma_update_bits(uc->rchan->reg_rt, reg, mask, val); +} + +static inline dma_addr_t udma_curr_cppi5_desc_paddr(struct udma_desc *d, + int idx) +{ + return d->hwdesc[idx].cppi5_desc_paddr; +} + +static inline void *udma_curr_cppi5_desc_vaddr(struct udma_desc *d, int id= x) +{ + return d->hwdesc[idx].cppi5_desc_vaddr; +} + +static inline dma_addr_t udma_get_rx_flush_hwdesc_paddr(struct udma_chan *= uc) +{ + return uc->ud->rx_flush.hwdescs[uc->config.pkt_mode].cppi5_desc_paddr; +} + +static inline void udma_fetch_epib(struct udma_chan *uc, struct udma_desc = *d) +{ + struct cppi5_host_desc_t *h_desc =3D d->hwdesc[0].cppi5_desc_vaddr; + + memcpy(d->metadata, h_desc->epib, d->metadata_size); +} + /* Direct access to UDMA low lever resources for the glue layer */ int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thr= ead); int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread, --=20 2.54.0 From nobody Tue Sep 29 08:26:17 2026 Received: from mx0a-0002e601.pphosted.com (mx0a-0002e601.pphosted.com [148.163.150.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F060371895; Mon, 28 Sep 2026 02:58:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.150.75 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564341; cv=fail; b=Wk3YrHkTUI6kE/dwK4DsCoRx4aoJn1IbpNC5XH85VJE0FBxcgOc/1XEghKAOg8vF3pMvOCzAhrg1sdlxJOCb9Hj27TM5TO/g6p3YGpz14VMm2mcgEoKnzxJ+eTVcV0K4w5VXkDzDKVhdUKVM3FJtM8rjtSnEQYJp5bpjChUuqUI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564341; c=relaxed/simple; bh=oOVkMmTaGAXp5/IPFcWjjYID0tc7XJq9PhiQXfYL74M=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kq2+rt2fdONfc6KsDvicwmcuWB8BsgkEC2+6/M1DOzorbpTOBjRMQvJWCapcnTLpVoOQlpj0JENqF46Q1aEoc9/wDtpCg7qxG9qS4Rj5gOpC/eWc9+CMaOc++sb6ouuEEbjnOMme4yJVZWoKSNR25WuZ7HB9atm3OW9MVsVCick= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=mWF84qlQ; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=CK9WvyXM; arc=fail smtp.client-ip=148.163.150.75 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="mWF84qlQ"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="CK9WvyXM" Received: from pps.filterd (m0384305.ppops.net [127.0.0.1]) by m0384305.ppops.net (8.18.1.11/8.18.1.11) with ESMTP id 68RNiAXc3706250; Sun, 27 Sep 2026 21:58:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=HmrWC352jGNFSwZ8VO5JUAExUZ3Gk8JbL9ClBlqAw DA=; b=mWF84qlQRrtpPUxyBDaOPHIJTg/YrEGAPM1HOozNujC2WtTgqKFPBDG7R jLWMMF0/lRWW8beUPUcGlnHO0xd4GUJ8qygW/Vz6ZHF7nIdFZ7oKDwcR5ATpa+Z1 QxAqM2I5D2rW6aPw9cd8dbrMpkF3rDrjjIMkrasVc615xlcTdJfErc4oByzryIVb k3eCUaU5qGNwfO7uTHW8NQPRkSZZaZmRppm9XymsIt0jknmvaTCB8kjKRCD8kfqu LNCkTmBFYuSg2ai0d7MI3UQctjqJqbwKfgUA9YFoLho0u637c/WujtkQiTpDD9Mr 7uE2dfjgIz8rK4XyRjTO3aDjoC48w== Received: from bn1pr04cu002.outbound.protection.outlook.com (mail-eastus2azon11010034.outbound.protection.outlook.com [52.101.56.34]) by m0384305.ppops.net (PPS) with ESMTPS id 4gy00nb1q5-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Sun, 27 Sep 2026 21:58:46 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Vt2tVqz7Ttq9DktEt6NfkKvKpr0lbrChd1Urlgfm4Mfkp6IuZyBUkCXfJTqEWnD94HbSix2azbZ5FTwVSarf564EAcgzF7ZHq7fnSl3vOYKODHTo/oDgyyCx0VBeTF5wuZZ/V1s3WjNVMQT6FSqs4nhAXJKmqIfXG1vnTtLve3ETYSZrO3wNutqwVX5Z8r1hAKVjAkG94M1WWahLY0CveCjT52J+3HyCb3ebTeJlJE0IuMitYedHD4NPK/cU0itZMQm9QxGMkqGCs24cCO5sWZqw37ey+hj+BDyJ3gyWxztCFPF+FGydAoG40zz7/wrk4aUBukfqisMHWGYOEpBvAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=HmrWC352jGNFSwZ8VO5JUAExUZ3Gk8JbL9ClBlqAwDA=; b=b+CUyK86TUEarQJjRs0+FbsSwrcMBRxrtSxCqpr7nFOQHomkuvycBvYu9wo+dSKPqREMl8UFcPHRcrZPY72QKIDjPIHraSMctYYGvM31etTyAHTkT+y+3mBEm6vqMiRAyymZMRIVRE52mjKCNuyEYJkwdsW3zi9Ku/JSpEJ7quAALrjhyYlvf6OVETsMdaR6Q+XkO020H10Tx5kBla1ezV/KwN5y917GUeq3Rn24fS2eaVNCApmC6cmPjHQWJVWJIepJWKN5Mx8YXWz/HzrSGqsveKb5YSoyIMiBV8QnG2Mp3LPPld/UhUvEZGWnSbdQjqOdF7DvcbT6IHv/b8YrDQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.23.194) smtp.rcpttodomain=nxp.com smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=HmrWC352jGNFSwZ8VO5JUAExUZ3Gk8JbL9ClBlqAwDA=; b=CK9WvyXMB37dD+NH/FLsUNPtLdOrsCVYEzrb6KI2yXoFsJAgU6vCjXM4WtvDqmuljsVtke0Is9GaAtO4fOBFlPjjvuYOzqEZstvK+J7/Q22bcnF14JxuTi1738I9Pqz04ftJRqZocCNb5NxftLIkiAdQhcq7u1UQH4LXIAHunPc= Received: from CH0PR04CA0071.namprd04.prod.outlook.com (2603:10b6:610:74::16) by IA1PR10MB5972.namprd10.prod.outlook.com (2603:10b6:208:3ec::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.451.18; Mon, 28 Sep 2026 02:58:37 +0000 Received: from CH2PEPF00000147.namprd02.prod.outlook.com (2603:10b6:610:74:cafe::6f) by CH0PR04CA0071.outlook.office365.com (2603:10b6:610:74::16) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.451.23 via Frontend Transport; Mon, 28 Sep 2026 02:58:37 +0000 X-MS-Exchange-Authentication-Results: mx.microsoft.com 1; spf=pass (sender IP is 198.47.23.194) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.23.194 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.23.194; helo=lewvzet200.ext.ti.com; pr=C Received: from lewvzet200.ext.ti.com (198.47.23.194) by CH2PEPF00000147.mail.protection.outlook.com (10.167.244.104) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Mon, 28 Sep 2026 02:58:37 +0000 Received: from DLEE200.ent.ti.com (157.170.170.75) by lewvzet200.ext.ti.com (10.4.14.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:21 -0500 Received: from DLEE203.ent.ti.com (157.170.170.78) by DLEE200.ent.ti.com (157.170.170.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:21 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE203.ent.ti.com (157.170.170.78) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45 via Frontend Transport; Sun, 27 Sep 2026 21:58:21 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [10.24.51.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 68S2vqqC2256662; Sun, 27 Sep 2026 21:58:16 -0500 From: Sai Sree Kartheek Adivi To: , , , , , , , , , , , , , CC: , Subject: [PATCH v10 05/19] dmaengine: ti: k3-udma: move descriptor management to k3-udma-common.c Date: Mon, 28 Sep 2026 08:26:11 +0530 Message-ID: <20260928025749.1055383-6-s-adivi@ti.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260928025749.1055383-1-s-adivi@ti.com> References: <20260928025749.1055383-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000147:EE_|IA1PR10MB5972:EE_ X-MS-Office365-Filtering-Correlation-Id: 4dd3365a-0600-4693-bcad-08df1d0c647b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|23010399003|1800799024|7416014|376014|36860700016|13003099007|921020|6133799003|3023799007|10067099003|5023799004|56012099006|18002099003|22082099003|10063799003; X-Microsoft-Antispam-Message-Info: Ung9rNsIqY1s3RfvpLeI+/M13yPp7XrMzddKKXnxZZNNf8DB8zgRwYb0BalCgSVkOiybyIWVMCYeeWXnURyZ9ZeV0+p0MZbxQVpzaDOUN1evcg3CJVRmtBGzVvEFzHaIf/cpnen0PehDD4WHZER1iYp1ujbCyfhHkcDyZdLD0qsy0HzIO1TpHEck6n+heB1C9z7IY3fexUEfU/lF0PJfzV1P7qWw/wOK/wPbshfpD+wL8Ldl2YpJ9DxDOLPVB8skDzMoNY34TJJ9CdoHefqHDdk8KlwltgbRIvDzmncTXldCPpe0wuZ5xAbx+d7MiCEX9iR/t8rq50/cteYaQYMPibC3uYHCdg7tRczN8aPuQBdgLanVZKhBEtlOxEqqXjJEdywXI1SoPWVtl63CINcz4J5kQfomWL6T9kQ6pe3Ic4iRvwlKEkcQLXion2UWgP0JEFHKY6VwVlpNoqZnvC50TX7zG/kQvBYKJ5W5USugUgCAwcUDcyoEECZhYCUWW2aNZ55J0DFTe3p4HS/dyEBoeVvUm7iag1zeKqZwaVa4n5CIsgEm4RFHHQPHUolHDejveLLgNWRpyvcA0tobPGGtBfD6RPc4upHk76iK1qRoNGCMym16+VORPopnpt029+aS+cBcNZpUhB3+rBTbhU/3Q7PQhAY2VJNMAU0BHkWwKjepVzy05AD8AAGD0qJunyB9 X-Forefront-Antispam-Report: CIP:198.47.23.194;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:lewvzet200.ext.ti.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(23010399003)(1800799024)(7416014)(376014)(36860700016)(13003099007)(921020)(6133799003)(3023799007)(10067099003)(5023799004)(56012099006)(18002099003)(22082099003)(10063799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ASH0fYa3UR3uw2zBkaiFATL63zHHuxsuyF4TpgViCz6r0xzveuIP/TisqyJqSTwyVF9gF59EkQhSkO1V+1RxRbQoLUMv15sNZ1XjzuJaQ+VCX5srevY8kr7v6lSKT26eCrLzFEPxHDVa3czld97BSIbyBEO8ri/Q/HQjlkImLKufseo/n/WWLU9P1cO4gzfYaEqnrw8rEI9G5jDc8S+0TX/BCuHK+f00Ku+HCBraHr587wBg2w4C+t97ZKHIHhHWwiGaNl7xC+JWWVUHttOEYoky7FG4R+uOLl38K9qFseezVnbzczbpLaB++1hiXoi4EByzZsrTG3argfDtc7/M9DHp+9stQ168/CSl1APqpOUFT/cPolZ2Ar+TakROHDV3U0Bwv0jik1MkAHkStFdvbevqU5u5G5ARVJuwFOspDzMqy7rzVC1IQ90qVX5dpxfX X-Exchange-RoutingPolicyChecked: NpWgujeAmDNWkBLkr5nv139Cb0djmAz5R1vBUtOgMQq79QcMNhai9NedtTf7wEHwttdyCvGQ3ZGkW/dkrIHHt0fYJpBRORMDXeH7cCQ9UPcWaE87l7fNqz6gacnD0jsBTdVxFkPqoRlLp3MChztBTD3Bh8Gc4TZfynulY+Q+IdwNWEId8jpZz4ZpdCM4MQs3taRfae8bPfyZEMeEmluop+LrZHia6DUxmVRqY179l+noMdkvt7Oa9yBeqlsTacJOW/UvHhRqECpDu2hd0cvEHtAsFWYPsC0N+s8fVpnljEhUnOdEAAMhl0kz+ZRhqz1V7/WCZVe2p1eQirI8W9j9bA== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 02:58:37.1627 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4dd3365a-0600-4693-bcad-08df1d0c647b X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.194];Helo=[lewvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000147.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR10MB5972 X-Proofpoint-GUID: 1rn7RVLNO5hjK16ocOY1Ea87UfQZyeC_ X-Authority-Analysis: v=2.4 cv=fKysTpae c=1 sm=1 tr=0 ts=6ab9d7e6 cx=c_pps a=KX2Ufr5/9I0VBrHrQzOW6Q==:117 a=WotqVVQAdb04rnGuttW3Kw==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=VdqzKS8jKosA:10 a=s63m1ICgrNkA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=taLDd7a_hP9WKsMzeGRc:22 a=sozttTNsAAAA:8 a=9fA4dagTuIDSJ7NYoQoA:9 a=x_a8ZKo73Tz1WADx:21 X-Proofpoint-ORIG-GUID: 1rn7RVLNO5hjK16ocOY1Ea87UfQZyeC_ X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX2ujpcIsD91Pd lfIVPZ/g3u6w+wWhAkz2PDGbSzpkuvtlBQ1A4m1J56om7BR974Kanhq7Y6TbMaa33bAyxny/30D rJuW0vUE+xCjE6b39T7rfPFnVzNyew4= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX426j5PPuw2l6 layuFLD9O6LTg94stIuSBm6AzL5BXX7H4kZs+LUKLdyaxqU5r9hKDvk9/At7s5o7aR4r9bsp1ef 2jNo3nmXs7aaNJnBFTITe5niLxdY3J0mnG3wuEQE/YzdTDCWMdy8kCLrMYlPfU7L7qrh3zkwCSS TXwhJhnuB+4TzpHLww8yLYnLFLeUjVBywZDp9Erzo1MrR5W2hGbKS9gwfYoZ6RqU4qu2bx+8d0i bswEq89ETTHaR2hW9hXmS3/vha49Y+JcOoq3Mf+aGumwfI6XbGy+rxojOUf1f/VtK1hfWVShxzq CVhvkBXjYG80vA33EgqQ4U+FCmbKaVenB8/7majDgYgYPIQvUcRCT0C6zvKXFF91e/hQ9ssfTkv FS3Rt7Hu1d7NX1JVsqX7woA/HbVlfrI2b7/GQ+q2D4m8EyJhLLEmD/6I2nsTkQuNrIdNzuTXBHd dVmKFcPa22Xg5Zw4Tgw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 spamscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 adultscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280011 Content-Type: text/plain; charset="utf-8" Refactor the K3 UDMA driver by moving all DMA descriptor handling functions from k3-udma.c to a new common library, k3-udma-common.c. This prepares the driver for supporting new K3 UDMA v2 variant (used in AM62L) that can reuse the same descriptor handling logic. To ensure this common code works correctly across all build configurations (built-in vs modules), introduce a hidden Kconfig symbol: CONFIG_TI_K3_UDMA_COMMON. No functional changes intended. Signed-off-by: Sai Sree Kartheek Adivi --- drivers/dma/ti/Kconfig | 4 + drivers/dma/ti/Makefile | 1 + drivers/dma/ti/k3-udma-common.c | 1243 +++++++++++++++++++++++++++++++ drivers/dma/ti/k3-udma.c | 1218 ------------------------------ drivers/dma/ti/k3-udma.h | 54 ++ 5 files changed, 1302 insertions(+), 1218 deletions(-) create mode 100644 drivers/dma/ti/k3-udma-common.c diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig index cbc30ab627832..a389ae04ec930 100644 --- a/drivers/dma/ti/Kconfig +++ b/drivers/dma/ti/Kconfig @@ -42,12 +42,16 @@ config TI_K3_UDMA select DMA_ENGINE select DMA_VIRTUAL_CHANNELS select SOC_TI + select TI_K3_UDMA_COMMON select TI_K3_RINGACC select TI_K3_PSIL help Enable support for the TI UDMA (Unified DMA) controller. This DMA engine is used in AM65x and j721e. =20 +config TI_K3_UDMA_COMMON + tristate + config TI_K3_UDMA_GLUE_LAYER tristate "Texas Instruments UDMA Glue layer for non DMAengine users" depends on ARCH_K3 || COMPILE_TEST diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile index d376c117cecf6..3b91c02e55eaf 100644 --- a/drivers/dma/ti/Makefile +++ b/drivers/dma/ti/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_TI_CPPI41) +=3D cppi41.o obj-$(CONFIG_TI_EDMA) +=3D edma.o obj-$(CONFIG_DMA_OMAP) +=3D omap-dma.o obj-$(CONFIG_TI_K3_UDMA) +=3D k3-udma.o +obj-$(CONFIG_TI_K3_UDMA_COMMON) +=3D k3-udma-common.o obj-$(CONFIG_TI_K3_UDMA_GLUE_LAYER) +=3D k3-udma-glue.o k3-psil-lib-objs :=3D k3-psil.o \ k3-psil-am654.o \ diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-commo= n.c new file mode 100644 index 0000000000000..3130805a8ec40 --- /dev/null +++ b/drivers/dma/ti/k3-udma-common.c @@ -0,0 +1,1243 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com + * Author: Peter Ujfalusi + */ + +#include +#include +#include +#include +#include + +#include "k3-udma.h" + +static const struct dma_descriptor_metadata_ops metadata_ops =3D { + .attach =3D udma_attach_metadata, + .get_ptr =3D udma_get_metadata_ptr, + .set_len =3D udma_set_metadata_len, +}; + +struct udma_desc *udma_udma_desc_from_paddr(struct udma_chan *uc, + dma_addr_t paddr) +{ + struct udma_desc *d =3D uc->terminated_desc; + + if (d) { + dma_addr_t desc_paddr =3D udma_curr_cppi5_desc_paddr(d, + d->desc_idx); + + if (desc_paddr !=3D paddr) + d =3D NULL; + } + + if (!d) { + d =3D uc->desc; + if (d) { + dma_addr_t desc_paddr =3D udma_curr_cppi5_desc_paddr(d, + d->desc_idx); + + if (desc_paddr !=3D paddr) + d =3D NULL; + } + } + + return d; +} +EXPORT_SYMBOL_GPL(udma_udma_desc_from_paddr); + +void udma_free_hwdesc(struct udma_chan *uc, struct udma_desc *d) +{ + if (uc->use_dma_pool) { + int i; + + for (i =3D 0; i < d->hwdesc_count; i++) { + if (!d->hwdesc[i].cppi5_desc_vaddr) + continue; + + dma_pool_free(uc->hdesc_pool, + d->hwdesc[i].cppi5_desc_vaddr, + d->hwdesc[i].cppi5_desc_paddr); + + d->hwdesc[i].cppi5_desc_vaddr =3D NULL; + } + } else if (d->hwdesc[0].cppi5_desc_vaddr) { + dma_free_coherent(uc->dma_dev, d->hwdesc[0].cppi5_desc_size, + d->hwdesc[0].cppi5_desc_vaddr, + d->hwdesc[0].cppi5_desc_paddr); + + d->hwdesc[0].cppi5_desc_vaddr =3D NULL; + } +} + +void udma_purge_desc_work(struct work_struct *work) +{ + struct udma_dev *ud =3D container_of(work, typeof(*ud), purge_work); + struct virt_dma_desc *vd, *_vd; + unsigned long flags; + LIST_HEAD(head); + + spin_lock_irqsave(&ud->lock, flags); + list_splice_tail_init(&ud->desc_to_purge, &head); + spin_unlock_irqrestore(&ud->lock, flags); + + list_for_each_entry_safe(vd, _vd, &head, node) { + struct udma_chan *uc =3D to_udma_chan(vd->tx.chan); + struct udma_desc *d =3D to_udma_desc(&vd->tx); + + udma_free_hwdesc(uc, d); + list_del(&vd->node); + kfree(d); + } + + /* If more to purge, schedule the work again */ + if (!list_empty(&ud->desc_to_purge)) + schedule_work(&ud->purge_work); +} +EXPORT_SYMBOL_GPL(udma_purge_desc_work); + +void udma_desc_free(struct virt_dma_desc *vd) +{ + struct udma_dev *ud =3D to_udma_dev(vd->tx.chan->device); + struct udma_chan *uc =3D to_udma_chan(vd->tx.chan); + struct udma_desc *d =3D to_udma_desc(&vd->tx); + unsigned long flags; + + if (uc->terminated_desc =3D=3D d) + uc->terminated_desc =3D NULL; + + if (uc->use_dma_pool) { + udma_free_hwdesc(uc, d); + kfree(d); + return; + } + + spin_lock_irqsave(&ud->lock, flags); + list_add_tail(&vd->node, &ud->desc_to_purge); + spin_unlock_irqrestore(&ud->lock, flags); + + schedule_work(&ud->purge_work); +} +EXPORT_SYMBOL_GPL(udma_desc_free); + +bool udma_desc_is_rx_flush(struct udma_chan *uc, dma_addr_t addr) +{ + if (uc->config.dir !=3D DMA_DEV_TO_MEM) + return false; + + if (addr =3D=3D udma_get_rx_flush_hwdesc_paddr(uc)) + return true; + + return false; +} +EXPORT_SYMBOL_GPL(udma_desc_is_rx_flush); + +bool udma_is_desc_really_done(struct udma_chan *uc, struct udma_desc *d) +{ + u32 peer_bcnt, bcnt; + + /* + * Only TX towards PDMA is affected. + * If DMA_PREP_INTERRUPT is not set by consumer then skip the transfer + * completion calculation, consumer must ensure that there is no stale + * data in DMA fabric in this case. + */ + if (uc->config.ep_type =3D=3D PSIL_EP_NATIVE || + uc->config.dir !=3D DMA_MEM_TO_DEV || !(uc->config.tx_flags & DMA_PRE= P_INTERRUPT)) + return true; + + peer_bcnt =3D udma_tchanrt_read(uc, UDMA_CHAN_RT_PEER_BCNT_REG); + bcnt =3D udma_tchanrt_read(uc, UDMA_CHAN_RT_BCNT_REG); + + /* Transfer is incomplete, store current residue and time stamp */ + if (peer_bcnt < bcnt) { + uc->tx_drain.residue =3D bcnt - peer_bcnt; + uc->tx_drain.tstamp =3D ktime_get(); + return false; + } + + return true; +} +EXPORT_SYMBOL_GPL(udma_is_desc_really_done); + +struct udma_desc *udma_alloc_tr_desc(struct udma_chan *uc, + size_t tr_size, int tr_count, + enum dma_transfer_direction dir) +{ + struct udma_hwdesc *hwdesc; + struct cppi5_desc_hdr_t *tr_desc; + struct udma_desc *d; + u32 reload_count =3D 0; + u32 ring_id; + + switch (tr_size) { + case 16: + case 32: + case 64: + case 128: + break; + default: + dev_err(uc->ud->dev, "Unsupported TR size of %zu\n", tr_size); + return NULL; + } + + /* We have only one descriptor containing multiple TRs */ + d =3D kzalloc(sizeof(*d) + sizeof(d->hwdesc[0]), GFP_NOWAIT); + if (!d) + return NULL; + + d->sglen =3D tr_count; + + d->hwdesc_count =3D 1; + hwdesc =3D &d->hwdesc[0]; + + /* Allocate memory for DMA ring descriptor */ + if (uc->use_dma_pool) { + hwdesc->cppi5_desc_size =3D uc->config.hdesc_size; + hwdesc->cppi5_desc_vaddr =3D dma_pool_zalloc(uc->hdesc_pool, + GFP_NOWAIT, + &hwdesc->cppi5_desc_paddr); + } else { + hwdesc->cppi5_desc_size =3D cppi5_trdesc_calc_size(tr_size, + tr_count); + hwdesc->cppi5_desc_size =3D ALIGN(hwdesc->cppi5_desc_size, + uc->ud->desc_align); + hwdesc->cppi5_desc_vaddr =3D dma_alloc_coherent(uc->ud->dev, + hwdesc->cppi5_desc_size, + &hwdesc->cppi5_desc_paddr, + GFP_NOWAIT); + } + + if (!hwdesc->cppi5_desc_vaddr) { + kfree(d); + return NULL; + } + + /* Start of the TR req records */ + hwdesc->tr_req_base =3D hwdesc->cppi5_desc_vaddr + tr_size; + /* Start address of the TR response array */ + hwdesc->tr_resp_base =3D hwdesc->tr_req_base + tr_size * tr_count; + + tr_desc =3D hwdesc->cppi5_desc_vaddr; + + if (uc->cyclic) + reload_count =3D CPPI5_INFO0_TRDESC_RLDCNT_INFINITE; + + if (dir =3D=3D DMA_DEV_TO_MEM) + ring_id =3D k3_ringacc_get_ring_id(uc->rflow->r_ring); + else + ring_id =3D k3_ringacc_get_ring_id(uc->tchan->tc_ring); + + cppi5_trdesc_init(tr_desc, tr_count, tr_size, 0, reload_count); + cppi5_desc_set_pktids(tr_desc, uc->id, + CPPI5_INFO1_DESC_FLOWID_DEFAULT); + cppi5_desc_set_retpolicy(tr_desc, 0, ring_id); + + return d; +} + +/** + * udma_get_tr_counters - calculate TR counters for a given length + * @len: Length of the transfer + * @align_to: Preferred alignment + * @tr0_cnt0: First TR icnt0 + * @tr0_cnt1: First TR icnt1 + * @tr1_cnt0: Second (if used) TR icnt0 + * + * For len < SZ_64K only one TR is enough, tr1_cnt0 is not updated + * For len >=3D SZ_64K two TRs are used in a simple way: + * First TR: SZ_64K-alignment blocks (tr0_cnt0, tr0_cnt1) + * Second TR: the remaining length (tr1_cnt0) + * + * Returns the number of TRs the length needs (1 or 2) + * -EINVAL if the length can not be supported + */ +int udma_get_tr_counters(size_t len, unsigned long align_to, + u16 *tr0_cnt0, u16 *tr0_cnt1, u16 *tr1_cnt0) +{ + if (len < SZ_64K) { + *tr0_cnt0 =3D len; + *tr0_cnt1 =3D 1; + + return 1; + } + + if (align_to > 3) + align_to =3D 3; + +realign: + *tr0_cnt0 =3D SZ_64K - BIT(align_to); + if (len / *tr0_cnt0 >=3D SZ_64K) { + if (align_to) { + align_to--; + goto realign; + } + return -EINVAL; + } + + *tr0_cnt1 =3D len / *tr0_cnt0; + *tr1_cnt0 =3D len % *tr0_cnt0; + + return 2; +} + +struct udma_desc * +udma_prep_slave_sg_tr(struct udma_chan *uc, struct scatterlist *sgl, + unsigned int sglen, enum dma_transfer_direction dir, + unsigned long tx_flags, void *context) +{ + struct scatterlist *sgent; + struct udma_desc *d; + struct cppi5_tr_type1_t *tr_req =3D NULL; + u16 tr0_cnt0, tr0_cnt1, tr1_cnt0; + unsigned int i; + size_t tr_size; + int num_tr =3D 0; + int tr_idx =3D 0; + u64 asel; + + /* estimate the number of TRs we will need */ + for_each_sg(sgl, sgent, sglen, i) { + if (sg_dma_len(sgent) < SZ_64K) + num_tr++; + else + num_tr +=3D 2; + } + + /* Now allocate and setup the descriptor. */ + tr_size =3D sizeof(struct cppi5_tr_type1_t); + d =3D udma_alloc_tr_desc(uc, tr_size, num_tr, dir); + if (!d) + return NULL; + + d->sglen =3D sglen; + + if (uc->ud->match_data->type =3D=3D DMA_TYPE_UDMA) + asel =3D 0; + else + asel =3D (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; + + tr_req =3D d->hwdesc[0].tr_req_base; + for_each_sg(sgl, sgent, sglen, i) { + dma_addr_t sg_addr =3D sg_dma_address(sgent); + + num_tr =3D udma_get_tr_counters(sg_dma_len(sgent), __ffs(sg_addr), + &tr0_cnt0, &tr0_cnt1, &tr1_cnt0); + if (num_tr < 0) { + dev_err(uc->ud->dev, "size %u is not supported\n", + sg_dma_len(sgent)); + udma_free_hwdesc(uc, d); + kfree(d); + return NULL; + } + + cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false, + false, CPPI5_TR_EVENT_SIZE_COMPLETION, 0); + cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT); + + sg_addr |=3D asel; + tr_req[tr_idx].addr =3D sg_addr; + tr_req[tr_idx].icnt0 =3D tr0_cnt0; + tr_req[tr_idx].icnt1 =3D tr0_cnt1; + tr_req[tr_idx].dim1 =3D tr0_cnt0; + tr_idx++; + + if (num_tr =3D=3D 2) { + cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, + false, false, + CPPI5_TR_EVENT_SIZE_COMPLETION, 0); + cppi5_tr_csf_set(&tr_req[tr_idx].flags, + CPPI5_TR_CSF_SUPR_EVT); + + tr_req[tr_idx].addr =3D sg_addr + tr0_cnt1 * tr0_cnt0; + tr_req[tr_idx].icnt0 =3D tr1_cnt0; + tr_req[tr_idx].icnt1 =3D 1; + tr_req[tr_idx].dim1 =3D tr1_cnt0; + tr_idx++; + } + + d->residue +=3D sg_dma_len(sgent); + } + + cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags, + CPPI5_TR_CSF_SUPR_EVT | CPPI5_TR_CSF_EOP); + + return d; +} + +struct udma_desc * +udma_prep_slave_sg_triggered_tr(struct udma_chan *uc, struct scatterlist *= sgl, + unsigned int sglen, + enum dma_transfer_direction dir, + unsigned long tx_flags, void *context) +{ + struct scatterlist *sgent; + struct cppi5_tr_type15_t *tr_req =3D NULL; + enum dma_slave_buswidth dev_width; + u32 csf =3D CPPI5_TR_CSF_SUPR_EVT; + u16 tr_cnt0, tr_cnt1; + dma_addr_t dev_addr; + struct udma_desc *d; + unsigned int i; + size_t tr_size, sg_len; + int num_tr =3D 0; + int tr_idx =3D 0; + u32 burst, trigger_size, port_window; + u64 asel; + + if (dir =3D=3D DMA_DEV_TO_MEM) { + dev_addr =3D uc->cfg.src_addr; + dev_width =3D uc->cfg.src_addr_width; + burst =3D uc->cfg.src_maxburst; + port_window =3D uc->cfg.src_port_window_size; + } else if (dir =3D=3D DMA_MEM_TO_DEV) { + dev_addr =3D uc->cfg.dst_addr; + dev_width =3D uc->cfg.dst_addr_width; + burst =3D uc->cfg.dst_maxburst; + port_window =3D uc->cfg.dst_port_window_size; + } else { + dev_err(uc->ud->dev, "%s: bad direction?\n", __func__); + return NULL; + } + + if (!burst) + burst =3D 1; + + if (port_window) { + if (port_window !=3D burst) { + dev_err(uc->ud->dev, + "The burst must be equal to port_window\n"); + return NULL; + } + + tr_cnt0 =3D dev_width * port_window; + tr_cnt1 =3D 1; + } else { + tr_cnt0 =3D dev_width; + tr_cnt1 =3D burst; + } + trigger_size =3D tr_cnt0 * tr_cnt1; + + /* estimate the number of TRs we will need */ + for_each_sg(sgl, sgent, sglen, i) { + sg_len =3D sg_dma_len(sgent); + + if (sg_len % trigger_size) { + dev_err(uc->ud->dev, + "Not aligned SG entry (%zu for %u)\n", sg_len, + trigger_size); + return NULL; + } + + if (sg_len / trigger_size < SZ_64K) + num_tr++; + else + num_tr +=3D 2; + } + + /* Now allocate and setup the descriptor. */ + tr_size =3D sizeof(struct cppi5_tr_type15_t); + d =3D udma_alloc_tr_desc(uc, tr_size, num_tr, dir); + if (!d) + return NULL; + + d->sglen =3D sglen; + + if (uc->ud->match_data->type =3D=3D DMA_TYPE_UDMA) { + asel =3D 0; + csf |=3D CPPI5_TR_CSF_EOL_ICNT0; + } else { + asel =3D (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; + dev_addr |=3D asel; + } + + tr_req =3D d->hwdesc[0].tr_req_base; + for_each_sg(sgl, sgent, sglen, i) { + u16 tr0_cnt2, tr0_cnt3, tr1_cnt2; + dma_addr_t sg_addr =3D sg_dma_address(sgent); + + sg_len =3D sg_dma_len(sgent); + num_tr =3D udma_get_tr_counters(sg_len / trigger_size, 0, + &tr0_cnt2, &tr0_cnt3, &tr1_cnt2); + if (num_tr < 0) { + dev_err(uc->ud->dev, "size %zu is not supported\n", + sg_len); + udma_free_hwdesc(uc, d); + kfree(d); + return NULL; + } + + cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE15, false, + true, CPPI5_TR_EVENT_SIZE_COMPLETION, 0); + cppi5_tr_csf_set(&tr_req[tr_idx].flags, csf); + cppi5_tr_set_trigger(&tr_req[tr_idx].flags, + uc->config.tr_trigger_type, + CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC, 0, 0); + + sg_addr |=3D asel; + if (dir =3D=3D DMA_DEV_TO_MEM) { + tr_req[tr_idx].addr =3D dev_addr; + tr_req[tr_idx].icnt0 =3D tr_cnt0; + tr_req[tr_idx].icnt1 =3D tr_cnt1; + tr_req[tr_idx].icnt2 =3D tr0_cnt2; + tr_req[tr_idx].icnt3 =3D tr0_cnt3; + tr_req[tr_idx].dim1 =3D (-1) * tr_cnt0; + + tr_req[tr_idx].daddr =3D sg_addr; + tr_req[tr_idx].dicnt0 =3D tr_cnt0; + tr_req[tr_idx].dicnt1 =3D tr_cnt1; + tr_req[tr_idx].dicnt2 =3D tr0_cnt2; + tr_req[tr_idx].dicnt3 =3D tr0_cnt3; + tr_req[tr_idx].ddim1 =3D tr_cnt0; + tr_req[tr_idx].ddim2 =3D trigger_size; + tr_req[tr_idx].ddim3 =3D trigger_size * tr0_cnt2; + } else { + tr_req[tr_idx].addr =3D sg_addr; + tr_req[tr_idx].icnt0 =3D tr_cnt0; + tr_req[tr_idx].icnt1 =3D tr_cnt1; + tr_req[tr_idx].icnt2 =3D tr0_cnt2; + tr_req[tr_idx].icnt3 =3D tr0_cnt3; + tr_req[tr_idx].dim1 =3D tr_cnt0; + tr_req[tr_idx].dim2 =3D trigger_size; + tr_req[tr_idx].dim3 =3D trigger_size * tr0_cnt2; + + tr_req[tr_idx].daddr =3D dev_addr; + tr_req[tr_idx].dicnt0 =3D tr_cnt0; + tr_req[tr_idx].dicnt1 =3D tr_cnt1; + tr_req[tr_idx].dicnt2 =3D tr0_cnt2; + tr_req[tr_idx].dicnt3 =3D tr0_cnt3; + tr_req[tr_idx].ddim1 =3D (-1) * tr_cnt0; + } + + tr_idx++; + + if (num_tr =3D=3D 2) { + cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE15, + false, true, + CPPI5_TR_EVENT_SIZE_COMPLETION, 0); + cppi5_tr_csf_set(&tr_req[tr_idx].flags, csf); + cppi5_tr_set_trigger(&tr_req[tr_idx].flags, + uc->config.tr_trigger_type, + CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC, + 0, 0); + + sg_addr +=3D trigger_size * tr0_cnt2 * tr0_cnt3; + if (dir =3D=3D DMA_DEV_TO_MEM) { + tr_req[tr_idx].addr =3D dev_addr; + tr_req[tr_idx].icnt0 =3D tr_cnt0; + tr_req[tr_idx].icnt1 =3D tr_cnt1; + tr_req[tr_idx].icnt2 =3D tr1_cnt2; + tr_req[tr_idx].icnt3 =3D 1; + tr_req[tr_idx].dim1 =3D (-1) * tr_cnt0; + + tr_req[tr_idx].daddr =3D sg_addr; + tr_req[tr_idx].dicnt0 =3D tr_cnt0; + tr_req[tr_idx].dicnt1 =3D tr_cnt1; + tr_req[tr_idx].dicnt2 =3D tr1_cnt2; + tr_req[tr_idx].dicnt3 =3D 1; + tr_req[tr_idx].ddim1 =3D tr_cnt0; + tr_req[tr_idx].ddim2 =3D trigger_size; + } else { + tr_req[tr_idx].addr =3D sg_addr; + tr_req[tr_idx].icnt0 =3D tr_cnt0; + tr_req[tr_idx].icnt1 =3D tr_cnt1; + tr_req[tr_idx].icnt2 =3D tr1_cnt2; + tr_req[tr_idx].icnt3 =3D 1; + tr_req[tr_idx].dim1 =3D tr_cnt0; + tr_req[tr_idx].dim2 =3D trigger_size; + + tr_req[tr_idx].daddr =3D dev_addr; + tr_req[tr_idx].dicnt0 =3D tr_cnt0; + tr_req[tr_idx].dicnt1 =3D tr_cnt1; + tr_req[tr_idx].dicnt2 =3D tr1_cnt2; + tr_req[tr_idx].dicnt3 =3D 1; + tr_req[tr_idx].ddim1 =3D (-1) * tr_cnt0; + } + tr_idx++; + } + + d->residue +=3D sg_len; + } + + cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags, csf | CPPI5_TR_CSF_EOP); + + return d; +} + +int udma_configure_statictr(struct udma_chan *uc, struct udma_desc *d, + enum dma_slave_buswidth dev_width, + u16 elcnt) +{ + if (uc->config.ep_type !=3D PSIL_EP_PDMA_XY) + return 0; + + /* Bus width translates to the element size (ES) */ + switch (dev_width) { + case DMA_SLAVE_BUSWIDTH_1_BYTE: + d->static_tr.elsize =3D 0; + break; + case DMA_SLAVE_BUSWIDTH_2_BYTES: + d->static_tr.elsize =3D 1; + break; + case DMA_SLAVE_BUSWIDTH_3_BYTES: + d->static_tr.elsize =3D 2; + break; + case DMA_SLAVE_BUSWIDTH_4_BYTES: + d->static_tr.elsize =3D 3; + break; + case DMA_SLAVE_BUSWIDTH_8_BYTES: + d->static_tr.elsize =3D 4; + break; + default: /* not reached */ + return -EINVAL; + } + + d->static_tr.elcnt =3D elcnt; + + if (uc->config.pkt_mode || !uc->cyclic) { + /* + * PDMA must close the packet when the channel is in packet mode. + * For TR mode when the channel is not cyclic we also need PDMA + * to close the packet otherwise the transfer will stall because + * PDMA holds on the data it has received from the peripheral. + */ + unsigned int div =3D dev_width * elcnt; + + if (uc->cyclic) + d->static_tr.bstcnt =3D d->residue / d->sglen / div; + else + d->static_tr.bstcnt =3D d->residue / div; + } else if (uc->ud->match_data->type =3D=3D DMA_TYPE_BCDMA && + uc->config.dir =3D=3D DMA_DEV_TO_MEM && + uc->cyclic) { + /* + * For cyclic mode with BCDMA we have to set EOP in each TR to + * prevent short packet errors seen on channel teardown. So the + * PDMA must close the packet after every TR transfer by setting + * burst count equal to the number of bytes transferred. + */ + struct cppi5_tr_type1_t *tr_req =3D d->hwdesc[0].tr_req_base; + + d->static_tr.bstcnt =3D + (tr_req->icnt0 * tr_req->icnt1) / dev_width; + } else { + d->static_tr.bstcnt =3D 0; + } + + if (uc->config.dir =3D=3D DMA_DEV_TO_MEM && + d->static_tr.bstcnt > uc->ud->match_data->statictr_z_mask) + return -EINVAL; + + return 0; +} + +struct udma_desc * +udma_prep_slave_sg_pkt(struct udma_chan *uc, struct scatterlist *sgl, + unsigned int sglen, enum dma_transfer_direction dir, + unsigned long tx_flags, void *context) +{ + struct scatterlist *sgent; + struct cppi5_host_desc_t *h_desc =3D NULL; + struct udma_desc *d; + u32 ring_id; + unsigned int i; + u64 asel; + + d =3D kzalloc(struct_size(d, hwdesc, sglen), GFP_NOWAIT); + if (!d) + return NULL; + + d->sglen =3D sglen; + d->hwdesc_count =3D sglen; + + if (dir =3D=3D DMA_DEV_TO_MEM) + ring_id =3D k3_ringacc_get_ring_id(uc->rflow->r_ring); + else + ring_id =3D k3_ringacc_get_ring_id(uc->tchan->tc_ring); + + if (uc->ud->match_data->type =3D=3D DMA_TYPE_UDMA) + asel =3D 0; + else + asel =3D (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; + + for_each_sg(sgl, sgent, sglen, i) { + struct udma_hwdesc *hwdesc =3D &d->hwdesc[i]; + dma_addr_t sg_addr =3D sg_dma_address(sgent); + struct cppi5_host_desc_t *desc; + size_t sg_len =3D sg_dma_len(sgent); + + hwdesc->cppi5_desc_vaddr =3D dma_pool_zalloc(uc->hdesc_pool, + GFP_NOWAIT, + &hwdesc->cppi5_desc_paddr); + if (!hwdesc->cppi5_desc_vaddr) { + dev_err(uc->ud->dev, + "descriptor%d allocation failed\n", i); + + udma_free_hwdesc(uc, d); + kfree(d); + return NULL; + } + + d->residue +=3D sg_len; + hwdesc->cppi5_desc_size =3D uc->config.hdesc_size; + desc =3D hwdesc->cppi5_desc_vaddr; + + if (i =3D=3D 0) { + cppi5_hdesc_init(desc, 0, 0); + /* Flow and Packed ID */ + cppi5_desc_set_pktids(&desc->hdr, uc->id, + CPPI5_INFO1_DESC_FLOWID_DEFAULT); + cppi5_desc_set_retpolicy(&desc->hdr, 0, ring_id); + } else { + cppi5_hdesc_reset_hbdesc(desc); + cppi5_desc_set_retpolicy(&desc->hdr, 0, 0xffff); + } + + /* attach the sg buffer to the descriptor */ + sg_addr |=3D asel; + cppi5_hdesc_attach_buf(desc, sg_addr, sg_len, sg_addr, sg_len); + + /* Attach link as host buffer descriptor */ + if (h_desc) + cppi5_hdesc_link_hbdesc(h_desc, + hwdesc->cppi5_desc_paddr | asel); + + if (uc->ud->match_data->type =3D=3D DMA_TYPE_PKTDMA || + dir =3D=3D DMA_MEM_TO_DEV) + h_desc =3D desc; + } + + if (d->residue >=3D SZ_4M) { + dev_err(uc->ud->dev, + "%s: Transfer size %u is over the supported 4M range\n", + __func__, d->residue); + udma_free_hwdesc(uc, d); + kfree(d); + return NULL; + } + + h_desc =3D d->hwdesc[0].cppi5_desc_vaddr; + cppi5_hdesc_set_pktlen(h_desc, d->residue); + + return d; +} + +int udma_attach_metadata(struct dma_async_tx_descriptor *desc, + void *data, size_t len) +{ + struct udma_desc *d =3D to_udma_desc(desc); + struct udma_chan *uc =3D to_udma_chan(desc->chan); + struct cppi5_host_desc_t *h_desc; + u32 psd_size =3D len; + u32 flags =3D 0; + + if (!uc->config.pkt_mode || !uc->config.metadata_size) + return -EOPNOTSUPP; + + if (!data || len > uc->config.metadata_size) + return -EINVAL; + + if (uc->config.needs_epib && len < CPPI5_INFO0_HDESC_EPIB_SIZE) + return -EINVAL; + + h_desc =3D d->hwdesc[0].cppi5_desc_vaddr; + if (d->dir =3D=3D DMA_MEM_TO_DEV) + memcpy(h_desc->epib, data, len); + + if (uc->config.needs_epib) + psd_size -=3D CPPI5_INFO0_HDESC_EPIB_SIZE; + + d->metadata =3D data; + d->metadata_size =3D len; + if (uc->config.needs_epib) + flags |=3D CPPI5_INFO0_HDESC_EPIB_PRESENT; + + cppi5_hdesc_update_flags(h_desc, flags); + cppi5_hdesc_update_psdata_size(h_desc, psd_size); + + return 0; +} + +void *udma_get_metadata_ptr(struct dma_async_tx_descriptor *desc, + size_t *payload_len, size_t *max_len) +{ + struct udma_desc *d =3D to_udma_desc(desc); + struct udma_chan *uc =3D to_udma_chan(desc->chan); + struct cppi5_host_desc_t *h_desc; + + if (!uc->config.pkt_mode || !uc->config.metadata_size) + return ERR_PTR(-EOPNOTSUPP); + + h_desc =3D d->hwdesc[0].cppi5_desc_vaddr; + + *max_len =3D uc->config.metadata_size; + + *payload_len =3D cppi5_hdesc_epib_present(&h_desc->hdr) ? + CPPI5_INFO0_HDESC_EPIB_SIZE : 0; + *payload_len +=3D cppi5_hdesc_get_psdata_size(h_desc); + + return h_desc->epib; +} + +int udma_set_metadata_len(struct dma_async_tx_descriptor *desc, + size_t payload_len) +{ + struct udma_desc *d =3D to_udma_desc(desc); + struct udma_chan *uc =3D to_udma_chan(desc->chan); + struct cppi5_host_desc_t *h_desc; + u32 psd_size =3D payload_len; + u32 flags =3D 0; + + if (!uc->config.pkt_mode || !uc->config.metadata_size) + return -EOPNOTSUPP; + + if (payload_len > uc->config.metadata_size) + return -EINVAL; + + if (uc->config.needs_epib && payload_len < CPPI5_INFO0_HDESC_EPIB_SIZE) + return -EINVAL; + + h_desc =3D d->hwdesc[0].cppi5_desc_vaddr; + + if (uc->config.needs_epib) { + psd_size -=3D CPPI5_INFO0_HDESC_EPIB_SIZE; + flags |=3D CPPI5_INFO0_HDESC_EPIB_PRESENT; + } + + cppi5_hdesc_update_flags(h_desc, flags); + cppi5_hdesc_update_psdata_size(h_desc, psd_size); + + return 0; +} + +struct dma_async_tx_descriptor * +udma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sglen, enum dma_transfer_direction dir, + unsigned long tx_flags, void *context) +{ + struct udma_chan *uc =3D to_udma_chan(chan); + enum dma_slave_buswidth dev_width; + struct udma_desc *d; + u32 burst; + + if (dir !=3D uc->config.dir && + (uc->config.dir =3D=3D DMA_MEM_TO_MEM && !uc->config.tr_trigger_type)= ) { + dev_err(chan->device->dev, + "%s: chan%d is for %s, not supporting %s\n", + __func__, uc->id, + dmaengine_get_direction_text(uc->config.dir), + dmaengine_get_direction_text(dir)); + return NULL; + } + + if (dir =3D=3D DMA_DEV_TO_MEM) { + dev_width =3D uc->cfg.src_addr_width; + burst =3D uc->cfg.src_maxburst; + } else if (dir =3D=3D DMA_MEM_TO_DEV) { + dev_width =3D uc->cfg.dst_addr_width; + burst =3D uc->cfg.dst_maxburst; + } else { + dev_err(chan->device->dev, "%s: bad direction?\n", __func__); + return NULL; + } + + if (!burst) + burst =3D 1; + + uc->config.tx_flags =3D tx_flags; + + if (uc->config.pkt_mode) + d =3D udma_prep_slave_sg_pkt(uc, sgl, sglen, dir, tx_flags, + context); + else if (is_slave_direction(uc->config.dir)) + d =3D udma_prep_slave_sg_tr(uc, sgl, sglen, dir, tx_flags, + context); + else + d =3D udma_prep_slave_sg_triggered_tr(uc, sgl, sglen, dir, + tx_flags, context); + + if (!d) + return NULL; + + d->dir =3D dir; + d->desc_idx =3D 0; + d->tr_idx =3D 0; + + /* static TR for remote PDMA */ + if (udma_configure_statictr(uc, d, dev_width, burst)) { + dev_err(uc->ud->dev, + "%s: StaticTR Z is limited to maximum %u (%u)\n", + __func__, uc->ud->match_data->statictr_z_mask, + d->static_tr.bstcnt); + + udma_free_hwdesc(uc, d); + kfree(d); + return NULL; + } + + if (uc->config.metadata_size) + d->vd.tx.metadata_ops =3D &metadata_ops; + + return vchan_tx_prep(&uc->vc, &d->vd, tx_flags); +} +EXPORT_SYMBOL_GPL(udma_prep_slave_sg); + +struct udma_desc * +udma_prep_dma_cyclic_tr(struct udma_chan *uc, dma_addr_t buf_addr, + size_t buf_len, size_t period_len, + enum dma_transfer_direction dir, unsigned long flags) +{ + struct udma_desc *d; + size_t tr_size, period_addr; + struct cppi5_tr_type1_t *tr_req; + unsigned int periods =3D buf_len / period_len; + u16 tr0_cnt0, tr0_cnt1, tr1_cnt0; + unsigned int i; + int num_tr; + u32 period_csf =3D 0; + + num_tr =3D udma_get_tr_counters(period_len, __ffs(buf_addr), &tr0_cnt0, + &tr0_cnt1, &tr1_cnt0); + if (num_tr < 0) { + dev_err(uc->ud->dev, "size %zu is not supported\n", + period_len); + return NULL; + } + + /* Now allocate and setup the descriptor. */ + tr_size =3D sizeof(struct cppi5_tr_type1_t); + d =3D udma_alloc_tr_desc(uc, tr_size, periods * num_tr, dir); + if (!d) + return NULL; + + tr_req =3D d->hwdesc[0].tr_req_base; + if (uc->ud->match_data->type =3D=3D DMA_TYPE_UDMA) + period_addr =3D buf_addr; + else + period_addr =3D buf_addr | + ((u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT); + + /* + * For BCDMA <-> PDMA transfers, the EOP flag needs to be set on the + * last TR of a descriptor, to mark the packet as complete. + * This is required for getting the teardown completion message in case + * of TX, and to avoid short-packet error in case of RX. + * + * As we are in cyclic mode, we do not know which period might be the + * last one, so set the flag for each period. + */ + if (uc->config.ep_type =3D=3D PSIL_EP_PDMA_XY && + uc->ud->match_data->type =3D=3D DMA_TYPE_BCDMA) { + period_csf =3D CPPI5_TR_CSF_EOP; + } + + for (i =3D 0; i < periods; i++) { + int tr_idx =3D i * num_tr; + + cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false, + false, CPPI5_TR_EVENT_SIZE_COMPLETION, 0); + + tr_req[tr_idx].addr =3D period_addr; + tr_req[tr_idx].icnt0 =3D tr0_cnt0; + tr_req[tr_idx].icnt1 =3D tr0_cnt1; + tr_req[tr_idx].dim1 =3D tr0_cnt0; + + if (num_tr =3D=3D 2) { + cppi5_tr_csf_set(&tr_req[tr_idx].flags, + CPPI5_TR_CSF_SUPR_EVT); + tr_idx++; + + cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, + false, false, + CPPI5_TR_EVENT_SIZE_COMPLETION, 0); + + tr_req[tr_idx].addr =3D period_addr + tr0_cnt1 * tr0_cnt0; + tr_req[tr_idx].icnt0 =3D tr1_cnt0; + tr_req[tr_idx].icnt1 =3D 1; + tr_req[tr_idx].dim1 =3D tr1_cnt0; + } + + if (!(flags & DMA_PREP_INTERRUPT)) + period_csf |=3D CPPI5_TR_CSF_SUPR_EVT; + + if (period_csf) + cppi5_tr_csf_set(&tr_req[tr_idx].flags, period_csf); + + period_addr +=3D period_len; + } + + return d; +} + +struct udma_desc * +udma_prep_dma_cyclic_pkt(struct udma_chan *uc, dma_addr_t buf_addr, + size_t buf_len, size_t period_len, + enum dma_transfer_direction dir, unsigned long flags) +{ + struct udma_desc *d; + u32 ring_id; + int i; + int periods =3D buf_len / period_len; + + if (periods > (K3_UDMA_DEFAULT_RING_SIZE - 1)) + return NULL; + + if (period_len >=3D SZ_4M) + return NULL; + + d =3D kzalloc(struct_size(d, hwdesc, periods), GFP_NOWAIT); + if (!d) + return NULL; + + d->hwdesc_count =3D periods; + + /* TODO: re-check this... */ + if (dir =3D=3D DMA_DEV_TO_MEM) + ring_id =3D k3_ringacc_get_ring_id(uc->rflow->r_ring); + else + ring_id =3D k3_ringacc_get_ring_id(uc->tchan->tc_ring); + + if (uc->ud->match_data->type !=3D DMA_TYPE_UDMA) + buf_addr |=3D (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; + + for (i =3D 0; i < periods; i++) { + struct udma_hwdesc *hwdesc =3D &d->hwdesc[i]; + dma_addr_t period_addr =3D buf_addr + (period_len * i); + struct cppi5_host_desc_t *h_desc; + + hwdesc->cppi5_desc_vaddr =3D dma_pool_zalloc(uc->hdesc_pool, + GFP_NOWAIT, + &hwdesc->cppi5_desc_paddr); + if (!hwdesc->cppi5_desc_vaddr) { + dev_err(uc->ud->dev, + "descriptor%d allocation failed\n", i); + + udma_free_hwdesc(uc, d); + kfree(d); + return NULL; + } + + hwdesc->cppi5_desc_size =3D uc->config.hdesc_size; + h_desc =3D hwdesc->cppi5_desc_vaddr; + + cppi5_hdesc_init(h_desc, 0, 0); + cppi5_hdesc_set_pktlen(h_desc, period_len); + + /* Flow and Packed ID */ + cppi5_desc_set_pktids(&h_desc->hdr, uc->id, + CPPI5_INFO1_DESC_FLOWID_DEFAULT); + cppi5_desc_set_retpolicy(&h_desc->hdr, 0, ring_id); + + /* attach each period to a new descriptor */ + cppi5_hdesc_attach_buf(h_desc, + period_addr, period_len, + period_addr, period_len); + } + + return d; +} + +struct dma_async_tx_descriptor * +udma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t bu= f_len, + size_t period_len, enum dma_transfer_direction dir, + unsigned long flags) +{ + struct udma_chan *uc =3D to_udma_chan(chan); + enum dma_slave_buswidth dev_width; + struct udma_desc *d; + u32 burst; + + if (dir !=3D uc->config.dir) { + dev_err(chan->device->dev, + "%s: chan%d is for %s, not supporting %s\n", + __func__, uc->id, + dmaengine_get_direction_text(uc->config.dir), + dmaengine_get_direction_text(dir)); + return NULL; + } + + uc->cyclic =3D true; + + if (dir =3D=3D DMA_DEV_TO_MEM) { + dev_width =3D uc->cfg.src_addr_width; + burst =3D uc->cfg.src_maxburst; + } else if (dir =3D=3D DMA_MEM_TO_DEV) { + dev_width =3D uc->cfg.dst_addr_width; + burst =3D uc->cfg.dst_maxburst; + } else { + dev_err(uc->ud->dev, "%s: bad direction?\n", __func__); + return NULL; + } + + if (!burst) + burst =3D 1; + + if (uc->config.pkt_mode) + d =3D udma_prep_dma_cyclic_pkt(uc, buf_addr, buf_len, period_len, + dir, flags); + else + d =3D udma_prep_dma_cyclic_tr(uc, buf_addr, buf_len, period_len, + dir, flags); + + if (!d) + return NULL; + + d->sglen =3D buf_len / period_len; + + d->dir =3D dir; + d->residue =3D buf_len; + + /* static TR for remote PDMA */ + if (udma_configure_statictr(uc, d, dev_width, burst)) { + dev_err(uc->ud->dev, + "%s: StaticTR Z is limited to maximum %u (%u)\n", + __func__, uc->ud->match_data->statictr_z_mask, + d->static_tr.bstcnt); + + udma_free_hwdesc(uc, d); + kfree(d); + return NULL; + } + + if (uc->config.metadata_size) + d->vd.tx.metadata_ops =3D &metadata_ops; + + return vchan_tx_prep(&uc->vc, &d->vd, flags); +} +EXPORT_SYMBOL_GPL(udma_prep_dma_cyclic); + +struct dma_async_tx_descriptor * +udma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t sr= c, + size_t len, unsigned long tx_flags) +{ + struct udma_chan *uc =3D to_udma_chan(chan); + struct udma_desc *d; + struct cppi5_tr_type15_t *tr_req; + int num_tr; + size_t tr_size =3D sizeof(struct cppi5_tr_type15_t); + u16 tr0_cnt0, tr0_cnt1, tr1_cnt0; + u32 csf =3D CPPI5_TR_CSF_SUPR_EVT; + + if (uc->config.dir !=3D DMA_MEM_TO_MEM) { + dev_err(chan->device->dev, + "%s: chan%d is for %s, not supporting %s\n", + __func__, uc->id, + dmaengine_get_direction_text(uc->config.dir), + dmaengine_get_direction_text(DMA_MEM_TO_MEM)); + return NULL; + } + + num_tr =3D udma_get_tr_counters(len, __ffs(src | dest), &tr0_cnt0, + &tr0_cnt1, &tr1_cnt0); + if (num_tr < 0) { + dev_err(uc->ud->dev, "size %zu is not supported\n", + len); + return NULL; + } + + d =3D udma_alloc_tr_desc(uc, tr_size, num_tr, DMA_MEM_TO_MEM); + if (!d) + return NULL; + + d->dir =3D DMA_MEM_TO_MEM; + d->desc_idx =3D 0; + d->tr_idx =3D 0; + d->residue =3D len; + + if (uc->ud->match_data->type !=3D DMA_TYPE_UDMA) { + src |=3D (u64)uc->ud->asel << K3_ADDRESS_ASEL_SHIFT; + dest |=3D (u64)uc->ud->asel << K3_ADDRESS_ASEL_SHIFT; + } else { + csf |=3D CPPI5_TR_CSF_EOL_ICNT0; + } + + tr_req =3D d->hwdesc[0].tr_req_base; + + cppi5_tr_init(&tr_req[0].flags, CPPI5_TR_TYPE15, false, true, + CPPI5_TR_EVENT_SIZE_COMPLETION, 0); + cppi5_tr_csf_set(&tr_req[0].flags, csf); + + tr_req[0].addr =3D src; + tr_req[0].icnt0 =3D tr0_cnt0; + tr_req[0].icnt1 =3D tr0_cnt1; + tr_req[0].icnt2 =3D 1; + tr_req[0].icnt3 =3D 1; + tr_req[0].dim1 =3D tr0_cnt0; + + tr_req[0].daddr =3D dest; + tr_req[0].dicnt0 =3D tr0_cnt0; + tr_req[0].dicnt1 =3D tr0_cnt1; + tr_req[0].dicnt2 =3D 1; + tr_req[0].dicnt3 =3D 1; + tr_req[0].ddim1 =3D tr0_cnt0; + + if (num_tr =3D=3D 2) { + cppi5_tr_init(&tr_req[1].flags, CPPI5_TR_TYPE15, false, true, + CPPI5_TR_EVENT_SIZE_COMPLETION, 0); + cppi5_tr_csf_set(&tr_req[1].flags, csf); + + tr_req[1].addr =3D src + tr0_cnt1 * tr0_cnt0; + tr_req[1].icnt0 =3D tr1_cnt0; + tr_req[1].icnt1 =3D 1; + tr_req[1].icnt2 =3D 1; + tr_req[1].icnt3 =3D 1; + + tr_req[1].daddr =3D dest + tr0_cnt1 * tr0_cnt0; + tr_req[1].dicnt0 =3D tr1_cnt0; + tr_req[1].dicnt1 =3D 1; + tr_req[1].dicnt2 =3D 1; + tr_req[1].dicnt3 =3D 1; + } + + cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, csf | CPPI5_TR_CSF_EOP); + + if (uc->config.metadata_size) + d->vd.tx.metadata_ops =3D &metadata_ops; + + return vchan_tx_prep(&uc->vc, &d->vd, tx_flags); +} +EXPORT_SYMBOL_GPL(udma_prep_dma_memcpy); + +void udma_desc_pre_callback(struct virt_dma_chan *vc, + struct virt_dma_desc *vd, + struct dmaengine_result *result) +{ + struct udma_chan *uc =3D to_udma_chan(&vc->chan); + struct udma_desc *d; + u8 status; + + if (!vd) + return; + + d =3D to_udma_desc(&vd->tx); + + if (d->metadata_size) + udma_fetch_epib(uc, d); + + if (result) { + void *desc_vaddr =3D udma_curr_cppi5_desc_vaddr(d, d->desc_idx); + + if (cppi5_desc_get_type(desc_vaddr) =3D=3D + CPPI5_INFO0_DESC_TYPE_VAL_HOST) { + /* Provide residue information for the client */ + result->residue =3D d->residue - + cppi5_hdesc_get_pktlen(desc_vaddr); + if (result->residue) + result->result =3D DMA_TRANS_ABORTED; + else + result->result =3D DMA_TRANS_NOERROR; + } else { + result->residue =3D 0; + /* Propagate TR Response errors to the client */ + status =3D d->hwdesc[0].tr_resp_base->status; + if (status) + result->result =3D DMA_TRANS_ABORTED; + else + result->result =3D DMA_TRANS_NOERROR; + } + } +} +EXPORT_SYMBOL_GPL(udma_desc_pre_callback); + +MODULE_DESCRIPTION("Texas Instruments K3 UDMA Common Library"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 5336ec9fe79ce..a8fe919f307f6 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -131,105 +131,6 @@ static void udma_dump_chan_stdata(struct udma_chan *u= c) } } =20 -static struct udma_desc *udma_udma_desc_from_paddr(struct udma_chan *uc, - dma_addr_t paddr) -{ - struct udma_desc *d =3D uc->terminated_desc; - - if (d) { - dma_addr_t desc_paddr =3D udma_curr_cppi5_desc_paddr(d, - d->desc_idx); - - if (desc_paddr !=3D paddr) - d =3D NULL; - } - - if (!d) { - d =3D uc->desc; - if (d) { - dma_addr_t desc_paddr =3D udma_curr_cppi5_desc_paddr(d, - d->desc_idx); - - if (desc_paddr !=3D paddr) - d =3D NULL; - } - } - - return d; -} - -static void udma_free_hwdesc(struct udma_chan *uc, struct udma_desc *d) -{ - if (uc->use_dma_pool) { - int i; - - for (i =3D 0; i < d->hwdesc_count; i++) { - if (!d->hwdesc[i].cppi5_desc_vaddr) - continue; - - dma_pool_free(uc->hdesc_pool, - d->hwdesc[i].cppi5_desc_vaddr, - d->hwdesc[i].cppi5_desc_paddr); - - d->hwdesc[i].cppi5_desc_vaddr =3D NULL; - } - } else if (d->hwdesc[0].cppi5_desc_vaddr) { - dma_free_coherent(uc->dma_dev, d->hwdesc[0].cppi5_desc_size, - d->hwdesc[0].cppi5_desc_vaddr, - d->hwdesc[0].cppi5_desc_paddr); - - d->hwdesc[0].cppi5_desc_vaddr =3D NULL; - } -} - -static void udma_purge_desc_work(struct work_struct *work) -{ - struct udma_dev *ud =3D container_of(work, typeof(*ud), purge_work); - struct virt_dma_desc *vd, *_vd; - unsigned long flags; - LIST_HEAD(head); - - spin_lock_irqsave(&ud->lock, flags); - list_splice_tail_init(&ud->desc_to_purge, &head); - spin_unlock_irqrestore(&ud->lock, flags); - - list_for_each_entry_safe(vd, _vd, &head, node) { - struct udma_chan *uc =3D to_udma_chan(vd->tx.chan); - struct udma_desc *d =3D to_udma_desc(&vd->tx); - - udma_free_hwdesc(uc, d); - list_del(&vd->node); - kfree(d); - } - - /* If more to purge, schedule the work again */ - if (!list_empty(&ud->desc_to_purge)) - schedule_work(&ud->purge_work); -} - -static void udma_desc_free(struct virt_dma_desc *vd) -{ - struct udma_dev *ud =3D to_udma_dev(vd->tx.chan->device); - struct udma_chan *uc =3D to_udma_chan(vd->tx.chan); - struct udma_desc *d =3D to_udma_desc(&vd->tx); - unsigned long flags; - - if (uc->terminated_desc =3D=3D d) - uc->terminated_desc =3D NULL; - - if (uc->use_dma_pool) { - udma_free_hwdesc(uc, d); - kfree(d); - return; - } - - spin_lock_irqsave(&ud->lock, flags); - list_add_tail(&vd->node, &ud->desc_to_purge); - spin_unlock_irqrestore(&ud->lock, flags); - - schedule_work(&ud->purge_work); -} - static bool udma_is_chan_running(struct udma_chan *uc) { u32 trt_ctl =3D 0; @@ -303,17 +204,6 @@ static int udma_push_to_ring(struct udma_chan *uc, int= idx) return k3_ringacc_ring_push(ring, &paddr); } =20 -static bool udma_desc_is_rx_flush(struct udma_chan *uc, dma_addr_t addr) -{ - if (uc->config.dir !=3D DMA_DEV_TO_MEM) - return false; - - if (addr =3D=3D udma_get_rx_flush_hwdesc_paddr(uc)) - return true; - - return false; -} - static int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr) { struct k3_ring *ring =3D NULL; @@ -674,33 +564,6 @@ static void udma_cyclic_packet_elapsed(struct udma_cha= n *uc) d->desc_idx =3D (d->desc_idx + 1) % d->sglen; } =20 -static bool udma_is_desc_really_done(struct udma_chan *uc, struct udma_des= c *d) -{ - u32 peer_bcnt, bcnt; - - /* - * Only TX towards PDMA is affected. - * If DMA_PREP_INTERRUPT is not set by consumer then skip the transfer - * completion calculation, consumer must ensure that there is no stale - * data in DMA fabric in this case. - */ - if (uc->config.ep_type =3D=3D PSIL_EP_NATIVE || - uc->config.dir !=3D DMA_MEM_TO_DEV || !(uc->config.tx_flags & DMA_PRE= P_INTERRUPT)) - return true; - - peer_bcnt =3D udma_tchanrt_read(uc, UDMA_CHAN_RT_PEER_BCNT_REG); - bcnt =3D udma_tchanrt_read(uc, UDMA_CHAN_RT_BCNT_REG); - - /* Transfer is incomplete, store current residue and time stamp */ - if (peer_bcnt < bcnt) { - uc->tx_drain.residue =3D bcnt - peer_bcnt; - uc->tx_drain.tstamp =3D ktime_get(); - return false; - } - - return true; -} - static void udma_check_tx_completion(struct work_struct *work) { struct udma_chan *uc =3D container_of(work, typeof(*uc), @@ -2344,1047 +2207,6 @@ static int udma_slave_config(struct dma_chan *chan, return 0; } =20 -static struct udma_desc *udma_alloc_tr_desc(struct udma_chan *uc, - size_t tr_size, int tr_count, - enum dma_transfer_direction dir) -{ - struct udma_hwdesc *hwdesc; - struct cppi5_desc_hdr_t *tr_desc; - struct udma_desc *d; - u32 reload_count =3D 0; - u32 ring_id; - - switch (tr_size) { - case 16: - case 32: - case 64: - case 128: - break; - default: - dev_err(uc->ud->dev, "Unsupported TR size of %zu\n", tr_size); - return NULL; - } - - /* We have only one descriptor containing multiple TRs */ - d =3D kzalloc(sizeof(*d) + sizeof(d->hwdesc[0]), GFP_NOWAIT); - if (!d) - return NULL; - - d->sglen =3D tr_count; - - d->hwdesc_count =3D 1; - hwdesc =3D &d->hwdesc[0]; - - /* Allocate memory for DMA ring descriptor */ - if (uc->use_dma_pool) { - hwdesc->cppi5_desc_size =3D uc->config.hdesc_size; - hwdesc->cppi5_desc_vaddr =3D dma_pool_zalloc(uc->hdesc_pool, - GFP_NOWAIT, - &hwdesc->cppi5_desc_paddr); - } else { - hwdesc->cppi5_desc_size =3D cppi5_trdesc_calc_size(tr_size, - tr_count); - hwdesc->cppi5_desc_size =3D ALIGN(hwdesc->cppi5_desc_size, - uc->ud->desc_align); - hwdesc->cppi5_desc_vaddr =3D dma_alloc_coherent(uc->ud->dev, - hwdesc->cppi5_desc_size, - &hwdesc->cppi5_desc_paddr, - GFP_NOWAIT); - } - - if (!hwdesc->cppi5_desc_vaddr) { - kfree(d); - return NULL; - } - - /* Start of the TR req records */ - hwdesc->tr_req_base =3D hwdesc->cppi5_desc_vaddr + tr_size; - /* Start address of the TR response array */ - hwdesc->tr_resp_base =3D hwdesc->tr_req_base + tr_size * tr_count; - - tr_desc =3D hwdesc->cppi5_desc_vaddr; - - if (uc->cyclic) - reload_count =3D CPPI5_INFO0_TRDESC_RLDCNT_INFINITE; - - if (dir =3D=3D DMA_DEV_TO_MEM) - ring_id =3D k3_ringacc_get_ring_id(uc->rflow->r_ring); - else - ring_id =3D k3_ringacc_get_ring_id(uc->tchan->tc_ring); - - cppi5_trdesc_init(tr_desc, tr_count, tr_size, 0, reload_count); - cppi5_desc_set_pktids(tr_desc, uc->id, - CPPI5_INFO1_DESC_FLOWID_DEFAULT); - cppi5_desc_set_retpolicy(tr_desc, 0, ring_id); - - return d; -} - -/** - * udma_get_tr_counters - calculate TR counters for a given length - * @len: Length of the trasnfer - * @align_to: Preferred alignment - * @tr0_cnt0: First TR icnt0 - * @tr0_cnt1: First TR icnt1 - * @tr1_cnt0: Second (if used) TR icnt0 - * - * For len < SZ_64K only one TR is enough, tr1_cnt0 is not updated - * For len >=3D SZ_64K two TRs are used in a simple way: - * First TR: SZ_64K-alignment blocks (tr0_cnt0, tr0_cnt1) - * Second TR: the remaining length (tr1_cnt0) - * - * Returns the number of TRs the length needs (1 or 2) - * -EINVAL if the length can not be supported - */ -static int udma_get_tr_counters(size_t len, unsigned long align_to, - u16 *tr0_cnt0, u16 *tr0_cnt1, u16 *tr1_cnt0) -{ - if (len < SZ_64K) { - *tr0_cnt0 =3D len; - *tr0_cnt1 =3D 1; - - return 1; - } - - if (align_to > 3) - align_to =3D 3; - -realign: - *tr0_cnt0 =3D SZ_64K - BIT(align_to); - if (len / *tr0_cnt0 >=3D SZ_64K) { - if (align_to) { - align_to--; - goto realign; - } - return -EINVAL; - } - - *tr0_cnt1 =3D len / *tr0_cnt0; - *tr1_cnt0 =3D len % *tr0_cnt0; - - return 2; -} - -static struct udma_desc * -udma_prep_slave_sg_tr(struct udma_chan *uc, struct scatterlist *sgl, - unsigned int sglen, enum dma_transfer_direction dir, - unsigned long tx_flags, void *context) -{ - struct scatterlist *sgent; - struct udma_desc *d; - struct cppi5_tr_type1_t *tr_req =3D NULL; - u16 tr0_cnt0, tr0_cnt1, tr1_cnt0; - unsigned int i; - size_t tr_size; - int num_tr =3D 0; - int tr_idx =3D 0; - u64 asel; - - /* estimate the number of TRs we will need */ - for_each_sg(sgl, sgent, sglen, i) { - if (sg_dma_len(sgent) < SZ_64K) - num_tr++; - else - num_tr +=3D 2; - } - - /* Now allocate and setup the descriptor. */ - tr_size =3D sizeof(struct cppi5_tr_type1_t); - d =3D udma_alloc_tr_desc(uc, tr_size, num_tr, dir); - if (!d) - return NULL; - - d->sglen =3D sglen; - - if (uc->ud->match_data->type =3D=3D DMA_TYPE_UDMA) - asel =3D 0; - else - asel =3D (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; - - tr_req =3D d->hwdesc[0].tr_req_base; - for_each_sg(sgl, sgent, sglen, i) { - dma_addr_t sg_addr =3D sg_dma_address(sgent); - - num_tr =3D udma_get_tr_counters(sg_dma_len(sgent), __ffs(sg_addr), - &tr0_cnt0, &tr0_cnt1, &tr1_cnt0); - if (num_tr < 0) { - dev_err(uc->ud->dev, "size %u is not supported\n", - sg_dma_len(sgent)); - udma_free_hwdesc(uc, d); - kfree(d); - return NULL; - } - - cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false, - false, CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT); - - sg_addr |=3D asel; - tr_req[tr_idx].addr =3D sg_addr; - tr_req[tr_idx].icnt0 =3D tr0_cnt0; - tr_req[tr_idx].icnt1 =3D tr0_cnt1; - tr_req[tr_idx].dim1 =3D tr0_cnt0; - tr_idx++; - - if (num_tr =3D=3D 2) { - cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, - false, false, - CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - cppi5_tr_csf_set(&tr_req[tr_idx].flags, - CPPI5_TR_CSF_SUPR_EVT); - - tr_req[tr_idx].addr =3D sg_addr + tr0_cnt1 * tr0_cnt0; - tr_req[tr_idx].icnt0 =3D tr1_cnt0; - tr_req[tr_idx].icnt1 =3D 1; - tr_req[tr_idx].dim1 =3D tr1_cnt0; - tr_idx++; - } - - d->residue +=3D sg_dma_len(sgent); - } - - cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags, - CPPI5_TR_CSF_SUPR_EVT | CPPI5_TR_CSF_EOP); - - return d; -} - -static struct udma_desc * -udma_prep_slave_sg_triggered_tr(struct udma_chan *uc, struct scatterlist *= sgl, - unsigned int sglen, - enum dma_transfer_direction dir, - unsigned long tx_flags, void *context) -{ - struct scatterlist *sgent; - struct cppi5_tr_type15_t *tr_req =3D NULL; - enum dma_slave_buswidth dev_width; - u32 csf =3D CPPI5_TR_CSF_SUPR_EVT; - u16 tr_cnt0, tr_cnt1; - dma_addr_t dev_addr; - struct udma_desc *d; - unsigned int i; - size_t tr_size, sg_len; - int num_tr =3D 0; - int tr_idx =3D 0; - u32 burst, trigger_size, port_window; - u64 asel; - - if (dir =3D=3D DMA_DEV_TO_MEM) { - dev_addr =3D uc->cfg.src_addr; - dev_width =3D uc->cfg.src_addr_width; - burst =3D uc->cfg.src_maxburst; - port_window =3D uc->cfg.src_port_window_size; - } else if (dir =3D=3D DMA_MEM_TO_DEV) { - dev_addr =3D uc->cfg.dst_addr; - dev_width =3D uc->cfg.dst_addr_width; - burst =3D uc->cfg.dst_maxburst; - port_window =3D uc->cfg.dst_port_window_size; - } else { - dev_err(uc->ud->dev, "%s: bad direction?\n", __func__); - return NULL; - } - - if (!burst) - burst =3D 1; - - if (port_window) { - if (port_window !=3D burst) { - dev_err(uc->ud->dev, - "The burst must be equal to port_window\n"); - return NULL; - } - - tr_cnt0 =3D dev_width * port_window; - tr_cnt1 =3D 1; - } else { - tr_cnt0 =3D dev_width; - tr_cnt1 =3D burst; - } - trigger_size =3D tr_cnt0 * tr_cnt1; - - /* estimate the number of TRs we will need */ - for_each_sg(sgl, sgent, sglen, i) { - sg_len =3D sg_dma_len(sgent); - - if (sg_len % trigger_size) { - dev_err(uc->ud->dev, - "Not aligned SG entry (%zu for %u)\n", sg_len, - trigger_size); - return NULL; - } - - if (sg_len / trigger_size < SZ_64K) - num_tr++; - else - num_tr +=3D 2; - } - - /* Now allocate and setup the descriptor. */ - tr_size =3D sizeof(struct cppi5_tr_type15_t); - d =3D udma_alloc_tr_desc(uc, tr_size, num_tr, dir); - if (!d) - return NULL; - - d->sglen =3D sglen; - - if (uc->ud->match_data->type =3D=3D DMA_TYPE_UDMA) { - asel =3D 0; - csf |=3D CPPI5_TR_CSF_EOL_ICNT0; - } else { - asel =3D (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; - dev_addr |=3D asel; - } - - tr_req =3D d->hwdesc[0].tr_req_base; - for_each_sg(sgl, sgent, sglen, i) { - u16 tr0_cnt2, tr0_cnt3, tr1_cnt2; - dma_addr_t sg_addr =3D sg_dma_address(sgent); - - sg_len =3D sg_dma_len(sgent); - num_tr =3D udma_get_tr_counters(sg_len / trigger_size, 0, - &tr0_cnt2, &tr0_cnt3, &tr1_cnt2); - if (num_tr < 0) { - dev_err(uc->ud->dev, "size %zu is not supported\n", - sg_len); - udma_free_hwdesc(uc, d); - kfree(d); - return NULL; - } - - cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE15, false, - true, CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - cppi5_tr_csf_set(&tr_req[tr_idx].flags, csf); - cppi5_tr_set_trigger(&tr_req[tr_idx].flags, - uc->config.tr_trigger_type, - CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC, 0, 0); - - sg_addr |=3D asel; - if (dir =3D=3D DMA_DEV_TO_MEM) { - tr_req[tr_idx].addr =3D dev_addr; - tr_req[tr_idx].icnt0 =3D tr_cnt0; - tr_req[tr_idx].icnt1 =3D tr_cnt1; - tr_req[tr_idx].icnt2 =3D tr0_cnt2; - tr_req[tr_idx].icnt3 =3D tr0_cnt3; - tr_req[tr_idx].dim1 =3D (-1) * tr_cnt0; - - tr_req[tr_idx].daddr =3D sg_addr; - tr_req[tr_idx].dicnt0 =3D tr_cnt0; - tr_req[tr_idx].dicnt1 =3D tr_cnt1; - tr_req[tr_idx].dicnt2 =3D tr0_cnt2; - tr_req[tr_idx].dicnt3 =3D tr0_cnt3; - tr_req[tr_idx].ddim1 =3D tr_cnt0; - tr_req[tr_idx].ddim2 =3D trigger_size; - tr_req[tr_idx].ddim3 =3D trigger_size * tr0_cnt2; - } else { - tr_req[tr_idx].addr =3D sg_addr; - tr_req[tr_idx].icnt0 =3D tr_cnt0; - tr_req[tr_idx].icnt1 =3D tr_cnt1; - tr_req[tr_idx].icnt2 =3D tr0_cnt2; - tr_req[tr_idx].icnt3 =3D tr0_cnt3; - tr_req[tr_idx].dim1 =3D tr_cnt0; - tr_req[tr_idx].dim2 =3D trigger_size; - tr_req[tr_idx].dim3 =3D trigger_size * tr0_cnt2; - - tr_req[tr_idx].daddr =3D dev_addr; - tr_req[tr_idx].dicnt0 =3D tr_cnt0; - tr_req[tr_idx].dicnt1 =3D tr_cnt1; - tr_req[tr_idx].dicnt2 =3D tr0_cnt2; - tr_req[tr_idx].dicnt3 =3D tr0_cnt3; - tr_req[tr_idx].ddim1 =3D (-1) * tr_cnt0; - } - - tr_idx++; - - if (num_tr =3D=3D 2) { - cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE15, - false, true, - CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - cppi5_tr_csf_set(&tr_req[tr_idx].flags, csf); - cppi5_tr_set_trigger(&tr_req[tr_idx].flags, - uc->config.tr_trigger_type, - CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC, - 0, 0); - - sg_addr +=3D trigger_size * tr0_cnt2 * tr0_cnt3; - if (dir =3D=3D DMA_DEV_TO_MEM) { - tr_req[tr_idx].addr =3D dev_addr; - tr_req[tr_idx].icnt0 =3D tr_cnt0; - tr_req[tr_idx].icnt1 =3D tr_cnt1; - tr_req[tr_idx].icnt2 =3D tr1_cnt2; - tr_req[tr_idx].icnt3 =3D 1; - tr_req[tr_idx].dim1 =3D (-1) * tr_cnt0; - - tr_req[tr_idx].daddr =3D sg_addr; - tr_req[tr_idx].dicnt0 =3D tr_cnt0; - tr_req[tr_idx].dicnt1 =3D tr_cnt1; - tr_req[tr_idx].dicnt2 =3D tr1_cnt2; - tr_req[tr_idx].dicnt3 =3D 1; - tr_req[tr_idx].ddim1 =3D tr_cnt0; - tr_req[tr_idx].ddim2 =3D trigger_size; - } else { - tr_req[tr_idx].addr =3D sg_addr; - tr_req[tr_idx].icnt0 =3D tr_cnt0; - tr_req[tr_idx].icnt1 =3D tr_cnt1; - tr_req[tr_idx].icnt2 =3D tr1_cnt2; - tr_req[tr_idx].icnt3 =3D 1; - tr_req[tr_idx].dim1 =3D tr_cnt0; - tr_req[tr_idx].dim2 =3D trigger_size; - - tr_req[tr_idx].daddr =3D dev_addr; - tr_req[tr_idx].dicnt0 =3D tr_cnt0; - tr_req[tr_idx].dicnt1 =3D tr_cnt1; - tr_req[tr_idx].dicnt2 =3D tr1_cnt2; - tr_req[tr_idx].dicnt3 =3D 1; - tr_req[tr_idx].ddim1 =3D (-1) * tr_cnt0; - } - tr_idx++; - } - - d->residue +=3D sg_len; - } - - cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags, csf | CPPI5_TR_CSF_EOP); - - return d; -} - -static int udma_configure_statictr(struct udma_chan *uc, struct udma_desc = *d, - enum dma_slave_buswidth dev_width, - u16 elcnt) -{ - if (uc->config.ep_type !=3D PSIL_EP_PDMA_XY) - return 0; - - /* Bus width translates to the element size (ES) */ - switch (dev_width) { - case DMA_SLAVE_BUSWIDTH_1_BYTE: - d->static_tr.elsize =3D 0; - break; - case DMA_SLAVE_BUSWIDTH_2_BYTES: - d->static_tr.elsize =3D 1; - break; - case DMA_SLAVE_BUSWIDTH_3_BYTES: - d->static_tr.elsize =3D 2; - break; - case DMA_SLAVE_BUSWIDTH_4_BYTES: - d->static_tr.elsize =3D 3; - break; - case DMA_SLAVE_BUSWIDTH_8_BYTES: - d->static_tr.elsize =3D 4; - break; - default: /* not reached */ - return -EINVAL; - } - - d->static_tr.elcnt =3D elcnt; - - if (uc->config.pkt_mode || !uc->cyclic) { - /* - * PDMA must close the packet when the channel is in packet mode. - * For TR mode when the channel is not cyclic we also need PDMA - * to close the packet otherwise the transfer will stall because - * PDMA holds on the data it has received from the peripheral. - */ - unsigned int div =3D dev_width * elcnt; - - if (uc->cyclic) - d->static_tr.bstcnt =3D d->residue / d->sglen / div; - else - d->static_tr.bstcnt =3D d->residue / div; - } else if (uc->ud->match_data->type =3D=3D DMA_TYPE_BCDMA && - uc->config.dir =3D=3D DMA_DEV_TO_MEM && - uc->cyclic) { - /* - * For cyclic mode with BCDMA we have to set EOP in each TR to - * prevent short packet errors seen on channel teardown. So the - * PDMA must close the packet after every TR transfer by setting - * burst count equal to the number of bytes transferred. - */ - struct cppi5_tr_type1_t *tr_req =3D d->hwdesc[0].tr_req_base; - - d->static_tr.bstcnt =3D - (tr_req->icnt0 * tr_req->icnt1) / dev_width; - } else { - d->static_tr.bstcnt =3D 0; - } - - if (uc->config.dir =3D=3D DMA_DEV_TO_MEM && - d->static_tr.bstcnt > uc->ud->match_data->statictr_z_mask) - return -EINVAL; - - return 0; -} - -static struct udma_desc * -udma_prep_slave_sg_pkt(struct udma_chan *uc, struct scatterlist *sgl, - unsigned int sglen, enum dma_transfer_direction dir, - unsigned long tx_flags, void *context) -{ - struct scatterlist *sgent; - struct cppi5_host_desc_t *h_desc =3D NULL; - struct udma_desc *d; - u32 ring_id; - unsigned int i; - u64 asel; - - d =3D kzalloc_flex(*d, hwdesc, sglen, GFP_NOWAIT); - if (!d) - return NULL; - - d->sglen =3D sglen; - d->hwdesc_count =3D sglen; - - if (dir =3D=3D DMA_DEV_TO_MEM) - ring_id =3D k3_ringacc_get_ring_id(uc->rflow->r_ring); - else - ring_id =3D k3_ringacc_get_ring_id(uc->tchan->tc_ring); - - if (uc->ud->match_data->type =3D=3D DMA_TYPE_UDMA) - asel =3D 0; - else - asel =3D (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; - - for_each_sg(sgl, sgent, sglen, i) { - struct udma_hwdesc *hwdesc =3D &d->hwdesc[i]; - dma_addr_t sg_addr =3D sg_dma_address(sgent); - struct cppi5_host_desc_t *desc; - size_t sg_len =3D sg_dma_len(sgent); - - hwdesc->cppi5_desc_vaddr =3D dma_pool_zalloc(uc->hdesc_pool, - GFP_NOWAIT, - &hwdesc->cppi5_desc_paddr); - if (!hwdesc->cppi5_desc_vaddr) { - dev_err(uc->ud->dev, - "descriptor%d allocation failed\n", i); - - udma_free_hwdesc(uc, d); - kfree(d); - return NULL; - } - - d->residue +=3D sg_len; - hwdesc->cppi5_desc_size =3D uc->config.hdesc_size; - desc =3D hwdesc->cppi5_desc_vaddr; - - if (i =3D=3D 0) { - cppi5_hdesc_init(desc, 0, 0); - /* Flow and Packed ID */ - cppi5_desc_set_pktids(&desc->hdr, uc->id, - CPPI5_INFO1_DESC_FLOWID_DEFAULT); - cppi5_desc_set_retpolicy(&desc->hdr, 0, ring_id); - } else { - cppi5_hdesc_reset_hbdesc(desc); - cppi5_desc_set_retpolicy(&desc->hdr, 0, 0xffff); - } - - /* attach the sg buffer to the descriptor */ - sg_addr |=3D asel; - cppi5_hdesc_attach_buf(desc, sg_addr, sg_len, sg_addr, sg_len); - - /* Attach link as host buffer descriptor */ - if (h_desc) - cppi5_hdesc_link_hbdesc(h_desc, - hwdesc->cppi5_desc_paddr | asel); - - if (uc->ud->match_data->type =3D=3D DMA_TYPE_PKTDMA || - dir =3D=3D DMA_MEM_TO_DEV) - h_desc =3D desc; - } - - if (d->residue >=3D SZ_4M) { - dev_err(uc->ud->dev, - "%s: Transfer size %u is over the supported 4M range\n", - __func__, d->residue); - udma_free_hwdesc(uc, d); - kfree(d); - return NULL; - } - - h_desc =3D d->hwdesc[0].cppi5_desc_vaddr; - cppi5_hdesc_set_pktlen(h_desc, d->residue); - - return d; -} - -static int udma_attach_metadata(struct dma_async_tx_descriptor *desc, - void *data, size_t len) -{ - struct udma_desc *d =3D to_udma_desc(desc); - struct udma_chan *uc =3D to_udma_chan(desc->chan); - struct cppi5_host_desc_t *h_desc; - u32 psd_size =3D len; - u32 flags =3D 0; - - if (!uc->config.pkt_mode || !uc->config.metadata_size) - return -ENOTSUPP; - - if (!data || len > uc->config.metadata_size) - return -EINVAL; - - if (uc->config.needs_epib && len < CPPI5_INFO0_HDESC_EPIB_SIZE) - return -EINVAL; - - h_desc =3D d->hwdesc[0].cppi5_desc_vaddr; - if (d->dir =3D=3D DMA_MEM_TO_DEV) - memcpy(h_desc->epib, data, len); - - if (uc->config.needs_epib) - psd_size -=3D CPPI5_INFO0_HDESC_EPIB_SIZE; - - d->metadata =3D data; - d->metadata_size =3D len; - if (uc->config.needs_epib) - flags |=3D CPPI5_INFO0_HDESC_EPIB_PRESENT; - - cppi5_hdesc_update_flags(h_desc, flags); - cppi5_hdesc_update_psdata_size(h_desc, psd_size); - - return 0; -} - -static void *udma_get_metadata_ptr(struct dma_async_tx_descriptor *desc, - size_t *payload_len, size_t *max_len) -{ - struct udma_desc *d =3D to_udma_desc(desc); - struct udma_chan *uc =3D to_udma_chan(desc->chan); - struct cppi5_host_desc_t *h_desc; - - if (!uc->config.pkt_mode || !uc->config.metadata_size) - return ERR_PTR(-ENOTSUPP); - - h_desc =3D d->hwdesc[0].cppi5_desc_vaddr; - - *max_len =3D uc->config.metadata_size; - - *payload_len =3D cppi5_hdesc_epib_present(&h_desc->hdr) ? - CPPI5_INFO0_HDESC_EPIB_SIZE : 0; - *payload_len +=3D cppi5_hdesc_get_psdata_size(h_desc); - - return h_desc->epib; -} - -static int udma_set_metadata_len(struct dma_async_tx_descriptor *desc, - size_t payload_len) -{ - struct udma_desc *d =3D to_udma_desc(desc); - struct udma_chan *uc =3D to_udma_chan(desc->chan); - struct cppi5_host_desc_t *h_desc; - u32 psd_size =3D payload_len; - u32 flags =3D 0; - - if (!uc->config.pkt_mode || !uc->config.metadata_size) - return -ENOTSUPP; - - if (payload_len > uc->config.metadata_size) - return -EINVAL; - - if (uc->config.needs_epib && payload_len < CPPI5_INFO0_HDESC_EPIB_SIZE) - return -EINVAL; - - h_desc =3D d->hwdesc[0].cppi5_desc_vaddr; - - if (uc->config.needs_epib) { - psd_size -=3D CPPI5_INFO0_HDESC_EPIB_SIZE; - flags |=3D CPPI5_INFO0_HDESC_EPIB_PRESENT; - } - - cppi5_hdesc_update_flags(h_desc, flags); - cppi5_hdesc_update_psdata_size(h_desc, psd_size); - - return 0; -} - -static const struct dma_descriptor_metadata_ops metadata_ops =3D { - .attach =3D udma_attach_metadata, - .get_ptr =3D udma_get_metadata_ptr, - .set_len =3D udma_set_metadata_len, -}; - -static struct dma_async_tx_descriptor * -udma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, - unsigned int sglen, enum dma_transfer_direction dir, - unsigned long tx_flags, void *context) -{ - struct udma_chan *uc =3D to_udma_chan(chan); - enum dma_slave_buswidth dev_width; - struct udma_desc *d; - u32 burst; - - if (dir !=3D uc->config.dir && - (uc->config.dir =3D=3D DMA_MEM_TO_MEM && !uc->config.tr_trigger_type)= ) { - dev_err(chan->device->dev, - "%s: chan%d is for %s, not supporting %s\n", - __func__, uc->id, - dmaengine_get_direction_text(uc->config.dir), - dmaengine_get_direction_text(dir)); - return NULL; - } - - if (dir =3D=3D DMA_DEV_TO_MEM) { - dev_width =3D uc->cfg.src_addr_width; - burst =3D uc->cfg.src_maxburst; - } else if (dir =3D=3D DMA_MEM_TO_DEV) { - dev_width =3D uc->cfg.dst_addr_width; - burst =3D uc->cfg.dst_maxburst; - } else { - dev_err(chan->device->dev, "%s: bad direction?\n", __func__); - return NULL; - } - - if (!burst) - burst =3D 1; - - uc->config.tx_flags =3D tx_flags; - - if (uc->config.pkt_mode) - d =3D udma_prep_slave_sg_pkt(uc, sgl, sglen, dir, tx_flags, - context); - else if (is_slave_direction(uc->config.dir)) - d =3D udma_prep_slave_sg_tr(uc, sgl, sglen, dir, tx_flags, - context); - else - d =3D udma_prep_slave_sg_triggered_tr(uc, sgl, sglen, dir, - tx_flags, context); - - if (!d) - return NULL; - - d->dir =3D dir; - d->desc_idx =3D 0; - d->tr_idx =3D 0; - - /* static TR for remote PDMA */ - if (udma_configure_statictr(uc, d, dev_width, burst)) { - dev_err(uc->ud->dev, - "%s: StaticTR Z is limited to maximum %u (%u)\n", - __func__, uc->ud->match_data->statictr_z_mask, - d->static_tr.bstcnt); - - udma_free_hwdesc(uc, d); - kfree(d); - return NULL; - } - - if (uc->config.metadata_size) - d->vd.tx.metadata_ops =3D &metadata_ops; - - return vchan_tx_prep(&uc->vc, &d->vd, tx_flags); -} - -static struct udma_desc * -udma_prep_dma_cyclic_tr(struct udma_chan *uc, dma_addr_t buf_addr, - size_t buf_len, size_t period_len, - enum dma_transfer_direction dir, unsigned long flags) -{ - struct udma_desc *d; - size_t tr_size, period_addr; - struct cppi5_tr_type1_t *tr_req; - unsigned int periods =3D buf_len / period_len; - u16 tr0_cnt0, tr0_cnt1, tr1_cnt0; - unsigned int i; - int num_tr; - u32 period_csf =3D 0; - - num_tr =3D udma_get_tr_counters(period_len, __ffs(buf_addr), &tr0_cnt0, - &tr0_cnt1, &tr1_cnt0); - if (num_tr < 0) { - dev_err(uc->ud->dev, "size %zu is not supported\n", - period_len); - return NULL; - } - - /* Now allocate and setup the descriptor. */ - tr_size =3D sizeof(struct cppi5_tr_type1_t); - d =3D udma_alloc_tr_desc(uc, tr_size, periods * num_tr, dir); - if (!d) - return NULL; - - tr_req =3D d->hwdesc[0].tr_req_base; - if (uc->ud->match_data->type =3D=3D DMA_TYPE_UDMA) - period_addr =3D buf_addr; - else - period_addr =3D buf_addr | - ((u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT); - - /* - * For BCDMA <-> PDMA transfers, the EOP flag needs to be set on the - * last TR of a descriptor, to mark the packet as complete. - * This is required for getting the teardown completion message in case - * of TX, and to avoid short-packet error in case of RX. - * - * As we are in cyclic mode, we do not know which period might be the - * last one, so set the flag for each period. - */ - if (uc->config.ep_type =3D=3D PSIL_EP_PDMA_XY && - uc->ud->match_data->type =3D=3D DMA_TYPE_BCDMA) { - period_csf =3D CPPI5_TR_CSF_EOP; - } - - for (i =3D 0; i < periods; i++) { - int tr_idx =3D i * num_tr; - - cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false, - false, CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - - tr_req[tr_idx].addr =3D period_addr; - tr_req[tr_idx].icnt0 =3D tr0_cnt0; - tr_req[tr_idx].icnt1 =3D tr0_cnt1; - tr_req[tr_idx].dim1 =3D tr0_cnt0; - - if (num_tr =3D=3D 2) { - cppi5_tr_csf_set(&tr_req[tr_idx].flags, - CPPI5_TR_CSF_SUPR_EVT); - tr_idx++; - - cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, - false, false, - CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - - tr_req[tr_idx].addr =3D period_addr + tr0_cnt1 * tr0_cnt0; - tr_req[tr_idx].icnt0 =3D tr1_cnt0; - tr_req[tr_idx].icnt1 =3D 1; - tr_req[tr_idx].dim1 =3D tr1_cnt0; - } - - if (!(flags & DMA_PREP_INTERRUPT)) - period_csf |=3D CPPI5_TR_CSF_SUPR_EVT; - - if (period_csf) - cppi5_tr_csf_set(&tr_req[tr_idx].flags, period_csf); - - period_addr +=3D period_len; - } - - return d; -} - -static struct udma_desc * -udma_prep_dma_cyclic_pkt(struct udma_chan *uc, dma_addr_t buf_addr, - size_t buf_len, size_t period_len, - enum dma_transfer_direction dir, unsigned long flags) -{ - struct udma_desc *d; - u32 ring_id; - int i; - int periods =3D buf_len / period_len; - - if (periods > (K3_UDMA_DEFAULT_RING_SIZE - 1)) - return NULL; - - if (period_len >=3D SZ_4M) - return NULL; - - d =3D kzalloc_flex(*d, hwdesc, periods, GFP_NOWAIT); - if (!d) - return NULL; - - d->hwdesc_count =3D periods; - - /* TODO: re-check this... */ - if (dir =3D=3D DMA_DEV_TO_MEM) - ring_id =3D k3_ringacc_get_ring_id(uc->rflow->r_ring); - else - ring_id =3D k3_ringacc_get_ring_id(uc->tchan->tc_ring); - - if (uc->ud->match_data->type !=3D DMA_TYPE_UDMA) - buf_addr |=3D (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; - - for (i =3D 0; i < periods; i++) { - struct udma_hwdesc *hwdesc =3D &d->hwdesc[i]; - dma_addr_t period_addr =3D buf_addr + (period_len * i); - struct cppi5_host_desc_t *h_desc; - - hwdesc->cppi5_desc_vaddr =3D dma_pool_zalloc(uc->hdesc_pool, - GFP_NOWAIT, - &hwdesc->cppi5_desc_paddr); - if (!hwdesc->cppi5_desc_vaddr) { - dev_err(uc->ud->dev, - "descriptor%d allocation failed\n", i); - - udma_free_hwdesc(uc, d); - kfree(d); - return NULL; - } - - hwdesc->cppi5_desc_size =3D uc->config.hdesc_size; - h_desc =3D hwdesc->cppi5_desc_vaddr; - - cppi5_hdesc_init(h_desc, 0, 0); - cppi5_hdesc_set_pktlen(h_desc, period_len); - - /* Flow and Packed ID */ - cppi5_desc_set_pktids(&h_desc->hdr, uc->id, - CPPI5_INFO1_DESC_FLOWID_DEFAULT); - cppi5_desc_set_retpolicy(&h_desc->hdr, 0, ring_id); - - /* attach each period to a new descriptor */ - cppi5_hdesc_attach_buf(h_desc, - period_addr, period_len, - period_addr, period_len); - } - - return d; -} - -static struct dma_async_tx_descriptor * -udma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t bu= f_len, - size_t period_len, enum dma_transfer_direction dir, - unsigned long flags) -{ - struct udma_chan *uc =3D to_udma_chan(chan); - enum dma_slave_buswidth dev_width; - struct udma_desc *d; - u32 burst; - - if (dir !=3D uc->config.dir) { - dev_err(chan->device->dev, - "%s: chan%d is for %s, not supporting %s\n", - __func__, uc->id, - dmaengine_get_direction_text(uc->config.dir), - dmaengine_get_direction_text(dir)); - return NULL; - } - - uc->cyclic =3D true; - - if (dir =3D=3D DMA_DEV_TO_MEM) { - dev_width =3D uc->cfg.src_addr_width; - burst =3D uc->cfg.src_maxburst; - } else if (dir =3D=3D DMA_MEM_TO_DEV) { - dev_width =3D uc->cfg.dst_addr_width; - burst =3D uc->cfg.dst_maxburst; - } else { - dev_err(uc->ud->dev, "%s: bad direction?\n", __func__); - return NULL; - } - - if (!burst) - burst =3D 1; - - if (uc->config.pkt_mode) - d =3D udma_prep_dma_cyclic_pkt(uc, buf_addr, buf_len, period_len, - dir, flags); - else - d =3D udma_prep_dma_cyclic_tr(uc, buf_addr, buf_len, period_len, - dir, flags); - - if (!d) - return NULL; - - d->sglen =3D buf_len / period_len; - - d->dir =3D dir; - d->residue =3D buf_len; - - /* static TR for remote PDMA */ - if (udma_configure_statictr(uc, d, dev_width, burst)) { - dev_err(uc->ud->dev, - "%s: StaticTR Z is limited to maximum %u (%u)\n", - __func__, uc->ud->match_data->statictr_z_mask, - d->static_tr.bstcnt); - - udma_free_hwdesc(uc, d); - kfree(d); - return NULL; - } - - if (uc->config.metadata_size) - d->vd.tx.metadata_ops =3D &metadata_ops; - - return vchan_tx_prep(&uc->vc, &d->vd, flags); -} - -static struct dma_async_tx_descriptor * -udma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t sr= c, - size_t len, unsigned long tx_flags) -{ - struct udma_chan *uc =3D to_udma_chan(chan); - struct udma_desc *d; - struct cppi5_tr_type15_t *tr_req; - int num_tr; - size_t tr_size =3D sizeof(struct cppi5_tr_type15_t); - u16 tr0_cnt0, tr0_cnt1, tr1_cnt0; - u32 csf =3D CPPI5_TR_CSF_SUPR_EVT; - - if (uc->config.dir !=3D DMA_MEM_TO_MEM) { - dev_err(chan->device->dev, - "%s: chan%d is for %s, not supporting %s\n", - __func__, uc->id, - dmaengine_get_direction_text(uc->config.dir), - dmaengine_get_direction_text(DMA_MEM_TO_MEM)); - return NULL; - } - - num_tr =3D udma_get_tr_counters(len, __ffs(src | dest), &tr0_cnt0, - &tr0_cnt1, &tr1_cnt0); - if (num_tr < 0) { - dev_err(uc->ud->dev, "size %zu is not supported\n", - len); - return NULL; - } - - d =3D udma_alloc_tr_desc(uc, tr_size, num_tr, DMA_MEM_TO_MEM); - if (!d) - return NULL; - - d->dir =3D DMA_MEM_TO_MEM; - d->desc_idx =3D 0; - d->tr_idx =3D 0; - d->residue =3D len; - - if (uc->ud->match_data->type !=3D DMA_TYPE_UDMA) { - src |=3D (u64)uc->ud->asel << K3_ADDRESS_ASEL_SHIFT; - dest |=3D (u64)uc->ud->asel << K3_ADDRESS_ASEL_SHIFT; - } else { - csf |=3D CPPI5_TR_CSF_EOL_ICNT0; - } - - tr_req =3D d->hwdesc[0].tr_req_base; - - cppi5_tr_init(&tr_req[0].flags, CPPI5_TR_TYPE15, false, true, - CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - cppi5_tr_csf_set(&tr_req[0].flags, csf); - - tr_req[0].addr =3D src; - tr_req[0].icnt0 =3D tr0_cnt0; - tr_req[0].icnt1 =3D tr0_cnt1; - tr_req[0].icnt2 =3D 1; - tr_req[0].icnt3 =3D 1; - tr_req[0].dim1 =3D tr0_cnt0; - - tr_req[0].daddr =3D dest; - tr_req[0].dicnt0 =3D tr0_cnt0; - tr_req[0].dicnt1 =3D tr0_cnt1; - tr_req[0].dicnt2 =3D 1; - tr_req[0].dicnt3 =3D 1; - tr_req[0].ddim1 =3D tr0_cnt0; - - if (num_tr =3D=3D 2) { - cppi5_tr_init(&tr_req[1].flags, CPPI5_TR_TYPE15, false, true, - CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - cppi5_tr_csf_set(&tr_req[1].flags, csf); - - tr_req[1].addr =3D src + tr0_cnt1 * tr0_cnt0; - tr_req[1].icnt0 =3D tr1_cnt0; - tr_req[1].icnt1 =3D 1; - tr_req[1].icnt2 =3D 1; - tr_req[1].icnt3 =3D 1; - - tr_req[1].daddr =3D dest + tr0_cnt1 * tr0_cnt0; - tr_req[1].dicnt0 =3D tr1_cnt0; - tr_req[1].dicnt1 =3D 1; - tr_req[1].dicnt2 =3D 1; - tr_req[1].dicnt3 =3D 1; - } - - cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, csf | CPPI5_TR_CSF_EOP); - - if (uc->config.metadata_size) - d->vd.tx.metadata_ops =3D &metadata_ops; - - return vchan_tx_prep(&uc->vc, &d->vd, tx_flags); -} - static void udma_issue_pending(struct dma_chan *chan) { struct udma_chan *uc =3D to_udma_chan(chan); @@ -3587,46 +2409,6 @@ static void udma_synchronize(struct dma_chan *chan) udma_reset_rings(uc); } =20 -static void udma_desc_pre_callback(struct virt_dma_chan *vc, - struct virt_dma_desc *vd, - struct dmaengine_result *result) -{ - struct udma_chan *uc =3D to_udma_chan(&vc->chan); - struct udma_desc *d; - u8 status; - - if (!vd) - return; - - d =3D to_udma_desc(&vd->tx); - - if (d->metadata_size) - udma_fetch_epib(uc, d); - - if (result) { - void *desc_vaddr =3D udma_curr_cppi5_desc_vaddr(d, d->desc_idx); - - if (cppi5_desc_get_type(desc_vaddr) =3D=3D - CPPI5_INFO0_DESC_TYPE_VAL_HOST) { - /* Provide residue information for the client */ - result->residue =3D d->residue - - cppi5_hdesc_get_pktlen(desc_vaddr); - if (result->residue) - result->result =3D DMA_TRANS_ABORTED; - else - result->result =3D DMA_TRANS_NOERROR; - } else { - result->residue =3D 0; - /* Propagate TR Response errors to the client */ - status =3D d->hwdesc[0].tr_resp_base->status; - if (status) - result->result =3D DMA_TRANS_ABORTED; - else - result->result =3D DMA_TRANS_NOERROR; - } - } -} - /* * This tasklet handles the completion of a DMA descriptor by * calling its callback and freeing it. diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h index 54e1757c3de38..62c15b0cc9ae7 100644 --- a/drivers/dma/ti/k3-udma.h +++ b/drivers/dma/ti/k3-udma.h @@ -560,6 +560,60 @@ static inline void udma_fetch_epib(struct udma_chan *u= c, struct udma_desc *d) memcpy(d->metadata, h_desc->epib, d->metadata_size); } =20 +/* Common functions */ +struct udma_desc *udma_udma_desc_from_paddr(struct udma_chan *uc, + dma_addr_t paddr); +void udma_free_hwdesc(struct udma_chan *uc, struct udma_desc *d); +void udma_purge_desc_work(struct work_struct *work); +void udma_desc_free(struct virt_dma_desc *vd); +bool udma_desc_is_rx_flush(struct udma_chan *uc, dma_addr_t addr); +bool udma_is_desc_really_done(struct udma_chan *uc, struct udma_desc *d); +struct udma_desc *udma_alloc_tr_desc(struct udma_chan *uc, + size_t tr_size, int tr_count, + enum dma_transfer_direction dir); +int udma_get_tr_counters(size_t len, unsigned long align_to, + u16 *tr0_cnt0, u16 *tr0_cnt1, u16 *tr1_cnt0); +struct udma_desc *udma_prep_slave_sg_tr(struct udma_chan *uc, + struct scatterlist *sgl, unsigned int sglen, + enum dma_transfer_direction dir, + unsigned long tx_flags, void *context); +struct udma_desc *udma_prep_slave_sg_triggered_tr(struct udma_chan *uc, + struct scatterlist *sgl, unsigned int sglen, + enum dma_transfer_direction dir, + unsigned long tx_flags, void *context); +int udma_configure_statictr(struct udma_chan *uc, struct udma_desc *d, + enum dma_slave_buswidth dev_width, u16 elcnt); +struct udma_desc *udma_prep_slave_sg_pkt(struct udma_chan *uc, + struct scatterlist *sgl, unsigned int sglen, + enum dma_transfer_direction dir, + unsigned long tx_flags, void *context); +int udma_attach_metadata(struct dma_async_tx_descriptor *desc, + void *data, size_t len); +void *udma_get_metadata_ptr(struct dma_async_tx_descriptor *desc, + size_t *payload_len, size_t *max_len); +int udma_set_metadata_len(struct dma_async_tx_descriptor *desc, + size_t payload_len); +struct dma_async_tx_descriptor *udma_prep_slave_sg(struct dma_chan *chan, + struct scatterlist *sgl, unsigned int sglen, + enum dma_transfer_direction dir, + unsigned long tx_flags, void *context); +struct udma_desc *udma_prep_dma_cyclic_tr(struct udma_chan *uc, + dma_addr_t buf_addr, size_t buf_len, size_t period_len, + enum dma_transfer_direction dir, unsigned long flags); +struct udma_desc *udma_prep_dma_cyclic_pkt(struct udma_chan *uc, + dma_addr_t buf_addr, size_t buf_len, size_t period_len, + enum dma_transfer_direction dir, unsigned long flags); +struct dma_async_tx_descriptor *udma_prep_dma_cyclic(struct dma_chan *chan= , dma_addr_t buf_addr, + size_t buf_len, size_t period_len, + enum dma_transfer_direction dir, + unsigned long flags); +struct dma_async_tx_descriptor *udma_prep_dma_memcpy(struct dma_chan *chan, + dma_addr_t dest, dma_addr_t src, + size_t len, unsigned long tx_flags); +void udma_desc_pre_callback(struct virt_dma_chan *vc, + struct virt_dma_desc *vd, + struct dmaengine_result *result); + /* Direct access to UDMA low lever resources for the glue layer */ int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thr= ead); int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread, --=20 2.54.0 From nobody Tue Sep 29 08:26:17 2026 Received: from mx0a-0002e601.pphosted.com (mx0a-0002e601.pphosted.com [148.163.150.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28802374183; Mon, 28 Sep 2026 02:59:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.150.75 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564355; cv=fail; b=R0FkDEwCtlwFZPVtPuAiOT2aC18RGz7DkfFbQwP4pS/am9F7dICTdxe2U6CD2xI88nUCTW1str7w4oiuQt+xU/VZM5KVDMXZkBz4k+TBRha3wkdYTPTZ6cRNF0/YDsXo1ALfmUWpirqDE2RnGmA5uxISLspheXcInI/PhGfy1Hc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564355; c=relaxed/simple; bh=dD/rsHsFBpjNGtyELuHpnh2tpYV+yShZHEqC8bX3qLo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=H6TNz2JmxFPBiyzisIfiIYou+8GpVb6D9etQWUFiNA8rOzmPD5v4ZitUiKbT7KKCAhTsXcZJYJIDiylL9CMophRVJE6o3TnIFxKyZ1sWsjw7woQKh8dMhgL3THRwjku7pFL90qSy2e6nt879PKOqKlh7B2+vVZZdOq9xGN1gkqo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=o4XyIIzm; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=tGx3rPSo; arc=fail smtp.client-ip=148.163.150.75 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="o4XyIIzm"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="tGx3rPSo" Received: from pps.filterd (m0380145.ppops.net [127.0.0.1]) by m0380145.ppops.net (8.18.1.11/8.18.1.11) with ESMTP id 68S0miwF3149516; Sun, 27 Sep 2026 21:59:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=wnd7uUCK8Gj6RW+b9cimF4nYF7gX+Lhr0xbdaWpzZ Kw=; b=o4XyIIzmBQ4/rMv5H3bkK1DSL463uCEAbVlDgN9eTAzC/5fFLAEYY5mHP qwY08RrfURekJYyH1x/ulrY45cdC7Vr1nBy+yh3rD6Uott81cZWcDx5y7smFfpbY Xq+NcRo3KkIGvtb/2w1jEgrTuzgPE954vfxzuFR1Dc8ftPE3O7fbcO7WPMXoz8Ae u2cPvwe2xDl4wMUkyGgY2nP0TA0480G3Gn/U8Kjw+FhUh305atY8PyPWnsdRGF1D IxwkyN56MyIqu8QS8Os6EYlVaV6/rGSz9wkb0HVbv6KA9pYgfgSVgK8tdunZ00Fa Gln4xPZgpt3g26SGBBBJ9HNv57JpA== Received: from cy3pr05cu001.outbound.protection.outlook.com (mail-westcentralusazon11013042.outbound.protection.outlook.com [40.93.201.42]) by m0380145.ppops.net (PPS) with ESMTPS id 4gxy2nk6ee-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Sun, 27 Sep 2026 21:59:06 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Q4q42r1P/yq6xfhfgk+NqHLAI6nXXg2EXa9uYMZGTCik7KeTFJeaNFZXet1gdaTCqsi3rPzrtBYlykh64nq5e5eHYCz/g1y9EGyGD4TcvcQHcITPmR7uYdCPekkltyoLkBcurRVlUjvEufXFu95z+rpQSeRqs+0Z4fLwypTR3kshMRc0lu58BpNfXPrdOHOdw0kIqBtUQOd8R47TGASWghZJQaCJsk2fdqpRIlDE71ka/jGeq6Fh26AS0X7folRUy6xoIcCuPzn4sfztlL5YKArDaGYblPmXLWk6oMacoF1F9yr4GsJqSBew5SWpdAfoTbE7a2+9mscnvlqgd1TgHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=wnd7uUCK8Gj6RW+b9cimF4nYF7gX+Lhr0xbdaWpzZKw=; b=YRCLtubbriMTA465xGpcZzluL4v5/HU4NTgSnAGIsJaPfSUTV6S0teZ/FUYP7/e95K4342GtYHePVo9R4MqtX62uWK5OTZCoFUCLhcuMbiXKAnsw66ZCSKCWNoHsQG5/lSQpUmDkIT+o2ZGEBkZq1Cw6MBS+uOvOTGJeb+Eph0G0Go7+VmJyQ52MUYg5hnmeVeBwTUtoC5Xu9Hj302DEs3T3qop0kfyRajQtN48ZNvYk6rd79FAbSupFqrQcLFPql1y70684zgbE2Rqgz6aT2UxzVK2QxJj7ShGMdr5kM5T6QBbkXAhr6wn8k+TaA/lJk/bxMaWGtUbrtEcBviQ++w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.21.195) smtp.rcpttodomain=nxp.com smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=wnd7uUCK8Gj6RW+b9cimF4nYF7gX+Lhr0xbdaWpzZKw=; b=tGx3rPSohetGVvkjHMKJC3942qb0GQuJUIGDXjA+ZvP5G2ldGEYdymu9w/eM1lvy05F1j9QDDbk2NZ+EV07awJK4Uv9qPDA85XdWf0Ou/pHbCWP+1WDTrr4iCMkw56IpPJW5hw02VzXrgh1HmEuZaJevmpTRuWg0fzj9usf6RpQ= Received: from SJ0PR03CA0109.namprd03.prod.outlook.com (2603:10b6:a03:333::24) by DS0PR10MB8101.namprd10.prod.outlook.com (2603:10b6:8:203::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.451.18; Mon, 28 Sep 2026 02:59:02 +0000 Received: from SJ1PEPF000023D0.namprd02.prod.outlook.com (2603:10b6:a03:333:cafe::86) by SJ0PR03CA0109.outlook.office365.com (2603:10b6:a03:333::24) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.428.11 via Frontend Transport; Mon, 28 Sep 2026 02:59:02 +0000 X-MS-Exchange-Authentication-Results: mx.microsoft.com 1; spf=pass (sender IP is 198.47.21.195) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.21.195 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.21.195; helo=flwvzet201.ext.ti.com; pr=C Received: from flwvzet201.ext.ti.com (198.47.21.195) by SJ1PEPF000023D0.mail.protection.outlook.com (10.167.244.4) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Mon, 28 Sep 2026 02:59:00 +0000 Received: from DFLE209.ent.ti.com (10.64.6.67) by flwvzet201.ext.ti.com (10.248.192.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:26 -0500 Received: from DFLE202.ent.ti.com (10.64.6.60) by DFLE209.ent.ti.com (10.64.6.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:26 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE202.ent.ti.com (10.64.6.60) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45 via Frontend Transport; Sun, 27 Sep 2026 21:58:26 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [10.24.51.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 68S2vqqD2256662; Sun, 27 Sep 2026 21:58:21 -0500 From: Sai Sree Kartheek Adivi To: , , , , , , , , , , , , , CC: , Subject: [PATCH v10 06/19] dmaengine: ti: k3-udma: move ring management functions to k3-udma-common.c Date: Mon, 28 Sep 2026 08:26:12 +0530 Message-ID: <20260928025749.1055383-7-s-adivi@ti.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260928025749.1055383-1-s-adivi@ti.com> References: <20260928025749.1055383-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D0:EE_|DS0PR10MB8101:EE_ X-MS-Office365-Filtering-Correlation-Id: de451366-05b5-4cc2-de1f-08df1d0c72a1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|23010399003|36860700016|921020|6133799003|3023799007|10067099003|56012099006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: 4QaFodbeJJtP/uke7N779UOcGJD4tZ0pT77MIhpUZqer9bx0+3VcQ9Q73a29E7GHQegxN4yNOosh4C8Xc5wEVuyBGHU+n4vbqUo5sGh4grWeG48wwyUkyP/5oE6itmadgxB8nUO0dyfATHaZXByOtpaVRPCl9d7S9PXjZ7zA1dss1sSkzloDNOAkbKeANgDlPGpqUT70lMKY006shasku/4FcRb43JhyfnMsByBA3XcfYB6szDfVlax4G+oY4BDHt8TWPoeygXc+ERIWMHjtF7UBdT6YtF7wOyKBIuK+wpRkBbkOrv+zaNiRlzSVHkL4eDk12h4LeAfwiB1x+SU3amM//Tek3a2tDJB8aXM7hN4wP1DV9s8qKgqfBFY3geerYF2HHU/3IVOchznUehOguoxvb9v/zkUsiravNFrpEdeR5ZGDBfnHdGxGetdXC+jxzey32fx1lonTtAteugsQLUhpxLpoV0aHB9YaEfJbB/uyw9B3aXkiWQc0RVutxXVnDin0v1eRcvfcrZagoNp8VcDfthlJn1q9yWxLmZzmgUSsbPyngKrk2vzyFnEESbPrcXrkavI6x+eovTuTef4f6CaTyq4SE0s0t/FAfdPY5QLvcK+5fkUedCtcnK0rQpdkI5i/fO79jJvEmGsSg/KzJ1d4kewsNOIfMOxYG6A7gf4PteVvnz0t2GmwGv+aI55ZEjYPOgYYpEVSxv/vrOK0L1xCVVbupuPFc8XoyoaWZ+TfpBwhv8wXb12uUB05NQav X-Forefront-Antispam-Report: CIP:198.47.21.195;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:flwvzet201.ext.ti.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(82310400026)(23010399003)(36860700016)(921020)(6133799003)(3023799007)(10067099003)(56012099006)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: K41AwO9A/WfsaiUKihWfF6Wv37jq5EpEjhVy8t2uQjwfgbFiW5wTsYidPhvTjGOf5DgSSMfMIVuaN7S1s7gx7AdDprXrc/1Kjaez3nXhIq86RfsqfMxjpf12D5fe0uHWnyFwZrrCZjsugUtMunR5sdK/TsLou08cwWR89tDW2uD2CyVNll612Yv8RWrrEL0yb0DHQO46G2IR2inSfQXV1IRGkttu5K9tn74welmgNPu3tG2Fq+PW9Hwl/UGW4Rb6eRhMQ3hFUlvX7MR7sMcda8SHTpQxFLf6Z8G9WdTzGJblfogFOveijX3rg8Wu9Dzal1PhzsQ4Rr3/LkLomMOPArz4+2jSj42BMtlVtOH/KfBf29kka9S3HqKsN+RvlKsDlRWPSKrrEyXVIyYTMYQuaDfXkzEx5dJcX8NB7mp8r+l9WcslZ4yd3ZPeRsQiOf60 X-Exchange-RoutingPolicyChecked: gSyZvIERfbjQtyjfBRIS8aQMnHcd1wO9SCbtIpflbVsuDfSOo6R5yU6kAIqGrPR22N01zbDuyi0qLqQimybpPwM/m80WvcPf1sQKQxBpx5pySNywO/jL35wQxZIuXfTfqeeFHGi9iBSoyFCFp8/j/z98MtL9mvWa3BgIz8yGlJvnnFg34alLq8Om6MePObY/uOzvCwQOuQfjvJjV0s9Ktr9tfWAyrVtECiQTiQD2y7xNsH5jb1jTY1mPgg8Ht7iV0IDVpcd3A+mtRdyyLIje80TQoJ55ywnR9s7iYWCpOacnCB8cljSwBBYRylCkozD9WiTp2b8+NYkDBVbk45CQvg== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 02:59:00.8579 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: de451366-05b5-4cc2-de1f-08df1d0c72a1 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D0.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR10MB8101 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX+Zua9XqQkxcz BkmikMFgwniA6pg84RUf6p66AslIC8QB5fRAZo4bBuxllyGigmpmPRQIS7vxt1OcuwxZCLKhB5N 2fErFQTiR/Z5VVPcr9BTWDFPVcev5Xw= X-Proofpoint-ORIG-GUID: s3kYZ3mv8wMP4hqJghbxEGLAjhe0BkQt X-Authority-Analysis: v=2.4 cv=RLgmjIi+ c=1 sm=1 tr=0 ts=6ab9d7fa cx=c_pps a=Xv5HOu5WSFZfuBAuS1yumw==:117 a=tJyPKKxUohctrY4NYmUjkA==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=VdqzKS8jKosA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=gO1vWkAQAl3rybz1DQOp:22 a=8AirrxEcAAAA:8 a=sozttTNsAAAA:8 a=g6TaX78G5PB857Cctd4A:9 a=ST-jHhOKWsTCqRlWije3:22 X-Proofpoint-GUID: s3kYZ3mv8wMP4hqJghbxEGLAjhe0BkQt X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX9X4YOs0t1oKx NAlk6ejpUEUXqVhbzmXj1bYtNi8vSphDW3NRDhRKVIwbiFigOLhukzTccXK5dm6cB6Ga3/pXqjV dfE/x91xgsJ8itadwCIaEpZ5fVTBJEWSWN+G8hQ9u/M9wYRSwsiyjw9FI9DuTEYKNw5GD3JJEJx 9PQjQM7P85Dz112eeJK2uZygjqkqflhWB878waeR8lmLGn7Jiry49CIc94nK7MjLexnDMQKDXzY VVpPqRheh02ZBLZNgnhx6b+LSYkzW2B1wn6q7OZC2jMUM81ZO0vEKHRMh2hOw0/TNzdBRp1XDgX T5IZRO2rp0U9LOuybj0Xjd2xo/vFgwYJBHIs1c/57TabVzPmbfoiPls6EHY/PLx+Cw/x++o/YY9 spyXQFX8uIoJQ9zLerI3VK91ZzZP1YT/CBu/2tU/z7lk5lZZnfTnSoucigXWk82BqDHUBfQn72Q EeWJNtTxlfOimQDSsCw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 malwarescore=0 adultscore=0 suspectscore=0 clxscore=1015 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280011 Content-Type: text/plain; charset="utf-8" Relocate the ring management functions such as push, pop, and reset from k3-udma.c to k3-udma-common.c file. These operations are common across multiple K3 UDMA variants and will be reused by future implementations like K3 UDMA v2. No functional changes intended. Reviewed-by: Frank Li Signed-off-by: Sai Sree Kartheek Adivi --- drivers/dma/ti/k3-udma-common.c | 103 ++++++++++++++++++++++++++++++++ drivers/dma/ti/k3-udma.c | 100 ------------------------------- drivers/dma/ti/k3-udma.h | 4 ++ 3 files changed, 107 insertions(+), 100 deletions(-) diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-commo= n.c index 3130805a8ec40..3ec5cc932280c 100644 --- a/drivers/dma/ti/k3-udma-common.c +++ b/drivers/dma/ti/k3-udma-common.c @@ -1239,5 +1239,108 @@ void udma_desc_pre_callback(struct virt_dma_chan *v= c, } EXPORT_SYMBOL_GPL(udma_desc_pre_callback); =20 +int udma_push_to_ring(struct udma_chan *uc, int idx) +{ + struct udma_desc *d =3D uc->desc; + struct k3_ring *ring =3D NULL; + dma_addr_t paddr; + + switch (uc->config.dir) { + case DMA_DEV_TO_MEM: + ring =3D uc->rflow->fd_ring; + break; + case DMA_MEM_TO_DEV: + case DMA_MEM_TO_MEM: + ring =3D uc->tchan->t_ring; + break; + default: + return -EINVAL; + } + + /* RX flush packet: idx =3D=3D -1 is only passed in case of DEV_TO_MEM */ + if (idx =3D=3D -1) { + paddr =3D udma_get_rx_flush_hwdesc_paddr(uc); + } else { + paddr =3D udma_curr_cppi5_desc_paddr(d, idx); + + wmb(); /* Ensure that writes are not moved over this point */ + } + + return k3_ringacc_ring_push(ring, &paddr); +} +EXPORT_SYMBOL_GPL(udma_push_to_ring); + +int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr) +{ + struct k3_ring *ring =3D NULL; + int ret; + + switch (uc->config.dir) { + case DMA_DEV_TO_MEM: + ring =3D uc->rflow->r_ring; + break; + case DMA_MEM_TO_DEV: + case DMA_MEM_TO_MEM: + ring =3D uc->tchan->tc_ring; + break; + default: + return -ENOENT; + } + + ret =3D k3_ringacc_ring_pop(ring, addr); + if (ret) + return ret; + + rmb(); /* Ensure that reads are not moved before this point */ + + /* Teardown completion */ + if (cppi5_desc_is_tdcm(*addr)) + return 0; + + /* Check for flush descriptor */ + if (udma_desc_is_rx_flush(uc, *addr)) + return -ENOENT; + + return 0; +} +EXPORT_SYMBOL_GPL(udma_pop_from_ring); + +void udma_reset_rings(struct udma_chan *uc) +{ + struct k3_ring *ring1 =3D NULL; + struct k3_ring *ring2 =3D NULL; + + switch (uc->config.dir) { + case DMA_DEV_TO_MEM: + if (uc->rchan) { + ring1 =3D uc->rflow->fd_ring; + ring2 =3D uc->rflow->r_ring; + } + break; + case DMA_MEM_TO_DEV: + case DMA_MEM_TO_MEM: + if (uc->tchan) { + ring1 =3D uc->tchan->t_ring; + ring2 =3D uc->tchan->tc_ring; + } + break; + default: + break; + } + + if (ring1) + k3_ringacc_ring_reset_dma(ring1, + k3_ringacc_ring_get_occ(ring1)); + if (ring2) + k3_ringacc_ring_reset(ring2); + + /* make sure we are not leaking memory by stalled descriptor */ + if (uc->terminated_desc) { + udma_desc_free(&uc->terminated_desc->vd); + uc->terminated_desc =3D NULL; + } +} +EXPORT_SYMBOL_GPL(udma_reset_rings); + MODULE_DESCRIPTION("Texas Instruments K3 UDMA Common Library"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index a8fe919f307f6..6a731fcfc0697 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -174,106 +174,6 @@ static bool udma_is_chan_paused(struct udma_chan *uc) return false; } =20 -static int udma_push_to_ring(struct udma_chan *uc, int idx) -{ - struct udma_desc *d =3D uc->desc; - struct k3_ring *ring =3D NULL; - dma_addr_t paddr; - - switch (uc->config.dir) { - case DMA_DEV_TO_MEM: - ring =3D uc->rflow->fd_ring; - break; - case DMA_MEM_TO_DEV: - case DMA_MEM_TO_MEM: - ring =3D uc->tchan->t_ring; - break; - default: - return -EINVAL; - } - - /* RX flush packet: idx =3D=3D -1 is only passed in case of DEV_TO_MEM */ - if (idx =3D=3D -1) { - paddr =3D udma_get_rx_flush_hwdesc_paddr(uc); - } else { - paddr =3D udma_curr_cppi5_desc_paddr(d, idx); - - wmb(); /* Ensure that writes are not moved over this point */ - } - - return k3_ringacc_ring_push(ring, &paddr); -} - -static int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr) -{ - struct k3_ring *ring =3D NULL; - int ret; - - switch (uc->config.dir) { - case DMA_DEV_TO_MEM: - ring =3D uc->rflow->r_ring; - break; - case DMA_MEM_TO_DEV: - case DMA_MEM_TO_MEM: - ring =3D uc->tchan->tc_ring; - break; - default: - return -ENOENT; - } - - ret =3D k3_ringacc_ring_pop(ring, addr); - if (ret) - return ret; - - rmb(); /* Ensure that reads are not moved before this point */ - - /* Teardown completion */ - if (cppi5_desc_is_tdcm(*addr)) - return 0; - - /* Check for flush descriptor */ - if (udma_desc_is_rx_flush(uc, *addr)) - return -ENOENT; - - return 0; -} - -static void udma_reset_rings(struct udma_chan *uc) -{ - struct k3_ring *ring1 =3D NULL; - struct k3_ring *ring2 =3D NULL; - - switch (uc->config.dir) { - case DMA_DEV_TO_MEM: - if (uc->rchan) { - ring1 =3D uc->rflow->fd_ring; - ring2 =3D uc->rflow->r_ring; - } - break; - case DMA_MEM_TO_DEV: - case DMA_MEM_TO_MEM: - if (uc->tchan) { - ring1 =3D uc->tchan->t_ring; - ring2 =3D uc->tchan->tc_ring; - } - break; - default: - break; - } - - if (ring1) - k3_ringacc_ring_reset_dma(ring1, - k3_ringacc_ring_get_occ(ring1)); - if (ring2) - k3_ringacc_ring_reset(ring2); - - /* make sure we are not leaking memory by stalled descriptor */ - if (uc->terminated_desc) { - udma_desc_free(&uc->terminated_desc->vd); - uc->terminated_desc =3D NULL; - } -} - static void udma_decrement_byte_counters(struct udma_chan *uc, u32 val) { if (uc->desc->dir =3D=3D DMA_DEV_TO_MEM) { diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h index 62c15b0cc9ae7..767b73021390d 100644 --- a/drivers/dma/ti/k3-udma.h +++ b/drivers/dma/ti/k3-udma.h @@ -614,6 +614,10 @@ void udma_desc_pre_callback(struct virt_dma_chan *vc, struct virt_dma_desc *vd, struct dmaengine_result *result); =20 +int udma_push_to_ring(struct udma_chan *uc, int idx); +int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr); +void udma_reset_rings(struct udma_chan *uc); + /* Direct access to UDMA low lever resources for the glue layer */ int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thr= ead); int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread, --=20 2.54.0 From nobody Tue Sep 29 08:26:17 2026 Received: from mx0b-0002e601.pphosted.com (mx0b-0002e601.pphosted.com [148.163.154.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0A9D36DA1A; Mon, 28 Sep 2026 02:59:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.154.28 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564344; cv=fail; b=eayLPqDS7ip5maUbf24kq3mY6539tI4uajUVFVPUD6NtJbzRMC5updckSbFKbgYvVIaYdvkXUfbOO4rorpsTfqAy2NwKGdFdhy6U0vK3WmiGBbe6V95u1cRiRD7ikWvRFJ3bqUUjp0PaOJn3pzVAmt/kUBwoqHbXniTSjruQyx0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564344; c=relaxed/simple; bh=RW+PqzSQ5WvJoIsZ7JEixWn8SAb1EUozaq6kISlvTK4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HToLPiZGGrVKDaAW+JSqTPerDSwnefv7clxi85eV8ic34ludWfKUZ8TBhT+aXEHClxetvsy0NcFaO8eqBI2nqsErupG84+j8IRZedptGIBazbry4sKpdjpJ0muq9mnvaU9b6sHR/lvQE9ujLoW+E644Q/AwJ6BQlOEBJMFLNBbg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=T9l3ZZMC; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=u7lE9WQR; arc=fail smtp.client-ip=148.163.154.28 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="T9l3ZZMC"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="u7lE9WQR" Received: from pps.filterd (m0374955.ppops.net [127.0.0.1]) by mx0b-0002e601.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68RKXZrw2806195; Sun, 27 Sep 2026 21:58:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=KrULaVwgCCElip4aRKBYaZURAqN1+fYOie+cnf4tK eI=; b=T9l3ZZMCOrgArwkC26BmRS+MK54uqm6PcOxqntzI1rNHHbas7V5TNJwvO yBWSgdH4730865lqqGWQQiZXWd9Q8YOHpIUe4cj6wfEkb3mPFVclm0ER0ePYlvSH Cg+Lrh1+pFO7yO8+RQupRAl7dmkT6VRtI5Ix69kTuyEPVCG1+14kyeTvsfpizbP/ K3r/Llxlc+rzF574GQvoqHdVUrca/Dw5OHz1mhjJuVYyXpaRVTx3GPGMTEEjWZlV 9wCEWx6OsrzVfwISev7mRUO0lrWzWFmHTLd4qsIib4yiC3JVNlq3XrWjZ2SXd0ii cOHBkzz/gDLiDJsn7tSitnjkKV4CQ== Received: from sa9pr02cu001.outbound.protection.outlook.com (mail-southcentralusazon11013006.outbound.protection.outlook.com [40.93.196.6]) by mx0b-0002e601.pphosted.com (PPS) with ESMTPS id 4gxwe5kfps-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Sun, 27 Sep 2026 21:58:53 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=G1AFUtYgBxKmYEhLZUGvRwA/qKTczKJTg0u4CgdAvILXkVY2GQFqfPaajY+RwVWHcUuya4euSg+TrhDiM31UPdhgdQWGZg/0Ggh/VYV2kQMMAir3se4Hba/0dH9vnzhs0enaO7iNIPpTXNugwInatJMikyPJX8tdmd1Ym5spV4ovntO8/5/MM9KGXAyDZRqYFBqavU4Bmbrg+0//OGn8CBQdoLEA44UIoYq0BHF+JWJuWcMYXHZc71hMymlqb/e9iW7a9pDCaELueJx3kXdFikRoV3ND3IQwKm2HD1CJ79/efOLABXxPRhrshn7gij4I0YBsu4jexBDwqYF/wdTrzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=KrULaVwgCCElip4aRKBYaZURAqN1+fYOie+cnf4tKeI=; b=TDqKcKB0FmNTQOS2ILjR6Xv0Pp7Qya6cYunW5M0Syo//sgUrEQ4llGWoVX7E9tg7iY5+qubX8/hsMhcvuf1j88uFSieCSQS86q4Ua9La1uPjVgiC0ZNzGSx9McmLKKbQ97k4iloGkcsLL6LS98l3myxDgRelqwy0x4hUE3/jevUz7XkGmLmEp977DMm7HIpjsGkISGnLZic8T8lsr5wCpWDWMdbF+FzT21k/3Oe3w2Xze8a8rQSpTleEuPvCqgz6hgiNuM9GTRAJzS63sgog7ZG64yK9QKY51BxEgMxMCPZF2MV7aPjNffkilTqnAy+9ka1iroqFnuavWoweLTjffA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.23.194) smtp.rcpttodomain=nxp.com smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=KrULaVwgCCElip4aRKBYaZURAqN1+fYOie+cnf4tKeI=; b=u7lE9WQRQeC8QWIYR3SnZkNHJSkT7Vl7yO77svjE76DLQVIqbw+e0b/EtAqcTKxBOMN3QuKhJgMmjJR79dRiS4uYQA6pcp/WBl4QHfeF01mChp7f8mrmwCMSmQM/p3XYkxf2pa1yHiE54BuGUletHWqmxecszjybsNVwXnh/rkY= Received: from CH0PR03CA0303.namprd03.prod.outlook.com (2603:10b6:610:118::16) by DM3PPFEDD6F73B8.namprd10.prod.outlook.com (2603:10b6:f:fc00::c56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.451.19; Mon, 28 Sep 2026 02:58:49 +0000 Received: from CH2PEPF00000146.namprd02.prod.outlook.com (2603:10b6:610:118:cafe::1a) by CH0PR03CA0303.outlook.office365.com (2603:10b6:610:118::16) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.451.23 via Frontend Transport; Mon, 28 Sep 2026 02:58:48 +0000 X-MS-Exchange-Authentication-Results: mx.microsoft.com 1; spf=pass (sender IP is 198.47.23.194) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.23.194 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.23.194; helo=lewvzet200.ext.ti.com; pr=C Received: from lewvzet200.ext.ti.com (198.47.23.194) by CH2PEPF00000146.mail.protection.outlook.com (10.167.244.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Mon, 28 Sep 2026 02:58:48 +0000 Received: from DLEE202.ent.ti.com (157.170.170.77) by lewvzet200.ext.ti.com (10.4.14.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:31 -0500 Received: from DLEE202.ent.ti.com (157.170.170.77) by DLEE202.ent.ti.com (157.170.170.77) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:30 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE202.ent.ti.com (157.170.170.77) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45 via Frontend Transport; Sun, 27 Sep 2026 21:58:30 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [10.24.51.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 68S2vqqE2256662; Sun, 27 Sep 2026 21:58:26 -0500 From: Sai Sree Kartheek Adivi To: , , , , , , , , , , , , , CC: , Subject: [PATCH v10 07/19] dmaengine: ti: k3-udma: Add variant-specific function pointers to udma_dev Date: Mon, 28 Sep 2026 08:26:13 +0530 Message-ID: <20260928025749.1055383-8-s-adivi@ti.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260928025749.1055383-1-s-adivi@ti.com> References: <20260928025749.1055383-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000146:EE_|DM3PPFEDD6F73B8:EE_ X-MS-Office365-Filtering-Correlation-Id: 1b2f2c86-ae28-4372-3e9d-08df1d0c6b7b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|23010399003|376014|7416014|82310400026|1800799024|921020|10067099003|56012099006|22082099003|18002099003|6133799003; X-Microsoft-Antispam-Message-Info: +fUpNQ/20DSVIJ/NLC/olWKRWDZenYm3YZmnMTGEoY77zf8XL6OWkkmxC32/cu8Hl4+1zMfBPav/2ZZmL7nqIhBwjEOf53rTCzUiyv9+TyMLecp7BvniuV+RpASyDWpYzoHDWS6OaQfiwCHW+klUH+6j3XovQmmgo6g9DNVJ2wFtUbHeIN9cMANr3DSSQ2N/4Pduz58OHSTqKxYjdkH1YnituNbdd8ZUtuYfL5zXQpGCY4P64Ig35Kufz39Z33JTk6ay1MnlluTmD4ykeJ6ix0H3by/HQ1fXbcjVD/8bDN2w4hBKMj/hk1q5lNc1y5ZUKppQH66W3pdns2RVfQHgswmQRyJ9vF9uqwcKzmUwgr9LlkZ5ufHztsoCz7/uV20saIKImyF0TlL9piS4Z5wJhO8sy/L+kZlaCx7g+EHpEoZC4btCYIuCa9d6nMPmnr/FrshAr99mi5NVHIzqNSegcvkZ6h9jUV88WEGgy6vcF+Ue0WHz5gA7Z1cj0xgF8O2QMxV48+K0bugqL7UQ/GMWPrAZGrlYMhIpS+zOGAcLvlzQoXz/ewo9kXG/ZgCjO3WdJK+k+rVnKTpxpVBNgw3eoxmeSsMe1P2cRioqGj2tE+JYXDWUmBw9CmuQPcLF3PuLSCJXCL6kWn6HDWw1wX12HYP0dZDRjPFyuxKGumGPzjnYqcd/uoYHqrXL2Vp8QCB/4vurnM5/3qobwb0L/N6J5Ote4j3JnBrTb3xrQr836q+J3idGzJkAGvCEoTWbhGxJ X-Forefront-Antispam-Report: CIP:198.47.23.194;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:lewvzet200.ext.ti.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(23010399003)(376014)(7416014)(82310400026)(1800799024)(921020)(10067099003)(56012099006)(22082099003)(18002099003)(6133799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: lfVOFXORyjvj+kdLvB7GOkspi313lVKryCO7oPjhT5821sQFn3BBMjEH6fqXDD+ay36UmRoNd4XyGTaQODTL+4KgjZElhlLFJNuBPVnrNtfGxzNpQitcH8eqk01EMbFnxX744cDbV9EXdsGp54THoVcdddooi4NggECJwjGczEmTkVzGN/3agM7EpcFSwmTZlBvOxUo9SGnumJOktcwtF/fm91IJILrROU/enCAVMhq5zrItMEh1Yasthtc5KdUDZThISQlEN8TPnZbmWkEEQj/PDybwLtrE9kZzEE7IbdUUy3SJQM8qtAi9+bavq3MrCKwcw9DwifeuZNinfHKJh3+HFO/gEi/IZqsvgrRAiZN+z91S4IQeXj1BF9E7PFu50HVaTPwuQ33ez3KrY4y2pdsNpOB6xg5lsPQTV0ofBiuIV405OABjk8I83ouezCm9 X-Exchange-RoutingPolicyChecked: gfbdch/qre2n+ccjte8avSHQzBImzM7myJ3DXhNqpK1b1MsrLyVxFoD4c6r1NaBK0LjiFzI0CDjfR1SS9Vbh3w5DZOe03V0jbg/sjbTVJAHRLddZs76oMpwB1Flhg/+dO+WwOcncjoSS3Fz7C6sUyMEWKz+swTeuGsMq/1xqknr+Yx+Go/j+rZ196nsa2jt6iQ/atbJWNpqHrB6Dlu+oFgRZZWtkUIRz6OpMX9NIc51DLBZSwR/yoN1T0k4Tp6VvXHDBG1YIjWHMzMWTMKCqXtZ7tF5B5BCKWW221VbqK5uHQzraRndIsB6QlYeyexR3ROU7osAoW4rBlD0vsWfjBw== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 02:58:48.8929 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1b2f2c86-ae28-4372-3e9d-08df1d0c6b7b X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.194];Helo=[lewvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000146.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PPFEDD6F73B8 X-Authority-Analysis: v=2.4 cv=aeP0Dhot c=1 sm=1 tr=0 ts=6ab9d7ee cx=c_pps a=oxxrQmGkUFFO/gDwv9AvRA==:117 a=WotqVVQAdb04rnGuttW3Kw==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=VdqzKS8jKosA:10 a=s63m1ICgrNkA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=fPAWb5peG099m5CrUpKH:22 a=8AirrxEcAAAA:8 a=sozttTNsAAAA:8 a=G_UKfOQgHLmTBcQ1_a4A:9 a=ST-jHhOKWsTCqRlWije3:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX3hxtd9z1CUDX Y/b+ioljFxEruwChBbEmBsgbFf/5clHxs09P3OneAEgEmLK/VjDXoRiUZ7O61+wG1tB7kb/J0X7 d090EgPAf6zBPSzXpaDRew9m4t0LZY5U1doC3F3J6gwnLdG/TataxfEKLYi89L3RboGV50G7xuk VpP3SOODPLyVLYXRwFZvVbojaeo88jJOjhHtOl5PgJ5+asCEVKi+n37xQOlRdFZnDfjb1P+/YLv pNuGToqUXAXxQvo2rQqJ6pTbgixFZoZkr2ZipkhQ7KTTa876bbok0Abo30PBOU4F/u/6mFo5Muv 3Qm9xYbp4uE/npgPryN6ayTJbgYwy6i4qpGC0PoIg5zg4fIy/nTaS6Kje9/J27u5WwXabr625w6 jyM14g5tHNITtsBEJuqpTJSkGaf4+Q+2iqXRmMn4uvGMMo/zs7jlXaKiXeVYDCvHFUiaPFl2PPj LlXQMTNgO8RSpo8m7Iw== X-Proofpoint-ORIG-GUID: xXs1rtU4G3FAatjmSiwNPOODRLKF0yKt X-Proofpoint-GUID: xXs1rtU4G3FAatjmSiwNPOODRLKF0yKt X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX+vQB2wW3s3YZ Xw7DQJaPjfpekv07gmhSTndxeuMmiEMmVsqEHqZNF4kSNnzJpidUGdDqzFBhuX8xsMu4q5T00qg bNhKm7NW3trQij2MxpoW0HVQ8Jq4Cjo= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 phishscore=0 spamscore=0 clxscore=1015 adultscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280011 Content-Type: text/plain; charset="utf-8" Introduce function pointers in the udma_dev structure to allow variant-specific implementations for certain operations. This prepares the driver for supporting multiple K3 UDMA variants, such as UDMA v2, with minimal code duplication. No functional changes intended in this commit. Reviewed-by: Frank Li Signed-off-by: Sai Sree Kartheek Adivi --- drivers/dma/ti/k3-udma-private.c | 10 ++++- drivers/dma/ti/k3-udma.c | 66 ++++++++++++++++++-------------- drivers/dma/ti/k3-udma.h | 12 ++++++ 3 files changed, 57 insertions(+), 31 deletions(-) diff --git a/drivers/dma/ti/k3-udma-private.c b/drivers/dma/ti/k3-udma-priv= ate.c index 624360423ef17..44c097fff5ee6 100644 --- a/drivers/dma/ti/k3-udma-private.c +++ b/drivers/dma/ti/k3-udma-private.c @@ -8,13 +8,19 @@ =20 int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thr= ead) { - return navss_psil_pair(ud, src_thread, dst_thread); + if (ud->psil_pair) + return ud->psil_pair(ud, src_thread, dst_thread); + + return 0; } EXPORT_SYMBOL(xudma_navss_psil_pair); =20 int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread, u32 dst_t= hread) { - return navss_psil_unpair(ud, src_thread, dst_thread); + if (ud->psil_unpair) + return ud->psil_unpair(ud, src_thread, dst_thread); + + return 0; } EXPORT_SYMBOL(xudma_navss_psil_unpair); =20 diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 6a731fcfc0697..36dcc888815ea 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -40,7 +40,7 @@ static const char * const mmr_names[] =3D { [MMR_TCHANRT] =3D "tchanrt", }; =20 -static int navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_th= read) +int navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread) { struct udma_tisci_rm *tisci_rm =3D &ud->tisci_rm; =20 @@ -50,8 +50,8 @@ static int navss_psil_pair(struct udma_dev *ud, u32 src_t= hread, u32 dst_thread) src_thread, dst_thread); } =20 -static int navss_psil_unpair(struct udma_dev *ud, u32 src_thread, - u32 dst_thread) +int navss_psil_unpair(struct udma_dev *ud, u32 src_thread, + u32 dst_thread) { struct udma_tisci_rm *tisci_rm =3D &ud->tisci_rm; =20 @@ -329,7 +329,7 @@ static int udma_start(struct udma_chan *uc) } =20 /* Make sure that we clear the teardown bit, if it is set */ - udma_reset_chan(uc, false); + uc->ud->reset_chan(uc, false); =20 /* Push descriptors before we start the channel */ udma_start_desc(uc); @@ -521,8 +521,8 @@ static void udma_check_tx_completion(struct work_struct= *work) if (uc->desc) { struct udma_desc *d =3D uc->desc; =20 - udma_decrement_byte_counters(uc, d->residue); - udma_start(uc); + uc->ud->decrement_byte_counters(uc, d->residue); + uc->ud->start(uc); vchan_cookie_complete(&d->vd); break; } @@ -554,7 +554,7 @@ static irqreturn_t udma_ring_irq_handler(int irq, void = *data) } =20 if (!uc->desc) - udma_start(uc); + uc->ud->start(uc); =20 goto out; } @@ -576,8 +576,8 @@ static irqreturn_t udma_ring_irq_handler(int irq, void = *data) vchan_cyclic_callback(&d->vd); } else { if (udma_is_desc_really_done(uc, d)) { - udma_decrement_byte_counters(uc, d->residue); - udma_start(uc); + uc->ud->decrement_byte_counters(uc, d->residue); + uc->ud->start(uc); vchan_cookie_complete(&d->vd); } else { schedule_delayed_work(&uc->tx_drain.work, @@ -612,8 +612,8 @@ static irqreturn_t udma_udma_irq_handler(int irq, void = *data) vchan_cyclic_callback(&d->vd); } else { /* TODO: figure out the real amount of data */ - udma_decrement_byte_counters(uc, d->residue); - udma_start(uc); + uc->ud->decrement_byte_counters(uc, d->residue); + uc->ud->start(uc); vchan_cookie_complete(&d->vd); } } @@ -1654,7 +1654,7 @@ static int udma_alloc_chan_resources(struct dma_chan = *chan) =20 if (udma_is_chan_running(uc)) { dev_warn(ud->dev, "chan%d: is running!\n", uc->id); - udma_reset_chan(uc, false); + ud->reset_chan(uc, false); if (udma_is_chan_running(uc)) { dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); ret =3D -EBUSY; @@ -1663,7 +1663,7 @@ static int udma_alloc_chan_resources(struct dma_chan = *chan) } =20 /* PSI-L pairing */ - ret =3D navss_psil_pair(ud, uc->config.src_thread, uc->config.dst_thread); + ret =3D ud->psil_pair(ud, uc->config.src_thread, uc->config.dst_thread); if (ret) { dev_err(ud->dev, "PSI-L pairing failed: 0x%04x -> 0x%04x\n", uc->config.src_thread, uc->config.dst_thread); @@ -1718,7 +1718,7 @@ static int udma_alloc_chan_resources(struct dma_chan = *chan) uc->irq_num_ring =3D 0; uc->irq_num_udma =3D 0; err_psi_free: - navss_psil_unpair(ud, uc->config.src_thread, uc->config.dst_thread); + ud->psil_unpair(ud, uc->config.src_thread, uc->config.dst_thread); uc->psil_paired =3D false; err_res_free: udma_free_tx_resources(uc); @@ -1821,7 +1821,7 @@ static int bcdma_alloc_chan_resources(struct dma_chan= *chan) =20 if (udma_is_chan_running(uc)) { dev_warn(ud->dev, "chan%d: is running!\n", uc->id); - udma_reset_chan(uc, false); + ud->reset_chan(uc, false); if (udma_is_chan_running(uc)) { dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); ret =3D -EBUSY; @@ -1849,8 +1849,8 @@ static int bcdma_alloc_chan_resources(struct dma_chan= *chan) uc->use_dma_pool =3D true; } else if (uc->config.dir !=3D DMA_MEM_TO_MEM) { /* PSI-L pairing */ - ret =3D navss_psil_pair(ud, uc->config.src_thread, - uc->config.dst_thread); + ret =3D ud->psil_pair(ud, uc->config.src_thread, + uc->config.dst_thread); if (ret) { dev_err(ud->dev, "PSI-L pairing failed: 0x%04x -> 0x%04x\n", @@ -1910,8 +1910,8 @@ static int bcdma_alloc_chan_resources(struct dma_chan= *chan) uc->irq_num_udma =3D 0; err_psi_free: if (uc->psil_paired) - navss_psil_unpair(ud, uc->config.src_thread, - uc->config.dst_thread); + ud->psil_unpair(ud, uc->config.src_thread, + uc->config.dst_thread); uc->psil_paired =3D false; err_res_free: bcdma_free_bchan_resources(uc); @@ -2014,7 +2014,7 @@ static int pktdma_alloc_chan_resources(struct dma_cha= n *chan) =20 if (udma_is_chan_running(uc)) { dev_warn(ud->dev, "chan%d: is running!\n", uc->id); - udma_reset_chan(uc, false); + ud->reset_chan(uc, false); if (udma_is_chan_running(uc)) { dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); ret =3D -EBUSY; @@ -2037,7 +2037,7 @@ static int pktdma_alloc_chan_resources(struct dma_cha= n *chan) uc->use_dma_pool =3D true; =20 /* PSI-L pairing */ - ret =3D navss_psil_pair(ud, uc->config.src_thread, uc->config.dst_thread); + ret =3D ud->psil_pair(ud, uc->config.src_thread, uc->config.dst_thread); if (ret) { dev_err(ud->dev, "PSI-L pairing failed: 0x%04x -> 0x%04x\n", uc->config.src_thread, uc->config.dst_thread); @@ -2083,7 +2083,7 @@ static int pktdma_alloc_chan_resources(struct dma_cha= n *chan) err_irq_free: uc->irq_num_ring =3D 0; err_psi_free: - navss_psil_unpair(ud, uc->config.src_thread, uc->config.dst_thread); + ud->psil_unpair(ud, uc->config.src_thread, uc->config.dst_thread); uc->psil_paired =3D false; err_res_free: udma_free_tx_resources(uc); @@ -2123,7 +2123,7 @@ static void udma_issue_pending(struct dma_chan *chan) */ if (!(uc->state =3D=3D UDMA_CHAN_IS_TERMINATING && udma_is_chan_running(uc))) - udma_start(uc); + uc->ud->start(uc); } =20 spin_unlock_irqrestore(&uc->vc.lock, flags); @@ -2265,7 +2265,7 @@ static int udma_terminate_all(struct dma_chan *chan) spin_lock_irqsave(&uc->vc.lock, flags); =20 if (udma_is_chan_running(uc)) - udma_stop(uc); + uc->ud->stop(uc); =20 if (uc->desc) { uc->terminated_desc =3D uc->desc; @@ -2297,11 +2297,11 @@ static void udma_synchronize(struct dma_chan *chan) dev_warn(uc->ud->dev, "chan%d teardown timeout!\n", uc->id); udma_dump_chan_stdata(uc); - udma_reset_chan(uc, true); + uc->ud->reset_chan(uc, true); } } =20 - udma_reset_chan(uc, false); + uc->ud->reset_chan(uc, false); if (udma_is_chan_running(uc)) dev_warn(uc->ud->dev, "chan%d refused to stop!\n", uc->id); =20 @@ -2355,7 +2355,7 @@ static void udma_free_chan_resources(struct dma_chan = *chan) =20 udma_terminate_all(chan); if (uc->terminated_desc) { - udma_reset_chan(uc, false); + ud->reset_chan(uc, false); udma_reset_rings(uc); } =20 @@ -2374,8 +2374,8 @@ static void udma_free_chan_resources(struct dma_chan = *chan) =20 /* Release PSI-L pairing */ if (uc->psil_paired) { - navss_psil_unpair(ud, uc->config.src_thread, - uc->config.dst_thread); + ud->psil_unpair(ud, uc->config.src_thread, + uc->config.dst_thread); uc->psil_paired =3D false; } =20 @@ -3694,6 +3694,14 @@ static int udma_probe(struct platform_device *pdev) ud->soc_data =3D soc->data; } =20 + // Setup function pointers + ud->start =3D udma_start; + ud->stop =3D udma_stop; + ud->reset_chan =3D udma_reset_chan; + ud->decrement_byte_counters =3D udma_decrement_byte_counters; + ud->psil_pair =3D navss_psil_pair; + ud->psil_unpair =3D navss_psil_unpair; + ret =3D udma_get_mmrs(pdev, ud); if (ret) return ret; diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h index 767b73021390d..16de0b218d8ad 100644 --- a/drivers/dma/ti/k3-udma.h +++ b/drivers/dma/ti/k3-udma.h @@ -348,6 +348,15 @@ struct udma_dev { u32 psil_base; u32 atype; u32 asel; + + int (*start)(struct udma_chan *uc); + int (*stop)(struct udma_chan *uc); + int (*reset_chan)(struct udma_chan *uc, bool hard); + void (*decrement_byte_counters)(struct udma_chan *uc, u32 val); + int (*psil_pair)(struct udma_dev *ud, u32 src_thread, + u32 dst_thread); + int (*psil_unpair)(struct udma_dev *ud, u32 src_thread, + u32 dst_thread); }; =20 struct udma_desc { @@ -618,6 +627,9 @@ int udma_push_to_ring(struct udma_chan *uc, int idx); int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr); void udma_reset_rings(struct udma_chan *uc); =20 +int navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread); +int navss_psil_unpair(struct udma_dev *ud, u32 src_thread, u32 dst_thread); + /* Direct access to UDMA low lever resources for the glue layer */ int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thr= ead); int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread, --=20 2.54.0 From nobody Tue Sep 29 08:26:17 2026 Received: from mx0a-0002e601.pphosted.com (mx0a-0002e601.pphosted.com [148.163.150.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA18E369D47; Mon, 28 Sep 2026 02:59:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.150.75 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564383; cv=fail; b=DF5oJSdR64GqTpjiDOaWIwoAUG9awY4hUsc0mYI3134OZPQwQujmu97+c+62If92j2qiDusqsD1ujr3UgtIaz9vJKVDOUX0fun3eYJ+BI8Ou4nI4Cy1WbIFcv0ewPAXyIsLfnAnElPaI/wrisJkLU+CDdh6G+RZHXLql6Nk7HIo= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564383; c=relaxed/simple; bh=nbboQwr+r6K/mlp324YEHHX6OzKxyxUfhtz0Y5t777A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pqPbhmH1UK1VDxR44oVtokURrXSKZHbIN5DOB1dtmGsG51l7KCnSTU4PBFkViwU6Wk5YRLv7Wb7RD5SA5Mvi1oCgO6XkRRmijJp2KYZTgmEv4c3Pupow3gPYlfQYASraTKJRCTzor8sV0NNaI/eT6rW8TzzC+AFmzWj5UWxKCvs= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=VhOX7hk1; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=F7UKOH58; arc=fail smtp.client-ip=148.163.150.75 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="VhOX7hk1"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="F7UKOH58" Received: from pps.filterd (m0384305.ppops.net [127.0.0.1]) by m0384305.ppops.net (8.18.1.11/8.18.1.11) with ESMTP id 68S0RoKr3706315; Sun, 27 Sep 2026 21:59:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=sWggb4LwGdFXmbCia/o8TFUFG5mJHyx58KIubg4Xb nI=; b=VhOX7hk110/UUEe5igjYO9+ti6bBKvQZeS8PPiu5CTWTZZCFcKDlooStc m1edAHhBx3EKfTCWAF47+vzFVVw5BfioMxcu1FN44RqWmEwgry2WSnXyBLgp7Eil k1odfhBFdycfFMoI98rREO6dVmb/4HvV/qRyaGej21wMrExUsL2obWAoZduh3P0X TjD6HE3t+MxU8fpYuRAf8paVHM/idRxOiXgELlhWg0P3Xy3D0hZ84zRKcPWtB1I8 nO9DZx6lrGtdTiYa7y7Us90163jfNiAr2dInkZpyb0eDEM62Ns577fAxphvdukV5 4sddwMXVAw9ZOhpe2stNQ9ppRkgOg== Received: from ph7pr06cu001.outbound.protection.outlook.com (mail-westus3azon11010044.outbound.protection.outlook.com [52.101.201.44]) by m0384305.ppops.net (PPS) with ESMTPS id 4gy00nb1sw-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Sun, 27 Sep 2026 21:59:25 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=S8gTGKyXKTzMPvNR4XIGZeGtP7M1VWHp+VwpifMptDsBqPhxaaklOb38WAl0TOC5yaLR7VdymO/YjmZMqGKoLTz2YxaerwaYqgo5O7Cp3T3w1ulJCy/YTMHOmllGoIfvBjksEflu8mWoTJXKReAHzTYDtQcFlVBPUleXaRbRitd2mBPHUf3iIz+UTAbrvBMura5TJOmF6REyY73Z+Rplp0jVjhY9fDg3/q+AUtarTDV1Yl3xdFqGIa+t/CmOami9q96usp3lTg7vQ2i04fUpkTov8O4NkxKSHJcuNtpBuS4i8sE2lNYRMR3dY5703t77ctphZpSfQ506XkRgd7uT8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=sWggb4LwGdFXmbCia/o8TFUFG5mJHyx58KIubg4XbnI=; b=LTwbm57j9jEFotW1uHRiOUGIhnsFB8/Y6UOdbCDpx8aLSFQvVHU2Q6l2mDSwBm6B35ufcsdR2WYtkk/oIbhPuzFp2xMfKH9G+xWRAETCtBdf0gMSuuJan1C+rT+zh0jEcWIEPH0kK6v7UyTdiYDGdCV9Wedy4mbSKb0o6jtz+Dd2WPv1eWSZFhPIJTGZE0MtyBtQCHJHBSXTzFFHAKGwu8H/EGd1fGPPueGFw0esNsO2R5lcM/TsqHw4ObPtLgiynsSNqRkwwffaROzKZBGNHZp9U4jAVTHPBuH5FEaEbmOg6EWnCKEc6urXJmAeIAeNnPVDEHyp0LRHLiFb9rVGhw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.21.195) smtp.rcpttodomain=nxp.com smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sWggb4LwGdFXmbCia/o8TFUFG5mJHyx58KIubg4XbnI=; b=F7UKOH58ld2q+1hkFzCgaG2fz1mHx7A9QcayQ18zya3LaH3paPeu7pBAc96HA7fQnRN4Dko04cY92VyCP0Wl2x8mMZZMfrobxvHuwM8vc/jBiFB23PFt7YQKFr9wqildPyGzKgb/8CLbl+jC72j1dF1sLMjVwnxyW7OgOqPJ8pk= Received: from PH7P220CA0082.NAMP220.PROD.OUTLOOK.COM (2603:10b6:510:32c::17) by SN7PR10MB6620.namprd10.prod.outlook.com (2603:10b6:806:2af::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.7; Mon, 28 Sep 2026 02:59:18 +0000 Received: from SJ1PEPF000023D2.namprd02.prod.outlook.com (2603:10b6:510:32c:cafe::87) by PH7P220CA0082.outlook.office365.com (2603:10b6:510:32c::17) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.451.23 via Frontend Transport; Mon, 28 Sep 2026 02:59:18 +0000 X-MS-Exchange-Authentication-Results: mx.microsoft.com 1; spf=pass (sender IP is 198.47.21.195) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.21.195 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.21.195; helo=flwvzet201.ext.ti.com; pr=C Received: from flwvzet201.ext.ti.com (198.47.21.195) by SJ1PEPF000023D2.mail.protection.outlook.com (10.167.244.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Mon, 28 Sep 2026 02:59:16 +0000 Received: from DFLE210.ent.ti.com (10.64.6.68) by flwvzet201.ext.ti.com (10.248.192.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:35 -0500 Received: from DFLE208.ent.ti.com (10.64.6.66) by DFLE210.ent.ti.com (10.64.6.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:35 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE208.ent.ti.com (10.64.6.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45 via Frontend Transport; Sun, 27 Sep 2026 21:58:36 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [10.24.51.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 68S2vqqF2256662; Sun, 27 Sep 2026 21:58:31 -0500 From: Sai Sree Kartheek Adivi To: , , , , , , , , , , , , , CC: , Subject: [PATCH v10 08/19] dmaengine: ti: k3-udma: move udma utility functions to k3-udma-common.c Date: Mon, 28 Sep 2026 08:26:14 +0530 Message-ID: <20260928025749.1055383-9-s-adivi@ti.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260928025749.1055383-1-s-adivi@ti.com> References: <20260928025749.1055383-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D2:EE_|SN7PR10MB6620:EE_ X-MS-Office365-Filtering-Correlation-Id: e4bcfd05-a3a3-4e98-dcb5-08df1d0c7be0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|36860700016|82310400026|23010399003|921020|6133799003|3023799007|10067099003|5023799004|56012099006|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: th37/oCcYHiLcjFDYap8rO4xYxcmxWKKPiJtMlu0LPaEcKP/7xHP5uf4oWeNPqQlW65wK0MhilmObi0V1bYu5jge1XtBgzQYhcJsOlcXL+o/DAX9jI+L83VFjat2HLynVU+BwgFVlgIAZccJ7VmGcPUs5izXQjn9ug80e/lgG/cyoaj9dSNHZisltpt+CdrK8kA+PBBYoPctArAQxDxa0ggoRsWklJG7jj0/uOGf15x8wS9vB/ePq96yU1czuSiC23ytvaSFbzNStXlWH6ED9tYn2M5LFD+r2UFMrES9ulnhYOOPDntwcm+nDkRlDg//5piFTMtsDrlaVyyfE9l/8zwnw8vYIFkBNpvanmIk5oq83LG4WtGBbwiQ3jp2pXaA3dJUeWS4XnpXI6GeV4N/Ti+Uxnj//b4mfHY+XTuFxhyeYMS0qfhLN8SRYILRGbRkj8RUoLsOhKU2bkSIsGTwHtKCYnXgWaEDU5zW9ChmqJthhL8uG5odVulHCkv3ZOymMzWTavn0XCJDNshSGksSJuXpIw4VZfvB9hm8tzBDRztlk6Fe6q5ft83bjjiZLOrzhhZLbZR1l0NDQSIloduL3TKbw1LNtJxaELfLCwbvQcanmmHXENGQs6BqX3Egd2nijJOqwnfk/1VneLuL+5isusDU/xhJHp/lOD2dmZ6iULiHcUe4X7epaYPRR1J254atj6SqMz3s02pQbfqPwIUoYoxzZnXATzlyqbBLibtCOVfbX5DGlh/fDbJ9ljSNKAlF X-Forefront-Antispam-Report: CIP:198.47.21.195;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:flwvzet201.ext.ti.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(36860700016)(82310400026)(23010399003)(921020)(6133799003)(3023799007)(10067099003)(5023799004)(56012099006)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: GdK5wkVqL+/OajkgBmXgc0bCdbR5eyUeVjnd2/VdODGdqGRjQBueIBeacVDbI0cVHXImzmWwZx3K5Gh3+qJa+SWjx62WiVnZSYZTfx9PsQycNB2vAuGE+QiPTDk2kbO0re33XwHvX/bW6W8mR9tQu/rN5A8z7ftyKNSVFY7aCZKLESBCxONIGUniaUmWsFAlDTbkg+GrobJf9Re6t2oos+NA44lhWpnKWq8EKW6aiODuxAPhdPlDXZ46YIyRjxsTjHG3mC2MX4G54beFEIQb8Nq5v7vgGSRZ59JVjbIS7pHSVWwjcCGZV22tWA2bRa5gadHb4l+/e+R/mMMR1qetGCECaZ87W1pmhTr6okcCQuI8DpbHuLlXcI6RuNkyLy2QcGiBv3PNcgPxQo/OrRGNcs/MVhotz1ibzV5ZUR1/fFfCbvKWpk+ljNN6BOx6wj/0 X-Exchange-RoutingPolicyChecked: Q8Rv/2VakPPoedUd3umQlZeBb5k/znFmoa639rLbiXhTlb0+U1e1AxbMwH5QLjRbePQe1Cz0l+uYhe8lBJ+gW5+ZBbqwYgHTvO42y3jl/nsvzW5G62z/2RJvxXrDOmL3ReSUi35/He4/GTe7+pTRwQog7P1YQJ1DjSV2rTTp1idkjswEx7usNOPX7Wbh9LwrTGbU65IHDfWWFbyRkcDWNYzcwFQ3LPagkslLJJ5RwAkd1S95dyfU2wvRd/Sy4BEQlYJu23NQcQr3WCjMszmWhFc+Bug8ZXjkt7dwhu4zVyVDUA1r+lOPnp8M2gTH9TMwI2i2c3miyB33LBfUpAGhww== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 02:59:16.3662 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e4bcfd05-a3a3-4e98-dcb5-08df1d0c7be0 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR10MB6620 X-Proofpoint-GUID: 7NAtogmXpc3LgV3xg6jy1w0vHucuHxln X-Authority-Analysis: v=2.4 cv=fKysTpae c=1 sm=1 tr=0 ts=6ab9d80d cx=c_pps a=BI8ydP9R2Zc1CK2A4JEEvQ==:117 a=tJyPKKxUohctrY4NYmUjkA==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=VdqzKS8jKosA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=taLDd7a_hP9WKsMzeGRc:22 a=sozttTNsAAAA:8 a=bI_GjgVLxrynCmwSAzAA:9 X-Proofpoint-ORIG-GUID: 7NAtogmXpc3LgV3xg6jy1w0vHucuHxln X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX8rJJgAZhIjM5 mohOp9TMX8RThvTaT6DzTmlflZv4V+PhQIEHem7oZVJOIRktZ24zzlVC4PiKk7QtHKjru89Zj97 b3x4cf2pF02ITblovtirWSah/Lg1hgA= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfXwT+fh/DBIA2m ucSJv9AEI5+Du6t4qqG6cs7atuplrstvwqJOph1zfuWUjh0ODE8+8gmQYSEcp9y9pQtH6Mx3ce1 7CUhepXwHJdgQDc3fDzPrnhr83pdiLOsHMdcPhzj9YEtrHr1TnVH+JpIvXmoahlaPm9/cNrK4aT K1+cYFI0JnseCzByqCJ1H1BeW0zoUDIa4hTTOv7RmDQEkpBrNHwTBtjouf2up1y6hARMDMr6jEY RDd4Bmp+y4wz3iAcjcYDAKlEWLjU0omNDLztC+dBdmRHFWYoT6l8sm/xNlBcfJdk/eRsoKnGr3j cANtyrma7tWK/xcwo9aJTbB8xEBsCFTi4oQF/0c4hC7BOTYgpnWCSm+xs3TUkD9PZXQYFNPbj/q qOrLxJZEHnx6RVd+oWyu46Z3VM6gpJdnatN1ia9WhdNQEdYy0YW73bVAsV7FI0N7Mrn8ikhyFwp TVpsq0saV1Nv9C+PQaQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 spamscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 adultscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280011 Content-Type: text/plain; charset="utf-8" Relocate udma utility functions from k3-udma.c to k3-udma-common.c file. The implementation of these functions is largely shared between K3 UDMA and K3 UDMA v2. This refactor improves code reuse and maintainability across multiple variants. No functional changes intended. Signed-off-by: Sai Sree Kartheek Adivi --- drivers/dma/ti/k3-udma-common.c | 549 ++++++++++++++++++++++++++++++++ drivers/dma/ti/k3-udma.c | 531 ------------------------------ drivers/dma/ti/k3-udma.h | 28 ++ 3 files changed, 577 insertions(+), 531 deletions(-) diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-commo= n.c index 3ec5cc932280c..dbd667d77f137 100644 --- a/drivers/dma/ti/k3-udma-common.c +++ b/drivers/dma/ti/k3-udma-common.c @@ -4,6 +4,7 @@ * Author: Peter Ujfalusi */ =20 +#include #include #include #include @@ -46,6 +47,28 @@ struct udma_desc *udma_udma_desc_from_paddr(struct udma_= chan *uc, } EXPORT_SYMBOL_GPL(udma_udma_desc_from_paddr); =20 +void udma_start_desc(struct udma_chan *uc) +{ + struct udma_chan_config *ucc =3D &uc->config; + + if (uc->ud->match_data->type =3D=3D DMA_TYPE_UDMA && ucc->pkt_mode && + (uc->cyclic || ucc->dir =3D=3D DMA_DEV_TO_MEM)) { + int i; + + /* + * UDMA only: Push all descriptors to ring for packet mode + * cyclic or RX + * PKTDMA supports pre-linked descriptor and cyclic is not + * supported + */ + for (i =3D 0; i < uc->desc->sglen; i++) + udma_push_to_ring(uc, i); + } else { + udma_push_to_ring(uc, 0); + } +} +EXPORT_SYMBOL_GPL(udma_start_desc); + void udma_free_hwdesc(struct udma_chan *uc, struct udma_desc *d) { if (uc->use_dma_pool) { @@ -1342,5 +1365,531 @@ void udma_reset_rings(struct udma_chan *uc) } EXPORT_SYMBOL_GPL(udma_reset_rings); =20 +u8 udma_get_chan_tpl_index(struct udma_tpl *tpl_map, int chan_id) +{ + int i; + + for (i =3D 0; i < tpl_map->levels; i++) { + if (chan_id >=3D tpl_map->start_idx[i]) + return i; + } + + return 0; +} +EXPORT_SYMBOL_GPL(udma_get_chan_tpl_index); + +void k3_configure_chan_coherency(struct dma_chan *chan, u32 asel) +{ + struct device *chan_dev =3D dmaengine_chan_dev(chan); + + if (asel =3D=3D 0) { + /* No special handling for the channel */ + chan->chan_dev->chan_dma_dev =3D false; + + dev_clear_dma_coherent(chan_dev); + chan_dev->dma_parms =3D NULL; + } else if (asel =3D=3D 14 || asel =3D=3D 15) { + chan->chan_dev->chan_dma_dev =3D true; + + dev_set_dma_coherent(chan_dev); + dma_coerce_mask_and_coherent(chan_dev, DMA_BIT_MASK(48)); + chan_dev->dma_parms =3D chan_dev->parent->dma_parms; + } else { + dev_warn(chan->device->dev, "Invalid ASEL value: %u\n", asel); + + dev_clear_dma_coherent(chan_dev); + chan_dev->dma_parms =3D NULL; + } +} +EXPORT_SYMBOL_GPL(k3_configure_chan_coherency); + +void udma_reset_uchan(struct udma_chan *uc) +{ + memset(&uc->config, 0, sizeof(uc->config)); + uc->config.remote_thread_id =3D -1; + uc->config.mapped_channel_id =3D -1; + uc->config.default_flow_id =3D -1; + uc->state =3D UDMA_CHAN_IS_IDLE; +} +EXPORT_SYMBOL_GPL(udma_reset_uchan); + +void udma_dump_chan_stdata(struct udma_chan *uc) +{ + struct device *dev =3D uc->ud->dev; + u32 offset; + int i; + + if (uc->config.dir =3D=3D DMA_MEM_TO_DEV || uc->config.dir =3D=3D DMA_MEM= _TO_MEM) { + dev_dbg(dev, "TCHAN State data:\n"); + for (i =3D 0; i < 32; i++) { + offset =3D UDMA_CHAN_RT_STDATA_REG + i * 4; + dev_dbg(dev, "TRT_STDATA[%02d]: 0x%08x\n", i, + udma_tchanrt_read(uc, offset)); + } + } + + if (uc->config.dir =3D=3D DMA_DEV_TO_MEM || uc->config.dir =3D=3D DMA_MEM= _TO_MEM) { + dev_dbg(dev, "RCHAN State data:\n"); + for (i =3D 0; i < 32; i++) { + offset =3D UDMA_CHAN_RT_STDATA_REG + i * 4; + dev_dbg(dev, "RRT_STDATA[%02d]: 0x%08x\n", i, + udma_rchanrt_read(uc, offset)); + } + } +} + +bool udma_is_chan_running(struct udma_chan *uc) +{ + u32 trt_ctl =3D 0; + u32 rrt_ctl =3D 0; + + if (uc->tchan) + trt_ctl =3D udma_tchanrt_read(uc, UDMA_CHAN_RT_CTL_REG); + if (uc->rchan) + rrt_ctl =3D udma_rchanrt_read(uc, UDMA_CHAN_RT_CTL_REG); + + if (trt_ctl & UDMA_CHAN_RT_CTL_EN || rrt_ctl & UDMA_CHAN_RT_CTL_EN) + return true; + + return false; +} +EXPORT_SYMBOL_GPL(udma_is_chan_running); + +bool udma_chan_needs_reconfiguration(struct udma_chan *uc) +{ + /* Only PDMAs have staticTR */ + if (uc->config.ep_type =3D=3D PSIL_EP_NATIVE) + return false; + + /* Check if the staticTR configuration has changed for TX */ + if (memcmp(&uc->static_tr, &uc->desc->static_tr, sizeof(uc->static_tr))) + return true; + + return false; +} +EXPORT_SYMBOL_GPL(udma_chan_needs_reconfiguration); + +void udma_cyclic_packet_elapsed(struct udma_chan *uc) +{ + struct udma_desc *d =3D uc->desc; + struct cppi5_host_desc_t *h_desc; + + h_desc =3D d->hwdesc[d->desc_idx].cppi5_desc_vaddr; + cppi5_hdesc_reset_to_original(h_desc); + udma_push_to_ring(uc, d->desc_idx); + d->desc_idx =3D (d->desc_idx + 1) % d->sglen; +} +EXPORT_SYMBOL_GPL(udma_cyclic_packet_elapsed); + +void udma_check_tx_completion(struct work_struct *work) +{ + struct udma_chan *uc =3D container_of(work, typeof(*uc), + tx_drain.work.work); + bool desc_done =3D true; + u32 residue_diff; + ktime_t time_diff; + unsigned long delay; + unsigned long flags; + + while (1) { + spin_lock_irqsave(&uc->vc.lock, flags); + + if (uc->desc) { + /* Get previous residue and time stamp */ + residue_diff =3D uc->tx_drain.residue; + time_diff =3D uc->tx_drain.tstamp; + /* + * Get current residue and time stamp or see if + * transfer is complete + */ + desc_done =3D udma_is_desc_really_done(uc, uc->desc); + } + + if (!desc_done) { + /* + * Find the time delta and residue delta w.r.t + * previous poll + */ + time_diff =3D ktime_sub(uc->tx_drain.tstamp, + time_diff) + 1; + residue_diff -=3D uc->tx_drain.residue; + if (residue_diff) { + /* + * Try to guess when we should check + * next time by calculating rate at + * which data is being drained at the + * peer device + */ + delay =3D (time_diff / residue_diff) * + uc->tx_drain.residue; + } else { + /* No progress, check again in 1 second */ + schedule_delayed_work(&uc->tx_drain.work, HZ); + break; + } + + spin_unlock_irqrestore(&uc->vc.lock, flags); + + usleep_range(ktime_to_us(delay), + ktime_to_us(delay) + 10); + continue; + } + + if (uc->desc) { + struct udma_desc *d =3D uc->desc; + + uc->ud->decrement_byte_counters(uc, d->residue); + uc->ud->start(uc); + vchan_cookie_complete(&d->vd); + break; + } + + break; + } + + spin_unlock_irqrestore(&uc->vc.lock, flags); +} +EXPORT_SYMBOL_GPL(udma_check_tx_completion); + +int udma_slave_config(struct dma_chan *chan, + struct dma_slave_config *cfg) +{ + struct udma_chan *uc =3D to_udma_chan(chan); + + memcpy(&uc->cfg, cfg, sizeof(uc->cfg)); + + return 0; +} +EXPORT_SYMBOL_GPL(udma_slave_config); + +void udma_issue_pending(struct dma_chan *chan) +{ + struct udma_chan *uc =3D to_udma_chan(chan); + unsigned long flags; + + spin_lock_irqsave(&uc->vc.lock, flags); + + /* If we have something pending and no active descriptor, then */ + if (vchan_issue_pending(&uc->vc) && !uc->desc) { + /* + * start a descriptor if the channel is NOT [marked as + * terminating _and_ it is still running (teardown has not + * completed yet)]. + */ + if (!(uc->state =3D=3D UDMA_CHAN_IS_TERMINATING && + udma_is_chan_running(uc))) + uc->ud->start(uc); + } + + spin_unlock_irqrestore(&uc->vc.lock, flags); +} +EXPORT_SYMBOL_GPL(udma_issue_pending); + +int udma_terminate_all(struct dma_chan *chan) +{ + struct udma_chan *uc =3D to_udma_chan(chan); + unsigned long flags; + LIST_HEAD(head); + + spin_lock_irqsave(&uc->vc.lock, flags); + + if (udma_is_chan_running(uc)) + uc->ud->stop(uc); + + if (uc->desc) { + uc->terminated_desc =3D uc->desc; + uc->desc =3D NULL; + uc->terminated_desc->terminated =3D true; + cancel_delayed_work(&uc->tx_drain.work); + } + + uc->paused =3D false; + + vchan_get_all_descriptors(&uc->vc, &head); + spin_unlock_irqrestore(&uc->vc.lock, flags); + vchan_dma_desc_free_list(&uc->vc, &head); + + return 0; +} +EXPORT_SYMBOL_GPL(udma_terminate_all); + +void udma_synchronize(struct dma_chan *chan) +{ + struct udma_chan *uc =3D to_udma_chan(chan); + unsigned long timeout =3D msecs_to_jiffies(1000); + + vchan_synchronize(&uc->vc); + + if (uc->state =3D=3D UDMA_CHAN_IS_TERMINATING) { + timeout =3D wait_for_completion_timeout(&uc->teardown_completed, + timeout); + if (!timeout) { + dev_warn(uc->ud->dev, "chan%d teardown timeout!\n", + uc->id); + udma_dump_chan_stdata(uc); + uc->ud->reset_chan(uc, true); + } + } + + uc->ud->reset_chan(uc, false); + if (udma_is_chan_running(uc)) + dev_warn(uc->ud->dev, "chan%d refused to stop!\n", uc->id); + + cancel_delayed_work_sync(&uc->tx_drain.work); + udma_reset_rings(uc); +} +EXPORT_SYMBOL_GPL(udma_synchronize); + +/* + * This tasklet handles the completion of a DMA descriptor by + * calling its callback and freeing it. + */ +void udma_vchan_complete(struct tasklet_struct *t) +{ + struct virt_dma_chan *vc =3D from_tasklet(vc, t, task); + struct virt_dma_desc *vd, *_vd; + struct dmaengine_desc_callback cb; + LIST_HEAD(head); + + spin_lock_irq(&vc->lock); + list_splice_tail_init(&vc->desc_completed, &head); + vd =3D vc->cyclic; + if (vd) { + vc->cyclic =3D NULL; + dmaengine_desc_get_callback(&vd->tx, &cb); + } else { + memset(&cb, 0, sizeof(cb)); + } + spin_unlock_irq(&vc->lock); + + udma_desc_pre_callback(vc, vd, NULL); + dmaengine_desc_callback_invoke(&cb, NULL); + + list_for_each_entry_safe(vd, _vd, &head, node) { + struct dmaengine_result result; + + dmaengine_desc_get_callback(&vd->tx, &cb); + + list_del(&vd->node); + + udma_desc_pre_callback(vc, vd, &result); + dmaengine_desc_callback_invoke(&cb, &result); + + vchan_vdesc_fini(vd); + } +} +EXPORT_SYMBOL_GPL(udma_vchan_complete); + +void udma_mark_resource_ranges(struct udma_dev *ud, unsigned long *map, + struct ti_sci_resource_desc *rm_desc, + char *name) +{ + bitmap_clear(map, rm_desc->start, rm_desc->num); + bitmap_clear(map, rm_desc->start_sec, rm_desc->num_sec); + dev_dbg(ud->dev, "ti_sci resource range for %s: %d:%d | %d:%d\n", name, + rm_desc->start, rm_desc->num, rm_desc->start_sec, + rm_desc->num_sec); +} +EXPORT_SYMBOL_GPL(udma_mark_resource_ranges); + +int udma_setup_rx_flush(struct udma_dev *ud) +{ + struct udma_rx_flush *rx_flush =3D &ud->rx_flush; + struct cppi5_desc_hdr_t *tr_desc; + struct cppi5_tr_type1_t *tr_req; + struct cppi5_host_desc_t *desc; + struct device *dev =3D ud->dev; + struct udma_hwdesc *hwdesc; + size_t tr_size; + + /* Allocate 1K buffer for discarded data on RX channel teardown */ + rx_flush->buffer_size =3D SZ_1K; + rx_flush->buffer_vaddr =3D devm_kzalloc(dev, rx_flush->buffer_size, + GFP_KERNEL); + if (!rx_flush->buffer_vaddr) + return -ENOMEM; + + rx_flush->buffer_paddr =3D dma_map_single(dev, rx_flush->buffer_vaddr, + rx_flush->buffer_size, + DMA_TO_DEVICE); + if (dma_mapping_error(dev, rx_flush->buffer_paddr)) + return -ENOMEM; + + /* Set up descriptor to be used for TR mode */ + hwdesc =3D &rx_flush->hwdescs[0]; + tr_size =3D sizeof(struct cppi5_tr_type1_t); + hwdesc->cppi5_desc_size =3D cppi5_trdesc_calc_size(tr_size, 1); + hwdesc->cppi5_desc_size =3D ALIGN(hwdesc->cppi5_desc_size, + ud->desc_align); + + hwdesc->cppi5_desc_vaddr =3D devm_kzalloc(dev, hwdesc->cppi5_desc_size, + GFP_KERNEL); + if (!hwdesc->cppi5_desc_vaddr) + return -ENOMEM; + + hwdesc->cppi5_desc_paddr =3D dma_map_single(dev, hwdesc->cppi5_desc_vaddr, + hwdesc->cppi5_desc_size, + DMA_TO_DEVICE); + if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr)) + return -ENOMEM; + + /* Start of the TR req records */ + hwdesc->tr_req_base =3D hwdesc->cppi5_desc_vaddr + tr_size; + /* Start address of the TR response array */ + hwdesc->tr_resp_base =3D hwdesc->tr_req_base + tr_size; + + tr_desc =3D hwdesc->cppi5_desc_vaddr; + cppi5_trdesc_init(tr_desc, 1, tr_size, 0, 0); + cppi5_desc_set_pktids(tr_desc, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT); + cppi5_desc_set_retpolicy(tr_desc, 0, 0); + + tr_req =3D hwdesc->tr_req_base; + cppi5_tr_init(&tr_req->flags, CPPI5_TR_TYPE1, false, false, + CPPI5_TR_EVENT_SIZE_COMPLETION, 0); + cppi5_tr_csf_set(&tr_req->flags, CPPI5_TR_CSF_SUPR_EVT); + + tr_req->addr =3D rx_flush->buffer_paddr; + tr_req->icnt0 =3D rx_flush->buffer_size; + tr_req->icnt1 =3D 1; + + dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr, + hwdesc->cppi5_desc_size, DMA_TO_DEVICE); + + /* Set up descriptor to be used for packet mode */ + hwdesc =3D &rx_flush->hwdescs[1]; + hwdesc->cppi5_desc_size =3D ALIGN(sizeof(struct cppi5_host_desc_t) + + CPPI5_INFO0_HDESC_EPIB_SIZE + + CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE, + ud->desc_align); + + hwdesc->cppi5_desc_vaddr =3D devm_kzalloc(dev, hwdesc->cppi5_desc_size, + GFP_KERNEL); + if (!hwdesc->cppi5_desc_vaddr) + return -ENOMEM; + + hwdesc->cppi5_desc_paddr =3D dma_map_single(dev, hwdesc->cppi5_desc_vaddr, + hwdesc->cppi5_desc_size, + DMA_TO_DEVICE); + if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr)) + return -ENOMEM; + + desc =3D hwdesc->cppi5_desc_vaddr; + cppi5_hdesc_init(desc, 0, 0); + cppi5_desc_set_pktids(&desc->hdr, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT); + cppi5_desc_set_retpolicy(&desc->hdr, 0, 0); + + cppi5_hdesc_attach_buf(desc, + rx_flush->buffer_paddr, rx_flush->buffer_size, + rx_flush->buffer_paddr, rx_flush->buffer_size); + + dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr, + hwdesc->cppi5_desc_size, DMA_TO_DEVICE); + return 0; +} +EXPORT_SYMBOL_GPL(udma_setup_rx_flush); + +#ifdef CONFIG_DEBUG_FS +void udma_dbg_summary_show_chan(struct seq_file *s, + struct dma_chan *chan) +{ + struct udma_chan *uc =3D to_udma_chan(chan); + struct udma_chan_config *ucc =3D &uc->config; + + seq_printf(s, " %-13s| %s", dma_chan_name(chan), + chan->dbg_client_name ?: "in-use"); + if (ucc->tr_trigger_type) + seq_puts(s, " (triggered, "); + else + seq_printf(s, " (%s, ", + dmaengine_get_direction_text(uc->config.dir)); + + switch (uc->config.dir) { + case DMA_MEM_TO_MEM: + if (uc->ud->match_data->type =3D=3D DMA_TYPE_BCDMA) { + seq_printf(s, "bchan%d)\n", uc->bchan->id); + return; + } + + seq_printf(s, "chan%d pair [0x%04x -> 0x%04x], ", uc->tchan->id, + ucc->src_thread, ucc->dst_thread); + break; + case DMA_DEV_TO_MEM: + seq_printf(s, "rchan%d [0x%04x -> 0x%04x], ", uc->rchan->id, + ucc->src_thread, ucc->dst_thread); + if (uc->ud->match_data->type =3D=3D DMA_TYPE_PKTDMA) + seq_printf(s, "rflow%d, ", uc->rflow->id); + break; + case DMA_MEM_TO_DEV: + seq_printf(s, "tchan%d [0x%04x -> 0x%04x], ", uc->tchan->id, + ucc->src_thread, ucc->dst_thread); + if (uc->ud->match_data->type =3D=3D DMA_TYPE_PKTDMA) + seq_printf(s, "tflow%d, ", uc->tchan->tflow_id); + break; + default: + seq_puts(s, ")\n"); + return; + } + + if (ucc->ep_type =3D=3D PSIL_EP_NATIVE) { + seq_puts(s, "PSI-L Native"); + if (ucc->metadata_size) { + seq_printf(s, "[%s", ucc->needs_epib ? " EPIB" : ""); + if (ucc->psd_size) + seq_printf(s, " PSDsize:%u", ucc->psd_size); + seq_puts(s, " ]"); + } + } else { + seq_puts(s, "PDMA"); + if (ucc->enable_acc32 || ucc->enable_burst) + seq_printf(s, "[%s%s ]", + ucc->enable_acc32 ? " ACC32" : "", + ucc->enable_burst ? " BURST" : ""); + } + + seq_printf(s, ", %s)\n", ucc->pkt_mode ? "Packet mode" : "TR mode"); +} + +void udma_dbg_summary_show(struct seq_file *s, + struct dma_device *dma_dev) +{ + struct dma_chan *chan; + + list_for_each_entry(chan, &dma_dev->channels, device_node) { + if (chan->client_count) + udma_dbg_summary_show_chan(s, chan); + } +} +EXPORT_SYMBOL_GPL(udma_dbg_summary_show); +#endif /* CONFIG_DEBUG_FS */ + +enum dmaengine_alignment udma_get_copy_align(struct udma_dev *ud) +{ + const struct udma_match_data *match_data =3D ud->match_data; + u8 tpl; + + if (!match_data->enable_memcpy_support) + return DMAENGINE_ALIGN_8_BYTES; + + /* Get the highest TPL level the device supports for memcpy */ + if (ud->bchan_cnt) + tpl =3D udma_get_chan_tpl_index(&ud->bchan_tpl, 0); + else if (ud->tchan_cnt) + tpl =3D udma_get_chan_tpl_index(&ud->tchan_tpl, 0); + else + return DMAENGINE_ALIGN_8_BYTES; + + switch (match_data->burst_size[tpl]) { + case TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES: + return DMAENGINE_ALIGN_256_BYTES; + case TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES: + return DMAENGINE_ALIGN_128_BYTES; + case TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES: + fallthrough; + default: + return DMAENGINE_ALIGN_64_BYTES; + } +} +EXPORT_SYMBOL_GPL(udma_get_copy_align); + MODULE_DESCRIPTION("Texas Instruments K3 UDMA Common Library"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 36dcc888815ea..cd73bf03e9cc6 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -61,92 +61,6 @@ int navss_psil_unpair(struct udma_dev *ud, u32 src_threa= d, src_thread, dst_thread); } =20 -static void k3_configure_chan_coherency(struct dma_chan *chan, u32 asel) -{ - struct device *chan_dev =3D dmaengine_chan_dev(chan); - - if (asel =3D=3D 0) { - /* No special handling for the channel */ - chan->chan_dev->chan_dma_dev =3D false; - - dev_clear_dma_coherent(chan_dev); - chan_dev->dma_parms =3D NULL; - } else if (asel =3D=3D 14 || asel =3D=3D 15) { - chan->chan_dev->chan_dma_dev =3D true; - - dev_set_dma_coherent(chan_dev); - dma_coerce_mask_and_coherent(chan_dev, DMA_BIT_MASK(48)); - chan_dev->dma_parms =3D chan_dev->parent->dma_parms; - } else { - dev_warn(chan->device->dev, "Invalid ASEL value: %u\n", asel); - - dev_clear_dma_coherent(chan_dev); - chan_dev->dma_parms =3D NULL; - } -} - -static u8 udma_get_chan_tpl_index(struct udma_tpl *tpl_map, int chan_id) -{ - int i; - - for (i =3D 0; i < tpl_map->levels; i++) { - if (chan_id >=3D tpl_map->start_idx[i]) - return i; - } - - return 0; -} - -static void udma_reset_uchan(struct udma_chan *uc) -{ - memset(&uc->config, 0, sizeof(uc->config)); - uc->config.remote_thread_id =3D -1; - uc->config.mapped_channel_id =3D -1; - uc->config.default_flow_id =3D -1; - uc->state =3D UDMA_CHAN_IS_IDLE; -} - -static void udma_dump_chan_stdata(struct udma_chan *uc) -{ - struct device *dev =3D uc->ud->dev; - u32 offset; - int i; - - if (uc->config.dir =3D=3D DMA_MEM_TO_DEV || uc->config.dir =3D=3D DMA_MEM= _TO_MEM) { - dev_dbg(dev, "TCHAN State data:\n"); - for (i =3D 0; i < 32; i++) { - offset =3D UDMA_CHAN_RT_STDATA_REG + i * 4; - dev_dbg(dev, "TRT_STDATA[%02d]: 0x%08x\n", i, - udma_tchanrt_read(uc, offset)); - } - } - - if (uc->config.dir =3D=3D DMA_DEV_TO_MEM || uc->config.dir =3D=3D DMA_MEM= _TO_MEM) { - dev_dbg(dev, "RCHAN State data:\n"); - for (i =3D 0; i < 32; i++) { - offset =3D UDMA_CHAN_RT_STDATA_REG + i * 4; - dev_dbg(dev, "RRT_STDATA[%02d]: 0x%08x\n", i, - udma_rchanrt_read(uc, offset)); - } - } -} - -static bool udma_is_chan_running(struct udma_chan *uc) -{ - u32 trt_ctl =3D 0; - u32 rrt_ctl =3D 0; - - if (uc->tchan) - trt_ctl =3D udma_tchanrt_read(uc, UDMA_CHAN_RT_CTL_REG); - if (uc->rchan) - rrt_ctl =3D udma_rchanrt_read(uc, UDMA_CHAN_RT_CTL_REG); - - if (trt_ctl & UDMA_CHAN_RT_CTL_EN || rrt_ctl & UDMA_CHAN_RT_CTL_EN) - return true; - - return false; -} - static bool udma_is_chan_paused(struct udma_chan *uc) { u32 val, pause_mask; @@ -275,40 +189,6 @@ static int udma_reset_chan(struct udma_chan *uc, bool = hard) return 0; } =20 -static void udma_start_desc(struct udma_chan *uc) -{ - struct udma_chan_config *ucc =3D &uc->config; - - if (uc->ud->match_data->type =3D=3D DMA_TYPE_UDMA && ucc->pkt_mode && - (uc->cyclic || ucc->dir =3D=3D DMA_DEV_TO_MEM)) { - int i; - - /* - * UDMA only: Push all descriptors to ring for packet mode - * cyclic or RX - * PKTDMA supports pre-linked descriptor and cyclic is not - * supported - */ - for (i =3D 0; i < uc->desc->sglen; i++) - udma_push_to_ring(uc, i); - } else { - udma_push_to_ring(uc, 0); - } -} - -static bool udma_chan_needs_reconfiguration(struct udma_chan *uc) -{ - /* Only PDMAs have staticTR */ - if (uc->config.ep_type =3D=3D PSIL_EP_NATIVE) - return false; - - /* Check if the staticTR configuration has changed for TX */ - if (memcmp(&uc->static_tr, &uc->desc->static_tr, sizeof(uc->static_tr))) - return true; - - return false; -} - static int udma_start(struct udma_chan *uc) { struct virt_dma_desc *vd =3D vchan_next_desc(&uc->vc); @@ -453,86 +333,6 @@ static int udma_stop(struct udma_chan *uc) return 0; } =20 -static void udma_cyclic_packet_elapsed(struct udma_chan *uc) -{ - struct udma_desc *d =3D uc->desc; - struct cppi5_host_desc_t *h_desc; - - h_desc =3D d->hwdesc[d->desc_idx].cppi5_desc_vaddr; - cppi5_hdesc_reset_to_original(h_desc); - udma_push_to_ring(uc, d->desc_idx); - d->desc_idx =3D (d->desc_idx + 1) % d->sglen; -} - -static void udma_check_tx_completion(struct work_struct *work) -{ - struct udma_chan *uc =3D container_of(work, typeof(*uc), - tx_drain.work.work); - bool desc_done =3D true; - u32 residue_diff; - ktime_t time_diff; - unsigned long delay; - unsigned long flags; - - while (1) { - spin_lock_irqsave(&uc->vc.lock, flags); - - if (uc->desc) { - /* Get previous residue and time stamp */ - residue_diff =3D uc->tx_drain.residue; - time_diff =3D uc->tx_drain.tstamp; - /* - * Get current residue and time stamp or see if - * transfer is complete - */ - desc_done =3D udma_is_desc_really_done(uc, uc->desc); - } - - if (!desc_done) { - /* - * Find the time delta and residue delta w.r.t - * previous poll - */ - time_diff =3D ktime_sub(uc->tx_drain.tstamp, - time_diff) + 1; - residue_diff -=3D uc->tx_drain.residue; - if (residue_diff) { - /* - * Try to guess when we should check - * next time by calculating rate at - * which data is being drained at the - * peer device - */ - delay =3D (time_diff / residue_diff) * - uc->tx_drain.residue; - } else { - /* No progress, check again in 1 second */ - schedule_delayed_work(&uc->tx_drain.work, HZ); - break; - } - - spin_unlock_irqrestore(&uc->vc.lock, flags); - - usleep_range(ktime_to_us(delay), - ktime_to_us(delay) + 10); - continue; - } - - if (uc->desc) { - struct udma_desc *d =3D uc->desc; - - uc->ud->decrement_byte_counters(uc, d->residue); - uc->ud->start(uc); - vchan_cookie_complete(&d->vd); - break; - } - - break; - } - - spin_unlock_irqrestore(&uc->vc.lock, flags); -} - static irqreturn_t udma_ring_irq_handler(int irq, void *data) { struct udma_chan *uc =3D data; @@ -2097,38 +1897,6 @@ static int pktdma_alloc_chan_resources(struct dma_ch= an *chan) return ret; } =20 -static int udma_slave_config(struct dma_chan *chan, - struct dma_slave_config *cfg) -{ - struct udma_chan *uc =3D to_udma_chan(chan); - - memcpy(&uc->cfg, cfg, sizeof(uc->cfg)); - - return 0; -} - -static void udma_issue_pending(struct dma_chan *chan) -{ - struct udma_chan *uc =3D to_udma_chan(chan); - unsigned long flags; - - spin_lock_irqsave(&uc->vc.lock, flags); - - /* If we have something pending and no active descriptor, then */ - if (vchan_issue_pending(&uc->vc) && !uc->desc) { - /* - * start a descriptor if the channel is NOT [marked as - * terminating _and_ it is still running (teardown has not - * completed yet)]. - */ - if (!(uc->state =3D=3D UDMA_CHAN_IS_TERMINATING && - udma_is_chan_running(uc))) - uc->ud->start(uc); - } - - spin_unlock_irqrestore(&uc->vc.lock, flags); -} - static enum dma_status udma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate) @@ -2256,98 +2024,6 @@ static int udma_resume(struct dma_chan *chan) return 0; } =20 -static int udma_terminate_all(struct dma_chan *chan) -{ - struct udma_chan *uc =3D to_udma_chan(chan); - unsigned long flags; - LIST_HEAD(head); - - spin_lock_irqsave(&uc->vc.lock, flags); - - if (udma_is_chan_running(uc)) - uc->ud->stop(uc); - - if (uc->desc) { - uc->terminated_desc =3D uc->desc; - uc->desc =3D NULL; - uc->terminated_desc->terminated =3D true; - cancel_delayed_work(&uc->tx_drain.work); - } - - uc->paused =3D false; - - vchan_get_all_descriptors(&uc->vc, &head); - spin_unlock_irqrestore(&uc->vc.lock, flags); - vchan_dma_desc_free_list(&uc->vc, &head); - - return 0; -} - -static void udma_synchronize(struct dma_chan *chan) -{ - struct udma_chan *uc =3D to_udma_chan(chan); - unsigned long timeout =3D msecs_to_jiffies(1000); - - vchan_synchronize(&uc->vc); - - if (uc->state =3D=3D UDMA_CHAN_IS_TERMINATING) { - timeout =3D wait_for_completion_timeout(&uc->teardown_completed, - timeout); - if (!timeout) { - dev_warn(uc->ud->dev, "chan%d teardown timeout!\n", - uc->id); - udma_dump_chan_stdata(uc); - uc->ud->reset_chan(uc, true); - } - } - - uc->ud->reset_chan(uc, false); - if (udma_is_chan_running(uc)) - dev_warn(uc->ud->dev, "chan%d refused to stop!\n", uc->id); - - cancel_delayed_work_sync(&uc->tx_drain.work); - udma_reset_rings(uc); -} - -/* - * This tasklet handles the completion of a DMA descriptor by - * calling its callback and freeing it. - */ -static void udma_vchan_complete(struct tasklet_struct *t) -{ - struct virt_dma_chan *vc =3D from_tasklet(vc, t, task); - struct virt_dma_desc *vd, *_vd; - struct dmaengine_desc_callback cb; - LIST_HEAD(head); - - spin_lock_irq(&vc->lock); - list_splice_tail_init(&vc->desc_completed, &head); - vd =3D vc->cyclic; - if (vd) { - vc->cyclic =3D NULL; - dmaengine_desc_get_callback(&vd->tx, &cb); - } else { - memset(&cb, 0, sizeof(cb)); - } - spin_unlock_irq(&vc->lock); - - udma_desc_pre_callback(vc, vd, NULL); - dmaengine_desc_callback_invoke(&cb, NULL); - - list_for_each_entry_safe(vd, _vd, &head, node) { - struct dmaengine_result result; - - dmaengine_desc_get_callback(&vd->tx, &cb); - - list_del(&vd->node); - - udma_desc_pre_callback(vc, vd, &result); - dmaengine_desc_callback_invoke(&cb, &result); - - vchan_vdesc_fini(vd); - } -} - static void udma_free_chan_resources(struct dma_chan *chan) { struct udma_chan *uc =3D to_udma_chan(chan); @@ -2822,17 +2498,6 @@ static int udma_get_mmrs(struct platform_device *pde= v, struct udma_dev *ud) return 0; } =20 -static void udma_mark_resource_ranges(struct udma_dev *ud, unsigned long *= map, - struct ti_sci_resource_desc *rm_desc, - char *name) -{ - bitmap_clear(map, rm_desc->start, rm_desc->num); - bitmap_clear(map, rm_desc->start_sec, rm_desc->num_sec); - dev_dbg(ud->dev, "ti_sci resource range for %s: %d:%d | %d:%d\n", name, - rm_desc->start, rm_desc->num, rm_desc->start_sec, - rm_desc->num_sec); -} - static const char * const range_names[] =3D { [RM_RANGE_BCHAN] =3D "ti,sci-rm-range-bchan", [RM_RANGE_TCHAN] =3D "ti,sci-rm-range-tchan", @@ -3463,202 +3128,6 @@ static int setup_resources(struct udma_dev *ud) return ch_count; } =20 -static int udma_setup_rx_flush(struct udma_dev *ud) -{ - struct udma_rx_flush *rx_flush =3D &ud->rx_flush; - struct cppi5_desc_hdr_t *tr_desc; - struct cppi5_tr_type1_t *tr_req; - struct cppi5_host_desc_t *desc; - struct device *dev =3D ud->dev; - struct udma_hwdesc *hwdesc; - size_t tr_size; - - /* Allocate 1K buffer for discarded data on RX channel teardown */ - rx_flush->buffer_size =3D SZ_1K; - rx_flush->buffer_vaddr =3D devm_kzalloc(dev, rx_flush->buffer_size, - GFP_KERNEL); - if (!rx_flush->buffer_vaddr) - return -ENOMEM; - - rx_flush->buffer_paddr =3D dma_map_single(dev, rx_flush->buffer_vaddr, - rx_flush->buffer_size, - DMA_TO_DEVICE); - if (dma_mapping_error(dev, rx_flush->buffer_paddr)) - return -ENOMEM; - - /* Set up descriptor to be used for TR mode */ - hwdesc =3D &rx_flush->hwdescs[0]; - tr_size =3D sizeof(struct cppi5_tr_type1_t); - hwdesc->cppi5_desc_size =3D cppi5_trdesc_calc_size(tr_size, 1); - hwdesc->cppi5_desc_size =3D ALIGN(hwdesc->cppi5_desc_size, - ud->desc_align); - - hwdesc->cppi5_desc_vaddr =3D devm_kzalloc(dev, hwdesc->cppi5_desc_size, - GFP_KERNEL); - if (!hwdesc->cppi5_desc_vaddr) - return -ENOMEM; - - hwdesc->cppi5_desc_paddr =3D dma_map_single(dev, hwdesc->cppi5_desc_vaddr, - hwdesc->cppi5_desc_size, - DMA_TO_DEVICE); - if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr)) - return -ENOMEM; - - /* Start of the TR req records */ - hwdesc->tr_req_base =3D hwdesc->cppi5_desc_vaddr + tr_size; - /* Start address of the TR response array */ - hwdesc->tr_resp_base =3D hwdesc->tr_req_base + tr_size; - - tr_desc =3D hwdesc->cppi5_desc_vaddr; - cppi5_trdesc_init(tr_desc, 1, tr_size, 0, 0); - cppi5_desc_set_pktids(tr_desc, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT); - cppi5_desc_set_retpolicy(tr_desc, 0, 0); - - tr_req =3D hwdesc->tr_req_base; - cppi5_tr_init(&tr_req->flags, CPPI5_TR_TYPE1, false, false, - CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - cppi5_tr_csf_set(&tr_req->flags, CPPI5_TR_CSF_SUPR_EVT); - - tr_req->addr =3D rx_flush->buffer_paddr; - tr_req->icnt0 =3D rx_flush->buffer_size; - tr_req->icnt1 =3D 1; - - dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr, - hwdesc->cppi5_desc_size, DMA_TO_DEVICE); - - /* Set up descriptor to be used for packet mode */ - hwdesc =3D &rx_flush->hwdescs[1]; - hwdesc->cppi5_desc_size =3D ALIGN(sizeof(struct cppi5_host_desc_t) + - CPPI5_INFO0_HDESC_EPIB_SIZE + - CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE, - ud->desc_align); - - hwdesc->cppi5_desc_vaddr =3D devm_kzalloc(dev, hwdesc->cppi5_desc_size, - GFP_KERNEL); - if (!hwdesc->cppi5_desc_vaddr) - return -ENOMEM; - - hwdesc->cppi5_desc_paddr =3D dma_map_single(dev, hwdesc->cppi5_desc_vaddr, - hwdesc->cppi5_desc_size, - DMA_TO_DEVICE); - if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr)) - return -ENOMEM; - - desc =3D hwdesc->cppi5_desc_vaddr; - cppi5_hdesc_init(desc, 0, 0); - cppi5_desc_set_pktids(&desc->hdr, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT); - cppi5_desc_set_retpolicy(&desc->hdr, 0, 0); - - cppi5_hdesc_attach_buf(desc, - rx_flush->buffer_paddr, rx_flush->buffer_size, - rx_flush->buffer_paddr, rx_flush->buffer_size); - - dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr, - hwdesc->cppi5_desc_size, DMA_TO_DEVICE); - return 0; -} - -#ifdef CONFIG_DEBUG_FS -static void udma_dbg_summary_show_chan(struct seq_file *s, - struct dma_chan *chan) -{ - struct udma_chan *uc =3D to_udma_chan(chan); - struct udma_chan_config *ucc =3D &uc->config; - - seq_printf(s, " %-13s| %s", dma_chan_name(chan), - chan->dbg_client_name ?: "in-use"); - if (ucc->tr_trigger_type) - seq_puts(s, " (triggered, "); - else - seq_printf(s, " (%s, ", - dmaengine_get_direction_text(uc->config.dir)); - - switch (uc->config.dir) { - case DMA_MEM_TO_MEM: - if (uc->ud->match_data->type =3D=3D DMA_TYPE_BCDMA) { - seq_printf(s, "bchan%d)\n", uc->bchan->id); - return; - } - - seq_printf(s, "chan%d pair [0x%04x -> 0x%04x], ", uc->tchan->id, - ucc->src_thread, ucc->dst_thread); - break; - case DMA_DEV_TO_MEM: - seq_printf(s, "rchan%d [0x%04x -> 0x%04x], ", uc->rchan->id, - ucc->src_thread, ucc->dst_thread); - if (uc->ud->match_data->type =3D=3D DMA_TYPE_PKTDMA) - seq_printf(s, "rflow%d, ", uc->rflow->id); - break; - case DMA_MEM_TO_DEV: - seq_printf(s, "tchan%d [0x%04x -> 0x%04x], ", uc->tchan->id, - ucc->src_thread, ucc->dst_thread); - if (uc->ud->match_data->type =3D=3D DMA_TYPE_PKTDMA) - seq_printf(s, "tflow%d, ", uc->tchan->tflow_id); - break; - default: - seq_printf(s, ")\n"); - return; - } - - if (ucc->ep_type =3D=3D PSIL_EP_NATIVE) { - seq_printf(s, "PSI-L Native"); - if (ucc->metadata_size) { - seq_printf(s, "[%s", ucc->needs_epib ? " EPIB" : ""); - if (ucc->psd_size) - seq_printf(s, " PSDsize:%u", ucc->psd_size); - seq_printf(s, " ]"); - } - } else { - seq_printf(s, "PDMA"); - if (ucc->enable_acc32 || ucc->enable_burst) - seq_printf(s, "[%s%s ]", - ucc->enable_acc32 ? " ACC32" : "", - ucc->enable_burst ? " BURST" : ""); - } - - seq_printf(s, ", %s)\n", ucc->pkt_mode ? "Packet mode" : "TR mode"); -} - -static void udma_dbg_summary_show(struct seq_file *s, - struct dma_device *dma_dev) -{ - struct dma_chan *chan; - - list_for_each_entry(chan, &dma_dev->channels, device_node) { - if (chan->client_count) - udma_dbg_summary_show_chan(s, chan); - } -} -#endif /* CONFIG_DEBUG_FS */ - -static enum dmaengine_alignment udma_get_copy_align(struct udma_dev *ud) -{ - const struct udma_match_data *match_data =3D ud->match_data; - u8 tpl; - - if (!match_data->enable_memcpy_support) - return DMAENGINE_ALIGN_8_BYTES; - - /* Get the highest TPL level the device supports for memcpy */ - if (ud->bchan_cnt) - tpl =3D udma_get_chan_tpl_index(&ud->bchan_tpl, 0); - else if (ud->tchan_cnt) - tpl =3D udma_get_chan_tpl_index(&ud->tchan_tpl, 0); - else - return DMAENGINE_ALIGN_8_BYTES; - - switch (match_data->burst_size[tpl]) { - case TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES: - return DMAENGINE_ALIGN_256_BYTES; - case TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES: - return DMAENGINE_ALIGN_128_BYTES; - case TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES: - fallthrough; - default: - return DMAENGINE_ALIGN_64_BYTES; - } -} - static int udma_probe(struct platform_device *pdev) { struct device_node *navss_node =3D pdev->dev.parent->of_node; diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h index 16de0b218d8ad..4878d13d84ed0 100644 --- a/drivers/dma/ti/k3-udma.h +++ b/drivers/dma/ti/k3-udma.h @@ -629,6 +629,34 @@ void udma_reset_rings(struct udma_chan *uc); =20 int navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread); int navss_psil_unpair(struct udma_dev *ud, u32 src_thread, u32 dst_thread); +void udma_start_desc(struct udma_chan *uc); +u8 udma_get_chan_tpl_index(struct udma_tpl *tpl_map, int chan_id); +void k3_configure_chan_coherency(struct dma_chan *chan, u32 asel); +void udma_reset_uchan(struct udma_chan *uc); +void udma_dump_chan_stdata(struct udma_chan *uc); +bool udma_is_chan_running(struct udma_chan *uc); + +bool udma_chan_needs_reconfiguration(struct udma_chan *uc); +void udma_cyclic_packet_elapsed(struct udma_chan *uc); +void udma_check_tx_completion(struct work_struct *work); +int udma_slave_config(struct dma_chan *chan, + struct dma_slave_config *cfg); +void udma_issue_pending(struct dma_chan *chan); +int udma_terminate_all(struct dma_chan *chan); +void udma_synchronize(struct dma_chan *chan); +void udma_vchan_complete(struct tasklet_struct *t); +void udma_mark_resource_ranges(struct udma_dev *ud, unsigned long *map, + struct ti_sci_resource_desc *rm_desc, + char *name); +int udma_setup_rx_flush(struct udma_dev *ud); +enum dmaengine_alignment udma_get_copy_align(struct udma_dev *ud); + +#ifdef CONFIG_DEBUG_FS +void udma_dbg_summary_show_chan(struct seq_file *s, + struct dma_chan *chan); +void udma_dbg_summary_show(struct seq_file *s, + struct dma_device *dma_dev); +#endif /* CONFIG_DEBUG_FS */ =20 /* Direct access to UDMA low lever resources for the glue layer */ int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thr= ead); --=20 2.54.0 From nobody Tue Sep 29 08:26:17 2026 Received: from mx0b-0002e601.pphosted.com (mx0b-0002e601.pphosted.com [148.163.154.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18275371895; Mon, 28 Sep 2026 02:59:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.154.28 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564365; cv=fail; b=WAAG3fQqhbwIP5dJbiiH0X5H6Kcos9+Zlp9s6sS6CTBJHTVDpW10k8EhNVZIziG2HMmawumvIxIm+jfv5Ox6EWIXPL5LanTEYMxxgdzDqf0FUiCkoshj8edSClcNPc7ciGC0OYCc5RbOmOYl0fA1gthbjQVEehJ+MBBUvYKLVZs= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564365; c=relaxed/simple; bh=3qAjKuu7BBHPqWb2rrF3pmtgChauMAgmrOONQXSywDQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YWYK3TxZu7TtqmdgLQ29oqNI4TP4xUsPiQFJW2ttHDWrkcriTutIHw6DEqhNmeylqLvX+nxAXRGt1A52kh9ValN5XCkom5h/mo6HFdciI9WDVxuCT57v03n3Qgbt7KLe5yQE5qIJJinCNH0DAB8t+9Lp8tf8sDrpGgAUXDrVBq8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=Tx2uSNJC; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=VBRPL8YN; arc=fail smtp.client-ip=148.163.154.28 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="Tx2uSNJC"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="VBRPL8YN" Received: from pps.filterd (m0374955.ppops.net [127.0.0.1]) by mx0b-0002e601.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68RKP2Br2807075; Sun, 27 Sep 2026 21:59:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=CpaO3ZkhzfTUqtlNX7D2ZF8DKvExXHd+0jazA8xEy +g=; b=Tx2uSNJCsC9Xr+NP3Md/PzrFJFRc4+k1OaVxVIY0LKg2g0sl1mOHjhGxk 8D8VagG9UX88tCO0E7SjkXAP0Fh+8yOCZDkbYXy8N1LR+Bdq7uXOGukHDW6BLLJn mTqvOdOaTLLWlWHQQe22SLREKBdCWNun3hgDFjki7RyAqnjEnQ97gOFmVaJ48t3S T7G/1GHJbVh6x/2ncDq3zbNc9aP1mYPNL3ZUDX2ozz/B8S2pOq5Etk9DhSmPIYlJ kl0tZX/TQuZqdKhN090q4H9HZYTyRqu58wRQ49N2RHCMshNAeuvowBX6gespK1b0 RKTtYpNaIdmJQu7nuFtmjYnsUOrxg== Received: from cy3pr05cu001.outbound.protection.outlook.com (mail-westcentralusazon11013052.outbound.protection.outlook.com [40.93.201.52]) by mx0b-0002e601.pphosted.com (PPS) with ESMTPS id 4gxwe5kfr8-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Sun, 27 Sep 2026 21:59:13 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=eGTIK+e4HRC62gOkUl5IT7N7LFqSyCweCTLQWeWSmQfS91Uq7nv0L/85OfVyLYrosZzkHpx69wJfVY3XfSvdQZmsRr9BHXbI9+yuS+lUbt7G49JzcLz+dPnbXVEU5RVcRSM/bDZkGdsLyzpk8Ga7iklwelMJd073jNoPPvjDgbEWuyejSZ3jTsdv/EyUSVVP9RS5huDsEAliQmlAqY08wUc428NsoeL7Whmip75skoHenn/j5cRTz/1D+2gDi3nz8uU6qUC3TC2U4RwSfYTQ0r6BA64N8sM5HeXpO8azkw/w9cYh8BBvIByXlpcB89LJx97e7VP488rrglpxRDq4dA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=CpaO3ZkhzfTUqtlNX7D2ZF8DKvExXHd+0jazA8xEy+g=; b=UqTOTKjxBiodsZ1mmDsjg0lYE0y6j4/UueRleULn5ElAJ0mGvmZOIQ0ihN154VGroV/r3f89BdQ4DSU2dskAif+qmzqbYCXzISqSRj2XW0I7FCTBbBJNV3UWYT46LtCZuGFJshZ7eWeHcFvpOBLA92J9sygmUx1YPdYI9IjSulM1NDt59e2NPIL4no6zHDo0dcfaVWwIEI82BgR9xDqnCHLZFjkj1HEebBdi+woZWcPWKJGvuvE4f78dkn1nBAZcydPR27X13YnyV5BFy6M1uuFY6queQLsSPn04ihzuYk6EfcPLXZoi9khf3mPC/A9vKJ4+8V6SFDyZrR+3cMkCig== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.21.194) smtp.rcpttodomain=nxp.com smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CpaO3ZkhzfTUqtlNX7D2ZF8DKvExXHd+0jazA8xEy+g=; b=VBRPL8YNc791of1bWai7AOTA+1E3tuwS3cJlnBPoL0eWWCiogrOtkhRRE97rm9PzL9olC8uxPvShKa1gh81SCcq/YzLgM1AUbSQPUb3tpKRjXp6Vcj7D2BFzaMdDSGJcEkyEdpgZ34SxheuTfM63qb95QW7VYx/rGGlTwSOoH/w= Received: from DM6PR05CA0042.namprd05.prod.outlook.com (2603:10b6:5:335::11) by DS4PR10MB997768.namprd10.prod.outlook.com (2603:10b6:8:34b::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.451.18; Mon, 28 Sep 2026 02:59:09 +0000 Received: from DS2PEPF000061C8.namprd02.prod.outlook.com (2603:10b6:5:335:cafe::8f) by DM6PR05CA0042.outlook.office365.com (2603:10b6:5:335::11) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Mon, 28 Sep 2026 02:59:09 +0000 X-MS-Exchange-Authentication-Results: mx.microsoft.com 1; spf=pass (sender IP is 198.47.21.194) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.21.194 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.21.194; helo=flwvzet200.ext.ti.com; pr=C Received: from flwvzet200.ext.ti.com (198.47.21.194) by DS2PEPF000061C8.mail.protection.outlook.com (10.167.23.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Mon, 28 Sep 2026 02:59:07 +0000 Received: from DFLE212.ent.ti.com (10.64.6.70) by flwvzet200.ext.ti.com (10.248.192.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:40 -0500 Received: from DFLE206.ent.ti.com (10.64.6.64) by DFLE212.ent.ti.com (10.64.6.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:40 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE206.ent.ti.com (10.64.6.64) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45 via Frontend Transport; Sun, 27 Sep 2026 21:58:40 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [10.24.51.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 68S2vqqG2256662; Sun, 27 Sep 2026 21:58:36 -0500 From: Sai Sree Kartheek Adivi To: , , , , , , , , , , , , , CC: , Subject: [PATCH v10 09/19] dmaengine: ti: k3-udma: move resource management functions to k3-udma-common.c Date: Mon, 28 Sep 2026 08:26:15 +0530 Message-ID: <20260928025749.1055383-10-s-adivi@ti.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260928025749.1055383-1-s-adivi@ti.com> References: <20260928025749.1055383-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF000061C8:EE_|DS4PR10MB997768:EE_ X-MS-Office365-Filtering-Correlation-Id: dbfc5aaf-e518-4c6b-42ad-08df1d0c76cb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|36860700016|82310400026|23010399003|921020|6133799003|3023799007|10067099003|56012099006|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: lUtYP89Cax4knDC3mjg09cOrKwGPijy/xUcZKRSK4CrIPiyp1d9bBSLOaNdIEHNBFIOLR9Jp0M9U2pMdJ/ufxUOILbh5EmSiENtaV9QfoOwhg5RJFIOpbmdlU+ZiaWnjAtHR8fBWwwcU6BNepdC0YSSMCY1h8t15XPmDrmx7cAutaGIc3mHoxsBmjuMiQdgJbIXA2Wre2Iq57jBSRzlC5F27ordxV0KHZ2SQi1JkA7HDOICYRhV0+XEg6kwXFYz1Pavpo6zOcITGlREEiqpmRzJ+CTDkNu7Fdse9Lu3rpAOoQ2MBavN5w/wx53zJxXfv7mck07S3ceaycnt9RY6jKodOWDHdljjvznfxokqanz2A7uBYTYEJQxkmMqnQY0qHkIMEtw0SJLjChsYXYt+mwfoa0+YD/2x/lJUuF6ZrSIF6CmB+cMSxB09F4iW2z0lvhy2MAOJYvALSFQHaFSCdizTqe96k8aEljUAtUuSwV5pplQMlx+AN+excayC2Q3mBWiMYv53fNjfHii/O9cUPzF1s91uafzlf8+9PP8VAm2EzHEGpZ7NNGt6kJ76hBk114Y/dkPY7C4E0Misod3Sl8+U+z+lkR4w1dD6tNFpDSHntkX04l2jpnCMBNGOdrx7Hf0IvxHb1CXl35jClBQ2NaV3F8dgg1Fqt6mXeefuAn9N1uET8YyRgGspdnyi82EofQl/RoPx8VPGYUbs7qCa7KjleD5bTtOWIQKaIDMyXpOpOUUoEmdlwMuP+a3I88imy X-Forefront-Antispam-Report: CIP:198.47.21.194;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:flwvzet200.ext.ti.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(36860700016)(82310400026)(23010399003)(921020)(6133799003)(3023799007)(10067099003)(56012099006)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: FXwTee86XPqslFGdEM9OgEqzXyzc9vDGOe1iuI+ty9R7XM6MdW935jL/rWXbpSfoK7yUBSvJGs1EzKRHr9Is0VcQV31vp/L8fPLWXD2kLx37YKP1C2aoBbHBvt+BIR1sEvpK6vdTdWqspoflOLSYa5UZkPpP39rEUFxYIKT8t+6THPGvXq6vbm4DcyKW+JGh8a9xz7iiPT9FzeC1XmnolXFFkJ04eXKBpHQhkyVY1N6Djgd2vKD6ntGDrgf5iWTxN6XSDyvi4of6WuYpWoTtO8mLaTWZMe+yggPpIIqG8omcakqi/JfkXv4AQPxhbVW+kyFFU3AvHJqTsDllwxQ/l9U5vDD3ZLHfP3OHs2XQXE7sISaqNMCvFzvIbG2wAs7p6eTgfZJXaBvpAJwJ/LeERpJmYgZOwnQ601ojy4Z9757VxWabJGGcPoLmAkrfUlvE X-Exchange-RoutingPolicyChecked: rgFjAz0az0vIHEJ8EwAjnZKi4jGK/34dgB+WBNp/xi1uXY+ktRTmMPPP9WxMdjl93ZO+Cy8tHWIQNLJ6/TGI/4sTOY3HKop0luP1nOehoUhxo08Jg90ISHcdWEKXgC4mcAVI2XqfH8gSVbxFx3qQGXHiC+mRZDtWRsXyIq8ejZHVrDnXKB57FkYQ72KuahIQPnxDKpAdk7dmJX7FBhjnWn5yRwy9wJgSrtnim1u92tDvqo6GHpClu2lFRRxb4qUAnKA65YtI51HGAlMXm/UMHLQftIG2HmniOB/IoztZrkvmREWytzHVOM5XU9HCsS24h7LAO/BD21cYT6pyM20Jrw== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 02:59:07.8844 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dbfc5aaf-e518-4c6b-42ad-08df1d0c76cb X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF000061C8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR10MB997768 X-Authority-Analysis: v=2.4 cv=aeP0Dhot c=1 sm=1 tr=0 ts=6ab9d801 cx=c_pps a=MYN/bj0IIkanzoD+9X5qzA==:117 a=iwqwCZQqcuTv3JOpYdM7/Q==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=VdqzKS8jKosA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=fPAWb5peG099m5CrUpKH:22 a=sozttTNsAAAA:8 a=AMbNDxq4J1R_ZtRBPm4A:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX/AZwUIZvcImK 1u2HCJGbh98LWfCIMyJMooOY2F7zitXEXGs9DJj+b4KuYJ98+4SFD6lXaLvzHtuoUne7gRpkiur idbZj9glJc4u/gs5t/VmBN7TWKlpdf8FVDnhai9Au8QcBPfoNHhN7Gc6Bd6h7ZaMl4GmCb6P5us QrgvvJIy+2JgpaLw+yYRwbrtNH4E40IcIMLz78NO1M04SMWl8UKt3q00sOm9fSxix7OLL4XF1bK 3bU2o+1+/LWUjqN0m1H47XTCANWCtk8jKXrDg5kMM2miHeGi8h4OAwfdA84XyJlH23Brn/sJ9dR RgaLOTHJ2XelyoUu1WMq7EXIxd2/mtsbCGvt7Qk8a87CaEQigCjRybhfYE9J+iRs1dAa21ArF+m 5hob//RK2L3H/ONHEV+oZKM6xrrTNFWtx2pVeJikfTySlxk1vOCBlIS+q96uHXUWatdyX+YHXVb xcuMnxb4zney6PMT/iQ== X-Proofpoint-ORIG-GUID: 5bNk7CRvgcWyOYG81BhITze2rOnyfjor X-Proofpoint-GUID: 5bNk7CRvgcWyOYG81BhITze2rOnyfjor X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfXxJ6yyDv6pydX Sv9iif598XO2Y5R+WogdquqKxKink6UF0XZHgaTWJJ344wlEQ2YlszA+SC2fOnnjZOpKP6Jeoet M4ySWoDLQJwOthiiwH64A1WG+J2zbQ4= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 phishscore=0 spamscore=0 clxscore=1015 adultscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280011 Content-Type: text/plain; charset="utf-8" Move functions responsible for allocation and release of udma resources such as channels, rings and flows from k3-udma.c to the common k3-udma-common.c file. The implementation of these functions is largely shared between K3 UDMA and K3 UDMA v2. This refactor improves code reuse and maintainability across multiple variants. No functional changes intended. Signed-off-by: Sai Sree Kartheek Adivi --- drivers/dma/ti/k3-udma-common.c | 443 ++++++++++++++++++++++++++++++++ drivers/dma/ti/k3-udma.c | 423 ------------------------------ drivers/dma/ti/k3-udma.h | 21 ++ 3 files changed, 464 insertions(+), 423 deletions(-) diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-commo= n.c index dbd667d77f137..34f8eab9ddb57 100644 --- a/drivers/dma/ti/k3-udma-common.c +++ b/drivers/dma/ti/k3-udma-common.c @@ -1891,5 +1891,448 @@ enum dmaengine_alignment udma_get_copy_align(struct= udma_dev *ud) } EXPORT_SYMBOL_GPL(udma_get_copy_align); =20 +/** + * __udma_alloc_gp_rflow_range - alloc range of GP RX flows + * @ud: UDMA device + * @from: Start the search from this flow id number + * @cnt: Number of consecutive flow ids to allocate + * + * Allocate range of RX flow ids for future use, those flows can be reques= ted + * only using explicit flow id number. if @from is set to -1 it will try t= o find + * first free range. if @from is positive value it will force allocation o= nly + * of the specified range of flows. + * + * Returns -ENOMEM if can't find free range. + * -EEXIST if requested range is busy. + * -EINVAL if wrong input values passed. + * Returns flow id on success. + */ +int __udma_alloc_gp_rflow_range(struct udma_dev *ud, int from, int cnt) +{ + int start, tmp_from; + DECLARE_BITMAP(tmp, K3_UDMA_MAX_RFLOWS); + + tmp_from =3D from; + if (tmp_from < 0) + tmp_from =3D ud->rchan_cnt; + /* default flows can't be allocated and accessible only by id */ + if (tmp_from < ud->rchan_cnt) + return -EINVAL; + + if (tmp_from + cnt > ud->rflow_cnt) + return -EINVAL; + + bitmap_or(tmp, ud->rflow_gp_map, ud->rflow_gp_map_allocated, + ud->rflow_cnt); + + start =3D bitmap_find_next_zero_area(tmp, + ud->rflow_cnt, + tmp_from, cnt, 0); + if (start >=3D ud->rflow_cnt) + return -ENOMEM; + + if (from >=3D 0 && start !=3D from) + return -EEXIST; + + bitmap_set(ud->rflow_gp_map_allocated, start, cnt); + return start; +} +EXPORT_SYMBOL_GPL(__udma_alloc_gp_rflow_range); + +int __udma_free_gp_rflow_range(struct udma_dev *ud, int from, int cnt) +{ + if (from < ud->rchan_cnt) + return -EINVAL; + if (from + cnt > ud->rflow_cnt) + return -EINVAL; + + bitmap_clear(ud->rflow_gp_map_allocated, from, cnt); + return 0; +} +EXPORT_SYMBOL_GPL(__udma_free_gp_rflow_range); + +struct udma_rflow *__udma_get_rflow(struct udma_dev *ud, int id) +{ + /* + * Attempt to request rflow by ID can be made for any rflow + * if not in use with assumption that caller knows what's doing. + * TI-SCI FW will perform additional permission check ant way, it's + * safe + */ + + if (id < 0 || id >=3D ud->rflow_cnt) + return ERR_PTR(-ENOENT); + + if (test_bit(id, ud->rflow_in_use)) + return ERR_PTR(-ENOENT); + + if (ud->rflow_gp_map) { + /* GP rflow has to be allocated first */ + if (!test_bit(id, ud->rflow_gp_map) && + !test_bit(id, ud->rflow_gp_map_allocated)) + return ERR_PTR(-EINVAL); + } + + dev_dbg(ud->dev, "get rflow%d\n", id); + set_bit(id, ud->rflow_in_use); + return &ud->rflows[id]; +} +EXPORT_SYMBOL_GPL(__udma_get_rflow); + +void __udma_put_rflow(struct udma_dev *ud, struct udma_rflow *rflow) +{ + if (!test_bit(rflow->id, ud->rflow_in_use)) { + dev_err(ud->dev, "attempt to put unused rflow%d\n", rflow->id); + return; + } + + dev_dbg(ud->dev, "put rflow%d\n", rflow->id); + clear_bit(rflow->id, ud->rflow_in_use); +} +EXPORT_SYMBOL_GPL(__udma_put_rflow); + +#define UDMA_RESERVE_RESOURCE(res) \ +struct udma_##res *__udma_reserve_##res(struct udma_dev *ud, \ + enum udma_tp_level tpl, \ + int id) \ +{ \ + if (id >=3D 0) { \ + if (test_bit(id, ud->res##_map)) { \ + dev_err(ud->dev, "res##%d is in use\n", id); \ + return ERR_PTR(-ENOENT); \ + } \ + } else { \ + int start; \ + \ + if (tpl >=3D ud->res##_tpl.levels) \ + tpl =3D ud->res##_tpl.levels - 1; \ + \ + start =3D ud->res##_tpl.start_idx[tpl]; \ + \ + id =3D find_next_zero_bit(ud->res##_map, ud->res##_cnt, \ + start); \ + if (id =3D=3D ud->res##_cnt) { \ + return ERR_PTR(-ENOENT); \ + } \ + } \ + \ + set_bit(id, ud->res##_map); \ + return &ud->res##s[id]; \ +} + +UDMA_RESERVE_RESOURCE(bchan); +EXPORT_SYMBOL_GPL(__udma_reserve_bchan); +UDMA_RESERVE_RESOURCE(tchan); +EXPORT_SYMBOL_GPL(__udma_reserve_tchan); +UDMA_RESERVE_RESOURCE(rchan); +EXPORT_SYMBOL_GPL(__udma_reserve_rchan); + +int udma_get_tchan(struct udma_chan *uc) +{ + struct udma_dev *ud =3D uc->ud; + int ret; + + if (uc->tchan) { + dev_dbg(ud->dev, "chan%d: already have tchan%d allocated\n", + uc->id, uc->tchan->id); + return 0; + } + + /* + * mapped_channel_id is -1 for UDMA, BCDMA and PKTDMA unmapped channels. + * For PKTDMA mapped channels it is configured to a channel which must + * be used to service the peripheral. + */ + uc->tchan =3D __udma_reserve_tchan(ud, uc->config.channel_tpl, + uc->config.mapped_channel_id); + if (IS_ERR(uc->tchan)) { + ret =3D PTR_ERR(uc->tchan); + uc->tchan =3D NULL; + return ret; + } + + if (ud->tflow_cnt) { + int tflow_id; + + /* Only PKTDMA have support for tx flows */ + if (uc->config.default_flow_id >=3D 0) + tflow_id =3D uc->config.default_flow_id; + else + tflow_id =3D uc->tchan->id; + + if (test_bit(tflow_id, ud->tflow_map)) { + dev_err(ud->dev, "tflow%d is in use\n", tflow_id); + clear_bit(uc->tchan->id, ud->tchan_map); + uc->tchan =3D NULL; + return -ENOENT; + } + + uc->tchan->tflow_id =3D tflow_id; + set_bit(tflow_id, ud->tflow_map); + } else { + uc->tchan->tflow_id =3D -1; + } + + return 0; +} +EXPORT_SYMBOL_GPL(udma_get_tchan); + +int udma_get_rchan(struct udma_chan *uc) +{ + struct udma_dev *ud =3D uc->ud; + int ret; + + if (uc->rchan) { + dev_dbg(ud->dev, "chan%d: already have rchan%d allocated\n", + uc->id, uc->rchan->id); + return 0; + } + + /* + * mapped_channel_id is -1 for UDMA, BCDMA and PKTDMA unmapped channels. + * For PKTDMA mapped channels it is configured to a channel which must + * be used to service the peripheral. + */ + uc->rchan =3D __udma_reserve_rchan(ud, uc->config.channel_tpl, + uc->config.mapped_channel_id); + if (IS_ERR(uc->rchan)) { + ret =3D PTR_ERR(uc->rchan); + uc->rchan =3D NULL; + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(udma_get_rchan); + +int udma_get_chan_pair(struct udma_chan *uc) +{ + struct udma_dev *ud =3D uc->ud; + int chan_id, end; + + if ((uc->tchan && uc->rchan) && uc->tchan->id =3D=3D uc->rchan->id) { + dev_info(ud->dev, "chan%d: already have %d pair allocated\n", + uc->id, uc->tchan->id); + return 0; + } + + if (uc->tchan) { + dev_err(ud->dev, "chan%d: already have tchan%d allocated\n", + uc->id, uc->tchan->id); + return -EBUSY; + } else if (uc->rchan) { + dev_err(ud->dev, "chan%d: already have rchan%d allocated\n", + uc->id, uc->rchan->id); + return -EBUSY; + } + + /* Can be optimized, but let's have it like this for now */ + end =3D min(ud->tchan_cnt, ud->rchan_cnt); + /* + * Try to use the highest TPL channel pair for MEM_TO_MEM channels + * Note: in UDMAP the channel TPL is symmetric between tchan and rchan + */ + chan_id =3D ud->tchan_tpl.start_idx[ud->tchan_tpl.levels - 1]; + for (; chan_id < end; chan_id++) { + if (!test_bit(chan_id, ud->tchan_map) && + !test_bit(chan_id, ud->rchan_map)) + break; + } + + if (chan_id =3D=3D end) + return -ENOENT; + + set_bit(chan_id, ud->tchan_map); + set_bit(chan_id, ud->rchan_map); + uc->tchan =3D &ud->tchans[chan_id]; + uc->rchan =3D &ud->rchans[chan_id]; + + /* UDMA does not use tx flows */ + uc->tchan->tflow_id =3D -1; + + return 0; +} +EXPORT_SYMBOL_GPL(udma_get_chan_pair); + +int udma_get_rflow(struct udma_chan *uc, int flow_id) +{ + struct udma_dev *ud =3D uc->ud; + int ret; + + if (!uc->rchan) { + dev_err(ud->dev, "chan%d: does not have rchan??\n", uc->id); + return -EINVAL; + } + + if (uc->rflow) { + dev_dbg(ud->dev, "chan%d: already have rflow%d allocated\n", + uc->id, uc->rflow->id); + return 0; + } + + uc->rflow =3D __udma_get_rflow(ud, flow_id); + if (IS_ERR(uc->rflow)) { + ret =3D PTR_ERR(uc->rflow); + uc->rflow =3D NULL; + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(udma_get_rflow); + +void udma_put_rchan(struct udma_chan *uc) +{ + struct udma_dev *ud =3D uc->ud; + + if (uc->rchan) { + dev_dbg(ud->dev, "chan%d: put rchan%d\n", uc->id, + uc->rchan->id); + clear_bit(uc->rchan->id, ud->rchan_map); + uc->rchan =3D NULL; + } +} +EXPORT_SYMBOL_GPL(udma_put_rchan); + +void udma_put_tchan(struct udma_chan *uc) +{ + struct udma_dev *ud =3D uc->ud; + + if (uc->tchan) { + dev_dbg(ud->dev, "chan%d: put tchan%d\n", uc->id, + uc->tchan->id); + clear_bit(uc->tchan->id, ud->tchan_map); + + if (uc->tchan->tflow_id >=3D 0) + clear_bit(uc->tchan->tflow_id, ud->tflow_map); + + uc->tchan =3D NULL; + } +} +EXPORT_SYMBOL_GPL(udma_put_tchan); + +void udma_put_rflow(struct udma_chan *uc) +{ + struct udma_dev *ud =3D uc->ud; + + if (uc->rflow) { + dev_dbg(ud->dev, "chan%d: put rflow%d\n", uc->id, + uc->rflow->id); + __udma_put_rflow(ud, uc->rflow); + uc->rflow =3D NULL; + } +} +EXPORT_SYMBOL_GPL(udma_put_rflow); + +void udma_free_tx_resources(struct udma_chan *uc) +{ + if (!uc->tchan) + return; + + k3_ringacc_ring_free(uc->tchan->t_ring); + k3_ringacc_ring_free(uc->tchan->tc_ring); + uc->tchan->t_ring =3D NULL; + uc->tchan->tc_ring =3D NULL; + + udma_put_tchan(uc); +} +EXPORT_SYMBOL_GPL(udma_free_tx_resources); + +void udma_free_rx_resources(struct udma_chan *uc) +{ + if (!uc->rchan) + return; + + if (uc->rflow) { + struct udma_rflow *rflow =3D uc->rflow; + + k3_ringacc_ring_free(rflow->fd_ring); + k3_ringacc_ring_free(rflow->r_ring); + rflow->fd_ring =3D NULL; + rflow->r_ring =3D NULL; + + udma_put_rflow(uc); + } + + udma_put_rchan(uc); +} +EXPORT_SYMBOL_GPL(udma_free_rx_resources); + +void udma_free_chan_resources(struct dma_chan *chan) +{ + struct udma_chan *uc =3D to_udma_chan(chan); + struct udma_dev *ud =3D to_udma_dev(chan->device); + + udma_terminate_all(chan); + if (uc->terminated_desc) { + ud->reset_chan(uc, false); + udma_reset_rings(uc); + } + + cancel_delayed_work_sync(&uc->tx_drain.work); + + if (uc->irq_num_ring > 0) { + free_irq(uc->irq_num_ring, uc); + + uc->irq_num_ring =3D 0; + } + if (uc->irq_num_udma > 0) { + free_irq(uc->irq_num_udma, uc); + + uc->irq_num_udma =3D 0; + } + + /* Release PSI-L pairing */ + if (uc->psil_paired) { + if (ud->psil_unpair) + ud->psil_unpair(ud, uc->config.src_thread, + uc->config.dst_thread); + uc->psil_paired =3D false; + } + + vchan_free_chan_resources(&uc->vc); + tasklet_kill(&uc->vc.task); + + bcdma_free_bchan_resources(uc); + udma_free_tx_resources(uc); + udma_free_rx_resources(uc); + udma_reset_uchan(uc); + + if (uc->use_dma_pool) { + dma_pool_destroy(uc->hdesc_pool); + uc->use_dma_pool =3D false; + } +} +EXPORT_SYMBOL_GPL(udma_free_chan_resources); + +void bcdma_put_bchan(struct udma_chan *uc) +{ + struct udma_dev *ud =3D uc->ud; + + if (uc->bchan) { + dev_dbg(ud->dev, "chan%d: put bchan%d\n", uc->id, + uc->bchan->id); + clear_bit(uc->bchan->id, ud->bchan_map); + uc->bchan =3D NULL; + uc->tchan =3D NULL; + } +} +EXPORT_SYMBOL_GPL(bcdma_put_bchan); + +void bcdma_free_bchan_resources(struct udma_chan *uc) +{ + if (!uc->bchan) + return; + + k3_ringacc_ring_free(uc->bchan->tc_ring); + k3_ringacc_ring_free(uc->bchan->t_ring); + uc->bchan->tc_ring =3D NULL; + uc->bchan->t_ring =3D NULL; + k3_configure_chan_coherency(&uc->vc.chan, 0); + + bcdma_put_bchan(uc); +} +EXPORT_SYMBOL_GPL(bcdma_free_bchan_resources); + MODULE_DESCRIPTION("Texas Instruments K3 UDMA Common Library"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index cd73bf03e9cc6..21978f17e327f 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -423,135 +423,6 @@ static irqreturn_t udma_udma_irq_handler(int irq, voi= d *data) return IRQ_HANDLED; } =20 -/** - * __udma_alloc_gp_rflow_range - alloc range of GP RX flows - * @ud: UDMA device - * @from: Start the search from this flow id number - * @cnt: Number of consecutive flow ids to allocate - * - * Allocate range of RX flow ids for future use, those flows can be reques= ted - * only using explicit flow id number. if @from is set to -1 it will try t= o find - * first free range. if @from is positive value it will force allocation o= nly - * of the specified range of flows. - * - * Returns -ENOMEM if can't find free range. - * -EEXIST if requested range is busy. - * -EINVAL if wrong input values passed. - * Returns flow id on success. - */ -static int __udma_alloc_gp_rflow_range(struct udma_dev *ud, int from, int = cnt) -{ - int start, tmp_from; - DECLARE_BITMAP(tmp, K3_UDMA_MAX_RFLOWS); - - tmp_from =3D from; - if (tmp_from < 0) - tmp_from =3D ud->rchan_cnt; - /* default flows can't be allocated and accessible only by id */ - if (tmp_from < ud->rchan_cnt) - return -EINVAL; - - if (tmp_from + cnt > ud->rflow_cnt) - return -EINVAL; - - bitmap_or(tmp, ud->rflow_gp_map, ud->rflow_gp_map_allocated, - ud->rflow_cnt); - - start =3D bitmap_find_next_zero_area(tmp, - ud->rflow_cnt, - tmp_from, cnt, 0); - if (start >=3D ud->rflow_cnt) - return -ENOMEM; - - if (from >=3D 0 && start !=3D from) - return -EEXIST; - - bitmap_set(ud->rflow_gp_map_allocated, start, cnt); - return start; -} - -static int __udma_free_gp_rflow_range(struct udma_dev *ud, int from, int c= nt) -{ - if (from < ud->rchan_cnt) - return -EINVAL; - if (from + cnt > ud->rflow_cnt) - return -EINVAL; - - bitmap_clear(ud->rflow_gp_map_allocated, from, cnt); - return 0; -} - -static struct udma_rflow *__udma_get_rflow(struct udma_dev *ud, int id) -{ - /* - * Attempt to request rflow by ID can be made for any rflow - * if not in use with assumption that caller knows what's doing. - * TI-SCI FW will perform additional permission check ant way, it's - * safe - */ - - if (id < 0 || id >=3D ud->rflow_cnt) - return ERR_PTR(-ENOENT); - - if (test_bit(id, ud->rflow_in_use)) - return ERR_PTR(-ENOENT); - - if (ud->rflow_gp_map) { - /* GP rflow has to be allocated first */ - if (!test_bit(id, ud->rflow_gp_map) && - !test_bit(id, ud->rflow_gp_map_allocated)) - return ERR_PTR(-EINVAL); - } - - dev_dbg(ud->dev, "get rflow%d\n", id); - set_bit(id, ud->rflow_in_use); - return &ud->rflows[id]; -} - -static void __udma_put_rflow(struct udma_dev *ud, struct udma_rflow *rflow) -{ - if (!test_bit(rflow->id, ud->rflow_in_use)) { - dev_err(ud->dev, "attempt to put unused rflow%d\n", rflow->id); - return; - } - - dev_dbg(ud->dev, "put rflow%d\n", rflow->id); - clear_bit(rflow->id, ud->rflow_in_use); -} - -#define UDMA_RESERVE_RESOURCE(res) \ -static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud, \ - enum udma_tp_level tpl, \ - int id) \ -{ \ - if (id >=3D 0) { \ - if (test_bit(id, ud->res##_map)) { \ - dev_err(ud->dev, "res##%d is in use\n", id); \ - return ERR_PTR(-ENOENT); \ - } \ - } else { \ - int start; \ - \ - if (tpl >=3D ud->res##_tpl.levels) \ - tpl =3D ud->res##_tpl.levels - 1; \ - \ - start =3D ud->res##_tpl.start_idx[tpl]; \ - \ - id =3D find_next_zero_bit(ud->res##_map, ud->res##_cnt, \ - start); \ - if (id =3D=3D ud->res##_cnt) { \ - return ERR_PTR(-ENOENT); \ - } \ - } \ - \ - set_bit(id, ud->res##_map); \ - return &ud->res##s[id]; \ -} - -UDMA_RESERVE_RESOURCE(bchan); -UDMA_RESERVE_RESOURCE(tchan); -UDMA_RESERVE_RESOURCE(rchan); - static int bcdma_get_bchan(struct udma_chan *uc) { struct udma_dev *ud =3D uc->ud; @@ -585,223 +456,6 @@ static int bcdma_get_bchan(struct udma_chan *uc) return 0; } =20 -static int udma_get_tchan(struct udma_chan *uc) -{ - struct udma_dev *ud =3D uc->ud; - int ret; - - if (uc->tchan) { - dev_dbg(ud->dev, "chan%d: already have tchan%d allocated\n", - uc->id, uc->tchan->id); - return 0; - } - - /* - * mapped_channel_id is -1 for UDMA, BCDMA and PKTDMA unmapped channels. - * For PKTDMA mapped channels it is configured to a channel which must - * be used to service the peripheral. - */ - uc->tchan =3D __udma_reserve_tchan(ud, uc->config.channel_tpl, - uc->config.mapped_channel_id); - if (IS_ERR(uc->tchan)) { - ret =3D PTR_ERR(uc->tchan); - uc->tchan =3D NULL; - return ret; - } - - if (ud->tflow_cnt) { - int tflow_id; - - /* Only PKTDMA have support for tx flows */ - if (uc->config.default_flow_id >=3D 0) - tflow_id =3D uc->config.default_flow_id; - else - tflow_id =3D uc->tchan->id; - - if (test_bit(tflow_id, ud->tflow_map)) { - dev_err(ud->dev, "tflow%d is in use\n", tflow_id); - clear_bit(uc->tchan->id, ud->tchan_map); - uc->tchan =3D NULL; - return -ENOENT; - } - - uc->tchan->tflow_id =3D tflow_id; - set_bit(tflow_id, ud->tflow_map); - } else { - uc->tchan->tflow_id =3D -1; - } - - return 0; -} - -static int udma_get_rchan(struct udma_chan *uc) -{ - struct udma_dev *ud =3D uc->ud; - int ret; - - if (uc->rchan) { - dev_dbg(ud->dev, "chan%d: already have rchan%d allocated\n", - uc->id, uc->rchan->id); - return 0; - } - - /* - * mapped_channel_id is -1 for UDMA, BCDMA and PKTDMA unmapped channels. - * For PKTDMA mapped channels it is configured to a channel which must - * be used to service the peripheral. - */ - uc->rchan =3D __udma_reserve_rchan(ud, uc->config.channel_tpl, - uc->config.mapped_channel_id); - if (IS_ERR(uc->rchan)) { - ret =3D PTR_ERR(uc->rchan); - uc->rchan =3D NULL; - return ret; - } - - return 0; -} - -static int udma_get_chan_pair(struct udma_chan *uc) -{ - struct udma_dev *ud =3D uc->ud; - int chan_id, end; - - if ((uc->tchan && uc->rchan) && uc->tchan->id =3D=3D uc->rchan->id) { - dev_info(ud->dev, "chan%d: already have %d pair allocated\n", - uc->id, uc->tchan->id); - return 0; - } - - if (uc->tchan) { - dev_err(ud->dev, "chan%d: already have tchan%d allocated\n", - uc->id, uc->tchan->id); - return -EBUSY; - } else if (uc->rchan) { - dev_err(ud->dev, "chan%d: already have rchan%d allocated\n", - uc->id, uc->rchan->id); - return -EBUSY; - } - - /* Can be optimized, but let's have it like this for now */ - end =3D min(ud->tchan_cnt, ud->rchan_cnt); - /* - * Try to use the highest TPL channel pair for MEM_TO_MEM channels - * Note: in UDMAP the channel TPL is symmetric between tchan and rchan - */ - chan_id =3D ud->tchan_tpl.start_idx[ud->tchan_tpl.levels - 1]; - for (; chan_id < end; chan_id++) { - if (!test_bit(chan_id, ud->tchan_map) && - !test_bit(chan_id, ud->rchan_map)) - break; - } - - if (chan_id =3D=3D end) - return -ENOENT; - - set_bit(chan_id, ud->tchan_map); - set_bit(chan_id, ud->rchan_map); - uc->tchan =3D &ud->tchans[chan_id]; - uc->rchan =3D &ud->rchans[chan_id]; - - /* UDMA does not use tx flows */ - uc->tchan->tflow_id =3D -1; - - return 0; -} - -static int udma_get_rflow(struct udma_chan *uc, int flow_id) -{ - struct udma_dev *ud =3D uc->ud; - int ret; - - if (!uc->rchan) { - dev_err(ud->dev, "chan%d: does not have rchan??\n", uc->id); - return -EINVAL; - } - - if (uc->rflow) { - dev_dbg(ud->dev, "chan%d: already have rflow%d allocated\n", - uc->id, uc->rflow->id); - return 0; - } - - uc->rflow =3D __udma_get_rflow(ud, flow_id); - if (IS_ERR(uc->rflow)) { - ret =3D PTR_ERR(uc->rflow); - uc->rflow =3D NULL; - return ret; - } - - return 0; -} - -static void bcdma_put_bchan(struct udma_chan *uc) -{ - struct udma_dev *ud =3D uc->ud; - - if (uc->bchan) { - dev_dbg(ud->dev, "chan%d: put bchan%d\n", uc->id, - uc->bchan->id); - clear_bit(uc->bchan->id, ud->bchan_map); - uc->bchan =3D NULL; - uc->tchan =3D NULL; - } -} - -static void udma_put_rchan(struct udma_chan *uc) -{ - struct udma_dev *ud =3D uc->ud; - - if (uc->rchan) { - dev_dbg(ud->dev, "chan%d: put rchan%d\n", uc->id, - uc->rchan->id); - clear_bit(uc->rchan->id, ud->rchan_map); - uc->rchan =3D NULL; - } -} - -static void udma_put_tchan(struct udma_chan *uc) -{ - struct udma_dev *ud =3D uc->ud; - - if (uc->tchan) { - dev_dbg(ud->dev, "chan%d: put tchan%d\n", uc->id, - uc->tchan->id); - clear_bit(uc->tchan->id, ud->tchan_map); - - if (uc->tchan->tflow_id >=3D 0) - clear_bit(uc->tchan->tflow_id, ud->tflow_map); - - uc->tchan =3D NULL; - } -} - -static void udma_put_rflow(struct udma_chan *uc) -{ - struct udma_dev *ud =3D uc->ud; - - if (uc->rflow) { - dev_dbg(ud->dev, "chan%d: put rflow%d\n", uc->id, - uc->rflow->id); - __udma_put_rflow(ud, uc->rflow); - uc->rflow =3D NULL; - } -} - -static void bcdma_free_bchan_resources(struct udma_chan *uc) -{ - if (!uc->bchan) - return; - - k3_ringacc_ring_free(uc->bchan->tc_ring); - k3_ringacc_ring_free(uc->bchan->t_ring); - uc->bchan->tc_ring =3D NULL; - uc->bchan->t_ring =3D NULL; - k3_configure_chan_coherency(&uc->vc.chan, 0); - - bcdma_put_bchan(uc); -} - static int bcdma_alloc_bchan_resources(struct udma_chan *uc) { struct k3_ring_cfg ring_cfg; @@ -847,19 +501,6 @@ static int bcdma_alloc_bchan_resources(struct udma_cha= n *uc) return ret; } =20 -static void udma_free_tx_resources(struct udma_chan *uc) -{ - if (!uc->tchan) - return; - - k3_ringacc_ring_free(uc->tchan->t_ring); - k3_ringacc_ring_free(uc->tchan->tc_ring); - uc->tchan->t_ring =3D NULL; - uc->tchan->tc_ring =3D NULL; - - udma_put_tchan(uc); -} - static int udma_alloc_tx_resources(struct udma_chan *uc) { struct k3_ring_cfg ring_cfg; @@ -917,25 +558,6 @@ static int udma_alloc_tx_resources(struct udma_chan *u= c) return ret; } =20 -static void udma_free_rx_resources(struct udma_chan *uc) -{ - if (!uc->rchan) - return; - - if (uc->rflow) { - struct udma_rflow *rflow =3D uc->rflow; - - k3_ringacc_ring_free(rflow->fd_ring); - k3_ringacc_ring_free(rflow->r_ring); - rflow->fd_ring =3D NULL; - rflow->r_ring =3D NULL; - - udma_put_rflow(uc); - } - - udma_put_rchan(uc); -} - static int udma_alloc_rx_resources(struct udma_chan *uc) { struct udma_dev *ud =3D uc->ud; @@ -2024,51 +1646,6 @@ static int udma_resume(struct dma_chan *chan) return 0; } =20 -static void udma_free_chan_resources(struct dma_chan *chan) -{ - struct udma_chan *uc =3D to_udma_chan(chan); - struct udma_dev *ud =3D to_udma_dev(chan->device); - - udma_terminate_all(chan); - if (uc->terminated_desc) { - ud->reset_chan(uc, false); - udma_reset_rings(uc); - } - - cancel_delayed_work_sync(&uc->tx_drain.work); - - if (uc->irq_num_ring > 0) { - free_irq(uc->irq_num_ring, uc); - - uc->irq_num_ring =3D 0; - } - if (uc->irq_num_udma > 0) { - free_irq(uc->irq_num_udma, uc); - - uc->irq_num_udma =3D 0; - } - - /* Release PSI-L pairing */ - if (uc->psil_paired) { - ud->psil_unpair(ud, uc->config.src_thread, - uc->config.dst_thread); - uc->psil_paired =3D false; - } - - vchan_free_chan_resources(&uc->vc); - tasklet_kill(&uc->vc.task); - - bcdma_free_bchan_resources(uc); - udma_free_tx_resources(uc); - udma_free_rx_resources(uc); - udma_reset_uchan(uc); - - if (uc->use_dma_pool) { - dma_pool_destroy(uc->hdesc_pool); - uc->use_dma_pool =3D false; - } -} - static struct platform_driver udma_driver; static struct platform_driver bcdma_driver; static struct platform_driver pktdma_driver; diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h index 4878d13d84ed0..329df7eb156b2 100644 --- a/drivers/dma/ti/k3-udma.h +++ b/drivers/dma/ti/k3-udma.h @@ -658,6 +658,27 @@ void udma_dbg_summary_show(struct seq_file *s, struct dma_device *dma_dev); #endif /* CONFIG_DEBUG_FS */ =20 +int __udma_alloc_gp_rflow_range(struct udma_dev *ud, int from, int cnt); +int __udma_free_gp_rflow_range(struct udma_dev *ud, int from, int cnt); +struct udma_rflow *__udma_get_rflow(struct udma_dev *ud, int id); +void __udma_put_rflow(struct udma_dev *ud, struct udma_rflow *rflow); +int udma_get_tchan(struct udma_chan *uc); +int udma_get_rchan(struct udma_chan *uc); +int udma_get_chan_pair(struct udma_chan *uc); +int udma_get_rflow(struct udma_chan *uc, int flow_id); +void udma_put_rchan(struct udma_chan *uc); +void udma_put_tchan(struct udma_chan *uc); +void udma_put_rflow(struct udma_chan *uc); +void udma_free_tx_resources(struct udma_chan *uc); +void udma_free_rx_resources(struct udma_chan *uc); +void udma_free_chan_resources(struct dma_chan *chan); +void bcdma_put_bchan(struct udma_chan *uc); +void bcdma_free_bchan_resources(struct udma_chan *uc); + +struct udma_bchan *__udma_reserve_bchan(struct udma_dev *ud, enum udma_tp_= level tpl, int id); +struct udma_tchan *__udma_reserve_tchan(struct udma_dev *ud, enum udma_tp_= level tpl, int id); +struct udma_rchan *__udma_reserve_rchan(struct udma_dev *ud, enum udma_tp_= level tpl, int id); + /* Direct access to UDMA low lever resources for the glue layer */ int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thr= ead); int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread, --=20 2.54.0 From nobody Tue Sep 29 08:26:17 2026 Received: from mx0a-0002e601.pphosted.com (mx0a-0002e601.pphosted.com [148.163.150.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F31B376A07; Mon, 28 Sep 2026 02:59:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.150.75 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564370; cv=fail; b=cuYqUkRqxtAK1wyAj51R2ZUK+rzwR7CZHejzE8vc8sx2RmcytMgQnBKq3uYf1OwpDM/SD6hyDlHnVLiOsZt5jxXc5r1N2Yg9apXMc64mlB7Ime0HbV/XuC7S/2hbYkgxmvIvYr8bzZt0OyjL9o0G+hqWVrjJ5VoUS5VE0GyKFmU= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564370; c=relaxed/simple; bh=NKs96bFDGRUwGUx17Y/gdXO7sxNdXAeMS2yTBLYBaAs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MdX2CIr979/FnJ+h5UQSajZIl/+faN+MWFsJEzgqhJUlNjEH+fhcxDmsV+x9wKjQQ3Bn1Xenxc/RPS8b/YBQQ5W8uTMOSdkhlvdw6g00KCBGt2/lswJIjihvrDhtc6UB7GVy0L/txoBdx9RWSRcbdqSkU2srnTgeQKoeqN8MYcQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=UEnPVBgT; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=lIJAZUK3; arc=fail smtp.client-ip=148.163.150.75 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="UEnPVBgT"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="lIJAZUK3" Received: from pps.filterd (m0384305.ppops.net [127.0.0.1]) by m0384305.ppops.net (8.18.1.11/8.18.1.11) with ESMTP id 68RNiAXg3706250; Sun, 27 Sep 2026 21:59:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=a15/C6QzRzzsL5TYHeYHQt/0QQVuGNSGXjd2F6SNL CQ=; b=UEnPVBgTB+3fh1g4rrl28YxaC6UE0ZOVxSstuWLnzSGeFhvDyHtNv4t2t NMyfXgOBsU/g+9TVtqlKP7jNqnfNMVV9BHJadO4/NzKT6629JENuPk/ya3Pc1Pl+ SllWCJ22RBzmia81kpMaVJIEVfMIsjrKBbuWRBIls/DGzm5aXUCvVCYPCl8j1Ahi jreN4pS76bKjBr+xGdaxvwhXdaIC/yoy8IP5gOWo4IF9kcW823VSSlgSBgjIlUC+ RfRQ2wir6oYC8W6WzGYRDKX+kbOJkGkyulC8DyQIILBOt7qHkOxnc+4O9o+zfTjz y//E6p3DqSbMTtlmC5iFB5AcmAE3g== Received: from sn4pr0501cu005.outbound.protection.outlook.com (mail-southcentralusazon11011026.outbound.protection.outlook.com [40.93.194.26]) by m0384305.ppops.net (PPS) with ESMTPS id 4gy00nb1sj-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Sun, 27 Sep 2026 21:59:18 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=e6gQW9ncN/3NPLqgYsPz7sLbLm3Q2NmVJuyiW4a30LiYyUBhyM/9udOpzHXT6C7tsDSdbdQtO7t+2MEHs7Yx+tSvsagIfvF+ub4Z4ywOSP5FFxLUEp04GfOnN9KfnQGmlkgZtIQrXDQ1xu1uekvEJOYl38HTHTIPV6trPXWPtDPPHsYfpCeeG+LVFB8xC0ImkV8g1Bs+6xRSrcUgtN9X2ZOKo1Me2/qlb0Fsy9b5ZendB6ArTJsE/cqZz/l4+9sAgelLDluktZSOhekcVI+r6eNkXV9cRAf7Xw1T5sK6l2AKRWDVSP8c0+CccsRTJAh2TtKmGdjVKcj5hy23Dbt1xA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=a15/C6QzRzzsL5TYHeYHQt/0QQVuGNSGXjd2F6SNLCQ=; b=Dahme1AiFVRKTQ0eSyJqP75kLk8oO1cyP6uHabcHRJWlDMYfanLYYsZGsFqaQvQzFC/VG4vwKe0jcwuE+2wfWoQcta63/MolFkDYNWl0mCC8S9u9Ak2xs5MrU0lseej53IyNbDwO7oXVEokTCJH1zZLLQ8skllBgqvpegm+MhDoHJT8mI0G0o1zXqB27VOlVqhSTeApg4Gq8q+ZbOPVwROrNHgmCdMQyihAv4mYIYE8WZKaV6KC/pG+yQCYmuSgPH2ed6qmvIjj8fqqXBw74it6NWz9z+R/mH8YILgXZfhtP9W8nhPt6QkYFZawZy56s952i1HyPvfxv0wpTebpl+w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.21.194) smtp.rcpttodomain=nxp.com smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=a15/C6QzRzzsL5TYHeYHQt/0QQVuGNSGXjd2F6SNLCQ=; b=lIJAZUK3qOrHI1rgxE/oSorzbu/afr1UgoL/DhsJGpLwz/tsR5A1veo6jRPf8ybKyg9UTJFdW2BK7CfaXJDw0rQsWVU0gH1qnQf4UPC9vvZh+snybxKOEWPzfhTCD/8gmzxTZzeSS9c7rlaIWBv2wAfr17FxmRTg16FmJVKWUnE= Received: from DS1PR04CA0002.namprd04.prod.outlook.com (2603:10b6:8:44f::16) by LV8PR10MB7751.namprd10.prod.outlook.com (2603:10b6:408:1e6::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.7; Mon, 28 Sep 2026 02:59:13 +0000 Received: from DS2PEPF000061C4.namprd02.prod.outlook.com (2603:10b6:8:44f:cafe::97) by DS1PR04CA0002.outlook.office365.com (2603:10b6:8:44f::16) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.451.23 via Frontend Transport; Mon, 28 Sep 2026 02:59:13 +0000 X-MS-Exchange-Authentication-Results: mx.microsoft.com 1; spf=pass (sender IP is 198.47.21.194) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.21.194 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.21.194; helo=flwvzet200.ext.ti.com; pr=C Received: from flwvzet200.ext.ti.com (198.47.21.194) by DS2PEPF000061C4.mail.protection.outlook.com (10.167.23.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Mon, 28 Sep 2026 02:59:12 +0000 Received: from DFLE205.ent.ti.com (10.64.6.63) by flwvzet200.ext.ti.com (10.248.192.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:45 -0500 Received: from DFLE215.ent.ti.com (10.64.6.73) by DFLE205.ent.ti.com (10.64.6.63) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:45 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE215.ent.ti.com (10.64.6.73) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45 via Frontend Transport; Sun, 27 Sep 2026 21:58:45 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [10.24.51.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 68S2vqqH2256662; Sun, 27 Sep 2026 21:58:40 -0500 From: Sai Sree Kartheek Adivi To: , , , , , , , , , , , , , CC: , Subject: [PATCH v10 10/19] dmaengine: ti: k3-udma: refactor resource setup functions Date: Mon, 28 Sep 2026 08:26:16 +0530 Message-ID: <20260928025749.1055383-11-s-adivi@ti.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260928025749.1055383-1-s-adivi@ti.com> References: <20260928025749.1055383-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF000061C4:EE_|LV8PR10MB7751:EE_ X-MS-Office365-Filtering-Correlation-Id: d8b7b5b1-091c-419c-7d2f-08df1d0c79d4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|23010399003|7416014|376014|82310400026|36860700016|921020|3023799007|6133799003|10067099003|56012099006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: 1xz587+ImIll6OQYKCJ8VCPa7nx8+KCau6+5mNgz26QIuV75XLsvIEsGGvuKH/Uqk6o7ca42AqLFozqUR0EaZJREmBFejEMHL10U49AjXHbo3KvyIo6J3pZu6d2MVNGUi4Bas0fIHVLlrL3YrrfUuXXgcRR84ZFymYMaY6RyUkzIct+zWPtZeC8kD0oVn+l31i8rwuQYDD9q3nuDEVEjUazCJFZKvyVIXbvLOc8OVy4oArTUGl9q9ypTzBfK03HD9O66gjwxdFt+FwkiXf/DsVl9fTxjJmHQyU42oajyQ36JiPFCtfrl6I4HeJyn/zgWw67PFQ8NdCj2I9/zELZRS24NA3WCwS1IGsCmSxLXGr9MOXuy+7r5GgEf+IwUNscZ2Tv8CBAPSZzfsvapplMzIdoIABh+u0JT7r0uqQwv4jLHcBcLNT4ThwtOhfK7trTtgOPfnR2N0gGwyRqJZT1B7TNpdyfAF7w9thF+eK/Jc5v/4rfZux1TEZwN1/CySuTCtSqzoyT/pfd3y5ZD43ptNPdyZ+Nl3r2csEMmsqq5fBIlCmCUZyGVmqS6hrTLT+7Yx0Sz2fUJazaG6UpbiXEOJi5X4buPpBc866Xtwza7EULLy4UWJT58m51DC4EfGd3NcHcUbkSu+5ZQCTR8akltJhBAw0Sq43LxO8WclWecK8/QRSKVwQp7HLmWIMX9X37Qs0sxfADXtBOe7YMPJDf7TEho+cOHU+YuHVv2LsXW11tIe8Dok8kh8a/t97DBzZEv X-Forefront-Antispam-Report: CIP:198.47.21.194;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:flwvzet200.ext.ti.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230040)(1800799024)(23010399003)(7416014)(376014)(82310400026)(36860700016)(921020)(3023799007)(6133799003)(10067099003)(56012099006)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YpnQbxhUinOrP69vUOpUx/wclUl7SDFXWd0zqzqyOZFUxwYp5eIFrNVTweAdM3eQdg143c6XMR+vs2H9Jdzfv4qcjQ5wzCjsTgr4Ov7HlnAkXg18FWrg1/FEA/CPDpxhGLq7orbSWa984JFpF0htydRcaXgEhVEZgevibIfJ3dH3KBwwLk0UlOjZDnZvs6cCTTPF831trSwhGyKWDydUh4d2D05zSkgF+AoH4urXqKO97xLK4M1+k+7KfWfYayA757wMUVmzBoFjIhcVi3pwFFY22Mhm7bTblDaKm3eI/EMqTXoVaTbQsLNt/RaBqHrGBD0PLmcjHyF+0wi+mxSsI8FkWsnN11kAllqWRZTIW9kpAA248YHlzt3syZzIEGuIZQ+5kOPlUkKL1VAd7xzRfY+MFxwdR8IB6D/cCczPrVC1uyLn9IFzTEnVeUFNo83F X-Exchange-RoutingPolicyChecked: EmkBjcjVa59W3a8tg5qJ87MbZejVvbzYAHcFQ26nW2R5yy0PsqQA+md6jR9eTVIlCtwUHWydLY419vdRyRXvRnCl5NtP66RlcIDi62B2n/Ts27NeFKQNiIXrC7lDMACQpIX0Qn4+9/YZc0hL3A7cMmJ59dBaIpP1hc1JL+6Q7m+64sghlspfvJLb+1iyGzK3OfR5bG8vInkMjY3Ef/Oa74c/jytAmOk5qd3yOn0QYkAyxIDhdxa4Z5neyyD2mRw9UZxFwHiDj+aHnz1vnwG/b/CAy4x8agifwQ1CQN2HJLfuIgR3v9/+EWX0YdXFYfPLYESDEIzj1ZyBUg6KH+e4Zg== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 02:59:12.9707 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d8b7b5b1-091c-419c-7d2f-08df1d0c79d4 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF000061C4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR10MB7751 X-Proofpoint-GUID: D37xmGs4QpdVXIqIroOklIqkKuOOJgAM X-Authority-Analysis: v=2.4 cv=fKysTpae c=1 sm=1 tr=0 ts=6ab9d807 cx=c_pps a=HGE+/hAEzspoXCOliImplg==:117 a=iwqwCZQqcuTv3JOpYdM7/Q==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=VdqzKS8jKosA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=taLDd7a_hP9WKsMzeGRc:22 a=sozttTNsAAAA:8 a=I_B2hWj7ayHADsQg9NcA:9 X-Proofpoint-ORIG-GUID: D37xmGs4QpdVXIqIroOklIqkKuOOJgAM X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX7ze5nzbEDma3 BA52pUvyoScm1zp5mfqoVKrFEF/BZYj0DnThHaHaqGTeje42LKQthJz+iIYAhjziZlc7kEfBeqh mNVVqp7pHKGq7B45zVPFObZuGIndNHU= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfXyYAfV7HkbXkh fwnB/ZCjiOLdh7jsMJLWFnzuduNUmzbrG3Bne+9tcPBqkUqgsDfxwG12IeH5LRWuAjl082Pcgg5 pJqBO/21fwfxbx9+RProJ0m4vKdxaJxVKYIGL0BmXC3tfCFq+RhLy1qIgHTot1+V+JafSNgyslz BWPSan3udXJErUQRi1kw/PHnOXjfwk3Y0UTJwKEuxjW/xVJUgXGIaAXm+bkzkehh9lBTD1KyTGo mwvGU07MwocicwtHEosjnV6ZMD84rRbrI22gxfncC1Pvjv5zKJirUnvz3kxn26188X5EUp7dxvb Xmtc7Cmbb0bRiCRyBbvVwoHkAAMRPZC5akp1julENUQa3pvEohqHp+/fatRzSLfnVJMZ5EVfral cb0pX5s0dqyEqaOxyA58M0csUEpRgo4sY0IYogAhz/j7U51mOXT7Vm3rhbVUASRrCEbELK4NTDG YQtbMxDqZH5HK1Qwsvw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 spamscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 adultscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280011 Content-Type: text/plain; charset="utf-8" The implementation of setup_resources, bcdma_setup_resources and pktdma_setup_resources is largely shared between all K3 UDMA variants with the only major difference being SCI resources setup. So, - Move the functions to k3-udma-common.c. - Split SCI resource setup for bcdma and pktdma into separate functions in variant specific driver (k3-udma.c). - Add function pointers for setup_sci_resources in udma_dev and call them as part of the actual resource setup implementations in k3-udma-common.c to retain the existing functionality. - Also since setup_resources call udma_setup_resources which is not required for all K3 UDMA variants, Add a function pointer in udma_dev and use that to call udma_setup_resources. - Rename setup_resources to k3_udma_setup_resources to avoid polluting global kernel namespace with generic symbol. This refactor improves code reuse and maintainability across multiple variants. No functional changes intended. Signed-off-by: Sai Sree Kartheek Adivi --- drivers/dma/ti/k3-udma-common.c | 200 ++++++++++++++++++++++++++++++++ drivers/dma/ti/k3-udma.c | 184 ++--------------------------- drivers/dma/ti/k3-udma.h | 6 + 3 files changed, 213 insertions(+), 177 deletions(-) diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-commo= n.c index 34f8eab9ddb57..d0afbab01786f 100644 --- a/drivers/dma/ti/k3-udma-common.c +++ b/drivers/dma/ti/k3-udma-common.c @@ -8,7 +8,9 @@ #include #include #include +#include #include +#include #include =20 #include "k3-udma.h" @@ -2334,5 +2336,203 @@ void bcdma_free_bchan_resources(struct udma_chan *u= c) } EXPORT_SYMBOL_GPL(bcdma_free_bchan_resources); =20 +static int bcdma_setup_resources(struct udma_dev *ud) +{ + int ret; + struct device *dev =3D ud->dev; + u32 cap; + + /* Set up the throughput level start indexes */ + cap =3D udma_read(ud->mmrs[MMR_GCFG], 0x2c); + if (BCDMA_CAP3_UBCHAN_CNT(cap)) { + ud->bchan_tpl.levels =3D 3; + ud->bchan_tpl.start_idx[1] =3D BCDMA_CAP3_UBCHAN_CNT(cap); + ud->bchan_tpl.start_idx[0] =3D BCDMA_CAP3_HBCHAN_CNT(cap); + } else if (BCDMA_CAP3_HBCHAN_CNT(cap)) { + ud->bchan_tpl.levels =3D 2; + ud->bchan_tpl.start_idx[0] =3D BCDMA_CAP3_HBCHAN_CNT(cap); + } else { + ud->bchan_tpl.levels =3D 1; + } + + cap =3D udma_read(ud->mmrs[MMR_GCFG], 0x30); + if (BCDMA_CAP4_URCHAN_CNT(cap)) { + ud->rchan_tpl.levels =3D 3; + ud->rchan_tpl.start_idx[1] =3D BCDMA_CAP4_URCHAN_CNT(cap); + ud->rchan_tpl.start_idx[0] =3D BCDMA_CAP4_HRCHAN_CNT(cap); + } else if (BCDMA_CAP4_HRCHAN_CNT(cap)) { + ud->rchan_tpl.levels =3D 2; + ud->rchan_tpl.start_idx[0] =3D BCDMA_CAP4_HRCHAN_CNT(cap); + } else { + ud->rchan_tpl.levels =3D 1; + } + + if (BCDMA_CAP4_UTCHAN_CNT(cap)) { + ud->tchan_tpl.levels =3D 3; + ud->tchan_tpl.start_idx[1] =3D BCDMA_CAP4_UTCHAN_CNT(cap); + ud->tchan_tpl.start_idx[0] =3D BCDMA_CAP4_HTCHAN_CNT(cap); + } else if (BCDMA_CAP4_HTCHAN_CNT(cap)) { + ud->tchan_tpl.levels =3D 2; + ud->tchan_tpl.start_idx[0] =3D BCDMA_CAP4_HTCHAN_CNT(cap); + } else { + ud->tchan_tpl.levels =3D 1; + } + + ud->bchan_map =3D devm_bitmap_zalloc(dev, ud->bchan_cnt, GFP_KERNEL); + ud->bchans =3D devm_kcalloc(dev, ud->bchan_cnt, sizeof(*ud->bchans), + GFP_KERNEL); + ud->tchan_map =3D devm_bitmap_zalloc(dev, ud->tchan_cnt, GFP_KERNEL); + ud->tchans =3D devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), + GFP_KERNEL); + ud->rchan_map =3D devm_bitmap_zalloc(dev, ud->rchan_cnt, GFP_KERNEL); + ud->rchans =3D devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), + GFP_KERNEL); + /* BCDMA do not really have flows, but the driver expect it */ + ud->rflow_in_use =3D devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt), + sizeof(unsigned long), + GFP_KERNEL); + ud->rflows =3D devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rflows), + GFP_KERNEL); + + if (!ud->bchan_map || !ud->tchan_map || !ud->rchan_map || + !ud->rflow_in_use || !ud->bchans || !ud->tchans || !ud->rchans || + !ud->rflows) + return -ENOMEM; + + if (ud->bcdma_setup_sci_resources) { + ret =3D ud->bcdma_setup_sci_resources(ud); + if (ret) + return ret; + } + + return 0; +} + +static int pktdma_setup_resources(struct udma_dev *ud) +{ + int ret; + struct device *dev =3D ud->dev; + u32 cap3; + + /* Set up the throughput level start indexes */ + cap3 =3D udma_read(ud->mmrs[MMR_GCFG], 0x2c); + if (UDMA_CAP3_UCHAN_CNT(cap3)) { + ud->tchan_tpl.levels =3D 3; + ud->tchan_tpl.start_idx[1] =3D UDMA_CAP3_UCHAN_CNT(cap3); + ud->tchan_tpl.start_idx[0] =3D UDMA_CAP3_HCHAN_CNT(cap3); + } else if (UDMA_CAP3_HCHAN_CNT(cap3)) { + ud->tchan_tpl.levels =3D 2; + ud->tchan_tpl.start_idx[0] =3D UDMA_CAP3_HCHAN_CNT(cap3); + } else { + ud->tchan_tpl.levels =3D 1; + } + + ud->rchan_tpl.levels =3D ud->tchan_tpl.levels; + ud->rchan_tpl.start_idx[0] =3D ud->tchan_tpl.start_idx[0]; + ud->rchan_tpl.start_idx[1] =3D ud->tchan_tpl.start_idx[1]; + + ud->tchan_map =3D devm_bitmap_zalloc(dev, ud->tchan_cnt, GFP_KERNEL); + ud->tchans =3D devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), + GFP_KERNEL); + ud->rchan_map =3D devm_bitmap_zalloc(dev, ud->rchan_cnt, GFP_KERNEL); + ud->rchans =3D devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), + GFP_KERNEL); + ud->rflow_in_use =3D devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt), + sizeof(unsigned long), + GFP_KERNEL); + ud->rflows =3D devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows), + GFP_KERNEL); + ud->tflow_map =3D devm_bitmap_zalloc(dev, ud->tflow_cnt, GFP_KERNEL); + + if (!ud->tchan_map || !ud->rchan_map || !ud->tflow_map || !ud->tchans || + !ud->rchans || !ud->rflows || !ud->rflow_in_use) + return -ENOMEM; + + if (ud->pktdma_setup_sci_resources) { + ret =3D ud->pktdma_setup_sci_resources(ud); + if (ret) + return ret; + } + + return 0; +} + +int k3_udma_setup_resources(struct udma_dev *ud) +{ + struct device *dev =3D ud->dev; + int ch_count, ret; + + switch (ud->match_data->type) { + case DMA_TYPE_UDMA: + if (!ud->udma_setup_resources) + return -EINVAL; + ret =3D ud->udma_setup_resources(ud); + break; + case DMA_TYPE_BCDMA: + ret =3D bcdma_setup_resources(ud); + break; + case DMA_TYPE_PKTDMA: + ret =3D pktdma_setup_resources(ud); + break; + default: + return -EINVAL; + } + + if (ret) + return ret; + + ch_count =3D ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt; + if (ud->bchan_cnt) + ch_count -=3D bitmap_weight(ud->bchan_map, ud->bchan_cnt); + ch_count -=3D bitmap_weight(ud->tchan_map, ud->tchan_cnt); + ch_count -=3D bitmap_weight(ud->rchan_map, ud->rchan_cnt); + if (!ch_count) + return -ENODEV; + + ud->channels =3D devm_kcalloc(dev, ch_count, sizeof(*ud->channels), + GFP_KERNEL); + if (!ud->channels) + return -ENOMEM; + + switch (ud->match_data->type) { + case DMA_TYPE_UDMA: + dev_info(dev, + "Channels: %d (tchan: %u, rchan: %u, gp-rflow: %u)\n", + ch_count, + ud->tchan_cnt - bitmap_weight(ud->tchan_map, + ud->tchan_cnt), + ud->rchan_cnt - bitmap_weight(ud->rchan_map, + ud->rchan_cnt), + ud->rflow_cnt - bitmap_weight(ud->rflow_gp_map, + ud->rflow_cnt)); + break; + case DMA_TYPE_BCDMA: + dev_info(dev, + "Channels: %d (bchan: %u, tchan: %u, rchan: %u)\n", + ch_count, + ud->bchan_cnt - bitmap_weight(ud->bchan_map, + ud->bchan_cnt), + ud->tchan_cnt - bitmap_weight(ud->tchan_map, + ud->tchan_cnt), + ud->rchan_cnt - bitmap_weight(ud->rchan_map, + ud->rchan_cnt)); + break; + case DMA_TYPE_PKTDMA: + dev_info(dev, + "Channels: %d (tchan: %u, rchan: %u)\n", + ch_count, + ud->tchan_cnt - bitmap_weight(ud->tchan_map, + ud->tchan_cnt), + ud->rchan_cnt - bitmap_weight(ud->rchan_map, + ud->rchan_cnt)); + break; + default: + break; + } + + return ch_count; +} +EXPORT_SYMBOL_GPL(k3_udma_setup_resources); + MODULE_DESCRIPTION("Texas Instruments K3 UDMA Common Library"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 21978f17e327f..9a261747c8709 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -2083,7 +2083,7 @@ static const char * const range_names[] =3D { [RM_RANGE_TFLOW] =3D "ti,sci-rm-range-tflow", }; =20 -static int udma_setup_resources(struct udma_dev *ud) +int udma_setup_resources(struct udma_dev *ud) { int ret, i, j; struct device *dev =3D ud->dev; @@ -2245,74 +2245,13 @@ static int udma_setup_resources(struct udma_dev *ud) return 0; } =20 -static int bcdma_setup_resources(struct udma_dev *ud) +static int bcdma_setup_sci_resources(struct udma_dev *ud) { int ret, i, j; struct device *dev =3D ud->dev; struct ti_sci_resource *rm_res, irq_res; struct udma_tisci_rm *tisci_rm =3D &ud->tisci_rm; const struct udma_oes_offsets *oes =3D &ud->soc_data->oes; - u32 cap; - - /* Set up the throughput level start indexes */ - cap =3D udma_read(ud->mmrs[MMR_GCFG], 0x2c); - if (BCDMA_CAP3_UBCHAN_CNT(cap)) { - ud->bchan_tpl.levels =3D 3; - ud->bchan_tpl.start_idx[1] =3D BCDMA_CAP3_UBCHAN_CNT(cap); - ud->bchan_tpl.start_idx[0] =3D BCDMA_CAP3_HBCHAN_CNT(cap); - } else if (BCDMA_CAP3_HBCHAN_CNT(cap)) { - ud->bchan_tpl.levels =3D 2; - ud->bchan_tpl.start_idx[0] =3D BCDMA_CAP3_HBCHAN_CNT(cap); - } else { - ud->bchan_tpl.levels =3D 1; - } - - cap =3D udma_read(ud->mmrs[MMR_GCFG], 0x30); - if (BCDMA_CAP4_URCHAN_CNT(cap)) { - ud->rchan_tpl.levels =3D 3; - ud->rchan_tpl.start_idx[1] =3D BCDMA_CAP4_URCHAN_CNT(cap); - ud->rchan_tpl.start_idx[0] =3D BCDMA_CAP4_HRCHAN_CNT(cap); - } else if (BCDMA_CAP4_HRCHAN_CNT(cap)) { - ud->rchan_tpl.levels =3D 2; - ud->rchan_tpl.start_idx[0] =3D BCDMA_CAP4_HRCHAN_CNT(cap); - } else { - ud->rchan_tpl.levels =3D 1; - } - - if (BCDMA_CAP4_UTCHAN_CNT(cap)) { - ud->tchan_tpl.levels =3D 3; - ud->tchan_tpl.start_idx[1] =3D BCDMA_CAP4_UTCHAN_CNT(cap); - ud->tchan_tpl.start_idx[0] =3D BCDMA_CAP4_HTCHAN_CNT(cap); - } else if (BCDMA_CAP4_HTCHAN_CNT(cap)) { - ud->tchan_tpl.levels =3D 2; - ud->tchan_tpl.start_idx[0] =3D BCDMA_CAP4_HTCHAN_CNT(cap); - } else { - ud->tchan_tpl.levels =3D 1; - } - - ud->bchan_map =3D devm_kmalloc_array(dev, BITS_TO_LONGS(ud->bchan_cnt), - sizeof(unsigned long), GFP_KERNEL); - ud->bchans =3D devm_kcalloc(dev, ud->bchan_cnt, sizeof(*ud->bchans), - GFP_KERNEL); - ud->tchan_map =3D devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt), - sizeof(unsigned long), GFP_KERNEL); - ud->tchans =3D devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), - GFP_KERNEL); - ud->rchan_map =3D devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt), - sizeof(unsigned long), GFP_KERNEL); - ud->rchans =3D devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), - GFP_KERNEL); - /* BCDMA do not really have flows, but the driver expect it */ - ud->rflow_in_use =3D devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt), - sizeof(unsigned long), - GFP_KERNEL); - ud->rflows =3D devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rflows), - GFP_KERNEL); - - if (!ud->bchan_map || !ud->tchan_map || !ud->rchan_map || - !ud->rflow_in_use || !ud->bchans || !ud->tchans || !ud->rchans || - !ud->rflows) - return -ENOMEM; =20 /* Get resource ranges from tisci */ for (i =3D 0; i < RM_RANGE_LAST; i++) { @@ -2476,51 +2415,13 @@ static int bcdma_setup_resources(struct udma_dev *u= d) return 0; } =20 -static int pktdma_setup_resources(struct udma_dev *ud) +static int pktdma_setup_sci_resources(struct udma_dev *ud) { int ret, i, j; struct device *dev =3D ud->dev; struct ti_sci_resource *rm_res, irq_res; struct udma_tisci_rm *tisci_rm =3D &ud->tisci_rm; const struct udma_oes_offsets *oes =3D &ud->soc_data->oes; - u32 cap3; - - /* Set up the throughput level start indexes */ - cap3 =3D udma_read(ud->mmrs[MMR_GCFG], 0x2c); - if (UDMA_CAP3_UCHAN_CNT(cap3)) { - ud->tchan_tpl.levels =3D 3; - ud->tchan_tpl.start_idx[1] =3D UDMA_CAP3_UCHAN_CNT(cap3); - ud->tchan_tpl.start_idx[0] =3D UDMA_CAP3_HCHAN_CNT(cap3); - } else if (UDMA_CAP3_HCHAN_CNT(cap3)) { - ud->tchan_tpl.levels =3D 2; - ud->tchan_tpl.start_idx[0] =3D UDMA_CAP3_HCHAN_CNT(cap3); - } else { - ud->tchan_tpl.levels =3D 1; - } - - ud->rchan_tpl.levels =3D ud->tchan_tpl.levels; - ud->rchan_tpl.start_idx[0] =3D ud->tchan_tpl.start_idx[0]; - ud->rchan_tpl.start_idx[1] =3D ud->tchan_tpl.start_idx[1]; - - ud->tchan_map =3D devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt), - sizeof(unsigned long), GFP_KERNEL); - ud->tchans =3D devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), - GFP_KERNEL); - ud->rchan_map =3D devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt), - sizeof(unsigned long), GFP_KERNEL); - ud->rchans =3D devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), - GFP_KERNEL); - ud->rflow_in_use =3D devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt), - sizeof(unsigned long), - GFP_KERNEL); - ud->rflows =3D devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows), - GFP_KERNEL); - ud->tflow_map =3D devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tflow_cnt), - sizeof(unsigned long), GFP_KERNEL); - - if (!ud->tchan_map || !ud->rchan_map || !ud->tflow_map || !ud->tchans || - !ud->rchans || !ud->rflows || !ud->rflow_in_use) - return -ENOMEM; =20 /* Get resource ranges from tisci */ for (i =3D 0; i < RM_RANGE_LAST; i++) { @@ -2631,80 +2532,6 @@ static int pktdma_setup_resources(struct udma_dev *u= d) return 0; } =20 -static int setup_resources(struct udma_dev *ud) -{ - struct device *dev =3D ud->dev; - int ch_count, ret; - - switch (ud->match_data->type) { - case DMA_TYPE_UDMA: - ret =3D udma_setup_resources(ud); - break; - case DMA_TYPE_BCDMA: - ret =3D bcdma_setup_resources(ud); - break; - case DMA_TYPE_PKTDMA: - ret =3D pktdma_setup_resources(ud); - break; - default: - return -EINVAL; - } - - if (ret) - return ret; - - ch_count =3D ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt; - if (ud->bchan_cnt) - ch_count -=3D bitmap_weight(ud->bchan_map, ud->bchan_cnt); - ch_count -=3D bitmap_weight(ud->tchan_map, ud->tchan_cnt); - ch_count -=3D bitmap_weight(ud->rchan_map, ud->rchan_cnt); - if (!ch_count) - return -ENODEV; - - ud->channels =3D devm_kcalloc(dev, ch_count, sizeof(*ud->channels), - GFP_KERNEL); - if (!ud->channels) - return -ENOMEM; - - switch (ud->match_data->type) { - case DMA_TYPE_UDMA: - dev_info(dev, - "Channels: %d (tchan: %u, rchan: %u, gp-rflow: %u)\n", - ch_count, - ud->tchan_cnt - bitmap_weight(ud->tchan_map, - ud->tchan_cnt), - ud->rchan_cnt - bitmap_weight(ud->rchan_map, - ud->rchan_cnt), - ud->rflow_cnt - bitmap_weight(ud->rflow_gp_map, - ud->rflow_cnt)); - break; - case DMA_TYPE_BCDMA: - dev_info(dev, - "Channels: %d (bchan: %u, tchan: %u, rchan: %u)\n", - ch_count, - ud->bchan_cnt - bitmap_weight(ud->bchan_map, - ud->bchan_cnt), - ud->tchan_cnt - bitmap_weight(ud->tchan_map, - ud->tchan_cnt), - ud->rchan_cnt - bitmap_weight(ud->rchan_map, - ud->rchan_cnt)); - break; - case DMA_TYPE_PKTDMA: - dev_info(dev, - "Channels: %d (tchan: %u, rchan: %u)\n", - ch_count, - ud->tchan_cnt - bitmap_weight(ud->tchan_map, - ud->tchan_cnt), - ud->rchan_cnt - bitmap_weight(ud->rchan_map, - ud->rchan_cnt)); - break; - default: - break; - } - - return ch_count; -} - static int udma_probe(struct platform_device *pdev) { struct device_node *navss_node =3D pdev->dev.parent->of_node; @@ -2747,6 +2574,9 @@ static int udma_probe(struct platform_device *pdev) ud->decrement_byte_counters =3D udma_decrement_byte_counters; ud->psil_pair =3D navss_psil_pair; ud->psil_unpair =3D navss_psil_unpair; + ud->udma_setup_resources =3D udma_setup_resources; + ud->bcdma_setup_sci_resources =3D bcdma_setup_sci_resources; + ud->pktdma_setup_sci_resources =3D pktdma_setup_sci_resources; =20 ret =3D udma_get_mmrs(pdev, ud); if (ret) @@ -2876,7 +2706,7 @@ static int udma_probe(struct platform_device *pdev) INIT_LIST_HEAD(&ud->ddev.channels); INIT_LIST_HEAD(&ud->desc_to_purge); =20 - ch_count =3D setup_resources(ud); + ch_count =3D k3_udma_setup_resources(ud); if (ch_count <=3D 0) return ch_count; =20 diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h index 329df7eb156b2..d64b670d42490 100644 --- a/drivers/dma/ti/k3-udma.h +++ b/drivers/dma/ti/k3-udma.h @@ -357,6 +357,9 @@ struct udma_dev { u32 dst_thread); int (*psil_unpair)(struct udma_dev *ud, u32 src_thread, u32 dst_thread); + int (*udma_setup_resources)(struct udma_dev *ud); + int (*bcdma_setup_sci_resources)(struct udma_dev *ud); + int (*pktdma_setup_sci_resources)(struct udma_dev *ud); }; =20 struct udma_desc { @@ -679,6 +682,9 @@ struct udma_bchan *__udma_reserve_bchan(struct udma_dev= *ud, enum udma_tp_level struct udma_tchan *__udma_reserve_tchan(struct udma_dev *ud, enum udma_tp_= level tpl, int id); struct udma_rchan *__udma_reserve_rchan(struct udma_dev *ud, enum udma_tp_= level tpl, int id); =20 +int udma_setup_resources(struct udma_dev *ud); +int k3_udma_setup_resources(struct udma_dev *ud); + /* Direct access to UDMA low lever resources for the glue layer */ int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thr= ead); int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread, --=20 2.54.0 From nobody Tue Sep 29 08:26:17 2026 Received: from mx0b-0002e601.pphosted.com (mx0b-0002e601.pphosted.com [148.163.154.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A242374A0E; Mon, 28 Sep 2026 02:59:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.154.28 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564350; cv=fail; b=Ah5jdTxwkz1aM/bC5j34GHoWA02XM9S9dcMc/qSU2fQEgVWA7U1vx0LyfF1qDytDr8NVG01GsrJPuqs43+IeTx1KRcoeuvfMj34PPEtucSVmabIDV7PppKKptRGtTWbBOX3OoXDhPZnbZivpOskXDT9GtUbBJbGsWutoTpnpTFk= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564350; c=relaxed/simple; bh=Z5yqiGYQb+zbhB5jd+Fn5cjG2p1x73Xbil4wKmJeRnY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HfJwfqRIeCVB5nT2ayYVl/HFO7x79+5UgqKswPoqFEL8/+HbhN56nIWFljV/jdS+LBanK8vNpa1rG0ctjuOPH67YAdaddXd3s8LelFDCpNfa8/XX4W/ErktKMd3e3/IkKyivzSVZVO+y1rOOGO6N8Dc8eK6teJGoI8oLpSAMW2g= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=gGeEoJ3F; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=sGd9/ZJm; arc=fail smtp.client-ip=148.163.154.28 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="gGeEoJ3F"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="sGd9/ZJm" Received: from pps.filterd (m0374956.ppops.net [127.0.0.1]) by mx0b-0002e601.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68RM4Jhe2282852; Sun, 27 Sep 2026 21:59:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=H7SuJRbIzkpZSygmg8FrIDrs0PBd7WpV3zdPr7z8b TQ=; b=gGeEoJ3FNeESkJej6X7iouPw8HSVQZyRdEifrzUdPZNg8v1o86lqOLVVd GKgPJId4oeDipL/s8PbEenvV9d6EjIPFvp2VyLI6jJwdJDQoHP/K8iM1cbDaR7IE mbCbkA0mEsP3sg3ixyf1nSggB8LFn/0oZTXdQL0z1XB7SsE7Hogjw7xYKgagWQpz WwfRnhGO+xRS6/isWoBejNuZdG6EldHaF14tbG14qUFrPM9muVmogjevzIdQk432 vwW2bsZckWvIHuzAlqcP44sNr+1922czv5zZk+jzrGbFdx1sEn/7TMuKrWL+P7bU Usdiyy0maV4b5gUaCIPWPYLHh8G1A== Received: from ph0pr06cu001.outbound.protection.outlook.com (mail-westus3azon11011011.outbound.protection.outlook.com [40.107.208.11]) by mx0b-0002e601.pphosted.com (PPS) with ESMTPS id 4gxw6nufxv-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Sun, 27 Sep 2026 21:59:00 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=r5PmNXtSwEl6E/1KOQ0bhDp6JzRw/7GhizbAaT+EdBVjaRXYwJZ9XYfhdiK8YdW4rgICRSE8WDSBUqtxsyk5Xcap5Z4rW8WesdWdm74zTq1PmBBnb19Xjx4hLSSWD6a062UxODFTJvETOvHmuopSWa4sl4lHwSrlxVQj08/YGhbD7P5Bp5FD2RkW3SJtkSMA0GQXBqolHgPKck5E246V+hq2YDXttsupt0lcHc0qZRSw3TcSidu/yswjGkRtOgA+lP5Nuvv7kzIPxTNV15T5tgGEyQbAO7kcs+7Fket8LxmpilUI/Tu7qd1wthrn0d3+qNI+vaxWnVPQOEOrIR9S1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=H7SuJRbIzkpZSygmg8FrIDrs0PBd7WpV3zdPr7z8bTQ=; b=cYUZ4iKgr1RZmGb/KH5vbQeQu/RbC9HClSZXcCr+cOGnNGrsNj3YF1juV5BbsWj2xMUaRFlw43X/U0af4KVZMZK+Uyhm/gnEofgRXbQ4CRqHzoFwdLpVXL4Ljf2XQB7nD+lSlSHDkjZhtaFMkKSOryRT/CgAwJPj1YtH/uSj6h6iSS1lY+2HR2+sU6hT7f7F9BoygqouRaJwVM97m/eMnS398VNlF6HeCDuVbAiPpzHza++O1i2Bobfc6ebe7xRdXRitjPt8Yt3vp2OHYW3g5cxZitdOL8ke3LUzGZVoNYlsgdVus9C9wL939RsTdzo9iKEpX+Isfty5/Aj9lxq6jA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.23.194) smtp.rcpttodomain=nxp.com smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=H7SuJRbIzkpZSygmg8FrIDrs0PBd7WpV3zdPr7z8bTQ=; b=sGd9/ZJmWtCspZSxiaowgmokZkiOKS176EWI1GH1obW06X8Di8ZpshpzL1Ieo76VeLTHbALVxr6C81U6Byll4jEtGeAh/vwSOdV5usAVXUQdf/wmKn/U8QwQS1uqrAqgGWa6rUkxmJu9ZKwoxL4bRpQ1QcAbNRRx4hR5r0rU3ys= Received: from CH0PR03CA0330.namprd03.prod.outlook.com (2603:10b6:610:118::22) by IA1PR10MB7537.namprd10.prod.outlook.com (2603:10b6:208:457::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.7; Mon, 28 Sep 2026 02:58:56 +0000 Received: from CH2PEPF00000146.namprd02.prod.outlook.com (2603:10b6:610:118:cafe::3b) by CH0PR03CA0330.outlook.office365.com (2603:10b6:610:118::22) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.451.23 via Frontend Transport; Mon, 28 Sep 2026 02:58:56 +0000 X-MS-Exchange-Authentication-Results: mx.microsoft.com 1; spf=pass (sender IP is 198.47.23.194) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.23.194 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.23.194; helo=lewvzet200.ext.ti.com; pr=C Received: from lewvzet200.ext.ti.com (198.47.23.194) by CH2PEPF00000146.mail.protection.outlook.com (10.167.244.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Mon, 28 Sep 2026 02:58:56 +0000 Received: from DLEE206.ent.ti.com (157.170.170.90) by lewvzet200.ext.ti.com (10.4.14.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:50 -0500 Received: from DLEE209.ent.ti.com (157.170.170.98) by DLEE206.ent.ti.com (157.170.170.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:49 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE209.ent.ti.com (157.170.170.98) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45 via Frontend Transport; Sun, 27 Sep 2026 21:58:49 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [10.24.51.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 68S2vqqI2256662; Sun, 27 Sep 2026 21:58:45 -0500 From: Sai Sree Kartheek Adivi To: , , , , , , , , , , , , , CC: , Subject: [PATCH v10 11/19] dmaengine: ti: k3-udma: move inclusion of k3-udma-private.c to k3-udma-common.c Date: Mon, 28 Sep 2026 08:26:17 +0530 Message-ID: <20260928025749.1055383-12-s-adivi@ti.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260928025749.1055383-1-s-adivi@ti.com> References: <20260928025749.1055383-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000146:EE_|IA1PR10MB7537:EE_ X-MS-Office365-Filtering-Correlation-Id: ba131219-1337-4958-31c9-08df1d0c6fb6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|23010399003|36860700016|921020|22082099003|18002099003|56012099006|10067099003|3023799007; X-Microsoft-Antispam-Message-Info: lB4yuiN3LYHRIefQ/miJcj4bYIlyBfjSMrkqpL5DBCvBZwStxhYmmMXDGRMvJxO11uPvVUyD1rNq2cBmg+UGXXRRPBu4pQ7XHaOOTYTsuEHopTWoUbCawTALeJuzfGXd5Ie4nLP6CQJ9aLi0ykJb9RpP1UDUQ6tYQphfGIOkLlpd43vnlwOB/9YJrqAbqaemwUO0nC2bKu5z9U0GgUzh37c/zk1nIF4b32LrFurCfQMjkWxyyPMyxMgWVthw2HiE3DA6XpjvAP/c06RDO2v50NKly+o94jQo9NPsBgDsLCarInNz5J8E3me2nec0KsX4+Gx3aAxlP1CiMQslqW6t0qU+27WaF0GA/PR9svDNSfsDLor+uGAGYxgbKso2znx4TbAYd5tnlMR7M70JMSVVrMURcXPX9mJu/zBQzjp8i25yMeH7fbWpz27GaEUYbqHocnLkKnCwQRa6E7k++2gxwlkhxWAYHsx8uIomxtmxTeTvMJ7X2/QZUB0IgqLW9vLwfYLljuDhH2gSlvwGmVpXRmX++ZSICzQFxwxJh5BRQsI9R/nzUAgD8ECsEpjwCQzzbUccK5RSi8ff1dFb/oqtyjSFmkLC0dGPWvpCKSTGNyrSsGDsnqL+by5NqLhp4ZouVsGPlcntf3cqtVLpLbI0NP6w5+4SIj42YadaF9rIoT6Kfa5FIZNeZw8IWVr8nDskat2hsbwof5/KWroQrSxoeecFT/jyLQehIwNXtZ6oCtRaQ1fUFmC0L7R94rmfwPbz X-Forefront-Antispam-Report: CIP:198.47.23.194;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:lewvzet200.ext.ti.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(1800799024)(23010399003)(36860700016)(921020)(22082099003)(18002099003)(56012099006)(10067099003)(3023799007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: VSZIbSMGz6mTh7Z/Rafp5ddYKx2o0gRMlG3nQL0Q0Jetnum5etbCq2EUkUFrczhuHYp2OpN9EY7T8mxKgDvSNIroc2Qd70uQfPwoSKd7hrCO75MbJQjLMj9EB45HJFbVqZ8ylNC9OoW2Ye0jzaAvKiDa/TZx8JepJQ0g21/XAUjfd1CoouuCAddDe0WMUyJynzGudCx2VLgh3Ue+rA9O4ylfmvyU5NrtZxC+2LOEO3YpHSbHjWB5UW5Eg+zUB0lLqpyGtLh9VGzchF8wNL85fy57aJLhOA9v6uHR+IhV6nRl6FDpW4FxB2kywLYpJ5GGuQiAbUZuMHDXZc4khVvsLMj3Q3JJImdtP+Y7/Fkfsd2cBhQ744A8ed53H2NAlTsxSw/xL1Jzeh/mH4QqMSANkkhIVwgjJ+nzYRBQNj43I3/B7ae5n44Q/FinH14m3/rr X-Exchange-RoutingPolicyChecked: bm9q9ak+vBppgNAt6g1YJW+PtEKGIUpjvEtFY9wBCRy5Wmkcwqo0AyjA0wBC6E/CIYochma6ecvr2zwvSR6PjaihBmDRSXRlMJyZ+fmP9WXi9uvolh768R2ResLLRXdECmMYJMlyL7ks8rRtmEJPF89kpE7J5DmOZAxRk92mY/JwkvCoahaD9rRcowipYZBXDIjBNY5R4zpXPq0552uobd48H9mQJZi+xxpbx9zkIAYQCk0ZvEhOsxXY4pzzZFa8fPWONXScisgrTPQb745qHtFmLHzT34Jsi0kzM7lzIeXZnufJSE9Tje8k+MYt9xqQZXjPuXev4sriJav0XfulRw== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 02:58:56.0031 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ba131219-1337-4958-31c9-08df1d0c6fb6 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.194];Helo=[lewvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000146.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR10MB7537 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX8y56HLF2nMcw U1WzDeGYXgTwdZXuI5KgTHnpXCmj3cyYg9w4yZTecgO/AP1LL/ur4ZXcnH1pWw0fYclYVa15Gw6 7u0VJsbaNPmHGGv+/9HRWr1Rbytsq8Q= X-Authority-Analysis: v=2.4 cv=dbkVTnXe c=1 sm=1 tr=0 ts=6ab9d7f4 cx=c_pps a=cvmpvQQCsZncHh92cDAFKQ==:117 a=WotqVVQAdb04rnGuttW3Kw==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=VdqzKS8jKosA:10 a=s63m1ICgrNkA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=jwouBfj2j3NM8CExmVVE:22 a=sozttTNsAAAA:8 a=tBjUjbL6H5YkyfA7LM4A:9 X-Proofpoint-ORIG-GUID: F6O2V_M9Ez0reQk-QvMNY8-3OB9Ip8O5 X-Proofpoint-GUID: F6O2V_M9Ez0reQk-QvMNY8-3OB9Ip8O5 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX2B5Roz98TlOS Sv56D06e8AJxn4OWMWLSVADlWy31Vi6qbTKKdWQ0OH9JQaON5/0Z6sc/pE4uSD8QUc9FyEkHkHy sU+Q4LfUldyCFkbTKwCeQcRSYMGsBnHYFKSkzLLSqgoH2iHbmBPnr8BvqT97b65R5Eh9p9XKcZP 1zfT6IhDrdedXMzZ6kX2rAU78MCKkZFeFI2P60Z/IvQ3UccC3WL2r0VzByVjHyuC2K8rWhTLHHN 2GxxkBODQzXplp2YksDOBi7F6yGI69k4G11JtBEU3Z1U66gc0/UlkqzNsUyiIbUbYd6a4Dc2Y3T 9gYN1jqkie4oAuJZsHGQjj7tjK5CuZK2hRpOt/JYge19mRWYI9GuXHRAm9S0oZaZk3DWJsx2YXe n8NsWonCXG+qY+2gxnTC21pmFTrKeaA/eglJXpPG6K/4s/kBWq0sdbc7WOxNPedZsa9TACvSdlg m13QJG+17y6UwE2VFNQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 impostorscore=0 adultscore=0 bulkscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280011 Content-Type: text/plain; charset="utf-8" Relocate the #include directive for k3-udma-private.c to k3-udma-common.c so that the code can be shared between other UDMA variants (like k3-udma-v2). This change improves modularity and prepares for variant-specific implementations. No functional changes intended. Signed-off-by: Sai Sree Kartheek Adivi --- drivers/dma/ti/k3-udma-common.c | 3 +++ drivers/dma/ti/k3-udma.c | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-commo= n.c index d0afbab01786f..eb555cc08347d 100644 --- a/drivers/dma/ti/k3-udma-common.c +++ b/drivers/dma/ti/k3-udma-common.c @@ -2536,3 +2536,6 @@ EXPORT_SYMBOL_GPL(k3_udma_setup_resources); =20 MODULE_DESCRIPTION("Texas Instruments K3 UDMA Common Library"); MODULE_LICENSE("GPL v2"); + +/* Private interfaces to UDMA */ +#include "k3-udma-private.c" diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 9a261747c8709..ddedd51ab26d9 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -2857,5 +2857,3 @@ module_platform_driver(udma_driver); MODULE_DESCRIPTION("Texas Instruments UDMA support"); MODULE_LICENSE("GPL v2"); =20 -/* Private interfaces to UDMA */ -#include "k3-udma-private.c" --=20 2.54.0 From nobody Tue Sep 29 08:26:17 2026 Received: from mx0b-0002e601.pphosted.com (mx0b-0002e601.pphosted.com [148.163.154.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B38D636DA1A; Mon, 28 Sep 2026 02:59:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.154.28 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564354; cv=fail; b=rKeXCsJm12w48OyycV0bypnt1a61SZLFR3rfZZw0owm0Mk5G1ah5dnbNUomHZ99l85vi5blzLxrJUk22yO5xpJuj8U+c5+zDgsisXNifuA/UgPhO9JAlHVSarAG3TSKVHM1Ih82WWriexOyS1oiRsPBnFOpkrwLzu03VGeHjRmE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564354; c=relaxed/simple; bh=3kueG8Wpje7rJ+Pgv3ADxRyZSbSU8IYt3jDgNMUkNBw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=iyZYt1bkgqt+zunJUY9an6b6w5gGRGDpcTd4uqbGatTjr2WUZqPqz9uSH+iPH9FnRt5ebrOfAKsYS51mMj1N3OZCkK9vlIOIsOVFyIbfcr5jVVUnhI6Q1ku0jeQE8FAzsWXJFOJGB60ba/qO8JqGatLhgOqSOEYEyK5zNRx1aDw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=mrDOPBIt; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=E4kRtNls; arc=fail smtp.client-ip=148.163.154.28 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="mrDOPBIt"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="E4kRtNls" Received: from pps.filterd (m0374955.ppops.net [127.0.0.1]) by mx0b-0002e601.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68RMIQXN2806212; Sun, 27 Sep 2026 21:59:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=4HFwqLYoy5w0cVsCk363PdZE219la0RU3eCFrZ602 dk=; b=mrDOPBItdkbHFyx6WbAuWtY5zefnRFeLsgvUay3xbzxFylK1Ts/DTzJ55 gtgfThkLiS/YC0HkNnpIewlYwf+pn9h6OSV4rHSfm+5VQTwnRhb441A87PtAjKUh 5nCa+JEMS5SfJsH8jiGn2Pg3V1SjdCcQIPz2DmFLcODDVeYm+IyDwTgYIDeUhyHT hfTKwvW3vRTHQ6MFbD3zWGKxjxUSov9i+04LMABPKv49OauhQ6bZ8w4vS96Y6Nc2 mY9L5xxwszRTiQCyysMMCNAV7R42DU5YIA6vV1JalA6bcgE4/hpCvErDuu2gNix1 e0jFRVj5ham1xtOnDtFM2wIqJ/anA== Received: from ph0pr06cu001.outbound.protection.outlook.com (mail-westus3azon11011065.outbound.protection.outlook.com [40.107.208.65]) by mx0b-0002e601.pphosted.com (PPS) with ESMTPS id 4gxwe5kfqm-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Sun, 27 Sep 2026 21:59:02 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=c2G66s+zaic4GP+jhgYfnkG6a7SNnd2WCgi1hJLhjEmtWkx9ApIRnPBf8tdkQywhkByprH9DyzmyUA80PTKi2OujTdcLeSHt8SWCyP9yuhcdjpk7Ao7z77kRZG5T37f8cZGrN8jUzo721eHSbA72UiTBzms+PaVn7V/rix5hAd732iu7FbP/sXnHEzomZEBkOCGybGNB674zme6HQqp+q9rda86Cngq5kryohOGgYIljKD0NSCbXVlA4sKCBs+2FqHndlRiNtNVVZoUYecnBV0NbB6GJfQHIykUVRsC2PdIYapj2psCMDr+iyvX2OWgwyxJHHcG5s6sG8BtTPXRpOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=4HFwqLYoy5w0cVsCk363PdZE219la0RU3eCFrZ602dk=; b=e7LZcl6lyMhF2QDuWH/V+zGkK2y+feRUoCBzdu5A+uF7gv7m0owYabXPPi9B16UkkHFbRi+V9RJrhWoaxnG4HY2Z+1MTmE8JLJQUYsuWYgzZaSvn1JRj9cex9m4azfPl62OrioX4RbEEjFsnnBzBMa5UMNCbfjppkFoXzAX2IAWgXxrtSF1BHEYWIM0FH/TYoYUnd8xqzkTGEC1UdG485lXT7OcvvKMEU7A/3lnXlgq+FD0dol8NfmWWNYTuQfBblkjLDtdp4U6dg2O5u0ABksTZYdS3gKqugn5hf2gnPaQIkfNDHSfPbNFxAfGJmiGYbVdosdtqVnDgwGxyRZM8oQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.23.194) smtp.rcpttodomain=nxp.com smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4HFwqLYoy5w0cVsCk363PdZE219la0RU3eCFrZ602dk=; b=E4kRtNlshblTYtukGjoTY0pBfwePoE4gxjg6eYKnrwASCB1OnR7E6VP0roO1PrHXICQRS+GOH+OIsla6XPS0reBaFBj8533/PLR4jkFa/70563L134mxwiRWAfG5cCquRpmqfPwQuLUi3sJGXMzjTzg3pen8hgZ5QH/dhuZn7oA= Received: from CH0PR03CA0313.namprd03.prod.outlook.com (2603:10b6:610:118::34) by SN4PR10MB998044.namprd10.prod.outlook.com (2603:10b6:806:214::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.451.18; Mon, 28 Sep 2026 02:58:57 +0000 Received: from CH2PEPF00000146.namprd02.prod.outlook.com (2603:10b6:610:118:cafe::d) by CH0PR03CA0313.outlook.office365.com (2603:10b6:610:118::34) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.451.23 via Frontend Transport; Mon, 28 Sep 2026 02:58:57 +0000 X-MS-Exchange-Authentication-Results: mx.microsoft.com 1; spf=pass (sender IP is 198.47.23.194) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.23.194 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.23.194; helo=lewvzet200.ext.ti.com; pr=C Received: from lewvzet200.ext.ti.com (198.47.23.194) by CH2PEPF00000146.mail.protection.outlook.com (10.167.244.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Mon, 28 Sep 2026 02:58:57 +0000 Received: from DLEE210.ent.ti.com (157.170.170.112) by lewvzet200.ext.ti.com (10.4.14.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:54 -0500 Received: from DLEE210.ent.ti.com (157.170.170.112) by DLEE210.ent.ti.com (157.170.170.112) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:54 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE210.ent.ti.com (157.170.170.112) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45 via Frontend Transport; Sun, 27 Sep 2026 21:58:54 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [10.24.51.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 68S2vqqJ2256662; Sun, 27 Sep 2026 21:58:50 -0500 From: Sai Sree Kartheek Adivi To: , , , , , , , , , , , , , CC: , Subject: [PATCH v10 12/19] drivers: soc: ti: k3-ringacc: handle absence of tisci Date: Mon, 28 Sep 2026 08:26:18 +0530 Message-ID: <20260928025749.1055383-13-s-adivi@ti.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260928025749.1055383-1-s-adivi@ti.com> References: <20260928025749.1055383-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000146:EE_|SN4PR10MB998044:EE_ X-MS-Office365-Filtering-Correlation-Id: dfad4083-5db7-421c-e595-08df1d0c7098 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|23010399003|82310400026|36860700016|7416014|376014|921020|6133799003|10067099003|56012099006|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: /tYNWeJUR4dydBeiLEaZl0GgxuD/nZvkbx71yqeY4B7pzuFM87LmB8MsQJnrobXyiMXxvp3aRbJYZEZWuaRniB3GeCh5Vr2RMDa9vdHT/Jr11J6kNrrL9ct4pazkx7cfsvXfJ3QZdhy/3TrksubFKixQPrcvfSYTWus6WHDXqx5evbkaXV99eoI20dY+5b8A18V5mOFaFvS15Bb3elOhE0ka2O2AVD63WGhbPan7Gh4GqZQlvlXKec/7SnitIxHELca2YW862XxAj+fYYLlyCTIcIFSFTfY88ULSF9EBrC+MWUsGoVHejH4uzRPssrsbXwjDODwmipT8ZkvA/WPE1swYOcoI9mf9Kh7gqGvVPJQyX2y+Y9h6AfWT+KdtI+xQ9prT9ACVFJzXneW8mT202SDP4jcKHVjBNFk9W1qmSqQl+v2d8BYDWtAhR4Zg/or4NmDskpVQ8Oa+wiBtohDwsmRkXEpb/6JjU2AscXYXZlvbpFrwjC8XVyYlh13nCt8iqG+8mqiB1jBCCxNPVh+neMYRGr7QmPtrMoypyYE8actfte6UzjETJQN67MkfUfP0vXqQmfEJYwtggeAqKCDt6gcIdt8SprVRSDMZlapfVh4D57zBPrp0bEfmmNA8rnzvvZ96nWJ+K9vctsSVHsO3tcC5nouqGc3Mp4g8nhwFZjd+DvgTgOqAr0z6rGNbrMcZCILqyRKTfeFi/Unz4YLDw4pA1kizbXKCn/E/W6Jd7mBQM37TY+wMyGyk2J/n6vbK X-Forefront-Antispam-Report: CIP:198.47.23.194;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:lewvzet200.ext.ti.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(23010399003)(82310400026)(36860700016)(7416014)(376014)(921020)(6133799003)(10067099003)(56012099006)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6Er6T6DjZKA//7MmTDmIyfTS3q0IgFjdx18tID0y3WEpGZpwwGvFmeeHuggnw57w0JvBFDrpHBKDkX2hDg90D3To003LSxoj4M3HvAm+V5QwuxHwqk5qNB3LB1SS9g4xg6AdLgh4Jp/Pehd14VqFk1lWo5wrPjeNqMovNPPEWkax1ZmlSB7sm3uKeqAt+TEtov00W+F8kZl5/2Fu5DnB+08jOyFhE5jFUQVpmxwuWLNK23aYOpZndOJelJD1z7RIHpjt2JvjvWv+3rWAPjr4qQzMmfzlHlNVcIteVn0pYdb7iZyWNdlkAwFR0lfSkuTqyIV6T0aDKgdgfwlbE/vfKUECckjrKiYZSvmyn1EBps9Uvq2RQKXoiinTJt6fj8PmfWTY/d2I03nqSrFD6TULzpn8sqQY9tJ5TYa1p3PewqfWNTLjTWaJA/kaBKnHNCjf X-Exchange-RoutingPolicyChecked: ZZuzSm+7ub3pRbO+BsmU9rT5Lqk7y6uI6MnaDq7h1qYPcuQdFwE+qzbasR+tFyZeEUWJszvEo16iupZtRKZGT2yvpFBHyX/840w9pvVkTgf1lu0zyUUoB334tlmYyR9kaF7D8bJRpX9bskgmRTroYDVW4yXqglf+sCFLGOeydvKmX8mwGJNCGA2iHNSd9Qm3FjhFnhA/iNkk8GGT1QO/OEgA2EswCx2CbAIzzQe7ReHNtqH2Ro58uFhbf4vGU3IaTgMHIC7ZAkN0kFU/S58lcChGeXkImPhgusYYeREXiTBRA9vafwFgzGBF/GPuqOZFw1O64PdQyw0oKMBmrOqfqQ== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 02:58:57.4840 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dfad4083-5db7-421c-e595-08df1d0c7098 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.194];Helo=[lewvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000146.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN4PR10MB998044 X-Authority-Analysis: v=2.4 cv=aeP0Dhot c=1 sm=1 tr=0 ts=6ab9d7f6 cx=c_pps a=qx7sgmNqCaiUqJuMW1Xodg==:117 a=WotqVVQAdb04rnGuttW3Kw==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=VdqzKS8jKosA:10 a=s63m1ICgrNkA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=fPAWb5peG099m5CrUpKH:22 a=sozttTNsAAAA:8 a=AlZmxT5CGg0Uo3zr_lEA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX2AEDPmfa8eL5 Q+711JzUcITvJ0xIYaDTUbbMKICsm5K8PG8W9GI4D99J13Nm/sqHC+/ZsW4VdTDAULPk07XS5zB Y7pQjTc+odx9aV+lbvJ6Vf7n5UH9G7iJL1nxiuEeBE8igm3XQ0+mRcfoTmQu2dCzHacRMOgsEs0 e4680HqnnlbmF1gqJadOV0l/Z/gGPKlW02kKaOBzKNY5DiIBdlxswn74H8AsWJ9Hp7cU60+Ob01 bsOC10RVxlgDbo7u61bCFT2krOC/07uh6O6LXdUdZoM02XeYHdAejddwg8LOeh9WVzbpBb+geJE DUG+H9QIF1VF1p+6Nb3AiTpJUk8mzw2TMwpee7ijkbc7jAvLSW2XqUeGOwkP4eQetSVdOk0Qzg5 5wIeqQpXCqCelJSfvjWvkLUG/tkcgWwyjl90gCXLkHeFsSrtz3wwilxPqCulQJEm6Ew3YnS1VvK X/fvf9/WlGbDEuRb8pQ== X-Proofpoint-ORIG-GUID: zw5yDoyX54r9T9XJ0lkYOnLcGkngSD4u X-Proofpoint-GUID: zw5yDoyX54r9T9XJ0lkYOnLcGkngSD4u X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX15PxNc4a8HVb QOWTpnvdrWnUUH9XVD7nEl+BYRad4q9gjSDfokLoHQR4GlqwpHs/xJ/iFehwR/nH9vHrL3qPsiu RiQ74Wy7mJnth4S8Wh+b1XrYQGztIqo= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 phishscore=0 spamscore=0 clxscore=1015 adultscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280011 Content-Type: text/plain; charset="utf-8" Handle absence of tisci with direct register writes. This will support platforms that do not have tisci firmware like AM62L. Signed-off-by: Sai Sree Kartheek Adivi --- drivers/soc/ti/k3-ringacc.c | 180 ++++++++++++++++++++++++++---- include/linux/soc/ti/k3-ringacc.h | 18 +++ 2 files changed, 179 insertions(+), 19 deletions(-) diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c index 5966db4327b13..15fab94e8cad0 100644 --- a/drivers/soc/ti/k3-ringacc.c +++ b/drivers/soc/ti/k3-ringacc.c @@ -7,6 +7,7 @@ =20 #include #include +#include #include #include #include @@ -46,6 +47,53 @@ struct k3_ring_rt_regs { u32 hwindx; }; =20 +#define K3_RINGACC_RT_CFG_REGS_OFS 0x40 +#define K3_DMARING_CFG_ADDR_HI_MASK GENMASK(3, 0) +#define K3_DMARING_CFG_ASEL_SHIFT 16 +#define K3_DMARING_CFG_SIZE_MASK GENMASK(15, 0) + +/** + * struct k3_ring_cfg_regs - The RA Configuration Registers region + * + * @ba_lo: Ring Base Address Low Register + * @ba_hi: Ring Base Address High Register + * @size: Ring Size Register + */ +struct k3_ring_cfg_regs { + u32 ba_lo; + u32 ba_hi; + u32 size; +}; + +#define K3_RINGACC_RT_INT_REGS_OFS 0x140 +#define K3_RINGACC_RT_INT_ENABLE_SET_COMPLETE BIT(0) +#define K3_RINGACC_RT_INT_ENABLE_SET_TR BIT(2) + +/** + * struct k3_ring_intr_regs { + * + * @enable_set: Ring Interrupt Enable Register + * @resv_1: Reserved + * @clr: Ring Interrupt Clear Register + * @resv_2: Reserved + * @status_set: Ring Interrupt Status Set Register + * @resv_3: Reserved + * @status: Ring Interrupt Status Register + * @resv_4: Reserved + * @status_masked: Ring Interrupt Status Masked Register + */ +struct k3_ring_intr_regs { + u32 enable_set; + u32 resv_1; + u32 clr; + u32 resv_2; + u32 status_set; + u32 resv_3; + u32 status; + u32 resv_4; + u32 status_masked; +}; + #define K3_RINGACC_RT_REGS_STEP 0x1000 #define K3_DMARING_RT_REGS_STEP 0x2000 #define K3_DMARING_RT_REGS_REVERSE_OFS 0x1000 @@ -139,6 +187,8 @@ struct k3_ring_state { * struct k3_ring - RA Ring descriptor * * @rt: Ring control/status registers + * @cfg: Ring config registers + * @intr: Ring interrupt registers * @fifos: Ring queues registers * @proxy: Ring Proxy Datapath registers * @ring_mem_dma: Ring buffer dma address @@ -158,6 +208,8 @@ struct k3_ring_state { */ struct k3_ring { struct k3_ring_rt_regs __iomem *rt; + struct k3_ring_cfg_regs __iomem *cfg; + struct k3_ring_intr_regs __iomem *intr; struct k3_ring_fifo_regs __iomem *fifos; struct k3_ringacc_proxy_target_regs __iomem *proxy; dma_addr_t ring_mem_dma; @@ -467,15 +519,37 @@ static void k3_ringacc_ring_reset_sci(struct k3_ring = *ring) struct k3_ringacc *ringacc =3D ring->parent; int ret; =20 - ring_cfg.nav_id =3D ringacc->tisci_dev_id; - ring_cfg.index =3D ring->ring_id; - ring_cfg.valid_params =3D TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID; - ring_cfg.count =3D ring->size; + if (!ringacc->tisci) { + u32 reg; =20 - ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); - if (ret) - dev_err(ringacc->dev, "TISCI reset ring fail (%d) ring_idx %d\n", - ret, ring->ring_id); + if (!ring->cfg) + return; + + reg =3D readl(&ring->cfg->size); + reg &=3D ~K3_DMARING_CFG_SIZE_MASK; + writel(reg, &ring->cfg->size); + + ret =3D readl_poll_timeout(&ring->cfg->size, reg, + !(reg & K3_DMARING_CFG_SIZE_MASK), + 1, 100); + if (ret) + dev_err(ringacc->dev, "ring %d size clear timeout\n", + ring->ring_id); + + reg =3D readl(&ring->cfg->size); + reg |=3D ring->size; + writel(reg, &ring->cfg->size); + } else { + ring_cfg.nav_id =3D ringacc->tisci_dev_id; + ring_cfg.index =3D ring->ring_id; + ring_cfg.valid_params =3D TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID; + ring_cfg.count =3D ring->size; + + ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); + if (ret) + dev_err(ringacc->dev, "TISCI reset ring fail (%d) ring_idx %d\n", + ret, ring->ring_id); + } } =20 void k3_ringacc_ring_reset(struct k3_ring *ring) @@ -501,6 +575,9 @@ static void k3_ringacc_ring_reconfig_qmode_sci(struct k= 3_ring *ring, ring_cfg.valid_params =3D TI_SCI_MSG_VALUE_RM_RING_MODE_VALID; ring_cfg.mode =3D mode; =20 + if (!ringacc->tisci) + return; + ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); if (ret) dev_err(ringacc->dev, "TISCI reconf qmode fail (%d) ring_idx %d\n", @@ -576,10 +653,28 @@ static void k3_ringacc_ring_free_sci(struct k3_ring *= ring) ring_cfg.index =3D ring->ring_id; ring_cfg.valid_params =3D TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER; =20 - ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); - if (ret) - dev_err(ringacc->dev, "TISCI ring free fail (%d) ring_idx %d\n", - ret, ring->ring_id); + if (!ringacc->tisci) { + u32 reg; + + writel(K3_RINGACC_RT_INT_ENABLE_SET_COMPLETE | K3_RINGACC_RT_INT_ENABLE_= SET_TR, + &ring->intr->clr); + + reg =3D readl(&ring->cfg->size); + reg &=3D ~K3_DMARING_CFG_SIZE_MASK; + reg |=3D ring_cfg.count & K3_DMARING_CFG_SIZE_MASK; + + writel(reg, &ring->cfg->size); + + writel(ring_cfg.addr_lo, &ring->cfg->ba_lo); + writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) + + (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT), + &ring->cfg->ba_hi); + } else { + ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); + if (ret) + dev_err(ringacc->dev, "TISCI ring free fail (%d) ring_idx %d\n", + ret, ring->ring_id); + } } =20 int k3_ringacc_ring_free(struct k3_ring *ring) @@ -670,15 +765,36 @@ int k3_ringacc_get_ring_irq_num(struct k3_ring *ring) } EXPORT_SYMBOL_GPL(k3_ringacc_get_ring_irq_num); =20 +u32 k3_ringacc_ring_get_irq_status(struct k3_ring *ring) +{ + struct k3_ringacc *ringacc =3D ring->parent; + struct k3_ring *fwd_ring =3D &ringacc->rings[ring->ring_id]; + + if (!fwd_ring->intr) + return 0; + + return readl(&fwd_ring->intr->status); +} +EXPORT_SYMBOL_GPL(k3_ringacc_ring_get_irq_status); + +void k3_ringacc_ring_clear_irq(struct k3_ring *ring, u32 status) +{ + struct k3_ringacc *ringacc =3D ring->parent; + struct k3_ring *fwd_ring =3D &ringacc->rings[ring->ring_id]; + + if (!fwd_ring->intr) + return; + + writel(status, &fwd_ring->intr->status); +} +EXPORT_SYMBOL_GPL(k3_ringacc_ring_clear_irq); + static int k3_ringacc_ring_cfg_sci(struct k3_ring *ring) { struct ti_sci_msg_rm_ring_cfg ring_cfg =3D { 0 }; struct k3_ringacc *ringacc =3D ring->parent; int ret; =20 - if (!ringacc->tisci) - return -EINVAL; - ring_cfg.nav_id =3D ringacc->tisci_dev_id; ring_cfg.index =3D ring->ring_id; ring_cfg.valid_params =3D TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER; @@ -689,6 +805,24 @@ static int k3_ringacc_ring_cfg_sci(struct k3_ring *rin= g) ring_cfg.size =3D ring->elm_size; ring_cfg.asel =3D ring->asel; =20 + if (!ringacc->tisci) { + u32 reg; + + writel(ring_cfg.addr_lo, &ring->cfg->ba_lo); + writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) + + (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT), + &ring->cfg->ba_hi); + + reg =3D readl(&ring->cfg->size); + reg &=3D ~K3_DMARING_CFG_SIZE_MASK; + reg |=3D ring_cfg.count & K3_DMARING_CFG_SIZE_MASK; + + writel(reg, &ring->cfg->size); + writel(K3_RINGACC_RT_INT_ENABLE_SET_COMPLETE | K3_RINGACC_RT_INT_ENABLE_= SET_TR, + &ring->intr->enable_set); + return 0; + } + ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); if (ret) dev_err(ringacc->dev, "TISCI config ring fail (%d) ring_idx %d\n", @@ -1481,9 +1615,12 @@ struct k3_ringacc *k3_ringacc_dmarings_init(struct p= latform_device *pdev, =20 mutex_init(&ringacc->req_lock); =20 - base_rt =3D devm_platform_ioremap_resource_byname(pdev, "ringrt"); - if (IS_ERR(base_rt)) - return ERR_CAST(base_rt); + base_rt =3D data->base_rt; + if (!base_rt) { + base_rt =3D devm_platform_ioremap_resource_byname(pdev, "ringrt"); + if (IS_ERR(base_rt)) + return ERR_CAST(base_rt); + } =20 ringacc->rings =3D devm_kzalloc(dev, sizeof(*ringacc->rings) * @@ -1499,6 +1636,10 @@ struct k3_ringacc *k3_ringacc_dmarings_init(struct p= latform_device *pdev, struct k3_ring *ring =3D &ringacc->rings[i]; =20 ring->rt =3D base_rt + K3_DMARING_RT_REGS_STEP * i; + ring->cfg =3D base_rt + K3_RINGACC_RT_CFG_REGS_OFS + + K3_DMARING_RT_REGS_STEP * i; + ring->intr =3D base_rt + K3_RINGACC_RT_INT_REGS_OFS + + K3_DMARING_RT_REGS_STEP * i; ring->parent =3D ringacc; ring->ring_id =3D i; ring->proxy_id =3D K3_RINGACC_PROXY_NOT_USED; @@ -1512,7 +1653,8 @@ struct k3_ringacc *k3_ringacc_dmarings_init(struct pl= atform_device *pdev, ring->flags =3D K3_RING_FLAG_REVERSE; } =20 - ringacc->tisci_ring_ops =3D &ringacc->tisci->ops.rm_ring_ops; + if (ringacc->tisci) + ringacc->tisci_ring_ops =3D &ringacc->tisci->ops.rm_ring_ops; =20 dev_info(dev, "Number of rings: %u\n", ringacc->num_rings); =20 diff --git a/include/linux/soc/ti/k3-ringacc.h b/include/linux/soc/ti/k3-ri= ngacc.h index 39b022b925986..4b6ec925e2f2d 100644 --- a/include/linux/soc/ti/k3-ringacc.h +++ b/include/linux/soc/ti/k3-ringacc.h @@ -158,6 +158,23 @@ u32 k3_ringacc_get_ring_id(struct k3_ring *ring); */ int k3_ringacc_get_ring_irq_num(struct k3_ring *ring); =20 +/** + * k3_ringacc_ring_get_irq_status - Get the irq status for the ring + * @ring: pointer on ring + * + * Returns the interrupt status + */ +u32 k3_ringacc_ring_get_irq_status(struct k3_ring *ring); + +/** + * k3_ringacc_ring_clear_irq - Clear the given interrupts + * @ring: pointer on ring + * @status: mask of interrupt status bits to clear + * + * Clears only the interrupt status bits set in @status on the ring + */ +void k3_ringacc_ring_clear_irq(struct k3_ring *ring, u32 status); + /** * k3_ringacc_ring_cfg - ring configure * @ring: pointer on ring @@ -262,6 +279,7 @@ struct k3_ringacc_init_data { const struct ti_sci_handle *tisci; u32 tisci_dev_id; u32 num_rings; + void __iomem *base_rt; }; =20 struct k3_ringacc *k3_ringacc_dmarings_init(struct platform_device *pdev, --=20 2.54.0 From nobody Tue Sep 29 08:26:17 2026 Received: from mx0a-0002e601.pphosted.com (mx0a-0002e601.pphosted.com [148.163.150.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41A5536E48C; Mon, 28 Sep 2026 02:59:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.150.75 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564370; cv=fail; b=bOvCNuiNdvA/xHmv500kCWYm6Mbua+Bf7VsnpPT5cx5rhY1xYssVlUm+7C7riLn6K5zdctOS17BO4KsN+yTg772K+k/IKgLD+LCsKDyJ+a3+gjrj7ZNiY1bOm33YlFD+LeJtbcjiKxXR/fRRHuqxJllLYIHIT1WKMzuSCesx+eE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564370; c=relaxed/simple; bh=ohB6AyPL1yGPs/XQrk1PoSqa8tTfeiAf7nsFDQnY7WU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=n2UHIL0J6fv5YJa678EpnwwZG25nr35iHomMr7LRiY11KM7l+0E/TyeKnXJJJ2FNpe7R9SWk8eaFHMRYb6KmE33UK/Bau3fWeF4RT6xUFv1EbQlen6p0+QvG0smsXNTlLnA2rSiHT/rMHSOZaVXwXNc7dllkQx8iVvHwnumjsTc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=PPY9LYY1; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=jyU+QoXx; arc=fail smtp.client-ip=148.163.150.75 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="PPY9LYY1"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="jyU+QoXx" Received: from pps.filterd (m0380145.ppops.net [127.0.0.1]) by m0380145.ppops.net (8.18.1.11/8.18.1.11) with ESMTP id 68RNEFCT2775340; Sun, 27 Sep 2026 21:59:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=sOa2U5ZSaBR2ea/MCYm95KDZuvR6EJKU/8kMxBPtU yI=; b=PPY9LYY1NncJogXoqjFS4tVXqCE8pT+mWhefTQLqySldivxQxD3ruxcvK 8XQM06bnbKOgfLl9ROvCU0DtxEV4SCFmZzRBLpTVNA6gmQppMN60K2wB0O2XjiMe Qk4AxD0SDM5g3yjM0D2mpDVIGrWEImpP67EOtOQb8cT9482zbMlhJYyHnRLejWYr RPAIqi7ssX6EfHrP4r/8xVhwU4z3Z4OlnAhl0hCwse6sYQ4+K+lHDKCjj2KvCsYi lHKXO7kTyD4Ak28hp3x+SkMYTRPsH52dJM4HLeBJ4ZMkBxUapJMtZ9eERdJWqkuO rGSeWo8tXJndLYQ+tVXt5a21rMhrg== Received: from cy7pr03cu001.outbound.protection.outlook.com (mail-westcentralusazon11010024.outbound.protection.outlook.com [40.93.198.24]) by m0380145.ppops.net (PPS) with ESMTPS id 4gxy2nk6fe-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Sun, 27 Sep 2026 21:59:19 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=lExGGNojCNydlcGhp/RfnZrCQwAKAoK4FltWl3AZ805C0pf81kQStTTfsWKg5miMZfPJd+5MPU+pxt8Rld5F5KNe5adgwu21JIDU5cyJIEvoIJq4bkHvUIKjWZcJ5HYJT0ix6RW7OgYwaTIgfTlHD6qqeSnJX4HcBnYA8DrVdjTkif/wwKFUW9UgvUvXVkmMtSsh1AhEgXyOuqZal4zgIxNhbcwEZdxmLoXFw/Y4EyZHaLvaPdL4rlh9KIXDvl9EeYBjLfgdwsd3MB7p3nL52ofKTQNBgZKErQXtFEQYNy8XkfpN+DubdNrOdIT4sW4GtO6YY515KWd9nqocloMB0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=sOa2U5ZSaBR2ea/MCYm95KDZuvR6EJKU/8kMxBPtUyI=; b=QqI1eYDBwty3BlCOnT6eDmI0rB2C2i3tR1BMaX1YLE0J9EJmT3uj25XrbwwmnUas5FeB3MQue8dGrO9B0CZy3aFTzlY0i30g8UOJSPwdifEjt0fZE59Z1yRTMikcw+gzTu4UuxUAhfZ1+uxliXRioM6qPJoYZI5Gd34N0ujw7MEKr7wBXzT/QOwpZld+GAuZGgFelZ3fGtY8msjLZFLexb+w5g1voTMCihbf6gAbcooUBrvqstCfwXx4EdJM6FZfcmuyYViCxyBvfhLfz9MSMhXo4wXSbS15eSWXyOpqvPkthmZABP4ATmA4C5pIqyXlDWA/MrgXh2pFP6xF62biaw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.23.195) smtp.rcpttodomain=nxp.com smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sOa2U5ZSaBR2ea/MCYm95KDZuvR6EJKU/8kMxBPtUyI=; b=jyU+QoXx/0sAzj1Q08oTUsxHvdfacsEeGA0nKQQrdgwlLwyXuJLdi6KFSm9caW/hOlhM8+6CpaKwuaC4PxOa4dFL94UbcwywQVh2V0lenmz9mMZl5fE3pn0ZRorA/8jWC1eialKOEpRoxr3fGcKVOv3LpJYWODV7CzVBF7jdGCA= Received: from SJ0PR03CA0086.namprd03.prod.outlook.com (2603:10b6:a03:331::31) by CH0PR10MB7439.namprd10.prod.outlook.com (2603:10b6:610:189::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.451.19; Mon, 28 Sep 2026 02:59:15 +0000 Received: from SJ5PEPF000001EF.namprd05.prod.outlook.com (2603:10b6:a03:331:cafe::1) by SJ0PR03CA0086.outlook.office365.com (2603:10b6:a03:331::31) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.451.23 via Frontend Transport; Mon, 28 Sep 2026 02:59:15 +0000 X-MS-Exchange-Authentication-Results: mx.microsoft.com 1; spf=pass (sender IP is 198.47.23.195) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.23.195 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.23.195; helo=lewvzet201.ext.ti.com; pr=C Received: from lewvzet201.ext.ti.com (198.47.23.195) by SJ5PEPF000001EF.mail.protection.outlook.com (10.167.242.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Mon, 28 Sep 2026 02:59:15 +0000 Received: from DLEE212.ent.ti.com (157.170.170.114) by lewvzet201.ext.ti.com (10.4.14.104) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:59 -0500 Received: from DLEE211.ent.ti.com (157.170.170.113) by DLEE212.ent.ti.com (157.170.170.114) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:58:59 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE211.ent.ti.com (157.170.170.113) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45 via Frontend Transport; Sun, 27 Sep 2026 21:58:59 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [10.24.51.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 68S2vqqK2256662; Sun, 27 Sep 2026 21:58:55 -0500 From: Sai Sree Kartheek Adivi To: , , , , , , , , , , , , , CC: , Subject: [PATCH v10 13/19] dt-bindings: dma: ti: Add K3 BCDMA V2 Date: Mon, 28 Sep 2026 08:26:19 +0530 Message-ID: <20260928025749.1055383-14-s-adivi@ti.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260928025749.1055383-1-s-adivi@ti.com> References: <20260928025749.1055383-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001EF:EE_|CH0PR10MB7439:EE_ X-MS-Office365-Filtering-Correlation-Id: be4e162c-1680-4986-65cf-08df1d0c7b21 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|7416014|1800799024|36860700016|82310400026|13003099007|921020|3023799007|6133799003|10067099003|56012099006|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: KDuRZW0lBedeQ0T4qJ4TfGcJej2LzXO1TIx7huOBsBgLmIl2XO628yPv7FcBtd5UoUJhMctaTY0Z6RAZG4dRvRu/gbDV72O/ohffbJXiA8HLKkzhj777S4+N7jWZGzv+yk8iW1NS7XXhGYw8jYhJlLbZZpSgTySqRy2iS9VMrP9dJtv/fSfLVb9ueVdbMNksZ6bL2epTYSCXvjR0AzfESV1TtsiOh/IVRF37tM9trh5FBdms9T5UwlbzkDhoEcuqWsBJfTRx6ltkIRIjNqzuOP1414Aa6+bnEzBLNdH5dmVJUaEQ7IFPEFSih5HilIQ7Tk2qYDySpvjA95XjX3VOHmPd/Rg7CuSdvFowxeveIVdwTODn3j+3Jv/d/QsjCG/N/3vKUHA/uLJ6yIJGDIuRwwOWxq5hcN2P1oMecW/gdC4J+t6QgpF37MEfKt2LcHzq30j6nno3/1INbcpdrZxnMjFpA2KiL+7TuFJwaertRVccWwfW32qsz1+NA0hqXlyUUPk6L1iQwcJjYBbOtBKhzrqWdBEhaodVn1rAuIaInNsEHG2igyJ1bEZALtxq1T2fE70m7HeHhN08CBD3vLuEOk3I06L+kCPmELMEtl1Gch8M/vaOz5bjCCqMW+kM7cZ9gWSqJOAtOqty2awWWiREpOYCkv+GnP/Q6q6k0y/MaHsVqVlsoZWfoJ1qWXD+jCPdAS2rYEk3kmFjoKrlPTQ5iw== X-Forefront-Antispam-Report: CIP:198.47.23.195;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:lewvzet201.ext.ti.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(23010399003)(376014)(7416014)(1800799024)(36860700016)(82310400026)(13003099007)(921020)(3023799007)(6133799003)(10067099003)(56012099006)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 9WTuwGcd7OSKBjCKq0Narv3aid5QITqWYl6D4c3T15RY2gmwSfUtqcyFllcTEyH/O/CN67vaxUuS3x79NumHXjVat30sLXAGAHfaZNfIU5ysw60UWC1NJfdztzK0Lv3EoMrZpt30hTQPn/tluJu8Z9t6jyTpLtBPaAPVQ3rqswgywdj3+lm0c8h7EeVyKhoDeSiComGwrIJqoyPUoGuK3hXH+MCY4r9xzCf87W2Gdhm+RybzbuThuHbx3xAmfe/OJUqfwrlXpQ3Ai+h1sBXN5XFercLs+9dwIlA7rsw/aa+Bn4MAi1ZtOynGasRooyjgFVlMrfBMWDaA0k2NE+F0BdfamWzISeKJtyX5Pvne+wk3grocHbZYBN8NeVw3tUS6KdI4gkd/CtJyIZj4imv29Js57uW9+qzUrYEEcjhliaHbEKxydJVdVx/B/D6AFTPm X-Exchange-RoutingPolicyChecked: 3UoCeZqM79TNaJAokQad71C7C71bjjTDDJSrfEeTZJxSPDEUnP5INliQ46M/51i5674b8nvJVSGHCe57jprfRnNiblds+9eHlT0dBc0Zzc4TIKZ3Cbrqqk4X1wuZBqqsGqgFq+E+UX2CosE6yuG7ZaUDR6EMkEYMo/cRglBwuJdRzUbW8Eq/50NfPDGh1tOSznf+PaAdRyQIbqVd47sNuNTk1pLUijdb3gVmi7ZXz08VvqY1kqDQGJ33joFP+PIJ19hqcqHRyWWgrUrN7j7SUdln9Lk2vE9fGHyrYCoUIAfEmz9Lnj7b7d8HhUKmSWz45eRlK0Kxu771c8sPEck8pA== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 02:59:15.1127 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be4e162c-1680-4986-65cf-08df1d0c7b21 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001EF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR10MB7439 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX70Rbcz/PbD4V Ars+KijaRRV+EQkmAHNOO1DwfDdsnfAWo9HRp7Ay8vhSWqpaGARh6hQb3yiZfrTGmDYU8WJVqYK XuN9jhsVjbXVrAdMlXQLJhBRv3B9rfg= X-Proofpoint-ORIG-GUID: r_OvPNcv8aXLW3vkVMn5oHcrbGGqnf7g X-Authority-Analysis: v=2.4 cv=RLgmjIi+ c=1 sm=1 tr=0 ts=6ab9d807 cx=c_pps a=V/jExjqSSumuV0DCu/2ZVg==:117 a=f+v6EHfkeJbVwR46tk4DMg==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=VdqzKS8jKosA:10 a=s63m1ICgrNkA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=gO1vWkAQAl3rybz1DQOp:22 a=gEfo2CItAAAA:8 a=sozttTNsAAAA:8 a=EUspDBNiAAAA:8 a=6W6IBMoaatw3SABbmX8A:9 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-GUID: r_OvPNcv8aXLW3vkVMn5oHcrbGGqnf7g X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX86mi9Dyr7XUr MFkdMZqRaX43YZIIACyLsZcYmAzF0xybGXCWqMa4N7vg3bmXeTCWQ6u2twV6vtxH7I90HDXH7z2 bkctC/AzDyGxuo6t+EIfxlGtYHrQBB8AuhstoIi8ctvoDCsNaAjGxdvSzCa3BDGEXk8duVP1hO4 WJnzpcaUFNzlfg18FeDEbKQuWe1WHT31/63xYZoolNQ5mnfM3ijA1GvoZ/YYYxQ0XmDqJK13Aor Cvh4C10WiO2rq97NI+27JuXGuhkwlnWFAm8nXbAI09H6KJb15EQLLaHkpvv0tn2+ilgF3hSDIXQ SWn/axjugXgapo9cPksgYahYHy3IF1mB0Qh++dvKZTJwSpdRZ89lveIr8/zx30GVvAtlvsndXzb nu0MIGEd7AgQ4ADOFd8mV8BlDMIjuw7giDLbS621eIvpkGHN3YoC8ONGt2oKDTuqIsSYHHlTUkC HH7yQ7G207HB9W/7lIw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 malwarescore=0 adultscore=0 suspectscore=0 clxscore=1015 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280011 Content-Type: text/plain; charset="utf-8" New binding document for Texas Instruments K3 Block Copy DMA (BCDMA) V2. BCDMA V2 is introduced as part of AM62L. Signed-off-by: Sai Sree Kartheek Adivi Reviewed-by: Krzysztof Kozlowski --- .../bindings/dma/ti/ti,am62l-dmss-bcdma.yaml | 211 ++++++++++++++++++ 1 file changed, 211 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/ti/ti,am62l-dmss-= bcdma.yaml diff --git a/Documentation/devicetree/bindings/dma/ti/ti,am62l-dmss-bcdma.y= aml b/Documentation/devicetree/bindings/dma/ti/ti,am62l-dmss-bcdma.yaml new file mode 100644 index 0000000000000..76184485ebcba --- /dev/null +++ b/Documentation/devicetree/bindings/dma/ti/ti,am62l-dmss-bcdma.yaml @@ -0,0 +1,211 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2026 Texas Instruments Incorporated +# Author: Sai Sree Kartheek Adivi +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/ti/ti,am62l-dmss-bcdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments K3 DMSS BCDMA V2 + +maintainers: + - Sai Sree Kartheek Adivi + +description: + The BCDMA V2 is intended to perform similar functions as the TR + mode channels of K3 UDMA-P. + BCDMA V2 includes block copy channels and Split channels. + + Block copy channels mainly used for memory to memory transfers, but with + optional triggers a block copy channel can service peripherals by access= ing + directly to memory mapped registers or area. + + Split channels can be used to service PSI-L based peripherals. + The peripherals can be PSI-L native or legacy, non PSI-L native peripher= als + with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric a= nd the + legacy peripheral. + +allOf: + - $ref: /schemas/dma/dma-controller.yaml# + +properties: + compatible: + const: ti,am62l-dmss-bcdma + + reg: + items: + - description: BCDMA Control & Status Registers region + - description: Block Copy Channel Realtime Registers region + - description: Channel Realtime Registers region + - description: Ring Realtime Registers region + + reg-names: + items: + - const: gcfg + - const: bchanrt + - const: chanrt + - const: ringrt + + "#dma-cells": + const: 4 + description: | + cell 1: Trigger type for the channel + 0 - disable / no trigger + 1 - internal channel event + 2 - external signal + 3 - timer manager event + + cell 2: parameter for the trigger: + if cell 1 is 0 (disable / no trigger): + Unused, ignored + if cell 1 is 1 (internal channel event): + channel number whose TR event should trigger the current channel. + if cell 1 is 2 or 3 (external signal or timer manager event): + index of global interfaces that come into the DMA. + + Please refer to the device documentation for global interface in= dexes. + + cell 3: Channel ID for the peripheral + This is the mapped_channel_id assigned to the peripheral in the PS= I-L + endpoint map. For XYMF peripherals (SPI, CRC32) each chip-select/F= IFO + has a distinct channel ID; use the channel ID for the specific + direction and chip-select being requested. Use 0 for triggered + block-copy channels (cell 1 !=3D 0). + + Please refer to the device documentation for the channel map. + + cell 4: ASEL value for the channel + + interrupts: + maxItems: 75 + description: + Interrupts for DMA channels. + + interrupt-names: + minItems: 75 + maxItems: 75 + items: + pattern: "^chan([0-9]|1[0-3]|1[6-9]|2[0-9]|3[0-9]|4[0-7]|4[89]|5[0-3= ]|6[4-8]|8[01]|12[89]|13[0-9]|14[0-3])$" + description: + The name of the interrupt corresponding to the DMA channel. + +required: + - compatible + - reg + - reg-names + - "#dma-cells" + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + dma-controller@485c4000 { + compatible =3D "ti,am62l-dmss-bcdma"; + reg =3D <0x485c4000 0x4000>, + <0x48880000 0x10000>, + <0x48800000 0x80000>, + <0x47000000 0x200000>; + reg-names =3D "gcfg", "bchanrt", "chanrt", "ringrt"; + + #dma-cells =3D <4>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "chan0", "chan1", "chan2", "chan3", "chan4", + "chan5", "chan6", "chan7", "chan8", "chan9", + "chan10", "chan11", "chan12", "chan13", + "chan16", "chan17", "chan18", "chan19", + "chan20", "chan21", "chan22", "chan23", + "chan24", "chan25", "chan26", "chan27", + "chan28", "chan29", "chan30", "chan31", + "chan32", "chan33", "chan34", "chan35", + "chan36", "chan37", "chan38", "chan39", + "chan40", "chan41", "chan42", "chan43", + "chan44", "chan45", "chan46", "chan47", + "chan48", "chan49", "chan50", "chan51", + "chan52", "chan53", "chan64", "chan65", + "chan66", "chan80", "chan81", "chan67", + "chan68", "chan128", "chan129", "chan130", + "chan131", "chan132", "chan133", "chan134", + "chan135", "chan136", "chan137", "chan138", + "chan139", "chan140", "chan141", "chan142", + "chan143"; + }; --=20 2.54.0 From nobody Tue Sep 29 08:26:17 2026 Received: from mx0b-0002e601.pphosted.com (mx0b-0002e601.pphosted.com [148.163.154.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F9DC370D69; Mon, 28 Sep 2026 02:59:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.154.28 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564385; cv=fail; b=mQjOj3Q9utBelk40ge+MZHBmwMBnffd/VtmRPfvvybwLylVusZ3P8EBkwZ2fV4PMumzSr0d9nypu606O2i6huj81O3m5+6hjXLfSOCGzhJCVY1XMGDDsvjhgltLAnINuBIScOoUWEe9dc0nCrI8r7JQYSZJZapV66sGHPu/z+Y8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564385; c=relaxed/simple; bh=hfx9tyedLuwQpWQzmyhpCVk7zXwPKahSmmir+wIDops=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TL/qR57wX9GykVtijkL0H5VmaLkz9AVU31iZR7VUtcOfXAKMUkQU6g8mcexL45c3EVeGH+A9jtPAmSVmUHHvTqyhpy69/BQRLSRx6lSeynHzDK9Kn4669RBzqqGQjM7D7rOV13HDFuhltvLkQKZYZ2lR0dFrIBqirsQThxxQPF4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=KGtxZYJt; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=B4i+WxJ9; arc=fail smtp.client-ip=148.163.154.28 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="KGtxZYJt"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="B4i+WxJ9" Received: from pps.filterd (m0374955.ppops.net [127.0.0.1]) by mx0b-0002e601.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68RLD7Jp2806166; Sun, 27 Sep 2026 21:59:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=oWMlIJVgWFG1s20YaWxHB9JpHlwzpEvZrR2JSB+RB zE=; b=KGtxZYJtRYZ2Uf/+tDys44HcSq5gk2A2dGsGtvvX6e2Jj3naBqcAM82LP 8kdSo0DNalROxjxvGD55Ka/MXanYGS65kPE8pr+cccNbhGIuCUvi0Ug4gjNRCfO2 MDcuoBCrK4AltXrINikB4xvl1j+IHX8qIyuk84iHb8AW5t1c/9FFQyAVwcC/6Zgh mas+iCSzY2BINKDy2V5SNEK8/PB85f88BW1uDrxnPoqx53ETVdXJYEUZ/NefMRmW CLrREs/dFp8QUcM0Z65Hm7nCHu0Fo2jJzrKHRBURu+WbTbjz2J8od5lL/sR8RvrT 4ZECKQNScoSfozWsgiuUnLAWYQzzw== Received: from ch1pr05cu001.outbound.protection.outlook.com (mail-northcentralusazon11010023.outbound.protection.outlook.com [52.101.193.23]) by mx0b-0002e601.pphosted.com (PPS) with ESMTPS id 4gxwe5kfsu-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Sun, 27 Sep 2026 21:59:34 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=r1+CpSwg1+4m89Zc6N8of4mJxV3FNfRaAE94n7yjpj8NQ2lieeDcK/IFafJJpt0sjaPcLNZ8v9163tXjcXPvPr+/tQqWo4d/AwrKav2h9lJDocsOkeGGDnbtAaAOApg5809bG7+Kdd8jpsGMTrgKRzhNVoqbJ/m764uRnp28carIFjwPqQPi5XxCxFAmHxyoBvB6tk9HRj1wmtP8SSfnATOTCssiV63uODNj84ZGMv6+hTSTzrv/lYc8QvtIcLFT/J90qdEeithgvoyKLB575zw8VtP7zu5BwgXgrC23CUMGEAkh4MKvfnFAc6VrCQfmw5g0lG9pniIRtzOGaeidCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=oWMlIJVgWFG1s20YaWxHB9JpHlwzpEvZrR2JSB+RBzE=; b=hG2FLPh1XGEu5L/KlnetlPUuFkqKxRVul8hX5OnnydhfdiTkBjFjLR32uXEaPFQlFkdS3cylyB467wNdRxu+YAO6VBDx14CT6tBAfVPSES4jphjGcmZQQ6LK8h5CWKWzg1vSnOGa1qLNGHbArn2f8EP/qpydAOmA8lAkihxbtRTIgugxvhFDSV0OuDwp8r827DJ2Dgn/2O4GAPnJqd0FX8xN7XxURFR+T9RNqOCxNyLaTA9M27NliiI6Pk18ZfrgalDYbd1Lgni8rKY9dzwMM6d67KfOVBZ/Nq8+r8AI662k1Smf5JlyJlX+bF7CZCBkYWFcjhRug2dBWNnm1lD8Sw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.23.195) smtp.rcpttodomain=nxp.com smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=oWMlIJVgWFG1s20YaWxHB9JpHlwzpEvZrR2JSB+RBzE=; b=B4i+WxJ9FcqHd0iaX7cC5TQr77PmZegwvpgnzb+acRK+M9ud4elHUqvF34YXU7cOjAtbuOa+LMQOkhcCz6tZ2BoX1gu95LYnBYBnC3Y4JK/g3Sw5FLKrnb8lnoSGbdV5vWDGxOQSIuG46ZqcE8epD1K2MN/izqzZH5QfH3+kIeI= Received: from SJ0PR05CA0177.namprd05.prod.outlook.com (2603:10b6:a03:339::32) by CH3PR10MB6904.namprd10.prod.outlook.com (2603:10b6:610:145::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.451.19; Mon, 28 Sep 2026 02:59:31 +0000 Received: from SJ5PEPF000001ED.namprd05.prod.outlook.com (2603:10b6:a03:339:cafe::60) by SJ0PR05CA0177.outlook.office365.com (2603:10b6:a03:339::32) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.428.6 via Frontend Transport; Mon, 28 Sep 2026 02:59:30 +0000 X-MS-Exchange-Authentication-Results: mx.microsoft.com 1; spf=pass (sender IP is 198.47.23.195) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.23.195 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.23.195; helo=lewvzet201.ext.ti.com; pr=C Received: from lewvzet201.ext.ti.com (198.47.23.195) by SJ5PEPF000001ED.mail.protection.outlook.com (10.167.242.201) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Mon, 28 Sep 2026 02:59:30 +0000 Received: from DLEE200.ent.ti.com (157.170.170.75) by lewvzet201.ext.ti.com (10.4.14.104) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:59:04 -0500 Received: from DLEE207.ent.ti.com (157.170.170.95) by DLEE200.ent.ti.com (157.170.170.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:59:04 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE207.ent.ti.com (157.170.170.95) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45 via Frontend Transport; Sun, 27 Sep 2026 21:59:04 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [10.24.51.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 68S2vqqL2256662; Sun, 27 Sep 2026 21:58:59 -0500 From: Sai Sree Kartheek Adivi To: , , , , , , , , , , , , , CC: , Subject: [PATCH v10 14/19] dt-bindings: dma: ti: Add K3 PKTDMA V2 Date: Mon, 28 Sep 2026 08:26:20 +0530 Message-ID: <20260928025749.1055383-15-s-adivi@ti.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260928025749.1055383-1-s-adivi@ti.com> References: <20260928025749.1055383-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001ED:EE_|CH3PR10MB6904:EE_ X-MS-Office365-Filtering-Correlation-Id: eec7329d-45d8-4192-0b25-08df1d0c8478 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|23010399003|36860700016|1800799024|82310400026|921020|56012099006|10067099003|22082099003|18002099003|6133799003|3023799007|13003099007; X-Microsoft-Antispam-Message-Info: tu9PSKftq3kXxvnMSSGnk1h2d0eqlgOnD8lsODGbPgo7asVzy3rWZTiEriuwbDEWqYZGywkz3usAG++t0SUNE8yNe70EkcvLIWctjR3rIaCjmz2Su4hmTRKEfurRJWR+c2hTwbPce9ROCVn+X9Vnyvo/cgHaT6QQGia+a6Q/SHn4aNSNQ9n4opyR8gx10wFBy+89Y8yx3fdOvTWBmPhD5rZFgTe1wHMen8/JyQmgwWjMvjcMnr1s0Tn8d+0PGcRvqdcnUfYVNkX3q3g/3NZkn9Vie7sx6AZMH7gUM4jo5PEMD93to2/pafs73QBzgIvyrjquP/WBKNQivyNV6VV9rqHzUQ/nxRVDOVHyzzE0c+fckAvzE4JtpVwdhYJ4p9rXKtGpUs/T3mQtXQAfZs3IpIPaq7bHOSIlrDk3k+XZwugU3uQfJr0XRGpiElniyOrZax2EC9LK9OnGnl+DDbq2TpWOGVKoM8nKTPT1b1NteTKQvinyHINeQqbHavlKHpiHcM/lH8R4P3DmExz9GQxTjyqi3zU8nVEa4rkGCYNZRvdj4Zw8YaexA36JKo/ucfNor59i6hADjhxvJsuDANbGTYWBLx1b0qRplydaG5L5V3rALhlY2gLZhUabfDVR61vM1eAoOheFToCWG2+H90n3LI50z+TIdtb5AdkpkfYLER8VoKp8Dx46fsDjjnri9ewA X-Forefront-Antispam-Report: CIP:198.47.23.195;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:lewvzet201.ext.ti.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(376014)(23010399003)(36860700016)(1800799024)(82310400026)(921020)(56012099006)(10067099003)(22082099003)(18002099003)(6133799003)(3023799007)(13003099007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2LuWXxWyaTgy9DPGyAlU+dOpD3l1b+gG8WI21p4eiX2AbkV0mj+R1klqlqgBYtKetbwTBqYHKEquAgePKt7TCXZ7JoRsLkgLcl7mECqhBGYtqJUVEEnlYSFfJXzll+cEsLCvr4i2c2KeRK6OUgWS2FCVSqQnlnU7ZPtSQCSaayp7iqeAp/IYxM7a5gGc4Xbe7PFF+WcLLDVuADs74YIvnN8NeOoNrDpCU+1LH8er4K1MVoYbo7MW1P/kbYqvlDyWlY8JHle9nm4oY1S0tzvUca6q89QYX1olH4Acc0lmn12D5SswYVfSLEQ6ttY77I53RUd0QfrAVFQ4Gzl0TWJjcvxq3OTo6OVnTgfsbcXEpUBD0Re0zfznMjShVv59YinDzmcsjiqXtrNWVdkiWEeF77P5m2BQH5hn9QZ3iUMIcD7iDDxH9iiU8T0df0n1xGWG X-Exchange-RoutingPolicyChecked: gdpjHaIhhCEboYfGV6+HyQXIH8dm48vIWA4bhkV4SQiMlnYRERVuvh1NXKJr978UcsfLjzLCseU6rIogjeB5wqJhUFkgL/n1Tljh2kZ2shtXEECq4fPCvDQ7mBNc7AyIHHNrwlWZ902Gtw9HOF6ZyOkcmJoV8dg0TbAGXmf0Y8DWI7sF/1GyHRPpQMHZUOxAJ8s1mVXiQPk7DgVsRtX3owBCnXBOQcXGOzC7O3V0pTB5r4o17lCHJqyOIaM3244wrvogyvFm6FoSceziQPbALXQHgMNU0IENEf1XXbtNSC/R+n51d4EgREgZHKljftHdhPGMJhMnzglEbu37vV7vnA== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 02:59:30.7932 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eec7329d-45d8-4192-0b25-08df1d0c8478 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001ED.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR10MB6904 X-Authority-Analysis: v=2.4 cv=aeP0Dhot c=1 sm=1 tr=0 ts=6ab9d816 cx=c_pps a=ubRrNrA1i3DLWGMHTGxaeQ==:117 a=f+v6EHfkeJbVwR46tk4DMg==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=VdqzKS8jKosA:10 a=s63m1ICgrNkA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=fPAWb5peG099m5CrUpKH:22 a=gEfo2CItAAAA:8 a=sozttTNsAAAA:8 a=3biYmkHrlXwTjyWc3LcA:9 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfXy5GxwZqVSQ3l KMEWCRPQNRMJN/GDsvhcdLTvD26Ei1VxeLtU/3EUjwl0IdyZ1PPuDsv369H5y4HA/sjsrTkTLY3 lN6z9yIq8TVx95lje4/hZUJxS7geuiw+Rovf73d3xel+V3WQOJwHhMgMOduruZpW2gcElsdOkfe yro2Lp+vqNXJLTdT/Q4mqk9k4GThUSgDq50adxuAiS5Tm371hq7gI8sWX3Mi8lL0XMCT9/dOqa6 +XGukTt8j8H7Id8hfyv0xloLxS9GTMor4O1BdnAeocUaSHZStP0qm7MSbKUU+SwELyPyWPPJWgf sbp7CDvtZra0nv4/T3Uo7XMaQGD9iaWKuDX4CqszV5xA/BJpCAsITEgJumaIkJFG8DcookO39x8 cDSatiK8G7TEvMRERIWtXdstDr31Drwzinj0QkgXzZYjBpmv8EHJ+lBw06udasUKIfw3mw9H1TW 3ghxgmvLWnjB/cg5X/g== X-Proofpoint-ORIG-GUID: 2KA_KFw-dH2PQRDREmI2Lk2tBK7Zt49r X-Proofpoint-GUID: 2KA_KFw-dH2PQRDREmI2Lk2tBK7Zt49r X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX6IMvoH+dO9PR XaFU1QsLw2EIgGdUoZZv3Q+Xnrrm3CVXYdKVVDtM4grgshfNyPW5GapoPxbM65imoZkl3wxDCKY 5FeEhqzGBMx4PXJ2GIUp1NGkTTPrYpY= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 phishscore=0 spamscore=0 clxscore=1015 adultscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280011 Content-Type: text/plain; charset="utf-8" New binding document for Texas Instruments K3 Packet DMA (PKTDMA) V2. PKTDMA V2 is introduced as part of AM62L. Signed-off-by: Sai Sree Kartheek Adivi --- .../bindings/dma/ti/ti,am62l-dmss-pktdma.yaml | 189 ++++++++++++++++++ 1 file changed, 189 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/ti/ti,am62l-dmss-= pktdma.yaml diff --git a/Documentation/devicetree/bindings/dma/ti/ti,am62l-dmss-pktdma.= yaml b/Documentation/devicetree/bindings/dma/ti/ti,am62l-dmss-pktdma.yaml new file mode 100644 index 0000000000000..caeacd4cf5ab3 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/ti/ti,am62l-dmss-pktdma.yaml @@ -0,0 +1,189 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2026 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/ti/ti,am62l-dmss-pktdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments K3 DMSS PKTDMA V2 + +maintainers: + - Sai Sree Kartheek Adivi + +description: + The PKTDMA V2 is intended to perform similar functions as the packet mode + channels of K3 UDMA-P. PKTDMA V2 only includes Split channels to service + PSI-L based peripherals. + + The peripherals can be PSI-L native or legacy, non PSI-L native peripher= als + with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric a= nd the + legacy peripheral. + +allOf: + - $ref: /schemas/dma/dma-controller.yaml# + +properties: + compatible: + const: ti,am62l-dmss-pktdma + + reg: + items: + - description: Packet DMA Control & Status + - description: Channel Realtime + - description: Ring Realtime + + reg-names: + items: + - const: gcfg + - const: chanrt + - const: ringrt + + "#dma-cells": + const: 2 + description: | + cell 1: Flow ID for the peripheral + This is the hardware flow index assigned to the peripheral. TX and= RX + flow indices are mixed across the valid range. For XYMF peripherals + (SPI, CRC32) each chip-select/FIFO has a distinct flow ID; use the + flow ID for the specific direction and chip-select being requested. + + Please refer to the device documentation for the flow map. + + cell 2: ASEL value for the channel + + interrupts: + maxItems: 78 + description: + Interrupts for DMA channels. + + interrupt-names: + minItems: 78 + maxItems: 78 + items: + pattern: "^(t|r)x-([0-9]|1[0-3]|1[6-9]|2[0-9]|3[0-9]|4[0-7]|6[4-9]|7= [0-9]|9[6-9]|10[0-9]|11[01])$" + description: + The name of the interrupt corresponding to the DMA flow. + TX flows use the "tx-" prefix, RX flows use the "rx-" prefix. + +required: + - compatible + - reg + - reg-names + - "#dma-cells" + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + dma-controller@485c0000 { + compatible =3D "ti,am62l-dmss-pktdma"; + reg =3D <0x485c0000 0x4000>, + <0x48900000 0x80000>, + <0x47200000 0x100000>; + reg-names =3D "gcfg", "chanrt", "ringrt"; + + #dma-cells =3D <2>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "rx-0", "tx-1", "rx-2", "tx-3", "rx-4", + "tx-5", "rx-6", "tx-7", "rx-8", "tx-9", + "rx-10", "tx-11", "rx-12", "tx-13", + "rx-16", "tx-17", "rx-18", "tx-19", + "rx-20", "tx-21", "rx-22", "tx-23", + "rx-24", "tx-25", "rx-26", "tx-27", + "rx-28", "tx-29", "rx-30", "tx-31", + "rx-32", "tx-33", "rx-34", "tx-35", + "rx-36", "tx-37", "rx-38", "tx-39", + "rx-40", "tx-41", "rx-42", "tx-43", + "rx-44", "tx-45", "rx-46", "tx-47", + "tx-64", "tx-65", "tx-66", "tx-67", + "tx-68", "tx-69", "tx-70", "tx-71", + "tx-72", "tx-73", "tx-74", "tx-75", + "tx-76", "tx-77", "tx-78", "tx-79", + "rx-96", "rx-97", "rx-98", "rx-99", + "rx-100", "rx-101", "rx-102", "rx-103", + "rx-104", "rx-105", "rx-106", "rx-107", + "rx-108", "rx-109", "rx-110", "rx-111"; + }; --=20 2.54.0 From nobody Tue Sep 29 08:26:17 2026 Received: from mx0a-0002e601.pphosted.com (mx0a-0002e601.pphosted.com [148.163.150.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82C57376A1A; Mon, 28 Sep 2026 03:00:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.150.75 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564416; cv=fail; b=WLfbUC65XotlSNHdvQ6qDLF12wXfv7NOK1mry3qe3cNQ9yFv7Of299pbj12yezg0Jec/vf13ub0ZCzx9puBOras6KYp8XiJGDC0rYbGLEJhGF30vGq22myaJ8ZeDGhpBzcw4dngx5aTDcZFb7+RAKrTY7xu1TKOXo4NQmcmwJzg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564416; c=relaxed/simple; bh=qdzGF/AkqzMS/VsskoF1Vr7DlzwubPVXThq/KcVW6Xw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Rv04AZBpMVsTHP5q2LvX0QNNiG0JiRVSXgCIWDBEPFRMB/6Z85wGYY5HWr6wb9a5gMrXDZLn0eLh18sKcqqizymrfeFJZUWK84CY/JAzfrEdzSR9lcGhpV6t3NF+nJ9f4MVUwp/VvX787weLw+UNZ9rpXr9O59Kmc5Dl8kHCOJA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=gr8sbtmB; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=dm3Wtz8h; arc=fail smtp.client-ip=148.163.150.75 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="gr8sbtmB"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="dm3Wtz8h" Received: from pps.filterd (m0384305.ppops.net [127.0.0.1]) by m0384305.ppops.net (8.18.1.11/8.18.1.11) with ESMTP id 68S0RoKt3706315; Sun, 27 Sep 2026 22:00:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=jV6566MJCH+9XTWopmZWS4gz9dkHmEXUB8EyqFBzq eA=; b=gr8sbtmBc4+WtL72r4gbNUaXRdDG945aQev3mjcTU6A2Juog8Kpi4+dBk EFxyyJKRcJTh7etSf7EjE1PS0j6bynQAItvj8V0EsGV2dgK4GNyuBHjey5lZiq1h GYOGuCRD0Zpi5gchYdrkzbgiar9wqjZSd0zjGXP8GVCtCNapILWjh23Q/HsFN1Hr Ld63NyeSnesRS75vcDis3eCewyoXebMxGWfyiO7Vfbu2jodrhTxq8s316mkxCKfV xRNJNNevhb74DnjlrZIpZJvfH3lcIx1CKdRpjc+2zp9ZXhi5uRgljPd12hGI9fjz hcUtkoVa3WrjywLrPrtKfKx+KvKIQ== Received: from byapr05cu005.outbound.protection.outlook.com (mail-westusazon11010047.outbound.protection.outlook.com [52.101.85.47]) by m0384305.ppops.net (PPS) with ESMTPS id 4gy00nb1ug-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Sun, 27 Sep 2026 22:00:03 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=lioiTfQ773D8Ky9k9xX71NVYs0ksHz1zj/G0bAW1djv9df/Rk3y/GbKCE0+clA73U+ARzrdHX9btNCFjOqzSx8+1Sp8SQm7GtN1EylbRDK0t1MVzPjzk6iQyxzuQsMPv2I8YXznr/qLYBs7vzwCA5FghHJ1UWsegjWiVt1Af2AgLQU66CUdt3QEpVAJ5gOqf7iTVoAkNef/6+9k5JiPAQMcO14xfv836+vVcbndgbIiYif6BbU8ccO5eOj+fBS1YeBg+Dz9yN9o7pgBelgFk8TpdEwltxeveb8A7DwxOsKuOmAZ4e8EGQvUrw68v+c34M9M5G6xbwwtQWLm7NE12rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=jV6566MJCH+9XTWopmZWS4gz9dkHmEXUB8EyqFBzqeA=; b=nDUT77uT8B5uUAQDDJuiujzzeh79urjraSCyRZ/bV5imOTbHQSHnn8A7w9Yc1mXh8UC6z4bHMghm6PEO0NoC8U/FUG178IuYXgrP1+USs1RCSk1QEPJX3U8H0l1OYg1JK576UOLgk11JIsrFM6wf8uQIn1mWr4C31VyWmko15dZricHYv/+Ixzk9IbMVhjtp1Py6svVI1KlY0csw4Wk2VuN3SaVdZEnhgVsV5pH4oYJkH5S57seOsEsuUMdFn+oradIp5fNIz16Y4WZJDMsCOW5zAFBrbszjS6BN1HZZ9z/QNtNv1kfWxU+KPfHXNiI28HSoV1IUTc+jyagxurcbtw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.21.195) smtp.rcpttodomain=nxp.com smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jV6566MJCH+9XTWopmZWS4gz9dkHmEXUB8EyqFBzqeA=; b=dm3Wtz8hjsZC1FVDzev5tpX1wpHVB5MR6zcnAY0vpm+fGfNbCHUzvAt4NiiviNzR5aqmIgsPZVFvgBknAlzyUye+D7k0PxyWRTGOFeH+CrxfEiCg2ZyI9xWTjKpAtT/WDZRwCLhEEp9DMEDbep3je8/tF7nYrjLwQ8bNzwJ+rJY= Received: from PH7PR03CA0030.namprd03.prod.outlook.com (2603:10b6:510:339::35) by DM4PR10MB6839.namprd10.prod.outlook.com (2603:10b6:8:105::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.7; Mon, 28 Sep 2026 02:59:56 +0000 Received: from SJ1PEPF000023CC.namprd02.prod.outlook.com (2603:10b6:510:339:cafe::83) by PH7PR03CA0030.outlook.office365.com (2603:10b6:510:339::35) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.451.23 via Frontend Transport; Mon, 28 Sep 2026 02:59:56 +0000 X-MS-Exchange-Authentication-Results: mx.microsoft.com 1; spf=pass (sender IP is 198.47.21.195) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.21.195 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.21.195; helo=flwvzet201.ext.ti.com; pr=C Received: from flwvzet201.ext.ti.com (198.47.21.195) by SJ1PEPF000023CC.mail.protection.outlook.com (10.167.244.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Mon, 28 Sep 2026 02:59:54 +0000 Received: from DFLE209.ent.ti.com (10.64.6.67) by flwvzet201.ext.ti.com (10.248.192.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:59:09 -0500 Received: from DFLE209.ent.ti.com (10.64.6.67) by DFLE209.ent.ti.com (10.64.6.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:59:09 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE209.ent.ti.com (10.64.6.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45 via Frontend Transport; Sun, 27 Sep 2026 21:59:09 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [10.24.51.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 68S2vqqM2256662; Sun, 27 Sep 2026 21:59:04 -0500 From: Sai Sree Kartheek Adivi To: , , , , , , , , , , , , , CC: , Subject: [PATCH v10 15/19] dmaengine: ti: k3-psil-am62l: Add AM62Lx PSIL and PDMA data Date: Mon, 28 Sep 2026 08:26:21 +0530 Message-ID: <20260928025749.1055383-16-s-adivi@ti.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260928025749.1055383-1-s-adivi@ti.com> References: <20260928025749.1055383-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CC:EE_|DM4PR10MB6839:EE_ X-MS-Office365-Filtering-Correlation-Id: 5bfb430c-9e2c-4d74-3c3b-08df1d0c9283 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|23010399003|7416014|376014|1800799024|82310400026|921020|56012099006|10067099003|18002099003|22082099003|13003099007|3023799007; X-Microsoft-Antispam-Message-Info: lUfj+6a76ofO5OyDOC+wmOzVMnMFWkFR5OCdb3XNVCT0CPlhNSPgFk4sqVnfixbXZYDGERML8gk2FOzG9epj74sSfh7yPkIAY1GvjJrshxQF0OlvQsI3jWDPbiAAQtHFrTv5kA1GUaR8Q0GevWxJLQKWWP2xfAHIFuC+KlbGl4L5PElFZE3NDIbOdk131isV2qOGbLu0VHkO8hyUewfsAL+IraE1S12hV4s9/fUw9HTqBWSSBZ0zHvkvANBWtm0jPxaIE5J+GW+hhPHgXwof4RpPQx2Uabl53ELJYchPosjCcmxhMXF0nri7OdauzKaKsTqXsYnh638MTQVvnNzBFN9KOZ+D7Gl8bwXAf9uZo4v86R/T57QjzZ2TKe+28sL20oMuytyi8xtgFdV7C+/ttsXJvkno4EMuitNHbEqg6KHz/wdJMIblCZg/KVLVkr60+CWW5w1cZM4nN8cUj1Z0WE4TbndASv5Kyf00LrIC+sawJUFEspkUAuBpp3hzJUa4RjEeCHrtRECq1kYpWvLCqmAQawgN958wRtROjTJ3s4xbvhmSOrNXdFEZM7vr5JlcRguZ1wqHYlwEX/4cyA4+Cwbbi53oWv2iayX3R2gCvtW3s1ATgNOCIW9b/0jc5jnevAuSqX4SIsYJfhNKmUMeOHxcUa++O6lR1CdRpiEQ60iCNO+6qxax6sk/6YrdSvug X-Forefront-Antispam-Report: CIP:198.47.21.195;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:flwvzet201.ext.ti.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230040)(36860700016)(23010399003)(7416014)(376014)(1800799024)(82310400026)(921020)(56012099006)(10067099003)(18002099003)(22082099003)(13003099007)(3023799007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: OJV2dzNq+lFWcKA4BTyWuE+/SN/y3UpnlFQfKgqyAQCe8xegcs02SSprnxG8W6OB+RqmLCXmeRIDjVIIkbEBDvERrVQIgKj3joIf4bDdv0YlIgX4YWNFnPSr/Y0As7lGGuwh1QA+4kCrFjpjzcZTdda/wD4tiQTf6RUYXp3LCn+nOxsiHNyTmgAeOwbDcROoJisE45hVDj0pejMXOsIcJcNsHiKhstYn84Nv90zBJjkyne3xf22sta6uR6c3+IJ6FAyWbIjrulkiJet3Dpb6KgsYf6DDMzHYxvxzSo1uBC3kGqcBnbYvL4+RQDaDxuz2Z3c5x4xdDrQsduJ8dqHw9LomsF6QNBEh2GL3Fadto0LyQG6tp732K/P5+ZN9SMCR73EE7GIPflW8tX8mdL3YLNsSI2hfN7kKpyHvuQZaBR3VdRvZbOAnqnS2gaTzn81M X-Exchange-RoutingPolicyChecked: WWQKVujQy8qM4R39Fa+loYy3yIvOnBitqSzzJ63dPJKOBwcazsG4fjBeOzZbtp4Th9X9L32VFnUn0NQN66KJWfTRp1X1Mkqg+VGSe2y2fODDCnSykGiq8dqlyEG++/Ea1QXwZ+xOCzRZA+S0AbqSUMO/cPLGF2jHLZNiPmhuJ+e5bv16GgMdhuiYeEsqrUm7oy3/j3BlmWyTfHYVJ4BZQt/DOIegGfaM9QF2XwfOQwAGM+diufj660/+XYBwswslzZDJp5vHbHmBBCNYWhjE7grbOoF4QA/BZm8znHkYrJZO6pBUNiiV1z4giW5KV1SpyNUtXFPvKNeaszMmwPlLvA== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 02:59:54.3497 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5bfb430c-9e2c-4d74-3c3b-08df1d0c9283 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CC.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR10MB6839 X-Proofpoint-GUID: Fk1Han9cXQZoI4lrRr3hKkGEHlSgRoUd X-Authority-Analysis: v=2.4 cv=fKysTpae c=1 sm=1 tr=0 ts=6ab9d833 cx=c_pps a=UMwgOSM+WKnhBjpqxZ5HKA==:117 a=tJyPKKxUohctrY4NYmUjkA==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=VdqzKS8jKosA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=taLDd7a_hP9WKsMzeGRc:22 a=sozttTNsAAAA:8 a=SxTibnW5tSAW0Is98DsA:9 X-Proofpoint-ORIG-GUID: Fk1Han9cXQZoI4lrRr3hKkGEHlSgRoUd X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX0c7AeCeLnDzI aRZdl/mJ0GW8n07YiI3fFfmHL531Wg0b4bE5hpIejET0VoskcI0I2rrNO5ojRBwB85a4QgZ5Og1 nMk5FeFnR8tMrlOCc5BdvBSN9lgj7BA= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX7mztzNLOvjCi a5k+KLNiRYejsl1+rsLJKALjxzWeYOmoOBIFOSzisMA7kWxfWxSg5eIYYU78pV+l/bojkzLwTiY nmPdx1LQLMyGxN0+S2Rt+2gt0FLh+ZIz9mTRmUR//RPOuyXL11pTjNvuordz5zevHoY8K6c6e4D j3PCnpc3qch6xKGyWideK1Ge9gMGhUbb4GJXMaXeHl4iSr4AcipK9dBmkXf/JrevJlTaBJDsv35 kMu9d62sJ5WoKknR4eKSsxBSsjli8+O31TS0Mz4p95IILru3Ig3uZ936yEYljucmKwuTktR/XQJ FjsA1woe5sLogxIHoSuTkFDGQlHL5nzh2R6v1xVEkzFKWi880XB0pIZwHAlMF3b276xuR07MOKb cIL8o1hfhLoB3SPQ2htO2i9EUG3fOtllysppAVdxgULFHWeXCnJaDSVzrrStmbQKFV4uXAw69vu vB/utAtMUQj7vSaQsHg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 spamscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 adultscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280011 Content-Type: text/plain; charset="utf-8" Add PSIL and PDMA data for AM62Lx SoC. Introduce new PSIL_EP_PDMA_XYMF type for channels that have multiple selectable fifos. Also add a new fifo_id field to psil_endpoint_config to specify the selectable fifo_id. Signed-off-by: Sai Sree Kartheek Adivi Reviewed-by: Vignesh Raghavendra --- drivers/dma/ti/Makefile | 3 +- drivers/dma/ti/k3-psil-am62l.c | 169 +++++++++++++++++++++++++++++++++ drivers/dma/ti/k3-psil-priv.h | 5 + drivers/dma/ti/k3-psil.c | 90 +++++++++++++++++- include/linux/dma/k3-psil.h | 3 + 5 files changed, 265 insertions(+), 5 deletions(-) create mode 100644 drivers/dma/ti/k3-psil-am62l.c diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile index 3b91c02e55eaf..41bfba944dc6c 100644 --- a/drivers/dma/ti/Makefile +++ b/drivers/dma/ti/Makefile @@ -14,6 +14,7 @@ k3-psil-lib-objs :=3D k3-psil.o \ k3-psil-am62.o \ k3-psil-am62a.o \ k3-psil-j784s4.o \ - k3-psil-am62p.o + k3-psil-am62p.o \ + k3-psil-am62l.o obj-$(CONFIG_TI_K3_PSIL) +=3D k3-psil-lib.o obj-$(CONFIG_TI_DMA_CROSSBAR) +=3D dma-crossbar.o diff --git a/drivers/dma/ti/k3-psil-am62l.c b/drivers/dma/ti/k3-psil-am62l.c new file mode 100644 index 0000000000000..ee77fae3787a4 --- /dev/null +++ b/drivers/dma/ti/k3-psil-am62l.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.t= i.com + */ + +#include + +#include "k3-psil-priv.h" + +#define PSIL_PDMA_XY_TR(x, ch) \ + { \ + .thread_id =3D x, \ + .ep_config =3D { \ + .ep_type =3D PSIL_EP_PDMA_XY, \ + .mapped_channel_id =3D ch, \ + .default_flow_id =3D -1, \ + }, \ + } + +#define PSIL_PDMA_XYMF_TR(x, ch, fifo) \ + { \ + .thread_id =3D x, \ + .ep_config =3D { \ + .ep_type =3D PSIL_EP_PDMA_XYMF, \ + .mapped_channel_id =3D ch, \ + .default_flow_id =3D -1, \ + .fifo_id =3D fifo, \ + }, \ + } + +#define PSIL_PDMA_XY_PKT(x, ch) \ + { \ + .thread_id =3D x, \ + .ep_config =3D { \ + .ep_type =3D PSIL_EP_PDMA_XY, \ + .mapped_channel_id =3D ch, \ + .pkt_mode =3D 1, \ + .default_flow_id =3D -1 \ + }, \ + } + +#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \ + { \ + .thread_id =3D x, \ + .ep_config =3D { \ + .ep_type =3D PSIL_EP_NATIVE, \ + .pkt_mode =3D 1, \ + .needs_epib =3D 1, \ + .psd_size =3D 16, \ + .mapped_channel_id =3D ch, \ + .flow_start =3D flow_base, \ + .flow_num =3D flow_cnt, \ + .default_flow_id =3D flow_base, \ + }, \ + } + +#define PSIL_PDMA_MCASP(x, ch) \ + { \ + .thread_id =3D x, \ + .ep_config =3D { \ + .ep_type =3D PSIL_EP_PDMA_XY, \ + .pdma_acc32 =3D 1, \ + .pdma_burst =3D 1, \ + .mapped_channel_id =3D ch, \ + .default_flow_id =3D -1 \ + }, \ + } + +/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ +static struct psil_ep am62l_src_ep_map[] =3D { + /* PDMA_MAIN1 - UART0-6 */ + PSIL_PDMA_XY_PKT(0x4400, 0), + PSIL_PDMA_XY_PKT(0x4401, 2), + PSIL_PDMA_XY_PKT(0x4402, 4), + PSIL_PDMA_XY_PKT(0x4403, 6), + PSIL_PDMA_XY_PKT(0x4404, 8), + PSIL_PDMA_XY_PKT(0x4405, 10), + PSIL_PDMA_XY_PKT(0x4406, 12), + /* PDMA_MAIN0 - SPI0 - CH0-3 */ + PSIL_PDMA_XYMF_TR(0x4300, 16, 0), + PSIL_PDMA_XYMF_TR(0x4300, 18, 1), + PSIL_PDMA_XYMF_TR(0x4300, 20, 2), + PSIL_PDMA_XYMF_TR(0x4300, 22, 3), + /* PDMA_MAIN0 - SPI1 - CH0-3 */ + PSIL_PDMA_XYMF_TR(0x4301, 24, 0), + PSIL_PDMA_XYMF_TR(0x4301, 26, 1), + PSIL_PDMA_XYMF_TR(0x4301, 28, 2), + PSIL_PDMA_XYMF_TR(0x4301, 30, 3), + /* PDMA_MAIN0 - SPI2 - CH0-3 */ + PSIL_PDMA_XYMF_TR(0x4302, 32, 0), + PSIL_PDMA_XYMF_TR(0x4302, 34, 1), + PSIL_PDMA_XYMF_TR(0x4302, 36, 2), + PSIL_PDMA_XYMF_TR(0x4302, 38, 3), + /* PDMA_MAIN0 - SPI3 - CH0-3 */ + PSIL_PDMA_XYMF_TR(0x4303, 40, 0), + PSIL_PDMA_XYMF_TR(0x4303, 42, 1), + PSIL_PDMA_XYMF_TR(0x4303, 44, 2), + PSIL_PDMA_XYMF_TR(0x4303, 46, 3), + /* PDMA_MAIN2 - MCASP0-2 */ + PSIL_PDMA_MCASP(0x4500, 48), + PSIL_PDMA_MCASP(0x4501, 50), + PSIL_PDMA_MCASP(0x4502, 52), + /* PDMA_MAIN0 - AES */ + PSIL_PDMA_XY_TR(0x4700, 65), + /* PDMA_MAIN0 - ADC */ + PSIL_PDMA_XY_TR(0x4503, 80), + PSIL_PDMA_XY_TR(0x4504, 81), + PSIL_ETHERNET(0x4600, 96, 96, 16), +}; + +/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */ +static struct psil_ep am62l_dst_ep_map[] =3D { + /* PDMA_MAIN1 - UART0-6 */ + PSIL_PDMA_XY_PKT(0xC400, 1), + PSIL_PDMA_XY_PKT(0xC401, 3), + PSIL_PDMA_XY_PKT(0xC402, 5), + PSIL_PDMA_XY_PKT(0xC403, 7), + PSIL_PDMA_XY_PKT(0xC404, 9), + PSIL_PDMA_XY_PKT(0xC405, 11), + PSIL_PDMA_XY_PKT(0xC406, 13), + /* PDMA_MAIN0 - SPI0 - CH0-3 */ + PSIL_PDMA_XYMF_TR(0xC300, 17, 0), + PSIL_PDMA_XYMF_TR(0xC300, 19, 1), + PSIL_PDMA_XYMF_TR(0xC300, 21, 2), + PSIL_PDMA_XYMF_TR(0xC300, 23, 3), + /* PDMA_MAIN0 - SPI1 - CH0-3 */ + PSIL_PDMA_XYMF_TR(0xC301, 25, 0), + PSIL_PDMA_XYMF_TR(0xC301, 27, 1), + PSIL_PDMA_XYMF_TR(0xC301, 29, 2), + PSIL_PDMA_XYMF_TR(0xC301, 31, 3), + /* PDMA_MAIN0 - SPI2 - CH0-3 */ + PSIL_PDMA_XYMF_TR(0xC302, 33, 0), + PSIL_PDMA_XYMF_TR(0xC302, 35, 1), + PSIL_PDMA_XYMF_TR(0xC302, 37, 2), + PSIL_PDMA_XYMF_TR(0xC302, 39, 3), + /* PDMA_MAIN0 - SPI3 - CH0-3 */ + PSIL_PDMA_XYMF_TR(0xC303, 41, 0), + PSIL_PDMA_XYMF_TR(0xC303, 43, 1), + PSIL_PDMA_XYMF_TR(0xC303, 45, 2), + PSIL_PDMA_XYMF_TR(0xC303, 47, 3), + /* PDMA_MAIN2 - MCASP0-2 */ + PSIL_PDMA_MCASP(0xC500, 49), + PSIL_PDMA_MCASP(0xC501, 51), + PSIL_PDMA_MCASP(0xC502, 53), + /* PDMA_MAIN0 - SHA */ + PSIL_PDMA_XY_TR(0xC700, 64), + /* PDMA_MAIN0 - AES */ + PSIL_PDMA_XY_TR(0xC701, 66), + /* PDMA_MAIN0 - CRC32 - CH0-1 */ + PSIL_PDMA_XYMF_TR(0xC702, 67, 0), + PSIL_PDMA_XYMF_TR(0xC702, 68, 1), + /* CPSW3G */ + PSIL_ETHERNET(0xc600, 64, 64, 2), + PSIL_ETHERNET(0xc601, 66, 66, 2), + PSIL_ETHERNET(0xc602, 68, 68, 2), + PSIL_ETHERNET(0xc603, 70, 70, 2), + PSIL_ETHERNET(0xc604, 72, 72, 2), + PSIL_ETHERNET(0xc605, 74, 74, 2), + PSIL_ETHERNET(0xc606, 76, 76, 2), + PSIL_ETHERNET(0xc607, 78, 78, 2), +}; + +struct psil_ep_map am62l_ep_map =3D { + .name =3D "am62l", + .src =3D am62l_src_ep_map, + .src_count =3D ARRAY_SIZE(am62l_src_ep_map), + .dst =3D am62l_dst_ep_map, + .dst_count =3D ARRAY_SIZE(am62l_dst_ep_map), +}; diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h index a577be97e3447..970afd46a79e6 100644 --- a/drivers/dma/ti/k3-psil-priv.h +++ b/drivers/dma/ti/k3-psil-priv.h @@ -35,6 +35,10 @@ struct psil_ep_map { }; =20 struct psil_endpoint_config *psil_get_ep_config(u32 thread_id); +struct psil_endpoint_config *psil_get_ep_config_by_id(u32 channel_id, + bool is_pktdma, + u32 *thread_id, + bool *dev_to_mem); =20 /* SoC PSI-L endpoint maps */ extern struct psil_ep_map am654_ep_map; @@ -46,5 +50,6 @@ extern struct psil_ep_map am62_ep_map; extern struct psil_ep_map am62a_ep_map; extern struct psil_ep_map j784s4_ep_map; extern struct psil_ep_map am62p_ep_map; +extern struct psil_ep_map am62l_ep_map; =20 #endif /* K3_PSIL_PRIV_H_ */ diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c index c4b6f0df46861..153ed5fc79e53 100644 --- a/drivers/dma/ti/k3-psil.c +++ b/drivers/dma/ti/k3-psil.c @@ -28,6 +28,7 @@ static const struct soc_device_attribute k3_soc_devices[]= =3D { { .family =3D "J784S4", .data =3D &j784s4_ep_map }, { .family =3D "AM62PX", .data =3D &am62p_ep_map }, { .family =3D "J722S", .data =3D &am62p_ep_map }, + { .family =3D "AM62LX", .data =3D &am62l_ep_map }, { /* sentinel */ } }; =20 @@ -71,12 +72,68 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thr= ead_id) } EXPORT_SYMBOL_GPL(psil_get_ep_config); =20 +struct psil_endpoint_config *psil_get_ep_config_by_id(u32 channel_id, + bool is_pktdma, + u32 *thread_id, + bool *dev_to_mem) +{ + int i; + + mutex_lock(&ep_map_mutex); + if (!soc_ep_map) { + const struct soc_device_attribute *soc; + + soc =3D soc_device_match(k3_soc_devices); + if (soc) { + soc_ep_map =3D soc->data; + } else { + pr_err("PSIL: No compatible machine found for map\n"); + mutex_unlock(&ep_map_mutex); + return ERR_PTR(-ENOTSUPP); + } + } + + if (soc_ep_map->src) { + for (i =3D 0; i < soc_ep_map->src_count; i++) { + struct psil_ep *ep =3D &soc_ep_map->src[i]; + + if (ep->ep_config.mapped_channel_id !=3D (s16)channel_id) + continue; + if ((bool)ep->ep_config.pkt_mode !=3D is_pktdma) + continue; + *thread_id =3D ep->thread_id; + *dev_to_mem =3D true; + mutex_unlock(&ep_map_mutex); + return &ep->ep_config; + } + } + + if (soc_ep_map->dst) { + for (i =3D 0; i < soc_ep_map->dst_count; i++) { + struct psil_ep *ep =3D &soc_ep_map->dst[i]; + + if (ep->ep_config.mapped_channel_id !=3D (s16)channel_id) + continue; + if ((bool)ep->ep_config.pkt_mode !=3D is_pktdma) + continue; + *thread_id =3D ep->thread_id; + *dev_to_mem =3D false; + mutex_unlock(&ep_map_mutex); + return &ep->ep_config; + } + } + + mutex_unlock(&ep_map_mutex); + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL_GPL(psil_get_ep_config_by_id); + int psil_set_new_ep_config(struct device *dev, const char *name, struct psil_endpoint_config *ep_config) { struct psil_endpoint_config *dst_ep_config; - struct of_phandle_args dma_spec; - u32 thread_id; + struct of_phandle_args dma_spec =3D { 0 }; + u32 thread_id =3D 0; int index; =20 if (!dev || !dev->of_node) @@ -90,9 +147,34 @@ int psil_set_new_ep_config(struct device *dev, const ch= ar *name, index, &dma_spec)) return -ENOENT; =20 - thread_id =3D dma_spec.args[0]; + if (of_device_is_compatible(dma_spec.np, "ti,am62l-dmss-pktdma")) { + bool dev_to_mem; + + if (dma_spec.args_count < 1) { + of_node_put(dma_spec.np); + return -EINVAL; + } =20 - dst_ep_config =3D psil_get_ep_config(thread_id); + thread_id =3D dma_spec.args[0]; + dst_ep_config =3D psil_get_ep_config_by_id(dma_spec.args[0], + true, + &thread_id, &dev_to_mem); + } else if (of_device_is_compatible(dma_spec.np, "ti,am62l-dmss-bcdma")) { + bool dev_to_mem; + + if (dma_spec.args_count < 3) { + of_node_put(dma_spec.np); + return -EINVAL; + } + + thread_id =3D dma_spec.args[2]; + dst_ep_config =3D psil_get_ep_config_by_id(dma_spec.args[2], + false, + &thread_id, &dev_to_mem); + } else { + thread_id =3D dma_spec.args[0]; + dst_ep_config =3D psil_get_ep_config(thread_id); + } if (IS_ERR(dst_ep_config)) { pr_err("PSIL: thread ID 0x%04x not defined in map\n", thread_id); diff --git a/include/linux/dma/k3-psil.h b/include/linux/dma/k3-psil.h index 5f106d852f1cf..36e347311f8b2 100644 --- a/include/linux/dma/k3-psil.h +++ b/include/linux/dma/k3-psil.h @@ -35,6 +35,7 @@ enum udma_tp_level { enum psil_endpoint_type { PSIL_EP_NATIVE =3D 0, PSIL_EP_PDMA_XY, + PSIL_EP_PDMA_XYMF, PSIL_EP_PDMA_MCAN, PSIL_EP_PDMA_AASRC, }; @@ -78,6 +79,8 @@ struct psil_endpoint_config { u16 flow_start; u16 flow_num; s16 default_flow_id; + /* XYMF FIFO index (0-3 for CS0-CS3), Only for PSIL_EP_PDMA_XYMF */ + u8 fifo_id; }; =20 int psil_set_new_ep_config(struct device *dev, const char *name, --=20 2.54.0 From nobody Tue Sep 29 08:26:17 2026 Received: from mx0b-0002e601.pphosted.com (mx0b-0002e601.pphosted.com [148.163.154.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCD3E370D5C; Mon, 28 Sep 2026 03:00:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.154.28 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564429; cv=fail; b=lYuAlE3hJAEwLL096CSpDxHSpvcxhee+t/Cwi7asRjWLUecDozkc6EJsWtJHK35m8wHUo+KS+B8LfzDyPjSROpHFJ86JUqZ8bdsX26iVLhoXHgVhackkOUJPM7E3XgiOdDYAbhcOBTnF5XMe23f4jZ5WGxQz4szpF8ymTWJ2PSA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564429; c=relaxed/simple; bh=2Ez7amCjSDTisU2iuf03NSpPNcUYDoDIoafDY1yx+v8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ePoycevG44Gb0Tluk938zwg0OaD/vruKVTNT2WSFP3dIOr7kFGjZeKAKzGd/wwFucRI9HICP/PPigIzcwpJGrl/ztTZVoKEF0axcAQ7yXnaII+p/GzdU1wMhrPGAAEgAN/daAsUG1kDGqZiIcL76E9kgtT8TCaicNdwofJSitfc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=J69U8W2x; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=kntRIzcx; arc=fail smtp.client-ip=148.163.154.28 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="J69U8W2x"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="kntRIzcx" Received: from pps.filterd (m0374956.ppops.net [127.0.0.1]) by mx0b-0002e601.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68RL6HQl2282713; Sun, 27 Sep 2026 22:00:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=VVelekKAo1TJZ90A//x9mk48t/9BIiTrGDLHJyz/K SI=; b=J69U8W2x92EzRl7mUSLEc3C+Wly5cK3a+icq47WkS7Drpj7Ee6e/Yd27R gYtxI9NcnQeUMrnvWNRDOmFR0OTMmn90yNidSZzzQrDcZxQ3D0krGCxGg/CZbi7Z 41iRLpU4o87U4seZRhJCvPDPxqsfySDKOh5jc0T3aSa0z5NJPZnk2ZcbPOp/j1/L x4D7oNeinCm8relMFYWNrsURQWAR/FvMVWXPOSxpZAc/i3Qapw48t0E3Nh5e64gZ /9f/xwqG1d/BUnT3BQtxQ6L1qlQc8pnbPRDmNveLF2z14g1xoZHygY/Dv9Od7EQO oI17+fL5rcbeUmYre3l27S/SdqClg== Received: from mw6pr02cu001.outbound.protection.outlook.com (mail-westus2azon11012045.outbound.protection.outlook.com [52.101.48.45]) by mx0b-0002e601.pphosted.com (PPS) with ESMTPS id 4gxw6nug4k-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Sun, 27 Sep 2026 22:00:10 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=K03IMUnYdN1PCpHuidCMV8VmOVQDTpVf0U+1tiOUCAnWF8J0vB1Q79kdp6iUaFu1rH58rCqq0fyvk0He50Vkb/ftDGERuYye6qgWpMvL1/SyA9B1J6az4HgasDn1F659Dh8qcmSrnVWago/VcSYDxxw4FAyVWP+7bBh3mYUGESTaC+z87UavYyqi5kWF9oDzDoXHWbIfWsA2cqrng1rtEfUP8CKKBP3PtRgKQivgCN8MGj2c/r3S31dpY/+vpIHoBpyiWKJd9KHw3xCLglBHW2DJ1Nvm77cXta4+L9qpqm6YklbkrB0w3+urzzpvjIKOjmfNMFpxzRV0W0qbWHwuUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=VVelekKAo1TJZ90A//x9mk48t/9BIiTrGDLHJyz/KSI=; b=Is7ySX+KZYfGxlQX6ji/zvTDg09ged16YHAoyQGrY44KI4UYjmjMljeL/3LxZIO1knmQcCH1qdvo1IR2y8kRFQK2AhMNmcFF8DGzz/9DRxBJgvSbsho81kUaG81eVP0dOiHXNiWbyAPLVkCkUhHKfiE5rF1KKethpWCbTOEZKSGM05fQl5loX20ZJti293gSfmmJ9mH8TaJaKLy+Iwc0mbkJXhXxSBjOi7IaGsBi2frJeJ3Vbu0nyPl2jtegB2rf+kia0u/wfSGlrDymcnwqD2SeJHPvDYdTBTAVC65fohhS/TvIAe4+gHlpOiHNEaZM15QMi6FoqvFDBGbnQO7Rxg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.21.195) smtp.rcpttodomain=nxp.com smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VVelekKAo1TJZ90A//x9mk48t/9BIiTrGDLHJyz/KSI=; b=kntRIzcxZhBSw1x2kDLhhJL86PA/gKwmzNOCiWPEu559QKEd2flQP/s7w3EIHEQ66pZgQHUPFSK0hfgXPv1LsHih5qKvWnK4bT8aD+P2/xPD7CMef2FIWchP5/eOCyS0KC1QPoPllP2FzkDcEHlw1b+/rZi2yNSKl3BtGbUyNTY= Received: from PH7PR03CA0020.namprd03.prod.outlook.com (2603:10b6:510:339::29) by CH3PR10MB7742.namprd10.prod.outlook.com (2603:10b6:610:1ae::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.7; Mon, 28 Sep 2026 03:00:04 +0000 Received: from SJ1PEPF000023CC.namprd02.prod.outlook.com (2603:10b6:510:339:cafe::75) by PH7PR03CA0020.outlook.office365.com (2603:10b6:510:339::29) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.451.23 via Frontend Transport; Mon, 28 Sep 2026 03:00:03 +0000 X-MS-Exchange-Authentication-Results: mx.microsoft.com 1; spf=pass (sender IP is 198.47.21.195) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.21.195 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.21.195; helo=flwvzet201.ext.ti.com; pr=C Received: from flwvzet201.ext.ti.com (198.47.21.195) by SJ1PEPF000023CC.mail.protection.outlook.com (10.167.244.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Mon, 28 Sep 2026 03:00:01 +0000 Received: from DFLE203.ent.ti.com (10.64.6.61) by flwvzet201.ext.ti.com (10.248.192.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:59:13 -0500 Received: from DFLE206.ent.ti.com (10.64.6.64) by DFLE203.ent.ti.com (10.64.6.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:59:13 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE206.ent.ti.com (10.64.6.64) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45 via Frontend Transport; Sun, 27 Sep 2026 21:59:13 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [10.24.51.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 68S2vqqN2256662; Sun, 27 Sep 2026 21:59:09 -0500 From: Sai Sree Kartheek Adivi To: , , , , , , , , , , , , , CC: , Subject: [PATCH v10 16/19] dmaengine: ti: k3-udma-v2: New driver for K3 BCDMA_V2 Date: Mon, 28 Sep 2026 08:26:22 +0530 Message-ID: <20260928025749.1055383-17-s-adivi@ti.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260928025749.1055383-1-s-adivi@ti.com> References: <20260928025749.1055383-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CC:EE_|CH3PR10MB7742:EE_ X-MS-Office365-Filtering-Correlation-Id: bd6e1173-e05d-4d5e-989a-08df1d0c96d0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|23010399003|7416014|376014|1800799024|10067099003|3023799007|6133799003|22082099003|18002099003|56012099006|13003099007|921020; X-Microsoft-Antispam-Message-Info: ov7jXUaa3talnSwl/GsZGIgJBahJ3IevLJfYf09bU2v0SU7AH/d1fedYHrwA60BcXw4ewrwH6QM2VweuN64+84Ets2QpsFaS1+IVYZa2r82HxkVfBm/0OyC+EYAm2tCb68QpMndyqJtR2IwAtnZvZhebanSeUlGEB3gD0RCdYbVigUDAECP1McYs51i4HlRZyQKWkxKHxP08vbmIHwqkOj54mIHbOKUSmWGFmAAzW2mgGWcGy6P75FXn/6E8nQFqSBK42RkKB0PssEfuelr98ENZGtS4kzMMVZu1lbrNGU+80xd8GwEujhdqEycaxl5tyFycbV9aYpSPAOA7HTfUihSFe6UoUpW9TIyQ7z8EialrrX9JySDnu4diYl3KEzZsiaYnvN85cnwp4pHE/h0oOb7YSZsQ/cYLc8Y3mPXAjQNzxBQWVXtgQ1UrzfqofcBX6SH0y18dk0TXGOMJarcONx29bwO5wL5HbmOiPcUkMNIWONOAxQIwMw7AYHocmsbFuaC6Uoqoo8kyzbo3OyrX4JdtkxObcfJV2JkNpP+bAmJlrmI5zLPT5QnIiRtLgxju+soNeV2yPxAbGH9SyQSspwO9tBrYxYNHedkAR5IXS0yIP+7W5cEpRksk38Chr2Ok2pWgr+2fmX4W5Jjn+QU8xaO1sjj7hDmv6BsIFkefgrOGsm2B/XZTfw3E0zLm979/ X-Forefront-Antispam-Report: CIP:198.47.21.195;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:flwvzet201.ext.ti.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(23010399003)(7416014)(376014)(1800799024)(10067099003)(3023799007)(6133799003)(22082099003)(18002099003)(56012099006)(13003099007)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: xVmtv5ddfzMXbBhUENYUY+CSJ6lmwxSUBZ9m++pLeyTxrmvOzKlP+oOXCQa8BQf5niSDXH76TS3gjj2fs4HjrZzrQ9bihRz7frBZUbIj4O9Xl4el2PEYOWJnb57fB96HEj622z97Fr1VeD4frJG8iAHuVsn3RfQtSNXH7idX1/1ndDZx1oK2A57t1MlRecEHs3p17o3dFTzyR0i/HUQ/3Gja3HyedzLPP/y1Mhxo016nbafSI6RJRZkcjpVY0XSGyAuMRDfdabrjgXmLqLLasqCmkblSPUdhuTmJiCUaXKH4VT4LicJfzjdWEX5Dr3Xn7E/+acGmcv7uXASYBb7E3pLScO19t+f60EktBRT47RJwDGvxRY4Ppqe+Te3KlTZhkjjUtkHd1BQDbBAb0gkSO9JaRYqvedjkSDEz6UNbgfXwZm9OyJww/Dq4VwMWlAdJ X-Exchange-RoutingPolicyChecked: G1q6MKJqD+73UrB88U62KvP/gLqRcG6Jz4CmiHQgNykujVj/SPuZ3Lv0K3jaMEM/AFu78ipyVdZNsEtFinHG/Va/P2c0Q24cxmZgKTdg3KHT3PfRDzenUCUCkf2CVx/ufE2hSwKESoEVKiNmk+Rh1CK2KozlKQVTRvzVVIbHE6ljZgZY4ftx8pLbBObibRm4F/2LrgLMiKb/vXmUBvPRhE11Red5ZubA3DU4hnygNgQulreWKsorIU52SSJdW1eHvBZu45yrdHByH6WrKtKEifMs/Y/eEagZvJIIIQWYYlIvTHA+0zCwSublW4VY9fcSwGQoKK0JRsxYBxkEI9cg0g== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 03:00:01.5623 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bd6e1173-e05d-4d5e-989a-08df1d0c96d0 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CC.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR10MB7742 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX8HN7RseeEloq QoSH2s2QzzKSsPnVQvp5LBzre9kfTDTlMyI17kX21gDiO7kUv77KM9IUDAPx796ncrGgcbAnu5b QfHzNUXAilMfjOo/x5Bree3hp2TdXgA= X-Authority-Analysis: v=2.4 cv=dbkVTnXe c=1 sm=1 tr=0 ts=6ab9d83a cx=c_pps a=klJJBKWT8dzIbr5yswcz1A==:117 a=tJyPKKxUohctrY4NYmUjkA==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=VdqzKS8jKosA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=jwouBfj2j3NM8CExmVVE:22 a=sozttTNsAAAA:8 a=ZcKzTWI0sPZvCTUPIhAA:9 X-Proofpoint-ORIG-GUID: TSpCjeP1go3LniKMm55ULpgpQaHOG3nt X-Proofpoint-GUID: TSpCjeP1go3LniKMm55ULpgpQaHOG3nt X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX1hKvCyq0wNjL /uFd2Ifuepl5LZPxOM8irsO1ZWwOfyXaYZbBbwWcDDEoxTh/8E5ti4KaEFlWu9QbanQFMG0p1VT QBI7gyr+qoquSY0XE8+EeGWrtp1IXUSz1AMpi7DrjMvY0OY5y23Z//oNifwbb7q74eSTkKkAYvR EuRXkb6wF976O2R9j0sYYGAAvehYUdKoG2AfXeuSr+1xslhx1a8xPq83YL+yK3ehbv/+LdTwKRN 8nEG4cA0O7zRgCYGbOF4iZo/hNa4AgAT4Tl6RpAR7DRHJV6TZJO9wkwdpVwhYJyKzErbciGkh0J AvO6C2qR8BuWMR5tnhx19aZPR4zuUUsx7oAtFQJHAcbSvRozvNdnB7oTSZcIo6zrvC950mdEQzL HEivY/z6v62iZA9jlng6oy5DFxDVFGOtfrlUpq1iuTHJWdKZv1GLL60XlTwprid6Dyf6+TBXbFT gigK7KDvNYe+xqo/fFQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 impostorscore=0 adultscore=0 bulkscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280011 Content-Type: text/plain; charset="utf-8" Add support for BCDMA_V2. The BCDMA_V2 is different than the existing BCDMA supported by the k3-udma driver. The changes in BCDMA_V2 are: - Autopair: There is no longer a need for PSIL pair and AUTOPAIR bit needs to set in the RT_CTL register. - Static channel mapping: Each channel is mapped to a single peripheral. - Direct IRQs: There is no INT-A and interrupt lines from DMA are directly connected to GIC. - Remote side configuration handled by DMA. So no need to write to PEER registers to START / STOP / PAUSE / TEARDOWN. - Unified Channel Space: Tx and Rx channels share a single register space. Each channel index is specifically fixed in hardware as either Tx or Rx in an interleaved manner. Also, since a version member is introduced in the match_data, Add version v1 in match_data of SoCs using v1 DMA. Signed-off-by: Sai Sree Kartheek Adivi Reviewed-by: Vignesh Raghavendra --- drivers/dma/ti/Kconfig | 14 +- drivers/dma/ti/Makefile | 1 + drivers/dma/ti/k3-udma-common.c | 94 +- drivers/dma/ti/k3-udma-v2.c | 1327 +++++++++++++++++++++++++++++ drivers/dma/ti/k3-udma.c | 9 + drivers/dma/ti/k3-udma.h | 123 +-- include/linux/soc/ti/k3-ringacc.h | 3 + 7 files changed, 1499 insertions(+), 72 deletions(-) create mode 100644 drivers/dma/ti/k3-udma-v2.c diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig index a389ae04ec930..595fdf3ecbc9d 100644 --- a/drivers/dma/ti/Kconfig +++ b/drivers/dma/ti/Kconfig @@ -49,6 +49,18 @@ config TI_K3_UDMA Enable support for the TI UDMA (Unified DMA) controller. This DMA engine is used in AM65x and j721e. =20 +config TI_K3_UDMA_V2 + tristate "Texas Instruments K3 UDMA v2 support" + depends on ARCH_K3 + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + select TI_K3_UDMA_COMMON + select TI_K3_RINGACC + select TI_K3_PSIL + help + Enable support for the TI UDMA (Unified DMA) v2 controller. This + DMA engine is used in AM62L. + config TI_K3_UDMA_COMMON tristate =20 @@ -62,7 +74,7 @@ config TI_K3_UDMA_GLUE_LAYER =20 config TI_K3_PSIL tristate - default TI_K3_UDMA + default TI_K3_UDMA || TI_K3_UDMA_V2 =20 config TI_DMA_CROSSBAR bool diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile index 41bfba944dc6c..296aa3421e71b 100644 --- a/drivers/dma/ti/Makefile +++ b/drivers/dma/ti/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_TI_CPPI41) +=3D cppi41.o obj-$(CONFIG_TI_EDMA) +=3D edma.o obj-$(CONFIG_DMA_OMAP) +=3D omap-dma.o obj-$(CONFIG_TI_K3_UDMA) +=3D k3-udma.o +obj-$(CONFIG_TI_K3_UDMA_V2) +=3D k3-udma-v2.o obj-$(CONFIG_TI_K3_UDMA_COMMON) +=3D k3-udma-common.o obj-$(CONFIG_TI_K3_UDMA_GLUE_LAYER) +=3D k3-udma-glue.o k3-psil-lib-objs :=3D k3-psil.o \ diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-commo= n.c index eb555cc08347d..30cb8044ff100 100644 --- a/drivers/dma/ti/k3-udma-common.c +++ b/drivers/dma/ti/k3-udma-common.c @@ -171,8 +171,13 @@ bool udma_is_desc_really_done(struct udma_chan *uc, st= ruct udma_desc *d) uc->config.dir !=3D DMA_MEM_TO_DEV || !(uc->config.tx_flags & DMA_PRE= P_INTERRUPT)) return true; =20 - peer_bcnt =3D udma_tchanrt_read(uc, UDMA_CHAN_RT_PEER_BCNT_REG); - bcnt =3D udma_tchanrt_read(uc, UDMA_CHAN_RT_BCNT_REG); + if (uc->ud->match_data->version =3D=3D K3_UDMA_V1) { + peer_bcnt =3D udma_tchanrt_read(uc, UDMA_CHAN_RT_PEER_BCNT_REG); + bcnt =3D udma_tchanrt_read(uc, UDMA_CHAN_RT_BCNT_REG); + } else { + peer_bcnt =3D udma_chanrt_read(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG); + bcnt =3D udma_chanrt_read(uc, UDMA_CHAN_RT_BCNT_REG); + } =20 /* Transfer is incomplete, store current residue and time stamp */ if (peer_bcnt < bcnt) { @@ -319,6 +324,7 @@ udma_prep_slave_sg_tr(struct udma_chan *uc, struct scat= terlist *sgl, size_t tr_size; int num_tr =3D 0; int tr_idx =3D 0; + u32 extra_flags =3D 0; u64 asel; =20 /* estimate the number of TRs we will need */ @@ -342,6 +348,16 @@ udma_prep_slave_sg_tr(struct udma_chan *uc, struct sca= tterlist *sgl, else asel =3D (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; =20 + /* + * BCDMA V2 stalls and stops processing further TRs if a TR's ICNT0 + * is not a multiple of 16 bytes. Setting EOP on every TR (not just + * the last one) avoids that stall condition. Intentional, not a bug. + */ + if (uc->ud->match_data->type =3D=3D DMA_TYPE_BCDMA && + uc->ud->match_data->version =3D=3D K3_UDMA_V2 && + dir =3D=3D DMA_MEM_TO_DEV) + extra_flags =3D CPPI5_TR_CSF_EOP; + tr_req =3D d->hwdesc[0].tr_req_base; for_each_sg(sgl, sgent, sglen, i) { dma_addr_t sg_addr =3D sg_dma_address(sgent); @@ -358,7 +374,7 @@ udma_prep_slave_sg_tr(struct udma_chan *uc, struct scat= terlist *sgl, =20 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false, false, CPPI5_TR_EVENT_SIZE_COMPLETION, 0); - cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT); + cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT | extra_fl= ags); =20 sg_addr |=3D asel; tr_req[tr_idx].addr =3D sg_addr; @@ -372,7 +388,7 @@ udma_prep_slave_sg_tr(struct udma_chan *uc, struct scat= terlist *sgl, false, false, CPPI5_TR_EVENT_SIZE_COMPLETION, 0); cppi5_tr_csf_set(&tr_req[tr_idx].flags, - CPPI5_TR_CSF_SUPR_EVT); + CPPI5_TR_CSF_SUPR_EVT | extra_flags); =20 tr_req[tr_idx].addr =3D sg_addr + tr0_cnt1 * tr0_cnt0; tr_req[tr_idx].icnt0 =3D tr1_cnt0; @@ -593,7 +609,7 @@ int udma_configure_statictr(struct udma_chan *uc, struc= t udma_desc *d, enum dma_slave_buswidth dev_width, u16 elcnt) { - if (uc->config.ep_type !=3D PSIL_EP_PDMA_XY) + if (uc->config.ep_type !=3D PSIL_EP_PDMA_XY && uc->config.ep_type !=3D PS= IL_EP_PDMA_XYMF) return 0; =20 /* Bus width translates to the element size (ES) */ @@ -951,7 +967,8 @@ udma_prep_dma_cyclic_tr(struct udma_chan *uc, dma_addr_= t buf_addr, * As we are in cyclic mode, we do not know which period might be the * last one, so set the flag for each period. */ - if (uc->config.ep_type =3D=3D PSIL_EP_PDMA_XY && + if ((uc->config.ep_type =3D=3D PSIL_EP_PDMA_XY || + uc->config.ep_type =3D=3D PSIL_EP_PDMA_XYMF) && uc->ud->match_data->type =3D=3D DMA_TYPE_BCDMA) { period_csf =3D CPPI5_TR_CSF_EOP; } @@ -2052,6 +2069,8 @@ int udma_get_tchan(struct udma_chan *uc) uc->tchan =3D NULL; return ret; } + if (ud->match_data->version =3D=3D K3_UDMA_V2) + uc->chan =3D uc->tchan; =20 if (ud->tflow_cnt) { int tflow_id; @@ -2102,6 +2121,8 @@ int udma_get_rchan(struct udma_chan *uc) uc->rchan =3D NULL; return ret; } + if (ud->match_data->version =3D=3D K3_UDMA_V2) + uc->chan =3D uc->rchan; =20 return 0; } @@ -2192,6 +2213,7 @@ void udma_put_rchan(struct udma_chan *uc) uc->rchan->id); clear_bit(uc->rchan->id, ud->rchan_map); uc->rchan =3D NULL; + uc->chan =3D NULL; } } EXPORT_SYMBOL_GPL(udma_put_rchan); @@ -2209,6 +2231,7 @@ void udma_put_tchan(struct udma_chan *uc) clear_bit(uc->tchan->tflow_id, ud->tflow_map); =20 uc->tchan =3D NULL; + uc->chan =3D NULL; } } EXPORT_SYMBOL_GPL(udma_put_tchan); @@ -2317,6 +2340,7 @@ void bcdma_put_bchan(struct udma_chan *uc) clear_bit(uc->bchan->id, ud->bchan_map); uc->bchan =3D NULL; uc->tchan =3D NULL; + uc->chan =3D NULL; } } EXPORT_SYMBOL_GPL(bcdma_put_bchan); @@ -2384,9 +2408,16 @@ static int bcdma_setup_resources(struct udma_dev *ud) ud->tchan_map =3D devm_bitmap_zalloc(dev, ud->tchan_cnt, GFP_KERNEL); ud->tchans =3D devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), GFP_KERNEL); - ud->rchan_map =3D devm_bitmap_zalloc(dev, ud->rchan_cnt, GFP_KERNEL); - ud->rchans =3D devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), - GFP_KERNEL); + if (ud->match_data->version =3D=3D K3_UDMA_V1) { + ud->rchan_map =3D devm_bitmap_zalloc(dev, ud->rchan_cnt, GFP_KERNEL); + ud->rchans =3D devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), + GFP_KERNEL); + } else { + ud->rchan_map =3D ud->tchan_map; + ud->rchans =3D ud->tchans; + ud->chan_map =3D ud->tchan_map; + ud->chans =3D ud->tchans; + } /* BCDMA do not really have flows, but the driver expect it */ ud->rflow_in_use =3D devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt), sizeof(unsigned long), @@ -2481,11 +2512,18 @@ int k3_udma_setup_resources(struct udma_dev *ud) if (ret) return ret; =20 - ch_count =3D ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt; - if (ud->bchan_cnt) - ch_count -=3D bitmap_weight(ud->bchan_map, ud->bchan_cnt); - ch_count -=3D bitmap_weight(ud->tchan_map, ud->tchan_cnt); - ch_count -=3D bitmap_weight(ud->rchan_map, ud->rchan_cnt); + if (ud->match_data->version =3D=3D K3_UDMA_V1) { + ch_count =3D ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt; + if (ud->bchan_cnt) + ch_count -=3D bitmap_weight(ud->bchan_map, ud->bchan_cnt); + ch_count -=3D bitmap_weight(ud->tchan_map, ud->tchan_cnt); + ch_count -=3D bitmap_weight(ud->rchan_map, ud->rchan_cnt); + } else { + ch_count =3D ud->bchan_cnt + ud->tchan_cnt; + if (ud->bchan_cnt) + ch_count -=3D bitmap_weight(ud->bchan_map, ud->bchan_cnt); + ch_count -=3D bitmap_weight(ud->tchan_map, ud->tchan_cnt); + } if (!ch_count) return -ENODEV; =20 @@ -2507,15 +2545,25 @@ int k3_udma_setup_resources(struct udma_dev *ud) ud->rflow_cnt)); break; case DMA_TYPE_BCDMA: - dev_info(dev, - "Channels: %d (bchan: %u, tchan: %u, rchan: %u)\n", - ch_count, - ud->bchan_cnt - bitmap_weight(ud->bchan_map, - ud->bchan_cnt), - ud->tchan_cnt - bitmap_weight(ud->tchan_map, - ud->tchan_cnt), - ud->rchan_cnt - bitmap_weight(ud->rchan_map, - ud->rchan_cnt)); + if (ud->match_data->version =3D=3D K3_UDMA_V1) { + dev_info(dev, + "Channels: %d (bchan: %u, tchan: %u, rchan: %u)\n", + ch_count, + ud->bchan_cnt - bitmap_weight(ud->bchan_map, + ud->bchan_cnt), + ud->tchan_cnt - bitmap_weight(ud->tchan_map, + ud->tchan_cnt), + ud->rchan_cnt - bitmap_weight(ud->rchan_map, + ud->rchan_cnt)); + } else { + dev_info(dev, + "Channels: %d (bchan: %u, chan: %u)\n", + ch_count, + ud->bchan_cnt - bitmap_weight(ud->bchan_map, + ud->bchan_cnt), + ud->chan_cnt - bitmap_weight(ud->chan_map, + ud->chan_cnt)); + } break; case DMA_TYPE_PKTDMA: dev_info(dev, diff --git a/drivers/dma/ti/k3-udma-v2.c b/drivers/dma/ti/k3-udma-v2.c new file mode 100644 index 0000000000000..ba3042e866cac --- /dev/null +++ b/drivers/dma/ti/k3-udma-v2.c @@ -0,0 +1,1327 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Derived from K3 UDMA driver (k3-udma.c) + * Copyright (C) 2024-2025 Texas Instruments Incorporated - http://www.ti= .com + * Author: Peter Ujfalusi + * Author: Sai Sree Kartheek Adivi + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../virt-dma.h" +#include "k3-udma.h" +#include "k3-psil-priv.h" + +static const char * const v2_mmr_names[] =3D { + [V2_MMR_GCFG] =3D "gcfg", + [V2_MMR_BCHANRT] =3D "bchanrt", + [V2_MMR_CHANRT] =3D "chanrt", +}; + +static int udma_v2_check_chan_autopair_completion(struct udma_chan *uc) +{ + u32 val; + + val =3D udma_chanrt_read(uc, UDMA_CHAN_RT_CTL_REG); + if (val & UDMA_CHAN_RT_CTL_PAIR_TIMEOUT) + return -ETIMEDOUT; + else if (val & UDMA_CHAN_RT_CTL_PAIR_COMPLETE) + return 1; + + /* timeout didn't occur and also pairing didn't happen yet. */ + return 0; +} + +static bool udma_v2_is_chan_paused(struct udma_chan *uc) +{ + u32 val, pause_mask; + + if (uc->config.dir =3D=3D DMA_MEM_TO_MEM) { + val =3D udma_chanrt_read(uc, UDMA_CHAN_RT_CTL_REG); + pause_mask =3D UDMA_CHAN_RT_CTL_PAUSE; + } else { + val =3D udma_chanrt_read(uc, UDMA_CHAN_RT_PDMA_STATE_REG); + pause_mask =3D UDMA_CHAN_RT_PDMA_STATE_PAUSE; + } + + if (val & pause_mask) + return true; + + return false; +} + +static void udma_v2_decrement_byte_counters(struct udma_chan *uc, u32 val) +{ + udma_chanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val); + udma_chanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val); + if (uc->config.ep_type !=3D PSIL_EP_NATIVE) + udma_chanrt_write(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG, val); +} + +static void udma_v2_reset_counters(struct udma_chan *uc) +{ + u32 val; + + val =3D udma_chanrt_read(uc, UDMA_CHAN_RT_BCNT_REG); + udma_chanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val); + + val =3D udma_chanrt_read(uc, UDMA_CHAN_RT_SBCNT_REG); + udma_chanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val); + + val =3D udma_chanrt_read(uc, UDMA_CHAN_RT_PCNT_REG); + udma_chanrt_write(uc, UDMA_CHAN_RT_PCNT_REG, val); + + if (!uc->bchan) { + val =3D udma_chanrt_read(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG); + udma_chanrt_write(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG, val); + } +} + +static int udma_v2_reset_chan(struct udma_chan *uc, bool hard) +{ + udma_chanrt_write(uc, UDMA_CHAN_RT_CTL_REG, 0); + + /* Reset all counters */ + udma_v2_reset_counters(uc); + + /* Hard reset: re-initialize the channel to reset */ + if (hard) { + struct udma_chan_config ucc_backup; + int ret; + + memcpy(&ucc_backup, &uc->config, sizeof(uc->config)); + uc->ud->ddev.device_free_chan_resources(&uc->vc.chan); + + /* restore the channel configuration */ + memcpy(&uc->config, &ucc_backup, sizeof(uc->config)); + ret =3D uc->ud->ddev.device_alloc_chan_resources(&uc->vc.chan); + if (ret) + return ret; + + /* + * Setting forced teardown after forced reset helps recovering + * the rchan. + */ + if (uc->config.dir =3D=3D DMA_DEV_TO_MEM) + udma_chanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN | + UDMA_CHAN_RT_CTL_FTDOWN, + UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN | + UDMA_CHAN_RT_CTL_FTDOWN); + } + uc->state =3D UDMA_CHAN_IS_IDLE; + + return 0; +} + +static int udma_v2_start(struct udma_chan *uc) +{ + struct virt_dma_desc *vd =3D vchan_next_desc(&uc->vc); + struct udma_dev *ud =3D uc->ud; + int status; + + if (!vd) { + uc->desc =3D NULL; + return -ENOENT; + } + + list_del(&vd->node); + + uc->desc =3D to_udma_desc(&vd->tx); + + /* Channel is already running and does not need reconfiguration */ + if (udma_is_chan_running(uc) && !udma_chan_needs_reconfiguration(uc)) { + udma_start_desc(uc); + goto out; + } + + /* Make sure that we clear the teardown bit, if it is set */ + ud->reset_chan(uc, false); + + /* Push descriptors before we start the channel */ + udma_start_desc(uc); + + switch (uc->config.dir) { + case DMA_DEV_TO_MEM: + /* Config remote TR */ + if (uc->config.ep_type =3D=3D PSIL_EP_PDMA_XY || + uc->config.ep_type =3D=3D PSIL_EP_PDMA_XYMF) { + u32 val =3D PDMA_STATIC_TR_Y(uc->desc->static_tr.elcnt) | + PDMA_STATIC_TR_X(uc->desc->static_tr.elsize); + const struct udma_match_data *match_data =3D + uc->ud->match_data; + + if (uc->config.enable_acc32) + val |=3D PDMA_STATIC_TR_XY_ACC32; + if (uc->config.enable_burst) + val |=3D PDMA_STATIC_TR_XY_BURST; + + udma_chanrt_write(uc, + UDMA_CHAN_RT_STATIC_TR_XY_REG, + val); + + udma_chanrt_write(uc, + UDMA_CHAN_RT_STATIC_TR_Z_REG, + PDMA_STATIC_TR_Z(uc->desc->static_tr.bstcnt, + match_data->statictr_z_mask)); + + /* save the current staticTR configuration */ + memcpy(&uc->static_tr, &uc->desc->static_tr, + sizeof(uc->static_tr)); + } + + if (uc->config.ep_type =3D=3D PSIL_EP_PDMA_XYMF) + udma_chanrt_write(uc, UDMA_CHAN_RT_FIFO_SEL_REG, uc->config.fifo_id); + + udma_chanrt_write(uc, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_AUTOPAIR); + + /* Poll for autopair completion */ + read_poll_timeout_atomic(udma_v2_check_chan_autopair_completion, + status, status !=3D 0, 100, 500, false, uc); + + if (status <=3D 0) { + udma_chanrt_write(uc, UDMA_CHAN_RT_CTL_REG, 0); + return -ETIMEDOUT; + } + + break; + case DMA_MEM_TO_DEV: + /* Config remote TR */ + if (uc->config.ep_type =3D=3D PSIL_EP_PDMA_XY || + uc->config.ep_type =3D=3D PSIL_EP_PDMA_XYMF) { + u32 val =3D PDMA_STATIC_TR_Y(uc->desc->static_tr.elcnt) | + PDMA_STATIC_TR_X(uc->desc->static_tr.elsize); + + if (uc->config.enable_acc32) + val |=3D PDMA_STATIC_TR_XY_ACC32; + if (uc->config.enable_burst) + val |=3D PDMA_STATIC_TR_XY_BURST; + + udma_chanrt_write(uc, + UDMA_CHAN_RT_STATIC_TR_XY_REG, + val); + + /* save the current staticTR configuration */ + memcpy(&uc->static_tr, &uc->desc->static_tr, + sizeof(uc->static_tr)); + } + + if (uc->config.ep_type =3D=3D PSIL_EP_PDMA_XYMF) + udma_chanrt_write(uc, UDMA_CHAN_RT_FIFO_SEL_REG, uc->config.fifo_id); + + udma_chanrt_write(uc, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_AUTOPAIR); + + /* Poll for autopair completion */ + read_poll_timeout_atomic(udma_v2_check_chan_autopair_completion, + status, status !=3D 0, 100, 500, false, uc); + + if (status <=3D 0) { + udma_chanrt_write(uc, UDMA_CHAN_RT_CTL_REG, 0); + return -ETIMEDOUT; + } + + break; + case DMA_MEM_TO_MEM: + udma_bchanrt_write(uc, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_EN); + + break; + default: + return -EINVAL; + } + + uc->state =3D UDMA_CHAN_IS_ACTIVE; +out: + + return 0; +} + +static int udma_v2_stop(struct udma_chan *uc) +{ + uc->state =3D UDMA_CHAN_IS_TERMINATING; + reinit_completion(&uc->teardown_completed); + + if (uc->config.dir =3D=3D DMA_DEV_TO_MEM) { + if (!uc->cyclic && !uc->desc) + udma_push_to_ring(uc, -1); + } + + if (uc->config.dir !=3D DMA_MEM_TO_MEM) + udma_chanrt_write(uc, UDMA_CHAN_RT_PEER_REG(8), UDMA_CHAN_RT_PEER_REG8_F= LUSH); + + udma_chanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN, + UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN); + + return 0; +} + +static irqreturn_t udma_v2_udma_irq_handler(int irq, void *data) +{ + struct udma_chan *uc =3D data; + struct udma_dev *ud =3D uc->ud; + struct udma_desc *d; + + switch (uc->config.dir) { + case DMA_DEV_TO_MEM: + k3_ringacc_ring_clear_irq(uc->rflow->r_ring, + K3_RINGACC_RT_INT_STATUS_TR); + break; + case DMA_MEM_TO_DEV: + case DMA_MEM_TO_MEM: + k3_ringacc_ring_clear_irq(uc->tchan->tc_ring, + K3_RINGACC_RT_INT_STATUS_TR); + break; + default: + return IRQ_NONE; + } + + spin_lock(&uc->vc.lock); + d =3D uc->desc; + if (d) { + d->tr_idx =3D (d->tr_idx + 1) % d->sglen; + + if (uc->cyclic) { + vchan_cyclic_callback(&d->vd); + } else { + /* TODO: figure out the real amount of data */ + ud->decrement_byte_counters(uc, d->residue); + ud->start(uc); + vchan_cookie_complete(&d->vd); + } + } + + spin_unlock(&uc->vc.lock); + + return IRQ_HANDLED; +} + +static irqreturn_t udma_v2_ring_irq_handler(int irq, void *data) +{ + struct udma_chan *uc =3D data; + struct udma_dev *ud =3D uc->ud; + struct udma_desc *d; + dma_addr_t paddr =3D 0; + u32 intr_status, reg; + bool tr_handled =3D false; + + switch (uc->config.dir) { + case DMA_DEV_TO_MEM: + intr_status =3D k3_ringacc_ring_get_irq_status(uc->rflow->r_ring); + break; + case DMA_MEM_TO_DEV: + case DMA_MEM_TO_MEM: + intr_status =3D k3_ringacc_ring_get_irq_status(uc->tchan->tc_ring); + break; + default: + return IRQ_NONE; + } + + if (!intr_status) + return IRQ_NONE; /* Not this channel's interrupt */ + + if (intr_status & K3_RINGACC_RT_INT_STATUS_TR) { + reg =3D udma_chanrt_read(uc, UDMA_CHAN_RT_CTL_REG); + + /* check teardown status */ + if ((reg & UDMA_CHAN_RT_CTL_TDOWN) && !(reg & UDMA_CHAN_RT_CTL_EN)) + complete_all(&uc->teardown_completed); + udma_v2_udma_irq_handler(irq, data); + tr_handled =3D true; + + if (!(intr_status & K3_RINGACC_RT_INT_STATUS_COMPLETE)) + return IRQ_HANDLED; + } + + if (udma_pop_from_ring(uc, &paddr) || !paddr) + return tr_handled ? IRQ_HANDLED : IRQ_NONE; + + spin_lock(&uc->vc.lock); + + /* Teardown completion message */ + if (cppi5_desc_is_tdcm(paddr)) { + complete_all(&uc->teardown_completed); + + if (uc->terminated_desc) { + udma_desc_free(&uc->terminated_desc->vd); + uc->terminated_desc =3D NULL; + } + + if (!uc->desc) + ud->start(uc); + + goto out; + } + + d =3D udma_udma_desc_from_paddr(uc, paddr); + + if (d) { + dma_addr_t desc_paddr =3D udma_curr_cppi5_desc_paddr(d, + d->desc_idx); + if (desc_paddr !=3D paddr) { + dev_err(uc->ud->dev, "not matching descriptors!\n"); + goto out; + } + + if (d =3D=3D uc->desc) { + /* active descriptor */ + if (uc->cyclic) { + udma_cyclic_packet_elapsed(uc); + vchan_cyclic_callback(&d->vd); + } else { + if (udma_is_desc_really_done(uc, d)) { + ud->decrement_byte_counters(uc, d->residue); + ud->start(uc); + vchan_cookie_complete(&d->vd); + } else { + schedule_delayed_work(&uc->tx_drain.work, + 0); + } + } + } else { + /* + * terminated descriptor, mark the descriptor as + * completed to update the channel's cookie marker + */ + dma_cookie_complete(&d->vd.tx); + } + } +out: + spin_unlock(&uc->vc.lock); + + return IRQ_HANDLED; +} + +static int bcdma_v2_get_bchan(struct udma_chan *uc) +{ + struct udma_dev *ud =3D uc->ud; + enum udma_tp_level tpl; + int ret; + + if (uc->bchan) { + dev_dbg(ud->dev, "chan%d: already have bchan%d allocated\n", + uc->id, uc->bchan->id); + return 0; + } + + /* + * Use normal channels for peripherals, and highest TPL channel for + * mem2mem + */ + if (uc->config.tr_trigger_type) + tpl =3D 0; + else + tpl =3D ud->bchan_tpl.levels - 1; + + /* + * UDMA V2 uses a static 1:1 mapping between the virtual channel index + * (uc->id) and the hardware bchan/tchan/rchan index -- unlike V1, which + * dynamically allocates from a shared pool. Passing uc->id directly to + * __udma_reserve_*() is intentional, not a bug. + */ + uc->bchan =3D __udma_reserve_bchan(ud, tpl, uc->id); + if (IS_ERR(uc->bchan)) { + ret =3D PTR_ERR(uc->bchan); + uc->bchan =3D NULL; + return ret; + } + uc->chan =3D uc->bchan; + uc->tchan =3D uc->bchan; + + return 0; +} + +static int bcdma_v2_alloc_bchan_resources(struct udma_chan *uc) +{ + struct k3_ring_cfg ring_cfg; + struct udma_dev *ud =3D uc->ud; + int ret; + + ret =3D bcdma_v2_get_bchan(uc); + if (ret) + return ret; + + ret =3D k3_ringacc_request_rings_pair(ud->ringacc, ud->match_data->chan_c= nt + uc->id, -1, + &uc->bchan->t_ring, + &uc->bchan->tc_ring); + if (ret) { + ret =3D -EBUSY; + goto err_ring; + } + + memset(&ring_cfg, 0, sizeof(ring_cfg)); + ring_cfg.size =3D K3_UDMA_DEFAULT_RING_SIZE; + ring_cfg.elm_size =3D K3_RINGACC_RING_ELSIZE_8; + ring_cfg.mode =3D K3_RINGACC_RING_MODE_RING; + + k3_configure_chan_coherency(&uc->vc.chan, ud->asel); + ring_cfg.asel =3D ud->asel; + ring_cfg.dma_dev =3D dmaengine_get_dma_device(&uc->vc.chan); + + ret =3D k3_ringacc_ring_cfg(uc->bchan->t_ring, &ring_cfg); + if (ret) + goto err_ringcfg; + + return 0; + +err_ringcfg: + k3_ringacc_ring_free(uc->bchan->tc_ring); + uc->bchan->tc_ring =3D NULL; + k3_ringacc_ring_free(uc->bchan->t_ring); + uc->bchan->t_ring =3D NULL; + k3_configure_chan_coherency(&uc->vc.chan, 0); +err_ring: + bcdma_put_bchan(uc); + + return ret; +} + +static int udma_v2_alloc_tx_resources(struct udma_chan *uc) +{ + struct k3_ring_cfg ring_cfg; + struct udma_dev *ud =3D uc->ud; + struct udma_tchan *tchan; + int ring_idx, ret; + + ret =3D udma_get_tchan(uc); + if (ret) + return ret; + + tchan =3D uc->tchan; + if (tchan->tflow_id >=3D 0) + ring_idx =3D tchan->tflow_id; + else + ring_idx =3D tchan->id; + + ret =3D k3_ringacc_request_rings_pair(ud->ringacc, ring_idx, -1, + &tchan->t_ring, + &tchan->tc_ring); + if (ret) { + ret =3D -EBUSY; + goto err_ring; + } + + memset(&ring_cfg, 0, sizeof(ring_cfg)); + ring_cfg.size =3D K3_UDMA_DEFAULT_RING_SIZE; + ring_cfg.elm_size =3D K3_RINGACC_RING_ELSIZE_8; + ring_cfg.mode =3D K3_RINGACC_RING_MODE_RING; + + k3_configure_chan_coherency(&uc->vc.chan, uc->config.asel); + ring_cfg.asel =3D uc->config.asel; + ring_cfg.dma_dev =3D dmaengine_get_dma_device(&uc->vc.chan); + + ret =3D k3_ringacc_ring_cfg(tchan->t_ring, &ring_cfg); + ret |=3D k3_ringacc_ring_cfg(tchan->tc_ring, &ring_cfg); + + if (ret) + goto err_ringcfg; + + return 0; + +err_ringcfg: + k3_ringacc_ring_free(uc->tchan->tc_ring); + uc->tchan->tc_ring =3D NULL; + k3_ringacc_ring_free(uc->tchan->t_ring); + uc->tchan->t_ring =3D NULL; +err_ring: + udma_put_tchan(uc); + + return ret; +} + +static int udma_v2_alloc_rx_resources(struct udma_chan *uc) +{ + struct udma_dev *ud =3D uc->ud; + struct k3_ring_cfg ring_cfg; + struct udma_rflow *rflow; + int fd_ring_id; + int ret; + + ret =3D udma_get_rchan(uc); + if (ret) + return ret; + + /* For MEM_TO_MEM we don't need rflow or rings */ + if (uc->config.dir =3D=3D DMA_MEM_TO_MEM) + return 0; + + if (uc->config.default_flow_id >=3D 0) + ret =3D udma_get_rflow(uc, uc->config.default_flow_id); + else + ret =3D udma_get_rflow(uc, uc->rchan->id); + + if (ret) { + ret =3D -EBUSY; + goto err_rflow; + } + + rflow =3D uc->rflow; + if (ud->tflow_cnt) + fd_ring_id =3D ud->tflow_cnt + rflow->id; + else + fd_ring_id =3D uc->rchan->id; + ret =3D k3_ringacc_request_rings_pair(ud->ringacc, fd_ring_id, -1, + &rflow->fd_ring, &rflow->r_ring); + if (ret) { + ret =3D -EBUSY; + goto err_ring; + } + + memset(&ring_cfg, 0, sizeof(ring_cfg)); + + ring_cfg.elm_size =3D K3_RINGACC_RING_ELSIZE_8; + ring_cfg.size =3D K3_UDMA_DEFAULT_RING_SIZE; + ring_cfg.mode =3D K3_RINGACC_RING_MODE_RING; + + k3_configure_chan_coherency(&uc->vc.chan, uc->config.asel); + ring_cfg.asel =3D uc->config.asel; + ring_cfg.dma_dev =3D dmaengine_get_dma_device(&uc->vc.chan); + + ret =3D k3_ringacc_ring_cfg(rflow->fd_ring, &ring_cfg); + + ring_cfg.size =3D K3_UDMA_DEFAULT_RING_SIZE; + ret |=3D k3_ringacc_ring_cfg(rflow->r_ring, &ring_cfg); + + if (ret) + goto err_ringcfg; + + return 0; + +err_ringcfg: + k3_ringacc_ring_free(rflow->r_ring); + rflow->r_ring =3D NULL; + k3_ringacc_ring_free(rflow->fd_ring); + rflow->fd_ring =3D NULL; +err_ring: + udma_put_rflow(uc); +err_rflow: + udma_put_rchan(uc); + + return ret; +} + +static int bcdma_v2_alloc_chan_resources(struct dma_chan *chan) +{ + struct udma_chan *uc =3D to_udma_chan(chan); + struct udma_dev *ud =3D to_udma_dev(chan->device); + struct platform_device *pdev =3D to_platform_device(ud->dev); + char irq_name[10]; + u32 irq_ring_idx; + int ret; + + /* Only TR mode is supported */ + uc->config.pkt_mode =3D false; + + /* + * Make sure that the completion is in a known state: + * No teardown, the channel is idle + */ + reinit_completion(&uc->teardown_completed); + complete_all(&uc->teardown_completed); + uc->state =3D UDMA_CHAN_IS_IDLE; + + switch (uc->config.dir) { + case DMA_MEM_TO_MEM: + /* Non synchronized - mem to mem type of transfer */ + dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-MEM\n", __func__, + uc->id); + + ret =3D bcdma_v2_alloc_bchan_resources(uc); + if (ret) + return ret; + + irq_ring_idx =3D ud->match_data->chan_cnt + uc->id; + break; + case DMA_MEM_TO_DEV: + /* Slave transfer synchronized - mem to dev (TX) transfer */ + dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__, + uc->id); + + ret =3D udma_v2_alloc_tx_resources(uc); + if (ret) { + uc->config.remote_thread_id =3D -1; + return ret; + } + + uc->config.src_thread =3D ud->psil_base + uc->tchan->id; + uc->config.dst_thread =3D uc->config.remote_thread_id; + uc->config.dst_thread |=3D K3_PSIL_DST_THREAD_ID_OFFSET; + + irq_ring_idx =3D uc->tchan->id; + + break; + case DMA_DEV_TO_MEM: + /* Slave transfer synchronized - dev to mem (RX) transfer */ + dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__, + uc->id); + + ret =3D udma_v2_alloc_rx_resources(uc); + if (ret) { + uc->config.remote_thread_id =3D -1; + return ret; + } + + uc->config.src_thread =3D uc->config.remote_thread_id; + uc->config.dst_thread =3D (ud->psil_base + uc->rchan->id) | + K3_PSIL_DST_THREAD_ID_OFFSET; + + irq_ring_idx =3D uc->rchan->id; + + break; + default: + /* Can not happen */ + dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n", + __func__, uc->id, uc->config.dir); + return -EINVAL; + } + + /* check if the channel configuration was successful */ + if (ret) + goto err_res_free; + + if (udma_is_chan_running(uc)) { + dev_warn(ud->dev, "chan%d: is running!\n", uc->id); + ud->reset_chan(uc, false); + if (udma_is_chan_running(uc)) { + dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); + ret =3D -EBUSY; + goto err_res_free; + } + } + + uc->dma_dev =3D dmaengine_get_dma_device(chan); + if (uc->config.dir =3D=3D DMA_MEM_TO_MEM && !uc->config.tr_trigger_type)= { + uc->config.hdesc_size =3D + cppi5_trdesc_calc_size(sizeof(struct cppi5_tr_type15_t), 2); + + uc->hdesc_pool =3D dma_pool_create(uc->name, ud->ddev.dev, + uc->config.hdesc_size, + ud->desc_align, + 0); + if (!uc->hdesc_pool) { + dev_err(ud->ddev.dev, + "Descriptor pool allocation failed\n"); + uc->use_dma_pool =3D false; + ret =3D -ENOMEM; + goto err_res_free; + } + + uc->use_dma_pool =3D true; + } else if (uc->config.dir !=3D DMA_MEM_TO_MEM) { + uc->psil_paired =3D true; + } + + INIT_DELAYED_WORK(&uc->tx_drain.work, udma_check_tx_completion); + + snprintf(irq_name, sizeof(irq_name), "chan%u", irq_ring_idx); + uc->irq_num_ring =3D platform_get_irq_byname(pdev, irq_name); + if (uc->irq_num_ring < 0) { + ret =3D uc->irq_num_ring; + goto err_res_free; + } + + ret =3D request_irq(uc->irq_num_ring, udma_v2_ring_irq_handler, + IRQF_SHARED | IRQF_TRIGGER_HIGH, uc->name, uc); + if (ret) { + dev_err(ud->dev, "chan%d: ring irq request failed\n", uc->id); + goto err_irq_free; + } + + udma_reset_rings(uc); + + return 0; + +err_irq_free: + uc->irq_num_ring =3D 0; + uc->irq_num_udma =3D 0; +err_res_free: + bcdma_free_bchan_resources(uc); + udma_free_tx_resources(uc); + udma_free_rx_resources(uc); + + udma_reset_uchan(uc); + + if (uc->use_dma_pool) { + dma_pool_destroy(uc->hdesc_pool); + uc->use_dma_pool =3D false; + } + + return ret; +} + +static enum dma_status udma_v2_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct udma_chan *uc =3D to_udma_chan(chan); + enum dma_status ret; + unsigned long flags; + + spin_lock_irqsave(&uc->vc.lock, flags); + + ret =3D dma_cookie_status(chan, cookie, txstate); + + if (!udma_is_chan_running(uc)) + ret =3D DMA_COMPLETE; + + if (ret =3D=3D DMA_IN_PROGRESS && udma_v2_is_chan_paused(uc)) + ret =3D DMA_PAUSED; + + if (ret =3D=3D DMA_COMPLETE || !txstate) + goto out; + + if (uc->desc && uc->desc->vd.tx.cookie =3D=3D cookie) { + u32 peer_bcnt =3D 0; + u32 bcnt =3D 0; + u32 residue =3D uc->desc->residue; + u32 delay =3D 0; + + if (uc->desc->dir =3D=3D DMA_MEM_TO_DEV) { + bcnt =3D udma_chanrt_read(uc, UDMA_CHAN_RT_SBCNT_REG); + + if (uc->config.ep_type !=3D PSIL_EP_NATIVE) { + peer_bcnt =3D udma_chanrt_read(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG); + + if (bcnt > peer_bcnt) + delay =3D bcnt - peer_bcnt; + } + } else if (uc->desc->dir =3D=3D DMA_DEV_TO_MEM) { + bcnt =3D udma_chanrt_read(uc, UDMA_CHAN_RT_BCNT_REG); + + if (uc->config.ep_type !=3D PSIL_EP_NATIVE) { + peer_bcnt =3D udma_chanrt_read(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG); + + if (peer_bcnt > bcnt) + delay =3D peer_bcnt - bcnt; + } + } else { + bcnt =3D udma_chanrt_read(uc, UDMA_CHAN_RT_BCNT_REG); + } + + if (bcnt && !(bcnt % uc->desc->residue)) + residue =3D 0; + else + residue -=3D bcnt % uc->desc->residue; + + if (!residue && (uc->config.dir =3D=3D DMA_DEV_TO_MEM || !delay)) { + ret =3D DMA_COMPLETE; + delay =3D 0; + } + + dma_set_residue(txstate, residue); + dma_set_in_flight_bytes(txstate, delay); + + } else { + ret =3D DMA_COMPLETE; + } + +out: + spin_unlock_irqrestore(&uc->vc.lock, flags); + return ret; +} + +static int udma_v2_pause(struct dma_chan *chan) +{ + struct udma_chan *uc =3D to_udma_chan(chan); + unsigned long flags; + + /* pause the channel */ + spin_lock_irqsave(&uc->vc.lock, flags); + udma_chanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_PAUSE, UDMA_CHAN_RT_CTL_PAUSE); + spin_unlock_irqrestore(&uc->vc.lock, flags); + + return 0; +} + +static int udma_v2_resume(struct dma_chan *chan) +{ + struct udma_chan *uc =3D to_udma_chan(chan); + unsigned long flags; + + /* resume the channel */ + spin_lock_irqsave(&uc->vc.lock, flags); + udma_chanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_PAUSE, 0); + spin_unlock_irqrestore(&uc->vc.lock, flags); + + return 0; +} + +static struct platform_driver bcdma_v2_driver; + +static bool udma_v2_dma_filter_fn(struct dma_chan *chan, void *param) +{ + struct udma_v2_filter_param *filter_param; + struct psil_endpoint_config *ep_config; + struct udma_chan_config *ucc; + struct udma_chan *uc; + struct udma_dev *ud; + + if (chan->device->dev->driver !=3D &bcdma_v2_driver.driver) + return false; + + uc =3D to_udma_chan(chan); + ucc =3D &uc->config; + ud =3D uc->ud; + filter_param =3D param; + + if (filter_param->asel > 15) { + dev_err(ud->dev, "Invalid channel asel: %u\n", + filter_param->asel); + return false; + } + + ucc->asel =3D filter_param->asel; + ucc->tr_trigger_type =3D filter_param->tr_trigger_type; + + if (ucc->tr_trigger_type) { + ucc->dir =3D DMA_MEM_TO_MEM; + goto triggered_bchan; + } else { + u32 thread_id; + bool dev_to_mem; + + ep_config =3D psil_get_ep_config_by_id(filter_param->channel_id, + (ud->match_data->type =3D=3D DMA_TYPE_PKTDMA), + &thread_id, &dev_to_mem); + if (IS_ERR(ep_config)) { + dev_err(ud->dev, "No config for channel %u\n", + filter_param->channel_id); + ucc->atype =3D 0; + ucc->asel =3D 0; + return false; + } + ucc->remote_thread_id =3D thread_id; + ucc->dir =3D dev_to_mem ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; + } + if (IS_ERR(ep_config)) { + dev_err(ud->dev, "No configuration for psi-l thread 0x%04x\n", + ucc->remote_thread_id); + ucc->dir =3D DMA_MEM_TO_MEM; + ucc->remote_thread_id =3D -1; + ucc->atype =3D 0; + ucc->asel =3D 0; + return false; + } + + ucc->pkt_mode =3D ep_config->pkt_mode; + ucc->channel_tpl =3D ep_config->channel_tpl; + ucc->notdpkt =3D ep_config->notdpkt; + ucc->ep_type =3D ep_config->ep_type; + ucc->fifo_id =3D ep_config->fifo_id; + + if (ud->match_data->version =3D=3D K3_UDMA_V2 && + ep_config->mapped_channel_id >=3D 0) { + ucc->mapped_channel_id =3D ep_config->mapped_channel_id; + ucc->default_flow_id =3D ep_config->default_flow_id; + } else { + ucc->mapped_channel_id =3D -1; + ucc->default_flow_id =3D -1; + } + + ucc->needs_epib =3D ep_config->needs_epib; + ucc->psd_size =3D ep_config->psd_size; + ucc->metadata_size =3D + (ucc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_SIZE : 0) + + ucc->psd_size; + + if (ucc->ep_type !=3D PSIL_EP_NATIVE) { + const struct udma_match_data *match_data =3D ud->match_data; + + if ((match_data->flags & UDMA_FLAG_PDMA_ACC32) && ep_config->pdma_acc32) + ucc->enable_acc32 =3D true; + else + ucc->enable_acc32 =3D false; + + if ((match_data->flags & UDMA_FLAG_PDMA_BURST) && ep_config->pdma_burst) + ucc->enable_burst =3D true; + else + ucc->enable_burst =3D false; + } + if (ucc->pkt_mode) + ucc->hdesc_size =3D ALIGN(sizeof(struct cppi5_host_desc_t) + + ucc->metadata_size, ud->desc_align); + + dev_dbg(ud->dev, "chan%d: Remote thread: 0x%04x (%s)\n", uc->id, + ucc->remote_thread_id, dmaengine_get_direction_text(ucc->dir)); + + return true; + +triggered_bchan: + dev_dbg(ud->dev, "chan%d: triggered channel (type: %u)\n", uc->id, + ucc->tr_trigger_type); + + return true; +} + +static struct dma_chan *udma_v2_of_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct udma_dev *ud =3D ofdma->of_dma_data; + dma_cap_mask_t mask =3D ud->ddev.cap_mask; + struct udma_v2_filter_param filter_param; + struct dma_chan *chan; + + if (ud->match_data->type =3D=3D DMA_TYPE_BCDMA) { + if (dma_spec->args_count !=3D 4) + return NULL; + + filter_param.tr_trigger_type =3D dma_spec->args[0]; + filter_param.trigger_param =3D dma_spec->args[1]; + filter_param.channel_id =3D dma_spec->args[2]; + filter_param.asel =3D dma_spec->args[3]; + } else { + if (dma_spec->args_count !=3D 1 && dma_spec->args_count !=3D 2) + return NULL; + + filter_param.channel_id =3D dma_spec->args[0]; + filter_param.tr_trigger_type =3D 0; + if (dma_spec->args_count =3D=3D 2) + filter_param.asel =3D dma_spec->args[1]; + else + filter_param.asel =3D 0; + } + + chan =3D __dma_request_channel(&mask, udma_v2_dma_filter_fn, &filter_para= m, + ofdma->of_node); + if (!chan) { + dev_err(ud->dev, "get channel fail in %s.\n", __func__); + return ERR_PTR(-EINVAL); + } + + return chan; +} + +static struct udma_match_data bcdma_v2_am62l_data =3D { + .type =3D DMA_TYPE_BCDMA, + .version =3D K3_UDMA_V2, + .psil_base =3D 0x2000, /* for tchan and rchan, not applicable to bchan */ + .enable_memcpy_support =3D true, /* Supported via bchan */ + .flags =3D UDMA_FLAGS_J7_CLASS, + .statictr_z_mask =3D GENMASK(23, 0), + .burst_size =3D { + TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES, /* Normal Channels */ + 0, /* No H Channels */ + 0, /* No UH Channels */ + }, + .bchan_cnt =3D 16, + .chan_cnt =3D 128, + .tchan_cnt =3D 128, + .rchan_cnt =3D 128, +}; + +static const struct of_device_id udma_of_match[] =3D { + { + .compatible =3D "ti,am62l-dmss-bcdma", + .data =3D &bcdma_v2_am62l_data, + }, + { /* Sentinel */ }, +}; + +static const struct soc_device_attribute k3_soc_devices[] =3D { + { .family =3D "AM62LX", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, udma_of_match); + +static int udma_v2_get_mmrs(struct platform_device *pdev, struct udma_dev = *ud) +{ + int i; + + ud->mmrs[V2_MMR_GCFG] =3D devm_platform_ioremap_resource_byname(pdev, + v2_mmr_names[V2_MMR_GCFG]); + if (IS_ERR(ud->mmrs[V2_MMR_GCFG])) + return PTR_ERR(ud->mmrs[V2_MMR_GCFG]); + + ud->bchan_cnt =3D ud->match_data->bchan_cnt; + /* There are no tchan and rchan in BCDMA_V2. + * Duplicate chan as tchan and rchan to keep the common code + * in k3-udma-common.c functional for BCDMA_V2. + */ + ud->chan_cnt =3D ud->match_data->chan_cnt; + ud->tchan_cnt =3D ud->match_data->chan_cnt; + ud->rchan_cnt =3D ud->match_data->chan_cnt; + ud->rflow_cnt =3D ud->chan_cnt; + + for (i =3D 1; i < V2_MMR_LAST; i++) { + if (i =3D=3D V2_MMR_BCHANRT && ud->bchan_cnt =3D=3D 0) + continue; + if (i =3D=3D V2_MMR_CHANRT && ud->chan_cnt =3D=3D 0) + continue; + + ud->mmrs[i] =3D devm_platform_ioremap_resource_byname(pdev, v2_mmr_names= [i]); + if (IS_ERR(ud->mmrs[i])) + return PTR_ERR(ud->mmrs[i]); + } + + return 0; +} + +static int udma_v2_probe(struct platform_device *pdev) +{ + const struct soc_device_attribute *soc; + struct device *dev =3D &pdev->dev; + const struct of_device_id *match; + struct udma_dev *ud; + int ch_count, i, ret; + + ret =3D dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(48)); + if (ret) + dev_err(dev, "failed to set dma mask stuff\n"); + + ud =3D devm_kzalloc(dev, sizeof(*ud), GFP_KERNEL); + if (!ud) + return -ENOMEM; + + match =3D of_match_node(udma_of_match, dev->of_node); + if (!match) { + dev_err(dev, "No compatible match found\n"); + return -ENODEV; + } + ud->match_data =3D match->data; + + ud->soc_data =3D ud->match_data->soc_data; + if (!ud->soc_data) { + soc =3D soc_device_match(k3_soc_devices); + if (!soc) { + dev_err(dev, "No compatible SoC found\n"); + return -ENODEV; + } + ud->soc_data =3D soc->data; + } + + ud->start =3D udma_v2_start; + ud->stop =3D udma_v2_stop; + ud->reset_chan =3D udma_v2_reset_chan; + ud->decrement_byte_counters =3D udma_v2_decrement_byte_counters; + ud->bcdma_setup_sci_resources =3D NULL; + + ret =3D udma_v2_get_mmrs(pdev, ud); + if (ret) + return ret; + + struct k3_ringacc_init_data ring_init_data =3D {0}; + + ring_init_data.num_rings =3D ud->bchan_cnt + ud->chan_cnt; + + ud->ringacc =3D k3_ringacc_dmarings_init(pdev, &ring_init_data); + + if (IS_ERR(ud->ringacc)) + return PTR_ERR(ud->ringacc); + + dma_cap_set(DMA_SLAVE, ud->ddev.cap_mask); + + dma_cap_set(DMA_CYCLIC, ud->ddev.cap_mask); + ud->ddev.device_prep_dma_cyclic =3D udma_prep_dma_cyclic; + + ud->ddev.device_config =3D udma_slave_config; + ud->ddev.device_prep_slave_sg =3D udma_prep_slave_sg; + ud->ddev.device_issue_pending =3D udma_issue_pending; + ud->ddev.device_tx_status =3D udma_v2_tx_status; + ud->ddev.device_pause =3D udma_v2_pause; + ud->ddev.device_resume =3D udma_v2_resume; + ud->ddev.device_terminate_all =3D udma_terminate_all; + ud->ddev.device_synchronize =3D udma_synchronize; +#ifdef CONFIG_DEBUG_FS + ud->ddev.dbg_summary_show =3D udma_dbg_summary_show; +#endif + + ud->ddev.device_alloc_chan_resources =3D + bcdma_v2_alloc_chan_resources; + + ud->ddev.device_free_chan_resources =3D udma_free_chan_resources; + + ud->ddev.src_addr_widths =3D TI_UDMAC_BUSWIDTHS; + ud->ddev.dst_addr_widths =3D TI_UDMAC_BUSWIDTHS; + ud->ddev.directions =3D BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); + ud->ddev.residue_granularity =3D DMA_RESIDUE_GRANULARITY_BURST; + ud->ddev.desc_metadata_modes =3D DESC_METADATA_CLIENT | + DESC_METADATA_ENGINE; + if (ud->match_data->enable_memcpy_support && + !(ud->match_data->type =3D=3D DMA_TYPE_BCDMA && ud->bchan_cnt =3D=3D = 0)) { + dma_cap_set(DMA_MEMCPY, ud->ddev.cap_mask); + ud->ddev.device_prep_dma_memcpy =3D udma_prep_dma_memcpy; + ud->ddev.directions |=3D BIT(DMA_MEM_TO_MEM); + } + + ud->ddev.dev =3D dev; + ud->dev =3D dev; + ud->psil_base =3D ud->match_data->psil_base; + + INIT_LIST_HEAD(&ud->ddev.channels); + INIT_LIST_HEAD(&ud->desc_to_purge); + + ch_count =3D k3_udma_setup_resources(ud); + if (ch_count <=3D 0) + return ch_count; + + spin_lock_init(&ud->lock); + INIT_WORK(&ud->purge_work, udma_purge_desc_work); + + ud->desc_align =3D 64; + if (ud->desc_align < dma_get_cache_alignment()) + ud->desc_align =3D dma_get_cache_alignment(); + + ret =3D udma_setup_rx_flush(ud); + if (ret) + return ret; + + for (i =3D 0; i < ud->bchan_cnt; i++) { + struct udma_bchan *bchan =3D &ud->bchans[i]; + + bchan->id =3D i; + bchan->reg_rt =3D ud->mmrs[V2_MMR_BCHANRT] + i * 0x1000; + } + + for (i =3D 0; i < ud->tchan_cnt; i++) { + struct udma_tchan *tchan =3D &ud->tchans[i]; + + tchan->id =3D i; + tchan->reg_rt =3D ud->mmrs[V2_MMR_CHANRT] + i * 0x1000; + } + + for (i =3D 0; i < ud->rchan_cnt; i++) { + struct udma_rchan *rchan =3D &ud->rchans[i]; + + rchan->id =3D i; + rchan->reg_rt =3D ud->mmrs[V2_MMR_CHANRT] + i * 0x1000; + } + + for (i =3D 0; i < ud->rflow_cnt; i++) { + struct udma_rflow *rflow =3D &ud->rflows[i]; + + rflow->id =3D i; + rflow->reg_rt =3D ud->rflow_rt + i * 0x2000; + } + + for (i =3D 0; i < ch_count; i++) { + struct udma_chan *uc =3D &ud->channels[i]; + + uc->ud =3D ud; + uc->vc.desc_free =3D udma_desc_free; + uc->id =3D i; + uc->bchan =3D NULL; + uc->tchan =3D NULL; + uc->rchan =3D NULL; + uc->config.remote_thread_id =3D -1; + uc->config.mapped_channel_id =3D -1; + uc->config.default_flow_id =3D -1; + uc->config.dir =3D DMA_MEM_TO_MEM; + uc->name =3D devm_kasprintf(dev, GFP_KERNEL, "%s chan%d", + dev_name(dev), i); + if (!uc->name) + return -ENOMEM; + + vchan_init(&uc->vc, &ud->ddev); + /* Use custom vchan completion handling */ + tasklet_setup(&uc->vc.task, udma_vchan_complete); + init_completion(&uc->teardown_completed); + INIT_DELAYED_WORK(&uc->tx_drain.work, udma_check_tx_completion); + } + + /* Configure the copy_align to the maximum burst size the device supports= */ + ud->ddev.copy_align =3D udma_get_copy_align(ud); + + ret =3D dma_async_device_register(&ud->ddev); + if (ret) { + dev_err(dev, "failed to register slave DMA engine: %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, ud); + + ret =3D of_dma_controller_register(dev->of_node, udma_v2_of_xlate, ud); + if (ret) { + dev_err(dev, "failed to register of_dma controller\n"); + dma_async_device_unregister(&ud->ddev); + } + + return ret; +} + +static int __maybe_unused udma_v2_pm_suspend(struct device *dev) +{ + struct udma_dev *ud =3D dev_get_drvdata(dev); + struct dma_device *dma_dev =3D &ud->ddev; + struct dma_chan *chan; + struct udma_chan *uc; + + list_for_each_entry(chan, &dma_dev->channels, device_node) { + if (chan->client_count) { + uc =3D to_udma_chan(chan); + /* backup the channel configuration */ + memcpy(&uc->backup_config, &uc->config, + sizeof(struct udma_chan_config)); + dev_dbg(dev, "Suspending channel %s\n", + dma_chan_name(chan)); + ud->ddev.device_free_chan_resources(chan); + } + } + + return 0; +} + +static int __maybe_unused udma_v2_pm_resume(struct device *dev) +{ + struct udma_dev *ud =3D dev_get_drvdata(dev); + struct dma_device *dma_dev =3D &ud->ddev; + struct dma_chan *chan; + struct udma_chan *uc; + int ret; + + list_for_each_entry(chan, &dma_dev->channels, device_node) { + if (chan->client_count) { + uc =3D to_udma_chan(chan); + /* restore the channel configuration */ + memcpy(&uc->config, &uc->backup_config, + sizeof(struct udma_chan_config)); + dev_dbg(dev, "Resuming channel %s\n", + dma_chan_name(chan)); + ret =3D ud->ddev.device_alloc_chan_resources(chan); + if (ret) + return ret; + } + } + + return 0; +} + +static const struct dev_pm_ops udma_pm_ops =3D { + SET_LATE_SYSTEM_SLEEP_PM_OPS(udma_v2_pm_suspend, udma_v2_pm_resume) +}; + +static struct platform_driver bcdma_v2_driver =3D { + .driver =3D { + .name =3D "ti-udma-v2", + .of_match_table =3D udma_of_match, + .suppress_bind_attrs =3D true, + .pm =3D &udma_pm_ops, + }, + .probe =3D udma_v2_probe, +}; + +module_platform_driver(bcdma_v2_driver); +MODULE_DESCRIPTION("Texas Instruments K3 UDMA v2 support"); +MODULE_LICENSE("GPL"); diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index ddedd51ab26d9..6bf35dfec5e4e 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -1810,6 +1810,7 @@ static struct dma_chan *udma_of_xlate(struct of_phand= le_args *dma_spec, =20 static struct udma_match_data am654_main_data =3D { .type =3D DMA_TYPE_UDMA, + .version =3D K3_UDMA_V1, .psil_base =3D 0x1000, .enable_memcpy_support =3D true, .statictr_z_mask =3D GENMASK(11, 0), @@ -1822,6 +1823,7 @@ static struct udma_match_data am654_main_data =3D { =20 static struct udma_match_data am654_mcu_data =3D { .type =3D DMA_TYPE_UDMA, + .version =3D K3_UDMA_V1, .psil_base =3D 0x6000, .enable_memcpy_support =3D false, .statictr_z_mask =3D GENMASK(11, 0), @@ -1834,6 +1836,7 @@ static struct udma_match_data am654_mcu_data =3D { =20 static struct udma_match_data j721e_main_data =3D { .type =3D DMA_TYPE_UDMA, + .version =3D K3_UDMA_V1, .psil_base =3D 0x1000, .enable_memcpy_support =3D true, .flags =3D UDMA_FLAGS_J7_CLASS, @@ -1847,6 +1850,7 @@ static struct udma_match_data j721e_main_data =3D { =20 static struct udma_match_data j721e_mcu_data =3D { .type =3D DMA_TYPE_UDMA, + .version =3D K3_UDMA_V1, .psil_base =3D 0x6000, .enable_memcpy_support =3D false, /* MEM_TO_MEM is slow via MCU UDMA */ .flags =3D UDMA_FLAGS_J7_CLASS, @@ -1876,6 +1880,7 @@ static struct udma_soc_data j721s2_bcdma_csi_soc_data= =3D { =20 static struct udma_match_data am62a_bcdma_csirx_data =3D { .type =3D DMA_TYPE_BCDMA, + .version =3D K3_UDMA_V1, .psil_base =3D 0x3100, .enable_memcpy_support =3D false, .burst_size =3D { @@ -1888,6 +1893,7 @@ static struct udma_match_data am62a_bcdma_csirx_data = =3D { =20 static struct udma_match_data am64_bcdma_data =3D { .type =3D DMA_TYPE_BCDMA, + .version =3D K3_UDMA_V1, .psil_base =3D 0x2000, /* for tchan and rchan, not applicable to bchan */ .enable_memcpy_support =3D true, /* Supported via bchan */ .flags =3D UDMA_FLAGS_J7_CLASS, @@ -1901,6 +1907,7 @@ static struct udma_match_data am64_bcdma_data =3D { =20 static struct udma_match_data am64_pktdma_data =3D { .type =3D DMA_TYPE_PKTDMA, + .version =3D K3_UDMA_V1, .psil_base =3D 0x1000, .enable_memcpy_support =3D false, /* PKTDMA does not support MEM_TO_MEM */ .flags =3D UDMA_FLAGS_J7_CLASS, @@ -1914,6 +1921,7 @@ static struct udma_match_data am64_pktdma_data =3D { =20 static struct udma_match_data j721s2_bcdma_csi_data =3D { .type =3D DMA_TYPE_BCDMA, + .version =3D K3_UDMA_V1, .psil_base =3D 0x2000, .enable_memcpy_support =3D false, .burst_size =3D { @@ -1926,6 +1934,7 @@ static struct udma_match_data j721s2_bcdma_csi_data = =3D { =20 static struct udma_match_data j722s_bcdma_csi_data =3D { .type =3D DMA_TYPE_BCDMA, + .version =3D K3_UDMA_V1, .psil_base =3D 0x3100, .enable_memcpy_support =3D false, .burst_size =3D { diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h index d64b670d42490..b2e5455b1087e 100644 --- a/drivers/dma/ti/k3-udma.h +++ b/drivers/dma/ti/k3-udma.h @@ -32,6 +32,12 @@ #define UDMA_CHAN_RT_SWTRIG_REG 0x8 #define UDMA_CHAN_RT_STDATA_REG 0x80 =20 +#define UDMA_CHAN_RT_STATIC_TR_XY_REG 0x800 +#define UDMA_CHAN_RT_STATIC_TR_Z_REG 0x804 +#define UDMA_CHAN_RT_PERIPH_BCNT_REG 0x810 +#define UDMA_CHAN_RT_FIFO_SEL_REG 0x824 +#define UDMA_CHAN_RT_PDMA_STATE_REG 0x80c + #define UDMA_CHAN_RT_PEER_REG(i) (0x200 + ((i) * 0x4)) #define UDMA_CHAN_RT_PEER_STATIC_TR_XY_REG \ UDMA_CHAN_RT_PEER_REG(0) /* PSI-L: 0x400 */ @@ -71,8 +77,16 @@ #define UDMA_CHAN_RT_CTL_TDOWN BIT(30) #define UDMA_CHAN_RT_CTL_PAUSE BIT(29) #define UDMA_CHAN_RT_CTL_FTDOWN BIT(28) +#define UDMA_CHAN_RT_CTL_AUTOPAIR BIT(23) +#define UDMA_CHAN_RT_CTL_PAIR_TIMEOUT BIT(17) +#define UDMA_CHAN_RT_CTL_PAIR_COMPLETE BIT(16) #define UDMA_CHAN_RT_CTL_ERROR BIT(0) =20 +/* UDMA_CHAN_RT_PDMA_STATE_REG */ +#define UDMA_CHAN_RT_PDMA_STATE_IN_EVT BIT(31) +#define UDMA_CHAN_RT_PDMA_STATE_TDOWN BIT(30) +#define UDMA_CHAN_RT_PDMA_STATE_PAUSE BIT(29) + /* UDMA_CHAN_RT_PEER_RT_EN_REG */ #define UDMA_PEER_RT_EN_ENABLE BIT(31) #define UDMA_PEER_RT_EN_TEARDOWN BIT(30) @@ -103,6 +117,9 @@ */ #define PDMA_STATIC_TR_Z(x, mask) ((x) & (mask)) =20 +/* UDMA_CHAN_RT_PEER_REG(8) */ +#define UDMA_CHAN_RT_PEER_REG8_FLUSH 0x09000000 + /* Address Space Select */ #define K3_ADDRESS_ASEL_SHIFT 48 =20 @@ -208,6 +225,11 @@ enum k3_dma_type { DMA_TYPE_PKTDMA, }; =20 +enum k3_dma_version { + K3_UDMA_V1 =3D 0, + K3_UDMA_V2, +}; + enum udma_mmr { MMR_GCFG =3D 0, MMR_BCHANRT, @@ -216,6 +238,13 @@ enum udma_mmr { MMR_LAST, }; =20 +enum udma_v2_mmr { + V2_MMR_GCFG =3D 0, + V2_MMR_BCHANRT, + V2_MMR_CHANRT, + V2_MMR_LAST, +}; + struct udma_filter_param { int remote_thread_id; u32 atype; @@ -223,6 +252,13 @@ struct udma_filter_param { u32 tr_trigger_type; }; =20 +struct udma_v2_filter_param { + u32 tr_trigger_type; + u32 trigger_param; + u32 channel_id; + u32 asel; +}; + struct udma_tchan { void __iomem *reg_rt; =20 @@ -234,17 +270,13 @@ struct udma_tchan { }; =20 #define udma_bchan udma_tchan +#define udma_rchan udma_tchan =20 struct udma_rflow { int id; struct k3_ring *fd_ring; /* Free Descriptor ring */ struct k3_ring *r_ring; /* Receive ring */ -}; - -struct udma_rchan { void __iomem *reg_rt; - - int id; }; =20 struct udma_oes_offsets { @@ -266,12 +298,19 @@ struct udma_oes_offsets { =20 struct udma_match_data { enum k3_dma_type type; + enum k3_dma_version version; u32 psil_base; bool enable_memcpy_support; u32 flags; u32 statictr_z_mask; u8 burst_size[3]; struct udma_soc_data *soc_data; + u32 bchan_cnt; + u32 chan_cnt; + u32 tchan_cnt; + u32 rchan_cnt; + u32 tflow_cnt; + u32 rflow_cnt; }; =20 struct udma_soc_data { @@ -306,6 +345,7 @@ struct udma_dev { struct dma_device ddev; struct device *dev; void __iomem *mmrs[MMR_LAST]; + void __iomem *rflow_rt; const struct udma_match_data *match_data; const struct udma_soc_data *soc_data; =20 @@ -326,12 +366,14 @@ struct udma_dev { struct udma_rx_flush rx_flush; =20 int bchan_cnt; + int chan_cnt; int tchan_cnt; int echan_cnt; int rchan_cnt; int rflow_cnt; int tflow_cnt; unsigned long *bchan_map; + unsigned long *chan_map; unsigned long *tchan_map; unsigned long *rchan_map; unsigned long *rflow_gp_map; @@ -340,6 +382,7 @@ struct udma_dev { unsigned long *tflow_map; =20 struct udma_bchan *bchans; + struct udma_tchan *chans; struct udma_tchan *tchans; struct udma_rchan *rchans; struct udma_rflow *rflows; @@ -411,6 +454,7 @@ struct udma_chan_config { bool enable_acc32; bool enable_burst; enum udma_tp_level channel_tpl; /* Channel Throughput Level */ + u8 fifo_id; /* XYMF FIFO index */ =20 u32 tr_trigger_type; unsigned long tx_flags; @@ -434,6 +478,7 @@ struct udma_chan { char *name; =20 struct udma_bchan *bchan; + struct udma_tchan *chan; struct udma_tchan *tchan; struct udma_rchan *rchan; struct udma_rflow *rflow; @@ -503,51 +548,33 @@ static inline void udma_update_bits(void __iomem *bas= e, int reg, writel(tmp, base + reg); } =20 -/* TCHANRT */ -static inline u32 udma_tchanrt_read(struct udma_chan *uc, int reg) -{ - if (!uc->tchan) - return 0; - return udma_read(uc->tchan->reg_rt, reg); -} - -static inline void udma_tchanrt_write(struct udma_chan *uc, int reg, u32 v= al) -{ - if (!uc->tchan) - return; - udma_write(uc->tchan->reg_rt, reg, val); +#define _UDMA_REG_ACCESS(channel) \ +static inline u32 udma_##channel##rt_read(struct udma_chan *uc, int reg) \ +{ \ + if (!uc->channel) \ + return 0; \ + return udma_read(uc->channel->reg_rt, reg); \ +} \ +\ +static inline void udma_##channel##rt_write(struct udma_chan *uc, int reg,= u32 val) \ +{ \ + if (!uc->channel) \ + return; \ + udma_write(uc->channel->reg_rt, reg, val); \ +} \ +\ +static inline void udma_##channel##rt_update_bits(struct udma_chan *uc, in= t reg, \ + u32 mask, u32 val) \ +{ \ + if (!uc->channel) \ + return; \ + udma_update_bits(uc->channel->reg_rt, reg, mask, val); \ } =20 -static inline void udma_tchanrt_update_bits(struct udma_chan *uc, int reg, - u32 mask, u32 val) -{ - if (!uc->tchan) - return; - udma_update_bits(uc->tchan->reg_rt, reg, mask, val); -} - -/* RCHANRT */ -static inline u32 udma_rchanrt_read(struct udma_chan *uc, int reg) -{ - if (!uc->rchan) - return 0; - return udma_read(uc->rchan->reg_rt, reg); -} - -static inline void udma_rchanrt_write(struct udma_chan *uc, int reg, u32 v= al) -{ - if (!uc->rchan) - return; - udma_write(uc->rchan->reg_rt, reg, val); -} - -static inline void udma_rchanrt_update_bits(struct udma_chan *uc, int reg, - u32 mask, u32 val) -{ - if (!uc->rchan) - return; - udma_update_bits(uc->rchan->reg_rt, reg, mask, val); -} +_UDMA_REG_ACCESS(chan); +_UDMA_REG_ACCESS(bchan); +_UDMA_REG_ACCESS(tchan); +_UDMA_REG_ACCESS(rchan); =20 static inline dma_addr_t udma_curr_cppi5_desc_paddr(struct udma_desc *d, int idx) diff --git a/include/linux/soc/ti/k3-ringacc.h b/include/linux/soc/ti/k3-ri= ngacc.h index 4b6ec925e2f2d..deb2c569ed14e 100644 --- a/include/linux/soc/ti/k3-ringacc.h +++ b/include/linux/soc/ti/k3-ringacc.h @@ -10,6 +10,9 @@ =20 #include =20 +#define K3_RINGACC_RT_INT_STATUS_COMPLETE BIT(0) +#define K3_RINGACC_RT_INT_STATUS_TR BIT(2) + struct device_node; =20 /** --=20 2.54.0 From nobody Tue Sep 29 08:26:17 2026 Received: from mx0b-0002e601.pphosted.com (mx0b-0002e601.pphosted.com [148.163.154.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E5E6375F81; Mon, 28 Sep 2026 03:00:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.154.28 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564411; cv=fail; b=LNDJ/1ATrOZsqCcH1TkEwryursesiFfVl4hrWVDqujAYl12SL2yhtQ+GhBUw+UKJ9JJqDOoImHUahSguL8Z8qLYcb1NRyKiJp4LFYw2ruQM/2vEfJdEwMhqp4Jg0L7aUfU+6+aV1Q1x6zGg7GLJedxwNeCWkej+IPFx7+9d8l+4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564411; c=relaxed/simple; bh=Do7nquElUjCNjxHKKJz06ikWEBbk7dhAX7liOkypM60=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=t/83BBQvTErrnK+LT05dfYvPKdasrz3f1Qg2RaExkJrYLcabSUplfWz2vaj2U3TqRsgxMMlx2iuXRy4tSmMM04yEzug7AFT+/QuoEnAj0kOpMVXkr08koODRd29/4fPg3cd8dfhY4GVWQ3UyW8FdeD6+oqPz0QxQDQLAh/KOjJs= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=HST2iMyO; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=f1l3iM6z; arc=fail smtp.client-ip=148.163.154.28 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="HST2iMyO"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="f1l3iM6z" Received: from pps.filterd (m0374956.ppops.net [127.0.0.1]) by mx0b-0002e601.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68RKXrrw2283895; Sun, 27 Sep 2026 21:59:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=o5ObAcdStGiVBEZbyTMbr7HN9Rmm0jREHAxzzpZXU AE=; b=HST2iMyO6fG8w9LvFcehrbjrpgOBuTSZkh8uOdXUJUX3JGs0CzYwtpCwm lKYsqB8+P9VQKJANJjGdX4Y75RPpTOvIXhFq3hP0ZlYahjj4f/VBaQJgfytq9Egy V7jE5hnLxzCnqH/2NWWrkYmIQk2gfWyeeH30N/EwW9czDWWncsZQMI4rfJE0Meju DY6IfWRQQEtVipHAJErnDxqkEdi5e1SiRZkjfYhVUF4D+5GzsKHPpgpzeEquHxhk 1P2zAbajM64M6g3iflAUPF0Dt1rGFYm0TBsP7GvO7dzyENcl6h6zMBAnBeQX61Cj 9Cx1TBu8tM6XSTb/SGfoYwBrZovwg== Received: from ph8pr06cu001.outbound.protection.outlook.com (mail-westus3azon11012003.outbound.protection.outlook.com [40.107.209.3]) by mx0b-0002e601.pphosted.com (PPS) with ESMTPS id 4gxw6nug30-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Sun, 27 Sep 2026 21:59:53 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=GsR9l30HHlJ4K6NQdEVR92a19dBpMKydIxQ4bmem6frDgxyKLeQYXA7IphOqLIkTJmD23/mwBzpWy469TnTsgAL/wHmDf2gsoypWUCHNvKlz5sh7HIhB2JM3zxrfw0SghoqzCnVvN8CK66zgR8TnQozBU8Yckdfkuu7i9sh8SIDokXGEzWFfrInQ3jary1iMiDBD6q6F3QvlYj1nt6cHmmIpZw2scAY33C7R8iG2m57NmdqboXXPoqwyrPv2SnB4V7DIxDO1u3r+e/DcH4tb4Ja6fys8GdL4scR4CxlPNlPQi2ea6phjRN/JH6l3VOU15QzMLZudL3bM4gFZ0/kwog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=o5ObAcdStGiVBEZbyTMbr7HN9Rmm0jREHAxzzpZXUAE=; b=f+6tkZAcKdaUrAU9vLvuO/LGBMFwMZ1cCGATKLDOGrkbZg4etwq4s7ZjP6K44xNdJbF+Ldal8Cr02dJV2+Sj6+NG/N4eFnIsZxTDcQp9jyfMLs4/aU8NjesDsm+nf/jx3C442HeUaiRKRD5H7otzjirKpixB+9PwYwb2Ipgy8sG15XzLQREs052XS4VWwu5levKRCujiX8VY2DY+Pa1SXbMgMu1EEtGxH8LzJ1oiZbfzlUqIz0K4VwwNPvrykLYL1ziLzng0ft4c4KzIZHnDtwnRu/0pyBAp6kQLovX8Gp052d0Z/MaPK0pMAIBDVTn6NMSO9wFRONil6+ORkSlOrw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.21.194) smtp.rcpttodomain=nxp.com smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=o5ObAcdStGiVBEZbyTMbr7HN9Rmm0jREHAxzzpZXUAE=; b=f1l3iM6zHKd8zAQfjGSa2Daowf6Qqf6W6H/cJ7i15v/w6zQvnCRwq2T3/fsplB51UPJrZasrx4sov5D/BgbC8v2Oho93i7NJq4kKkQkTmDzE8gDootyWur6dPKU02DOLxUhKKfyI8yG7fpiZkhulI3rwbnup+88I13EcFlELY2o= Received: from DS1PR04CA0012.namprd04.prod.outlook.com (2603:10b6:8:44f::7) by IA1PR10MB6711.namprd10.prod.outlook.com (2603:10b6:208:418::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.7; Mon, 28 Sep 2026 02:59:48 +0000 Received: from DS2PEPF000061C4.namprd02.prod.outlook.com (2603:10b6:8:44f:cafe::47) by DS1PR04CA0012.outlook.office365.com (2603:10b6:8:44f::7) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.451.23 via Frontend Transport; Mon, 28 Sep 2026 02:59:47 +0000 X-MS-Exchange-Authentication-Results: mx.microsoft.com 1; spf=pass (sender IP is 198.47.21.194) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.21.194 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.21.194; helo=flwvzet200.ext.ti.com; pr=C Received: from flwvzet200.ext.ti.com (198.47.21.194) by DS2PEPF000061C4.mail.protection.outlook.com (10.167.23.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Mon, 28 Sep 2026 02:59:46 +0000 Received: from DFLE208.ent.ti.com (10.64.6.66) by flwvzet200.ext.ti.com (10.248.192.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:59:18 -0500 Received: from DFLE215.ent.ti.com (10.64.6.73) by DFLE208.ent.ti.com (10.64.6.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:59:18 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE215.ent.ti.com (10.64.6.73) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45 via Frontend Transport; Sun, 27 Sep 2026 21:59:18 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [10.24.51.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 68S2vqqO2256662; Sun, 27 Sep 2026 21:59:14 -0500 From: Sai Sree Kartheek Adivi To: , , , , , , , , , , , , , CC: , Subject: [PATCH v10 17/19] dmaengine: ti: k3-udma-v2: Add support for PKTDMA V2 Date: Mon, 28 Sep 2026 08:26:23 +0530 Message-ID: <20260928025749.1055383-18-s-adivi@ti.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260928025749.1055383-1-s-adivi@ti.com> References: <20260928025749.1055383-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF000061C4:EE_|IA1PR10MB6711:EE_ X-MS-Office365-Filtering-Correlation-Id: 93e39810-5b16-4779-df84-08df1d0c8dbe X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|7416014|82310400026|1800799024|36860700016|921020|6133799003|56012099006|10067099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: AS8WmCiFIBTCO6X8IBDK7zMoyr+6+cz9iHn2Oxa9lBfBjJaWlRjlG4WidJdTnVjVdlu/K1ENuyZC0jGm2t9AH139tnXqqKB7uLumBDPbEm3y7oAahR7vtXodw1TF9YgYq2H1DAh8EvgPQuBGfo1l5hZFDrJWKqFTh8PJEVZLn+x+NPU3l1B/FfPguiiBiky6HMhoRfJxVDFYYs15TWl75if7xFjKcnXr2p9AoeNQThx15NlA5YZCaQoa/QmvmBsJ9ZFMypY2cVP8H6hcsGLLlgpqEXEzXSJYQyGIerCKA3+CMEbf4z2sBiSKQYTx5iHFcT9XPX2+f840BROzdMcLdeLkclKxmSQmoY+9YhxeKq9Dm2dgmpNp5Opfg3946xlQ5A/cJFohePM8kPNg6r9REVgilavbugSegYbYNCfJG88QtSfuC670tDBxEqN6I79oQvZMKMLdeUlLoN9xxk5yzZskObTwlXYXCrDfQzhUi4rti5HoeIbI9MzWjDSlHNatgC1i9NrizG0Fq1vDIuh7fTWyI+2EIKF/+qm2GsUobM5oSwLDlwp5/IzLS/tVAO0/YC/ISiBU7wOR9BJPVD9ZIvRBXZ5OAX5HtM08XcJ4vR/2ZRZhZ00DwIEs8eRIATqydDuN/nhGD5x2msmsXTtnvkbcRTruqDWbcbK9DpXi2+MZ0s4XniWCc25ACKl84tHX58FHLU/kAG5sj0XysDaHMKIJwbvLP5UNDr/ieN/N+7et636i4uGndArQgWuz4X26 X-Forefront-Antispam-Report: CIP:198.47.21.194;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:flwvzet200.ext.ti.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230040)(23010399003)(376014)(7416014)(82310400026)(1800799024)(36860700016)(921020)(6133799003)(56012099006)(10067099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4QH69KefIL0Ax4p9DnhM6kJDNEe5pLNmYVWDFdbqu75fi5zWlFccDZZ8uhcVULMbl2QsON/gJOzR9R8LDXEK84qvP4cqlD7O53p4f7XC31D705jyu5mXUjZ2lg5EyV82n2Dbs6I9mHzCDHAjsZr0YbgzpK7OA/llLDoOSfJixMJOEaeXjMnbrdxwRZ7qAI/632xEBWSukx0kBCS2fx1eQPr4yvhZyo8xKvS0iI0IrkJbz8eeqFBrLJScJFQuZkt/CK0OFpAv0kefMCuVWt9U5Zz6pNRj4/90EBE9QBP9x+RCbEzHPOwfDRxuQy5PpHt2QnvOVN4muaxHgHGeIx4+9C0rCR0Ztz3iYKXwGVDW9r/yKHI1fvvgO5/1EPmw/EylxYaeaVPfp1qGvHpbK9XEGCtD4TFBHP2gNXaXlGidPdMXePi/wxo1QSf6BWorIYCU X-Exchange-RoutingPolicyChecked: aj1sYbiqWVkvY99o9wHUshuxhI5ecD2xcoecY7fOeZr7wLTAdPtF0LMYudsJESmSIJqbD75LESkfMIib8m/tCmk2U5rSBtkNBevKQnZhnoKNT6L20F9TRMdbceNNMZa0lKx8VD5TD6OT1yq8x842cPv24t32K1D5zAjZhy9YUambGHjs5GXWJxYtj45bzbEo84NK1lTIzHiSfjsbRMs2cGSJXOteTq14v4+R3gv/+IiVPIzJoK6on+zEwJCU9wGsi2pfdkw0O7p+EDcICFPAc223ul5afpNxk4vEmiRU3zP5bmK5/zk62atA6+TkDVUBAE09iizCSfPqZ0eSIwKdQg== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 02:59:46.3923 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 93e39810-5b16-4779-df84-08df1d0c8dbe X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF000061C4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR10MB6711 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX6IRZsmacqTd8 Gg1rilx3ogBrfFQbDOJ9KgcS58ZNWQ55ZSxNQiNuhlmK2PzFcr5CFVwzl0qHISPylkwpixDISdy EC2rbOLQHuZEYjYy+SZTtZCX8GNN6JQ= X-Authority-Analysis: v=2.4 cv=dbkVTnXe c=1 sm=1 tr=0 ts=6ab9d829 cx=c_pps a=9H9ADJ10uJ0pYmVeXPB43g==:117 a=iwqwCZQqcuTv3JOpYdM7/Q==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=VdqzKS8jKosA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=jwouBfj2j3NM8CExmVVE:22 a=sozttTNsAAAA:8 a=s8P6Qq-zSQWvIvMPkfEA:9 X-Proofpoint-ORIG-GUID: D58o6zC2iecsZkxMiJeJmyFkSqYkaEWh X-Proofpoint-GUID: D58o6zC2iecsZkxMiJeJmyFkSqYkaEWh X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX7QZer9UAxNy0 Ai7p9XPPpWtqI/nS18Ps5/tyEt4BtmPlgNJYf22U9QhHom82+8zhTEuxGXIT5XgYu2FGGT89eim wJ49/IN1cR44IGNn0ee5x+AtGDBfHeSeeYDTkPiwYUnannvJkeWjJJJDwxy4HYXy2+pHCtzGwYJ lAHEXV1adN7qzxEBRxWXIhO0f1oC64PqP+DV37/rRpqOrPCXh3w1e7MEv1RN8W8WwUAJBB7uwTj sOwJEW5+QW98sV1n/jVxJgKlvTAQmoBpSHZi2Tvh+MXqtByjQIRABpYkRXz3HnmNTH7Aj25ybXo tCoHBLaEAZAJNDiVXHwhJnLGoNio3izZXcdH1XQJgMsL7aUSq/qSFPsaGZE3/o1Y51bK6QHxMgr oMSfe6axtRDKUQ4nGJSkb8MmDxGX0P7IUUkW3FKJTrCGYICIITzV/5AfP2GrurNk4s/CPOoq89G CtMLPpx/7LcekTSn6HQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 impostorscore=0 adultscore=0 bulkscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280011 Content-Type: text/plain; charset="utf-8" The PKTDMA V2 is different than the existing PKTDMA supported by the k3-udma driver. The changes in PKTDMA V2 are: - Autopair: There is no longer a need for PSIL pair and AUTOPAIR bit needs to set in the RT_CTL register. - Static channel mapping: Each channel is mapped to a single peripheral. - Direct IRQs: There is no INT-A and interrupt lines from DMA are directly connected to GIC. - Remote side configuration handled by DMA. So no need to write to PEER registers to START / STOP / PAUSE / TEARDOWN. - Unified Channel Space: Tx and Rx channels share a single register space. Each channel index is specifically fixed in hardware as either Tx or Rx in an interleaved manner. Signed-off-by: Sai Sree Kartheek Adivi --- drivers/dma/ti/k3-udma-common.c | 35 +++-- drivers/dma/ti/k3-udma-glue.c | 23 ++++ drivers/dma/ti/k3-udma-private.c | 22 ++- drivers/dma/ti/k3-udma-v2.c | 222 +++++++++++++++++++++++++++++-- drivers/dma/ti/k3-udma.h | 3 + 5 files changed, 278 insertions(+), 27 deletions(-) diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-commo= n.c index 30cb8044ff100..5fa3a7b8d2026 100644 --- a/drivers/dma/ti/k3-udma-common.c +++ b/drivers/dma/ti/k3-udma-common.c @@ -2465,9 +2465,16 @@ static int pktdma_setup_resources(struct udma_dev *u= d) ud->tchan_map =3D devm_bitmap_zalloc(dev, ud->tchan_cnt, GFP_KERNEL); ud->tchans =3D devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), GFP_KERNEL); - ud->rchan_map =3D devm_bitmap_zalloc(dev, ud->rchan_cnt, GFP_KERNEL); - ud->rchans =3D devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), - GFP_KERNEL); + if (ud->match_data->version =3D=3D K3_UDMA_V1) { + ud->rchan_map =3D devm_bitmap_zalloc(dev, ud->rchan_cnt, GFP_KERNEL); + ud->rchans =3D devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), + GFP_KERNEL); + } else { + ud->rchan_map =3D ud->tchan_map; + ud->rchans =3D ud->tchans; + ud->chan_map =3D ud->tchan_map; + ud->chans =3D ud->tchans; + } ud->rflow_in_use =3D devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt), sizeof(unsigned long), GFP_KERNEL); @@ -2566,13 +2573,21 @@ int k3_udma_setup_resources(struct udma_dev *ud) } break; case DMA_TYPE_PKTDMA: - dev_info(dev, - "Channels: %d (tchan: %u, rchan: %u)\n", - ch_count, - ud->tchan_cnt - bitmap_weight(ud->tchan_map, - ud->tchan_cnt), - ud->rchan_cnt - bitmap_weight(ud->rchan_map, - ud->rchan_cnt)); + if (ud->match_data->version =3D=3D K3_UDMA_V1) { + dev_info(dev, + "Channels: %d (tchan: %u, rchan: %u)\n", + ch_count, + ud->tchan_cnt - bitmap_weight(ud->tchan_map, + ud->tchan_cnt), + ud->rchan_cnt - bitmap_weight(ud->rchan_map, + ud->rchan_cnt)); + } else { + dev_info(dev, + "Channels: %d (tchan + rchan: %u)\n", + ch_count, + ud->chan_cnt - bitmap_weight(ud->chan_map, + ud->chan_cnt)); + } break; default: break; diff --git a/drivers/dma/ti/k3-udma-glue.c b/drivers/dma/ti/k3-udma-glue.c index 70eaf7ee57e68..996c130b10f4a 100644 --- a/drivers/dma/ti/k3-udma-glue.c +++ b/drivers/dma/ti/k3-udma-glue.c @@ -166,6 +166,29 @@ static int of_k3_udma_glue_parse_chn(struct device_nod= e *chn_np, goto out_put_spec; =20 thread_id =3D dma_spec.args[0]; + + /* + * V2 PKTDMA DT specifiers encode the hardware flow/channel ID in + * args[0] rather than the PSI-L thread ID used by V1. Resolve the + * PSI-L thread ID before the common path checks the direction bit. + */ + if (common->udmax->match_data->version =3D=3D K3_UDMA_V2 && + xudma_is_pktdma(common->udmax)) { + struct psil_endpoint_config *ep_cfg; + u32 psil_thread_id; + bool dev_to_mem; + + ep_cfg =3D psil_get_ep_config_by_id(thread_id, true, + &psil_thread_id, &dev_to_mem); + if (IS_ERR(ep_cfg)) { + dev_err(common->dev, + "No PSI-L config for flow %u\n", thread_id); + ret =3D PTR_ERR(ep_cfg); + goto out_put_spec; + } + thread_id =3D psil_thread_id; + } + if (dma_spec.args_count =3D=3D 2) { if (dma_spec.args[1] > 2 && !xudma_is_pktdma(common->udmax)) { dev_err(common->dev, "Invalid channel atype: %u\n", diff --git a/drivers/dma/ti/k3-udma-private.c b/drivers/dma/ti/k3-udma-priv= ate.c index 44c097fff5ee6..525155d3bb513 100644 --- a/drivers/dma/ti/k3-udma-private.c +++ b/drivers/dma/ti/k3-udma-private.c @@ -174,16 +174,30 @@ EXPORT_SYMBOL(xudma_is_pktdma); =20 int xudma_pktdma_tflow_get_irq(struct udma_dev *ud, int udma_tflow_id) { - const struct udma_oes_offsets *oes =3D &ud->soc_data->oes; + if (ud->match_data->version =3D=3D K3_UDMA_V1) { + const struct udma_oes_offsets *oes =3D &ud->soc_data->oes; =20 - return msi_get_virq(ud->dev, udma_tflow_id + oes->pktdma_tchan_flow); + return msi_get_virq(ud->dev, udma_tflow_id + oes->pktdma_tchan_flow); + } + struct platform_device *pdev =3D to_platform_device(ud->dev); + char irq_name[10]; + + snprintf(irq_name, sizeof(irq_name), "tx-%u", udma_tflow_id); + return platform_get_irq_byname(pdev, irq_name); } EXPORT_SYMBOL(xudma_pktdma_tflow_get_irq); =20 int xudma_pktdma_rflow_get_irq(struct udma_dev *ud, int udma_rflow_id) { - const struct udma_oes_offsets *oes =3D &ud->soc_data->oes; + if (ud->match_data->version =3D=3D K3_UDMA_V1) { + const struct udma_oes_offsets *oes =3D &ud->soc_data->oes; + + return msi_get_virq(ud->dev, udma_rflow_id + oes->pktdma_rchan_flow); + } + struct platform_device *pdev =3D to_platform_device(ud->dev); + char irq_name[10]; =20 - return msi_get_virq(ud->dev, udma_rflow_id + oes->pktdma_rchan_flow); + snprintf(irq_name, sizeof(irq_name), "rx-%u", udma_rflow_id); + return platform_get_irq_byname(pdev, irq_name); } EXPORT_SYMBOL(xudma_pktdma_rflow_get_irq); diff --git a/drivers/dma/ti/k3-udma-v2.c b/drivers/dma/ti/k3-udma-v2.c index ba3042e866cac..a71471aa7707a 100644 --- a/drivers/dma/ti/k3-udma-v2.c +++ b/drivers/dma/ti/k3-udma-v2.c @@ -578,7 +578,7 @@ static int udma_v2_alloc_rx_resources(struct udma_chan = *uc) =20 rflow =3D uc->rflow; if (ud->tflow_cnt) - fd_ring_id =3D ud->tflow_cnt + rflow->id; + fd_ring_id =3D rflow->id; else fd_ring_id =3D uc->rchan->id; ret =3D k3_ringacc_request_rings_pair(ud->ringacc, fd_ring_id, -1, @@ -770,6 +770,148 @@ static int bcdma_v2_alloc_chan_resources(struct dma_c= han *chan) return ret; } =20 +static int pktdma_v2_alloc_chan_resources(struct dma_chan *chan) +{ + struct udma_chan *uc =3D to_udma_chan(chan); + struct udma_dev *ud =3D to_udma_dev(chan->device); + struct platform_device *pdev =3D to_platform_device(ud->dev); + char irq_name[10]; + u32 irq_ring_idx; + int ret; + + /* + * Make sure that the completion is in a known state: + * No teardown, the channel is idle + */ + reinit_completion(&uc->teardown_completed); + complete_all(&uc->teardown_completed); + uc->state =3D UDMA_CHAN_IS_IDLE; + + switch (uc->config.dir) { + case DMA_MEM_TO_DEV: + /* Slave transfer synchronized - mem to dev (TX) transfer */ + dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__, + uc->id); + + ret =3D udma_v2_alloc_tx_resources(uc); + if (ret) { + uc->config.remote_thread_id =3D -1; + return ret; + } + + uc->config.src_thread =3D ud->psil_base + uc->tchan->id; + uc->config.dst_thread =3D uc->config.remote_thread_id; + uc->config.dst_thread |=3D K3_PSIL_DST_THREAD_ID_OFFSET; + + irq_ring_idx =3D uc->config.mapped_channel_id; + break; + case DMA_DEV_TO_MEM: + /* Slave transfer synchronized - dev to mem (RX) transfer */ + dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__, + uc->id); + + ret =3D udma_v2_alloc_rx_resources(uc); + if (ret) { + uc->config.remote_thread_id =3D -1; + return ret; + } + + uc->config.src_thread =3D uc->config.remote_thread_id; + uc->config.dst_thread =3D (ud->psil_base + uc->rchan->id) | + K3_PSIL_DST_THREAD_ID_OFFSET; + + irq_ring_idx =3D uc->config.mapped_channel_id; + udma_write(uc->rflow->reg_rt, UDMA_RX_FLOWRT_RFA, BIT(28)); + break; + default: + /* Can not happen */ + dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n", + __func__, uc->id, uc->config.dir); + return -EINVAL; + } + + /* check if the channel configuration was successful */ + if (ret) + goto err_res_free; + + if (udma_is_chan_running(uc)) { + dev_warn(ud->dev, "chan%d: is running!\n", uc->id); + ud->reset_chan(uc, false); + if (udma_is_chan_running(uc)) { + dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); + ret =3D -EBUSY; + goto err_res_free; + } + } + + uc->dma_dev =3D dmaengine_get_dma_device(chan); + uc->hdesc_pool =3D dma_pool_create(uc->name, uc->dma_dev, + uc->config.hdesc_size, ud->desc_align, + 0); + if (!uc->hdesc_pool) { + dev_err(ud->ddev.dev, + "Descriptor pool allocation failed\n"); + uc->use_dma_pool =3D false; + ret =3D -ENOMEM; + goto err_res_free; + } + + uc->use_dma_pool =3D true; + + uc->psil_paired =3D true; + + INIT_DELAYED_WORK(&uc->tx_drain.work, udma_check_tx_completion); + + if (uc->config.dir =3D=3D DMA_MEM_TO_DEV) + snprintf(irq_name, sizeof(irq_name), "tx-%u", irq_ring_idx); + else + snprintf(irq_name, sizeof(irq_name), "rx-%u", irq_ring_idx); + uc->irq_num_ring =3D platform_get_irq_byname(pdev, irq_name); + if (uc->irq_num_ring < 0) { + ret =3D uc->irq_num_ring; + goto err_res_free; + } + + ret =3D request_irq(uc->irq_num_ring, udma_v2_ring_irq_handler, + IRQF_SHARED | IRQF_TRIGGER_HIGH, uc->name, uc); + + if (ret) { + dev_err(ud->dev, "chan%d: ring irq request failed\n", uc->id); + goto err_irq_free; + } + + uc->irq_num_udma =3D 0; + + udma_reset_rings(uc); + + if (uc->tchan) + dev_dbg(ud->dev, + "chan%d: tchan%d, tflow%d, Remote thread: 0x%04x\n", + uc->id, uc->tchan->id, uc->tchan->tflow_id, + uc->config.remote_thread_id); + else if (uc->rchan) + dev_dbg(ud->dev, + "chan%d: rchan%d, rflow%d, Remote thread: 0x%04x\n", + uc->id, uc->rchan->id, uc->rflow->id, + uc->config.remote_thread_id); + return 0; + +err_irq_free: + uc->irq_num_ring =3D 0; +err_res_free: + udma_free_tx_resources(uc); + udma_free_rx_resources(uc); + + udma_reset_uchan(uc); + + if (uc->use_dma_pool) { + dma_pool_destroy(uc->hdesc_pool); + uc->use_dma_pool =3D false; + } + + return ret; +} + static enum dma_status udma_v2_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate) @@ -1032,11 +1174,34 @@ static struct udma_match_data bcdma_v2_am62l_data = =3D { .rchan_cnt =3D 128, }; =20 +static struct udma_match_data pktdma_v2_am62l_data =3D { + .type =3D DMA_TYPE_PKTDMA, + .version =3D K3_UDMA_V2, + .psil_base =3D 0x1000, + .enable_memcpy_support =3D false, /* PKTDMA does not support MEM_TO_MEM */ + .flags =3D UDMA_FLAGS_J7_CLASS, + .statictr_z_mask =3D GENMASK(23, 0), + .burst_size =3D { + TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES, /* Normal Channels */ + 0, /* No H Channels */ + 0, /* No UH Channels */ + }, + .tchan_cnt =3D 97, + .rchan_cnt =3D 97, + .chan_cnt =3D 97, + .tflow_cnt =3D 112, + .rflow_cnt =3D 112, +}; + static const struct of_device_id udma_of_match[] =3D { { .compatible =3D "ti,am62l-dmss-bcdma", .data =3D &bcdma_v2_am62l_data, }, + { + .compatible =3D "ti,am62l-dmss-pktdma", + .data =3D &pktdma_v2_am62l_data, + }, { /* Sentinel */ }, }; =20 @@ -1055,15 +1220,23 @@ static int udma_v2_get_mmrs(struct platform_device = *pdev, struct udma_dev *ud) if (IS_ERR(ud->mmrs[V2_MMR_GCFG])) return PTR_ERR(ud->mmrs[V2_MMR_GCFG]); =20 - ud->bchan_cnt =3D ud->match_data->bchan_cnt; - /* There are no tchan and rchan in BCDMA_V2. + /* There are no tchan and rchan in BCDMA_V2 and PKTDMA_V2. * Duplicate chan as tchan and rchan to keep the common code - * in k3-udma-common.c functional for BCDMA_V2. + * in k3-udma-common.c functional. */ - ud->chan_cnt =3D ud->match_data->chan_cnt; - ud->tchan_cnt =3D ud->match_data->chan_cnt; - ud->rchan_cnt =3D ud->match_data->chan_cnt; - ud->rflow_cnt =3D ud->chan_cnt; + if (ud->match_data->type =3D=3D DMA_TYPE_BCDMA) { + ud->bchan_cnt =3D ud->match_data->bchan_cnt; + ud->chan_cnt =3D ud->match_data->chan_cnt; + ud->tchan_cnt =3D ud->match_data->chan_cnt; + ud->rchan_cnt =3D ud->match_data->chan_cnt; + ud->rflow_cnt =3D ud->chan_cnt; + } else if (ud->match_data->type =3D=3D DMA_TYPE_PKTDMA) { + ud->chan_cnt =3D ud->match_data->chan_cnt; + ud->tchan_cnt =3D ud->match_data->tchan_cnt; + ud->rchan_cnt =3D ud->match_data->rchan_cnt; + ud->tflow_cnt =3D ud->match_data->tflow_cnt; + ud->rflow_cnt =3D ud->match_data->rflow_cnt; + } =20 for (i =3D 1; i < V2_MMR_LAST; i++) { if (i =3D=3D V2_MMR_BCHANRT && ud->bchan_cnt =3D=3D 0) @@ -1117,6 +1290,7 @@ static int udma_v2_probe(struct platform_device *pdev) ud->reset_chan =3D udma_v2_reset_chan; ud->decrement_byte_counters =3D udma_v2_decrement_byte_counters; ud->bcdma_setup_sci_resources =3D NULL; + ud->pktdma_setup_sci_resources =3D NULL; =20 ret =3D udma_v2_get_mmrs(pdev, ud); if (ret) @@ -1124,7 +1298,17 @@ static int udma_v2_probe(struct platform_device *pde= v) =20 struct k3_ringacc_init_data ring_init_data =3D {0}; =20 - ring_init_data.num_rings =3D ud->bchan_cnt + ud->chan_cnt; + if (ud->match_data->type =3D=3D DMA_TYPE_BCDMA) { + ring_init_data.num_rings =3D ud->bchan_cnt + ud->chan_cnt; + } else if (ud->match_data->type =3D=3D DMA_TYPE_PKTDMA) { + ring_init_data.num_rings =3D ud->rflow_cnt; + + ud->rflow_rt =3D devm_platform_ioremap_resource_byname(pdev, "ringrt"); + if (IS_ERR(ud->rflow_rt)) + return PTR_ERR(ud->rflow_rt); + + ring_init_data.base_rt =3D ud->rflow_rt; + } =20 ud->ringacc =3D k3_ringacc_dmarings_init(pdev, &ring_init_data); =20 @@ -1133,8 +1317,10 @@ static int udma_v2_probe(struct platform_device *pde= v) =20 dma_cap_set(DMA_SLAVE, ud->ddev.cap_mask); =20 - dma_cap_set(DMA_CYCLIC, ud->ddev.cap_mask); - ud->ddev.device_prep_dma_cyclic =3D udma_prep_dma_cyclic; + if (ud->match_data->type !=3D DMA_TYPE_PKTDMA) { + dma_cap_set(DMA_CYCLIC, ud->ddev.cap_mask); + ud->ddev.device_prep_dma_cyclic =3D udma_prep_dma_cyclic; + } =20 ud->ddev.device_config =3D udma_slave_config; ud->ddev.device_prep_slave_sg =3D udma_prep_slave_sg; @@ -1148,8 +1334,18 @@ static int udma_v2_probe(struct platform_device *pde= v) ud->ddev.dbg_summary_show =3D udma_dbg_summary_show; #endif =20 - ud->ddev.device_alloc_chan_resources =3D - bcdma_v2_alloc_chan_resources; + switch (ud->match_data->type) { + case DMA_TYPE_BCDMA: + ud->ddev.device_alloc_chan_resources =3D + bcdma_v2_alloc_chan_resources; + break; + case DMA_TYPE_PKTDMA: + ud->ddev.device_alloc_chan_resources =3D + pktdma_v2_alloc_chan_resources; + break; + default: + return -EINVAL; + } =20 ud->ddev.device_free_chan_resources =3D udma_free_chan_resources; =20 diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h index b2e5455b1087e..2a9686f7a09bc 100644 --- a/drivers/dma/ti/k3-udma.h +++ b/drivers/dma/ti/k3-udma.h @@ -27,8 +27,11 @@ #define UDMA_RX_FLOW_ID_FW_OES_REG 0x80 #define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88 =20 +#define UDMA_RX_FLOWRT_RFA 0x8 + /* BCHANRT/TCHANRT/RCHANRT registers */ #define UDMA_CHAN_RT_CTL_REG 0x0 +#define UDMA_CHAN_RT_CFG_REG 0x4 #define UDMA_CHAN_RT_SWTRIG_REG 0x8 #define UDMA_CHAN_RT_STDATA_REG 0x80 =20 --=20 2.54.0 From nobody Tue Sep 29 08:26:17 2026 Received: from mx0a-0002e601.pphosted.com (mx0a-0002e601.pphosted.com [148.163.150.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4036030594F; Mon, 28 Sep 2026 03:00:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.150.75 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564403; cv=fail; b=N4e+FprmDvRg8wjtbb96DVOu39PbZzTEfOYZtRiA5+On4cIzNrhQxYzR+A4CE13Q+upOqzUorFpHKvkPMOpOogEd9U7UrZi8pH6YoXEADzHgjfyL2oWS5OCZoE85iUp2N3Q1VM9KNL2Ki71qbM5vwomJXUmDrjViB681vWo61Ig= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564403; c=relaxed/simple; bh=OwjYwFqSFCd9saDH1/jYqBu3oZUbBDlB0ryNvJXz1Xw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WVt3zYWSrXAFL4Wpgh5CO0vpK77/CZOWClK7YNzJRzeJ57O58/wj4ofgIvoG2Q7VkpbXPfQ/nj9fIhaEWug5dqlj9Tn++bbTY4o26YcQ/VwV6VqeyK7c6tUeyx3hiFWgsPBSxsu++K/MsaGCmKzwOFPWzcCzDUYjI+Wj1xATIME= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=DBm0hXjT; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=M0DK/tWi; arc=fail smtp.client-ip=148.163.150.75 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="DBm0hXjT"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="M0DK/tWi" Received: from pps.filterd (m0384305.ppops.net [127.0.0.1]) by m0384305.ppops.net (8.18.1.11/8.18.1.11) with ESMTP id 68RNi5sG3706846; Sun, 27 Sep 2026 21:59:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=CBC3W2Sz8Ol7rD66X3Ume4mUVMmNDlyyyBOXPTW0k e4=; b=DBm0hXjTN6+m//nfIdEVqUZGEWdor1BtSTxUgV4an+tKf1SZuT5G1J3bx XPYj+AWme7zhkddWolIZFfmXgO/bxBQmgfJkiIS7DJ4qr0jlb6ZNKDTnKgDe82mr hK1T3jADCzoBa/NUSqQ2pk96C0fXnuTpDmqMWDCIHRMBVDWcH77rqrobHtJYyd7o ugRL81XtC50cCjoED6qhPxuhlDHBugi78GIY7CJNu20ca2ZMX0F2mKTizvKXwa4k EEqqJ30Zfr7V09h1Pf/VOo6vkf6GFpO59QhhsqVZ5hQOBOB4Ra96pQ+IqfwVMuD4 Jrhv1jqldquux9ds+/5417CjP3oEQ== Received: from bn1pr04cu002.outbound.protection.outlook.com (mail-eastus2azon11010064.outbound.protection.outlook.com [52.101.56.64]) by m0384305.ppops.net (PPS) with ESMTPS id 4gy00nb1u2-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Sun, 27 Sep 2026 21:59:50 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=RMjzGZ69O2GV+viwt8PYySRq+mmSO9iTHFNNGAuVGHe/9gbqa++k+GpyAKOKxWkwn3XkQMpO5koc5uKmFh7pnaPP7/g7JNIEZb9Xkm3+aXZbC0magRIja66zHMajGWWvWl0bu6bBmLylD3wHJgpejeWDOPxkTOYsVOCPAHWyOKpcQkHryo6MS0l32DIkuycLJ73NooogADfLw0OyDFsTj+kMhgtFF3sJUqyfs89Pxi0Myvb5bM6FBhF9aKA+q6UtXsPi/wwcA/nP/+h8jT7OYhW2cKBLumiz9vN2x/88ru1Yp3Mto4ByUA1lRr4dj7j2nrJcFXCV9ZL9CcQhQKYolw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=CBC3W2Sz8Ol7rD66X3Ume4mUVMmNDlyyyBOXPTW0ke4=; b=XtXTcxxwytK7NST0uNQDHd3EShZu89CpFv9rnfjJsInVP/qJP7K5WLp1lg6g8Y5YJDoHQbio+ML+uvbcgNKmj7bdhRDPsNsMzD6yYYraK+OTytL3+v64rLGoPrQgLTeekyhBnZUmtoA/paggRzf5+jStlQAUJM0T0KlWnzOUjZc6UljSNFcwCZAojdGlAfdHfhxd7rG3j/ce6WEdzdAFu+op+0WyaXL7G3DuHeZwk+xmO1nEYRRg+IFS19CvvRlf5UgPe0BTF6JLhn2HOkqbGioKHaOyZ0R4uqck0+eAidcmMEOuKfXByhWyJKTVJCD5NzAoP5l35y4DYHpVnmTzRA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.23.195) smtp.rcpttodomain=nxp.com smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CBC3W2Sz8Ol7rD66X3Ume4mUVMmNDlyyyBOXPTW0ke4=; b=M0DK/tWitAaBFAB2EQz3vk2a1G/TR1/1tryYGkbPVtNTtFCxTvOieSHiFs83EIHbqeO3SehMcgS57fSgptjxZC6/r1K/vdWIMWDpLbntzaGv1bu5OVZBXWBol6Skwo6Ft0euwncFq+y24EDpYz0ME25atW++F6QiNgvUvP9M760= Received: from SJ0PR05CA0156.namprd05.prod.outlook.com (2603:10b6:a03:339::11) by CY8PR10MB7265.namprd10.prod.outlook.com (2603:10b6:930:79::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.7; Mon, 28 Sep 2026 02:59:45 +0000 Received: from SJ5PEPF000001ED.namprd05.prod.outlook.com (2603:10b6:a03:339:cafe::4e) by SJ0PR05CA0156.outlook.office365.com (2603:10b6:a03:339::11) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Mon, 28 Sep 2026 02:59:45 +0000 X-MS-Exchange-Authentication-Results: mx.microsoft.com 1; spf=pass (sender IP is 198.47.23.195) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.23.195 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.23.195; helo=lewvzet201.ext.ti.com; pr=C Received: from lewvzet201.ext.ti.com (198.47.23.195) by SJ5PEPF000001ED.mail.protection.outlook.com (10.167.242.201) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Mon, 28 Sep 2026 02:59:45 +0000 Received: from DLEE212.ent.ti.com (157.170.170.114) by lewvzet201.ext.ti.com (10.4.14.104) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:59:23 -0500 Received: from DLEE211.ent.ti.com (157.170.170.113) by DLEE212.ent.ti.com (157.170.170.114) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:59:22 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE211.ent.ti.com (157.170.170.113) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45 via Frontend Transport; Sun, 27 Sep 2026 21:59:22 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [10.24.51.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 68S2vqqP2256662; Sun, 27 Sep 2026 21:59:18 -0500 From: Sai Sree Kartheek Adivi To: , , , , , , , , , , , , , CC: , Subject: [PATCH v10 18/19] dmaengine: ti: k3-udma-v2: Update glue layer to support PKTDMA V2 Date: Mon, 28 Sep 2026 08:26:24 +0530 Message-ID: <20260928025749.1055383-19-s-adivi@ti.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260928025749.1055383-1-s-adivi@ti.com> References: <20260928025749.1055383-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001ED:EE_|CY8PR10MB7265:EE_ X-MS-Office365-Filtering-Correlation-Id: fcdd2ade-5b77-4a7a-d7ec-08df1d0c8cfc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|36860700016|376014|23010399003|1800799024|10067099003|6133799003|3023799007|22082099003|18002099003|56012099006|13003099007|921020; X-Microsoft-Antispam-Message-Info: +oVWou9m6/euQ4+lnm7qK5sX3jCOqI4o7DuL+yET6ar+a4bf3ec9L8ocfwJJPxUDmDRqs4yo5YfA0RhdfnO52r00cVCOJgrIBxcYodbrFKs+w/0YPTQ8ESuWLjn1Ti/vJrm1+DMj9FP8WJaa3mUeGWBPjPuDUli/AuCazc38mB2NrT3Vn6UETE7/g0So44HVT7Fskrwe4r53us96JLIrbCty3M3c/m8GyzgjqJ6GEk7geq46Ru1Cr7CHcgripelHHhH1DGxZ/Sby0NKe069d9VfReuBMKxevSyLO53q8eCLh44E9TtQE49azhkQ6/qKEOP58VPTfap3Y2u/Igy5pAdy/xtYH1LCdlyHfRZ0v97GOFxmPfT24U3I/0S0YbGMnSyuMitLC4xPGUPHIyXqwqQrDvta/b6UYDnUWXDnWlpmWr8lY8EjCFcJIIAIKpFFXgHvNA6VUgUE1vYY/G0kA1SdRUR2Ewyp5z9gj3hR0CFp0/6t0+hO0X2n/Q0zc3LU+7yVBP3fbeJxX8g2Q5xxr8BUhq0UlL8pUYvJ9UGqkOXkDIusUQKzdj0a8rIx+8yTm+rWnZiAxrCrGnsbTAh3xRzIg98TRpRVKjUTf3UR82Bc/g9ZoTVne3/z+HCDb9H66J/r0pENDPHzGOT8e6BWTjIi3uDw+VByGETREzkI0iNJQpFYlqKTEByPYZoxU0+i+ X-Forefront-Antispam-Report: CIP:198.47.23.195;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:lewvzet201.ext.ti.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(36860700016)(376014)(23010399003)(1800799024)(10067099003)(6133799003)(3023799007)(22082099003)(18002099003)(56012099006)(13003099007)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: UfiXG+hfMNXlCRVytIXPgX84zSl5pzZy5bVfgF8ASQil5IXM2zGWaOgkd/fp3kDXwTx5DiCwHqd63vFX6EU3MIwTT3pUiGXNuQR0XGCGI7HhAiw0+BXxPPAQ+eI1DwT4mjo6FgmRqR6Q6wiMQD1n84J0h+0ggZB3K8lGm7JwPjIHu8GaPpVv2Sraapoy1am1VYRF4uGcfeN64CKy4XZdl2HYDYQAbroB07bgPOoor4BHd3Fmep3uRVLED9/Dwbe+pLfF7aXjavJsjmekplBC/ULj5cysX+4dwvLFqHR2k8ctb0N0t49VikbI5i6Yl1Q00417hEANKT2TTN1mSHG7+R/LeGf2qYopfWV+KZgJ6RTPvtbseXVpLFX16f9RnNxAlfL0Kxuosldj+4iVQaf2gCOwSwSJfuOSklfcG+MflL6mspeh61dcOUfVNJhLqVlf X-Exchange-RoutingPolicyChecked: VxZ88l8RulRTlEHnWM1eEGRBbgzMhJRTy+/XbokMt9LNpLtyMeF3GjEHJ0wB4WZWE7SE0ZJSYKDVwYh7qnM9dHZTE2mEG2rMGiQ+WSnPKoNp38kLXdsUeg0DvIenV+rSNI75cW6DNShD82E76GgNO5bhddds5kfXtWyYP80kAgYk3IsHISHDEdZg1WuKLI67rQPeycddN++3jueIfg6kuT2tz4msCe8d4g6j5c0tNid9T/f0JXmWZ93t1cibe5o7YF9rrlgWkdMwIVyr5mnI3M1G8/L6aScyHJDpvusmuL5zBYs/Jt/9uOL0tSr/aMbP98TkDAZ3mXUc8dWmmSVFig== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 02:59:45.0745 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fcdd2ade-5b77-4a7a-d7ec-08df1d0c8cfc X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001ED.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR10MB7265 X-Proofpoint-GUID: 2Q7skfkwPijV7llpz5WifWU8Uff6QuZ1 X-Authority-Analysis: v=2.4 cv=fKysTpae c=1 sm=1 tr=0 ts=6ab9d826 cx=c_pps a=tGbvjRCxuxMasaU8K2d5rg==:117 a=f+v6EHfkeJbVwR46tk4DMg==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=VdqzKS8jKosA:10 a=s63m1ICgrNkA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=taLDd7a_hP9WKsMzeGRc:22 a=sozttTNsAAAA:8 a=4Ig8warNfptl5lTuD7MA:9 X-Proofpoint-ORIG-GUID: 2Q7skfkwPijV7llpz5WifWU8Uff6QuZ1 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX+tXWSHUlk1wb ZMCnkuM7I8regjhA76WCMA6vkA1N5xECGlxE2NdjqPM9o83Msm5Xm+6o70lnkAVT6hcivoudt6U HgG6xspMriPxvectfo8dQLJ5B4Ugoc4= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX4S7VEII3ve/R epnUTv2S9Jd0dhF7YS2HPoYQBpOq7V7Ow26Pz3kDyNCZOOj3elHGbO76T+qQmwgilT0N18g5oLL puKoZSkoqgvnxCdtNmKq3sG9xazZOkO7QWZU1NzsWRMW2coLHzeIxA2TAfLZdX21ctTa7BiHOem UdEC03YM91wRqu3sA1I5bG7QFJPvckD8EKJXU7e0Rnb0+2fwbvSijDVYa9EF1feRGGiDX0T96MD AjY4P9u8CdG1ltSbbiFNNOXcuiow8cRIZ+aEM4ms4GJzqGbYpovOCE6AXIJgDy0kXjg8tQ/JOpJ 9Dv3eCt25ZamSpM2g9T8Q96Z3Kh+7kQxty1d8aC6EEoaoHvho4BAOwhwp7bswK7C3dzzCDG3Ro9 NmJGd5zoaNmw7F8KS6bl3MMSJrdVpcr8CIEFHgR5aQj7/XRRkesDzpbj9wJgbq5olwq7i5Tyx/4 voGElPotq2V8lrlDMbw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 spamscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 adultscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280011 Content-Type: text/plain; charset="utf-8" Update glue layer to support PKTDMA V2 for non DMAengine users. The updates include - Handling absence of TISCI - Direct IRQs - Autopair: Lack of PSIL pair. Signed-off-by: Sai Sree Kartheek Adivi --- drivers/dma/ti/Kconfig | 2 +- drivers/dma/ti/k3-udma-glue.c | 190 ++++++++++++++++++++++++------- drivers/dma/ti/k3-udma-private.c | 5 + drivers/dma/ti/k3-udma.h | 13 +++ 4 files changed, 169 insertions(+), 41 deletions(-) diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig index 595fdf3ecbc9d..3d001f2e3f040 100644 --- a/drivers/dma/ti/Kconfig +++ b/drivers/dma/ti/Kconfig @@ -67,7 +67,7 @@ config TI_K3_UDMA_COMMON config TI_K3_UDMA_GLUE_LAYER tristate "Texas Instruments UDMA Glue layer for non DMAengine users" depends on ARCH_K3 || COMPILE_TEST - depends on TI_K3_UDMA + depends on TI_K3_UDMA || TI_K3_UDMA_V2 help Say y here to support the K3 NAVSS DMA glue interface If unsure, say N. diff --git a/drivers/dma/ti/k3-udma-glue.c b/drivers/dma/ti/k3-udma-glue.c index 996c130b10f4a..309a74a0b2a67 100644 --- a/drivers/dma/ti/k3-udma-glue.c +++ b/drivers/dma/ti/k3-udma-glue.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -267,6 +268,23 @@ static int k3_udma_glue_cfg_tx_chn(struct k3_udma_glue= _tx_channel *tx_chn) const struct udma_tisci_rm *tisci_rm =3D tx_chn->common.tisci_rm; struct ti_sci_msg_rm_udmap_tx_ch_cfg req; =20 + if (!tisci_rm->tisci) { + u32 val =3D 0; + + if (tx_chn->tx_pause_on_err) + val |=3D UDMA_CHAN_CFG_PAUSE_ON_ERR; + if (tx_chn->tx_filt_einfo) + val |=3D UDMA_CHAN_CFG_FILT_EINFO; + if (tx_chn->tx_filt_pswords) + val |=3D UDMA_CHAN_CFG_FILT_PSWORDS; + if (tx_chn->tx_supr_tdpkt) + val |=3D UDMA_CHAN_CFG_TX_SUPR_TDPKT; + + xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CFG_REG, val); + + return 0; + } + memset(&req, 0, sizeof(req)); =20 req.valid_params =3D TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | @@ -525,21 +543,39 @@ int k3_udma_glue_enable_tx_chn(struct k3_udma_glue_tx= _channel *tx_chn) { int ret; =20 - ret =3D xudma_navss_psil_pair(tx_chn->common.udmax, - tx_chn->common.src_thread, - tx_chn->common.dst_thread); - if (ret) { - dev_err(tx_chn->common.dev, "PSI-L request err %d\n", ret); - return ret; - } + if (tx_chn->common.udmax->match_data->version =3D=3D K3_UDMA_V1) { + ret =3D xudma_navss_psil_pair(tx_chn->common.udmax, + tx_chn->common.src_thread, + tx_chn->common.dst_thread); + if (ret) { + dev_err(tx_chn->common.dev, "PSI-L request err %d\n", ret); + return ret; + } =20 - tx_chn->psil_paired =3D true; + tx_chn->psil_paired =3D true; =20 - xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_RT_EN_REG, - UDMA_PEER_RT_EN_ENABLE); + xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_RT_EN_REG, + UDMA_PEER_RT_EN_ENABLE); =20 - xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG, - UDMA_CHAN_RT_CTL_EN); + xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_EN); + } else { + u32 val; + + xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_AUTOPAIR | UDMA_CHAN_RT_CTL_EN); + + ret =3D read_poll_timeout(xudma_tchanrt_read, val, + val & (UDMA_CHAN_RT_CTL_PAIR_COMPLETE | + UDMA_CHAN_RT_CTL_PAIR_TIMEOUT), + 100, 500, false, + tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG); + if (ret || (val & UDMA_CHAN_RT_CTL_PAIR_TIMEOUT)) { + dev_err(tx_chn->common.dev, "TX channel autopair timeout\n"); + xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG, 0); + return -ETIMEDOUT; + } + } =20 k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn en"); return 0; @@ -573,8 +609,16 @@ void k3_udma_glue_tdown_tx_chn(struct k3_udma_glue_tx_= channel *tx_chn, =20 k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn tdown1"); =20 - xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG, - UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN); + if (tx_chn->common.udmax->match_data->version =3D=3D K3_UDMA_V1) { + xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN); + } else { + xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_REG(8), + UDMA_CHAN_RT_PEER_REG8_FLUSH); + val =3D xudma_tchanrt_read(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG); + xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG, + val | UDMA_CHAN_RT_CTL_TDOWN); + } =20 val =3D xudma_tchanrt_read(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG); =20 @@ -589,10 +633,12 @@ void k3_udma_glue_tdown_tx_chn(struct k3_udma_glue_tx= _channel *tx_chn, i++; } =20 - val =3D xudma_tchanrt_read(tx_chn->udma_tchanx, - UDMA_CHAN_RT_PEER_RT_EN_REG); - if (sync && (val & UDMA_PEER_RT_EN_ENABLE)) - dev_err(tx_chn->common.dev, "TX tdown peer not stopped\n"); + if (tx_chn->common.udmax->match_data->version =3D=3D K3_UDMA_V1) { + val =3D xudma_tchanrt_read(tx_chn->udma_tchanx, + UDMA_CHAN_RT_PEER_RT_EN_REG); + if (sync && (val & UDMA_PEER_RT_EN_ENABLE)) + dev_err(tx_chn->common.dev, "TX tdown peer not stopped\n"); + } k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn tdown2"); } EXPORT_SYMBOL_GPL(k3_udma_glue_tdown_tx_chn); @@ -705,7 +751,6 @@ static int k3_udma_glue_cfg_rx_chn(struct k3_udma_glue_= rx_channel *rx_chn) TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID; =20 - req.nav_id =3D tisci_rm->tisci_dev_id; req.index =3D rx_chn->udma_rchan_id; req.rx_fetch_size =3D rx_chn->common.hdesc_size >> 2; /* @@ -725,11 +770,24 @@ static int k3_udma_glue_cfg_rx_chn(struct k3_udma_glu= e_rx_channel *rx_chn) req.rx_chan_type =3D TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR; req.rx_atype =3D rx_chn->common.atype_asel; =20 + if (!tisci_rm->tisci) { + u32 val =3D 0; + + if (rx_chn->common.epib) + val |=3D UDMA_CHAN_CFG_FILT_EINFO; + if (rx_chn->common.psdata_size) + val |=3D UDMA_CHAN_CFG_FILT_PSWORDS; + + xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CFG_REG, val); + + return 0; + } + + req.nav_id =3D tisci_rm->tisci_dev_id; ret =3D tisci_rm->tisci_udmap_ops->rx_ch_cfg(tisci_rm->tisci, &req); if (ret) dev_err(rx_chn->common.dev, "rchan%d cfg failed %d\n", - rx_chn->udma_rchan_id, ret); - + rx_chn->udma_rchan_id, ret); return ret; } =20 @@ -778,8 +836,11 @@ static int k3_udma_glue_cfg_rx_flow(struct k3_udma_glu= e_rx_channel *rx_chn, } =20 if (xudma_is_pktdma(rx_chn->common.udmax)) { - rx_ringfdq_id =3D flow->udma_rflow_id + + if (tisci_rm->tisci) + rx_ringfdq_id =3D flow->udma_rflow_id + xudma_get_rflow_ring_offset(rx_chn->common.udmax); + else + rx_ringfdq_id =3D flow->udma_rflow_id; rx_ring_id =3D 0; } else { rx_ring_id =3D flow_cfg->ring_rxq_id; @@ -826,6 +887,21 @@ static int k3_udma_glue_cfg_rx_flow(struct k3_udma_glu= e_rx_channel *rx_chn, rx_ringfdq_id =3D k3_ringacc_get_ring_id(flow->ringrxfdq); } =20 + if (!tisci_rm->tisci) { + u32 val =3D 0; + + if (rx_chn->common.epib) + val |=3D UDMA_FLOWRT_RFA_RX_EINFO_PRESENT; + if (rx_chn->common.psdata_size) + val |=3D UDMA_FLOWRT_RFA_RX_PSINFO_PRESENT; + if (flow_cfg->rx_error_handling) + val |=3D UDMA_FLOWRT_RFA_RX_ERROR_HANDLING; + + xudma_rflowrt_write(flow->udma_rflow, UDMA_RX_FLOWRT_RFA, val); + rx_chn->flows_ready++; + return 0; + } + memset(&req, 0, sizeof(req)); =20 req.valid_params =3D @@ -1331,6 +1407,9 @@ int k3_udma_glue_rx_flow_enable(struct k3_udma_glue_r= x_channel *rx_chn, if (!rx_chn->remote) return -EINVAL; =20 + if (!tisci_rm->tisci) + return 0; + rx_ring_id =3D k3_ringacc_get_ring_id(flow->ringrx); rx_ringfdq_id =3D k3_ringacc_get_ring_id(flow->ringrxfdq); =20 @@ -1372,6 +1451,9 @@ int k3_udma_glue_rx_flow_disable(struct k3_udma_glue_= rx_channel *rx_chn, if (!rx_chn->remote) return -EINVAL; =20 + if (!tisci_rm->tisci) + return 0; + memset(&req, 0, sizeof(req)); req.valid_params =3D TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID | @@ -1407,21 +1489,39 @@ int k3_udma_glue_enable_rx_chn(struct k3_udma_glue_= rx_channel *rx_chn) if (rx_chn->flows_ready < rx_chn->flow_num) return -EINVAL; =20 - ret =3D xudma_navss_psil_pair(rx_chn->common.udmax, - rx_chn->common.src_thread, - rx_chn->common.dst_thread); - if (ret) { - dev_err(rx_chn->common.dev, "PSI-L request err %d\n", ret); - return ret; - } + if (rx_chn->common.udmax->match_data->version =3D=3D K3_UDMA_V1) { + ret =3D xudma_navss_psil_pair(rx_chn->common.udmax, + rx_chn->common.src_thread, + rx_chn->common.dst_thread); + if (ret) { + dev_err(rx_chn->common.dev, "PSI-L request err %d\n", ret); + return ret; + } =20 - rx_chn->psil_paired =3D true; + rx_chn->psil_paired =3D true; =20 - xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG, - UDMA_CHAN_RT_CTL_EN); + xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_EN); =20 - xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG, - UDMA_PEER_RT_EN_ENABLE); + xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG, + UDMA_PEER_RT_EN_ENABLE); + } else { + u32 val; + + xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_AUTOPAIR | UDMA_CHAN_RT_CTL_EN); + + ret =3D read_poll_timeout(xudma_rchanrt_read, val, + val & (UDMA_CHAN_RT_CTL_PAIR_COMPLETE | + UDMA_CHAN_RT_CTL_PAIR_TIMEOUT), + 100, 500, false, + rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG); + if (ret || (val & UDMA_CHAN_RT_CTL_PAIR_TIMEOUT)) { + dev_err(rx_chn->common.dev, "RX channel autopair timeout\n"); + xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG, 0); + return -ETIMEDOUT; + } + } =20 k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt en"); return 0; @@ -1458,8 +1558,16 @@ void k3_udma_glue_tdown_rx_chn(struct k3_udma_glue_r= x_channel *rx_chn, =20 k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt tdown1"); =20 - xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG, - UDMA_PEER_RT_EN_ENABLE | UDMA_PEER_RT_EN_TEARDOWN); + if (rx_chn->common.udmax->match_data->version =3D=3D K3_UDMA_V1) { + xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG, + UDMA_PEER_RT_EN_ENABLE | UDMA_PEER_RT_EN_TEARDOWN); + } else { + xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_REG(8), + UDMA_CHAN_RT_PEER_REG8_FLUSH); + val =3D xudma_rchanrt_read(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG); + xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG, + val | UDMA_CHAN_RT_CTL_TDOWN); + } =20 val =3D xudma_rchanrt_read(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG); =20 @@ -1474,10 +1582,12 @@ void k3_udma_glue_tdown_rx_chn(struct k3_udma_glue_= rx_channel *rx_chn, i++; } =20 - val =3D xudma_rchanrt_read(rx_chn->udma_rchanx, - UDMA_CHAN_RT_PEER_RT_EN_REG); - if (sync && (val & UDMA_PEER_RT_EN_ENABLE)) - dev_err(rx_chn->common.dev, "TX tdown peer not stopped\n"); + if (rx_chn->common.udmax->match_data->version =3D=3D K3_UDMA_V1) { + val =3D xudma_rchanrt_read(rx_chn->udma_rchanx, + UDMA_CHAN_RT_PEER_RT_EN_REG); + if (sync && (val & UDMA_PEER_RT_EN_ENABLE)) + dev_err(rx_chn->common.dev, "TX tdown peer not stopped\n"); + } k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt tdown2"); } EXPORT_SYMBOL_GPL(k3_udma_glue_tdown_rx_chn); diff --git a/drivers/dma/ti/k3-udma-private.c b/drivers/dma/ti/k3-udma-priv= ate.c index 525155d3bb513..d6d99f60519a1 100644 --- a/drivers/dma/ti/k3-udma-private.c +++ b/drivers/dma/ti/k3-udma-private.c @@ -3,6 +3,10 @@ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com * Author: Peter Ujfalusi */ +#include +#include +#include +#include #include #include =20 @@ -165,6 +169,7 @@ void xudma_##res##rt_write(struct udma_##res *p, int re= g, u32 val) \ EXPORT_SYMBOL(xudma_##res##rt_write) XUDMA_RT_IO_FUNCTIONS(tchan); XUDMA_RT_IO_FUNCTIONS(rchan); +XUDMA_RT_IO_FUNCTIONS(rflow); =20 int xudma_is_pktdma(struct udma_dev *ud) { diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h index 2a9686f7a09bc..983cf2c32531c 100644 --- a/drivers/dma/ti/k3-udma.h +++ b/drivers/dma/ti/k3-udma.h @@ -85,6 +85,17 @@ #define UDMA_CHAN_RT_CTL_PAIR_COMPLETE BIT(16) #define UDMA_CHAN_RT_CTL_ERROR BIT(0) =20 +/* UDMA_CHAN_CFG_REG */ +#define UDMA_CHAN_CFG_PAUSE_ON_ERR BIT(31) +#define UDMA_CHAN_CFG_FILT_EINFO BIT(30) +#define UDMA_CHAN_CFG_FILT_PSWORDS BIT(29) +#define UDMA_CHAN_CFG_TX_SUPR_TDPKT BIT(8) + +/* UDMA_RX_FLOWRT_RFA */ +#define UDMA_FLOWRT_RFA_RX_EINFO_PRESENT BIT(30) +#define UDMA_FLOWRT_RFA_RX_PSINFO_PRESENT BIT(29) +#define UDMA_FLOWRT_RFA_RX_ERROR_HANDLING BIT(28) + /* UDMA_CHAN_RT_PDMA_STATE_REG */ #define UDMA_CHAN_RT_PDMA_STATE_IN_EVT BIT(31) #define UDMA_CHAN_RT_PDMA_STATE_TDOWN BIT(30) @@ -747,6 +758,8 @@ u32 xudma_rchanrt_read(struct udma_rchan *rchan, int re= g); void xudma_rchanrt_write(struct udma_rchan *rchan, int reg, u32 val); bool xudma_rflow_is_gp(struct udma_dev *ud, int id); int xudma_get_rflow_ring_offset(struct udma_dev *ud); +u32 xudma_rflowrt_read(struct udma_rflow *rflow, int reg); +void xudma_rflowrt_write(struct udma_rflow *rflow, int reg, u32 val); =20 int xudma_is_pktdma(struct udma_dev *ud); =20 --=20 2.54.0 From nobody Tue Sep 29 08:26:17 2026 Received: from mx0b-0002e601.pphosted.com (mx0b-0002e601.pphosted.com [148.163.154.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D634B376A07; Mon, 28 Sep 2026 03:00:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.154.28 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564432; cv=fail; b=AxAW1AYgnuCH+Q6kJLKdfUG9HLabfTFmO1UnRTmB6Rc0z0b/OMCxNpf0c1le0+D3BUaZBWK4NWOtWCSP6DRoxKSSsEFilt8vauvceBiJB4O6AQf9LgIStCq0zgeleon7jSzx1UYkmMKGngSeLdpu61l/g+hRQHzryHo9YykIwFM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790564432; c=relaxed/simple; bh=SXE/PfhbM1KB+3h/HfokUGluEpLtK/xTJZ99cP3ILLs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gr7yrkIx7iPSECxAq00AoXWaZS3LJebj84uO5FIGL4seSbnD6SolllVcN26jz3U3JypDAVnklMnGqjF0RKak5H2ONJDCJZd9bOaeB7AWu2ManMDKQgGLfgtp5dZD1vD6uf0CoT6xZr16B3khYRKxXG2Yf+KDXd7Kh5kbmQIqkI8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=DQHMNucV; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=bwfA5aSl; arc=fail smtp.client-ip=148.163.154.28 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="DQHMNucV"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="bwfA5aSl" Received: from pps.filterd (m0374956.ppops.net [127.0.0.1]) by mx0b-0002e601.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68RL6HQo2282713; Sun, 27 Sep 2026 22:00:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=vePeP0gaMHS0CYLoTCYK1Wcq7MJTuul12sQYk9J9p jU=; b=DQHMNucV3sMtSurQvZxPBgNZonYTLUzfKN++DjR+Et+MtcfdWDk3OzLCW E8PlfvscOXsIKD3fSwjK4ssdF3U4+ho1QUrO9DGtdksjuJA68NcHIm0v9EgFOFHU K96Eb7nTQN98WDGrFYj5bwcjqFGctqEqVQc6TnvzGNJ0iIQ0lXOxATE5F755edgF yY6MBXj3IGiduQ8Ao4hXgL916p2q9BWdm9R57uTzjTJIGA6tU/Ph7a+J0kA6NXis mhrLBlinOOCnoF3Ye2gFSC4t4jnJF0Pwl3Q7dkuNHkhNcYCV+ZvB5jjS5emPaWBO 5s+Krvf0bLeln9ijm6NdIU25VdgoA== Received: from byapr05cu005.outbound.protection.outlook.com (mail-westusazon11010060.outbound.protection.outlook.com [52.101.85.60]) by mx0b-0002e601.pphosted.com (PPS) with ESMTPS id 4gxw6nug5b-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Sun, 27 Sep 2026 22:00:21 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=kOu29oam6KLet4fT1rOy4eZ5gCLC2+HmwS506Rh4b9CGo0UixHxYgfVXgLvAYQLSpDc0d6/0MADZ4SBBw60rJzLWSeh7lne1Cst1zQqu5HJlWRC4k7FcgpDsmZf5nOTlW+L6jGHG/p3df16I916SvULZLnPhEfa6VLjVN+husRqRe+a+ybkTAjOEjaE0YTHDh18FMsX4SnemEHnY97l3horbzbTB41J6fbsvjFw/0SHkVmYvYqFlciWesiLF5SWDTFpZL1oCPrk5VGlHtptwYrOgya7jZB2VWc+X67Dm7Heswlw5ieKX593cR9xnzzV+ES1VSwStKANnRxOsWy912A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=vePeP0gaMHS0CYLoTCYK1Wcq7MJTuul12sQYk9J9pjU=; b=U260iHFZQinOmH+6JFV1xK8MJbYBX8R8w91ZGVodqyBdW1XYLNoblWc8r8o6igX1ceAHhQvFQpoAgAHd1r5fiuHBvjWP+K+aMdF5giWfhm2e0rO/BPX99rBbPW3Xtjo8QMOvgqoG9ryteZwKvfp0K0txuauyF/RrhZ1jBSReg52Kuib60mab9ov5f3zfYabyD0EvUpemTE3Jy2kPAldlCEhuRbT42rzBQMzrVBW5PGDprC6IAsRTu8fQETZbRbGoGmJgkXEAYr34AW1IQnRsTAjV0PS1+d8rUUNOVH5NdypF3AiYzxQ+kT2XAw4P1XnLaFDlv8fSmMwNnx4A/xYGvg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.21.195) smtp.rcpttodomain=nxp.com smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vePeP0gaMHS0CYLoTCYK1Wcq7MJTuul12sQYk9J9pjU=; b=bwfA5aSlT5eTNq+CZsfJGB3PKoDPvbfueBLggNK8arZ2rOXD53T43WzHNdNCvivg1qq7VfBtLS+IWZw1NYoPC0bMJnjYDhrJb1xlRSN1WWcWNR7smIl2+YBZOWEf7TOATHt40OqCJhvDfcdjK/RXZkmuASYsksFPCxg90k1I4VA= Received: from PH7P220CA0164.NAMP220.PROD.OUTLOOK.COM (2603:10b6:510:33b::7) by DSVPR10MB998102.namprd10.prod.outlook.com (2603:10b6:8:3aa::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.451.18; Mon, 28 Sep 2026 03:00:17 +0000 Received: from SJ1PEPF000023CF.namprd02.prod.outlook.com (2603:10b6:510:33b:cafe::45) by PH7P220CA0164.outlook.office365.com (2603:10b6:510:33b::7) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.451.23 via Frontend Transport; Mon, 28 Sep 2026 03:00:16 +0000 X-MS-Exchange-Authentication-Results: mx.microsoft.com 1; spf=pass (sender IP is 198.47.21.195) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.21.195 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.21.195; helo=flwvzet201.ext.ti.com; pr=C Received: from flwvzet201.ext.ti.com (198.47.21.195) by SJ1PEPF000023CF.mail.protection.outlook.com (10.167.244.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Mon, 28 Sep 2026 03:00:15 +0000 Received: from DFLE205.ent.ti.com (10.64.6.63) by flwvzet201.ext.ti.com (10.248.192.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:59:27 -0500 Received: from DFLE202.ent.ti.com (10.64.6.60) by DFLE205.ent.ti.com (10.64.6.63) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 27 Sep 2026 21:59:28 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE202.ent.ti.com (10.64.6.60) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45 via Frontend Transport; Sun, 27 Sep 2026 21:59:27 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [10.24.51.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 68S2vqqQ2256662; Sun, 27 Sep 2026 21:59:23 -0500 From: Sai Sree Kartheek Adivi To: , , , , , , , , , , , , , CC: , Subject: [PATCH v10 19/19] dmaengine: ti: k3-udma: Validate resource ID and fix logging in reservation Date: Mon, 28 Sep 2026 08:26:25 +0530 Message-ID: <20260928025749.1055383-20-s-adivi@ti.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260928025749.1055383-1-s-adivi@ti.com> References: <20260928025749.1055383-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CF:EE_|DSVPR10MB998102:EE_ X-MS-Office365-Filtering-Correlation-Id: f69e3851-2e8d-4cb8-920c-08df1d0c9ee8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|82310400026|36860700016|23010399003|921020|10067099003|56012099006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: bdv8aedXjNxJSBeUjdeeMju0TtttZaLnXjsOrGOSafljK/95tbgfhQT8CjqWqGU+9DngTm76XZ/yzuSGFwvav1d+06jlorgsFu2SBX5o3gmO83+Rw33vSXUOi6qg22MdVfqnN14Wd2nJjRDH1EdlqQQFQpgOzWeEHv8LSO7fS/oWcSeJWUkX2BWHlyDuOag4XtWgVBVzqhXrv/Zl2YnmC7+fbVS2kjWFOuV8qwsKvBkM1Cyi0qzhzBw7HjYuyGuMnWSS6o8/eYz5VmFP9TlNxYl1aBhL1d9BxRYPJCcOrX/OhnA0f0pbzCOkJjOp0zUfT/PSFvjSnlmgutxJvOfG+JEDRQvFV81j7wnRwvYcvzMHWKSW/Ayu1++L9N4q+/MZkxZjGB7rsqXxwvoropL8ylG9n3LpkgbgNbNY68csYkJ9gKAL8JAtkNMm+qpCXTbYEJPHIg6msLuY0GJA+n3vQahxGOf+cmyIxu95dacJALu5tbJ/scpzvzIFv2HpiEpcMRoKjeeL38TXmToKMImB6ZDzSCWYJDxrVpU4KmnJ5Bmawy2Px+jvESN8Sauo3v41hOMWrFvPZwqIVowqvEHcPbVZvrYxU6APeMojOm5zcuPWDUHa+Xv8LJea7LGiCDyAMWGtK3d+U0p4LEWD0E1ulok8SvqAixJqrtRjMaQHkdfnRK+PE5cWTpjAXZgQNGlXcKwflk5uwtPDYzY2kS9lwVU3eGqzID5AgrUxRSEuZ5sMgJPTiiw9qPPrvxJxfTA6 X-Forefront-Antispam-Report: CIP:198.47.21.195;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:flwvzet201.ext.ti.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(82310400026)(36860700016)(23010399003)(921020)(10067099003)(56012099006)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: FQMixtTsxU94VUP3KCi2nZM7w5Yiuvg+gmPYcVU1cuLDouK//+gBspfYA58/94im7SL1GO28lQmLDhjHRx6xuljUyHg2qpwxBbOfGSt6owGwcj06CUYvgmhyguXDbKy4HXC+MyggZ/UDmP8IlB6cY66dtsHDDBRLqzhtuOvi+x6FTU2IECp2KCl/Zd8ORszFvwMhNDn45EuPE/0gbLH3ngOi9pIAy4/qeaCLFJQIuLR7h2/gZCFgHTMXbSGClRjMjxS6Qy3rhsdq3xm+DZeRuEB3PA0CqnWa7o+BW2GIeAuUlOgcODXRUBHmADzuzD6U+20cybsoa1fLKisFM5Kkv1P7Vbz3hpL3dhIaOwqAR4e+9c9BC2lWGqy9qWuhovbipOddHaxoNyTKsQwvBaRyHBk8WDSU14I/u3GFhskkB96dKxj3XON5icTStc8PJz/M X-Exchange-RoutingPolicyChecked: eaY6w6wEgKhPdbuX5foZu+FoQtqZtOTyBoljPmorDG0EvnDmgnTCCLMr+eIkC3PL9vE+VuPjEwfEQ6USI7wWg0AS/foM+VUHyc/N7sNzzBz2e1uB+9UTe0Qdc6XYPTEI/8FWRsM1AvAvHNKM1EhqhsNWnGqpfFIjiihqUWKzHJzAb/MVtcQ5c5qw6LciWWRrXcG48GR6TqkYcgjwDyH2M1tiQAV8yURmleOliK0TtCwUT/FcrL1Ks5ax2aaBs6yeXMuYljCLVqnDyBqrq2DcjGvX88ulkFfGZoOnGXasEgWCh1gwKghhlR3HyzhuqmGYfcOZt8MpmhAgrSHvP3zzDg== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 03:00:15.1409 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f69e3851-2e8d-4cb8-920c-08df1d0c9ee8 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CF.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DSVPR10MB998102 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX4kOGhZX0LsSz ieuhzMsRNLziwz8yT4pMwMY0q4i/HrmEDy3eKpB7mCrIMAR5wfKU3YR61+Ux/L4vjdGm9WHwM16 zfKr38xgOmV1Y5wCiyawD8gh9b4uefE= X-Authority-Analysis: v=2.4 cv=dbkVTnXe c=1 sm=1 tr=0 ts=6ab9d845 cx=c_pps a=tP1g6Cq6k527JP85+VkTLg==:117 a=tJyPKKxUohctrY4NYmUjkA==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=VdqzKS8jKosA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=jwouBfj2j3NM8CExmVVE:22 a=sozttTNsAAAA:8 a=awo6gdX1Wv1SqJAOH5YA:9 X-Proofpoint-ORIG-GUID: EfHV3mojHnoKhmERSy6rsiPxN5U8BlX2 X-Proofpoint-GUID: EfHV3mojHnoKhmERSy6rsiPxN5U8BlX2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAxMSBTYWx0ZWRfX3KmNteLEbkUk b2WCQoJquR73u2Lc0OeIuqZIJAaTwnf4hM4kIHEu7CuXQwo4s0ohKnFkYHPIy3VNVaG6V5V7gHE e/cNC5wIR9PGD3cxJj3m2F96I22/A//2bzzbvEv7tZaZa5hXE1aAGQCMpZUx+FbOsbKLWNeR2PK c6NKOoitoP2XaUfx1PtpwOeIaj9gJgFxm+RwN0+mNcrN2I8+Ru0Wfg4+F2kHsEJi3ju3cqlM1Zo alkq6Vz6Jen2Skp9e+4Ze0Mh/PpQSAuzbCOQK88d4VGgZmwBBW2+eNHzZnWVFK99zwQF35WBTS6 FEoUh4Cgj0ZXrGC2HfbtelxY48rQFXjiHvvP/NlimBLjqq0UpVWs51WSKSkHLkedMXxpbCCvdfb xhcU2pu2cT42Nz+fDzYpy7AZUErQJkXdK9CJMIvPvBl2AsyzphfPd9Bf3pUkOwkWV7nbXZSNOy/ XxyLbqDv3MjOyBl169w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 impostorscore=0 adultscore=0 bulkscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280011 Content-Type: text/plain; charset="utf-8" The `__udma_reserve_##res` macro currently lacks a bounds check for the provided `id`. If a caller passes an ID exceeding the resource count (`ud->res##_cnt`), `test_bit()` performs an out-of-bounds memory access on the bitmap. Additionally, the macro returns `-ENOENT` when a resource is already in use, which is semantically incorrect. The logging logic is also broken, printing the literal "res##" instead of the resource name. Update the macro to: 1. Validate `id` against `ud->res##_cnt` and return `-EINVAL` if out of bounds. 2. Return `-EBUSY` instead of `-ENOENT` when a resource is already reserved, correctly reflecting the resource state. 3. Use the stringification operator `#res` to correctly print the resource name (e.g., "tchan") in error messages. Signed-off-by: Sai Sree Kartheek Adivi Reviewed-by: Vignesh Raghavendra --- drivers/dma/ti/k3-udma-common.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-commo= n.c index 5fa3a7b8d2026..812a177f7285d 100644 --- a/drivers/dma/ti/k3-udma-common.c +++ b/drivers/dma/ti/k3-udma-common.c @@ -2016,9 +2016,14 @@ struct udma_##res *__udma_reserve_##res(struct udma_= dev *ud, \ int id) \ { \ if (id >=3D 0) { \ + if (id >=3D ud->res##_cnt) { \ + dev_err(ud->dev, \ + #res " id %d is out of bounds.\n", id); \ + return ERR_PTR(-EINVAL); \ + } \ if (test_bit(id, ud->res##_map)) { \ - dev_err(ud->dev, "res##%d is in use\n", id); \ - return ERR_PTR(-ENOENT); \ + dev_err(ud->dev, #res "%d is in use\n", id); \ + return ERR_PTR(-EBUSY); \ } \ } else { \ int start; \ --=20 2.54.0