From nobody Mon Sep 28 05:45:36 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF184394788; Sun, 27 Sep 2026 13:09:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790514567; cv=none; b=dWSsoN1ofVF2se1d1ZIwSPF9b9iCxcVkt+nl1s5vVzOc+Cw+zAo+H9c0VvuTv3qav9mOJNsH8Vfd9r9pPDbFpi1HRMTXx5oOtPZoD/bDY3X+g7XtvgGX2nXNHIS8kgoDdcvXxovCMWJ9jioJQ058IVPbxkAtUV46X069SfNlJkw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790514567; c=relaxed/simple; bh=VV3PcSRW35Gh+Yndg2F831wLiF0LGsxmujAoDExyn0g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DxZcSOSS9w0C53H0rb1NmPH7A9I/l/PVlwQJXEdtbaatVbjiob9lGM3AA4JcBbws3goSkNMin3GWPU6cUcWEJ2RkL1GHgrhpiT3QqgzfkeG6RbI3I0gKR8maUyvRJ7SaNfK2OC7lBz3DUA2rmqMRILXxQh2HuirEeKElLooZAE8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YA+SdiUT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YA+SdiUT" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5ED25C4AF13; Sun, 27 Sep 2026 13:09:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790514567; bh=VV3PcSRW35Gh+Yndg2F831wLiF0LGsxmujAoDExyn0g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=YA+SdiUTDHUrzX4RMKaOq+lhn8PAPgEuhF25f2k7zwxR12n4kBjCd4rOj/umWp3eF AHpX4YndMFCE6QiLL5dKEiq9kKLG41wsOZ5jCEJrFTjSFb2JnZrprHEdXpJlvMkMyD JNmgOK7gBN1DHA1FvQKpaZxrl2uslxuCCGVinkpwxUkIPw9tdPHSy2quOBoKY5cnN9 OWHd41rnZgzSRgGjqx7jShxCNENXwG9AxG4ZNs9E6EgSE+uR18ex8ugFBw+YV1/PzI d0XfASa08RCaq+C2tLvgYIpmxjHm+ypQPzEwBsdyCHws6k0CBkxeRIfzgaIQgcbCns JteDxE86s4wBQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E8B7C9830E; Sun, 27 Sep 2026 13:09:27 +0000 (UTC) From: Daniel Drake via B4 Relay Date: Sun, 27 Sep 2026 14:09:00 +0100 Subject: [PATCH v7 1/6] iommu_pt: Fix test_pgsize_boundary() failure on narrow-OA formats Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260927-bcm2712-iommu-submit-v7-1-dfa2b975cbc9@reactivated.net> References: <20260927-bcm2712-iommu-submit-v7-0-dfa2b975cbc9@reactivated.net> In-Reply-To: <20260927-bcm2712-iommu-submit-v7-0-dfa2b975cbc9@reactivated.net> To: "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Daniel Drake Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, nick.hollinghurst@raspberrypi.com, james.quinlan@broadcom.com, Jason Gunthorpe X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1340; i=dan@reactivated.net; h=from:subject:message-id; bh=JFow46Vnz8reduVDvIc0YSORwX6vyQZXYpGoWC0l8YY=; b=kA0DAAoBw+aPsVMUR7sByyZiAGq5FYShEQEKIjovVnD1hOPwEinZcQ0OYFUbR7fJ9dJFV2SiT IkCMwQAAQoAHRYhBDpF/SxQ/WISFd9V+MPmj7FTFEe7BQJquRWEAAoJEMPmj7FTFEe7Qv8P/i1o 7q0v4JhmkVXw0zJ3ay5fArpJIAHgLXLRffJNLdwrOa9YfVsn+D0/FX3kLS9tAdMVGBNbT5Z1hR8 RjUtf+wj18jGAjjsE1d99HDuEFI5fVUlA9QR5QIgtnHTx07FYUITqCMHnYwLv88NlS29vqJESlQ C6/6j+RRAkWz0ce+mDMwXwW/QBwZx8SCrfCkLoJa/7NGbIRXFMwa3EEL6bA4tCGYZqc+1kFBYqo 2qcesp1j3zUAUPwgnb+0x16mD0jHaboMIDNqUT0lk+oUrSXbr8rHERHdv0Rrc8UDXEHGIKFzo98 82IHDfIv/4Zuf7JXFrHMHtqhnYSdyucJP1qUffTeWok5vsADncPF0Yn+uHz6xyU38oIKnShjs7x VyhC8bYCe1HpStUZVRdl2hSnWGErXQ3ndXMaZwt5JpAYiHa4feODm7rSowu0aMzLsOEPooWjsZG B97JQ6SZZLzQO5dhLZWRO9Saaxz+2SGBtTaV6z04u1DNKyU9n+nd4rgVgwqCD3TVjTcrpQpNQB+ DhIWRvGUuIGcZvzgzFehHyztrPx3uxMLUiZiGJ1gBpdeYbFB5AMqogfYGkneIe9tk910cs+Pxpu 6UYDWUNWbhkufG01535W/S2IAYLEPd5o/eQHcwtkVAek+lz+Bah1PpxaPXFU3DqhqfS+jQw3/vq dU0yA X-Developer-Key: i=dan@reactivated.net; a=openpgp; fpr=3A45FD2C50FD621215DF55F8C3E68FB1531447BB X-Endpoint-Received: by B4 Relay for dan@reactivated.net/default with auth_id=1070 X-Original-From: Daniel Drake Reply-To: dan@reactivated.net From: Daniel Drake test_pgsize_boundary() tests boundary mapping with a hardcoded physical address that requires 38 bits of physical address space. However, the upcoming page table format for the Broadcom BCM2712 IOMMU only supports 37 bits of output address space. This causes a test failure as iommu_map() rejects the large address with -ERANGE. Drop the high bits of the address (they are not relevant to the boundary calculations being tested) so that it fits into 32 bits. Reviewed-by: Jason Gunthorpe Signed-off-by: Daniel Drake --- drivers/iommu/generic_pt/kunit_iommu_pt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/generic_pt/kunit_iommu_pt.h b/drivers/iommu/gene= ric_pt/kunit_iommu_pt.h index ece1c9b8c55d..9fc71db74234 100644 --- a/drivers/iommu/generic_pt/kunit_iommu_pt.h +++ b/drivers/iommu/generic_pt/kunit_iommu_pt.h @@ -403,7 +403,7 @@ static void test_pgsize_boundary(struct kunit *test) priv->smallest_pgsz !=3D SZ_4K) kunit_skip(test, "Format does not have the required range"); =20 - do_map(test, 0xfef80000, 0x208b95d000, 0xfef9ffff - 0xfef80000 + 1); + do_map(test, 0xfef80000, 0x8b95d000, 0xfef9ffff - 0xfef80000 + 1); } =20 /* See https://lore.kernel.org/r/20250826143816.38686-1-eugkoira@amazon.co= m */ --=20 2.55.0 From nobody Mon Sep 28 05:45:36 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF2D43D6477; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260927-bcm2712-iommu-submit-v7-2-dfa2b975cbc9@reactivated.net> References: <20260927-bcm2712-iommu-submit-v7-0-dfa2b975cbc9@reactivated.net> In-Reply-To: <20260927-bcm2712-iommu-submit-v7-0-dfa2b975cbc9@reactivated.net> To: "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Daniel Drake Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, nick.hollinghurst@raspberrypi.com, james.quinlan@broadcom.com, Jason Gunthorpe , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3762; i=dan@reactivated.net; h=from:subject:message-id; bh=u7rJyBVNS3KWB72oeww+xedcyOSO1pu/9F/9FnMv+ZQ=; b=owEBbQKS/ZANAwAKAcPmj7FTFEe7AcsmYgBquRWECYGMBQdbsB2gNcq4Q1xw08k/ntG52bF+4 YfovzXHOCmJAjMEAAEKAB0WIQQ6Rf0sUP1iEhXfVfjD5o+xUxRHuwUCarkVhAAKCRDD5o+xUxRH uz1vD/9RzIY4deEi9rxCqIEQK+m3BFJjbNwrYh9IwwYJz+EHxf89OOM264wn+CJUzAPPbqV43n2 SmfKViwwEJYbvExYXpnjxRtgEIS4hgZgExlnqgE84A/AkDwt/E9uUjxoQNKoFMnxtJ2lnBKeB6P Zx66frOS88cW0uoE1cUZWWKkIDn3fcbWs+k8vRn9LDseE0UxdnWVQ8C33sDL7MfGLRX4JL+mVzf 813lDls0iT7z8RwJGrZ6sFhrspX2djUhZj3bjpl1v7PqGBSytg3FKlBNyR3q46NL4AH/8CMrxWL f/WwCq8dxf1nVOl8cscVmK26vOcOWFxLn5Pxb2LnSF/PXwBvh+aVbnpEGSzkH4IkVPbKj2wJL9I RP43SGlDUoQqh5Dj6TUEraokfxMQnyzL8eq14NmzX5H0L3TlQIQoqgxa/LyXnBf95bWpLSXz1SJ XmrbVegWr+yaVlv0vA6RFuNoMffqyVY6rMNPXYUrMllxkOwIvRLyFRiRi5duTP8o9CJ417Z4YeR QnXExCgxAZcNag56OzPVtH/LFq+RPmzQ7L1cim5rh8nXtNU0Jc2px5GxEvGrRTiwlaDQsdEDwpI HRNT+7FETDlfGC3nJEasqUNFDIknYTlv2z3nJ7Jw3J05++DdE7Ege8LKAyMOTXY4MTfq50UlVA0 Ernq3x7tIicu0Yw== X-Developer-Key: i=dan@reactivated.net; a=openpgp; fpr=3A45FD2C50FD621215DF55F8C3E68FB1531447BB X-Endpoint-Received: by B4 Relay for dan@reactivated.net/default with auth_id=1070 X-Original-From: Daniel Drake Reply-To: dan@reactivated.net From: Daniel Drake Add bindings for the Broadcom BCM2712 IOMMUs and their shared TLB cache. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Daniel Drake --- .../bindings/iommu/brcm,bcm2712-iommu.yaml | 54 ++++++++++++++++++= ++++ .../bindings/iommu/brcm,bcm2712-iommuc.yaml | 40 ++++++++++++++++ 2 files changed, 94 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/brcm,bcm2712-iommu.yam= l b/Documentation/devicetree/bindings/iommu/brcm,bcm2712-iommu.yaml new file mode 100644 index 000000000000..5ca8ce469ec3 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/brcm,bcm2712-iommu.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/brcm,bcm2712-iommu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM2712 IOMMU + +maintainers: + - Daniel Drake + - Florian Fainelli + - Jim Quinlan + +description: + The BCM2712 SoC features multiple independent IOMMU instances providing + address translation for multimedia hardware blocks, such as the VC6 disp= lay + pipeline, camera receivers, and ISP. Each IOMMU has its own page tables, + control registers, and local TLB, and is additionally linked to a centra= lized + L2 TLB (IOMMUC). + +properties: + compatible: + const: brcm,bcm2712-iommu + + reg: + maxItems: 1 + + '#iommu-cells': + const: 0 + + brcm,iommu-cache: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the shared IOMMU cache (IOMMUC). Each IOMMU instance cach= es + translated descriptors in this centralized L2 TLB cache block and mu= st + trigger cache invalidation commands on it when updating or unmapping= page + table entries. + +required: + - compatible + - reg + - '#iommu-cells' + - brcm,iommu-cache + +additionalProperties: false + +examples: + - | + iommu@5200 { + compatible =3D "brcm,bcm2712-iommu"; + reg =3D <0x5200 0x80>; + brcm,iommu-cache =3D <&iommuc>; + #iommu-cells =3D <0>; + }; diff --git a/Documentation/devicetree/bindings/iommu/brcm,bcm2712-iommuc.ya= ml b/Documentation/devicetree/bindings/iommu/brcm,bcm2712-iommuc.yaml new file mode 100644 index 000000000000..47c584ad667a --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/brcm,bcm2712-iommuc.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/brcm,bcm2712-iommuc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM2712 Shared IOMMU Cache (IOMMUC) + +maintainers: + - Daniel Drake + - Florian Fainelli + - Jim Quinlan + +description: + The BCM2712 IOMMUC is a centralized Translation Lookaside Buffer (TLB) c= ache + which accelerates address translation across the SoC's IOMMU devices. If= an + address mapping is not found in the IOMMU's local TLB cache, then this + IOMMUC is consulted as a L2 TLB. The SoC includes a single IOMMUC which = is + shared between all IOMMUs, and it must be explicitly invalidated when + modifying or unmapping IOMMU page tables. + +properties: + compatible: + const: brcm,bcm2712-iommuc + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + iommuc@5b00 { + compatible =3D "brcm,bcm2712-iommuc"; + reg =3D <0x5b00 0x80>; + }; --=20 2.55.0 From nobody Mon Sep 28 05:45:36 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF21B39FCCA; Sun, 27 Sep 2026 13:09:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790514567; cv=none; b=Jw7nNuwGzjIfxpRyAur17u8L07MjerPUxbDCHi/TjXuirBIZSxaLEC3FCbWzlE6/97C4PO31/+X0X3Barc5IENX3h7BBVs7MKBzDEYJfrN/61SQyFacUgv20jS+UqIE7lBS3IACK7zwjJ0eEghiNrh5NyoitK7O65B8iUU6IEmY= ARC-Message-Signature: i=1; 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a=openpgp; fpr=3A45FD2C50FD621215DF55F8C3E68FB1531447BB X-Endpoint-Received: by B4 Relay for dan@reactivated.net/default with auth_id=1070 X-Original-From: Daniel Drake Reply-To: dan@reactivated.net From: Daniel Drake On BCM2712, the Hardware Video Scaler (HVS) is connected behind an IOMMU. Add the optional iommus property to allow describing this connection. Acked-by: Conor Dooley Reviewed-by: Florian Fainelli Signed-off-by: Daniel Drake --- Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yam= l b/Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml index 9aca38a58a16..8f8aae9f3788 100644 --- a/Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml +++ b/Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml @@ -35,6 +35,9 @@ properties: minItems: 1 maxItems: 2 =20 + iommus: + maxItems: 1 + required: - compatible - reg --=20 2.55.0 From nobody Mon Sep 28 05:45:36 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4DDD3E49C1; Sun, 27 Sep 2026 13:09:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260927-bcm2712-iommu-submit-v7-4-dfa2b975cbc9@reactivated.net> References: <20260927-bcm2712-iommu-submit-v7-0-dfa2b975cbc9@reactivated.net> In-Reply-To: <20260927-bcm2712-iommu-submit-v7-0-dfa2b975cbc9@reactivated.net> To: "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Daniel Drake Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, nick.hollinghurst@raspberrypi.com, james.quinlan@broadcom.com, Jason Gunthorpe X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=13852; i=dan@reactivated.net; h=from:subject:message-id; bh=0P+lUXYOAgHwLKK7IMQBMw6DGl1StORwkeDAvWwmVYw=; b=owEBbQKS/ZANAwAKAcPmj7FTFEe7AcsmYgBquRWFU3GU2jPnusqsekrGt3S1zI+EiSt4NQG91 QyQr+JvyViJAjMEAAEKAB0WIQQ6Rf0sUP1iEhXfVfjD5o+xUxRHuwUCarkVhQAKCRDD5o+xUxRH uzjMEACITl0YO9GviqoTM5n28hBMmItayRozIT6ynMmAGnkh/ydSzr5LeFM2Dt0pDVWTMQO8BsK IgNxnG/Oy44/n6WmdprSOZDL3Jwx8UrVX9tePUemmQ/0Vn6QB9N5uFJEJ5xIWsQ6AmKAyKKVvY7 CmIUmwXvX+IABpBfWaqhoRPS3SLmC41A9HszJtZfQmO8TUXDajATY+jLhOPb9x9thMBU+K/Fpxd eAb8FIE4tvgCBtsc1bQRIfr1nIP0E1fR6rf7fVn/4FvH3n+yz9V7w2JTM0M6jJwyL5K5joVj7Tc m+clqGUP1KVGh3CwGPlYOalJEzdyB0Er444BnTdMgnzJ2f7lYnhdyPEJA6hpLupcwz9kHDlAaG1 z1tAenpalfoRjQQQyCWY09AYWuFSntPyFjQMoEoD4hoIiEHGAFaqVSVE2bcyINXDJwvGmqgVPjm akSAJ5Ub6slC+pIgHXtdsjZVMUJ1aIWZtXxEHx5NevE0Hm1SOJgZdSBjUWLpIC7lqxjJJvXMu9F xWhBLhS34WT/3euhW98lRrNQK8NXPsh8kfleV65YTN2ONHkST3gqN69JwBXZ9HK9CvqjdAdl8vN pXV0jQjCLU70AqFsh+zk2Nu4D28X1YEq8kOrZXjb6FGP7rNmsyjIgnbX5ap4Qn1pidApET1Fz7z NggExlN+YeymLIA== X-Developer-Key: i=dan@reactivated.net; a=openpgp; fpr=3A45FD2C50FD621215DF55F8C3E68FB1531447BB X-Endpoint-Received: by B4 Relay for dan@reactivated.net/default with auth_id=1070 X-Original-From: Daniel Drake Reply-To: dan@reactivated.net From: Daniel Drake Implement generic_pt support for the 2-level page table format used by the BCM2712 IOMMUs. Adapted from Raspberry Pi's downstream bcm2712-iommu driver (original author Nick Hollinghurst). Reviewed-by: Jason Gunthorpe Signed-off-by: Daniel Drake --- drivers/iommu/generic_pt/.kunitconfig | 1 + drivers/iommu/generic_pt/Kconfig | 10 + drivers/iommu/generic_pt/fmt/Makefile | 2 + drivers/iommu/generic_pt/fmt/bcm2712.h | 288 +++++++++++++++++++++++= ++++ drivers/iommu/generic_pt/fmt/defs_bcm2712.h | 18 ++ drivers/iommu/generic_pt/fmt/iommu_bcm2712.c | 6 + include/linux/generic_pt/common.h | 6 + include/linux/generic_pt/iommu.h | 12 ++ 8 files changed, 343 insertions(+) diff --git a/drivers/iommu/generic_pt/.kunitconfig b/drivers/iommu/generic_= pt/.kunitconfig index 0bb98fe581fe..a3da74328f12 100644 --- a/drivers/iommu/generic_pt/.kunitconfig +++ b/drivers/iommu/generic_pt/.kunitconfig @@ -7,6 +7,7 @@ CONFIG_IOMMU_PT_AMDV1=3Dy CONFIG_IOMMU_PT_VTDSS=3Dy CONFIG_IOMMU_PT_RISCV64=3Dy CONFIG_IOMMU_PT_X86_64=3Dy +CONFIG_IOMMU_PT_BCM2712=3Dy CONFIG_IOMMU_PT_KUNIT_TEST=3Dy =20 CONFIG_IOMMUFD=3Dy diff --git a/drivers/iommu/generic_pt/Kconfig b/drivers/iommu/generic_pt/Kc= onfig index f4ed1add58b7..2a81dac960ac 100644 --- a/drivers/iommu/generic_pt/Kconfig +++ b/drivers/iommu/generic_pt/Kconfig @@ -72,6 +72,15 @@ config IOMMU_PT_X86_64 =20 Selected automatically by an IOMMU driver that uses this format. =20 +config IOMMU_PT_BCM2712 + tristate "IOMMU page table for Broadcom BCM2712" + help + iommu_domain implementation for the Broadcom BCM2712 IOMMU found on + Raspberry Pi 5. It supports 4K page sizes over a 2-level page table + format. + + Selected automatically by an IOMMU driver that uses this format. + config IOMMU_PT_KUNIT_TEST tristate "IOMMU Page Table KUnit Test" if !KUNIT_ALL_TESTS depends on KUNIT @@ -79,6 +88,7 @@ config IOMMU_PT_KUNIT_TEST depends on IOMMU_PT_RISCV64 || !IOMMU_PT_RISCV64 depends on IOMMU_PT_X86_64 || !IOMMU_PT_X86_64 depends on IOMMU_PT_VTDSS || !IOMMU_PT_VTDSS + depends on IOMMU_PT_BCM2712 || !IOMMU_PT_BCM2712 default KUNIT_ALL_TESTS help Enable kunit tests for GENERIC_PT and IOMMU_PT that covers all the diff --git a/drivers/iommu/generic_pt/fmt/Makefile b/drivers/iommu/generic_= pt/fmt/Makefile index ea024d582594..82ca3c36823d 100644 --- a/drivers/iommu/generic_pt/fmt/Makefile +++ b/drivers/iommu/generic_pt/fmt/Makefile @@ -9,6 +9,8 @@ iommu_pt_fmt-$(CONFIG_IOMMU_PT_RISCV64) +=3D riscv64 =20 iommu_pt_fmt-$(CONFIG_IOMMU_PT_X86_64) +=3D x86_64 =20 +iommu_pt_fmt-$(CONFIG_IOMMU_PT_BCM2712) +=3D bcm2712 + IOMMU_PT_KUNIT_TEST :=3D define create_format obj-$(2) +=3D iommu_$(1).o diff --git a/drivers/iommu/generic_pt/fmt/bcm2712.h b/drivers/iommu/generic= _pt/fmt/bcm2712.h new file mode 100644 index 000000000000..2c5b034441c1 --- /dev/null +++ b/drivers/iommu/generic_pt/fmt/bcm2712.h @@ -0,0 +1,288 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2026 Daniel Drake + * + * BCM2712 IOMMU simple two level page table + */ +#ifndef __GENERIC_PT_FMT_BCM2712_H +#define __GENERIC_PT_FMT_BCM2712_H + +#include "defs_bcm2712.h" +#include "../pt_defs.h" + +#include +#include +#include +#include + +enum { + /* Hardware provides a two-level page table */ + PT_MAX_TOP_LEVEL =3D 1, + + /* Hardware page size is strictly 4kb */ + PT_GRANULE_LG2SZ =3D ilog2(SZ_4K), + PT_TABLEMEM_LG2SZ =3D PT_GRANULE_LG2SZ, + + /* Table entries and leaf entries are 32 bits */ + PT_ITEM_WORD_SIZE =3D sizeof(pt_bcm2712_entry_t), + + /* Leaf entries encode a 25-bit PFN */ + PT_MAX_OUTPUT_ADDRESS_LG2 =3D 25 + PT_GRANULE_LG2SZ, + + /* + * For simplicity, only manage mappings within an address space of + * exactly 4GB. This is because our Level 1 directory page will be 4kb + * in the smallest case, permitting 1024 entries pointing at Level 0 + * pages, each permitting 4mb of mapped memory. + */ + PT_MAX_VA_ADDRESS_LG2 =3D ilog2(SZ_4G), + + /* Level 1 base address is programmed as a 32-bit PFN */ + PT_TOP_PHYS_MASK =3D GENMASK_ULL(31 + PT_GRANULE_LG2SZ, PT_GRANULE_LG2SZ), +}; + +/* PTE bits */ +enum { + BCM2712PT_VALID =3D BIT(28), + BCM2712PT_WRITE =3D BIT(29), + BCM2712PT_PAGESIZE =3D GENMASK(31, 30), + BCM2712PT_PFN =3D GENMASK(24, 0), +}; + +#define common_to_bcm2712pt(common_ptr) \ + container_of_const(common_ptr, struct pt_bcm2712, common) +#define to_bcm2712pt(pts) common_to_bcm2712pt((pts)->range->common) + +static inline pt_oaddr_t bcm2712pt_table_pa(const struct pt_state *pts) +{ + return oalog2_mul(FIELD_GET(BCM2712PT_PFN, pts->entry), + PT_GRANULE_LG2SZ); +} +#define pt_table_pa bcm2712pt_table_pa +#define pt_item_oa bcm2712pt_table_pa + +static inline bool bcm2712pt_can_have_leaf(const struct pt_state *pts) +{ + return true; +} +#define pt_can_have_leaf bcm2712pt_can_have_leaf + +/* 4MB pages are installed at level 1, everything else at level 0 */ +static inline unsigned int bcm2712pt_pgsz_lg2_to_level(struct pt_common *c= ommon, + unsigned int pgsize_lg2) +{ + return pgsize_lg2 =3D=3D ilog2(SZ_4M) ? 1 : 0; +} +#define pt_pgsz_lg2_to_level bcm2712pt_pgsz_lg2_to_level + +static inline pt_vaddr_t bcm2712pt_possible_sizes(const struct pt_state *p= ts) +{ + struct pt_bcm2712 *table =3D common_to_bcm2712pt(pts->range->common); + + if (pts->level =3D=3D 1) + return SZ_4M; + + return SZ_4K | + (table->bigpage_lg2 ? BIT_ULL(table->bigpage_lg2) : 0) | + (table->superpage_lg2 ? BIT_ULL(table->superpage_lg2) : 0); +} +#define pt_possible_sizes bcm2712pt_possible_sizes + +static inline unsigned int +bcm2712pt_entry_num_contig_lg2(const struct pt_state *pts) +{ + struct pt_bcm2712 *table =3D common_to_bcm2712pt(pts->range->common); + u32 pgsz =3D FIELD_GET(BCM2712PT_PAGESIZE, pts->entry); + + if (pts->level !=3D 0 || !(pts->entry & BCM2712PT_VALID)) + return 0; + + /* + * Superpage/bigpage contiguous mapping (really just hinting) is handled + * via PAGESIZE bits on each leaf entry. + */ + if (pgsz =3D=3D 2 && table->superpage_lg2) + return table->superpage_lg2 - PT_GRANULE_LG2SZ; + else if (pgsz =3D=3D 1 && table->bigpage_lg2) + return table->bigpage_lg2 - PT_GRANULE_LG2SZ; + return 0; +} +#define pt_entry_num_contig_lg2 bcm2712pt_entry_num_contig_lg2 + +static inline unsigned int bcm2712pt_num_items_lg2(const struct pt_state *= pts) +{ + return PT_TABLEMEM_LG2SZ - ilog2(PT_ITEM_WORD_SIZE); +} +#define pt_num_items_lg2 bcm2712pt_num_items_lg2 + +static inline enum pt_entry_type bcm2712pt_load_entry_raw(struct pt_state = *pts) +{ + const pt_bcm2712_entry_t *tablep =3D + pt_cur_table(pts, pt_bcm2712_entry_t); + + pts->entry =3D READ_ONCE(tablep[pts->index]); + if (!(pts->entry & BCM2712PT_VALID)) + return PT_ENTRY_EMPTY; + + if (pts->level =3D=3D 1) { + if (FIELD_GET(BCM2712PT_PAGESIZE, pts->entry) =3D=3D 3) + return PT_ENTRY_OA; + return PT_ENTRY_TABLE; + } + + return PT_ENTRY_OA; +} +#define pt_load_entry_raw bcm2712pt_load_entry_raw + +static inline void +bcm2712pt_install_leaf_entry(struct pt_state *pts, pt_oaddr_t oa, + unsigned int oasz_lg2, + const struct pt_write_attrs *attrs) +{ + pt_bcm2712_entry_t *tablep =3D pt_cur_table(pts, pt_bcm2712_entry_t); + pt_bcm2712_entry_t entry; + + if (!pt_check_install_leaf_args(pts, oa, oasz_lg2)) + return; + + entry =3D BCM2712PT_VALID | attrs->descriptor_bits | + FIELD_PREP(BCM2712PT_PFN, oalog2_div(oa, PT_GRANULE_LG2SZ)); + + if (pts->level =3D=3D 1) { + /* Level 1 hugepage (4MB) */ + entry |=3D FIELD_PREP(BCM2712PT_PAGESIZE, 3); + WRITE_ONCE(tablep[pts->index], entry); + pts->entry =3D entry; + return; + } + + if (oasz_lg2 =3D=3D PT_GRANULE_LG2SZ) { + WRITE_ONCE(tablep[pts->index], entry); + pts->entry =3D entry; + } else { + struct pt_bcm2712 *table =3D + common_to_bcm2712pt(pts->range->common); + u32 *end; + + tablep +=3D pts->index; + end =3D tablep + log2_to_int(oasz_lg2 - PT_GRANULE_LG2SZ); + + /* + * Leaf entries can contain hints indicating bigpage/superpage + * contiguous mappings to permit TLB optimization + */ + if (oasz_lg2 =3D=3D table->superpage_lg2) + entry |=3D FIELD_PREP(BCM2712PT_PAGESIZE, 2); + else if (oasz_lg2 =3D=3D table->bigpage_lg2) + entry |=3D FIELD_PREP(BCM2712PT_PAGESIZE, 1); + + pts->entry =3D entry; + for (; tablep !=3D end; tablep++, entry++) + WRITE_ONCE(*tablep, entry); + } +} +#define pt_install_leaf_entry bcm2712pt_install_leaf_entry + +static inline bool bcm2712pt_install_table(struct pt_state *pts, + pt_oaddr_t table_pa, + const struct pt_write_attrs *attrs) +{ + pt_bcm2712_entry_t entry =3D + BCM2712PT_VALID | + FIELD_PREP(BCM2712PT_PFN, + oalog2_div(table_pa, PT_GRANULE_LG2SZ)); + + return pt_table_install32(pts, entry); +} +#define pt_install_table bcm2712pt_install_table + +static inline void bcm2712pt_attr_from_entry(const struct pt_state *pts, + struct pt_write_attrs *attrs) +{ + attrs->descriptor_bits =3D pts->entry & BCM2712PT_WRITE; +} +#define pt_attr_from_entry bcm2712pt_attr_from_entry + +static inline unsigned int bcm2712pt_max_sw_bit(struct pt_common *common) +{ + return 2; +} +#define pt_max_sw_bit bcm2712pt_max_sw_bit + +static inline u32 bcm2712pt_sw_bit(unsigned int bitnr) +{ + if (__builtin_constant_p(bitnr) && bitnr > 2) + BUILD_BUG(); + if (PT_WARN_ON(bitnr > 2)) + return 0; + + /* Bits 27, 26 and 25 are believed spare */ + return BIT(27 - bitnr); +} +#define pt_sw_bit bcm2712pt_sw_bit + +/* --- iommu */ +#include +#include + +#define pt_iommu_table pt_iommu_bcm2712 + +/* The common struct is in the per-format common struct */ +static inline struct pt_common *common_from_iommu(struct pt_iommu *iommu_t= able) +{ + return &container_of(iommu_table, struct pt_iommu_table, iommu) + ->bcm2712pt.common; +} + +static inline struct pt_iommu *iommu_from_common(struct pt_common *common) +{ + return &container_of(common, struct pt_iommu_table, bcm2712pt.common) + ->iommu; +} + +static inline int bcm2712_pt_iommu_set_prot(struct pt_common *common, + struct pt_write_attrs *attrs, + unsigned int iommu_prot) +{ + attrs->descriptor_bits =3D 0; + if (iommu_prot & IOMMU_WRITE) + attrs->descriptor_bits |=3D BCM2712PT_WRITE; + return 0; +} +#define pt_iommu_set_prot bcm2712_pt_iommu_set_prot + +static inline int bcm2712_pt_fmt_init(struct pt_iommu_table *fmt_table, + const struct pt_iommu_bcm2712_cfg *cfg) +{ + fmt_table->bcm2712pt.bigpage_lg2 =3D cfg->bigpage_lg2; + fmt_table->bcm2712pt.superpage_lg2 =3D cfg->superpage_lg2; + + pt_top_set_level(&fmt_table->bcm2712pt.common, PT_MAX_TOP_LEVEL); + return 0; +} +#define pt_iommu_fmt_init bcm2712_pt_fmt_init + +static inline void +bcm2712pt_iommu_fmt_hw_info(struct pt_iommu_bcm2712 *table, + const struct pt_range *top_range, + struct pt_iommu_bcm2712_hw_info *info) +{ + info->pt_base =3D virt_to_phys(top_range->top_table); + PT_WARN_ON(info->pt_base & ~PT_TOP_PHYS_MASK); +} +#define pt_iommu_fmt_hw_info bcm2712pt_iommu_fmt_hw_info + +#if defined(GENERIC_PT_KUNIT) +static const struct pt_iommu_bcm2712_cfg bcm2712_kunit_fmt_cfgs[] =3D { + [0] =3D { + .common.hw_max_vasz_lg2 =3D 32, + .common.hw_max_oasz_lg2 =3D 37, + .bigpage_lg2 =3D 16, + .superpage_lg2 =3D 20, + }, +}; +#define kunit_fmt_cfgs bcm2712_kunit_fmt_cfgs +enum { KUNIT_FMT_FEATURES =3D 0 }; +#endif + +#endif diff --git a/drivers/iommu/generic_pt/fmt/defs_bcm2712.h b/drivers/iommu/ge= neric_pt/fmt/defs_bcm2712.h new file mode 100644 index 000000000000..f1d983be1716 --- /dev/null +++ b/drivers/iommu/generic_pt/fmt/defs_bcm2712.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __GENERIC_PT_FMT_DEFS_BCM2712_H +#define __GENERIC_PT_FMT_DEFS_BCM2712_H + +#include +#include + +typedef u32 pt_bcm2712_entry_t; +typedef u64 pt_vaddr_t; +typedef u64 pt_oaddr_t; + +struct bcm2712pt_write_attrs { + pt_bcm2712_entry_t descriptor_bits; + gfp_t gfp; +}; +#define pt_write_attrs bcm2712pt_write_attrs + +#endif diff --git a/drivers/iommu/generic_pt/fmt/iommu_bcm2712.c b/drivers/iommu/g= eneric_pt/fmt/iommu_bcm2712.c new file mode 100644 index 000000000000..43fbc3cf3adc --- /dev/null +++ b/drivers/iommu/generic_pt/fmt/iommu_bcm2712.c @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only +#define PT_FMT bcm2712 +#define PT_SUPPORTED_FEATURES BIT(PT_FEAT_DMA_INCOHERENT) + +#include +#include "iommu_template.h" diff --git a/include/linux/generic_pt/common.h b/include/linux/generic_pt/c= ommon.h index 07ef1c8341a4..1b39b27f0cfa 100644 --- a/include/linux/generic_pt/common.h +++ b/include/linux/generic_pt/common.h @@ -213,4 +213,10 @@ enum { PT_FEAT_X86_64_AMD_ENCRYPT_TABLES =3D PT_FEAT_FMT_START, }; =20 +struct pt_bcm2712 { + struct pt_common common; + u8 bigpage_lg2; + u8 superpage_lg2; +}; + #endif diff --git a/include/linux/generic_pt/iommu.h b/include/linux/generic_pt/io= mmu.h index dd0edd02a48a..13ebb72a67de 100644 --- a/include/linux/generic_pt/iommu.h +++ b/include/linux/generic_pt/iommu.h @@ -346,6 +346,18 @@ struct pt_iommu_x86_64_hw_info { =20 IOMMU_FORMAT(x86_64, x86_64_pt); =20 +struct pt_iommu_bcm2712_cfg { + struct pt_iommu_cfg common; + u8 bigpage_lg2; + u8 superpage_lg2; +}; + +struct pt_iommu_bcm2712_hw_info { + phys_addr_t pt_base; +}; + +IOMMU_FORMAT(bcm2712, bcm2712pt); + #undef IOMMU_PROTOTYPES #undef IOMMU_FORMAT #endif --=20 2.55.0 From nobody Mon Sep 28 05:45:36 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E52C23EFFBA; Sun, 27 Sep 2026 13:09:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260927-bcm2712-iommu-submit-v7-5-dfa2b975cbc9@reactivated.net> References: <20260927-bcm2712-iommu-submit-v7-0-dfa2b975cbc9@reactivated.net> In-Reply-To: <20260927-bcm2712-iommu-submit-v7-0-dfa2b975cbc9@reactivated.net> To: "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Daniel Drake Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, nick.hollinghurst@raspberrypi.com, james.quinlan@broadcom.com, Jason Gunthorpe X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=24058; i=dan@reactivated.net; h=from:subject:message-id; bh=Jnbl/XzcfRfkNN4vH5bvABW2ecsn36jX7MWS73GrFgA=; b=owEBbQKS/ZANAwAKAcPmj7FTFEe7AcsmYgBquRWFjGhKYMCLzAL1gCLG2iL146a+HKeetafZG jvSOJeBpTuJAjMEAAEKAB0WIQQ6Rf0sUP1iEhXfVfjD5o+xUxRHuwUCarkVhQAKCRDD5o+xUxRH u1I2D/wPRUl9d0kShvWKCXd1N7CEFvSVFEDoZogI4kGib5se810ruQyBdXSw5WQScUhhDRgwCvX 5Ivi4r35OJuQIelTLqO/1DCeW0byZSDW0b1cv46zSQSdOViwD+HXWAESrCexGiv3w/yEKjrv0L9 Zlg5609Eyyae5Uf5tQNwe9Hun3useTWsqEup4FbDPrD9Znsva78eQlfnYpdrebSmIKb9rIZJxr2 reDT5JJvUETfxZL+4tTN501tfSp7HfxkIwMzzZmvatE50wOUziUDU0ONN4A7EmD8keAJJR61jcE sqwr90hL3i3WRQmxByRcg+ISqvWS6/4q+9L1KX3+kyqBal+ykL/kgMu5tgKlSKTD6rh3SMVJrX1 Rim5Xo8TCLQMpqzH5nRabpe4Ifs84f5ib55im5HZ9jPTMPkJvQuMUOm3j0TSdWQTBgtYhAty/J0 C9n+26iKqKYzVRs36enpRBcRS4toircGjEgbRxL94GBsF2rg9QYngl1g4ZTfI7/eJu1/Gtf0RuS 5b7sxQpF/PV2WTFxhHy6lT3tATAgpCJm/2ffKPBklM5t5kJkUGGabFn2dkP7KvS7xZekrLHFA11 2waMkcVDY3kkMDs069yHYub/uE0Y2Wwh6n2B8Bq0F+k9tSAUsluxI8n3MyX/hMFYSHWKGcBUr+P KTut1CpLrcx6hqw== X-Developer-Key: i=dan@reactivated.net; a=openpgp; fpr=3A45FD2C50FD621215DF55F8C3E68FB1531447BB X-Endpoint-Received: by B4 Relay for dan@reactivated.net/default with auth_id=1070 X-Original-From: Daniel Drake Reply-To: dan@reactivated.net From: Daniel Drake This IOMMU translates memory access requests for the VC6 display pipeline and various multimedia devices in the Broadcom BCM2712 SoC used on Raspberry Pi 5. The driver uses the generic_pt framework to manage the 2-level page tables. It also provides support for the centralized L2 TLB (IOMMUC), which is shared across the SoC's IOMMU instances and must be flushed when modifying or unmapping page table entries. Adapted from Raspberry Pi's downstream bcm2712-iommu driver (original author Nick Hollinghurst). Reviewed-by: Jason Gunthorpe Signed-off-by: Daniel Drake --- MAINTAINERS | 12 + drivers/iommu/Kconfig | 15 + drivers/iommu/Makefile | 1 + drivers/iommu/bcm2712-iommu-cache.c | 84 ++++++ drivers/iommu/bcm2712-iommu-cache.h | 9 + drivers/iommu/bcm2712-iommu.c | 550 ++++++++++++++++++++++++++++++++= ++++ 6 files changed, 671 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 6215fcb07770..032401692efb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5166,6 +5166,18 @@ N: bcm2712 N: bcm283* N: raspberrypi =20 +BROADCOM BCM2712 IOMMU DRIVER +M: Daniel Drake +M: Florian Fainelli +M: Jim Quinlan +R: Broadcom internal kernel review list +L: iommu@lists.linux.dev +L: linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/iommu/brcm,bcm2712-iommu* +F: drivers/iommu/bcm2712-iommu* +F: drivers/iommu/generic_pt/fmt/*bcm2712* + BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITECTURE M: Florian Fainelli M: Ray Jui diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 6e07bd69467a..de85fba9c0a7 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -386,6 +386,21 @@ config VSI_IOMMU Say Y here if you want to use this IOMMU in front of these hardware blocks. =20 +config BCM2712_IOMMU + bool "BCM2712 IOMMU driver" + depends on (ARCH_BCM2835 && ARM64) || COMPILE_TEST + select IOMMU_API + select GENERIC_PT + select IOMMU_PT + select IOMMU_PT_BCM2712 + help + Support for IOMMU on BCM2712 SoC. This IOMMU can be used by the + display controller and various multimedia devices to perform + efficient memory management. + + Say Y here if you want to use this IOMMU in front of these + hardware blocks. + config IOMMU_DEBUG_PAGEALLOC bool "Debug IOMMU mappings against page allocations" depends on DEBUG_PAGEALLOC && IOMMU_API && PAGE_EXTENSION diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile index 2f05725eaab1..29a26d2a3af1 100644 --- a/drivers/iommu/Makefile +++ b/drivers/iommu/Makefile @@ -37,4 +37,5 @@ obj-$(CONFIG_IOMMU_IOPF) +=3D io-pgfault.o obj-$(CONFIG_SPRD_IOMMU) +=3D sprd-iommu.o obj-$(CONFIG_APPLE_DART) +=3D apple-dart.o obj-$(CONFIG_VSI_IOMMU) +=3D vsi-iommu.o +obj-$(CONFIG_BCM2712_IOMMU) +=3D bcm2712-iommu.o bcm2712-iommu-cache.o obj-$(CONFIG_IOMMU_DEBUG_PAGEALLOC) +=3D iommu-debug-pagealloc.o diff --git a/drivers/iommu/bcm2712-iommu-cache.c b/drivers/iommu/bcm2712-io= mmu-cache.c new file mode 100644 index 000000000000..8ed436943b83 --- /dev/null +++ b/drivers/iommu/bcm2712-iommu-cache.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * IOMMU driver for BCM2712 TLB cache + * + * Copyright (c) 2023 Raspberry Pi Ltd. + * Copyright (c) 2026 Daniel Drake + * + * The BCM2712 IOMMUC is a centralized TLB which accelerates address trans= lation + * across the SoC's IOMMU devices. If an address mapping is not found in t= he + * IOMMU's local TLB cache, then this IOMMUC is consulted. The IOMMUC must= be + * explicitly invalidated when modifying or unmapping IOMMU page tables. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "bcm2712-iommu-cache.h" + +struct bcm2712_iommu_cache { + struct device *dev; + spinlock_t hw_lock; + void __iomem *reg_base; +}; + +#define MMUC_CONTROL_ENABLE BIT(0) +#define MMUC_CONTROL_FLUSH BIT(1) +#define MMUC_CONTROL_FLUSHING BIT(2) + +void bcm2712_iommu_cache_flush(struct bcm2712_iommu_cache *cache) +{ + u32 val; + int ret; + + scoped_guard(spinlock_irqsave, &cache->hw_lock) { + writel(MMUC_CONTROL_ENABLE | MMUC_CONTROL_FLUSH, + cache->reg_base); + + ret =3D readl_poll_timeout_atomic(cache->reg_base, val, + !(val & MMUC_CONTROL_FLUSHING), + 0, 50); + } + + if (ret) + dev_err_ratelimited(cache->dev, "cache flush timed out\n"); +} + +static int bcm2712_iommu_cache_probe(struct platform_device *pdev) +{ + struct bcm2712_iommu_cache *cache; + + cache =3D devm_kzalloc(&pdev->dev, sizeof(*cache), GFP_KERNEL); + if (!cache) + return -ENOMEM; + + cache->dev =3D &pdev->dev; + spin_lock_init(&cache->hw_lock); + + cache->reg_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(cache->reg_base)) + return PTR_ERR(cache->reg_base); + + platform_set_drvdata(pdev, cache); + return 0; +} + +static const struct of_device_id bcm2712_iommu_cache_of_match[] =3D { + { .compatible =3D "brcm,bcm2712-iommuc" }, + { /* sentinel */ }, +}; + +static struct platform_driver bcm2712_iommu_cache_driver =3D { + .probe =3D bcm2712_iommu_cache_probe, + .driver =3D { + .name =3D "bcm2712-iommu-cache", + .of_match_table =3D bcm2712_iommu_cache_of_match, + .suppress_bind_attrs =3D true, + }, +}; +builtin_platform_driver(bcm2712_iommu_cache_driver); diff --git a/drivers/iommu/bcm2712-iommu-cache.h b/drivers/iommu/bcm2712-io= mmu-cache.h new file mode 100644 index 000000000000..d2f7851831cc --- /dev/null +++ b/drivers/iommu/bcm2712-iommu-cache.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _BCM2712_IOMMU_CACHE_H +#define _BCM2712_IOMMU_CACHE_H + +struct bcm2712_iommu_cache; + +void bcm2712_iommu_cache_flush(struct bcm2712_iommu_cache *cache); + +#endif diff --git a/drivers/iommu/bcm2712-iommu.c b/drivers/iommu/bcm2712-iommu.c new file mode 100644 index 000000000000..301855475c88 --- /dev/null +++ b/drivers/iommu/bcm2712-iommu.c @@ -0,0 +1,550 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * IOMMU driver for Broadcom BCM2712 + * + * Copyright (c) 2023-2025 Raspberry Pi Ltd. + * Copyright (c) 2026 Daniel Drake + * + * Each BCM2712 IOMMU has multiple devices hardwired into it, whose + * DMA transactions all route through the IOMMU. There is no stream ID tag= ging + * or any other kind of segmentation to differentiate between requests from + * different devices. It is also not possible to toggle a specific device + * between iommu-mapped and bypass modes. + * + * The hardware supports the simultaneous configuration of a bypass window + * (where memory accesses operate in identity mode) and a translation aper= ture + * (supporting page mapping). While combining these two would allow for + * GART-like operation, this driver's paging domain implementation configu= res + * only the translation aperture (starting at IOVA 0) offering a degree of + * memory protection. + * + * The page table format is a two-level format handled by generic_pt/bcm27= 12. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "bcm2712-iommu-cache.h" +#include "dma-iommu.h" +#include "iommu-pages.h" + +/* BCM2712 IOMMU is organized around 4Kbyte pages */ +#define IOMMU_PAGE_SHIFT 12 +#define IOMMU_PAGE_SIZE (1ul << IOMMU_PAGE_SHIFT) +/* A PTE is 4 bytes */ +#define PTE_SIZE_SHIFT 2 +/* L1/L2 table sizing (IOMMU hardware pages): 1024 entries per page */ +#define PTES_PER_IOPG_SHIFT (IOMMU_PAGE_SHIFT - PTE_SIZE_SHIFT) + +#define MMMU_CTRL_OFFSET 0x00 +#define MMMU_CTRL_CAP_EXCEEDED BIT(27) +#define MMMU_CTRL_CAP_EXCEEDED_ABORT_EN BIT(26) +#define MMMU_CTRL_CAP_EXCEEDED_INT_EN BIT(25) +#define MMMU_CTRL_CAP_EXCEEDED_EXCEPTION_EN BIT(24) +#define MMMU_CTRL_PT_INVALID BIT(20) +#define MMMU_CTRL_PT_INVALID_ABORT_EN BIT(19) +#define MMMU_CTRL_PT_INVALID_INT_EN BIT(18) +#define MMMU_CTRL_PT_INVALID_EXCEPTION_EN BIT(17) +#define MMMU_CTRL_PT_INVALID_EN BIT(16) +#define MMMU_CTRL_WRITE_VIOLATION BIT(12) +#define MMMU_CTRL_WRITE_VIOLATION_ABORT_EN BIT(11) +#define MMMU_CTRL_WRITE_VIOLATION_INT_EN BIT(10) +#define MMMU_CTRL_WRITE_VIOLATION_EXCEPTION_EN BIT(9) +#define MMMU_CTRL_BYPASS BIT(8) +#define MMMU_CTRL_TLB_CLEARING BIT(7) +#define MMMU_CTRL_STATS_CLEAR BIT(3) +#define MMMU_CTRL_TLB_CLEAR BIT(2) +#define MMMU_CTRL_STATS_ENABLE BIT(1) +#define MMMU_CTRL_ENABLE BIT(0) + +#define MMMU_CTRL_OPERATING_FLAGS (\ + MMMU_CTRL_CAP_EXCEEDED_ABORT_EN | \ + MMMU_CTRL_PT_INVALID_ABORT_EN | \ + MMMU_CTRL_PT_INVALID_EN | \ + MMMU_CTRL_WRITE_VIOLATION_ABORT_EN | \ + MMMU_CTRL_STATS_ENABLE | \ + MMMU_CTRL_ENABLE) + +#define MMMU_PT_PA_BASE_OFFSET 0x04 + +#define MMMU_ADDR_CAP_OFFSET 0x14 +#define MMMU_ADDR_CAP_ENABLE BIT(31) +#define ADDR_CAP_SHIFT ilog2(SZ_256M) + +#define MMMU_SHOOT_DOWN_OFFSET 0x18 +#define MMMU_SHOOT_DOWN_SHOOTING BIT(31) +#define MMMU_SHOOT_DOWN_SHOOT BIT(30) + +#define MMMU_BYPASS_START_OFFSET 0x1c +#define MMMU_BYPASS_START_ENABLE BIT(31) + +#define MMMU_BYPASS_END_OFFSET 0x20 +#define MMMU_BYPASS_END_ENABLE BIT(31) + +#define MMMU_MISC_OFFSET 0x24 +#define MMMU_MISC_SINGLE_TABLE BIT(31) + +#define MMMU_ILLEGAL_ADR_OFFSET 0x30 +#define MMMU_ILLEGAL_ADR_ENABLE BIT(31) + +#define MMMU_DEBUG_INFO_OFFSET 0x38 +#define MMMU_DEBUG_INFO_VERSION_MASK 0x0000000Fu +#define MMMU_DEBUG_INFO_VA_WIDTH_MASK 0x000000F0u +#define MMMU_DEBUG_INFO_PA_WIDTH_MASK 0x00000F00u +#define MMMU_DEBUG_INFO_BIGPAGE_WIDTH_MASK 0x000FF000u +#define MMMU_DEBUG_INFO_SUPERPAGE_WIDTH_MASK 0x0FF00000u +#define MMMU_DEBUG_INFO_BYPASS_4M BIT(28) +#define MMMU_DEBUG_INFO_BYPASS BIT(29) + +struct bcm2712_iommu { + struct device *dev; + struct iommu_device iommu; + struct bcm2712_iommu_domain *domain; + struct bcm2712_iommu_cache *cache; + void __iomem *reg_base; + spinlock_t hw_lock; + size_t bigpage_size; + size_t superpage_size; +}; + +struct bcm2712_iommu_domain { + union { + struct iommu_domain base; + struct pt_iommu_bcm2712 pt; + }; + struct bcm2712_iommu *mmu; + void *default_page; +}; + +static inline void bcm2712_iommu_writel(struct bcm2712_iommu *mmu, + unsigned int offset, u32 val) +{ + writel(val, mmu->reg_base + offset); +} + +static inline u32 bcm2712_iommu_readl(struct bcm2712_iommu *mmu, + unsigned int offset) +{ + return readl(mmu->reg_base + offset); +} + +static struct bcm2712_iommu_domain * +to_bcm2712_domain(struct iommu_domain *domain) +{ + return container_of(domain, struct bcm2712_iommu_domain, base); +} + +static void bcm2712_iommu_init(struct bcm2712_iommu *mmu) +{ + unsigned int bigpage_width, superpage_width; + u32 u =3D bcm2712_iommu_readl(mmu, MMMU_DEBUG_INFO_OFFSET); + u32 pa_width =3D FIELD_GET(MMMU_DEBUG_INFO_PA_WIDTH_MASK, u); + + dev_dbg(mmu->dev, "DEBUG_INFO =3D 0x%08x\n", u); + WARN_ON(FIELD_GET(MMMU_DEBUG_INFO_VERSION_MASK, u) < 4 || + FIELD_GET(MMMU_DEBUG_INFO_VA_WIDTH_MASK, u) < 6 || + pa_width < 6 || !(u & MMMU_DEBUG_INFO_BYPASS)); + + dma_set_mask_and_coherent(mmu->dev, DMA_BIT_MASK(pa_width + 30u)); + + bigpage_width =3D FIELD_GET(MMMU_DEBUG_INFO_BIGPAGE_WIDTH_MASK, u); + if (bigpage_width) + mmu->bigpage_size =3D IOMMU_PAGE_SIZE << bigpage_width; + + superpage_width =3D FIELD_GET(MMMU_DEBUG_INFO_SUPERPAGE_WIDTH_MASK, u); + if (superpage_width) + mmu->superpage_size =3D IOMMU_PAGE_SIZE << superpage_width; + + /* Disable MMU and clear sticky flags */ + bcm2712_iommu_writel(mmu, MMMU_CTRL_OFFSET, + MMMU_CTRL_CAP_EXCEEDED | MMMU_CTRL_PT_INVALID | + MMMU_CTRL_WRITE_VIOLATION | + MMMU_CTRL_STATS_CLEAR); + + /* Put MMU into 2-level mode */ + bcm2712_iommu_writel(mmu, MMMU_MISC_OFFSET, + bcm2712_iommu_readl(mmu, MMMU_MISC_OFFSET) & + ~MMMU_MISC_SINGLE_TABLE); +} + +static int bcm2712_iommu_identity_attach(struct iommu_domain *identity_dom= ain, + struct device *dev, + struct iommu_domain *old) +{ + struct bcm2712_iommu *mmu =3D dev_iommu_priv_get(dev); + + guard(spinlock_irqsave)(&mmu->hw_lock); + bcm2712_iommu_writel(mmu, MMMU_CTRL_OFFSET, 0); + mmu->domain =3D NULL; + + return 0; +} + +static struct iommu_domain bcm2712_identity_domain =3D { + .type =3D IOMMU_DOMAIN_IDENTITY, + .ops =3D &(const struct iommu_domain_ops) { + .attach_dev =3D bcm2712_iommu_identity_attach, + }, +}; + +static int bcm2712_iommu_clear_and_enable(struct bcm2712_iommu *mmu) + __must_hold(&mmu->hw_lock) +{ + u32 val; + + bcm2712_iommu_cache_flush(mmu->cache); + bcm2712_iommu_writel(mmu, MMMU_CTRL_OFFSET, + MMMU_CTRL_OPERATING_FLAGS | MMMU_CTRL_TLB_CLEAR); + return readl_poll_timeout_atomic(mmu->reg_base + MMMU_CTRL_OFFSET, val, + !(val & MMMU_CTRL_TLB_CLEARING), 0, + 50); +} + + +static int bcm2712_iommu_attach_dev(struct iommu_domain *domain, + struct device *dev, + struct iommu_domain *old) +{ + struct bcm2712_iommu *mmu =3D dev_iommu_priv_get(dev); + struct bcm2712_iommu_domain *mydomain =3D to_bcm2712_domain(domain); + struct pt_iommu_bcm2712_hw_info info; + u32 default_page_pfn; + int ret =3D 0; + + /* all attached devices must belong to the same IOMMU instance */ + if (mydomain->mmu !=3D mmu) + return -EINVAL; + + scoped_guard(spinlock_irqsave, &mmu->hw_lock) { + if (mmu->domain =3D=3D mydomain) + break; + + /* Configure translation aperture */ + bcm2712_iommu_writel(mmu, MMMU_ADDR_CAP_OFFSET, + MMMU_ADDR_CAP_ENABLE | + (domain->geometry.aperture_end >> + ADDR_CAP_SHIFT)); + + /* + * When the IOMMU handles a request, it adds the + * PT_PA_BASE_OFFSET to (IOVA>>32) to calculate the PFN of the + * corresponding L1 directory page. + * IOVA bits [31:22] are then used to fetch the L1 descriptor + * within (which in turn points to the L2 table). + * This clever logic would allow for a L1 table larger than 4kb + * (and hence a larger aperture). + */ + pt_iommu_bcm2712_hw_info(&mydomain->pt, &info); + bcm2712_iommu_writel(mmu, MMMU_PT_PA_BASE_OFFSET, + info.pt_base >> IOMMU_PAGE_SHIFT); + + /* Disable bypass window */ + bcm2712_iommu_writel(mmu, MMMU_BYPASS_START_OFFSET, 0); + bcm2712_iommu_writel(mmu, MMMU_BYPASS_END_OFFSET, 0); + + /* + * A default (error) page is used to catch illegal reads/writes. + */ + default_page_pfn =3D virt_to_phys(mydomain->default_page) >> + IOMMU_PAGE_SHIFT; + bcm2712_iommu_writel(mmu, MMMU_ILLEGAL_ADR_OFFSET, + MMMU_ILLEGAL_ADR_ENABLE | + default_page_pfn); + + ret =3D bcm2712_iommu_clear_and_enable(mmu); + if (ret) { + bcm2712_iommu_writel(mmu, MMMU_CTRL_OFFSET, 0); + mmu->domain =3D NULL; + break; + } + + mmu->domain =3D mydomain; + } + + if (ret) + dev_err_ratelimited(mmu->dev, + "TLB clear timed out during attach\n"); + + return ret; +} + +static int bcm2712_iommu_shootdown_range(struct bcm2712_iommu *mmu, + unsigned long iova, size_t size) + __must_hold(&mmu->hw_lock) +{ + unsigned long start_pfn =3D iova >> IOMMU_PAGE_SHIFT; + unsigned long end_pfn =3D (iova + size - 1) >> IOMMU_PAGE_SHIFT; + unsigned long pfn; + u32 val; + int ret; + + /* Shootdown register deals with 4 pages at a time */ + for (pfn =3D round_down(start_pfn, 4); pfn <=3D end_pfn; pfn +=3D 4) { + bcm2712_iommu_writel(mmu, MMMU_SHOOT_DOWN_OFFSET, + MMMU_SHOOT_DOWN_SHOOT | pfn); + ret =3D readl_poll_timeout_atomic( + mmu->reg_base + MMMU_SHOOT_DOWN_OFFSET, val, + !(val & MMMU_SHOOT_DOWN_SHOOTING), 0, 50); + if (ret) + return ret; + } + + return 0; +} + +static int bcm2712_iommu_sync_range(struct iommu_domain *domain, + unsigned long iova, size_t size) +{ + struct bcm2712_iommu_domain *mydomain =3D to_bcm2712_domain(domain); + struct bcm2712_iommu *mmu =3D mydomain->mmu; + int ret =3D 0; + + if (!size) + return 0; + + scoped_guard(spinlock_irqsave, &mmu->hw_lock) { + if (mmu->domain !=3D mydomain) + return 0; + + /* If invalidating more than 1MB, just do a full TLB clear */ + if (size >=3D SZ_1M) { + ret =3D bcm2712_iommu_clear_and_enable(mmu); + } else { + bcm2712_iommu_cache_flush(mmu->cache); + ret =3D bcm2712_iommu_shootdown_range(mmu, iova, size); + } + } + + if (ret) + dev_err_ratelimited(mmu->dev, + "TLB sync timed out (size=3D%#zx)\n", size); + + return ret; +} + +static void bcm2712_iommu_sync(struct iommu_domain *domain, + struct iommu_iotlb_gather *gather) +{ + bcm2712_iommu_sync_range(domain, gather->start, + gather->end - gather->start + 1); + iommu_put_pages_list(&gather->freelist); +} + +static int bcm2712_iommu_sync_map(struct iommu_domain *domain, + unsigned long iova, size_t size) +{ + return bcm2712_iommu_sync_range(domain, iova, size); +} + +static void bcm2712_iommu_sync_all(struct iommu_domain *domain) +{ + size_t aperture_size =3D domain->geometry.aperture_end - + domain->geometry.aperture_start + 1; + + bcm2712_iommu_sync_range(domain, domain->geometry.aperture_start, + aperture_size); +} + +static void bcm2712_iommu_domain_free(struct iommu_domain *domain) +{ + struct bcm2712_iommu_domain *mydomain =3D to_bcm2712_domain(domain); + struct bcm2712_iommu *mmu =3D mydomain->mmu; + + scoped_guard(spinlock_irqsave, &mmu->hw_lock) { + if (mmu->domain =3D=3D mydomain) { + bcm2712_iommu_writel(mmu, MMMU_CTRL_OFFSET, 0); + mmu->domain =3D NULL; + } + } + + pt_iommu_deinit(&mydomain->pt.iommu); + if (mydomain->default_page) + iommu_free_pages(mydomain->default_page); + kfree(mydomain); +} + +static const struct iommu_domain_ops bcm2712_paging_domain_ops =3D { + IOMMU_PT_DOMAIN_OPS(bcm2712), + .attach_dev =3D bcm2712_iommu_attach_dev, + .iotlb_sync =3D bcm2712_iommu_sync, + .iotlb_sync_map =3D bcm2712_iommu_sync_map, + .flush_iotlb_all =3D bcm2712_iommu_sync_all, + .free =3D bcm2712_iommu_domain_free, +}; + +static struct iommu_domain *bcm2712_iommu_domain_alloc(struct device *dev) +{ + struct bcm2712_iommu *mmu =3D dev_iommu_priv_get(dev); + struct bcm2712_iommu_domain *domain; + struct pt_iommu_bcm2712_cfg cfg =3D {}; + int ret; + + domain =3D kzalloc_obj(*domain); + if (!domain) + return NULL; + + domain->mmu =3D mmu; + domain->pt.iommu.iommu_device =3D mmu->dev; + cfg.common.features =3D BIT(PT_FEAT_DMA_INCOHERENT); + + /* Bigpage and superpage sizes are typically 64K and 1M, but may vary */ + if (mmu->bigpage_size) + cfg.bigpage_lg2 =3D ilog2(mmu->bigpage_size); + if (mmu->superpage_size) + cfg.superpage_lg2 =3D ilog2(mmu->superpage_size); + + /* 2-level format: 10-bit L1 + 10-bit L2 + 12-bit page offset */ + cfg.common.hw_max_vasz_lg2 =3D + (2 * PTES_PER_IOPG_SHIFT) + IOMMU_PAGE_SHIFT; + + /* PTEs encode a 25-bit output address PFN */ + cfg.common.hw_max_oasz_lg2 =3D 25 + IOMMU_PAGE_SHIFT; + + ret =3D pt_iommu_bcm2712_init(&domain->pt, &cfg, GFP_KERNEL); + if (ret) + goto err; + + /* Set up a default (error) page used to catch illegal reads/writes */ + domain->default_page =3D iommu_alloc_pages_sz(GFP_KERNEL, PAGE_SIZE); + if (!domain->default_page) + goto err; + + domain->base.ops =3D &bcm2712_paging_domain_ops; + return &domain->base; + +err: + bcm2712_iommu_domain_free(&domain->base); + return NULL; +} + +static struct bcm2712_iommu * +bcm2712_iommu_get_by_fwnode(struct fwnode_handle *fwnode) +{ + struct device *dev __free(put_device) =3D + bus_find_device_by_fwnode(&platform_bus_type, fwnode); + + return dev ? dev_get_drvdata(dev) : NULL; +} + +static struct iommu_device *bcm2712_iommu_probe_device(struct device *dev) +{ + struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev); + struct bcm2712_iommu *mmu; + + if (!fwspec || !fwspec->iommu_fwnode) + return ERR_PTR(-ENODEV); + + mmu =3D bcm2712_iommu_get_by_fwnode(fwspec->iommu_fwnode); + if (!mmu) + return ERR_PTR(-ENODEV); + + dev_iommu_priv_set(dev, mmu); + + return &mmu->iommu; +} + +static int bcm2712_iommu_of_xlate(struct device *dev, + const struct of_phandle_args *args) +{ + return iommu_fwspec_add_ids(dev, args->args, 0); +} + +static const struct iommu_ops bcm2712_iommu_ops =3D { + .identity_domain =3D &bcm2712_identity_domain, + .domain_alloc_paging =3D bcm2712_iommu_domain_alloc, + .probe_device =3D bcm2712_iommu_probe_device, + .device_group =3D generic_single_device_group, + .get_resv_regions =3D iommu_dma_get_resv_regions, + .of_xlate =3D bcm2712_iommu_of_xlate, +}; + +static const struct of_device_id bcm2712_iommu_of_match[] =3D { + { .compatible =3D "brcm,bcm2712-iommu" }, + { /* sentinel */ } +}; + +static int bcm2712_iommu_init_cache(struct bcm2712_iommu *mmu, + struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + + struct device_node *cache_np __free(device_node) =3D + of_parse_phandle(dev->of_node, "brcm,iommu-cache", 0); + if (!cache_np) + return dev_err_probe(dev, -ENOENT, + "missing brcm,iommu-cache property\n"); + + struct platform_device *cache_pdev __free(platform_device_put) =3D + of_find_device_by_node(cache_np); + if (!cache_pdev) + return dev_err_probe(dev, -EPROBE_DEFER, + "waiting for cache device\n"); + + mmu->cache =3D platform_get_drvdata(cache_pdev); + if (!mmu->cache) + return dev_err_probe(dev, -EPROBE_DEFER, + "waiting for cache driver probe\n"); + + return 0; +} + +static int bcm2712_iommu_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct bcm2712_iommu *mmu; + int ret; + + mmu =3D devm_kzalloc(dev, sizeof(*mmu), GFP_KERNEL); + if (!mmu) + return -ENOMEM; + + mmu->dev =3D dev; + spin_lock_init(&mmu->hw_lock); + + mmu->reg_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(mmu->reg_base)) + return PTR_ERR(mmu->reg_base); + + ret =3D bcm2712_iommu_init_cache(mmu, pdev); + if (ret) + return ret; + + platform_set_drvdata(pdev, mmu); + bcm2712_iommu_init(mmu); + + ret =3D iommu_device_sysfs_add(&mmu->iommu, dev, NULL, "%s", + dev_name(dev)); + if (ret) + return ret; + + ret =3D iommu_device_register(&mmu->iommu, &bcm2712_iommu_ops, dev); + if (ret) { + iommu_device_sysfs_remove(&mmu->iommu); + return ret; + } + + return 0; +} + +static struct platform_driver bcm2712_iommu_driver =3D { + .driver =3D { + .name =3D "bcm2712-iommu", + .of_match_table =3D bcm2712_iommu_of_match, + .suppress_bind_attrs =3D true, + }, + .probe =3D bcm2712_iommu_probe, +}; +builtin_platform_driver(bcm2712_iommu_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Daniel Drake "); +MODULE_DESCRIPTION("Broadcom BCM2712 IOMMU driver"); --=20 2.55.0 From nobody Mon Sep 28 05:45:36 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F3E183F0ABB; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260927-bcm2712-iommu-submit-v7-6-dfa2b975cbc9@reactivated.net> References: <20260927-bcm2712-iommu-submit-v7-0-dfa2b975cbc9@reactivated.net> In-Reply-To: <20260927-bcm2712-iommu-submit-v7-0-dfa2b975cbc9@reactivated.net> To: "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Daniel Drake Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, nick.hollinghurst@raspberrypi.com, james.quinlan@broadcom.com, Jason Gunthorpe X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1369; i=dan@reactivated.net; h=from:subject:message-id; bh=XBvii0RwgTrT6cNpYro0FFGvRHg/uhSq0N5Er7AlhA0=; b=owEBbQKS/ZANAwAKAcPmj7FTFEe7AcsmYgBquRWFPaa7eS2gaq7AaVkTNnJd3emegf2BGGFmh DbZWcB33gKJAjMEAAEKAB0WIQQ6Rf0sUP1iEhXfVfjD5o+xUxRHuwUCarkVhQAKCRDD5o+xUxRH u1NeD/9L4Ly19FTjEUwHyNtmNCGMek+IcasBl2ei3pQ7W+9n+d3K+vxo+T1AbiIhbNf1R9ete+s HppNG1FouO3OgwNaCj+TEuR1bVk6bJvS+3hotqwZ2O10QYk1/asgVEadpFBSk5khKBp0DqUwv+m kvQgplx/pY1lIgDH0cer18bnpByb13Cw6e2/C93Tf4UmWuEm4grYsz1mG3EreJzVOFntwXD5g/L YJVAc5nVreB2RiuSzQnGK7r/yHN83+QTrwM5vzXHLTsoUpxGHVphIZY86LYSqpzgzqvQdUDowjJ I5srYJlaawFcwVDkKCqeVSurf95/51YmcG2N4KvbW6iHDme29UoOFIeywhX2RlkIwo+KNWo1b8C fnAtNT0NvGFcTDOHmRayRQfK6/rx6dYML0RivLrN5FMSGUvTShrCvM1C3ps0OfpVKR6Wx7JP3BL ef5O6li/p6PfUwdoJSq7dhX11m9T66gfWGNa5EClRY9kHOH0iCPnKgTn/U87pf89COQfevljPG1 T7NbCbZ7U05Y4la2IKOfIvEUyuLSfFKBLrWYXgfWyqJuSjBDt7pKT1ZvXKt3UytC1CbeI1rw0gc wC0N1AtlwFIfhdYpGsPJyBssCVCud5aB5tl4KVFqe954JCR+nfmfL9fNZzmOXWapuGjK0hsxJfl Dd6icagzsN5qV6Q== X-Developer-Key: i=dan@reactivated.net; a=openpgp; fpr=3A45FD2C50FD621215DF55F8C3E68FB1531447BB X-Endpoint-Received: by B4 Relay for dan@reactivated.net/default with auth_id=1070 X-Original-From: Daniel Drake Reply-To: dan@reactivated.net From: Daniel Drake Define the IOMMU and IOMMUC nodes for the Broadcom BCM2712 SoC found in the Raspberry Pi 5. Enable use of the IOMMU for the HVS device that handles memory allocations for the display block. Signed-off-by: Daniel Drake --- arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dt= s/broadcom/bcm2712.dtsi index 45aa8ec5e2b1..aca9e0e3a874 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -626,6 +626,19 @@ pcie2: pcie@1000120000 { status =3D "disabled"; }; =20 + iommu4: iommu@1000005200 { + /* IOMMU for VC4 (HVS & MPL/TXP), Unicam, PISP-FE, MiniBVN */ + compatible =3D "brcm,bcm2712-iommu"; + reg =3D <0x10 0x5200 0x0 0x80>; + #iommu-cells =3D <0>; + brcm,iommu-cache =3D <&iommuc>; + }; + + iommuc: iommuc@1000005b00 { + compatible =3D "brcm,bcm2712-iommuc"; + reg =3D <0x10 0x5b00 0x0 0x80>; + }; + mip0: msi-controller@1000130000 { compatible =3D "brcm,bcm2712-mip"; reg =3D <0x10 0x00130000 0x00 0xc0>, @@ -701,5 +714,6 @@ hvs: hvs@107c580000 { interrupt-parent =3D <&disp_intr>; interrupts =3D <2>, <9>, <16>; interrupt-names =3D "ch0-eof", "ch1-eof", "ch2-eof"; + iommus =3D <&iommu4>; }; }; --=20 2.55.0