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The non-pixel stream cannot address the low 600MB of IOVA space, while the pixel stream can address the full range: +-----------------------------------------------------------+ | non-pixel stream addressable range (600 MB - 3.5 GB) | | 0x25800000 - 0xe0000000 | +-----------------------------------------------------------+ | pixel stream addressable range (0 - 3.5 GB) | | 0x00000000 - 0xe0000000 | +-----------------------------------------------------------+ A single "iommus" property on the video-codec node puts every stream in one IOMMU domain sharing one IOVA allocator, so nothing restricts a non-pixel buffer to avoid 0 to 600MB. Once an allocation lands below that boundary the hardware faults, which shows up as unhandled SMMU page faults and spontaneous reboots: https://gitlab.freedesktop.org/drm/msm/-/work_items/100 Given that the address range restriction is for specific VPU stream, it should be ideally be moved to that stream. To achieve the same, a subset of streams is now represented as subnodes, so that each can be associated with its respective addressable range. The design was discussed and agreed by mainatiners here https://lore.kernel.org/all/c7b956a9-d3e8-4e18-b780-5d08f5cd2ca1@kernel.org In the past, this limitation was addressed with an iommu-map approach, with the iris driver dynamically creating the devices. That approach was later concluded to be a hack to avoid having subnodes, and was NAKed by the iommu maintainers. It was discussed in detail here: https://lore.kernel.org/all/c7b956a9-d3e8-4e18-b780-5d08f5cd2ca1@kernel.org/ "iommu-ranges" on the subnode describes the *allowed* IOVA range that stream is allowed to use, so the IOVA is allocated from the specified range only. Define all the possible subnodes so as to describe all the VPU hardware iommu interfaces, both secure as well as non secure. address-cells, size-cells and dma-ranges declares the 1:1 DMA translation into the parent. The parent "iommus" is kept as an alternative via "oneOf", so platforms that have not been converted to subnodes still validate. New platforms should use the subnode form. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Vikash Garodia --- .../bindings/media/qcom,sc7180-venus.yaml | 15 ---- .../bindings/media/qcom,venus-common.yaml | 97 ++++++++++++++++++= ++++ 2 files changed, 97 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml= b/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml index b21bed314848480b82153e49602f0b19e08e7335..bfd8b1ad473128c974bce84639c= b0aff59d8c2cc 100644 --- a/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml @@ -91,21 +91,6 @@ properties: deprecated: true additionalProperties: false =20 - video-firmware: - type: object - additionalProperties: false - - description: | - Firmware subnode is needed when the platform does not - have TrustZone. - - properties: - iommus: - maxItems: 1 - - required: - - iommus - required: - compatible - power-domain-names diff --git a/Documentation/devicetree/bindings/media/qcom,venus-common.yaml= b/Documentation/devicetree/bindings/media/qcom,venus-common.yaml index 59a3fde846d2196ab1e4588eb396012ba6860712..68d5e592a028c5eecde04ce72cd= 5ae6815ba5c82 100644 --- a/Documentation/devicetree/bindings/media/qcom,venus-common.yaml +++ b/Documentation/devicetree/bindings/media/qcom,venus-common.yaml @@ -47,6 +47,93 @@ properties: minItems: 1 maxItems: 4 =20 + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + dma-ranges: + maxItems: 1 + + non-pixel: + type: object + description: + Context bank for VPU non-pixel buffers, including compressed and int= ernal buffers. + additionalProperties: false + + properties: + iommus: + maxItems: 1 + iommu-ranges: + maxItems: 1 + required: + - iommus + - iommu-ranges + + pixel: + type: object + description: + Context bank for VPU pixel buffers containing uncompressed video dat= a. + additionalProperties: false + + properties: + iommus: + maxItems: 1 + required: + - iommus + + video-firmware: + type: object + description: + Context bank for the VPU firmware processing domain. + additionalProperties: false + + properties: + iommus: + maxItems: 1 + required: + - iommus + + secure-non-pixel: + type: object + description: + Context bank for VPU secure non-pixel buffers. + additionalProperties: false + + properties: + iommus: + maxItems: 1 + iommu-ranges: + maxItems: 1 + required: + - iommus + - iommu-ranges + + secure-pixel: + type: object + description: + Context bank for VPU secure pixel buffers containing uncompressed vi= deo data. + additionalProperties: false + + properties: + iommus: + maxItems: 1 + required: + - iommus + + secure-bitstream: + type: object + description: + Context bank for VPU secure bitstream buffers containing compressed = video data. + additionalProperties: false + + properties: + iommus: + maxItems: 1 + required: + - iommus + required: - reg - clocks @@ -55,4 +142,14 @@ required: - memory-region - power-domains =20 +oneOf: + - required: + - iommus + - required: + - '#address-cells' + - '#size-cells' + - dma-ranges + - non-pixel + - pixel + additionalProperties: true --=20 2.34.1 From nobody Fri Oct 2 11:44:04 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D7C23921DB for ; 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The non-pixel stream cannot address the low 600MB of IOVA space, while the pixel stream can address the full range: +-----------------------------------------------------------+ | non-pixel stream addressable range (600 MB - 3.5 GB) | | 0x25800000 - 0xe0000000 | +-----------------------------------------------------------+ | pixel stream addressable range (0 - 3.5 GB) | | 0x00000000 - 0xe0000000 | +-----------------------------------------------------------+ A single "iommus" property on the video-codec node puts every stream in one IOMMU domain sharing one IOVA allocator, so nothing restricts a non-pixel buffer to avoid 0 to 600MB. Once an allocation lands below that boundary the hardware faults, which shows up as unhandled SMMU page faults and spontaneous reboots: https://gitlab.freedesktop.org/drm/msm/-/work_items/100 Given that the address range restriction is for specific VPU stream, it should be ideally be moved to that stream. To achieve the same, a subset of streams is now represented as subnodes, so that each can be associated with its respective addressable range. The design was discussed and agreed by mainatiners here https://lore.kernel.org/all/c7b956a9-d3e8-4e18-b780-5d08f5cd2ca1@kernel.org In the past, this limitation was addressed with an iommu-map approach, with the iris driver dynamically creating the devices. That approach was later concluded to be a hack to avoid having subnodes, and was NAKed by the iommu maintainers. It was discussed in detail here: https://lore.kernel.org/all/c7b956a9-d3e8-4e18-b780-5d08f5cd2ca1@kernel.org/ Update example to the subnode form. Doing so, it picks up the supporting properties needed on the video-codec node, address-cells, size-cells and dma-ranges to declare 1:1 DMA translation into the parent. Reviewed-by: Krzysztof Kozlowski Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- .../devicetree/bindings/media/qcom,sm8550-iris.yaml | 17 +++++++++++++= +--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml = b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml index 0400ca1bff05dcef6b742c3fbf77e38adca9f280..6ee9d23554cffb30c92017ef99d= e15c2493455ac 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml @@ -98,10 +98,10 @@ required: - interconnect-names - resets - reset-names - - iommus - dma-coherent =20 allOf: + - $ref: qcom,venus-common.yaml# - if: properties: compatible: @@ -177,12 +177,23 @@ examples: resets =3D <&gcc GCC_VIDEO_AXI0_CLK_ARES>; reset-names =3D "bus"; =20 - iommus =3D <&apps_smmu 0x1940 0x0000>, - <&apps_smmu 0x1947 0x0000>; dma-coherent; =20 operating-points-v2 =3D <&iris_opp_table>; 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a=ed25519-sha256; t=1790404457; l=3890; i=vikash.garodia@oss.qualcomm.com; s=20241104; h=from:subject:message-id; bh=PnAbHBLCBhwxjoECu5HtUTAmt7Aan6lX4I7y/GynILA=; b=966U/Cf9rqiDOeyw2sHM5srfNuYx9ZLAtNA2e0HDMDSJ4mum8d5koMqmF8TD2r6GQWP7BIXzm AzgrNKWcB5UDlJxMaXwmtC2wx5yPgmWgCmeRJlzePWVN83NDV5ooRQc X-Developer-Key: i=vikash.garodia@oss.qualcomm.com; a=ed25519; pk=LY9Eqp4KiHWxzGNKGHbwRFEJOfRCSzG/rxQNmvZvaKE= X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI2MDAyNiBTYWx0ZWRfXxdwns3Nh9B34 wNVwBKyUx3/6KtcJZI2zTdOBD+P27gsrkmGPD7z/r2+6HDKzq81kKw2tG5C2Axax2xeZ9NyJcoE T2OSGpKFOfiLIpVhhXjFXU2V2et+KJw= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI2MDAyNiBTYWx0ZWRfXx25D2BWNezLV sxjYZf3wityC8E74z2pVkqPuvEv73Uf2mdg3aiLiAbul3zZu9BiPJ2rmlWva7Ie95F46zD4NEEF YP5/znGKbG2uFIWharafSMdZ0GaUEinGfLb52QbY6knx9Ho+ETQb41wzFdFL/uclc8mXkzTGOos T5AuX2ea4lKRYZWwayZtMViTVGuiVI1KlKD90zMvUiMn9GTREQQ+qWALGZ80B7WUsNF79L6i+gx TuNNbJv/XFq11t+nFNnNgqcaWet41o/NKjjDcXE6DNNBPyM5OOH5vopsfyed0edvyHMIfgZz/iC Iqu2CSqZEI1pxiSCNA3MVtyeYmHLCz410neww94NbCA8FgZOO+Sy2ByI04dYGUBoMWuBdUeOmAw uFlOW01VV3+HkShnvMt/00z4jH8/KNlILXrDYR48zUKkgpHQgjz3MHE9ZkJbX95wF0c9oemsscp IZ6JPHmDPz16SjRqwkA== X-Proofpoint-GUID: RQf7H0cf5Oe9QltF0hY-Mu0vrBSP9Eds X-Proofpoint-ORIG-GUID: RQf7H0cf5Oe9QltF0hY-Mu0vrBSP9Eds X-Authority-Analysis: v=2.4 cv=K6G3jCWI c=1 sm=1 tr=0 ts=6ab7678c cx=c_pps a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=e5mUnYsNAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=w7pRem5UOBajBC5HA0sA:9 a=QEXdDO2ut3YA:10 a=vBUdepa8ALXHeOFLBtFW:22 a=Vxmtnl_E_bksehYqCbjh:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 adultscore=0 priorityscore=1501 impostorscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609260026 The VPU issues DMA through several SMMU streams, and the hardware does not give every stream the same addressable range. The non-pixel stream cannot address the low 600MB of IOVA space, while the pixel stream can address the full range: +-----------------------------------------------------------+ | non-pixel stream addressable range (600 MB - 3.5 GB) | | 0x25800000 - 0xe0000000 | +-----------------------------------------------------------+ | pixel stream addressable range (0 - 3.5 GB) | | 0x00000000 - 0xe0000000 | +-----------------------------------------------------------+ A single "iommus" property on the video-codec node puts every stream in one IOMMU domain sharing one IOVA allocator, so nothing restricts a non-pixel buffer to avoid 0 to 600MB. Once an allocation lands below that boundary the hardware faults, which shows up as unhandled SMMU page faults and spontaneous reboots: https://gitlab.freedesktop.org/drm/msm/-/work_items/100 Given that the address range restriction is for specific VPU stream, it should be ideally be moved to that stream. To achieve the same, a subset of streams is now represented as subnodes, so that each can be associated with its respective addressable range. The design was discussed and agreed by mainatiners here https://lore.kernel.org/all/c7b956a9-d3e8-4e18-b780-5d08f5cd2ca1@kernel.org In the past, this limitation was addressed with an iommu-map approach, with the iris driver dynamically creating the devices. That approach was later concluded to be a hack to avoid having subnodes, and was NAKed by the iommu maintainers. It was discussed in detail here: https://lore.kernel.org/all/c7b956a9-d3e8-4e18-b780-5d08f5cd2ca1@kernel.org/ Update example to the subnode form. Doing so, it picks up the supporting properties needed on the video-codec node, address-cells, size-cells and dma-ranges to declare 1:1 DMA translation into the parent. Reviewed-by: Krzysztof Kozlowski Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- .../devicetree/bindings/media/qcom,sm8750-iris.yaml | 16 ++++++++++++= +--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/media/qcom,sm8750-iris.yaml = b/Documentation/devicetree/bindings/media/qcom,sm8750-iris.yaml index c42d3470bdac796cc878090e65becf6b62bd80ca..b6d5ded1aae6a1a6836c2c24b1d= ae548cdc6f9d2 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8750-iris.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8750-iris.yaml @@ -72,7 +72,6 @@ required: - dma-coherent - interconnects - interconnect-names - - iommus - power-domain-names - resets - reset-names @@ -110,8 +109,6 @@ examples: "vcodec0_core_freerun"; =20 dma-coherent; - iommus =3D <&apps_smmu 0x1940 0>, - <&apps_smmu 0x1947 0>; =20 interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_= ONLY &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_O= NLY>, @@ -144,6 +141,19 @@ examples: "core", "vcodec0_core"; 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But when "iommu-addresses" is the only property being described and there is no backing "reg" (i.e. no actual reserved system memory), it does not really belong under /reserved-memory. A device IOVA range is specific to its own address space, and does not describe the system physical memory to make it qualify under reserved-memory. Given this, place "iommu-addresses" inside reserved-memory only when it is paired with a "reg", otherwise, define it within the device own node. It was discussed here: https://lore.kernel.org/all/662f7093-fb0a-4564-9ca0-98e03e68ba9a@kernel.org Existing "iommu-addresses" property expects a phandle, which does not make sense when the property is defined within the device node. Introduce a new property, "iommu-ranges", to specify the device specific IOVA ranges when there is no backing "reg". Suggested-by: Rob Herring Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- drivers/iommu/of_iommu.c | 128 +++++++++++++++++++++++++++++++++++++++++++= +--- 1 file changed, 121 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index a18bb60f6f3dfdba853b6e16dd2a8616f6a731c7..9766a6944d0e11a6cd8b74b1b89= 428acffe3dfdf 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -190,6 +190,111 @@ iommu_resv_region_get_type(struct device *dev, return IOMMU_RESV_RESERVED; } =20 +/** + * of_iommu_derive_resv_regions - derive reserved regions which + * are outside of iommu-ranges + * @dev: device for which to get reserved regions + * @list: reserved region list + * + * A device can describe its own usable IOVA ranges directly on its node + * via "iommu-ranges". Everything not under those ranges is derived + * as a reserved region so the IOMMU allocator won't use it. Entries may + * appear in any order in the property. + */ +static void of_iommu_derive_resv_regions(struct device *dev, struct list_h= ead *list) +{ + struct of_iommu_range { + struct list_head node; + phys_addr_t start; + phys_addr_t end; + } *pos, *new, *next_range; + int size, prot =3D IOMMU_READ | IOMMU_WRITE; + struct iommu_resv_region *region; + const __be32 *maps, *end; + struct list_head *prev; + phys_addr_t next =3D 0; + LIST_HEAD(ranges); + + maps =3D of_get_property(dev->of_node, "iommu-ranges", &size); + if (!maps) + return; + + end =3D maps + size / sizeof(__be32); + + while (maps < end) { + phys_addr_t iova, iova_end; + size_t length; + + maps =3D of_translate_dma_region(dev->of_node, maps, &iova, &length); + if (!maps) { + dev_err(dev, "%pOF: failed to parse iommu-ranges\n", + dev->of_node); + break; + } + + if (!length) + continue; + + iova_end =3D iova + length - 1; + + if (iova_end < iova) { + dev_err(dev, "%pOF: iommu-ranges overflows address space\n", + dev->of_node); + continue; + } + + prev =3D &ranges; + list_for_each_entry(pos, &ranges, node) { + if (pos->start > iova) + break; + prev =3D &pos->node; + } + + new =3D kmalloc_obj(*new); + if (!new) + continue; + + new->start =3D iova; + new->end =3D iova_end; + list_add(&new->node, prev); + } + + if (list_empty(&ranges)) + return; + + if (of_dma_is_coherent(dev->of_node)) + prot |=3D IOMMU_CACHE; + + list_for_each_entry_safe(pos, next_range, &ranges, node) { + if (pos->start > next) { + region =3D iommu_alloc_resv_region(next, pos->start - next, prot, + IOMMU_RESV_RESERVED, GFP_KERNEL); + if (region) + list_add_tail(®ion->list, list); + } + + if (pos->end =3D=3D PHYS_ADDR_MAX) + goto exit; + + if (pos->end >=3D next) + next =3D pos->end + 1; + + list_del(&pos->node); + kfree(pos); + } + + region =3D iommu_alloc_resv_region(next, PHYS_ADDR_MAX - next + 1, + prot, IOMMU_RESV_RESERVED, GFP_KERNEL); + if (region) + list_add_tail(®ion->list, list); + +exit: + list_for_each_entry_safe(pos, next_range, &ranges, node) { + list_del(&pos->node); + kfree(pos); + } +} + /** * of_iommu_get_resv_regions - reserved region driver helper for device tr= ee * @dev: device for which to get reserved regions @@ -214,10 +319,14 @@ void of_iommu_get_resv_regions(struct device *dev, st= ruct list_head *list) =20 memset(&phys, 0, sizeof(phys)); =20 + maps =3D of_get_property(it.node, "iommu-addresses", &size); + if (!maps) + continue; + /* - * The "reg" property is optional and can be omitted by reserved-memory = regions - * that represent reservations in the IOVA space, which are regions that= should - * not be mapped. + * "iommu-addresses" must be used in combination with a "reg" that provi= des + * the physical address and size of this memory region, for an identity = 1:1 + * IOVA mapping to that physical memory. */ if (of_property_present(it.node, "reg")) { err =3D of_address_to_resource(it.node, 0, &phys); @@ -226,11 +335,11 @@ void of_iommu_get_resv_regions(struct device *dev, st= ruct list_head *list) it.node, err); continue; } - } - - maps =3D of_get_property(it.node, "iommu-addresses", &size); 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a=ed25519-sha256; t=1790404457; l=6003; i=vikash.garodia@oss.qualcomm.com; s=20241104; h=from:subject:message-id; bh=foRnImGSZ75lU1r/edBBVgqmVHY1e0szEa/Z/AKAvQU=; b=gSHDOwu5njS7et+ZfzmWbDotSvCOQ5fANphwBG97+btRnV3vBXuCytxIcpe4XgbQIyHMuH4Ek dZ91Xwp2Z3QBEVIvrm1EZPqUxKoHlpeHV7/H6U6lFMmauy27qSurmJA X-Developer-Key: i=vikash.garodia@oss.qualcomm.com; a=ed25519; pk=LY9Eqp4KiHWxzGNKGHbwRFEJOfRCSzG/rxQNmvZvaKE= X-Authority-Analysis: v=2.4 cv=VvS2kO2n c=1 sm=1 tr=0 ts=6ab7679c cx=c_pps a=JYo30EpNSr/tUYqK9jHPoA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=e5mUnYsNAAAA:8 a=EUspDBNiAAAA:8 a=UWePQM47DRlDhC0KtsoA:9 a=QEXdDO2ut3YA:10 a=Fk4IpSoW4aLDllm1B1p-:22 a=Vxmtnl_E_bksehYqCbjh:22 X-Proofpoint-GUID: HFbfCyyJZ5o7ts0MFaZYwNqKlSMeQOqY X-Proofpoint-ORIG-GUID: HFbfCyyJZ5o7ts0MFaZYwNqKlSMeQOqY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI2MDAyNiBTYWx0ZWRfX8lfPwg9lXzJm NVIxSYdjeImItZvKka35fBEGhoeRe5lwnkCX5AUtEoA5AQrkf1RTamxv0mCyAA1VhFnUDznUsJy mxrg3yyIbSMPzsc2K9mGK0/Q8lWA5g7C3NL3YQeKGV77Y4U3dUSBfW389zim261cnHelZMvvN93 23jj4h59W+pHVPT172Im0rUQYQjz8u445L1fpNM81ezmYoLWxRZlcKOmcjaqBelTXU4woYiETM4 EqcoW6ZLbfowCHDPB8Rw96jKqLy+rHV5ixRvOKaiMXYXztJOi4Q0VAghAsQEPqfR00S97MNW0gG 7yGM84+qCUpRJlSVYULLmrZOMZWPPSaLTg7Pmo7VMHktzZ9q0NPBzdKUc+Tc0UmQQHxnwjaHLpb 0pJzRjrak0HQJ+TC4E7hf0FwzF77iXPTbXp/RkOBhYXgqRkPsmHvSNoV37ueknkKfPq4jiNPyka Sys/QdEr3d+2ZLH9+Iw== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI2MDAyNiBTYWx0ZWRfX7d8RLeOlJG39 Tb3X3YPVppIHnLM5IWE6JBazRSk9rOdg0sXgWwC7MDSAz8xQM0VdKKDlFPqdo92xXEV2hPsZi36 mSd68j6YEaQuA7lVsXDRmgPpmw8gEOI= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 clxscore=1015 priorityscore=1501 spamscore=0 malwarescore=0 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609260026 The VPU issues DMA through several SMMU streams, and the hardware does not give every stream the same addressable range. The non-pixel stream cannot address the low 600MB of IOVA space, while the pixel stream can address the full range: +-----------------------------------------------------------+ | non-pixel stream addressable range (600 MB - 3.5 GB) | | 0x25800000 - 0xe0000000 | +-----------------------------------------------------------+ | pixel stream addressable range (0 - 3.5 GB) | | 0x00000000 - 0xe0000000 | +-----------------------------------------------------------+ A single "iommus" property on the video-codec node puts every stream in one IOMMU domain sharing one IOVA allocator, so nothing restricts a non-pixel buffer to avoid 0 to 600MB. Once an allocation lands below that boundary the hardware faults, which shows up as unhandled SMMU page faults and spontaneous reboots: https://gitlab.freedesktop.org/drm/msm/-/work_items/100 Now the device tree describes "non-pixel" and "pixel" as separate context bank subnodes, each carrying its own "iommus" stream IDs. Add helper functions to create and clean up devices from these DT subnodes, and call them from iris_probe() and iris_remove(). This applies to the common probe path as it is required for all platforms. Set the context banks before v4l2_device_register() so the DMA plumbing is in place before any video device is visible to userspace, and tear them down on the probe error path and in iris_remove(). Reviewed-by: Dmitry Baryshkov Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- drivers/media/platform/qcom/iris/iris_core.h | 4 ++ drivers/media/platform/qcom/iris/iris_probe.c | 71 +++++++++++++++++++++++= +++- 2 files changed, 74 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/p= latform/qcom/iris/iris_core.h index 24da60448cf24820af7947b85eb7208555ab7786..3c96f46cf567b2802148b2a7ced= b8488b6b9468b 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -36,6 +36,8 @@ struct qcom_ubwc_cfg_data; * struct iris_core - holds core parameters valid for all instances * * @dev: reference to device structure + * @np_dev: reference to non-pixel device structure + * @p_dev: reference to pixel device structure * @reg_base: IO memory base address * @irq: iris irq * @v4l2_dev: a holder for v4l2 device structure @@ -81,6 +83,8 @@ struct qcom_ubwc_cfg_data; =20 struct iris_core { struct device *dev; + struct device *np_dev; + struct device *p_dev; void __iomem *reg_base; int irq; struct v4l2_device v4l2_dev; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index e4acf4a74f944bcae83089ef5489f204d4b0078e..debd1f0e57038d7abf463e82fd8= 0f887b67750e8 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -150,6 +150,67 @@ static int iris_init_resources(struct iris_core *core) return iris_init_resets(core); } =20 +static struct device *iris_create_cb_dev(struct iris_core *core, const cha= r *name) +{ + struct platform_device_info plat_dev_info =3D {}; + struct device_node *child_of_node; + struct platform_device *pdev; + + child_of_node =3D of_get_child_by_name(core->dev->of_node, name); + if (!child_of_node) + return NULL; + + plat_dev_info.dma_mask =3D core->iris_platform_data->dma_mask; + plat_dev_info.fwnode =3D &child_of_node->fwnode; + plat_dev_info.name =3D child_of_node->name; + plat_dev_info.id =3D PLATFORM_DEVID_AUTO; + plat_dev_info.parent =3D core->dev; + + pdev =3D platform_device_register_full(&plat_dev_info); + of_node_put(child_of_node); + if (IS_ERR(pdev)) + return ERR_CAST(pdev); + + dma_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); + dma_set_seg_boundary(&pdev->dev, DMA_BIT_MASK(32)); + + return &pdev->dev; +} + +static int iris_init_cb_devs(struct iris_core *core) +{ + struct device *dev; + + dev =3D iris_create_cb_dev(core, "non-pixel"); + if (IS_ERR(dev)) + return PTR_ERR(dev); + + core->np_dev =3D dev; + + dev =3D iris_create_cb_dev(core, "pixel"); + if (IS_ERR(dev)) + goto unreg_np_dev; + + core->p_dev =3D dev; + + return 0; + +unreg_np_dev: + if (core->np_dev) + platform_device_unregister(to_platform_device(core->np_dev)); + core->np_dev =3D NULL; + + return PTR_ERR(dev); +} + +static void iris_deinit_cb_devs(struct iris_core *core) +{ + if (core->p_dev) + platform_device_unregister(to_platform_device(core->p_dev)); + if (core->np_dev) + platform_device_unregister(to_platform_device(core->np_dev)); +} + static int iris_register_video_device(struct iris_core *core, enum domain_= type type) { struct video_device *vdev; @@ -207,6 +268,8 @@ static void iris_remove(struct platform_device *pdev) =20 v4l2_device_unregister(&core->v4l2_dev); =20 + iris_deinit_cb_devs(core); + mutex_destroy(&core->lock); } =20 @@ -269,10 +332,14 @@ static int iris_probe(struct platform_device *pdev) if (ret) return ret; =20 - ret =3D v4l2_device_register(dev, &core->v4l2_dev); + ret =3D iris_init_cb_devs(core); if (ret) return ret; =20 + ret =3D v4l2_device_register(dev, &core->v4l2_dev); + if (ret) + goto err_cb_deinit; + ret =3D iris_register_video_device(core, DECODER); if (ret) goto err_v4l2_unreg; @@ -306,6 +373,8 @@ static int iris_probe(struct platform_device *pdev) video_unregister_device(core->vdev_dec); err_v4l2_unreg: v4l2_device_unregister(&core->v4l2_dev); +err_cb_deinit: + iris_deinit_cb_devs(core); =20 return ret; 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The non-pixel stream cannot address the low 600MB of IOVA space, while the pixel stream can address the full range. Add iris_get_cb_dev(), which maps a buffer type to the owning context bank device. Bitstream and internal buffers (BIN, ARP, COMV, LINE, NON_COMV, PERSIST) belong to the non-pixel device, and uncompressed buffers (DPB, PARTIAL, SCRATCH_1, SCRATCH_2, VPSS) to the pixel device. BUF_INPUT and BUF_OUTPUT depend on direction and are resolved from inst->domain: for a decoder the input is non-pixel and the output pixel, and the other way round for an encoder. Fall back to core->dev whenever the relevant context bank device is absent, so platforms still describing "iommus" on the parent iris node behave exactly as before to maintain backward compatibility. Reviewed-by: Dmitry Baryshkov Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- drivers/media/platform/qcom/iris/iris_buffer.c | 8 ++--- drivers/media/platform/qcom/iris/iris_hfi_queue.c | 16 +++++---- drivers/media/platform/qcom/iris/iris_resources.c | 41 +++++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_resources.h | 1 + drivers/media/platform/qcom/iris/iris_vidc.c | 4 +-- 5 files changed, 57 insertions(+), 13 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media= /platform/qcom/iris/iris_buffer.c index eb8de60c1177f5e1ab83b90a3c8c80e0b4d1f02e..6e03d13ac1a792c539bf8fe6d26= 354aa29d7b3a2 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -531,7 +531,7 @@ static int iris_create_internal_buffer(struct iris_inst= *inst, enum iris_buffer_type buffer_type, u32 index) { struct iris_buffers *buffers =3D &inst->buffers[buffer_type]; - struct iris_core *core =3D inst->core; + struct device *dev =3D iris_get_cb_dev(inst, buffer_type); struct iris_buffer *buffer; =20 if (!buffers->size) @@ -547,7 +547,7 @@ static int iris_create_internal_buffer(struct iris_inst= *inst, buffer->buffer_size =3D buffers->size; buffer->dma_attrs =3D DMA_ATTR_WRITE_COMBINE | DMA_ATTR_NO_KERNEL_MAPPING; =20 - buffer->kvaddr =3D dma_alloc_attrs(core->dev, buffer->buffer_size, + buffer->kvaddr =3D dma_alloc_attrs(dev, buffer->buffer_size, &buffer->device_addr, GFP_KERNEL, buffer->dma_attrs); if (!buffer->kvaddr) { kfree(buffer); @@ -650,10 +650,10 @@ int iris_queue_internal_buffers(struct iris_inst *ins= t, u32 plane) =20 void iris_destroy_internal_buffer(struct iris_inst *inst, struct iris_buff= er *buffer) { - struct iris_core *core =3D inst->core; + struct device *dev =3D iris_get_cb_dev(inst, buffer->type); =20 list_del(&buffer->list); - dma_free_attrs(core->dev, buffer->buffer_size, buffer->kvaddr, + dma_free_attrs(dev, buffer->buffer_size, buffer->kvaddr, buffer->device_addr, buffer->dma_attrs); kfree(buffer); } diff --git a/drivers/media/platform/qcom/iris/iris_hfi_queue.c b/drivers/me= dia/platform/qcom/iris/iris_hfi_queue.c index bf6db23b53e2106c08f2139b643f8626af8bc40a..ce6a682b0f9ada79f9fae26289d= b298855d777c2 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_queue.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_queue.c @@ -245,25 +245,26 @@ static void iris_hfi_queue_deinit(struct iris_iface_q= _info *iface_q) =20 int iris_hfi_queues_init(struct iris_core *core) { + struct device *dev =3D core->np_dev ? core->np_dev : core->dev; struct iris_hfi_queue_table_header *q_tbl_hdr; u32 queue_size; =20 /* Iris hardware requires 4K queue alignment */ queue_size =3D ALIGN((sizeof(*q_tbl_hdr) + (IFACEQ_QUEUE_SIZE * IFACEQ_NU= MQ)), SZ_4K); - core->iface_q_table_vaddr =3D dma_alloc_attrs(core->dev, queue_size, + core->iface_q_table_vaddr =3D dma_alloc_attrs(dev, queue_size, &core->iface_q_table_daddr, GFP_KERNEL, DMA_ATTR_WRITE_COMBINE); if (!core->iface_q_table_vaddr) { - dev_err(core->dev, "queues alloc and map failed\n"); + dev_err(dev, "queues alloc and map failed\n"); return -ENOMEM; } =20 - core->sfr_vaddr =3D dma_alloc_attrs(core->dev, SFR_SIZE, + core->sfr_vaddr =3D dma_alloc_attrs(dev, SFR_SIZE, &core->sfr_daddr, GFP_KERNEL, DMA_ATTR_WRITE_COMBINE); if (!core->sfr_vaddr) { - dev_err(core->dev, "sfr alloc and map failed\n"); - dma_free_attrs(core->dev, queue_size, core->iface_q_table_vaddr, + dev_err(dev, "sfr alloc and map failed\n"); + dma_free_attrs(dev, queue_size, core->iface_q_table_vaddr, core->iface_q_table_daddr, DMA_ATTR_WRITE_COMBINE); return -ENOMEM; } @@ -291,6 +292,7 @@ int iris_hfi_queues_init(struct iris_core *core) =20 void iris_hfi_queues_deinit(struct iris_core *core) { + struct device *dev =3D core->np_dev ? core->np_dev : core->dev; u32 queue_size; =20 if (!core->iface_q_table_vaddr) @@ -300,7 +302,7 @@ void iris_hfi_queues_deinit(struct iris_core *core) iris_hfi_queue_deinit(&core->message_queue); iris_hfi_queue_deinit(&core->command_queue); =20 - dma_free_attrs(core->dev, SFR_SIZE, core->sfr_vaddr, + dma_free_attrs(dev, SFR_SIZE, core->sfr_vaddr, core->sfr_daddr, DMA_ATTR_WRITE_COMBINE); =20 core->sfr_vaddr =3D NULL; @@ -309,7 +311,7 @@ void iris_hfi_queues_deinit(struct iris_core *core) queue_size =3D ALIGN(sizeof(struct iris_hfi_queue_table_header) + (IFACEQ_QUEUE_SIZE * IFACEQ_NUMQ), SZ_4K); =20 - dma_free_attrs(core->dev, queue_size, core->iface_q_table_vaddr, + dma_free_attrs(dev, queue_size, core->iface_q_table_vaddr, core->iface_q_table_daddr, DMA_ATTR_WRITE_COMBINE); =20 core->iface_q_table_vaddr =3D NULL; diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/me= dia/platform/qcom/iris/iris_resources.c index 2c4d34c7bd77d1f78d3572f659da656eb3b12113..a6c3df892ca9888d82414ca6b48= c80efbf7b06d0 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.c +++ b/drivers/media/platform/qcom/iris/iris_resources.c @@ -12,6 +12,7 @@ #include =20 #include "iris_core.h" +#include "iris_instance.h" #include "iris_resources.h" =20 #define BW_THRESHOLD 50000 @@ -138,3 +139,43 @@ int iris_disable_unprepare_clock(struct iris_core *cor= e, enum platform_clk_type =20 return 0; } + +struct device *iris_get_cb_dev(struct iris_inst *inst, enum iris_buffer_ty= pe buffer_type) +{ + struct iris_core *core =3D inst->core; + struct device *dev =3D NULL; + + switch (buffer_type) { + case BUF_INPUT: + if (inst->domain =3D=3D DECODER) + dev =3D core->np_dev; + else + dev =3D core->p_dev; + break; + case BUF_OUTPUT: + if (inst->domain =3D=3D DECODER) + dev =3D core->p_dev; + else + dev =3D core->np_dev; + break; + case BUF_DPB: + case BUF_PARTIAL: + case BUF_SCRATCH_1: + case BUF_SCRATCH_2: + case BUF_VPSS: + dev =3D core->p_dev; + break; + case BUF_BIN: + case BUF_ARP: + case BUF_COMV: + case BUF_LINE: + case BUF_NON_COMV: + case BUF_PERSIST: + dev =3D core->np_dev; + break; + default: + dev_err(core->dev, "invalid buffer type: %d\n", buffer_type); + } + + return dev ? dev : core->dev; +} diff --git a/drivers/media/platform/qcom/iris/iris_resources.h b/drivers/me= dia/platform/qcom/iris/iris_resources.h index 6bfbd2dc6db095ec05e53c894e048285f82446c6..a9a5bddb19c24917de4c5dba525= 67934b77e5c59 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.h +++ b/drivers/media/platform/qcom/iris/iris_resources.h @@ -15,5 +15,6 @@ int iris_unset_icc_bw(struct iris_core *core); int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw); int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk= _type clk_type); int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_ty= pe clk_type); +struct device *iris_get_cb_dev(struct iris_inst *inst, enum iris_buffer_ty= pe buffer_type); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index fcbc60016beec693f2ce27927a09a2d51494bc38..064cf0a80748dab1be0515c4c2b= 6688aeb2b7022 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -108,7 +108,7 @@ iris_m2m_queue_init(void *priv, struct vb2_queue *src_v= q, struct vb2_queue *dst_ src_vq->drv_priv =3D inst; src_vq->buf_struct_size =3D sizeof(struct iris_buffer); src_vq->min_reqbufs_allocation =3D MIN_BUFFERS; - src_vq->dev =3D inst->core->dev; + src_vq->dev =3D iris_get_cb_dev(inst, BUF_INPUT); src_vq->lock =3D &inst->ctx_q_lock; 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That device then has no IOMMU domain of its own and never performs DMA directly, so calling dma_set_mask_and_coherent() on it is meaningless, and on a device with no IOMMU it can fail and abort probe. Set the DMA mask only when device_iommu_mapped() reports an IOMMU on the core device. Platforms that have not been converted still carry "iommus" on the parent node and keep the existing setup. For converted platforms the mask is applied to each context bank device instead, in iris_create_cb_dev(). Reviewed-by: Dmitry Baryshkov Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- drivers/media/platform/qcom/iris/iris_probe.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index debd1f0e57038d7abf463e82fd80f887b67750e8..4bdb078d83b5c331869dab2409b= c4d10ab302737 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -352,9 +352,11 @@ static int iris_probe(struct platform_device *pdev) =20 dma_mask =3D core->iris_platform_data->dma_mask; =20 - ret =3D dma_set_mask_and_coherent(dev, dma_mask); - if (ret) - goto err_vdev_unreg_enc; + if (device_iommu_mapped(dev)) { + ret =3D dma_set_mask_and_coherent(dev, dma_mask); + if (ret) + goto err_vdev_unreg_enc; + } =20 dma_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); dma_set_seg_boundary(&pdev->dev, DMA_BIT_MASK(32)); --=20 2.34.1 From nobody Fri Oct 2 11:44:04 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 618743955C7 for ; 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The non-pixel stream cannot address the low 600MB of IOVA space, while the pixel stream can address the full range: +-----------------------------------------------------------+ | non-pixel stream addressable range (600 MB - 3.5 GB) | | 0x25800000 - 0xe0000000 | +-----------------------------------------------------------+ | pixel stream addressable range (0 - 3.5 GB) | | 0x00000000 - 0xe0000000 | +-----------------------------------------------------------+ A single "iommus" property on the video-codec node puts every stream in one IOMMU domain sharing one IOVA allocator, so nothing restricts a non-pixel buffer to avoid 0 to 600MB. Once an allocation lands below that boundary the hardware faults, which shows up as unhandled SMMU page faults and spontaneous reboots: https://gitlab.freedesktop.org/drm/msm/-/work_items/100 Given that the address range restriction is for specific VPU stream, it should be ideally be moved to that stream. To achieve the same, a subset of streams is now represented as subnodes, so that each can be associated with its respective addressable range. The design was discussed and agreed by mainatiners here https://lore.kernel.org/all/c7b956a9-d3e8-4e18-b780-5d08f5cd2ca1@kernel.org In the past, this limitation was addressed with an iommu-map approach, with the iris driver dynamically creating the devices. That approach was later concluded to be a hack to avoid having subnodes, and was NAKed by the iommu maintainers. It was discussed in detail here: https://lore.kernel.org/all/c7b956a9-d3e8-4e18-b780-5d08f5cd2ca1@kernel.org/ The video-codec node includes address-cells, size-cells and dma-ranges to declare 1:1 mapping for DMA translation to the parent. Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom= /hamoa.dtsi index 4e35254cdd11a87eb5e4817abd09a603522309e2..9819a1f5686ce92c2249cc1dd65= a491665fcfb94 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -5468,10 +5468,12 @@ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONL= Y>, resets =3D <&gcc GCC_VIDEO_AXI0_CLK_ARES>; reset-names =3D "bus"; =20 - iommus =3D <&apps_smmu 0x1940 0>, - <&apps_smmu 0x1947 0>; dma-coherent; =20 + #address-cells =3D <1>; + #size-cells =3D <1>; + dma-ranges =3D <0x0 0x0 0x0 0xe0000000>; + /* * IRIS firmware is signed by vendors, only * enable on boards where the proper signed firmware @@ -5479,6 +5481,15 @@ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY= >, */ status =3D "disabled"; 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The non-pixel stream cannot address the low 600MB of IOVA space, while the pixel stream can address the full range: +-----------------------------------------------------------+ | non-pixel stream addressable range (600 MB - 3.5 GB) | | 0x25800000 - 0xe0000000 | +-----------------------------------------------------------+ | pixel stream addressable range (0 - 3.5 GB) | | 0x00000000 - 0xe0000000 | +-----------------------------------------------------------+ A single "iommus" property on the video-codec node puts every stream in one IOMMU domain sharing one IOVA allocator, so nothing restricts a non-pixel buffer to avoid 0 to 600MB. Once an allocation lands below that boundary the hardware faults, which shows up as unhandled SMMU page faults and spontaneous reboots: https://gitlab.freedesktop.org/drm/msm/-/work_items/100 Given that the address range restriction is for specific VPU stream, it should be ideally be moved to that stream. To achieve the same, a subset of streams is now represented as subnodes, so that each can be associated with its respective addressable range. The design was discussed and agreed by mainatiners here https://lore.kernel.org/all/c7b956a9-d3e8-4e18-b780-5d08f5cd2ca1@kernel.org In the past, this limitation was addressed with an iommu-map approach, with the iris driver dynamically creating the devices. That approach was later concluded to be a hack to avoid having subnodes, and was NAKed by the iommu maintainers. It was discussed in detail here: https://lore.kernel.org/all/c7b956a9-d3e8-4e18-b780-5d08f5cd2ca1@kernel.org/ The video-codec node includes address-cells, size-cells and dma-ranges to declare 1:1 mapping for DMA translation to the parent. Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 23604436add303348867f890890f2f7af4f831af..60164b853ae0764cdd79c468049= 0e66a548b0613 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3690,8 +3690,6 @@ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, resets =3D <&gcc GCC_VIDEO_AXI0_CLK_ARES>; reset-names =3D "bus"; =20 - iommus =3D <&apps_smmu 0x1940 0>, - <&apps_smmu 0x1947 0>; dma-coherent; =20 /* @@ -3701,6 +3699,19 @@ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY= >, */ status =3D "disabled"; =20 + #address-cells =3D <1>; + #size-cells =3D <1>; + dma-ranges =3D <0x0 0x0 0x0 0xe0000000>; + + non-pixel { + iommus =3D <&apps_smmu 0x1940 0x0>; + iommu-ranges =3D <0x25800000 0xba800000>; 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The non-pixel stream cannot address the low 600MB of IOVA space, while the pixel stream can address the full range: +-----------------------------------------------------------+ | non-pixel stream addressable range (600 MB - 3.5 GB) | | 0x25800000 - 0xe0000000 | +-----------------------------------------------------------+ | pixel stream addressable range (0 - 3.5 GB) | | 0x00000000 - 0xe0000000 | +-----------------------------------------------------------+ A single "iommus" property on the video-codec node puts every stream in one IOMMU domain sharing one IOVA allocator, so nothing restricts a non-pixel buffer to avoid 0 to 600MB. Once an allocation lands below that boundary the hardware faults, which shows up as unhandled SMMU page faults and spontaneous reboots: https://gitlab.freedesktop.org/drm/msm/-/work_items/100 Given that the address range restriction is for specific VPU stream, it should be ideally be moved to that stream. To achieve the same, a subset of streams is now represented as subnodes, so that each can be associated with its respective addressable range. The design was discussed and agreed by mainatiners here https://lore.kernel.org/all/c7b956a9-d3e8-4e18-b780-5d08f5cd2ca1@kernel.org In the past, this limitation was addressed with an iommu-map approach, with the iris driver dynamically creating the devices. That approach was later concluded to be a hack to avoid having subnodes, and was NAKed by the iommu maintainers. It was discussed in detail here: https://lore.kernel.org/all/c7b956a9-d3e8-4e18-b780-5d08f5cd2ca1@kernel.org/ The video-codec node includes address-cells, size-cells and dma-ranges to declare 1:1 mapping for DMA translation to the parent. Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/lemans.dtsi | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index 695eae1b7256911e656ab1ecdd92aca135d92f39..afed5e43b4fcda8b8400e815d24= c5094834677f3 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -4962,12 +4962,23 @@ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONL= Y>, resets =3D <&gcc GCC_VIDEO_AXI0_CLK_ARES>; reset-names =3D "bus"; =20 - iommus =3D <&apps_smmu 0x0880 0x0400>, - <&apps_smmu 0x0887 0x0400>; dma-coherent; =20 + #address-cells =3D <1>; + #size-cells =3D <1>; + dma-ranges =3D <0x0 0x0 0x0 0xe0000000>; + status =3D "disabled"; =20 + non-pixel { + iommus =3D <&apps_smmu 0x0880 0x0400>; + iommu-ranges =3D <0x25800000 0xba800000>; + }; + + pixel { + iommus =3D <&apps_smmu 0x0887 0x0400>; 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The non-pixel stream cannot address the low 600MB of IOVA space, while the pixel stream can address the full range: +-----------------------------------------------------------+ | non-pixel stream addressable range (600 MB - 3.5 GB) | | 0x25800000 - 0xe0000000 | +-----------------------------------------------------------+ | pixel stream addressable range (0 - 3.5 GB) | | 0x00000000 - 0xe0000000 | +-----------------------------------------------------------+ A single "iommus" property on the video-codec node puts every stream in one IOMMU domain sharing one IOVA allocator, so nothing restricts a non-pixel buffer to avoid 0 to 600MB. Once an allocation lands below that boundary the hardware faults, which shows up as unhandled SMMU page faults and spontaneous reboots: https://gitlab.freedesktop.org/drm/msm/-/work_items/100 Given that the address range restriction is for specific VPU stream, it should be ideally be moved to that stream. To achieve the same, a subset of streams is now represented as subnodes, so that each can be associated with its respective addressable range. The design was discussed and agreed by mainatiners here https://lore.kernel.org/all/c7b956a9-d3e8-4e18-b780-5d08f5cd2ca1@kernel.org In the past, this limitation was addressed with an iommu-map approach, with the iris driver dynamically creating the devices. That approach was later concluded to be a hack to avoid having subnodes, and was NAKed by the iommu maintainers. It was discussed in detail here: https://lore.kernel.org/all/c7b956a9-d3e8-4e18-b780-5d08f5cd2ca1@kernel.org/ The video-codec node includes address-cells, size-cells and dma-ranges to declare 1:1 mapping for DMA translation to the parent. Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/monaco.dtsi | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qco= m/monaco.dtsi index 395d32d368443e6c73b934b183c3de007ca2e6b5..89ea87a274a159da872facb688c= d742d8d28f3c5 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -5403,12 +5403,23 @@ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONL= Y>, resets =3D <&gcc GCC_VIDEO_AXI0_CLK_ARES>; reset-names =3D "bus"; =20 - iommus =3D <&apps_smmu 0x0880 0x0400>, - <&apps_smmu 0x0887 0x0400>; dma-coherent; =20 + #address-cells =3D <1>; + #size-cells =3D <1>; + dma-ranges =3D <0x0 0x0 0x0 0xe0000000>; + status =3D "disabled"; =20 + non-pixel { + iommus =3D <&apps_smmu 0x0880 0x0400>; + iommu-ranges =3D <0x25800000 0xba800000>; + }; + + pixel { + iommus =3D <&apps_smmu 0x0887 0x0400>; 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a=ed25519-sha256; t=1790404457; l=3374; i=vikash.garodia@oss.qualcomm.com; s=20241104; h=from:subject:message-id; bh=zcX24z1Mg5QUNS5mW/qnvjI3UqwCsEZvZHUBAgeTQ9E=; b=CKd98yAC95m2QLEjpzTBnk3A9uK7M0MDRzlIoOi8jjmMuf85VxbIDe89cKqEzY7VEeJsjOhJk Bf/1oX7JekPDzEtBq8YYzsrwmekBao0E6s00wMBBBN51cZeBzH0LG4J X-Developer-Key: i=vikash.garodia@oss.qualcomm.com; a=ed25519; pk=LY9Eqp4KiHWxzGNKGHbwRFEJOfRCSzG/rxQNmvZvaKE= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI2MDAyNiBTYWx0ZWRfX0sQ07LaP/2po tRGfbHDf+qIQc26lpkhvOLFbF2/CnMnD9tpaT77wteCsZpApZwLukFgssDw25QVQN+mz5JcSmLb 4iEW+ejmtauti08rjvBzg8AYXNIuY4GphonjyLIVbrwm2dfeJYrKraOc2Jshdxxt4FOKuyGjZ2P 4MOigKVFp7iAg/vIHke3+Jr6Y5duUfdC6PKag5dEwahf5tZ2DDZ0b9UPxdPOyIJRLQeIqGw9Ycf dPsWGEp9NUYxpt9eabft5KtzX9W4TFmHtlG17TajLt5jdx/o/SRRs3DcJ0z4iId3OgxjVgHy1um E1yH7r+FzqdXKTsG+McM/9Xz082mFutGtLt+jZCtg4gd97TE43DATbB/I9yb0ThQ17kGKcwALiO TaudrNOoYPzOFbyIBTzFIhdvy9pS2sTvtNrHwIW9b2ggn/Y9vO9CK6GK5rXocJCkb3YRn/yTGU0 Oe8x2L9wCmOrwqNVLqQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI2MDAyNiBTYWx0ZWRfX7vcvmf8YKIhk nvzeJtAYxX9J9qMIjEm3EfvLVtiXcwr6jOMHuB2ZcSpajoCV26XB2FRHX+bm3G906C3VpCOKX4d GBjXD91pYSFaclABZjbdjh2hLXkfS+Q= X-Proofpoint-ORIG-GUID: aFSk5J663UVG3gdFz-POUvFCNfEWkGUQ X-Authority-Analysis: v=2.4 cv=X9LHu2Te c=1 sm=1 tr=0 ts=6ab767d3 cx=c_pps a=JYo30EpNSr/tUYqK9jHPoA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=e5mUnYsNAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=w7pRem5UOBajBC5HA0sA:9 a=QEXdDO2ut3YA:10 a=Fk4IpSoW4aLDllm1B1p-:22 a=Vxmtnl_E_bksehYqCbjh:22 X-Proofpoint-GUID: aFSk5J663UVG3gdFz-POUvFCNfEWkGUQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609260026 The VPU issues DMA through several SMMU streams, and the hardware does not give every stream the same addressable range. The non-pixel stream cannot address the low 600MB of IOVA space, while the pixel stream can address the full range: +-----------------------------------------------------------+ | non-pixel stream addressable range (600 MB - 3.5 GB) | | 0x25800000 - 0xe0000000 | +-----------------------------------------------------------+ | pixel stream addressable range (0 - 3.5 GB) | | 0x00000000 - 0xe0000000 | +-----------------------------------------------------------+ A single "iommus" property on the video-codec node puts every stream in one IOMMU domain sharing one IOVA allocator, so nothing restricts a non-pixel buffer to avoid 0 to 600MB. Once an allocation lands below that boundary the hardware faults, which shows up as unhandled SMMU page faults and spontaneous reboots: https://gitlab.freedesktop.org/drm/msm/-/work_items/100 Given that the address range restriction is for specific VPU stream, it should be ideally be moved to that stream. To achieve the same, a subset of streams is now represented as subnodes, so that each can be associated with its respective addressable range. The design was discussed and agreed by mainatiners here https://lore.kernel.org/all/c7b956a9-d3e8-4e18-b780-5d08f5cd2ca1@kernel.org In the past, this limitation was addressed with an iommu-map approach, with the iris driver dynamically creating the devices. That approach was later concluded to be a hack to avoid having subnodes, and was NAKed by the iommu maintainers. It was discussed in detail here: https://lore.kernel.org/all/c7b956a9-d3e8-4e18-b780-5d08f5cd2ca1@kernel.org/ The video-codec node includes address-cells, size-cells and dma-ranges to declare 1:1 mapping for DMA translation to the parent. Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index 4e317c422d92ed72dca8bd97ac33c89f9b462218..078115d57dacd5d5f407cb4592c= 989ba0e9f78c4 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5274,11 +5274,12 @@ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONL= Y>, "xo", "core"; =20 - iommus =3D <&apps_smmu 0x1940 0>, - <&apps_smmu 0x1947 0>; - dma-coherent; =20 + #address-cells =3D <1>; + #size-cells =3D <1>; + dma-ranges =3D <0x0 0x0 0x0 0xe0000000>; + /* * IRIS firmware is signed by vendors, only * enable on boards where the proper signed firmware @@ -5286,6 +5287,15 @@ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY= >, */ status =3D "disabled"; =20 + non-pixel { + iommus =3D <&apps_smmu 0x1940 0x0>; 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a=ed25519-sha256; t=1790404457; l=3606; i=vikash.garodia@oss.qualcomm.com; s=20241104; h=from:subject:message-id; bh=gYrrWAAu3UM4XmJOH+Y9uqQA/KhAPozl/f9r3EEBGVc=; b=cVzYlf+21Qkyg31UkTICAHS8cqDTjwIJ490Z1MDqYpbsVQmWntw0Ar2fcyFNznBufUXOkcG4j YauIRGQPqGbDhovDhtD4mRId4TTMMwo+RWWGvsrloF8EecXEEQKcEjS X-Developer-Key: i=vikash.garodia@oss.qualcomm.com; a=ed25519; pk=LY9Eqp4KiHWxzGNKGHbwRFEJOfRCSzG/rxQNmvZvaKE= X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI2MDAyNiBTYWx0ZWRfX8a1fXYFfWmXF xGgwymrvhS37xEXPLvr+YzzOXFKAU0s3OWkC4kIpScQbGh5zVVy0FM0TKtwsLgVsV9ho54P9MMT HNFEjIevLH06yFSd7/JU6TilqXNHJmg= X-Proofpoint-ORIG-GUID: I1NbO5ZLorHoZgeYb28-Mm2WrLb2jQwo X-Authority-Analysis: v=2.4 cv=WuK+otfv c=1 sm=1 tr=0 ts=6ab767db cx=c_pps a=JYo30EpNSr/tUYqK9jHPoA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=e5mUnYsNAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=w7pRem5UOBajBC5HA0sA:9 a=QEXdDO2ut3YA:10 a=Fk4IpSoW4aLDllm1B1p-:22 a=Vxmtnl_E_bksehYqCbjh:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI2MDAyNiBTYWx0ZWRfX5EB9iuKkyZt7 uPUgUO4ZPV7UXkWdr8lU/AUdDYtU7zuteVq9DFquSLWOZfDputspBWMqHgG2ET+1pb/w4EGcKzk NRU9MGZTiD8w6JKdWLlzX8e1nbx0st3ZUV9RxSc78uee2MFITrnhPhAVJEWESU1qrUq9kDZFHet tX4w3xw6MEDv21MvImi+HY6yRIeNk4Ji/kVhV4PI+8Wfqxhw5V4/HA2f7QQxwBkc4kZKJuLhYs7 LSAUobZTlW4+Umpw+SkNLmnHZMxSXZCL9BDALdFOUazM5HNgSlmK9clscvp3WxFQ9m9/PhB1WQg R2g8tTQJSrdcXPCE75bJCInFwRrY44gZL7+gRvthJLbgLEAluDaUh85fDM5tHGOOK+2Qfjj0Dr1 wJRQfKF+Gma6foHlb+GHebp5HHBxCW61SejxB/y9vKNe94MoIbteUvt5od7YhoiVzMFHrABREsa OgModCUgUbaRIhjkq8A== X-Proofpoint-GUID: I1NbO5ZLorHoZgeYb28-Mm2WrLb2jQwo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609260026 The VPU issues DMA through several SMMU streams, and the hardware does not give every stream the same addressable range. The non-pixel stream cannot address the low 600MB of IOVA space, while the pixel stream can address the full range: +-----------------------------------------------------------+ | non-pixel stream addressable range (600 MB - 3.5 GB) | | 0x25800000 - 0xe0000000 | +-----------------------------------------------------------+ | pixel stream addressable range (0 - 3.5 GB) | | 0x00000000 - 0xe0000000 | +-----------------------------------------------------------+ A single "iommus" property on the video-codec node puts every stream in one IOMMU domain sharing one IOVA allocator, so nothing restricts a non-pixel buffer to avoid 0 to 600MB. Once an allocation lands below that boundary the hardware faults, which shows up as unhandled SMMU page faults and spontaneous reboots: https://gitlab.freedesktop.org/drm/msm/-/work_items/100 Given that the address range restriction is for specific VPU stream, it should be ideally be moved to that stream. To achieve the same, a subset of streams is now represented as subnodes, so that each can be associated with its respective addressable range. The design was discussed and agreed by mainatiners here https://lore.kernel.org/all/c7b956a9-d3e8-4e18-b780-5d08f5cd2ca1@kernel.org In the past, this limitation was addressed with an iommu-map approach, with the iris driver dynamically creating the devices. That approach was later concluded to be a hack to avoid having subnodes, and was NAKed by the iommu maintainers. It was discussed in detail here: https://lore.kernel.org/all/c7b956a9-d3e8-4e18-b780-5d08f5cd2ca1@kernel.org/ The video-codec node includes address-cells, size-cells and dma-ranges to declare 1:1 mapping for DMA translation to the parent. Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index 28cf22da854d01413b8e86be3f6330354aad05f2..2e1e07eb5b6aa49850a7a5572ef= 9e755e298b799 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3025,8 +3025,6 @@ iris: video-codec@aa00000 { "vcodec0_core_freerun"; =20 dma-coherent; - iommus =3D <&apps_smmu 0x1940 0>, - <&apps_smmu 0x1947 0>; =20 interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, @@ -3059,6 +3057,10 @@ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY= >, "core", "vcodec0_core"; =20 + #address-cells =3D <1>; + #size-cells =3D <1>; + dma-ranges =3D <0x0 0x0 0x0 0xe0000000>; + /* * IRIS firmware is signed by vendors, only * enable in boards where the proper signed firmware @@ -3066,6 +3068,15 @@ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY= >, */ status =3D "disabled"; =20 + non-pixel { + iommus =3D <&apps_smmu 0x1940 0x0>; + iommu-ranges =3D <0x25800000 0xba800000>; + }; + + pixel { + iommus =3D <&apps_smmu 0x1947 0x0>; + }; + iris_opp_table: opp-table { compatible =3D "operating-points-v2"; =20 --=20 2.34.1