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[86.49.245.11]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49ff21d6209sm30158645e9.4.2026.09.25.08.17.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 08:17:02 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v6 01/16] iommu/dma: Prepare MSI physical address lists Date: Fri, 25 Sep 2026 17:16:44 +0200 Message-ID: <20260925151659.419512-2-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> References: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: w1wBGpCIWjOkRQO8Nzm2pQTnJrnhHbBM X-Authority-Analysis: v=2.4 cv=QYnzLcbv c=1 sm=1 tr=0 ts=6ab69071 cx=c_pps a=JIY1xp/sjQ9K5JH4t62bdg==:117 a=4CXLxsOAgPM/krjtHEZQyA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=SRrdq9N9AAAA:8 a=kJPfLSheDWDr1nFXzE0A:9 a=tNoRWFLymzeba-QzToBc:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfX+RAzi4A5dEsG I2YKa2PCDxcDbJgeLSUzoA51vM8ucZ40EU2qgSw+Qxkdz0KVFTT8LZOV5kJvyblrve/EXmhjpkP HZKusrSNSt1jBO/VQtV/1j6dT3gB3wc3Kh5lqwfigTHBR/tRjoRCdeRUNkdY9HNv4u1S5/w2P2o svyFUhkoN0tXDAusHwXIeeTy1S6y7ONlg/veUT+F77+YoW7wOfj31Ufr3c2rMubzrKXec2HfiG/ sjmzKAFjq8rnl7tLmfvFFdJWPVDHv+j7vqHm3HHx9srwI/hRcKu2A4z0h6WNu8910b8ld1eBHA9 2YP0EdGoc0dfUzTYBVUpiwAGfCPLQPsQR6QFRwDgVHnDjRviND58Mg+tQhHl+vPQ+nJzl8X7AJq Syx3pTRWDaaKH4RvoI5b0w1JrGeARjK/eQ2yNpG48RECIOlkzbafB+GcL9kwUmzcEeUWZF/6S2y o95Y16eVsT0zlWnUTbw== X-Proofpoint-ORIG-GUID: w1wBGpCIWjOkRQO8Nzm2pQTnJrnhHbBM X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfX9+Hn5oYlZmke 5u70vfAvuX8QC8yYxi0p2g0SlnSPTPvpFP+JsMij3ubTVgd0yqXo2TmnZZasWZKbA5G/UBE7qBU ot+aofn1jP1MmXIiIW5qAGK5ul0cxRo= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-25_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609250060 Content-Type: text/plain; charset="utf-8" Software MSI mappings may cover an ordered list of physical addresses which must be mapped into one contiguous IOVA range. Extend the internal DMA-IOMMU mapping helpers to accept an address array, address count, and required mapping granule. Teach iommu_dma_get_msi_page() to map the list into one contiguous IOVA allocation. Keep the existing per-page cache entries and mark the first entry with the size of the allocation so an identical list can reuse the mapping without changing the existing cache representation. This prepares for the forthcoming iommu_dma_prepare_msi_list() API. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/iommu/dma-iommu.c | 116 +++++++++++++++++++++++++++++--------- 1 file changed, 88 insertions(+), 28 deletions(-) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 58c624513cd4..0b4eb47d1a95 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -42,6 +42,7 @@ struct iommu_dma_msi_page { struct list_head list; dma_addr_t iova; phys_addr_t phys; + size_t range_size; /* IOVA range size, or 0 if not the first map */ }; =20 enum iommu_dma_queue_type { @@ -481,7 +482,7 @@ static int cookie_init_hw_msi_region(struct iommu_dma_c= ookie *cookie, num_pages =3D iova_align(iovad, end - start) >> iova_shift(iovad); =20 for (i =3D 0; i < num_pages; i++) { - msi_page =3D kmalloc_obj(*msi_page); + msi_page =3D kzalloc_obj(*msi_page); if (!msi_page) return -ENOMEM; =20 @@ -2191,15 +2192,42 @@ static struct list_head *cookie_msi_pages(const str= uct iommu_domain *domain) } } =20 +static bool iommu_dma_msi_range_matches(struct list_head *msi_page_list, + const struct iommu_dma_msi_page *base_page, + const phys_addr_t *phys_addrs, + unsigned int nr_addrs, size_t granule) +{ + const struct iommu_dma_msi_page *msi_page; + unsigned int nr_found =3D 0; + dma_addr_t offset; + + list_for_each_entry(msi_page, msi_page_list, list) { + if (msi_page->iova < base_page->iova) + continue; + offset =3D msi_page->iova - base_page->iova; + if (offset >=3D base_page->range_size) + continue; + if (!IS_ALIGNED((size_t)offset, granule) || + msi_page->phys !=3D phys_addrs[(size_t)offset / granule]) + return false; + nr_found++; + } + + return nr_found =3D=3D nr_addrs; +} + static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *de= v, - phys_addr_t msi_addr, struct iommu_domain *domain) + const phys_addr_t *phys_addrs, unsigned int nr_addrs, size_t granule, + struct iommu_domain *domain) { struct list_head *msi_page_list =3D cookie_msi_pages(domain); - struct iommu_dma_msi_page *msi_page; - dma_addr_t iova; + struct iommu_dma_msi_page *msi_page, *first_page =3D NULL; int prot =3D IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; - size_t size =3D cookie_msi_granule(domain); static DEFINE_MUTEX(msi_prepare_lock); + LIST_HEAD(new_msi_pages); + dma_addr_t base_iova; + unsigned int i; + size_t size; =20 /* * Normally a device's default domain is only ever attached to that @@ -2213,32 +2241,60 @@ static struct iommu_dma_msi_page *iommu_dma_get_msi= _page(struct device *dev, */ guard(mutex)(&msi_prepare_lock); =20 - msi_addr &=3D ~(phys_addr_t)(size - 1); - list_for_each_entry(msi_page, msi_page_list, list) - if (msi_page->phys =3D=3D msi_addr) + if (!nr_addrs || nr_addrs > SIZE_MAX / granule) + return NULL; + size =3D nr_addrs * granule; + + list_for_each_entry(msi_page, msi_page_list, list) { + if (msi_page->phys !=3D phys_addrs[0]) + continue; + if (nr_addrs =3D=3D 1) + return msi_page; + if (msi_page->range_size =3D=3D size && + iommu_dma_msi_range_matches(msi_page_list, msi_page, phys_addrs, + nr_addrs, granule)) return msi_page; + } =20 - msi_page =3D kzalloc_obj(*msi_page); - if (!msi_page) - return NULL; + for (i =3D 0; i < nr_addrs; i++) { + msi_page =3D kzalloc_obj(*msi_page); + if (!msi_page) + goto out_free_pages; + list_add_tail(&msi_page->list, &new_msi_pages); + } =20 - iova =3D iommu_dma_alloc_iova(domain, size, dma_get_mask(dev), dev); - if (!iova) - goto out_free_page; + base_iova =3D iommu_dma_alloc_iova(domain, size, dma_get_mask(dev), dev); + if (!base_iova) + goto out_free_pages; =20 - if (iommu_map(domain, iova, msi_addr, size, prot, GFP_KERNEL)) - goto out_free_iova; + i =3D 0; + list_for_each_entry(msi_page, &new_msi_pages, list) { + msi_page->phys =3D phys_addrs[i]; + msi_page->iova =3D base_iova + i * granule; + if (!i) + first_page =3D msi_page; + if (iommu_map(domain, msi_page->iova, msi_page->phys, granule, prot, GFP= _KERNEL)) + goto out_unmap; + i++; + } =20 - INIT_LIST_HEAD(&msi_page->list); - msi_page->phys =3D msi_addr; - msi_page->iova =3D iova; - list_add(&msi_page->list, msi_page_list); - return msi_page; + first_page->range_size =3D size; + list_splice(&new_msi_pages, msi_page_list); + return first_page; =20 -out_free_iova: - iommu_dma_free_iova(domain, iova, size, NULL); -out_free_page: - kfree(msi_page); +out_unmap: + if (i) { + size_t unmap =3D iommu_unmap(domain, base_iova, i * granule); + + WARN_ON_ONCE(unmap !=3D i * granule); + } + iommu_dma_free_iova(domain, base_iova, size, NULL); +out_free_pages: + while (!list_empty(&new_msi_pages)) { + msi_page =3D list_first_entry(&new_msi_pages, typeof(*msi_page), list); + list_del(&msi_page->list); + kfree(msi_page); + } return NULL; } =20 @@ -2247,19 +2303,23 @@ int iommu_dma_sw_msi(struct iommu_domain *domain, s= truct msi_desc *desc, { struct device *dev =3D msi_desc_to_dev(desc); const struct iommu_dma_msi_page *msi_page; + phys_addr_t phys_addr; + size_t granule; =20 if (!has_msi_cookie(domain)) { msi_desc_set_iommu_msi_iova(desc, 0, 0); return 0; } =20 + granule =3D cookie_msi_granule(domain); + phys_addr =3D ALIGN_DOWN(msi_addr, granule); + iommu_group_mutex_assert(dev); - msi_page =3D iommu_dma_get_msi_page(dev, msi_addr, domain); + msi_page =3D iommu_dma_get_msi_page(dev, &phys_addr, 1, granule, domain); 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[86.49.245.11]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49fe5cd4c8dsm176766415e9.3.2026.09.25.08.17.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 08:17:05 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com, Nutty Liu Subject: [PATCH v6 02/16] iommufd: Convert struct iommufd_sw_msi_maps to a growable bitmap Date: Fri, 25 Sep 2026 17:16:45 +0200 Message-ID: <20260925151659.419512-3-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> References: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfX0mOb4GC1X7DQ pC1cU4DotzY5Zrt25s3bizqAvDuCYYduGxzQUqym7W+2zXi/fCGSJn/kKfVvCvlXI3h8/tLCY3e r92FJRhyNiLdX0p80/2JaKScE8lKVSo= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfXxm17heoL7pVq hdfFjLl+y+8a0j0lmze407ccBLmTi2JHmx+IE586uxskmmXs0H7WO9RrXk+edLxCIWWU1BJkUSt /aP3l8PSu7s4wk4n+4eZ6b/ul+e+lq++4tvm/vOaZN+yvXQTufUxikud7KrVIsWghhficiLoaiv /bHgnrXNpsIuHkulY9zV99klu1d/5ehk3uxh/hrsVirba7QYXhjI0r+C92mtCIICiec0LFrjRzy LMkFv7yHqyYersDNe6YEtiRVeRMJZVa02f56cH5/2Xl06QB8g4IFsJcAVxHGwwaagvm6eCBCKOS LPNPbUyoLMPCQAPQGaPfoXHPhhv5Zaw7Ni+Yfleee6Fr+6q6QpTkK8hLJtT5ZRFtf7RT1WRiFUG bXLn33s5wplXuB8kK0NYMBAQVXcsxPkPehSx0SICtHsOmiQBenXryhpY3cKb4kz//PFYO7suJPS Qs+bMvxJtZKf1dhABzw== X-Proofpoint-GUID: Zu9w4L18g4W2hbyVN2TdmqER8NU6OdD8 X-Proofpoint-ORIG-GUID: Zu9w4L18g4W2hbyVN2TdmqER8NU6OdD8 X-Authority-Analysis: v=2.4 cv=Hf2B3SE8 c=1 sm=1 tr=0 ts=6ab69074 cx=c_pps a=KB4UBwrhAZV1kjiGHFQexw==:117 a=4CXLxsOAgPM/krjtHEZQyA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=69EAbJreAAAA:8 a=SRrdq9N9AAAA:8 a=8L5tTrZ4L9qXjquGIIcA:9 a=o1xkdb1NAhiiM49bd1HK:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-25_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 malwarescore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609250060 Content-Type: text/plain; charset="utf-8" struct iommufd_sw_msi_maps uses a fixed 64-bit bitmap, limiting each group and hardware page table to 64 software MSI mappings. RISC-V interrupt remapping needs a mapping for every possible CPU, so this limit is insufficient. Make the bitmap grow on demand and treat IDs beyond its current size as absent. Cap it at 16K entries to bound allocation size while leaving ample room for expected software MSI users. Signed-off-by: Andrew Jones Reviewed-by: Nutty Liu Tested-by: Fangyu Yu --- drivers/iommu/iommufd/device.c | 3 +- drivers/iommu/iommufd/driver.c | 37 ++++++++++++++-------- drivers/iommu/iommufd/hw_pagetable.c | 1 + drivers/iommu/iommufd/iommufd_private.h | 41 +++++++++++++++++++++++-- 4 files changed, 66 insertions(+), 16 deletions(-) diff --git a/drivers/iommu/iommufd/device.c b/drivers/iommu/iommufd/device.c index a664c70a6fe7..28e2c98ef953 100644 --- a/drivers/iommu/iommufd/device.c +++ b/drivers/iommu/iommufd/device.c @@ -49,6 +49,7 @@ static void iommufd_group_release(struct kref *kref) iommu_group_put(igroup->group); } mutex_destroy(&igroup->lock); + kfree(igroup->required_sw_msi.bitmap); kfree(igroup); } =20 @@ -450,7 +451,7 @@ static int iommufd_group_setup_msi(struct iommufd_group= *igroup, int rc; =20 if (cur->sw_msi_start !=3D igroup->sw_msi_start || - !test_bit(cur->id, igroup->required_sw_msi.bitmap)) + !iommufd_sw_msi_maps_test_bit(&igroup->required_sw_msi, cur->id)) continue; =20 rc =3D iommufd_sw_msi_install(ictx, hwpt_paging, cur); diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index e4d17a748178..ea705e416139 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -196,13 +196,15 @@ iommufd_sw_msi_get_map(struct iommufd_ctx *ictx, phys= _addr_t msi_addr, list_for_each_entry(cur, &ictx->sw_msi_list, sw_msi_item) { if (cur->sw_msi_start !=3D sw_msi_start) continue; + if (cur->pgoff =3D=3D UINT_MAX) + return ERR_PTR(-EOVERFLOW); max_pgoff =3D max(max_pgoff, cur->pgoff + 1); if (cur->msi_addr =3D=3D msi_addr) return cur; } =20 - if (ictx->sw_msi_id >=3D - BITS_PER_BYTE * sizeof_field(struct iommufd_sw_msi_maps, bitmap)) + if (ictx->sw_msi_id > IOMMUFD_SW_MSI_MAX_ID || + max_pgoff > (ULONG_MAX - sw_msi_start) / PAGE_SIZE) return ERR_PTR(-EOVERFLOW); =20 cur =3D kzalloc_obj(*cur); @@ -222,21 +224,25 @@ int iommufd_sw_msi_install(struct iommufd_ctx *ictx, struct iommufd_sw_msi_map *msi_map) { unsigned long iova; + int rc; =20 lockdep_assert_held(&ictx->sw_msi_lock); =20 + if (iommufd_sw_msi_maps_test_bit(&hwpt_paging->present_sw_msi, msi_map->i= d)) + return 0; + iova =3D msi_map->sw_msi_start + msi_map->pgoff * PAGE_SIZE; - if (!test_bit(msi_map->id, hwpt_paging->present_sw_msi.bitmap)) { - int rc; - - rc =3D iommu_map(hwpt_paging->common.domain, iova, - msi_map->msi_addr, PAGE_SIZE, - IOMMU_WRITE | IOMMU_READ | IOMMU_MMIO, - GFP_KERNEL_ACCOUNT); - if (rc) - return rc; - __set_bit(msi_map->id, hwpt_paging->present_sw_msi.bitmap); - } + rc =3D iommufd_sw_msi_maps_ensure(&hwpt_paging->present_sw_msi, msi_map->= id); + if (rc) + return rc; + + rc =3D iommu_map(hwpt_paging->common.domain, iova, + msi_map->msi_addr, PAGE_SIZE, + IOMMU_WRITE | IOMMU_READ | IOMMU_MMIO, + GFP_KERNEL_ACCOUNT); + if (rc) + return rc; + __set_bit(msi_map->id, hwpt_paging->present_sw_msi.bitmap); return 0; } EXPORT_SYMBOL_NS_GPL(iommufd_sw_msi_install, "IOMMUFD_INTERNAL"); @@ -290,6 +296,11 @@ int iommufd_sw_msi(struct iommu_domain *domain, struct= msi_desc *desc, if (IS_ERR(msi_map)) return PTR_ERR(msi_map); =20 + rc =3D iommufd_sw_msi_maps_ensure(&handle->idev->igroup->required_sw_msi, + msi_map->id); + if (rc) + return rc; + rc =3D iommufd_sw_msi_install(ictx, hwpt_paging, msi_map); if (rc) return rc; diff --git a/drivers/iommu/iommufd/hw_pagetable.c b/drivers/iommu/iommufd/h= w_pagetable.c index ef6e119c2a75..81f41d437c4c 100644 --- a/drivers/iommu/iommufd/hw_pagetable.c +++ b/drivers/iommu/iommufd/hw_pagetable.c @@ -41,6 +41,7 @@ void iommufd_hwpt_paging_destroy(struct iommufd_object *o= bj) } =20 __iommufd_hwpt_destroy(&hwpt_paging->common); + kfree(hwpt_paging->present_sw_msi.bitmap); refcount_dec(&hwpt_paging->ioas->obj.users); } =20 diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommuf= d/iommufd_private.h index eb2e85b27e42..774cbe28cbaf 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -29,11 +30,47 @@ struct iommufd_sw_msi_map { unsigned int id; }; =20 -/* Bitmap of struct iommufd_sw_msi_map::id */ +/* Bitmap of struct iommufd_sw_msi_map::id; starts empty, grows on demand.= */ struct iommufd_sw_msi_maps { - DECLARE_BITMAP(bitmap, 64); + unsigned long *bitmap; + unsigned int nbits; }; =20 +/* Large enough for foreseeable SW MSI users while bounding bitmap growth.= */ +#define IOMMUFD_SW_MSI_MAX_ID (16U * 1024 - 1) + +/* Grow bitmap to accommodate id. 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[86.49.245.11]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4887a74538asm7857424f8f.34.2026.09.25.08.17.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 08:17:07 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v6 03/16] iommufd: Split software MSI map lookup and allocation Date: Fri, 25 Sep 2026 17:16:46 +0200 Message-ID: <20260925151659.419512-4-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> References: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: vmOabCRjHyOO8wLmiRY7ykPw5LQl_nF- X-Proofpoint-ORIG-GUID: vmOabCRjHyOO8wLmiRY7ykPw5LQl_nF- X-Authority-Analysis: v=2.4 cv=NJFAaE6g c=1 sm=1 tr=0 ts=6ab69075 cx=c_pps a=P2rfLEam3zuxRRdjJWA2cw==:117 a=4CXLxsOAgPM/krjtHEZQyA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=SRrdq9N9AAAA:8 a=_mR3RRazA89hjPCjrIEA:9 a=ODZdjJIeia2B_SHc_B0f:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfXzDUovD8cvueL du9FXCJUJS+vKdhf2t8YKSOsCV4NcBG51A3r2UWwJBGBCRx/cKeQFoYchzK2KP0S78WH+YbXtil E6HnesKo2yQrrehdbWigAhSy6MSG4itO73HG3ULwAx5J8mdGXvpqsCHwple1BzvuI2xsNkm06mV wTsKrRO1UENO7QDNzrjpAr2eoMWquwBsMIQvSxoVdzab18D4kVZmEJtzlIIUD3VLUsXEwGvknVN jxShFynoyxtuCRxXgwhFnz1Crv1/JH8jOR0o/LhlahB+XabQtbS1JryNzCWBhLOtACgCvg5t1Ed qKWcU7hjKXLDQm3dIfD55vGGWB32n9l2EQIgKVRyLN87zmA3ydHeYimUgPG2LUfP5ygr0ZJdq7+ 9Bh8jSsqhw0em6jx2WrZsv4bJcx2JM/4LQ322n01yr16YnbhIFERpxDzvmPZrIjvIzgjLe3BhJz tmed5/uOh4JPlpCUrOQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfX0PHb5VdBa4qV /Y2Achd7PE2082CSRxNUuOR5lBRj5zw4/XvCumKfBWsTW4A+VeXKMP+mFyZUfjzePfk8hfhpn+w Bhs7dBmo494EqOMg5Hu/WVZAe7h1JDo= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-25_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 spamscore=0 phishscore=0 suspectscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609250060 Content-Type: text/plain; charset="utf-8" Separate lookup of an existing software MSI mapping from allocation of a new mapping. This prepares the code for allocating multiple mappings for an MSI physical address list. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/iommu/iommufd/driver.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index ea705e416139..501f1e1f2797 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -189,6 +189,23 @@ iommufd_sw_msi_get_map(struct iommufd_ctx *ictx, phys_= addr_t msi_addr, phys_addr_t sw_msi_start) { struct iommufd_sw_msi_map *cur; + + lockdep_assert_held(&ictx->sw_msi_lock); + + list_for_each_entry(cur, &ictx->sw_msi_list, sw_msi_item) { + if (cur->sw_msi_start !=3D sw_msi_start) + continue; + if (cur->msi_addr =3D=3D msi_addr) + return cur; + } + return NULL; +} + +static struct iommufd_sw_msi_map * +iommufd_sw_msi_alloc_map(struct iommufd_ctx *ictx, phys_addr_t msi_addr, + phys_addr_t sw_msi_start) +{ + struct iommufd_sw_msi_map *cur; unsigned int max_pgoff =3D 0; =20 lockdep_assert_held(&ictx->sw_msi_lock); @@ -199,8 +216,6 @@ iommufd_sw_msi_get_map(struct iommufd_ctx *ictx, phys_a= ddr_t msi_addr, if (cur->pgoff =3D=3D UINT_MAX) return ERR_PTR(-EOVERFLOW); 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[86.49.245.11]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4887a355d96sm8686711f8f.17.2026.09.25.08.17.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 08:17:09 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v6 04/16] iommufd: Bound software MSI mappings to the reserved range Date: Fri, 25 Sep 2026 17:16:47 +0200 Message-ID: <20260925151659.419512-5-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> References: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=TptzFzXh c=1 sm=1 tr=0 ts=6ab6907a cx=c_pps a=R6oCqFB+Yf/t2GF8e0/dFg==:117 a=4CXLxsOAgPM/krjtHEZQyA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=SRrdq9N9AAAA:8 a=f1RXMQGm8Qq6PoD2gk0A:9 a=TD8TdBvy0hsOASGTdmB-:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfX81fDljNfDr3o CiQOrbn/Uz1dRT0S0F9jOhys+v0V9f12JmYTxD8DtB49k7mekgPTyz4T5PyLHgJ53wvaHusP4xE DIzQPxO54Z/boVma/HrNI5UVp90Fq+ObHEt5QImfSJ8STj3oH8a7jyvaLc5O1e23PPX9CuZr5tt BwSCQf9VLj2/0chPp+dqD+RDGAYqtSNoJlNZCAk76nzuleR2RBi45LinDScrTg9y2MExpgx9+Tq EJq38+mACuSHVFOQLohpOKPUNoI5F7r/GkIMW5K3zo6lTFMFuRGSNo1MmAuwS1+MjfaHxSYNnH6 R7ZU8rq7cgTrE2cPyjlhPNalLtZ9ivV0a1h42IJ0bkCZuN9T2pIMssaSPA9foYcl+oreaOUxRun 8Aa0l1uHBgP+i3EzpwtmdI4wIQ2ep2+ghXSr6b/hTLB3tV6cQMYMb6Q9i3Edy/dr0qg8FTK6uJP QmnlCKlp1THCOa6v1Ig== X-Proofpoint-ORIG-GUID: PK85dbgUhHVgETFnQE4YMa9uLq4wAa2W X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfXzYbp2wgsWMSf THS/r8/X7MwY8CkbHyB3JxRs6mkcuUrQyDW0LE0mcbVqdcKBDZqeGQ5yAaKb8q/afFn6+iGjB3m UxRR+x8Eyh9wtwPk0ptjbbo4bbnVC08= X-Proofpoint-GUID: PK85dbgUhHVgETFnQE4YMa9uLq4wAa2W X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-25_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609250060 Content-Type: text/plain; charset="utf-8" Track the start and length of the software MSI reserved region as one range and pass it to the mapping lookup and allocation helpers. Reject cached mappings outside the region and new mappings when no complete page remains. This enforces the reserved region bounds and prepares the helpers to allocate contiguous MSI address lists. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/iommu/iommufd/device.c | 17 +++++++++++------ drivers/iommu/iommufd/driver.c | 21 ++++++++++++--------- drivers/iommu/iommufd/io_pagetable.c | 9 +++++---- drivers/iommu/iommufd/iommufd_private.h | 9 +++++++-- 4 files changed, 35 insertions(+), 21 deletions(-) diff --git a/drivers/iommu/iommufd/device.c b/drivers/iommu/iommufd/device.c index 28e2c98ef953..2b12b25a74da 100644 --- a/drivers/iommu/iommufd/device.c +++ b/drivers/iommu/iommufd/device.c @@ -84,7 +84,7 @@ static struct iommufd_group *iommufd_alloc_group(struct i= ommufd_ctx *ictx, kref_init(&new_igroup->ref); mutex_init(&new_igroup->lock); xa_init(&new_igroup->pasid_attach); - new_igroup->sw_msi_start =3D PHYS_ADDR_MAX; + new_igroup->sw_msi_range.start =3D PHYS_ADDR_MAX; /* group reference moves into new_igroup */ new_igroup->group =3D group; =20 @@ -440,7 +440,7 @@ static int iommufd_group_setup_msi(struct iommufd_group= *igroup, struct iommufd_ctx *ictx =3D igroup->ictx; struct iommufd_sw_msi_map *cur; =20 - if (igroup->sw_msi_start =3D=3D PHYS_ADDR_MAX) + if (igroup->sw_msi_range.start =3D=3D PHYS_ADDR_MAX) return 0; =20 /* @@ -450,7 +450,7 @@ static int iommufd_group_setup_msi(struct iommufd_group= *igroup, list_for_each_entry(cur, &ictx->sw_msi_list, sw_msi_item) { int rc; =20 - if (cur->sw_msi_start !=3D igroup->sw_msi_start || + if (cur->sw_msi_start !=3D igroup->sw_msi_range.start || !iommufd_sw_msi_maps_test_bit(&igroup->required_sw_msi, cur->id)) continue; =20 @@ -480,18 +480,23 @@ static int iommufd_device_attach_reserved_iova(struct iommufd_device *idev, struct iommufd_hwpt_paging *hwpt_paging) { + struct iommufd_sw_msi_range sw_msi_range =3D { + .start =3D PHYS_ADDR_MAX, + }; struct iommufd_group *igroup =3D idev->igroup; + bool first_attach; int rc; =20 lockdep_assert_held(&igroup->lock); =20 + first_attach =3D iommufd_group_first_attach(igroup, IOMMU_NO_PASID); rc =3D iopt_table_enforce_dev_resv_regions(&hwpt_paging->ioas->iopt, - idev->dev, - &igroup->sw_msi_start); + idev->dev, &sw_msi_range); if (rc) return rc; =20 - if (iommufd_group_first_attach(igroup, IOMMU_NO_PASID)) { + if (first_attach) { + igroup->sw_msi_range =3D sw_msi_range; rc =3D iommufd_group_setup_msi(igroup, hwpt_paging); if (rc) { iopt_remove_reserved_iova(&hwpt_paging->ioas->iopt, diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index 501f1e1f2797..c2ef15c2ca51 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -186,14 +186,15 @@ EXPORT_SYMBOL_NS_GPL(iommufd_viommu_report_event, "IO= MMUFD"); */ static struct iommufd_sw_msi_map * iommufd_sw_msi_get_map(struct iommufd_ctx *ictx, phys_addr_t msi_addr, - phys_addr_t sw_msi_start) + const struct iommufd_sw_msi_range *sw_msi_range) { struct iommufd_sw_msi_map *cur; =20 lockdep_assert_held(&ictx->sw_msi_lock); =20 list_for_each_entry(cur, &ictx->sw_msi_list, sw_msi_item) { - if (cur->sw_msi_start !=3D sw_msi_start) + if (cur->sw_msi_start !=3D sw_msi_range->start || + cur->pgoff >=3D sw_msi_range->length / PAGE_SIZE) continue; if (cur->msi_addr =3D=3D msi_addr) return cur; @@ -203,7 +204,7 @@ iommufd_sw_msi_get_map(struct iommufd_ctx *ictx, phys_a= ddr_t msi_addr, =20 static struct iommufd_sw_msi_map * iommufd_sw_msi_alloc_map(struct iommufd_ctx *ictx, phys_addr_t msi_addr, - phys_addr_t sw_msi_start) + const struct iommufd_sw_msi_range *sw_msi_range) { struct iommufd_sw_msi_map *cur; unsigned int max_pgoff =3D 0; @@ -211,7 +212,7 @@ iommufd_sw_msi_alloc_map(struct iommufd_ctx *ictx, phys= _addr_t msi_addr, lockdep_assert_held(&ictx->sw_msi_lock); =20 list_for_each_entry(cur, &ictx->sw_msi_list, sw_msi_item) { - if (cur->sw_msi_start !=3D sw_msi_start) + if (cur->sw_msi_start !=3D sw_msi_range->start) continue; if (cur->pgoff =3D=3D UINT_MAX) return ERR_PTR(-EOVERFLOW); @@ -219,14 +220,16 @@ iommufd_sw_msi_alloc_map(struct iommufd_ctx *ictx, ph= ys_addr_t msi_addr, } =20 if (ictx->sw_msi_id > IOMMUFD_SW_MSI_MAX_ID || - max_pgoff > (ULONG_MAX - sw_msi_start) / PAGE_SIZE) + max_pgoff > (ULONG_MAX - sw_msi_range->start) / PAGE_SIZE) return ERR_PTR(-EOVERFLOW); + if (max_pgoff >=3D sw_msi_range->length / PAGE_SIZE) + return ERR_PTR(-ENOSPC); =20 cur =3D kzalloc_obj(*cur); if (!cur) return ERR_PTR(-ENOMEM); =20 - cur->sw_msi_start =3D sw_msi_start; + cur->sw_msi_start =3D sw_msi_range->start; cur->msi_addr =3D msi_addr; cur->pgoff =3D max_pgoff; cur->id =3D ictx->sw_msi_id++; @@ -295,7 +298,7 @@ int iommufd_sw_msi(struct iommu_domain *domain, struct = msi_desc *desc, =20 handle =3D to_iommufd_handle(raw_handle); /* No IOMMU_RESV_SW_MSI means no change to the msi_msg */ - if (handle->idev->igroup->sw_msi_start =3D=3D PHYS_ADDR_MAX) + if (handle->idev->igroup->sw_msi_range.start =3D=3D PHYS_ADDR_MAX) return 0; =20 ictx =3D handle->idev->ictx; @@ -307,11 +310,11 @@ int iommufd_sw_msi(struct iommu_domain *domain, struc= t msi_desc *desc, */ msi_map =3D iommufd_sw_msi_get_map(handle->idev->ictx, msi_addr & PAGE_MASK, - handle->idev->igroup->sw_msi_start); + &handle->idev->igroup->sw_msi_range); if (!msi_map) msi_map =3D iommufd_sw_msi_alloc_map(handle->idev->ictx, msi_addr & PAGE_MASK, - handle->idev->igroup->sw_msi_start); + &handle->idev->igroup->sw_msi_range); if (IS_ERR(msi_map)) return PTR_ERR(msi_map); =20 diff --git a/drivers/iommu/iommufd/io_pagetable.c b/drivers/iommu/iommufd/i= o_pagetable.c index 4e447ce74cf6..0336d8f0908f 100644 --- a/drivers/iommu/iommufd/io_pagetable.c +++ b/drivers/iommu/iommufd/io_pagetable.c @@ -1579,7 +1579,7 @@ void iopt_remove_access(struct io_pagetable *iopt, /* Narrow the valid_iova_itree to include reserved ranges from a device. */ int iopt_table_enforce_dev_resv_regions(struct io_pagetable *iopt, struct device *dev, - phys_addr_t *sw_msi_start) + struct iommufd_sw_msi_range *sw_msi_range) { struct iommu_resv_region *resv; LIST_HEAD(resv_regions); @@ -1598,10 +1598,11 @@ int iopt_table_enforce_dev_resv_regions(struct io_p= agetable *iopt, if (resv->type =3D=3D IOMMU_RESV_DIRECT_RELAXABLE) continue; =20 - if (sw_msi_start && resv->type =3D=3D IOMMU_RESV_MSI) + if (sw_msi_range && resv->type =3D=3D IOMMU_RESV_MSI) num_hw_msi++; - if (sw_msi_start && resv->type =3D=3D IOMMU_RESV_SW_MSI) { - *sw_msi_start =3D resv->start; + if (sw_msi_range && resv->type =3D=3D IOMMU_RESV_SW_MSI) { + sw_msi_range->start =3D resv->start; + sw_msi_range->length =3D resv->length; num_sw_msi++; } =20 diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommuf= d/iommufd_private.h index 774cbe28cbaf..af7df868dd4f 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -22,6 +22,11 @@ struct iommu_option; struct iommufd_device; struct dma_buf_attachment; =20 +struct iommufd_sw_msi_range { + phys_addr_t start; + size_t length; +}; + struct iommufd_sw_msi_map { struct list_head sw_msi_item; phys_addr_t sw_msi_start; @@ -181,7 +186,7 @@ void iopt_table_remove_domain(struct io_pagetable *iopt, struct iommu_domain *domain); int iopt_table_enforce_dev_resv_regions(struct io_pagetable *iopt, struct device *dev, - phys_addr_t *sw_msi_start); + struct iommufd_sw_msi_range *sw_msi_range); int iopt_set_allow_iova(struct io_pagetable *iopt, struct rb_root_cached *allowed_iova); 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[86.49.245.11]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4887a30bcc4sm8249719f8f.1.2026.09.25.08.17.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 08:17:10 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v6 05/16] iommufd: Prepare software MSI maps for address lists Date: Fri, 25 Sep 2026 17:16:48 +0200 Message-ID: <20260925151659.419512-6-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> References: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: Cyrap3tYvSaQQ0CdzFT0-JiFW_Pc3X-B X-Proofpoint-GUID: Cyrap3tYvSaQQ0CdzFT0-JiFW_Pc3X-B X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfX9riBaUHirNw1 1Y03xmxEIP7o3tfNbu1ua3iUw0vhtVG6NFYYV/+YuNhmDYlaMI6JVs1E/rCnKg91SIOm41nLJOL n6F/crv6Wyh9V+Cu3a+taH/Ct74pX5w= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfX7GIssbGxO4ZQ V+fZp/CMn4HwpwRQ7SoL2dlfQl2pxiykBiyxpfG00c+ciZibecNhnoitBZCp0/nzQNn/rVYttLV UXBsOspX1dUoG3DmW5bgQpvPGCMwlrXirX9/PWHjE4WwGLKEhfzseCbs8jK1weRpcsN45G1bJc0 4Qjb2X1XKgqZlUq7/fovuWTMr3r3w0G/IhlXtpjGaWXugbfUAEy9SKsVSxIfpJOaAJYA3CpVbJo XaTnyuOirmZDABQOHfcx2U004DaBXt89FjDQkU9vJya4NRjn+JTnoVwuRUesEz+Hi/5MMcCD4NL VWjPU2prm51hm3Nv0UQ0tanysk+fNs3bl4Qkv8fgyHfmb1332j14xJAkDzoIbD6vtSEDapty/Bb miiAbLLnevDkrn61c3cgjPU1Vb18/fYo6yp2aV3FbqBJ0zzaHZax7a20Sg9SaqzhvcpOR6h2V+V kkmH5LDH4C33u2pLpXg== X-Authority-Analysis: v=2.4 cv=eNmGH3p1 c=1 sm=1 tr=0 ts=6ab69078 cx=c_pps a=ULNsgckmlI/WJG3HAyAuOQ==:117 a=4CXLxsOAgPM/krjtHEZQyA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=SRrdq9N9AAAA:8 a=noCGlsY9V4GqTmqY_BAA:9 a=1WsBpfsz9X-RYQiigVTh:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-25_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 spamscore=0 bulkscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609250060 Content-Type: text/plain; charset="utf-8" Teach iommufd_sw_msi_get_map() to match an ordered physical address list against an existing contiguous IOVA range. Mark the first map with the range size so an identical list can reuse the allocation. Teach iommufd_sw_msi_alloc_map() to reserve identifiers and offsets for the complete list and build its maps on a temporary list. Keep the existing scalar installation behavior and only publish newly allocated maps after installation succeeds. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/iommu/iommufd/driver.c | 161 ++++++++++++++++++------ drivers/iommu/iommufd/iommufd_private.h | 1 + 2 files changed, 123 insertions(+), 39 deletions(-) diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index c2ef15c2ca51..8b8f132ef3c5 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -179,35 +179,91 @@ EXPORT_SYMBOL_NS_GPL(iommufd_viommu_report_event, "IO= MMUFD"); =20 #ifdef CONFIG_IRQ_MSI_IOMMU /* - * Get a iommufd_sw_msi_map for the msi physical address requested by the = irq + * Get an iommufd_sw_msi_map for the msi physical addresses requested by t= he irq * layer. The mapping to IOVA is global to the iommufd file descriptor, ev= ery * domain that is attached to a device using the same MSI parameters will = use - * the same IOVA. + * the same contiguous IOVA range. */ static struct iommufd_sw_msi_map * -iommufd_sw_msi_get_map(struct iommufd_ctx *ictx, phys_addr_t msi_addr, - const struct iommufd_sw_msi_range *sw_msi_range) +iommufd_sw_msi_get_map(struct iommufd_ctx *ictx, const phys_addr_t *phys_a= ddrs, + unsigned int nr_addrs, const struct iommufd_sw_msi_range *sw_msi_= range) { - struct iommufd_sw_msi_map *cur; + struct iommufd_sw_msi_map *cur, *msi_map; + unsigned int nr_found; =20 lockdep_assert_held(&ictx->sw_msi_lock); =20 - list_for_each_entry(cur, &ictx->sw_msi_list, sw_msi_item) { - if (cur->sw_msi_start !=3D sw_msi_range->start || - cur->pgoff >=3D sw_msi_range->length / PAGE_SIZE) + list_for_each_entry(msi_map, &ictx->sw_msi_list, sw_msi_item) { + if (msi_map->sw_msi_start !=3D sw_msi_range->start || + msi_map->msi_addr !=3D phys_addrs[0]) + continue; + if (msi_map->range_size !=3D nr_addrs * PAGE_SIZE) continue; - if (cur->msi_addr =3D=3D msi_addr) - return cur; + if (msi_map->pgoff > sw_msi_range->length / PAGE_SIZE || + nr_addrs > sw_msi_range->length / PAGE_SIZE - msi_map->pgoff) + continue; + + nr_found =3D 0; + list_for_each_entry(cur, &ictx->sw_msi_list, sw_msi_item) { + unsigned int index; + + if (cur->sw_msi_start !=3D sw_msi_range->start || + cur->pgoff < msi_map->pgoff) + continue; + index =3D cur->pgoff - msi_map->pgoff; + if (index >=3D nr_addrs) + continue; + if (cur->msi_addr !=3D phys_addrs[index]) + break; + nr_found++; + } + if (nr_found =3D=3D nr_addrs) + return msi_map; } return NULL; } =20 +static int iommufd_sw_msi_check_alloc(struct iommufd_ctx *ictx, + const struct iommufd_sw_msi_range *sw_msi_range, + unsigned int first_pgoff, unsigned int nr_addrs, + size_t *range_size) +{ + unsigned long max_iova_pgoff; + unsigned int last_pgoff; + unsigned int last_id; + size_t range_pages; + + if (!nr_addrs) + return -EINVAL; + if (sw_msi_range->start > ULONG_MAX) + return -EOVERFLOW; + + range_pages =3D sw_msi_range->length / PAGE_SIZE; + max_iova_pgoff =3D (ULONG_MAX - sw_msi_range->start) / PAGE_SIZE; + + if (check_add_overflow(ictx->sw_msi_id, nr_addrs - 1, &last_id) || + last_id > IOMMUFD_SW_MSI_MAX_ID || + check_add_overflow(first_pgoff, nr_addrs - 1, &last_pgoff) || + last_pgoff > max_iova_pgoff || + check_mul_overflow((size_t)nr_addrs, PAGE_SIZE, range_size)) + return -EOVERFLOW; + + if (last_pgoff >=3D range_pages) + return -ENOSPC; + + return 0; +} + static struct iommufd_sw_msi_map * -iommufd_sw_msi_alloc_map(struct iommufd_ctx *ictx, phys_addr_t msi_addr, - const struct iommufd_sw_msi_range *sw_msi_range) +iommufd_sw_msi_alloc_map(struct iommufd_ctx *ictx, const phys_addr_t *phys= _addrs, + unsigned int nr_addrs, const struct iommufd_sw_msi_range *sw_msi_range, + struct list_head *new_msi_maps) { - struct iommufd_sw_msi_map *cur; - unsigned int max_pgoff =3D 0; + struct iommufd_sw_msi_map *cur, *first_map =3D NULL; + unsigned int next_pgoff =3D 0; + unsigned int i; + size_t size; + int rc; =20 lockdep_assert_held(&ictx->sw_msi_lock); =20 @@ -216,25 +272,38 @@ iommufd_sw_msi_alloc_map(struct iommufd_ctx *ictx, ph= ys_addr_t msi_addr, continue; if (cur->pgoff =3D=3D UINT_MAX) return ERR_PTR(-EOVERFLOW); - max_pgoff =3D max(max_pgoff, cur->pgoff + 1); + next_pgoff =3D max(next_pgoff, cur->pgoff + 1); } =20 - if (ictx->sw_msi_id > IOMMUFD_SW_MSI_MAX_ID || - max_pgoff > (ULONG_MAX - sw_msi_range->start) / PAGE_SIZE) - return ERR_PTR(-EOVERFLOW); - if (max_pgoff >=3D sw_msi_range->length / PAGE_SIZE) - return ERR_PTR(-ENOSPC); - - cur =3D kzalloc_obj(*cur); - if (!cur) - return ERR_PTR(-ENOMEM); - - cur->sw_msi_start =3D sw_msi_range->start; - cur->msi_addr =3D msi_addr; - cur->pgoff =3D max_pgoff; - cur->id =3D ictx->sw_msi_id++; - list_add_tail(&cur->sw_msi_item, &ictx->sw_msi_list); - return cur; + rc =3D iommufd_sw_msi_check_alloc(ictx, sw_msi_range, next_pgoff, nr_addr= s, &size); + if (rc) + return ERR_PTR(rc); + + for (i =3D 0; i < nr_addrs; i++) { + cur =3D kzalloc_obj(*cur); + if (!cur) + goto err_free; + + cur->sw_msi_start =3D sw_msi_range->start; + cur->msi_addr =3D phys_addrs[i]; + cur->pgoff =3D next_pgoff + i; + cur->id =3D ictx->sw_msi_id + i; + if (!i) { + cur->range_size =3D size; + first_map =3D cur; + } + list_add_tail(&cur->sw_msi_item, new_msi_maps); + } + + return first_map; + +err_free: + while (!list_empty(new_msi_maps)) { + cur =3D list_first_entry(new_msi_maps, typeof(*cur), sw_msi_item); + list_del(&cur->sw_msi_item); + kfree(cur); + } + return ERR_PTR(-ENOMEM); } =20 int iommufd_sw_msi_install(struct iommufd_ctx *ictx, @@ -280,7 +349,9 @@ int iommufd_sw_msi(struct iommu_domain *domain, struct = msi_desc *desc, struct iommufd_attach_handle *handle; struct iommufd_sw_msi_map *msi_map; struct iommufd_ctx *ictx; + LIST_HEAD(new_msi_maps); unsigned long iova; + phys_addr_t phys_addr; int rc; =20 /* @@ -308,29 +379,41 @@ int iommufd_sw_msi(struct iommu_domain *domain, struc= t msi_desc *desc, * assume the caller has checked that it is contained with a MMIO region * that is secure to map at PAGE_SIZE. */ - msi_map =3D iommufd_sw_msi_get_map(handle->idev->ictx, - msi_addr & PAGE_MASK, - &handle->idev->igroup->sw_msi_range); + phys_addr =3D msi_addr & PAGE_MASK; + msi_map =3D iommufd_sw_msi_get_map(ictx, &phys_addr, 1, &handle->idev->ig= roup->sw_msi_range); if (!msi_map) - msi_map =3D iommufd_sw_msi_alloc_map(handle->idev->ictx, - msi_addr & PAGE_MASK, - &handle->idev->igroup->sw_msi_range); + msi_map =3D iommufd_sw_msi_alloc_map(ictx, &phys_addr, 1, + &handle->idev->igroup->sw_msi_range, + &new_msi_maps); if (IS_ERR(msi_map)) return PTR_ERR(msi_map); =20 rc =3D iommufd_sw_msi_maps_ensure(&handle->idev->igroup->required_sw_msi, msi_map->id); if (rc) - return rc; + goto err_free; =20 rc =3D iommufd_sw_msi_install(ictx, hwpt_paging, msi_map); if (rc) - return rc; + goto err_free; __set_bit(msi_map->id, handle->idev->igroup->required_sw_msi.bitmap); =20 + if (!list_empty(&new_msi_maps)) { + list_splice_tail_init(&new_msi_maps, &ictx->sw_msi_list); + ictx->sw_msi_id++; + } + iova =3D msi_map->sw_msi_start + msi_map->pgoff * PAGE_SIZE; msi_desc_set_iommu_msi_iova(desc, iova, PAGE_SHIFT); return 0; + +err_free: + while (!list_empty(&new_msi_maps)) { + msi_map =3D list_first_entry(&new_msi_maps, typeof(*msi_map), sw_msi_ite= m); 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[86.49.245.11]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49fe5cd4c8dsm176773155e9.3.2026.09.25.08.17.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 08:17:13 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v6 06/16] iommufd: Install software MSI map ranges atomically Date: Fri, 25 Sep 2026 17:16:49 +0200 Message-ID: <20260925151659.419512-7-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> References: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfX+0e1WX5XAmnl +m1MQo55JTV7mXwxVlOB8wCuczqj/eXumcVoTJv8YZUnu68YbMyVjnbY4rmk7g3o3TsdeVs05DA NeLLh7Fn4iJ0/uUIugigz4YWVBwxA/d4dGwoxAZhy+t0/apKx1JNRZmkk8V42ldgVotsGmCQM/D QJ2H19VpBx10IhUoNTPplLKdS63RKmMsscAIjW1gTxuMgKt6KLOW++3ZJ6tVGd+qSImIzET87A2 PaMobHaLKJu71XUE/oRTJu4PUlRw5+3RDw+gTTKS39lblyUtz+x2N/8/W/YVkzasR5Lj2akn3kF XQLh2kD9AKopmMyNV9XsE3pFHDTTQ4j09NC2mVknYmHmZKy5a7AM+3ejzTVTxG8e3fgxnUYEqFj dQzaKjUcC93UmuNRTcl7v6KChCcTxQ/wPQO87F0Eyit0y9XF4DYrGgxJrxhTF/++aFzgdYt3iQQ MXnIc0rOB6AzSqpbjOA== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfX8tWXQgVhwBwa rEUNhZF6vcVLz308LGWNIFacodsRtYpWh/g73DVV6dMyOXNhzgdpoPYQqPsOyIfOSDiHRyhKYer YQBIc2NGzt+6/YtbsV4bMTqpLdeZMiM= X-Proofpoint-GUID: KDntEFB50G1cpla8iiDeuIz1yLVWvSAI X-Proofpoint-ORIG-GUID: KDntEFB50G1cpla8iiDeuIz1yLVWvSAI X-Authority-Analysis: v=2.4 cv=EJWTQFZC c=1 sm=1 tr=0 ts=6ab6907b cx=c_pps a=DUEm7b3gzWu7BqY5nP7+9g==:117 a=4CXLxsOAgPM/krjtHEZQyA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=SRrdq9N9AAAA:8 a=0NqqyPg6VgUUedX_kk0A:9 a=-aSRE8QhW-JAV6biHavz:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-25_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 bulkscore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609250060 Content-Type: text/plain; charset="utf-8" Add a range installation helper which installs every map in a contiguous software MSI range and rolls back only mappings added by the failed operation. Use the helper when replaying range mappings into a new paging domain. This prepares iommufd to publish and install physical address lists without exposing partially installed ranges. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/iommu/iommufd/driver.c | 76 ++++++++++++++++++++++++++++++---- 1 file changed, 68 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index 8b8f132ef3c5..3aff04d9dd04 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -178,6 +178,17 @@ int iommufd_viommu_report_event(struct iommufd_viommu = *viommu, EXPORT_SYMBOL_NS_GPL(iommufd_viommu_report_event, "IOMMUFD"); =20 #ifdef CONFIG_IRQ_MSI_IOMMU +static bool iommufd_sw_msi_range_index(const struct iommufd_sw_msi_map *ma= p, + const struct iommufd_sw_msi_map *base_map, + unsigned int nr_addrs, unsigned int *index) +{ + if (map->sw_msi_start !=3D base_map->sw_msi_start || map->pgoff < base_ma= p->pgoff) + return false; + + *index =3D map->pgoff - base_map->pgoff; + return *index < nr_addrs; +} + /* * Get an iommufd_sw_msi_map for the msi physical addresses requested by t= he irq * layer. The mapping to IOVA is global to the iommufd file descriptor, ev= ery @@ -207,11 +218,7 @@ iommufd_sw_msi_get_map(struct iommufd_ctx *ictx, const= phys_addr_t *phys_addrs, list_for_each_entry(cur, &ictx->sw_msi_list, sw_msi_item) { unsigned int index; =20 - if (cur->sw_msi_start !=3D sw_msi_range->start || - cur->pgoff < msi_map->pgoff) - continue; - index =3D cur->pgoff - msi_map->pgoff; - if (index >=3D nr_addrs) + if (!iommufd_sw_msi_range_index(cur, msi_map, nr_addrs, &index)) continue; if (cur->msi_addr !=3D phys_addrs[index]) break; @@ -306,9 +313,9 @@ iommufd_sw_msi_alloc_map(struct iommufd_ctx *ictx, cons= t phys_addr_t *phys_addrs return ERR_PTR(-ENOMEM); } =20 -int iommufd_sw_msi_install(struct iommufd_ctx *ictx, - struct iommufd_hwpt_paging *hwpt_paging, - struct iommufd_sw_msi_map *msi_map) +static int iommufd_sw_msi_install_one(struct iommufd_ctx *ictx, + struct iommufd_hwpt_paging *hwpt_paging, + struct iommufd_sw_msi_map *msi_map) { unsigned long iova; int rc; @@ -332,6 +339,59 @@ int iommufd_sw_msi_install(struct iommufd_ctx *ictx, __set_bit(msi_map->id, hwpt_paging->present_sw_msi.bitmap); return 0; } + +int iommufd_sw_msi_install(struct iommufd_ctx *ictx, + struct iommufd_hwpt_paging *hwpt_paging, + struct iommufd_sw_msi_map *base_map) +{ + struct iommufd_sw_msi_map *msi_map; + struct list_head *msi_maps =3D &ictx->sw_msi_list; + unsigned long *newly_mapped; + unsigned int nr_addrs =3D base_map->range_size ? base_map->range_size / P= AGE_SIZE : 1; + unsigned int nr_found =3D 0; + unsigned int index; + int rc =3D 0; + + newly_mapped =3D bitmap_zalloc(nr_addrs, GFP_KERNEL_ACCOUNT); + if (!newly_mapped) + return -ENOMEM; + + list_for_each_entry(msi_map, msi_maps, sw_msi_item) { + if (!iommufd_sw_msi_range_index(msi_map, base_map, nr_addrs, &index)) + continue; + if (iommufd_sw_msi_maps_test_bit(&hwpt_paging->present_sw_msi, msi_map->= id)) { + nr_found++; + continue; + } + rc =3D iommufd_sw_msi_install_one(ictx, hwpt_paging, msi_map); + if (rc) + goto err_unmap; + __set_bit(index, newly_mapped); + nr_found++; + } + if (nr_found !=3D nr_addrs) { + rc =3D -EINVAL; + goto err_unmap; + } + + bitmap_free(newly_mapped); + return 0; + +err_unmap: + list_for_each_entry(msi_map, msi_maps, sw_msi_item) { + unsigned long iova; + + if (!iommufd_sw_msi_range_index(msi_map, base_map, nr_addrs, &index) || + !test_bit(index, newly_mapped)) + continue; + + iova =3D msi_map->sw_msi_start + msi_map->pgoff * PAGE_SIZE; + WARN_ON_ONCE(iommu_unmap(hwpt_paging->common.domain, iova, PAGE_SIZE) != =3D PAGE_SIZE); + __clear_bit(msi_map->id, hwpt_paging->present_sw_msi.bitmap); + } + bitmap_free(newly_mapped); + return rc; +} EXPORT_SYMBOL_NS_GPL(iommufd_sw_msi_install, "IOMMUFD_INTERNAL"); =20 /* --=20 2.43.0 From nobody Sat Sep 26 14:39:04 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66B4B4C6EFC for ; Fri, 25 Sep 2026 15:17:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[86.49.245.11]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49fe5de187asm153857745e9.7.2026.09.25.08.17.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 08:17:14 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v6 07/16] iommufd: Prepare software MSI installation for address lists Date: Fri, 25 Sep 2026 17:16:50 +0200 Message-ID: <20260925151659.419512-8-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> References: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=aaj0Dhot c=1 sm=1 tr=0 ts=6ab6907d cx=c_pps a=N1BjEkVkxJi3uNfLdpvX3g==:117 a=4CXLxsOAgPM/krjtHEZQyA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=SRrdq9N9AAAA:8 a=fyE6B5mSzfnmm1qxREQA:9 a=crWF4MFLhNY0qMRaF8an:22 X-Proofpoint-GUID: levnzbuOAlKcweU1rwl5qzS2nauacyO1 X-Proofpoint-ORIG-GUID: levnzbuOAlKcweU1rwl5qzS2nauacyO1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfXz3/ZPDxVbBWu idUDPLIijbNNaUobfkg6ltXtcUUm93UERYUMXKK4woHyrIWmpf/ZWKnG8ML9/ZgwMRFoDNZVJNm eABfmfdc+6203iBcWUY8M2vZH82I4Lky0QpTOel+n00xx4X7Ycrn6bMQObd50fghtp4IvgbBYR2 1tBjjXk1MfyKn9c7vIvHvnSdhgEknfKNUHRLeOoCvho9HPRrs/9hySIjLHqzwP9fcQq6w/Qb0CV MXdeHX2KUJgl40ug76/nYa4JVL8tzYokZLt1KwLsoME31n4e5UzIOLmIjGHIuZReuopq6JXZjp0 H45klmFpeFxGyRh5BBlzwUocvxwxIoaoab5dJCkKRS7VYOuG2sQJW+o7Rti6OuB+Podn0zEEaIj Di4ofWGdjVWw4mA6J4C1TMWBIeW2wXu0AAl1VULgoGLt/E6XvK8/fb+VLHWJj5dFHGojjmw410D o5F82uKob/evWKusc5A== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfX5xSR4Nh5nkcP CRXpx/ewmPSxXx63XavIQ1jfgXh+9j5vq2lLHTUo785PdemiijVBm/ca9KySYTlJOHAkWqueRDV xsaxEe0hIHyOQchP2Fn7UAwEVSyXYxo= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-25_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 priorityscore=1501 spamscore=0 bulkscore=0 clxscore=1015 phishscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609250060 Content-Type: text/plain; charset="utf-8" Teach the software MSI path to install every mapping in an address list before publishing newly allocated maps. Mark the complete list as required by the group and roll back mappings installed by a failed operation. Keep iommufd_sw_msi() as a one-address wrapper so existing callers retain their current behavior. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/iommu/iommufd/driver.c | 101 +++++++++++++++++++++++---------- 1 file changed, 72 insertions(+), 29 deletions(-) diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index 3aff04d9dd04..f4e812e43822 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -340,14 +340,14 @@ static int iommufd_sw_msi_install_one(struct iommufd_= ctx *ictx, return 0; } =20 -int iommufd_sw_msi_install(struct iommufd_ctx *ictx, - struct iommufd_hwpt_paging *hwpt_paging, - struct iommufd_sw_msi_map *base_map) +static int __iommufd_sw_msi_install_range(struct iommufd_ctx *ictx, + struct iommufd_hwpt_paging *hwpt_paging, + struct list_head *msi_maps, + const struct iommufd_sw_msi_map *base_map, + unsigned int nr_addrs) { struct iommufd_sw_msi_map *msi_map; - struct list_head *msi_maps =3D &ictx->sw_msi_list; unsigned long *newly_mapped; - unsigned int nr_addrs =3D base_map->range_size ? base_map->range_size / P= AGE_SIZE : 1; unsigned int nr_found =3D 0; unsigned int index; int rc =3D 0; @@ -392,16 +392,36 @@ int iommufd_sw_msi_install(struct iommufd_ctx *ictx, bitmap_free(newly_mapped); return rc; } + +int iommufd_sw_msi_install(struct iommufd_ctx *ictx, + struct iommufd_hwpt_paging *hwpt_paging, + struct iommufd_sw_msi_map *base_map) +{ + unsigned int nr_addrs =3D base_map->range_size ? base_map->range_size / P= AGE_SIZE : 1; + + return __iommufd_sw_msi_install_range(ictx, hwpt_paging, &ictx->sw_msi_li= st, base_map, + nr_addrs); +} EXPORT_SYMBOL_NS_GPL(iommufd_sw_msi_install, "IOMMUFD_INTERNAL"); =20 -/* - * Called by the irq code if the platform translates the MSI address throu= gh the - * IOMMU. msi_addr is the physical address of the MSI page. iommufd will - * allocate a fd global iova for the physical page that is the same on all - * domains and devices. - */ -int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr) +static void iommufd_sw_msi_set_required(struct iommufd_group *igroup, + struct list_head *msi_maps, + const struct iommufd_sw_msi_map *base_map, + unsigned int nr_addrs) +{ + struct iommufd_sw_msi_map *msi_map; + unsigned int index; + + list_for_each_entry(msi_map, msi_maps, sw_msi_item) { + if (!iommufd_sw_msi_range_index(msi_map, base_map, nr_addrs, &index)) + continue; + __set_bit(msi_map->id, igroup->required_sw_msi.bitmap); + } +} + +static int iommufd_sw_msi_list(struct iommu_domain *domain, struct msi_des= c *desc, + const phys_addr_t *phys_addrs, unsigned int nr_addrs, + size_t granule) { struct device *dev =3D msi_desc_to_dev(desc); struct iommufd_hwpt_paging *hwpt_paging; @@ -410,10 +430,19 @@ int iommufd_sw_msi(struct iommu_domain *domain, struc= t msi_desc *desc, struct iommufd_sw_msi_map *msi_map; struct iommufd_ctx *ictx; LIST_HEAD(new_msi_maps); + struct list_head *msi_maps; unsigned long iova; - phys_addr_t phys_addr; + unsigned int i; int rc; =20 + if (granule !=3D PAGE_SIZE) + return -EOPNOTSUPP; + if (!nr_addrs || nr_addrs > SIZE_MAX / PAGE_SIZE) + return -EINVAL; + for (i =3D 0; i < nr_addrs; i++) + if (!IS_ALIGNED(phys_addrs[i], PAGE_SIZE)) + return -EINVAL; + /* * It is safe to call iommu_attach_handle_get() here because the iommu * core code invokes this under the group mutex which also prevents any @@ -434,33 +463,33 @@ int iommufd_sw_msi(struct iommu_domain *domain, struc= t msi_desc *desc, =20 ictx =3D handle->idev->ictx; guard(mutex)(&ictx->sw_msi_lock); - /* - * The input msi_addr is the exact byte offset of the MSI doorbell, we - * assume the caller has checked that it is contained with a MMIO region - * that is secure to map at PAGE_SIZE. - */ - phys_addr =3D msi_addr & PAGE_MASK; - msi_map =3D iommufd_sw_msi_get_map(ictx, &phys_addr, 1, &handle->idev->ig= roup->sw_msi_range); - if (!msi_map) - msi_map =3D iommufd_sw_msi_alloc_map(ictx, &phys_addr, 1, + msi_map =3D iommufd_sw_msi_get_map(ictx, phys_addrs, nr_addrs, + &handle->idev->igroup->sw_msi_range); + if (msi_map) { + msi_maps =3D &ictx->sw_msi_list; + } else { + msi_map =3D iommufd_sw_msi_alloc_map(ictx, phys_addrs, nr_addrs, &handle->idev->igroup->sw_msi_range, &new_msi_maps); - if (IS_ERR(msi_map)) - return PTR_ERR(msi_map); + if (IS_ERR(msi_map)) + return PTR_ERR(msi_map); + msi_maps =3D &new_msi_maps; + } =20 rc =3D iommufd_sw_msi_maps_ensure(&handle->idev->igroup->required_sw_msi, - msi_map->id); + msi_map->id + nr_addrs - 1); if (rc) goto err_free; =20 - rc =3D iommufd_sw_msi_install(ictx, hwpt_paging, msi_map); + rc =3D __iommufd_sw_msi_install_range(ictx, hwpt_paging, msi_maps, msi_ma= p, nr_addrs); if (rc) goto err_free; - __set_bit(msi_map->id, handle->idev->igroup->required_sw_msi.bitmap); + + iommufd_sw_msi_set_required(handle->idev->igroup, msi_maps, msi_map, nr_a= ddrs); =20 if (!list_empty(&new_msi_maps)) { list_splice_tail_init(&new_msi_maps, &ictx->sw_msi_list); - ictx->sw_msi_id++; + ictx->sw_msi_id +=3D nr_addrs; } =20 iova =3D msi_map->sw_msi_start + msi_map->pgoff * PAGE_SIZE; @@ -475,6 +504,20 @@ int iommufd_sw_msi(struct iommu_domain *domain, struct= msi_desc *desc, } return rc; } + +/* + * Called by the irq code if the platform translates the MSI address throu= gh the + * IOMMU. msi_addr is the physical address of the MSI page. iommufd will + * allocate a fd global iova for the physical page that is the same on all + * domains and devices. + */ +int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, + phys_addr_t msi_addr) +{ + phys_addr_t phys_addr =3D msi_addr & PAGE_MASK; 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[86.49.245.11]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49ff023f12esm66909405e9.0.2026.09.25.08.17.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 08:17:16 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v6 08/16] iommu/dma: Introduce iommu_dma_prepare_msi_list() Date: Fri, 25 Sep 2026 17:16:51 +0200 Message-ID: <20260925151659.419512-9-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> References: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=aaj0Dhot c=1 sm=1 tr=0 ts=6ab6907f cx=c_pps a=5HAIKLe1ejAbszaTRHs9Ug==:117 a=4CXLxsOAgPM/krjtHEZQyA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=SRrdq9N9AAAA:8 a=2ceW4JgIosI8Fxwmn1gA:9 a=gYDTvv6II1OnSo0itH1n:22 X-Proofpoint-GUID: y1LL3xSR4eFFtxp9sX15E98Ri6Wjruyw X-Proofpoint-ORIG-GUID: y1LL3xSR4eFFtxp9sX15E98Ri6Wjruyw X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfXxY4UV3CV0uZf tq6iD8tW0FeQX2wzyculeiTiZ+sZ9rp1+fOYrhhDfdAGrPlbbv0OdhNXkeJX3CII4v4mqAWsih3 APWEnn7SvcmAHbMUzitca9Hpwd5KjBPlq+XztFqn6vklk+8azujA6mybV2Jf8fW+TYBu5fBaUN5 0NFX4Jhp3t7aYm/P28KE735MRpQi7stKFbgTpqRtMB6Z4I9yji0OxAp7+RPJXk222ZEkcZU7zKK pgjQ8dKrVAvBiliV23pSiqOg+VW4ThS2DSSyc3Axk3i61/l3ZzC+RO4FF2wznoso5ZriwTbO9fR q+41MR1BjgcvtA8FyyjkCB+/6ptznWRJc7B3Zuds31yDQRqdp0zlwSA9ThWOOA4FT65RWgiqbZE er96kbpunldJV6UYuyHDRmURIs2DyebNoel3IsTETTv4uhPBRngQZkQT6wko/IVFPWsaNAlaH8h dSdbMWN9qziZ837g4Bw== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfX4Pf/fdJRPRSu FqIjZ58h6aMw547BwVILHeUVh3BwVPao0YngmrkM3b6F8zt3kaQX1yTWPzk1kUg43KPN7hTViTA HoJY8kD+cHAex4RgSk34cyGQ5i+ngXc= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-25_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 priorityscore=1501 spamscore=0 bulkscore=0 clxscore=1015 phishscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609250060 Content-Type: text/plain; charset="utf-8" Add iommu_dma_prepare_msi_list() to map an ordered physical address list through the current domain backend. Validate that the requested granule is a power of two no smaller than PAGE_SIZE and that every address is aligned to it. Refactor iommu_dma_prepare_msi() to obtain the backend granule and align its single address before using the same list dispatcher. Convert the DMA-IOMMU and iommufd backend entry points to consume address lists directly. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/iommu/dma-iommu.c | 13 ++-- drivers/iommu/dma-iommu.h | 13 +++- drivers/iommu/iommu-priv.h | 7 ++- drivers/iommu/iommu.c | 109 +++++++++++++++++++++++++++------ drivers/iommu/iommufd/driver.c | 24 +++----- include/linux/iommu.h | 8 +++ 6 files changed, 126 insertions(+), 48 deletions(-) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 0b4eb47d1a95..dc7b369792e4 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -2168,7 +2168,7 @@ static bool has_msi_cookie(const struct iommu_domain = *domain) domain->cookie_type =3D=3D IOMMU_COOKIE_DMA_MSI); } =20 -static size_t cookie_msi_granule(const struct iommu_domain *domain) +size_t iommu_dma_msi_granule(const struct iommu_domain *domain) { switch (domain->cookie_type) { case IOMMU_COOKIE_DMA_IOVA: @@ -2299,23 +2299,20 @@ static struct iommu_dma_msi_page *iommu_dma_get_msi= _page(struct device *dev, } =20 int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr) + const phys_addr_t *phys_addrs, unsigned int nr_addrs, size_t granul= e) { struct device *dev =3D msi_desc_to_dev(desc); const struct iommu_dma_msi_page *msi_page; - phys_addr_t phys_addr; - size_t granule; =20 if (!has_msi_cookie(domain)) { msi_desc_set_iommu_msi_iova(desc, 0, 0); return 0; } - - granule =3D cookie_msi_granule(domain); - phys_addr =3D ALIGN_DOWN(msi_addr, granule); + if (granule !=3D iommu_dma_msi_granule(domain)) + return -EOPNOTSUPP; =20 iommu_group_mutex_assert(dev); - msi_page =3D iommu_dma_get_msi_page(dev, &phys_addr, 1, granule, domain); + msi_page =3D iommu_dma_get_msi_page(dev, phys_addrs, nr_addrs, granule, d= omain); if (!msi_page) return -ENOMEM; =20 diff --git a/drivers/iommu/dma-iommu.h b/drivers/iommu/dma-iommu.h index 040d00252563..bf9cd4102d35 100644 --- a/drivers/iommu/dma-iommu.h +++ b/drivers/iommu/dma-iommu.h @@ -19,8 +19,9 @@ int iommu_dma_init_fq(struct iommu_domain *domain); =20 void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list= ); =20 +size_t iommu_dma_msi_granule(const struct iommu_domain *domain); int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr); + const phys_addr_t *phys_addrs, unsigned int nr_addrs, size_t granul= e); =20 extern bool iommu_dma_forcedac; =20 @@ -53,8 +54,14 @@ static inline void iommu_dma_get_resv_regions(struct dev= ice *dev, struct list_he { } =20 -static inline int iommu_dma_sw_msi(struct iommu_domain *domain, - struct msi_desc *desc, phys_addr_t msi_addr) +static inline size_t iommu_dma_msi_granule(const struct iommu_domain *doma= in) +{ + return 0; +} + +static inline int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi= _desc *desc, + const phys_addr_t *phys_addrs, unsigned int nr_addrs, + size_t granule) { return -ENODEV; } diff --git a/drivers/iommu/iommu-priv.h b/drivers/iommu/iommu-priv.h index aaffad5854fc..1122c99566d5 100644 --- a/drivers/iommu/iommu-priv.h +++ b/drivers/iommu/iommu-priv.h @@ -54,10 +54,11 @@ int iommu_replace_group_handle(struct iommu_group *grou= p, =20 #if IS_ENABLED(CONFIG_IOMMUFD_DRIVER_CORE) && IS_ENABLED(CONFIG_IRQ_MSI_IO= MMU) int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr); + const phys_addr_t *phys_addrs, unsigned int nr_addrs, size_t granule); #else /* !CONFIG_IOMMUFD_DRIVER_CORE || !CONFIG_IRQ_MSI_IOMMU */ -static inline int iommufd_sw_msi(struct iommu_domain *domain, - struct msi_desc *desc, phys_addr_t msi_addr) +static inline int iommufd_sw_msi(struct iommu_domain *domain, struct msi_d= esc *desc, + const phys_addr_t *phys_addrs, unsigned int nr_addrs, + size_t granule) { return -EOPNOTSUPP; } diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index b486b8bbd1fc..07602b467582 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -4223,21 +4223,89 @@ void pci_dev_reset_iommu_done(struct pci_dev *pdev) EXPORT_SYMBOL_GPL(pci_dev_reset_iommu_done); =20 #if IS_ENABLED(CONFIG_IRQ_MSI_IOMMU) +static int __iommu_dma_prepare_msi_list(struct iommu_group *group, struct = msi_desc *desc, + const phys_addr_t *phys_addrs, unsigned int nr_addrs, + size_t granule) +{ + if (!group->domain || group->domain->type =3D=3D IOMMU_DOMAIN_IDENTITY) + return 0; + + switch (group->domain->cookie_type) { + case IOMMU_COOKIE_DMA_MSI: + case IOMMU_COOKIE_DMA_IOVA: + return iommu_dma_sw_msi(group->domain, desc, phys_addrs, nr_addrs, granu= le); + case IOMMU_COOKIE_IOMMUFD: + return iommufd_sw_msi(group->domain, desc, phys_addrs, nr_addrs, granule= ); + default: + return -EOPNOTSUPP; + } +} + +static int iommu_dma_validate_msi_list(const phys_addr_t *phys_addrs, unsi= gned int nr_addrs, + size_t granule) +{ + unsigned int i; + + if (!nr_addrs || granule < PAGE_SIZE || !is_power_of_2(granule) || + nr_addrs > SIZE_MAX / granule) + return -EINVAL; + + for (i =3D 0; i < nr_addrs; i++) + if (!IS_ALIGNED(phys_addrs[i], granule)) + return -EINVAL; + + return 0; +} + +/** + * iommu_dma_prepare_msi_list() - Map MSI pages in the IOMMU domain + * @desc: MSI descriptor to update with the base IOVA + * @phys_addrs: Ordered MSI target physical addresses + * @nr_addrs: Number of addresses in @phys_addrs + * @granule: Mapping granule for every address + * + * @nr_addrs must be nonzero and @granule must be a power of two no smalle= r than + * PAGE_SIZE. Every address must be aligned to @granule. The addresses are= mapped + * in order to one contiguous IOVA range and may repeat. The list is consu= med + * synchronously and is not retained. + * + * When a software MSI mapping is required, the backend records the base I= OVA + * and granule shift in @desc. Otherwise, @desc is left unchanged. + * + * Return: 0 on success, -EINVAL if the parameters are invalid, -EOPNOTSUP= P if + * the domain backend cannot provide the mapping, or another negative error + * code from the backend. + */ +int iommu_dma_prepare_msi_list(struct msi_desc *desc, const phys_addr_t *p= hys_addrs, + unsigned int nr_addrs, size_t granule) +{ + struct device *dev =3D msi_desc_to_dev(desc); + struct iommu_group *group =3D dev->iommu_group; + int ret; + + ret =3D iommu_dma_validate_msi_list(phys_addrs, nr_addrs, granule); + if (ret || !group) + return ret; + + mutex_lock(&group->mutex); + ret =3D __iommu_dma_prepare_msi_list(group, desc, phys_addrs, nr_addrs, g= ranule); + mutex_unlock(&group->mutex); + return ret; +} + /** * iommu_dma_prepare_msi() - Map the MSI page in the IOMMU domain * @desc: MSI descriptor, will store the MSI page * @msi_addr: MSI target address to be mapped * - * The implementation of sw_msi() should take msi_addr and map it to - * an IOVA in the domain and call msi_desc_set_iommu_msi_iova() with the - * mapping information. - * * Return: 0 on success or negative error code if the mapping failed. */ int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr) { struct device *dev =3D msi_desc_to_dev(desc); struct iommu_group *group =3D dev->iommu_group; + phys_addr_t phys_addr; + size_t granule; int ret =3D 0; =20 if (!group) @@ -4248,21 +4316,26 @@ int iommu_dma_prepare_msi(struct msi_desc *desc, ph= ys_addr_t msi_addr) return ret; =20 mutex_lock(&group->mutex); - /* An IDENTITY domain must pass through */ - if (group->domain && group->domain->type !=3D IOMMU_DOMAIN_IDENTITY) { - switch (group->domain->cookie_type) { - case IOMMU_COOKIE_DMA_MSI: - case IOMMU_COOKIE_DMA_IOVA: - ret =3D iommu_dma_sw_msi(group->domain, desc, msi_addr); - break; - case IOMMU_COOKIE_IOMMUFD: - ret =3D iommufd_sw_msi(group->domain, desc, msi_addr); - break; - default: - ret =3D -EOPNOTSUPP; - break; - } + if (!group->domain || group->domain->type =3D=3D IOMMU_DOMAIN_IDENTITY) + goto out_unlock; + + switch (group->domain->cookie_type) { + case IOMMU_COOKIE_DMA_MSI: + case IOMMU_COOKIE_DMA_IOVA: + granule =3D iommu_dma_msi_granule(group->domain); + break; + case IOMMU_COOKIE_IOMMUFD: + granule =3D PAGE_SIZE; + break; + default: + ret =3D -EOPNOTSUPP; + goto out_unlock; } + + phys_addr =3D ALIGN_DOWN(msi_addr, granule); + ret =3D __iommu_dma_prepare_msi_list(group, desc, &phys_addr, 1, granule); + +out_unlock: mutex_unlock(&group->mutex); return ret; } diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index f4e812e43822..99104be956ca 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -419,9 +419,14 @@ static void iommufd_sw_msi_set_required(struct iommufd= _group *igroup, } } =20 -static int iommufd_sw_msi_list(struct iommu_domain *domain, struct msi_des= c *desc, - const phys_addr_t *phys_addrs, unsigned int nr_addrs, - size_t granule) +/* + * Called by the irq code if the platform translates the MSI addresses thr= ough the + * IOMMU. phys_addrs are the physical addresses of the MSI pages. iommufd = will + * allocate contiguous fd global iovas for the physical pages that are the= same on + * all domains and devices. + */ +int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, + const phys_addr_t *phys_addrs, unsigned int nr_addrs, size_t granule) { struct device *dev =3D msi_desc_to_dev(desc); struct iommufd_hwpt_paging *hwpt_paging; @@ -505,19 +510,6 @@ static int iommufd_sw_msi_list(struct iommu_domain *do= main, struct msi_desc *des return rc; } =20 -/* - * Called by the irq code if the platform translates the MSI address throu= gh the - * IOMMU. msi_addr is the physical address of the MSI page. iommufd will - * allocate a fd global iova for the physical page that is the same on all - * domains and devices. - */ -int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr) -{ - phys_addr_t phys_addr =3D msi_addr & PAGE_MASK; - - return iommufd_sw_msi_list(domain, desc, &phys_addr, 1, PAGE_SIZE); -} EXPORT_SYMBOL_NS_GPL(iommufd_sw_msi, "IOMMUFD"); #endif =20 diff --git a/include/linux/iommu.h b/include/linux/iommu.h index ac43b8b93f14..bf08be172e40 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -1561,8 +1561,16 @@ static inline void pci_dev_reset_iommu_done(struct p= ci_dev *pdev) =20 #ifdef CONFIG_IRQ_MSI_IOMMU #ifdef CONFIG_IOMMU_API +int iommu_dma_prepare_msi_list(struct msi_desc *desc, const phys_addr_t *p= hys_addrs, + unsigned int nr_addrs, size_t granule); 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[86.49.245.11]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4887a34a4e9sm6689080f8f.11.2026.09.25.08.17.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 08:17:19 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v6 09/16] iommu/riscv: Reserve an MSI IOVA window for iommufd Date: Fri, 25 Sep 2026 17:16:52 +0200 Message-ID: <20260925151659.419512-10-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> References: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: Mlo0_pqLHIke6IWbATTA7SrMr4PjXE-Y X-Proofpoint-GUID: Mlo0_pqLHIke6IWbATTA7SrMr4PjXE-Y X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfX05CW9xDjjJZW lkKA/o4QAXBJjR0mkuLeAZGr3sdEGZgaGPiqHqbqggavMadTBe6aRh6uCzLf6sU1idii14FXzuM Jx8p4W2AEuPj0VAAYkYOH3gqGRLGExo= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfX6w12lJD3sSf1 xj/5sUWeUUUoYA0aOzHcqYulDxa4/6XiNYLr9mK0v7D+IzMdj6ItvnMftYM5wYzHOnhnuDOAm/r uEdrVH762WwTVDf3BVom6yW8wZ8och2lS0hjn12E1d2Cr54BWyAwyLj/QH83SiXa13o+CERIfRl xNDWUO4YZSDCyNoV24JZB+tltoS4JCAFORnuHRitapm2tgZhcH4lBWwZbqj5Pf6R/HVI2YdF/Fw 8VZgnuu/GeAxM7XVjgL79gMPNnXH6IiorFcqt2/5GcIHOOcBuZomrHrB7ZPX3XU1MPSWcahlkCD 0egUqPls0KFcRy0LCtt4naVF6yVSo6mnBhcPOcS7NfZ6xAiLbvoGCkx2ecc3imGPUHiO/Q0pf8I U/wj391BSs3NZpm8VVPDxPhNijuJ5HGqpAzekZVXCZr87HsPMOnWm1mqSqt0+DRmEbKwizHMrEz p8KSS6+pgq6CiNvJowg== X-Authority-Analysis: v=2.4 cv=eNmGH3p1 c=1 sm=1 tr=0 ts=6ab69081 cx=c_pps a=P2rfLEam3zuxRRdjJWA2cw==:117 a=4CXLxsOAgPM/krjtHEZQyA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=SRrdq9N9AAAA:8 a=hTxnoE90eIxTBplCLnYA:9 a=ODZdjJIeia2B_SHc_B0f:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-25_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 spamscore=0 bulkscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609250060 Content-Type: text/plain; charset="utf-8" iommufd requires an IOMMU_RESV_SW_MSI region to allocate stable IOVAs for MSI targets. Advertise such a region when the device uses an IMSIC MSI hierarchy so interrupt remapping can map IMSIC pages instead of falling back to physical addresses. Reserve one page per possible CPU, sufficient for each supervisor IMSIC page. Use a 16 MiB base instead of the 128 MiB convention used by ARM SMMU. kvmtool places its guest IMSIC at 128 MiB, so with IRQ bypass the domain-wide guest MSI address match can also capture host-delivered MSI writes to the SW MSI window and misdeliver them to the guest. 16 MiB falls in a hole in the current kvmtool and QEMU virt memory maps, away from their guest IMSIC windows and RAM. Keep the window below 4 GiB so devices with 32-bit MSI address registers can use it. This only avoids known conflicts. A VMM can place a guest's IMSIC at any valid address, including the chosen SW MSI range. As long as a fixed SW MSI window is required, changing its base cannot solve this in general or guarantee disjoint host and guest MSI address spaces. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/iommu/riscv/iommu.c | 20 ++++++++++++++++++++ drivers/iommu/riscv/iommu.h | 4 ++++ drivers/irqchip/irq-riscv-imsic-state.c | 22 ++++++++++++++++++++++ include/linux/irqchip/riscv-imsic.h | 6 ++++++ 4 files changed, 52 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index fbdca69c436e..dcad99131670 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -20,10 +20,12 @@ #include #include #include +#include #include #include #include =20 +#include "../dma-iommu.h" #include "../iommu-pages.h" #include "iommu-bits.h" #include "iommu.h" @@ -1514,6 +1516,23 @@ static void riscv_iommu_release_device(struct device= *dev) kfree_rcu_mightsleep(info); } =20 +static void riscv_iommu_get_resv_regions(struct device *dev, struct list_h= ead *head) +{ + struct iommu_resv_region *region; + + if (imsic_dev_has_imsic_msi_parent(dev)) { + /* Each hart has one S-mode IMSIC page, a.k.a MSI target page */ + region =3D iommu_alloc_resv_region(RISCV_IOMMU_MSI_IOVA_BASE, + (size_t)num_possible_cpus() * PAGE_SIZE, + IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO, + IOMMU_RESV_SW_MSI, GFP_KERNEL); + if (region) + list_add_tail(®ion->list, head); + } + + iommu_dma_get_resv_regions(dev, head); +} + static const struct iommu_ops riscv_iommu_ops =3D { .of_xlate =3D riscv_iommu_of_xlate, .capable =3D riscv_iommu_capable, @@ -1524,6 +1543,7 @@ static const struct iommu_ops riscv_iommu_ops =3D { .device_group =3D riscv_iommu_device_group, .probe_device =3D riscv_iommu_probe_device, .release_device =3D riscv_iommu_release_device, + .get_resv_regions =3D riscv_iommu_get_resv_regions, }; =20 static int riscv_iommu_init_check(struct riscv_iommu_device *iommu) diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index 5676001548cc..6d5c70e9ac6d 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -15,9 +15,13 @@ #include #include #include +#include =20 #include "iommu-bits.h" =20 +/* IOVA base for the SW MSI reservation */ +#define RISCV_IOMMU_MSI_IOVA_BASE SZ_16M + struct riscv_iommu_device; =20 struct riscv_iommu_queue { diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-= riscv-imsic-state.c index b8d1bbbf42f7..df38a7670a89 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -64,6 +64,28 @@ const struct imsic_global_config *imsic_get_global_confi= g(void) } EXPORT_SYMBOL_GPL(imsic_get_global_config); =20 +/** + * imsic_dev_has_imsic_msi_parent - Check for an IMSIC MSI parent + * @dev: Device to check + * + * Return: true if @dev's MSI domain or any parent domain is the IMSIC base + * domain. + */ +bool imsic_dev_has_imsic_msi_parent(struct device *dev) +{ + struct irq_domain *domain; + + if (!imsic || !imsic->base_domain) + return false; + + for (domain =3D dev_get_msi_domain(dev); domain; domain =3D domain->paren= t) + if (domain =3D=3D imsic->base_domain) + return true; + + return false; +} +EXPORT_SYMBOL_GPL(imsic_dev_has_imsic_msi_parent); + static bool __imsic_eix_read_clear(unsigned long id, bool pend) { unsigned long isel, imask; diff --git a/include/linux/irqchip/riscv-imsic.h b/include/linux/irqchip/ri= scv-imsic.h index 61af3a5bea09..662cb0442424 100644 --- a/include/linux/irqchip/riscv-imsic.h +++ b/include/linux/irqchip/riscv-imsic.h @@ -81,6 +81,7 @@ struct imsic_global_config { #ifdef CONFIG_RISCV_IMSIC =20 const struct imsic_global_config *imsic_get_global_config(void); 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[86.49.245.11]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4887a355826sm8069686f8f.18.2026.09.25.08.17.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 08:17:21 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v6 10/16] irqchip/riscv-imsic: Add MSI address list Date: Fri, 25 Sep 2026 17:16:53 +0200 Message-ID: <20260925151659.419512-11-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> References: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: SCBEzpyjO6sDyaFHHomdwsja5OAy6MVk X-Proofpoint-ORIG-GUID: SCBEzpyjO6sDyaFHHomdwsja5OAy6MVk X-Authority-Analysis: v=2.4 cv=aLBlOr9m c=1 sm=1 tr=0 ts=6ab69082 cx=c_pps a=5HAIKLe1ejAbszaTRHs9Ug==:117 a=4CXLxsOAgPM/krjtHEZQyA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=SRrdq9N9AAAA:8 a=iYRKoqeTzvuv0UILnrsA:9 a=gYDTvv6II1OnSo0itH1n:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfX5bayYtf+NSYE KbAK2l2lj3wYNf2KDjkqDxifVSln/hHpX2h86kCZ3QJ037CuPNfh5+zD+yQpHtefm0dvx8IzCdT Efn+2HIhFA3r57ZZyIyLUBUo20OK+p8= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfX01QpSlEGaICH uU/XaewzG4wHzwc6817OEz3W04Nk4lOTkukg+OJW3wUVG6TsCO9Q/DkhCJ3PLwmxbvlDjnxhNhI jMIAzhbTVpFF1VVqIaioTDIcsdJA0SYibNgbDh87CEW8RC0pz0kcHvQcex9j/KB+E21L68SyVLi pKdzWpiCgEZdAFSjkQMZTHVixMqiOrRlXh1wD4dZix4K/+c0IeRBjXe2cMwjpzS+FVQv1A5zSrW YNqneuOCYiefH9psQYm4JTQCFXdAll3xa+m+4vIlVy72RYjJQdHoVjY8wEscee992fkWMlnd1Ok WEJBKGMFhjPP37tNXnFR7vDq4dVHWPgR9xqiOcA9RNUsBL4pz40TLWf/qsJVDMg+QSiGwgOv4pg Cg103YRpeo6yemObVNzKB6t/OuqdY8koFP7MYBaNfglWPFIiwu5B9PzIj9XYkOjg89FSnhGUBL8 Pd7vzNNhi82k9nY+LDw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-25_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 phishscore=0 adultscore=0 impostorscore=0 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609250060 Content-Type: text/plain; charset="utf-8" Upcoming RISC-V IOMMU interrupt remapping needs to map every possible host IMSIC target into one contiguous MSI IOVA range. MSI message composition then uses the target CPU's position within that range. Build an IMSIC physical address array indexed by logical CPU. Require every possible CPU to have an initialized IMSIC page before publishing the array. This preserves physical address zero as a valid target and guarantees the array has num_possible_cpus() entries. The array size and each target's index can therefore be derived directly, without storing duplicate count or per-CPU index metadata. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/irqchip/irq-riscv-imsic-state.c | 32 +++++++++++++++++++++++++ drivers/irqchip/irq-riscv-imsic-state.h | 3 +++ 2 files changed, 35 insertions(+) diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-= riscv-imsic-state.c index df38a7670a89..abd1cdb640ea 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -709,6 +709,31 @@ static int __init imsic_get_mmio_resource(struct fwnod= e_handle *fwnode, return of_address_to_resource(to_of_node(fwnode), index, res); } =20 +static int __init imsic_init_msi_pa_list(void) +{ + struct imsic_global_config *global =3D &imsic->global; + phys_addr_t *msi_pa_list; + unsigned int cpu; + + msi_pa_list =3D kcalloc(num_possible_cpus(), sizeof(*msi_pa_list), GFP_KE= RNEL); + if (!msi_pa_list) + return -ENOMEM; + + for_each_possible_cpu(cpu) { + struct imsic_local_config *local =3D per_cpu_ptr(global->local, cpu); + + if (!local->msi_va) { + kfree(msi_pa_list); + return -ENODEV; + } + + msi_pa_list[cpu] =3D local->msi_pa; + } + + imsic->msi_pa_list =3D msi_pa_list; + return 0; +} + static int __init imsic_parse_fwnode(struct fwnode_handle *fwnode, struct imsic_global_config *global, u32 *nr_parent_irqs, @@ -959,6 +984,12 @@ int __init imsic_setup_state(struct fwnode_handle *fwn= ode, void *opaque) goto out_local_cleanup; } =20 + rc =3D imsic_init_msi_pa_list(); + if (rc) { + pr_err("%pfwP: failed to initialize MSI address list\n", fwnode); + goto out_local_cleanup; + } + /* Initialize matrix allocator */ rc =3D imsic_matrix_init(); if (rc) { @@ -984,6 +1015,7 @@ int __init imsic_setup_state(struct fwnode_handle *fwn= ode, void *opaque) out_free_local: free_percpu(imsic->global.local); out_free_priv: + kfree(imsic->msi_pa_list); kfree(imsic); imsic =3D NULL; return rc; diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-= riscv-imsic-state.h index c42ee180b305..e51c61dcced3 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.h +++ b/drivers/irqchip/irq-riscv-imsic-state.h @@ -50,6 +50,9 @@ struct imsic_priv { /* Global configuration common for all HARTs */ struct imsic_global_config global; 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[86.49.245.11]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49ff43ad975sm63738805e9.13.2026.09.25.08.17.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 08:17:22 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v6 11/16] irqchip/riscv-imsic: Support IOMMU MSI address lists Date: Fri, 25 Sep 2026 17:16:54 +0200 Message-ID: <20260925151659.419512-12-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> References: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfX+6ACe+GWxn8r zEzBq692ikdVUf81IUEc/cafwAi5KaVgstTKIwKe1fCwM6g5cbEAfuxVrDxf7NQeqrr+7GB9mG0 6dFXzW9mEXTopEp3SPpdmCq1VJMSZ+Q= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfXx5ojA9o9ioC4 1POwXAzdgf4vY2jHclSsoeDkEhgGGKsMZf1HmpUcbdskYIfu2kQmaGqINc1HXnTc4dEuws/UdOW +QsumLJUBuUoItnxevSVTAxvEkPoAYmXzPlADFzgq9D97ocl5tgJVHU9JoXUUT0zQwIz1gnUcy3 1YbhF+m/smW1oPpxIAGjTj9ibWxDBQ6OiXJrR+4MdsAUlX+VzDBXChlNlkAiq450ldOG16YjHdb xYxJGgs4vbh7CjcUkauM8Ist9iUrjzpi3vKrVvLgzJ0c8tVWus/hHg1ffXOVtuJ8JBIJwomDZwr Ax/QgUtWsQ+k7B+jEIGAddOvgCIdJ98ZspPpAmRUD7fL6iP6c2VACtNyTJMNpQJrnevWkl5YgbU bb4KughM3B2zrCgKrRgpZ1s1urC76PadPD12k5x8bG6/VXYrH83P1CwafNt/FNiuNDkp4irJd2b 2pNNU1ewY98y2uHQvOQ== X-Proofpoint-GUID: dWxG-54IiOaU23PnLIq0Bh6J-_3R4ue4 X-Proofpoint-ORIG-GUID: dWxG-54IiOaU23PnLIq0Bh6J-_3R4ue4 X-Authority-Analysis: v=2.4 cv=Hf2B3SE8 c=1 sm=1 tr=0 ts=6ab69085 cx=c_pps a=5HAIKLe1ejAbszaTRHs9Ug==:117 a=4CXLxsOAgPM/krjtHEZQyA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=SRrdq9N9AAAA:8 a=jAyyop91dzRkNHH0oPsA:9 a=0bXxn9q0MV6snEgNplNhOjQmxlI=:19 a=gYDTvv6II1OnSo0itH1n:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-25_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 malwarescore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609250060 Content-Type: text/plain; charset="utf-8" RISC-V IOMMU host interrupt remapping maps every possible host IMSIC target into one contiguous IOVA range. MSI message composition therefore needs each target's position within that range. Prepare the complete IMSIC address list while allocating an IRQ. The list is guaranteed to exist after IMSIC state initialization. The IOMMU backend maps the pages and caches the contiguous base IOVA in the MSI descriptor when translation is needed. When the descriptor has an IOMMU MSI mapping, use the selected logical CPU directly as the page index within the IOVA range. Use the same path for initial composition and affinity updates. A zero iommu_msi_shift means no MSI address translation is required, so keep physical messages. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-riscv-imsic-platform.c | 24 +++++++++++++++++++--- 2 files changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 20b77fbc51ee..a038e1121be3 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -651,6 +651,7 @@ config RISCV_IMSIC select IRQ_DOMAIN_HIERARCHY select GENERIC_IRQ_MATRIX_ALLOCATOR select GENERIC_MSI_IRQ + select IRQ_MSI_IOMMU select IRQ_MSI_LIB =20 config RISCV_RPMI_SYSMSI diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/i= rq-riscv-imsic-platform.c index 643c8e459611..ddb2bb570cdc 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -69,8 +70,10 @@ static void imsic_irq_ack(struct irq_data *d) irq_move_irq(d); } =20 -static void imsic_irq_compose_vector_msg(struct imsic_vector *vec, struct = msi_msg *msg) +static void imsic_irq_compose_vector_msg(struct irq_data *d, struct imsic_= vector *vec, + struct msi_msg *msg) { + struct msi_desc *desc =3D irq_data_get_msi_desc(d); phys_addr_t msi_addr; =20 if (WARN_ON(!vec)) @@ -79,6 +82,12 @@ static void imsic_irq_compose_vector_msg(struct imsic_ve= ctor *vec, struct msi_ms if (WARN_ON(!imsic_cpu_page_phys(vec->cpu, 0, &msi_addr))) return; =20 + /* A zero shift means no IOMMU MSI mapping is needed. */ + if (desc->iommu_msi_shift) { + msi_addr =3D (desc->iommu_msi_iova << desc->iommu_msi_shift) + + vec->cpu * IMSIC_MMIO_PAGE_SZ; + } + msg->address_hi =3D upper_32_bits(msi_addr); msg->address_lo =3D lower_32_bits(msi_addr); msg->data =3D vec->local_id; @@ -86,7 +95,7 @@ static void imsic_irq_compose_vector_msg(struct imsic_vec= tor *vec, struct msi_ms =20 static void imsic_irq_compose_msg(struct irq_data *d, struct msi_msg *msg) { - imsic_irq_compose_vector_msg(irq_data_get_irq_chip_data(d), msg); + imsic_irq_compose_vector_msg(d, irq_data_get_irq_chip_data(d), msg); } =20 #ifdef CONFIG_SMP @@ -94,7 +103,7 @@ static void imsic_msi_update_msg(struct irq_data *d, str= uct imsic_vector *vec) { struct msi_msg msg =3D { }; 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[86.49.245.11]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4887a648895sm7632913f8f.28.2026.09.25.08.17.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 08:17:24 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v6 12/16] iommu/dma: Enable IOMMU_DMA for 64-bit RISC-V Date: Fri, 25 Sep 2026 17:16:55 +0200 Message-ID: <20260925151659.419512-13-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> References: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: TXmWbtZLTDUCZYeErpb7-FwvJBJvktJF X-Proofpoint-ORIG-GUID: TXmWbtZLTDUCZYeErpb7-FwvJBJvktJF X-Authority-Analysis: v=2.4 cv=NJFAaE6g c=1 sm=1 tr=0 ts=6ab69086 cx=c_pps a=N1BjEkVkxJi3uNfLdpvX3g==:117 a=4CXLxsOAgPM/krjtHEZQyA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=h0uksLzaAAAA:8 a=EUspDBNiAAAA:8 a=SRrdq9N9AAAA:8 a=vvBRGx3AIC5YeKHJuXcA:9 a=crWF4MFLhNY0qMRaF8an:22 a=MSi_79tMYmZZG2gvAgS0:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfXyFVC+VAbIbrm 3mNh1+lCxEMAJ+3g1qmYwhXAY4GZEDqhXTjqNeEuAwfgvf7VDRT9zBz59tDa6a7Ft5wJcU7TKt5 UD1Iwg5ThgH7wPv0qnuEmvz/XB/d20E0eZFmMwRjkHiFzEJEAeSxwHXbYMYCQcmp+++U4aXOUIF H1kWcyw8CvV2RW/I4XVYXGeijYFkPWcSB8Fdlb+pKHO80c5N5EdLtQ0v4o+OxkB3VksEAtkBZ/B UnAVxJs8vWQF+UXzSu+ZcYJ/K2Ma0qURKp8EAbQlJPHdfIMggedsAZqBoNDUB89dV7wQa+ChAZd PqVl5lIVkI4Xk2utgRpzYrBBsIlm3bjD+16b1l+ca12V6xC4m2iTsLRwo34UFTLIjEl1rnXrMVM Pa11xwBjgxJ6MoUNYtl/EIxjmxX7P1BZadq3m94+wCz2KLm/GJ7nH2UZ61LFzV2oNIW2Uo13THJ 9UXCvvlJp6uJRgo1FLA== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfXzdaWxiRkyj6L VoUEiFFXW5nxHBzcFIz8Xj0fSQfpAtBuxccUJqIW0KuW6H6+CgzCNi2qsD3CDKFc+wY19F1k8FR QgIaWYpnvnUdLq4m8PlTTRNWiSljo88= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-25_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 spamscore=0 phishscore=0 suspectscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609250060 Content-Type: text/plain; charset="utf-8" From: Tomasz Jeznach Enable IOMMU_DMA for 64-bit RISC-V now that the RISC-V IOMMU driver supports MSI remapping. Signed-off-by: Tomasz Jeznach Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- drivers/iommu/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 27954f462582..2d38d5b5accd 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -151,7 +151,7 @@ config OF_IOMMU =20 # IOMMU-agnostic DMA-mapping layer config IOMMU_DMA - def_bool ARM64 || X86 || S390 + def_bool ARM64 || X86 || S390 || (RISCV && 64BIT) select DMA_OPS_HELPERS select IOMMU_API select IOMMU_IOVA --=20 2.43.0 From nobody Sat Sep 26 14:39:04 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24D5F4D09F9 for ; Fri, 25 Sep 2026 15:17:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; 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[86.49.245.11]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4887a3625ccsm8182262f8f.22.2026.09.25.08.17.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 08:17:26 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com, Nutty Liu Subject: [PATCH v6 13/16] vfio: enable IOMMU_TYPE1 for RISC-V Date: Fri, 25 Sep 2026 17:16:56 +0200 Message-ID: <20260925151659.419512-14-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> References: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfX7n7jZu/8l5CW Jxz6rGdZykKDbu+bNT1QUW/wsca2QGGk/T+XwC7Ai55WcY80Xtig5mkYGVeNAiB6e2uisvcroKE QzRnQTV9e9jmmzNRB8db3SN3ABlGBs4= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfX62IaJWlCbaZk ZptfgM9o7kj9Y1sHDEnzE4Hl6OOa3F2KT4Url/WhIijnKy9QC9tL/sXM5SWh5ontSsjJ/btCvFe Ta1gSobSW9Y8nVy+qrfqfaT/E4PUQaCiv+sKfDfHshvnaA3c5fbFlkVpNH5ZEzsICjIWuet3Hry 7JdJXr//syAiciSmsW3etTlKt6uuKJ1u4qmIrPWVZhmyY5VqM4gcOwfvqmlHIFJ/8/yZyOfvGgn eCz6xmhrsgTZ+646WnHgRXtEkmnncP9GkUBIGzrn1L8VpMZIUFnRL0XEM15VXAxDxtJXrhhCdwx CSVpwKgorVatTA0dDgUidPKsoHsTQYZNBeVU819kZ5p9lQRhxmIcLoEribv9TJG1D7NGB5Qrwdy 5KgRLvnHNRfkVV42TfOKopBby+DMHBsKeKw5986nVX6nELSr65CqzSBHWh+EU+JbOdUPnl33ca4 ZvpmlvCWgdUIJplldNw== X-Authority-Analysis: v=2.4 cv=VuO2kO2n c=1 sm=1 tr=0 ts=6ab69088 cx=c_pps a=P2rfLEam3zuxRRdjJWA2cw==:117 a=4CXLxsOAgPM/krjtHEZQyA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=h0uksLzaAAAA:8 a=EUspDBNiAAAA:8 a=69EAbJreAAAA:8 a=SRrdq9N9AAAA:8 a=UCRwF759qLZD2Be3sjoA:9 a=ODZdjJIeia2B_SHc_B0f:22 a=MSi_79tMYmZZG2gvAgS0:22 X-Proofpoint-GUID: PBBO-GOItBNlkixNIBjM2MWCaPXLqJ2F X-Proofpoint-ORIG-GUID: PBBO-GOItBNlkixNIBjM2MWCaPXLqJ2F X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-25_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 spamscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609250060 Content-Type: text/plain; charset="utf-8" From: Tomasz Jeznach Enable VFIO support on RISC-V architecture, now that the RISC-V IOMMU driver reports the IOMMU_CAP_CACHE_COHERENCY capability VFIO_TYPE1 and iommufd both require before allowing a device to be bound. Signed-off-by: Tomasz Jeznach Signed-off-by: Andrew Jones Reviewed-by: Nutty Liu Tested-by: Fangyu Yu --- drivers/vfio/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/vfio/Kconfig b/drivers/vfio/Kconfig index b9d6e1c22aed..f7f5b9c1950d 100644 --- a/drivers/vfio/Kconfig +++ b/drivers/vfio/Kconfig @@ -38,7 +38,7 @@ config VFIO_GROUP =20 config VFIO_CONTAINER bool "Support for the VFIO container /dev/vfio/vfio" - select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64) + select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64 || RISCV) depends on VFIO_GROUP default y help --=20 2.43.0 From nobody Sat Sep 26 14:39:04 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC7514C67F6 for ; Fri, 25 Sep 2026 15:17:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[86.49.245.11]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49fe5cd4271sm230756115e9.5.2026.09.25.08.17.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 08:17:27 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com, Nutty Liu Subject: [PATCH v6 14/16] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch Date: Fri, 25 Sep 2026 17:16:57 +0200 Message-ID: <20260925151659.419512-15-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> References: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=TptzFzXh c=1 sm=1 tr=0 ts=6ab69089 cx=c_pps a=ULNsgckmlI/WJG3HAyAuOQ==:117 a=4CXLxsOAgPM/krjtHEZQyA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=h0uksLzaAAAA:8 a=EUspDBNiAAAA:8 a=69EAbJreAAAA:8 a=SRrdq9N9AAAA:8 a=Hp3hLBw8nfLOXl02dSwA:9 a=1WsBpfsz9X-RYQiigVTh:22 a=MSi_79tMYmZZG2gvAgS0:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfXzBizDmU5+xLz Uv6lVOilrnpT+JRXABGj24XPeXLClybiQQh0x3wVUuMOIzH6m6yjprXGMCqWxOW8RcNeeEbesZS Zk91QBT161rrtw/7Lsw5y52bskLSVLyjxtW0TbS0fiRDwb0Cqxdpdj5NywP9h25XdFDXCw2PEzA 3V6MOpld5oToDfreGQHD3sOXoB2659gi3itao239mtVIr0ogCgoyULo+ifpJP7hDGdFvd2dZRQc 0itJ7q4MTFBOhaO1Hsh6TCTOFEF1mb+sACCUE7jVjbCulnrbPtNQey4FzOKsbkHTPLQl1j8BWPG zjo5JA+SbhlzJxuv0b8U9bU/fccJw06b7YQj+M/VaV62/KCkBVzgPduSfNRM0IaqP3/4w4TpB2S fJV3fVIxJ+7FIq/9ORu7O/IZbbOOuX8huPHc8qtRB3i9yIzLdkVTN7v4NyN/z/ZHAD72HlZRKoR Eu+r3g4+OEEgsqEMz+w== X-Proofpoint-ORIG-GUID: qcoDN0oTnN0wGz0G2TTvangZKrOWVeBg X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfX+RPzJBiX9Fep 4k53sksAkoL3DJMBa/WrfgCaWDZg7Z3OsPxwuJXS2f/zSvNops/IwlyYGAOOXkWiD0Wr2I2F8/k 0nY9D5jpxTy8B+0/jYvYFOYRYqAqx/I= X-Proofpoint-GUID: qcoDN0oTnN0wGz0G2TTvangZKrOWVeBg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-25_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609250060 Content-Type: text/plain; charset="utf-8" From: Tomasz Jeznach Enable KVM/VFIO support on RISC-V architecture, now that VFIO device assignment is available on RISC-V through VFIO_IOMMU_TYPE1, so a RISC-V KVM guest can be notified about VFIO-assigned devices. Signed-off-by: Tomasz Jeznach Signed-off-by: Andrew Jones Reviewed-by: Nutty Liu Tested-by: Fangyu Yu --- arch/riscv/kvm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/kvm/Kconfig b/arch/riscv/kvm/Kconfig index ec2cee0a39e0..49179aae9504 100644 --- a/arch/riscv/kvm/Kconfig +++ b/arch/riscv/kvm/Kconfig @@ -29,6 +29,7 @@ config KVM select KVM_GENERIC_DIRTYLOG_READ_PROTECT select KVM_GENERIC_HARDWARE_ENABLING select KVM_MMIO + select KVM_VFIO select VIRT_XFER_TO_GUEST_WORK select SCHED_INFO select GUEST_PERF_EVENTS if PERF_EVENTS --=20 2.43.0 From nobody Sat Sep 26 14:39:04 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FFE4175A88 for ; Fri, 25 Sep 2026 15:17:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; 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Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- arch/riscv/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 04ae305d5511..daf382c05441 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -251,6 +251,10 @@ CONFIG_DMADEVICES=3Dy CONFIG_DMA_SUN6I=3Dm CONFIG_DW_AXI_DMAC=3Dy CONFIG_MMP_PDMA=3Dm +CONFIG_IOMMUFD=3Dm +CONFIG_VFIO_DEVICE_CDEV=3Dy +CONFIG_VFIO=3Dm +CONFIG_VFIO_PCI=3Dm CONFIG_VIRTIO_PCI=3Dy CONFIG_VIRTIO_BALLOON=3Dy CONFIG_VIRTIO_INPUT=3Dy --=20 2.43.0 From nobody Sat Sep 26 14:39:04 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26C604C653F for ; Fri, 25 Sep 2026 15:17:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; 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[86.49.245.11]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4887a355c65sm7978559f8f.19.2026.09.25.08.17.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 08:17:31 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v6 16/16] selftests/vfio: Allow building on RISC-V Date: Fri, 25 Sep 2026 17:16:59 +0200 Message-ID: <20260925151659.419512-17-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> References: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfX7G4QDVARrpSw E4s6zQiIbBjmBaTmXCtYEPWCHFA89OFnryNfyRe1zwUVLdolbQAn8NSRkl3xkDLYPJu3/HCVuYg +SYrKH1TQ5ztjHfasAru7cE3DpQQ982TX9zH6pDIpYa4A1TP489aPhA05KE+RnNGntckWXtyrsX +1Lwb7QNp1ZA5uf5y+ULz5isuxHYi1PXlBt3BzQSoOaIrxBQTcQQC07oVb+NfThG1SuwQavzvBo nCyR0hsPdl5cIWopffKfSvxfSJyAG8fNLB7ooq/UdcJGX9KV709N6AUcEGaKCsLLG7fFCPEvmF3 UPKpSn+RD1UFEJFetWQ+7Iht4OyvCgtI/f1oKGsC/kC/TDwaB9k67YN3hGrnK4/G8ktjX0WcscA XoZSpcYR6ru9AqEjzi/IyY/UNRBWPMGCB/PQKP2LBrXJuv45VEobX7VYFbabjnouBVxFn9DXGV5 n/kNpsEMXhuFCadCc7A== X-Authority-Analysis: v=2.4 cv=ZfKIpcVA c=1 sm=1 tr=0 ts=6ab6908d cx=c_pps a=R6oCqFB+Yf/t2GF8e0/dFg==:117 a=4CXLxsOAgPM/krjtHEZQyA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=SRrdq9N9AAAA:8 a=2eipm_--ddBYp9jzNeMA:9 a=TD8TdBvy0hsOASGTdmB-:22 X-Proofpoint-ORIG-GUID: 0VBKDUoOWU7OG5TUUSCMhG2do7sFgZbW X-Proofpoint-GUID: 0VBKDUoOWU7OG5TUUSCMhG2do7sFgZbW X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI1MDA2MCBTYWx0ZWRfXy+odPrO+aMIO z2TIPJ1b3oGw1xtsV5Xr4VnRiTMdZLU/kJspQ8eO2Z6rBrJjf3p0os6cMUDJoixH0oY+SOynMoE Fw4mag5+47mMiV/285R3lCvHUxtmf6U= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-25_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 impostorscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 adultscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609250060 Content-Type: text/plain; charset="utf-8" The generic VFIO selftests, including iommufd coverage, require no RISC-V-specific source changes. Top-level kselftest builds normalize riscv64 to riscv, while direct builds may use riscv64. Include both names in the architecture filter. Signed-off-by: Andrew Jones Tested-by: Fangyu Yu --- tools/testing/selftests/vfio/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/vfio/Makefile b/tools/testing/selftest= s/vfio/Makefile index 2c32c48db509..2c7d8ea81b61 100644 --- a/tools/testing/selftests/vfio/Makefile +++ b/tools/testing/selftests/vfio/Makefile @@ -1,6 +1,6 @@ ARCH ?=3D $(shell uname -m) =20 -ifeq (,$(filter $(ARCH),aarch64 arm64 x86 x86_64)) +ifeq (,$(filter $(ARCH),aarch64 arm64 x86 x86_64 riscv riscv64)) # Do nothing on unsupported architectures include ../lib.mk else --=20 2.43.0