From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 70CDA4A842D; Thu, 24 Sep 2026 16:05:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265924; cv=none; b=DMf5ATdVdakEDOUTcI7uaR1yCiFjOshTAPLf/VGkRiUH2a4z5IbtnVACeRSeRuDUYFMc0xxB6jPh5TWDR5cuE/e8SCzbXtxWq6brIYBMJ5zDxFfA/Wnjgv/1CFK8y+tAkNgLcCTjCI/hC4IxiAateizLXFzIkLrtVsAO+YSeH7w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265924; c=relaxed/simple; bh=8etL8j5vGoOKfN2wQDB5I5lyGIQPbmxu1sDx9j9STUQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QM/hFid8EuhgksBbbAEG7XBSo7MajecVbtF32XPIhYajAvxWJZS87W5sTxNmPG6zhSui8P6IKRQSJptVAjSodSxlfHj6PI8yJvyxQZM5RJZmBmp22uWgXleAqdGxI0b+m9WHUMlGZ+eK5HoboW8MkuEZ6lwpzrVZzv4Xml1c7t0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=o4preBcx; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="o4preBcx" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3DD62152B; Thu, 24 Sep 2026 09:05:18 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6EB8C3FAB1; Thu, 24 Sep 2026 09:05:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790265921; bh=8etL8j5vGoOKfN2wQDB5I5lyGIQPbmxu1sDx9j9STUQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o4preBcxR9lS0OHgcfJISBe0NoClJ3siN3qA5yN+NMMoHWydiS/mSRI7utoDG7jaG cNyeuXlYLrRLreVOVnxPVqb6+/QUHPGit9UCIS2Ed+0guKmlGa7Ovzwt1cyn7ICJSZ QnnU11lLGX1ykgbNcJvM+dkrXICKy0gVqpFiIwec= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Suzuki K Poulose Subject: [PATCH v20 01/22] KVM: arm64: protected VM: Handle user writes to CNTVCT_EL0/CNTPCT_EL0 Date: Thu, 24 Sep 2026 17:04:43 +0100 Message-ID: <20260924160504.853911-2-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Protected VMs doesn't allow setting offsets for virtual and physical counters, as the offset is always fixed to 0. The VM ioctl is filtered out based on the cap. However we don't prevent the userspace from trying to write to the CNTVCT/CNTPCT registers. This would lead to KVM triggering a WARN() in timer_set_offset() as the vm_offset pointer is set to NULL. Fix this by always "fixing" the timer offsets to 0 and marking that the timer offset is set in the kvm->arch.flags at KVM init time for protected VMs. This prevents the access to the VM specific vm_offset at low cost. A userspace writing to the CNT*CT_EL0 would observe success, without any real effect. This is cleaner over spilling "*_is_protected()" checks and "matches" what we really do in practise. i.e., always run with "fixed counter offset of 0". Reported by Sashiko Link: https://lore.kernel.org/all/20260908164641.416911F00A3A@smtp.kernel.o= rg Fixes: f7d05ee84a6a ("KVM: arm64: Prevent host from managing timer offsets = for protected VMs") Suggested-by: Marc Zyngier Tested-by: Gavin Shan Signed-off-by: Suzuki K Poulose --- Changes since v19: - Fix typos in commit description and explain why we choose the approach. - Improve comment in the code Changes since v18: - Retain NULL vm_offset for protected VMs to avoid host tampering with the offset. - Moved the flag setting into kvm_timer_init_vm(), where it should have be= en in the first place --- arch/arm64/kvm/arch_timer.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c index 6ac3321f4c575..a45845f4ae4ea 100644 --- a/arch/arm64/kvm/arch_timer.c +++ b/arch/arm64/kvm/arch_timer.c @@ -1110,8 +1110,7 @@ void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu) timer_context_init(vcpu, i); =20 /* Synchronize offsets across timers of a VM if not already provided */ - if (!vcpu_is_protected(vcpu) && - !test_bit(KVM_ARCH_FLAG_VM_COUNTER_OFFSET, &vcpu->kvm->arch.flags)) { + if (!test_bit(KVM_ARCH_FLAG_VM_COUNTER_OFFSET, &vcpu->kvm->arch.flags)) { timer_set_offset(vcpu_vtimer(vcpu), kvm_phys_timer_read()); timer_set_offset(vcpu_ptimer(vcpu), 0); } @@ -1133,6 +1132,15 @@ void kvm_timer_init_vm(struct kvm *kvm) */ for (int i =3D 0; i < NR_KVM_TIMERS; i++) kvm->arch.timer_data.ppi[i] =3D get_vgic_ppi(kvm, default_ppi[i]); + + /* + * Protected VMs don't allow the userspace to set counter offsets, + * either set via counter register writes or the dedicated ioctls. + * Pretend the offset has already been set and rely on the default + * offset being 0. + */ + if (kvm_vm_is_protected(kvm)) + set_bit(KVM_ARCH_FLAG_VM_COUNTER_OFFSET, &kvm->arch.flags); } =20 void kvm_timer_cpu_up(void) --=20 2.43.0 From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2665A4AA56C; Thu, 24 Sep 2026 16:05:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265928; cv=none; b=rtzbu5py1ibhkERMUO4Vo2UE9dx1pZnk63aIIFmiWqiLfZgqhbb4ejtDmyerQElJBtPx93hS/sSi5YMcjGx5PpKh24sfnGHkRgG1fXwRYVYidAjGsa0Z8a4HinQdYQz0hjN/HV9TUGyKySJ+3B3t7sZgPkPEKs/ipi/GByrHoDM= ARC-Message-Signature: i=1; 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Thu, 24 Sep 2026 09:05:22 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 16D8A3F86C; Thu, 24 Sep 2026 09:05:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790265926; bh=tQPgXa0jI7YAYMnIJ4TZ6BAVtiDhJcnzdYxdyAnW4NQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Fn8Yg7CasPv/kTLDY/bNSD3XpW/FBGNHfP16E8DGXiuSrl9OiLby0HvB6bGNTVsfA se6sn3iyMXeG2aI6yuMo45FnoIAb5iHHbpQdWINkLn7IgiPrqe5VCVziJsI5MWQ9g3 PKEklxiVCMI/AtAwd6wzdZCuSt+qdtE+zCBNouoQ= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Suzuki K Poulose , Fuad Tabba Subject: [PATCH v20 02/22] KVM: arm64: Disable Steal time accounting for protected guests Date: Thu, 24 Sep 2026 17:04:44 +0100 Message-ID: <20260924160504.853911-3-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" PVTIME support is advertised by KVM_CAP_STEAL_TIME, which doesn't take into account the kvm instance. Even with that, a VMM could skip the CAP check and proceed to configure the PVTIME as we don't do further check on the DEVICE_CTRL. Tighten this up by passing the KVM instance around wherever possible and catch things early. Reviewed-by: Fuad Tabba Tested-by: Gavin Shan Signed-off-by: Suzuki K Poulose --- arch/arm64/include/asm/kvm_host.h | 2 +- arch/arm64/kvm/arm.c | 2 +- arch/arm64/kvm/pvtime.c | 14 +++++++------- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 27fe0cd5b2d7a..286489a69dff5 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -1346,7 +1346,7 @@ long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); void kvm_update_stolen_time(struct kvm_vcpu *vcpu); =20 -bool kvm_arm_pvtime_supported(void); +bool kvm_arm_pvtime_supported(struct kvm *kvm); int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr); int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 8b080804bc90b..db36815630790 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -447,7 +447,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long = ext) r =3D system_supports_mte(); break; case KVM_CAP_STEAL_TIME: - r =3D kvm_arm_pvtime_supported(); + r =3D kvm_arm_pvtime_supported(kvm); break; case KVM_CAP_ARM_EL1_32BIT: r =3D cpus_have_final_cap(ARM64_HAS_32BIT_EL1); diff --git a/arch/arm64/kvm/pvtime.c b/arch/arm64/kvm/pvtime.c index 4ceabaa4c30bd..579e0a4720ad2 100644 --- a/arch/arm64/kvm/pvtime.c +++ b/arch/arm64/kvm/pvtime.c @@ -67,9 +67,9 @@ gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu) return base; } =20 -bool kvm_arm_pvtime_supported(void) +bool kvm_arm_pvtime_supported(struct kvm *kvm) { - return !!sched_info_on(); + return !!sched_info_on() && (!kvm || !kvm_vm_is_protected(kvm)); } =20 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, @@ -81,8 +81,8 @@ int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, int ret =3D 0; int idx; =20 - if (!kvm_arm_pvtime_supported() || - attr->attr !=3D KVM_ARM_VCPU_PVTIME_IPA) + if (!kvm_arm_pvtime_supported(kvm) || + (attr->attr !=3D KVM_ARM_VCPU_PVTIME_IPA)) return -ENXIO; =20 if (get_user(ipa, user)) @@ -110,8 +110,8 @@ int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, u64 __user *user =3D (u64 __user *)attr->addr; u64 ipa; =20 - if (!kvm_arm_pvtime_supported() || - attr->attr !=3D KVM_ARM_VCPU_PVTIME_IPA) + if (!kvm_arm_pvtime_supported(vcpu->kvm) || + (attr->attr !=3D KVM_ARM_VCPU_PVTIME_IPA)) return -ENXIO; =20 ipa =3D vcpu->arch.steal.base; @@ -126,7 +126,7 @@ int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, { switch (attr->attr) { case KVM_ARM_VCPU_PVTIME_IPA: - if (kvm_arm_pvtime_supported()) + if (kvm_arm_pvtime_supported(vcpu->kvm)) return 0; } return -ENXIO; --=20 2.43.0 From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 02BDA4AA56C; Thu, 24 Sep 2026 16:05:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265933; cv=none; b=FEFcP1msOzwYrekrkHtqWTYWz1OF12SsUOMGI2p4+FaEIQ2rawGN09FpAknJVEFG0wKeVeZUILfx6bMbdQnJe/bILLx+IJCGnuc0XIJjvHTy0hlQpdgFb6mnuTdJktl/BkS4EhNRvU3e64ZD3bA28gWIKrTb1jimQjzEAenl1xU= ARC-Message-Signature: i=1; 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Thu, 24 Sep 2026 09:05:27 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BE5393F86C; Thu, 24 Sep 2026 09:05:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790265931; bh=e4q/PWyF7pIt1CQ8fjppct+/tCsvdAGsy+TtiAPcvi8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Lt5pqYvVdtJL2rfpa/saSCOFRu/i/inIISap9zx1Ca/uq0WlmTBtAlx8/yTBkMZRY xseI4NYfObsbMspeYG/gAJOwIZmn/yn4up99m604CS0vg2ufDdKOm2W69qgt11fMPA VACjJtyUk97jIpTki3hBr0Rty0ICu83QtURnRy9Q= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Suzuki K Poulose , Fuad Tabba Subject: [PATCH v20 03/22] KVM: arm64: Include kvm_emulate.h in kvm/arm_psci.h Date: Thu, 24 Sep 2026 17:04:45 +0100 Message-ID: <20260924160504.853911-4-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Fix a potential build error (like below, when asm/kvm_emulate.h gets included after the kvm/arm_psci.h) by including the missing header file in kvm/arm_psci.h: ./include/kvm/arm_psci.h: In function =E2=80=98kvm_psci_version=E2=80=99: ./include/kvm/arm_psci.h:29:13: error: implicit declaration of function =E2=80=98vcpu_has_feature=E2=80=99; did you mean =E2=80=98cpu_have_featu= re=E2=80=99? [-Werror=3Dimplicit-function-declaration] 29 | if (vcpu_has_feature(vcpu, KVM_ARM_VCPU_PSCI_0_2)) { | ^~~~~~~~~~~~~~~~ | cpu_have_feature Reviewed-by: Gavin Shan Reviewed-by: Fuad Tabba Reviewed-by: Jonathan Cameron Tested-by: Gavin Shan Signed-off-by: Suzuki K Poulose --- include/kvm/arm_psci.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/kvm/arm_psci.h b/include/kvm/arm_psci.h index f86a006d67136..06c20612e9e7d 100644 --- a/include/kvm/arm_psci.h +++ b/include/kvm/arm_psci.h @@ -10,6 +10,8 @@ #include #include =20 +#include + #define KVM_ARM_PSCI_0_1 PSCI_VERSION(0, 1) #define KVM_ARM_PSCI_0_2 PSCI_VERSION(0, 2) #define KVM_ARM_PSCI_1_0 PSCI_VERSION(1, 0) --=20 2.43.0 From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E6DD154788; Thu, 24 Sep 2026 16:05:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265939; cv=none; b=hEop/fv0p9kCcUYDXoTVeJUkFgYFqdvk2L+1uPTYYvoOww06fPF2t2w2M33Ep41Dwxw4vKHAHVy0I/+RO86HLpPWIt5rgOFnW7rgDpQdlk2o6+O7uJwg6TZFST75l7O7XGW6Osvz81qHzqdaAUvTc5ukxVd40U7/Gw1TCXHXWug= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265939; c=relaxed/simple; bh=vhmzYOeEMeS1gUmiyRsM5hDk21KN/XfVddfQo5gUwVs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=to4PP11A2mxtWcehvlVjh9w/OdtaHtFj7S/dQ7JLkSj12L0/Dxq1HBo8t2lTdXDPkw5tF95qhHGIFtNaWySMX9UA8/S14v2hk/tiqLi6VtHtzMQ4+fNbOgjZUQW0QoVSXAYuZCys9Z5oEKgCM9UwSXibkQQtJUhGtrMamQbmJfI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=IfVjZlGF; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="IfVjZlGF" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 96A5A152B; Thu, 24 Sep 2026 09:05:32 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9A4283F86C; Thu, 24 Sep 2026 09:05:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790265936; bh=vhmzYOeEMeS1gUmiyRsM5hDk21KN/XfVddfQo5gUwVs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IfVjZlGFBFOo82R0dy/xaHAJ4Chh0qKIT4MXPi0AxpjOEm8iOEjQ/OEZYDpjfhQ0X exElgaxlLeOdxP54t9qkAyR3+clfAHFUeVzzYgr2AIp6eIhBgIgv5Adp/YpD/iemMe tF6mtCDuBUt5pkR50SnjJ+IkUQoGNgHVYaEjewrg= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Fuad Tabba , Suzuki K Poulose Subject: [PATCH v20 04/22] KVM: arm64: Avoid including linux/kvm_host.h in kvm_pgtable.h Date: Thu, 24 Sep 2026 17:04:46 +0100 Message-ID: <20260924160504.853911-5-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Steven Price To avoid future include cycles, drop the linux/kvm_host.h include in kvm_pgtable.h and include the lightweight headers required for the types and inline helpers used there. Additionally provide a forward declaration for struct kvm_s2_mmu as it's only used as a pointer in this file. Both pgtable.c and kvm_pkvm.h relied on the indirect inclusion of kvm_host.h, so make that explicit. Reviewed-by: Fuad Tabba Reviewed-by: Gavin Shan Signed-off-by: Steven Price Signed-off-by: Suzuki K Poulose --- Changes since v19: - Include asm/memory.h, asm/page.h , linux/bitfield.h in asm/kvm_pgtable.h= - Sashiko --- arch/arm64/include/asm/kvm_pgtable.h | 10 +++++++++- arch/arm64/include/asm/kvm_pkvm.h | 2 +- arch/arm64/kvm/hyp/pgtable.c | 1 + 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/= kvm_pgtable.h index 41a8687938eb6..a211a5d87bf96 100644 --- a/arch/arm64/include/asm/kvm_pgtable.h +++ b/arch/arm64/include/asm/kvm_pgtable.h @@ -7,10 +7,18 @@ #ifndef __ARM64_KVM_PGTABLE_H__ #define __ARM64_KVM_PGTABLE_H__ =20 +#include #include -#include +#include +#include +#include #include =20 +#include +#include + +struct kvm_s2_mmu; + #define KVM_PGTABLE_FIRST_LEVEL -1 #define KVM_PGTABLE_LAST_LEVEL 3 =20 diff --git a/arch/arm64/include/asm/kvm_pkvm.h b/arch/arm64/include/asm/kvm= _pkvm.h index beea00e693a0a..54a618d887fa4 100644 --- a/arch/arm64/include/asm/kvm_pkvm.h +++ b/arch/arm64/include/asm/kvm_pkvm.h @@ -7,9 +7,9 @@ #define __ARM64_KVM_PKVM_H__ =20 #include +#include #include #include -#include #include =20 /* Maximum number of VMs that can co-exist under pKVM. */ diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c index b74dd5ce1efd3..f48253b9d88b5 100644 --- a/arch/arm64/kvm/hyp/pgtable.c +++ b/arch/arm64/kvm/hyp/pgtable.c @@ -8,6 +8,7 @@ */ =20 #include +#include #include #include =20 --=20 2.43.0 From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 274D04ACC8A; Thu, 24 Sep 2026 16:05:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265943; cv=none; b=cPmznA0nWcuwgtRQBuTjJeTHJZzwsSEIjDFTx/zxu4z5cXYM42coMCSuIWGiqamEH6MbNJoerA3KzKualXiLJkXykESQV0yCmud0eCB+W7QHg475N2ybKbFgcsgWH5XCSZgTvIm//NwD9HetmLA1W2yZ8lOtdNoF0G0CEJwouP0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265943; c=relaxed/simple; bh=T9eIctwVtxFtu2naBbqkNNQZ5lLsvNie+O2i9aydJAc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fE6U4FC8viSuIWU+ZPj43avz2Srewv35i9N97CraF8R6hcAZ8oVIyLIIoODfOV0z74aVN/uVEhGTpmQ36kYEx2wWlHgcucgTbsjTUy50B0XXyaec10vZ0cirx28ZAVKJY9G+ZjSftBkQ7cuhsveRmUcS3iCeBjMWeFmsBxUnmB8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=hhbXYKX8; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="hhbXYKX8" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 29D1A152B; Thu, 24 Sep 2026 09:05:37 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6F1C13F86C; Thu, 24 Sep 2026 09:05:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790265940; bh=T9eIctwVtxFtu2naBbqkNNQZ5lLsvNie+O2i9aydJAc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hhbXYKX8qL9fxDGDDc54qs82TTNxw9xjxbN4cRRxhstUZVA5KuzmtSSfZ1cnJmdcE TsjoWsUOXnOk7TPwduuDmYY3NgyTxhNtkEkuUVN9l4EkF4XuLTeS+AiUr7Zp2ZKcPz NuSoxlDDAXfSiWjlims8oegIr54gmigBsuC3b4MY= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Suzuki K Poulose Subject: [PATCH v20 05/22] KVM: arm64: Track the type of VM in kvm_arch Date: Thu, 24 Sep 2026 17:04:47 +0100 Message-ID: <20260924160504.853911-6-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" KVM arm64 has different types of VMs with all the different modes in which the hypervisor code can be run. e.g., VHE, nVHE, pKVM etc. Then there is protected VM and normal VMs with pKVM. We might soon add other types, e.g., Arm CCA Realm. So in an effort to make the handling of these different types of VMs a bit more friendly to the eyes, add a VM flavor to the kvm_arch and we could then add handlers for different operations based on the VM type. Keep the flavor initialisation at the beginning to allow for the detection early enough and fail out on any unsupported requests. With that, add wrappers for checking the "type" of a VM and replace the existing users with the new wrappers. Given we already have the construct of "kvm_vm_is_protected" in the core KVM code, use that for all confidential compute guests including Realms that we are about to add. Adds __VM_PROTECTED marker vm flavor to draw the boundary for "protected VMs". In later patches, we would add Realm VMs, which would also be classified as protected. Add a explicit helper to detect if a given VM is a "protected" VM under pKV= M. Change the existing users that precisely want to check the VM type. These include : - kvm_arch_prepare_memory_region - For preventing memslot changes after pVM creation. All the others are retained as a wider check for confidential guest VMs. These are: - kvm_vm_ioctl_set_counter_offset - For disallowing timer offset configuration - io_mem_abort for dabt handling without valid syndrome information Both of which are true for Realms too. Realms support is restricted to VHE host and thus "kvm_vm_is_protected()" checks in the pkvm hyp specific code doesn't need to change, as the only protected guests it deals with is "protected pKVM" guests. To tighten this init_pkvm_hyp_vm() restricts the hyp copy of the vm_flavor to the ones it supports. vcpu_is_protected() usage from nVHE hyp code is tricky, as we need to convert the vcpu->kvm to the HYP VA before checking the flavor. This involves kern_hyp_va() usage in asm/kvm_host.h. To avoid build breaks, include asm/kvm_mmu.h to arm64/kvm/mmio.c. Suggested-by: Marc Zyngier Tested-by: Gavin Shan Signed-off-by: Suzuki K Poulose --- Changes since v19: - Fix vcpu_is_protected for nvhe hyp by using the kern_hyp_va() for vcpu->kvm - Gavin - Use READ_ONCE() to read the vm_flavor in EL2 pKVM code - Drop ',' after the end marker in vm_flavor enums - Replace !kvm_vm_is_protected() in kvm_arch_vcpu_put() with kvm_vm_is_unprotected_pkvm() Changes since v18: - Merge the __VM_PROTECTED marker and the widening of kvm_vm_is_protected() to this patch. - Merge the use of kvm_vm_is_unprotected_pkvm() for !kvm_vm_is_protected() given the scope changes here. - Drop Fuad's review tag, as this patch has multiple merges - Restrict the VM flavors to the supported types in init_pkvm_hyp_vm(). - Drop kvm_vm_hyp_is_pkvm() and revert to is_protected_kvm_enabled() - Use is_protected_kvm_enabled() to make the pKVM guest flavor checks. - s/PKVM/pKVM for commit descriptions too Changes since v17: * s/PKVM/pKVM for the comments * Drop type argument for pkvm_init_host_vm and also drop protected variabl= e. * Add helpers for checking if the VM is running on pKVM (kvm_vm_hyp_is_pkv= m()) * Use kvm_vm_hyp_is_pkvm() to replace is_protected_kvm_enabled() with valid kvm instance --- arch/arm64/include/asm/kvm_host.h | 51 +++++++++++++++++++++++++++++-- arch/arm64/include/asm/kvm_pkvm.h | 4 +-- arch/arm64/kvm/arm.c | 33 ++++++++++++++++---- arch/arm64/kvm/handle_exit.c | 2 +- arch/arm64/kvm/hyp/nvhe/pkvm.c | 6 +++- arch/arm64/kvm/mmio.c | 1 + arch/arm64/kvm/mmu.c | 2 +- arch/arm64/kvm/pkvm.c | 6 ++-- 8 files changed, 87 insertions(+), 18 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 286489a69dff5..63bd1f76edb7b 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -257,7 +257,6 @@ struct kvm_protected_vm { pkvm_handle_t handle; struct kvm_hyp_memcache teardown_mc; struct kvm_hyp_memcache stage2_teardown_mc; - bool is_protected; bool is_created; =20 /* @@ -306,9 +305,19 @@ enum fgt_group_id { __NR_FGT_GROUP_IDS__ }; =20 +enum kvm_arm_vm_flavor { + VM_NVHE, + VM_VHE, + VM_PKVM, /* Normal guests on pKVM */ + MARKER(__VM_PROTECTED), + VM_PROTECTED_PKVM, /* Protected VM */ + VM_FLAVOR_MAX +}; + struct kvm_arch { struct kvm_s2_mmu mmu; =20 + enum kvm_arm_vm_flavor vm_flavor; /* * Fine-Grained UNDEF, mimicking the FGT layout defined by the * architecture. We track them globally, as we present the @@ -1504,9 +1513,45 @@ struct kvm *kvm_arch_alloc_vm(void); =20 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE =20 -#define kvm_vm_is_protected(kvm) (is_protected_kvm_enabled() && (kvm)->arc= h.pkvm.is_protected) +#define kvm_vm_is_protected(kvm) ((kvm)->arch.vm_flavor >=3D __VM_PROTECTE= D) +/* + * Accessing vcpu->kvm from nVHE hyp stub is tricky, as we need to convert= the + * pointer to the hyp VA. With pKVM, the nVHE code runs with the hyp_vcpu, + * which is populated correctly. + */ +#define vcpu_is_protected(vcpu) \ + ({ \ + struct kvm *__kvm =3D READ_ONCE((vcpu)->kvm); \ + bool __protected =3D false; \ + \ + if (__kvm) { \ + if (is_nvhe_hyp_code() && \ + !is_protected_kvm_enabled()) \ + __kvm =3D kern_hyp_va(__kvm); \ + \ + __protected =3D kvm_vm_is_protected(__kvm); \ + } \ + __protected; \ + }) + +#define kvm_vm_is_protected_pkvm(kvm) \ + (is_protected_kvm_enabled() && ((kvm)->arch.vm_flavor =3D=3D VM_PROTECTED= _PKVM)) + +/* + * Rely on is_protected_kvm_enabled() check in kvm_vm_is_protected_pkvm() = to + * make sure the vcpu->kvm is always valid VA in the context + */ +#define vcpu_is_protected_pkvm(vcpu) \ + ({ \ + struct kvm *__kvm =3D READ_ONCE((vcpu)->kvm); \ + \ + (__kvm && kvm_vm_is_protected_pkvm(__kvm)); \ + }) + + +#define kvm_vm_is_unprotected_pkvm(kvm) \ + (is_protected_kvm_enabled() && ((kvm)->arch.vm_flavor =3D=3D VM_PKVM)) =20 -#define vcpu_is_protected(vcpu) kvm_vm_is_protected((vcpu)->kvm) =20 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/include/asm/kvm_pkvm.h b/arch/arm64/include/asm/kvm= _pkvm.h index 54a618d887fa4..e4ea80711bec6 100644 --- a/arch/arm64/include/asm/kvm_pkvm.h +++ b/arch/arm64/include/asm/kvm_pkvm.h @@ -17,7 +17,7 @@ =20 #define HYP_MEMBLOCK_REGIONS 128 =20 -int pkvm_init_host_vm(struct kvm *kvm, unsigned long type); +int pkvm_init_host_vm(struct kvm *kvm); int pkvm_create_hyp_vm(struct kvm *kvm); bool pkvm_hyp_vm_is_created(struct kvm *kvm); void pkvm_destroy_hyp_vm(struct kvm *kvm); @@ -49,7 +49,7 @@ static inline bool kvm_pkvm_ext_allowed(struct kvm *kvm, = long ext) case KVM_CAP_ARM_SUPPORTED_BLOCK_SIZES: return false; default: - return !kvm || !kvm_vm_is_protected(kvm); + return !kvm || kvm_vm_is_unprotected_pkvm(kvm); } } =20 diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index db36815630790..90547fbbc8ad7 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -214,6 +214,26 @@ static int kvm_arm_default_max_vcpus(void) return vgic_present ? kvm_vgic_get_max_vcpus() : KVM_MAX_VCPUS; } =20 +static int kvm_init_vm_flavor(struct kvm *kvm, unsigned long type) +{ + bool protected =3D type & KVM_VM_TYPE_ARM_PROTECTED; + + if (is_protected_kvm_enabled()) { + if (protected) + kvm->arch.vm_flavor =3D VM_PROTECTED_PKVM; + else + kvm->arch.vm_flavor =3D VM_PKVM; + } else if (protected) { + return -EINVAL; + } else if (has_vhe()) { + kvm->arch.vm_flavor =3D VM_VHE; + } else { + kvm->arch.vm_flavor =3D VM_NVHE; + } + + return 0; +} + /** * kvm_arch_init_vm - initializes a VM data structure * @kvm: pointer to the KVM struct @@ -236,6 +256,10 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long ty= pe) mutex_unlock(&kvm->lock); #endif =20 + ret =3D kvm_init_vm_flavor(kvm, type); + if (ret) + return ret; + kvm_init_nested(kvm); =20 ret =3D kvm_share_hyp(kvm, kvm + 1); @@ -257,12 +281,9 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long ty= pe) * If any failures occur after this is successful, make sure to * call __pkvm_unreserve_vm to unreserve the VM in hyp. */ - ret =3D pkvm_init_host_vm(kvm, type); + ret =3D pkvm_init_host_vm(kvm); if (ret) goto err_uninit_mmu; - } else if (type & KVM_VM_TYPE_ARM_PROTECTED) { - ret =3D -EINVAL; - goto err_uninit_mmu; } =20 kvm_vgic_early_init(kvm); @@ -751,7 +772,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) kvm_call_hyp_nvhe(__pkvm_vcpu_put); =20 /* __pkvm_vcpu_put implies a sync of the state */ - if (!kvm_vm_is_protected(vcpu->kvm)) + if (kvm_vm_is_unprotected_pkvm(vcpu->kvm)) vcpu_set_flag(vcpu, PKVM_HOST_STATE_DIRTY); } =20 @@ -985,7 +1006,7 @@ int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) =20 if (is_protected_kvm_enabled()) { /* Start with the vcpu in a dirty state */ - if (!kvm_vm_is_protected(vcpu->kvm)) + if (kvm_vm_is_unprotected_pkvm(vcpu->kvm)) vcpu_set_flag(vcpu, PKVM_HOST_STATE_DIRTY); ret =3D pkvm_create_hyp_vm(kvm); if (ret) diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index db37678dcb05c..384c5d258c7f8 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -490,7 +490,7 @@ static void handle_exit_pkvm_state(struct kvm_vcpu *vcp= u, int exception_index) { int exception_code =3D ARM_EXCEPTION_CODE(exception_index); =20 - if (!is_protected_kvm_enabled() || kvm_vm_is_protected(vcpu->kvm)) + if (!kvm_vm_is_unprotected_pkvm(vcpu->kvm)) return; =20 /* diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c index 459bd9eb7e4bc..ed51762aa4b5d 100644 --- a/arch/arm64/kvm/hyp/nvhe/pkvm.c +++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c @@ -432,7 +432,11 @@ static void init_pkvm_hyp_vm(struct kvm *host_kvm, str= uct pkvm_hyp_vm *hyp_vm, =20 hyp_vm->host_kvm =3D host_kvm; hyp_vm->kvm.created_vcpus =3D nr_vcpus; - hyp_vm->kvm.arch.pkvm.is_protected =3D READ_ONCE(host_kvm->arch.pkvm.is_p= rotected); + if (READ_ONCE(host_kvm->arch.vm_flavor) =3D=3D VM_PROTECTED_PKVM) + hyp_vm->kvm.arch.vm_flavor =3D VM_PROTECTED_PKVM; + else + hyp_vm->kvm.arch.vm_flavor =3D VM_PKVM; + hyp_vm->kvm.arch.flags =3D 0; pkvm_init_features_from_host(hyp_vm, host_kvm); =20 diff --git a/arch/arm64/kvm/mmio.c b/arch/arm64/kvm/mmio.c index d1c3a352d5a22..ab1d2fef9a522 100644 --- a/arch/arm64/kvm/mmio.c +++ b/arch/arm64/kvm/mmio.c @@ -6,6 +6,7 @@ =20 #include #include +#include #include =20 #include "trace.h" diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 9ba86450fe4af..0f4e8b71fa85d 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -2624,7 +2624,7 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm, hva_t hva, reg_end; int ret =3D 0; =20 - if (kvm_vm_is_protected(kvm)) { + if (kvm_vm_is_protected_pkvm(kvm)) { /* Cannot modify memslots once a pVM has run. */ if (pkvm_hyp_vm_is_created(kvm) && (change =3D=3D KVM_MR_DELETE || change =3D=3D KVM_MR_MOVE)) { diff --git a/arch/arm64/kvm/pkvm.c b/arch/arm64/kvm/pkvm.c index 8e4c6e4bec123..8e9176a700926 100644 --- a/arch/arm64/kvm/pkvm.c +++ b/arch/arm64/kvm/pkvm.c @@ -229,10 +229,9 @@ void pkvm_destroy_hyp_vm(struct kvm *kvm) mutex_unlock(&kvm->arch.config_lock); } =20 -int pkvm_init_host_vm(struct kvm *kvm, unsigned long type) +int pkvm_init_host_vm(struct kvm *kvm) { int ret; - bool protected =3D type & KVM_VM_TYPE_ARM_PROTECTED; =20 /* Reserve the VM in hyp and obtain a hyp handle for the VM. */ ret =3D kvm_call_hyp_nvhe(__pkvm_reserve_vm); @@ -240,8 +239,7 @@ int pkvm_init_host_vm(struct kvm *kvm, unsigned long ty= pe) return ret; =20 kvm->arch.pkvm.handle =3D ret; - kvm->arch.pkvm.is_protected =3D protected; - if (protected) { + if (kvm_vm_is_protected(kvm)) { pr_warn_once("kvm: protected VMs are experimental and for development on= ly, tainting kernel\n"); add_taint(TAINT_USER, LOCKDEP_STILL_OK); } --=20 2.43.0 From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5C86A4AD4AF; Thu, 24 Sep 2026 16:05:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265947; cv=none; b=c1Wzu9CJhCT/qJ7FvsupbePhofzd4VQBk5zjmk8cfHmEg8qCNeK8nYEMvT1ODg1nF25BwsTPOsLUCi0cX7Rdw5nEcNEYT9Wehy6hTOoUKmSCUWGu+Q2EXl0fOGPVqeAqbgmYPE/0PJ/Z0BmfgLjiAWSjFE5MtJ0qgo7+ZlmUW0Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265947; c=relaxed/simple; bh=j2b9WHiFALCo+wdRBdRdHxhVuEWadLpkN31xoR3hUMw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rPmw9+/u+CoIcXtF21iCAOBs0nQtFjWhMD4PGn7ZuOuMps022OsCp32tpIX8aGYxOBCwJ69gWjIvUZor7T0uInyiBO3ovvkuWdW+jAMyQ4s7wq3+ezTSPVrbUFoF2SR/1do/VpBaqG3T0KozEDBJZUWhnTdKznSI+l/jrEgV7co= ARC-Authentication-Results: i=1; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HL9LtMoQMp94k6RH6fPphaQ/7RlO8EOtXODTN1jdSMe3v+83ipfwYow2QynPV54An +/1Gc/sR1ZF2vo9yHbuAbuyS5IdhTIPGLKyVf9C2zO3fTN27qlhkoqde+W6WEAeQmz Rg6QQpiQiaq6PXU5U0J/2vH7h0FYwyZ/2l6KxpGs= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Suzuki K Poulose Subject: [PATCH v20 06/22] KVM: arm64: Don't call vcpu_set_pauth_traps for pKVM host Date: Thu, 24 Sep 2026 17:04:48 +0100 Message-ID: <20260924160504.853911-7-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" vcpu_set_pauth_traps() bails out and does nothing for pKVM hosts. Clean this up by moving the is_protected_kvm_enabled() check to the caller, in preparation for adding VM specific vcpu load/put callbacks. While at it, do an early return if the vcpu doesn't have ptrauth. No functional changes Signed-off-by: Suzuki K Poulose --- Changes since v19: - New patch, since addition of this to the Refactoring patch makes it a bit more bigger and harder to follow --- arch/arm64/kvm/arm.c | 52 +++++++++++++++++++++++--------------------- 1 file changed, 27 insertions(+), 25 deletions(-) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 90547fbbc8ad7..849f5fcc26c15 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -631,33 +631,34 @@ void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) =20 static void vcpu_set_pauth_traps(struct kvm_vcpu *vcpu) { - if (vcpu_has_ptrauth(vcpu) && !is_protected_kvm_enabled()) { - /* - * Either we're running an L2 guest, and the API/APK bits come - * from L1's HCR_EL2, or API/APK are both set. - */ - if (unlikely(is_nested_ctxt(vcpu))) { - u64 val; + if (!vcpu_has_ptrauth(vcpu)) + return; =20 - val =3D __vcpu_sys_reg(vcpu, HCR_EL2); - val &=3D (HCR_API | HCR_APK); - vcpu->arch.hcr_el2 &=3D ~(HCR_API | HCR_APK); - vcpu->arch.hcr_el2 |=3D val; - } else { - vcpu->arch.hcr_el2 |=3D (HCR_API | HCR_APK); - } + /* + * Either we're running an L2 guest, and the API/APK bits come + * from L1's HCR_EL2, or API/APK are both set. + */ + if (unlikely(is_nested_ctxt(vcpu))) { + u64 val; =20 - /* - * Save the host keys if there is any chance for the guest - * to use pauth, as the entry code will reload the guest - * keys in that case. - */ - if (vcpu->arch.hcr_el2 & (HCR_API | HCR_APK)) { - struct kvm_cpu_context *ctxt; + val =3D __vcpu_sys_reg(vcpu, HCR_EL2); + val &=3D (HCR_API | HCR_APK); + vcpu->arch.hcr_el2 &=3D ~(HCR_API | HCR_APK); + vcpu->arch.hcr_el2 |=3D val; + } else { + vcpu->arch.hcr_el2 |=3D (HCR_API | HCR_APK); + } =20 - ctxt =3D this_cpu_ptr_hyp_sym(kvm_hyp_ctxt); - ptrauth_save_keys(ctxt); - } + /* + * Save the host keys if there is any chance for the guest + * to use pauth, as the entry code will reload the guest + * keys in that case. + */ + if (vcpu->arch.hcr_el2 & (HCR_API | HCR_APK)) { + struct kvm_cpu_context *ctxt; + + ctxt =3D this_cpu_ptr_hyp_sym(kvm_hyp_ctxt); + ptrauth_save_keys(ctxt); } } =20 @@ -749,7 +750,8 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) else vcpu->arch.hcr_el2 |=3D HCR_TWI; =20 - vcpu_set_pauth_traps(vcpu); + if (!is_protected_kvm_enabled()) + vcpu_set_pauth_traps(vcpu); =20 if (is_protected_kvm_enabled()) { kvm_call_hyp_nvhe(__pkvm_vcpu_load, --=20 2.43.0 From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6EEBF4A99C4; Thu, 24 Sep 2026 16:05:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265953; cv=none; b=WpaSw48tcpWvD6eq4dc5umFq+W8lQb9ancQrzO45Hpp/AAhkst8R2qjwU5Sudn9isI2dvXpvtTKF5nl1VNPNAypx15vL+KWHJiNuQkgnuz30y73OxrGMbv6nbwwT4UM2clOzDht1Sf5hlyBVnfnidQk1xHgj2ZmTmTEeMl1iz7c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Thu, 24 Sep 2026 09:05:46 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 211E43F86C; Thu, 24 Sep 2026 09:05:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790265950; bh=WYaLGyFwljsRmpCG8+CIlgjwWFS50duC3yD1GV7CE8M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VNpcMhWARyZhReZJgzG5cPidgVSkI6j1JyWp0TGsX9m/TrXHJMwWVdViIUf8dX8mN mtHzIRb/kifuVCaD+p8BU8HP2osY5ZPvzZfCk+tKE9AKBUiYW0DYDU2BcGevX4ZSNH ODvRzvHi9zrQ9q54ejy90F8b61mwL/33YMMPVjyk= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Suzuki K Poulose Subject: [PATCH v20 07/22] KVM: arm64: Refactor the vcpu_load to allow for VM specific callbacks Date: Thu, 24 Sep 2026 17:04:49 +0100 Message-ID: <20260924160504.853911-8-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To keep the VCPU load/put handling cleaner with the different kinds of VM types, we are about to introduce VM specific callbacks to do just the right thing. In preparation for that, make some refactoring to add the change easier by mainly feature specific configurations to individual wrappers, so that different callbacks could reuse the helpers. Adds vcpu_prepare_mmu()/vcpu_put_mmu() wrappers to load/put MMU related configurations for !pKVM guests. Additionally makes it explicit that kvm_arm_vmid_clear_active() is not required for pKVM host. Add vcpu_load_pvtime(), vcpu_set_wfx_traps() wrappers for handling the corresponding configurations. While at it, also make it clear that the timer loading constraints only apply for the VHE. No functional changes intended. Based on a work by Marc Zyngier. Reviewed-by: Gavin Shan Tested-by: Gavin Shan Signed-off-by: Suzuki K Poulose --- Changes since v19: - Add vcpu_put_mmu() to pair with the vcpu_prepare_mmu() and make the call conditional on !is_protected_kvm_enabled(). Preparing the path for per-flavor callbacks - Update the timer load constraints comment to reflect that it only applies for VHE - Wrap kvm_arm_vmid_clear_active() to vcpu_put_mmu() to compliement with the vcpu_prepare_mmu(). Also only clear the VMID for non-pKVM guests --- arch/arm64/kvm/arm.c | 59 ++++++++++++++++++++++++++++++-------------- 1 file changed, 40 insertions(+), 19 deletions(-) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 849f5fcc26c15..6393b2c1a65de 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -684,14 +684,11 @@ static bool kvm_vcpu_should_clear_twe(struct kvm_vcpu= *vcpu) return single_task_running(); } =20 -void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) +static void vcpu_prepare_mmu(struct kvm_vcpu *vcpu) { struct kvm_s2_mmu *mmu; int *last_ran; =20 - if (is_protected_kvm_enabled()) - goto nommu; - if (vcpu_has_nv(vcpu)) kvm_vcpu_load_hw_mmu(vcpu); =20 @@ -721,34 +718,56 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cp= u) kvm_call_hyp(__kvm_flush_cpu_context, mmu); *last_ran =3D vcpu->vcpu_idx; } +} =20 -nommu: +static void vcpu_put_mmu(struct kvm_vcpu *vcpu) +{ + kvm_arm_vmid_clear_active(); +} + +static void vcpu_set_wfx_traps(struct kvm_vcpu *vcpu) +{ + if (kvm_vcpu_should_clear_twe(vcpu)) + vcpu->arch.hcr_el2 &=3D ~HCR_TWE; + else + vcpu->arch.hcr_el2 |=3D HCR_TWE; + + if (kvm_vcpu_should_clear_twi(vcpu)) + vcpu->arch.hcr_el2 &=3D ~HCR_TWI; + else + vcpu->arch.hcr_el2 |=3D HCR_TWI; +} + +static void vcpu_load_pvtime(struct kvm_vcpu *vcpu) +{ + if (kvm_arm_is_pvtime_enabled(&vcpu->arch)) + kvm_make_request(KVM_REQ_RECORD_STEAL, vcpu); +} + +void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) +{ vcpu->cpu =3D cpu; =20 + if (!is_protected_kvm_enabled()) + vcpu_prepare_mmu(vcpu); /* - * The timer must be loaded before the vgic to correctly set up physical - * interrupt deactivation in nested state (e.g. timer interrupt). + * For VHE, the timer must be loaded before the vgic to correctly + * set up physical interrupt deactivation in nested state (e.g. timer + * interrupt). */ kvm_timer_vcpu_load(vcpu); kvm_vgic_load(vcpu); kvm_vcpu_load_debug(vcpu); kvm_vcpu_load_fgt(vcpu); + if (has_vhe()) kvm_vcpu_load_vhe(vcpu); + kvm_arch_vcpu_load_fp(vcpu); kvm_vcpu_pmu_restore_guest(vcpu); - if (kvm_arm_is_pvtime_enabled(&vcpu->arch)) - kvm_make_request(KVM_REQ_RECORD_STEAL, vcpu); =20 - if (kvm_vcpu_should_clear_twe(vcpu)) - vcpu->arch.hcr_el2 &=3D ~HCR_TWE; - else - vcpu->arch.hcr_el2 |=3D HCR_TWE; - - if (kvm_vcpu_should_clear_twi(vcpu)) - vcpu->arch.hcr_el2 &=3D ~HCR_TWI; - else - vcpu->arch.hcr_el2 |=3D HCR_TWI; + vcpu_load_pvtime(vcpu); + vcpu_set_wfx_traps(vcpu); =20 if (!is_protected_kvm_enabled()) vcpu_set_pauth_traps(vcpu); @@ -787,7 +806,9 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) kvm_vcpu_pmu_restore_host(vcpu); if (vcpu_has_nv(vcpu)) kvm_vcpu_put_hw_mmu(vcpu); - kvm_arm_vmid_clear_active(); + + if (!is_protected_kvm_enabled()) + vcpu_put_mmu(vcpu); =20 vcpu_clear_on_unsupported_cpu(vcpu); vcpu->cpu =3D -1; --=20 2.43.0 From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C478F4AEBC0; Thu, 24 Sep 2026 16:05:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Wku7+SWf" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9EFB1152B; Thu, 24 Sep 2026 09:05:51 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BC0713F86C; Thu, 24 Sep 2026 09:05:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790265955; bh=E0gN5eJL+sVLkl6PPZuSbTVgK4lLcJZnmMqWJaO1rJg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Wku7+SWfUTbcLDGs9UepmHG5o2OCTOfpY8MwkfXZF1ZpX6vqIGI52hdVu2kg1S/Bd D4QPz0Zmlsv5UzBaNVce/ZW+c9ztFGGlQIbF/9txhaYJMo9475Wi55Pj7EYjdoznLC wrLfzRXDJPLyjM5xcJLHwAYoD8L9b9/XVB45RPi0= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Suzuki K Poulose Subject: [PATCH v20 08/22] KVM: arm64: Add vcpu load/put call backs for flavors Date: Thu, 24 Sep 2026 17:04:50 +0100 Message-ID: <20260924160504.853911-9-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add VM flavor specific handlers for VCPU load/put, in an effort to make it easier to follow the code. pauth traps were removed from VMs running PKVM as it is a no-op for them. Based on a patch by Marc Zyngier Suggested-by: Marc Zyngier Tested-by: Gavin Shan Signed-off-by: Suzuki K Poulose --- Changes since v19: - Order the vcpu ops by vm_flavor enum value - Rebase on the introduction of vcpu_put_mmu() wrapper in the previous pat= ch Changes since v17: - Use macro to initialize the per-flavor ops - Add a wrapper to initialise ops in the vcpu structure. - Add BUILD_BUG_ON for the array size - Remove irrelevant comment about the order of timer loading for !VHE - Use the explicti kvm_call_hyp_nvhe for nVHE flavor - Don't call nvhe_vcpu_put from pkvm_vcpu_put, open code them - Drop cpu argument for vcpu_load() callback. We set the cpu before the callbacks are invoked --- arch/arm64/include/asm/kvm_host.h | 6 ++ arch/arm64/kvm/arm.c | 138 +++++++++++++++++++++++------- 2 files changed, 114 insertions(+), 30 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 63bd1f76edb7b..9e1fa00d96f7c 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -150,6 +150,11 @@ struct kvm_vmid { atomic64_t id; }; =20 +struct kvm_vcpu_ops { + void (*vcpu_load)(struct kvm_vcpu *vcpu); + void (*vcpu_put)(struct kvm_vcpu *vcpu); +}; + struct kvm_s2_mmu { struct kvm_vmid vmid; =20 @@ -855,6 +860,7 @@ struct vncr_tlb; =20 struct kvm_vcpu_arch { struct kvm_cpu_context ctxt; + const struct kvm_vcpu_ops *vcpu_ops; =20 /* * Guest floating point state diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 6393b2c1a65de..bcb78fc7676c5 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -93,6 +93,7 @@ static const struct kvm_ioctl_cap_map vm_ioctl_caps[] =3D= { { KVM_ARM_PREFERRED_TARGET, KVM_CAP_ARM_BASIC }, }; =20 +static void kvm_init_vcpu_ops(struct kvm_vcpu *vcpu); /* * Set *ext to the capability. * Return 0 if found, or -EINVAL if no IOCTL matches. @@ -569,6 +570,8 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) mutex_unlock(&vcpu->mutex); #endif =20 + kvm_init_vcpu_ops(vcpu); + /* Force users to call KVM_ARM_VCPU_INIT */ vcpu_clear_flag(vcpu, VCPU_INITIALIZED); =20 @@ -744,12 +747,9 @@ static void vcpu_load_pvtime(struct kvm_vcpu *vcpu) kvm_make_request(KVM_REQ_RECORD_STEAL, vcpu); } =20 -void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) +static void vhe_vcpu_load(struct kvm_vcpu *vcpu) { - vcpu->cpu =3D cpu; - - if (!is_protected_kvm_enabled()) - vcpu_prepare_mmu(vcpu); + vcpu_prepare_mmu(vcpu); /* * For VHE, the timer must be loaded before the vgic to correctly * set up physical interrupt deactivation in nested state (e.g. timer @@ -759,26 +759,53 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cp= u) kvm_vgic_load(vcpu); kvm_vcpu_load_debug(vcpu); kvm_vcpu_load_fgt(vcpu); + kvm_vcpu_load_vhe(vcpu); + kvm_arch_vcpu_load_fp(vcpu); + kvm_vcpu_pmu_restore_guest(vcpu); + + vcpu_load_pvtime(vcpu); + vcpu_set_wfx_traps(vcpu); + vcpu_set_pauth_traps(vcpu); +} =20 - if (has_vhe()) - kvm_vcpu_load_vhe(vcpu); +static void nvhe_vcpu_load(struct kvm_vcpu *vcpu) +{ + vcpu_prepare_mmu(vcpu); + kvm_timer_vcpu_load(vcpu); + kvm_vgic_load(vcpu); + kvm_vcpu_load_debug(vcpu); + kvm_vcpu_load_fgt(vcpu); + kvm_arch_vcpu_load_fp(vcpu); + kvm_vcpu_pmu_restore_guest(vcpu); + + vcpu_load_pvtime(vcpu); + vcpu_set_wfx_traps(vcpu); + vcpu_set_pauth_traps(vcpu); +} =20 +static void pkvm_vcpu_load(struct kvm_vcpu *vcpu) +{ + kvm_timer_vcpu_load(vcpu); + kvm_vgic_load(vcpu); + kvm_vcpu_load_debug(vcpu); + kvm_vcpu_load_fgt(vcpu); kvm_arch_vcpu_load_fp(vcpu); kvm_vcpu_pmu_restore_guest(vcpu); =20 vcpu_load_pvtime(vcpu); vcpu_set_wfx_traps(vcpu); =20 - if (!is_protected_kvm_enabled()) - vcpu_set_pauth_traps(vcpu); + kvm_call_hyp_nvhe(__pkvm_vcpu_load, + vcpu->kvm->arch.pkvm.handle, + vcpu->vcpu_idx, vcpu->arch.hcr_el2); + kvm_call_hyp_nvhe(__vgic_v3_restore_vmcr_aprs, + &vcpu->arch.vgic_cpu.vgic_v3); +} =20 - if (is_protected_kvm_enabled()) { - kvm_call_hyp_nvhe(__pkvm_vcpu_load, - vcpu->kvm->arch.pkvm.handle, - vcpu->vcpu_idx, vcpu->arch.hcr_el2); - kvm_call_hyp(__vgic_v3_restore_vmcr_aprs, - &vcpu->arch.vgic_cpu.vgic_v3); - } +void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) +{ + vcpu->cpu =3D cpu; + vcpu->arch.vcpu_ops->vcpu_load(vcpu); =20 if (!cpumask_test_cpu(cpu, vcpu->kvm->arch.supported_cpus)) vcpu_set_on_unsupported_cpu(vcpu); @@ -786,30 +813,50 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cp= u) vcpu->arch.pid =3D pid_nr(vcpu->pid); } =20 -void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) +static void vhe_vcpu_put(struct kvm_vcpu *vcpu) { - if (is_protected_kvm_enabled()) { - kvm_call_hyp(__vgic_v3_save_aprs, &vcpu->arch.vgic_cpu.vgic_v3); - kvm_call_hyp_nvhe(__pkvm_vcpu_put); - - /* __pkvm_vcpu_put implies a sync of the state */ - if (kvm_vm_is_unprotected_pkvm(vcpu->kvm)) - vcpu_set_flag(vcpu, PKVM_HOST_STATE_DIRTY); - } - kvm_vcpu_put_debug(vcpu); kvm_arch_vcpu_put_fp(vcpu); - if (has_vhe()) - kvm_vcpu_put_vhe(vcpu); + kvm_vcpu_put_vhe(vcpu); kvm_timer_vcpu_put(vcpu); kvm_vgic_put(vcpu); kvm_vcpu_pmu_restore_host(vcpu); + if (vcpu_has_nv(vcpu)) kvm_vcpu_put_hw_mmu(vcpu); =20 - if (!is_protected_kvm_enabled()) - vcpu_put_mmu(vcpu); + vcpu_put_mmu(vcpu); +} =20 +static void nvhe_vcpu_put(struct kvm_vcpu *vcpu) +{ + kvm_vcpu_put_debug(vcpu); + kvm_arch_vcpu_put_fp(vcpu); + kvm_timer_vcpu_put(vcpu); + kvm_vgic_put(vcpu); + kvm_vcpu_pmu_restore_host(vcpu); + vcpu_put_mmu(vcpu); +} + +static void pkvm_vcpu_put(struct kvm_vcpu *vcpu) +{ + kvm_call_hyp_nvhe(__vgic_v3_save_aprs, &vcpu->arch.vgic_cpu.vgic_v3); + kvm_call_hyp_nvhe(__pkvm_vcpu_put); + + /* __pkvm_vcpu_put implies a sync of the state */ + if (kvm_vm_is_unprotected_pkvm(vcpu->kvm)) + vcpu_set_flag(vcpu, PKVM_HOST_STATE_DIRTY); + + kvm_vcpu_put_debug(vcpu); + kvm_arch_vcpu_put_fp(vcpu); + kvm_timer_vcpu_put(vcpu); + kvm_vgic_put(vcpu); + kvm_vcpu_pmu_restore_host(vcpu); +} + +void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) +{ + vcpu->arch.vcpu_ops->vcpu_put(vcpu); vcpu_clear_on_unsupported_cpu(vcpu); vcpu->cpu =3D -1; } @@ -2149,6 +2196,37 @@ int kvm_arch_vm_ioctl(struct file *filp, unsigned in= t ioctl, unsigned long arg) } } =20 +static const struct kvm_vcpu_ops vhe_vcpu_ops =3D { + .vcpu_load =3D vhe_vcpu_load, + .vcpu_put =3D vhe_vcpu_put, +}; + +static const struct kvm_vcpu_ops nvhe_vcpu_ops =3D { + .vcpu_load =3D nvhe_vcpu_load, + .vcpu_put =3D nvhe_vcpu_put, +}; + +static const struct kvm_vcpu_ops pkvm_vcpu_ops =3D { + .vcpu_load =3D pkvm_vcpu_load, + .vcpu_put =3D pkvm_vcpu_put, +}; + +#define KVM_VCPU_OPS(flavor, ops) \ + [(flavor)] =3D (ops) + +static const struct kvm_vcpu_ops *arm64_vcpu_ops[] =3D { + KVM_VCPU_OPS(VM_NVHE, &nvhe_vcpu_ops), + KVM_VCPU_OPS(VM_VHE, &vhe_vcpu_ops), + KVM_VCPU_OPS(VM_PKVM, &pkvm_vcpu_ops), + KVM_VCPU_OPS(VM_PROTECTED_PKVM, &pkvm_vcpu_ops), +}; + +static void kvm_init_vcpu_ops(struct kvm_vcpu *vcpu) +{ + BUILD_BUG_ON(ARRAY_SIZE(arm64_vcpu_ops) !=3D VM_FLAVOR_MAX); + vcpu->arch.vcpu_ops =3D arm64_vcpu_ops[vcpu->kvm->arch.vm_flavor]; +} + static unsigned long nvhe_percpu_size(void) { return (unsigned long)CHOOSE_NVHE_SYM(__per_cpu_end) - --=20 2.43.0 From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9E6B44AF668; Thu, 24 Sep 2026 16:06:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265962; cv=none; b=oILdXM/3SzY/JmCBgnWX33BJocs3rs+H9FkYJX09tBhg/xU7XWm+ukXF6uOLj1nCEE6sCdiqf/cuLTcASD8GYhRcfKb09JXe5568cFNxPG8X/mfTFfa0B3NlgRR+HXx5kTFYwv+Af2Y97Mx73v3xIYcdGGZwfOhfJ5Uy6SleQTM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265962; c=relaxed/simple; bh=RosB8NRTeZaidf7WIQy5/72KniYUL3pT9/e6vHv0efs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EoFCHQMwfKE6SUW6StKeKYRALZEHYVBrcD2+a9h57no294Fwto7LBiJ5HksvlupsYXsSEIM68Vf1ABmEA5jukSu6uI/7Z+VNZxjEzbH3euQR3LYucBjGpgjvkLymVAG2lDkJtVHBkmov7CXcw7FSem8GQNCu5u89ckPTk41fHjE= ARC-Authentication-Results: i=1; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Vll1Jx0io1INPQwoNKH2983r9hz0Hhn6LgJVkdXLc5+W3MOKnbjugXxyV2zaqec5H oxoJ4pLDAH8E44bfNSwBy2m8K5zSC8Pl6s9Fu5rUnfQlfNLWL2PHVAckz463eoTfaB rvBmb04PiFV0XcxggA6Jr1Qx5yPqelMblYQKbMHE= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Suzuki K Poulose , Fuad Tabba Subject: [PATCH v20 09/22] KVM: arm64: Reuse kvm_stage2_unmap_range in kvm_unmap_gfn_range Date: Thu, 24 Sep 2026 17:04:51 +0100 Message-ID: <20260924160504.853911-10-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding VM specific backends for stage2 operation, switch to kvm_stage2_unmap_range() instead of __unmap_stage2_range() from the kvm_unmap_gfn_range(). Drop the bail out check for protected VMs and defer that to the one in kvm_stage2_unmap_range(). Later we would replace the logic in kvm_stage2_unmap_range() with VM specific backends. No functional changes intended. Reviewed-by: Fuad Tabba Reviewed-by: Jonathan Cameron Tested-by: Gavin Shan Signed-off-by: Suzuki K Poulose --- arch/arm64/kvm/mmu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 0f4e8b71fa85d..365e2a12c2348 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -2436,12 +2436,12 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) =20 bool kvm_unmap_gfn_range(struct kvm *kvm, struct kvm_gfn_range *range) { - if (!kvm->arch.mmu.pgt || kvm_vm_is_protected(kvm)) + if (!kvm->arch.mmu.pgt) return false; =20 - __unmap_stage2_range(&kvm->arch.mmu, range->start << PAGE_SHIFT, - (range->end - range->start) << PAGE_SHIFT, - range->may_block); + kvm_stage2_unmap_range(&kvm->arch.mmu, range->start << PAGE_SHIFT, + (range->end - range->start) << PAGE_SHIFT, + range->may_block); =20 kvm_nested_s2_unmap(kvm, range->may_block); return false; --=20 2.43.0 From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5D2DF4AF668; Thu, 24 Sep 2026 16:06:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265967; cv=none; b=unoOSHHhnib9V/l9x340jnaKmqujAeZLf9FcIvIVu3N5NZAVQe9VFO0bdsjoIlouFJlFvV5QXSsirNIgSVMQbL6vTb+Fj8Oe4MCMV+fuPQVLD/XwJw2+kNSEw4+m9iX+hMdiSmYPNewxi4pf+sY1xuogLeKYHymPdGBLj6dbtOs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265967; c=relaxed/simple; bh=4wTaOKH93FEzC+nQtfSCv127ZNDnvHiP4mPJV/37TuU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Jv3aheBVkK4P6uJTGL9Ed8uLKuiG2szZxII2JJsTpqUn6MTvkl2V8Xic1L/DabCjb2WgM4PmhiZ5P2Gdmswz8jWyG6voxC2ZZW7uZdCbGk+m3VKObCfPHmrBBaljRVY1voO3wz2Mlatc7r+Ku2aY1mZoBZGKUIFuQbVguiregL8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=KuH0ONIV; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="KuH0ONIV" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F2E281E7D; Thu, 24 Sep 2026 09:06:00 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3BEC63F86C; Thu, 24 Sep 2026 09:06:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790265964; bh=4wTaOKH93FEzC+nQtfSCv127ZNDnvHiP4mPJV/37TuU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KuH0ONIVo/TrIV7cekkAC0IamsCb+pdqdpFFh0QV0NHDh0G3kzTtrL1UfBS4eJJhl m7JdWhlfDi0h/vMGx/z8yvJlkKUtgWr0SWuH6bYHtDuJ3Z1HOi03OiQKU4pjMp7e2w LbTpCe/bvNd8S6AYk4pmHf3f14Z+thkiEdbAs4eI= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Suzuki K Poulose Subject: [PATCH v20 10/22] KVM: arm64: Add VM specific callback for S2 MMU operations Date: Thu, 24 Sep 2026 17:04:52 +0100 Message-ID: <20260924160504.853911-11-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add VM type specific S2 MMU operation backends which can be initialized per VM flavor, to keep the handling cleaner. Reviewed-by: Jonathan Cameron Tested-by: Gavin Shan Signed-off-by: Suzuki K Poulose --- Changes since v19: - Add a blank line in kvm_arch_flush_remote_tlbs() --- arch/arm64/include/asm/kvm_host.h | 15 ++++ arch/arm64/kvm/mmu.c | 138 +++++++++++++++++++++++++----- 2 files changed, 132 insertions(+), 21 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 9e1fa00d96f7c..f01df02dabfe1 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -155,6 +155,19 @@ struct kvm_vcpu_ops { void (*vcpu_put)(struct kvm_vcpu *vcpu); }; =20 +struct kvm_gfn_range; + +struct kvm_vm_s2_ops { + bool (*vm_age_gfn)(struct kvm *kvm, struct kvm_gfn_range *range); + bool (*vm_test_age_gfn)(struct kvm *kvm, struct kvm_gfn_range *range); + int (*vm_flush_remote_tlbs)(struct kvm *kvm); + int (*vm_flush_remote_tlbs_range)(struct kvm *kvm, gfn_t gfn, + u64 nr_pages); + void (*vm_stage2_unmap_range)(struct kvm_s2_mmu *mmu, + phys_addr_t start, u64 size, + bool may_block); +}; + struct kvm_s2_mmu { struct kvm_vmid vmid; =20 @@ -332,6 +345,8 @@ struct kvm_arch { */ u64 fgu[__NR_FGT_GROUP_IDS__]; =20 + const struct kvm_vm_s2_ops *vm_s2_ops; + /* * Stage 2 paging state for VMs with nested S2 using a virtual * VMID. diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 365e2a12c2348..92cdbeb44807e 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -37,6 +37,8 @@ static unsigned long __ro_after_init io_map_base; =20 #define KVM_PGT_FN(fn) (!is_protected_kvm_enabled() ? fn : p ## fn) =20 +static int kvm_vm_init_vm_s2_ops(struct kvm *kvm); + static phys_addr_t __stage2_range_addr_end(phys_addr_t addr, phys_addr_t e= nd, phys_addr_t size) { @@ -166,6 +168,18 @@ static bool memslot_is_logging(struct kvm_memory_slot = *memslot) return memslot->dirty_bitmap && !(memslot->flags & KVM_MEM_READONLY); } =20 +static int pkvm_flush_remote_tlbs(struct kvm *kvm) +{ + kvm_call_hyp_nvhe(__pkvm_tlb_flush_vmid, kvm->arch.pkvm.handle); + return 0; +} + +static int kvm_vm_flush_remote_tlbs(struct kvm *kvm) +{ + kvm_call_hyp(__kvm_tlb_flush_vmid, &kvm->arch.mmu); + return 0; +} + /** * kvm_arch_flush_remote_tlbs() - flush all VM TLB entries for v7/8 * @kvm: pointer to kvm structure. @@ -174,26 +188,37 @@ static bool memslot_is_logging(struct kvm_memory_slot= *memslot) */ int kvm_arch_flush_remote_tlbs(struct kvm *kvm) { - if (is_protected_kvm_enabled()) - kvm_call_hyp_nvhe(__pkvm_tlb_flush_vmid, kvm->arch.pkvm.handle); - else - kvm_call_hyp(__kvm_tlb_flush_vmid, &kvm->arch.mmu); - return 0; + if (!kvm->arch.vm_s2_ops->vm_flush_remote_tlbs) + return 1; + + return kvm->arch.vm_s2_ops->vm_flush_remote_tlbs(kvm); +} + +static int pkvm_flush_remote_tlbs_range(struct kvm *kvm, + gfn_t gfn, u64 nr_pages) +{ + return pkvm_flush_remote_tlbs(kvm); } =20 -int kvm_arch_flush_remote_tlbs_range(struct kvm *kvm, - gfn_t gfn, u64 nr_pages) +static int kvm_vm_flush_remote_tlbs_range(struct kvm *kvm, + gfn_t gfn, u64 nr_pages) { u64 size =3D nr_pages << PAGE_SHIFT; u64 addr =3D gfn << PAGE_SHIFT; =20 - if (is_protected_kvm_enabled()) - kvm_call_hyp_nvhe(__pkvm_tlb_flush_vmid, kvm->arch.pkvm.handle); - else - kvm_tlb_flush_vmid_range(&kvm->arch.mmu, addr, size); + kvm_tlb_flush_vmid_range(&kvm->arch.mmu, addr, size); return 0; } =20 +int kvm_arch_flush_remote_tlbs_range(struct kvm *kvm, + gfn_t gfn, u64 nr_pages) +{ + if (!kvm->arch.vm_s2_ops->vm_flush_remote_tlbs_range) + return 1; + + return kvm->arch.vm_s2_ops->vm_flush_remote_tlbs_range(kvm, gfn, nr_pages= ); +} + static void *stage2_memcache_zalloc_page(void *arg) { struct kvm_mmu_memory_cache *mc =3D arg; @@ -337,13 +362,20 @@ static void __unmap_stage2_range(struct kvm_s2_mmu *m= mu, phys_addr_t start, u64 may_block)); } =20 +static void kvm_vm_stage2_unmap_range(struct kvm_s2_mmu *mmu, + phys_addr_t start, + u64 size, bool may_block) +{ + __unmap_stage2_range(mmu, start, size, may_block); +} + void kvm_stage2_unmap_range(struct kvm_s2_mmu *mmu, phys_addr_t start, u64 size, bool may_block) { - if (kvm_vm_is_protected(kvm_s2_mmu_to_kvm(mmu))) - return; + struct kvm *kvm =3D kvm_s2_mmu_to_kvm(mmu); =20 - __unmap_stage2_range(mmu, start, size, may_block); + if (kvm->arch.vm_s2_ops->vm_stage2_unmap_range) + kvm->arch.vm_s2_ops->vm_stage2_unmap_range(mmu, start, size, may_block); } =20 void kvm_stage2_flush_range(struct kvm_s2_mmu *mmu, phys_addr_t addr, phys= _addr_t end) @@ -983,6 +1015,12 @@ int kvm_init_stage2_mmu(struct kvm *kvm, struct kvm_s= 2_mmu *mmu, unsigned long t int cpu, err; struct kvm_pgtable *pgt; =20 + /* Initialize the VM ops for the VM instance for the first time */ + if (mmu =3D=3D &kvm->arch.mmu) { + err =3D kvm_vm_init_vm_s2_ops(kvm); + if (err) + return err; + } /* * If we already have our page tables in place, and that the * MMU context is the canonical one, we have a bug somewhere, @@ -2447,34 +2485,46 @@ bool kvm_unmap_gfn_range(struct kvm *kvm, struct kv= m_gfn_range *range) return false; } =20 -bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) +static bool kvm_vm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) { u64 size =3D (range->end - range->start) << PAGE_SHIFT; =20 - if (!kvm->arch.mmu.pgt || kvm_vm_is_protected(kvm)) - return false; - return KVM_PGT_FN(kvm_pgtable_stage2_test_clear_young)(kvm->arch.mmu.pgt, range->start << PAGE_SHIFT, size, true); +} + +bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) +{ + if (!kvm->arch.mmu.pgt || !kvm->arch.vm_s2_ops->vm_age_gfn) + return false; + + return kvm->arch.vm_s2_ops->vm_age_gfn(kvm, range); /* * TODO: Handle nested_mmu structures here using the reverse mapping in * a later version of patch series. */ } =20 -bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) +static bool kvm_vm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *ran= ge) { u64 size =3D (range->end - range->start) << PAGE_SHIFT; =20 - if (!kvm->arch.mmu.pgt || kvm_vm_is_protected(kvm)) - return false; =20 return KVM_PGT_FN(kvm_pgtable_stage2_test_clear_young)(kvm->arch.mmu.pgt, range->start << PAGE_SHIFT, size, false); } =20 +bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) +{ + + if (!kvm->arch.mmu.pgt || !kvm->arch.vm_s2_ops->vm_test_age_gfn) + return false; + + return kvm->arch.vm_s2_ops->vm_test_age_gfn(kvm, range); +} + phys_addr_t kvm_mmu_get_httbr(void) { return __pa(hyp_pgtable->pgd); @@ -2796,3 +2846,49 @@ void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool wa= s_enabled) =20 trace_kvm_toggle_cache(*vcpu_pc(vcpu), was_enabled, now_enabled); } + +static const struct kvm_vm_s2_ops protected_pkvm_vm_s2_ops =3D { + .vm_flush_remote_tlbs =3D pkvm_flush_remote_tlbs, + .vm_flush_remote_tlbs_range =3D pkvm_flush_remote_tlbs_range, + /* + * Not supported for Protected VMs under pKVM + * .vm_age_gfn + * .vm_test_age_gfn + * .vm_stage2_unmap_range + */ +}; + +static const struct kvm_vm_s2_ops pkvm_vm_s2_ops =3D { + .vm_flush_remote_tlbs =3D pkvm_flush_remote_tlbs, + .vm_flush_remote_tlbs_range =3D pkvm_flush_remote_tlbs_range, + .vm_age_gfn =3D kvm_vm_age_gfn, + .vm_test_age_gfn =3D kvm_vm_test_age_gfn, + .vm_stage2_unmap_range =3D kvm_vm_stage2_unmap_range, +}; + +static const struct kvm_vm_s2_ops kvm_default_vm_s2_ops =3D { + .vm_flush_remote_tlbs =3D kvm_vm_flush_remote_tlbs, + .vm_flush_remote_tlbs_range =3D kvm_vm_flush_remote_tlbs_range, + .vm_age_gfn =3D kvm_vm_age_gfn, + .vm_test_age_gfn =3D kvm_vm_test_age_gfn, + .vm_stage2_unmap_range =3D kvm_vm_stage2_unmap_range, +}; + +#define KVM_VM_S2_OPS(flavor, ops) \ + [flavor] =3D ops +static const struct kvm_vm_s2_ops *arm64_vm_s2_ops[] =3D { + KVM_VM_S2_OPS(VM_VHE, &kvm_default_vm_s2_ops), + KVM_VM_S2_OPS(VM_NVHE, &kvm_default_vm_s2_ops), + KVM_VM_S2_OPS(VM_PKVM, &pkvm_vm_s2_ops), + KVM_VM_S2_OPS(VM_PROTECTED_PKVM, &protected_pkvm_vm_s2_ops), +}; + +static int kvm_vm_init_vm_s2_ops(struct kvm *kvm) +{ + BUILD_BUG_ON(ARRAY_SIZE(arm64_vm_s2_ops) !=3D VM_FLAVOR_MAX); + + kvm->arch.vm_s2_ops =3D arm64_vm_s2_ops[kvm->arch.vm_flavor]; + if (WARN_ON(!kvm->arch.vm_s2_ops)) + return -EINVAL; + return 0; +} --=20 2.43.0 From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 963474B2044; Thu, 24 Sep 2026 16:06:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265971; cv=none; b=R8fXGqeHmmPdThrqW8w0w/OEh3MzMR77BMHltc6m2rDP0s17e9nHXP+4px+825qeBmjiLtEUQ2J+5Kk6xx2+vDVmd9u8IhuBqmU7+yOMpnU4Ka9tQ5ufrECErWUOna+YxGkQ5kmnsjEguygYXlLeIGmpHqge+x+X94nvEROwWEQ= ARC-Message-Signature: i=1; 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Thu, 24 Sep 2026 09:06:05 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D4CF43F86C; Thu, 24 Sep 2026 09:06:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790265968; bh=XKUI0O+yupvbzqqTCtUZd6FFNrWihRgYRS3Pt81HQOM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZLo+LMYOo3zDlgRnvgVuTcBsAZj2x1FVzaGN9lIWkFfFwBijU/CUySO2+3dxbw6ec HlyqqMi01NHfvhhb7UEOr/x4o7le5+19zMdQGJ3wDZdQ8g61abJ8lsRr0HwRTuhWiU QYIWHZyxYfEYXCAbiHGhvJrH4Xxm265z3Gn7d75Q= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Suzuki K Poulose Subject: [PATCH v20 11/22] KVM: arm64: Use a local kvm pointer in kvm_handle_guest_abort() Date: Thu, 24 Sep 2026 17:04:53 +0100 Message-ID: <20260924160504.853911-12-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" kvm_handle_guest_abort() repeatedly obtains the VM from vcpu->kvm. Introduce a local kvm pointer and use it throughout the function. While touching the code, fix the missing whitespace in the kvm_is_nested_s2_mmu() call. Suggested-by: Jonathan Cameron Signed-off-by: Suzuki K Poulose --- arch/arm64/kvm/mmu.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 92cdbeb44807e..8fe7178c40bec 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -2287,6 +2287,7 @@ int kvm_handle_guest_sea(struct kvm_vcpu *vcpu) */ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) { + struct kvm *kvm =3D vcpu->kvm; struct kvm_s2_trans nested_trans, *nested =3D NULL; unsigned long esr; phys_addr_t fault_ipa; /* The address we faulted on */ @@ -2307,7 +2308,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) * with an SEA. */ ipa =3D fault_ipa =3D kvm_vcpu_get_fault_ipa(vcpu); - if (KVM_BUG_ON(ipa =3D=3D INVALID_GPA, vcpu->kvm)) + if (KVM_BUG_ON(ipa =3D=3D INVALID_GPA, kvm)) return -EFAULT; =20 is_iabt =3D kvm_vcpu_trap_is_iabt(vcpu); @@ -2342,7 +2343,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) return -EFAULT; } =20 - idx =3D srcu_read_lock(&vcpu->kvm->srcu); + idx =3D srcu_read_lock(&kvm->srcu); =20 /* * We may have faulted on a shadow stage 2 page table if we are @@ -2357,7 +2358,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) * nothing to walk and we treat it as a 1:1 before going through the * canonical translation. */ - if (kvm_is_nested_s2_mmu(vcpu->kvm,vcpu->arch.hw_mmu) && + if (kvm_is_nested_s2_mmu(kvm, vcpu->arch.hw_mmu) && vcpu->arch.hw_mmu->nested_stage2_enabled) { u32 esr; =20 @@ -2385,7 +2386,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) } =20 gfn =3D ipa >> PAGE_SHIFT; - memslot =3D gfn_to_memslot(vcpu->kvm, gfn); + memslot =3D gfn_to_memslot(kvm, gfn); hva =3D gfn_to_hva_memslot_prot(memslot, gfn, &writable); write_fault =3D kvm_is_write_fault(vcpu); if (kvm_is_error_hva(hva) || (write_fault && !writable)) { @@ -2449,7 +2450,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) .hva =3D hva, }; =20 - if (kvm_vm_is_protected(vcpu->kvm)) { + if (kvm_vm_is_protected(kvm)) { ret =3D pkvm_mem_abort(&s2fd); } else { VM_WARN_ON_ONCE(kvm_vcpu_trap_is_permission_fault(vcpu) && @@ -2468,7 +2469,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) if (ret =3D=3D -ENOEXEC) ret =3D kvm_inject_sea_iabt(vcpu, kvm_vcpu_get_hfar(vcpu)); out_unlock: - srcu_read_unlock(&vcpu->kvm->srcu, idx); + srcu_read_unlock(&kvm->srcu, idx); return ret; } =20 --=20 2.43.0 From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1D62F4AA1E9; Thu, 24 Sep 2026 16:06:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265975; cv=none; b=Ci4yEaVSVmk6J9yu9VSqCAiNM+Q4YAix2cVn1B2kUReO2lAjjtVSoJ4V95VcEn8o7qZGn7LLn3Zwa7JX7YFwtPXdxVCftD0WM4sQiRy34WaNK5P2mbGd6Mf0FuPYITIWeDjkC/rTOUvoaECdMk0ZS3zpGTZK+W2LJi7YFRU0VJc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265975; c=relaxed/simple; bh=n7yz3W9kIeBZupUqbrSWGGV1frVjZNOBUu35dpOGsW4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Q5K1515P51X9Gt3OSHjI4eXMOcW3XdGsmPZm/GYSY+wHWDZJGd8wEmjrtWMiRG/3K8KiTRuqcTRFFG+a+0BZKf5PYYeCwfnocfY0hXYybUGnpsk+VFCEiEVLFPttbNjmJNT21rHyMaV4wyiegrKHQuYsQW9TG5ZkwPB/Xh2528A= ARC-Authentication-Results: i=1; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ag2masPkvZvyDP1TmM+xdPRFyN5L/1Y1gFz+h/8n8gGQMFGChtjAUw+S78JoQRC9e /8DRQe21byPh9MdIVJjRWyKeG3jXw8ILnsMs4tBLMuTpxXX4GRkEWrpjSNbTuJ8sKS B227iVBMt41jm6DYSIZG5gwjRItM3B6PaA18cWfI= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Suzuki K Poulose Subject: [PATCH v20 12/22] KVM: arm64: Abstract out memory abort handling Date: Thu, 24 Sep 2026 17:04:54 +0100 Message-ID: <20260924160504.853911-13-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the memory abort handling under VM specific s2 operation. Tested-by: Gavin Shan Signed-off-by: Suzuki K Poulose --- Changes since v19: - Drop local variable ret and directly return from if..else for kvm_vm_mem= _abort Changes since v18: - Ensure vm_mem_abort handler is always !NULL --- arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/kvm/mmu.c | 35 ++++++++++++++++++------------- 2 files changed, 22 insertions(+), 15 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index f01df02dabfe1..871f503e9f164 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -156,6 +156,7 @@ struct kvm_vcpu_ops { }; =20 struct kvm_gfn_range; +struct kvm_s2_fault_desc; =20 struct kvm_vm_s2_ops { bool (*vm_age_gfn)(struct kvm *kvm, struct kvm_gfn_range *range); @@ -166,6 +167,7 @@ struct kvm_vm_s2_ops { void (*vm_stage2_unmap_range)(struct kvm_s2_mmu *mmu, phys_addr_t start, u64 size, bool may_block); + int (*vm_mem_abort)(const struct kvm_s2_fault_desc *s2fd); }; =20 struct kvm_s2_mmu { diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 8fe7178c40bec..8e092efdf0825 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1743,7 +1743,7 @@ struct kvm_s2_fault_vma_info { bool map_non_cacheable; }; =20 -static int pkvm_mem_abort(const struct kvm_s2_fault_desc *s2fd) +static int protected_vm_mem_abort(const struct kvm_s2_fault_desc *s2fd) { unsigned int flags =3D FOLL_HWPOISON | FOLL_LONGTERM | FOLL_WRITE; struct kvm_vcpu *vcpu =3D s2fd->vcpu; @@ -2181,6 +2181,20 @@ static int user_mem_abort(const struct kvm_s2_fault_= desc *s2fd) return kvm_s2_fault_map(s2fd, &s2vi, prot, memcache); } =20 +static int kvm_vm_mem_abort(const struct kvm_s2_fault_desc *s2fd) +{ + struct kvm_vcpu *vcpu =3D s2fd->vcpu; + + VM_WARN_ON_ONCE(kvm_vcpu_trap_is_permission_fault(vcpu) && + !kvm_is_write_fault(vcpu) && + !kvm_vcpu_trap_is_exec_fault(vcpu)); + + if (kvm_slot_has_gmem(s2fd->memslot)) + return gmem_abort(s2fd); + else + return user_mem_abort(s2fd); +} + /* Resolve the access fault by making the page young again. */ static void handle_access_fault(struct kvm_vcpu *vcpu, phys_addr_t fault_i= pa) { @@ -2450,19 +2464,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) .hva =3D hva, }; =20 - if (kvm_vm_is_protected(kvm)) { - ret =3D pkvm_mem_abort(&s2fd); - } else { - VM_WARN_ON_ONCE(kvm_vcpu_trap_is_permission_fault(vcpu) && - !write_fault && - !kvm_vcpu_trap_is_exec_fault(vcpu)); - - if (kvm_slot_has_gmem(memslot)) - ret =3D gmem_abort(&s2fd); - else - ret =3D user_mem_abort(&s2fd); - } - + ret =3D kvm->arch.vm_s2_ops->vm_mem_abort(&s2fd); if (ret =3D=3D 0) ret =3D 1; out: @@ -2857,6 +2859,7 @@ static const struct kvm_vm_s2_ops protected_pkvm_vm_s= 2_ops =3D { * .vm_test_age_gfn * .vm_stage2_unmap_range */ + .vm_mem_abort =3D protected_vm_mem_abort, }; =20 static const struct kvm_vm_s2_ops pkvm_vm_s2_ops =3D { @@ -2865,6 +2868,7 @@ static const struct kvm_vm_s2_ops pkvm_vm_s2_ops =3D { .vm_age_gfn =3D kvm_vm_age_gfn, .vm_test_age_gfn =3D kvm_vm_test_age_gfn, .vm_stage2_unmap_range =3D kvm_vm_stage2_unmap_range, + .vm_mem_abort =3D kvm_vm_mem_abort, }; =20 static const struct kvm_vm_s2_ops kvm_default_vm_s2_ops =3D { @@ -2873,6 +2877,7 @@ static const struct kvm_vm_s2_ops kvm_default_vm_s2_o= ps =3D { .vm_age_gfn =3D kvm_vm_age_gfn, .vm_test_age_gfn =3D kvm_vm_test_age_gfn, .vm_stage2_unmap_range =3D kvm_vm_stage2_unmap_range, + .vm_mem_abort =3D kvm_vm_mem_abort, }; =20 #define KVM_VM_S2_OPS(flavor, ops) \ @@ -2889,7 +2894,7 @@ static int kvm_vm_init_vm_s2_ops(struct kvm *kvm) BUILD_BUG_ON(ARRAY_SIZE(arm64_vm_s2_ops) !=3D VM_FLAVOR_MAX); =20 kvm->arch.vm_s2_ops =3D arm64_vm_s2_ops[kvm->arch.vm_flavor]; - if (WARN_ON(!kvm->arch.vm_s2_ops)) + if (WARN_ON(!kvm->arch.vm_s2_ops || !kvm->arch.vm_s2_ops->vm_mem_abort)) return -EINVAL; return 0; } --=20 2.43.0 From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 85AC44A015C; Thu, 24 Sep 2026 16:06:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265981; cv=none; b=cm5qtM8M7QqNcKnEDdAVCnBLhShVfEyEzlDHN1hBmqY7G2uXxBb0RO8wW1q8HOsfW2eHPmhrghXoFp9hBi0zOm6HU6ATkzfBj8DFwIeIAFVyk760dP+/f+p/UK4B6GTxkjTKsXIbosTqFlxbezHLYDmLZr8pI379Z0+2QUYB0tI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Thu, 24 Sep 2026 09:06:14 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9EAAC3F86C; Thu, 24 Sep 2026 09:06:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790265977; bh=aUMJm4MmfVPuRwP9cR6se83O2r8UV6BA2hVIN/OMalE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ifI8ensjRQ0Jh5Jlv4SVCgwkex5CCuJrDuIQwOvtZq11ce8a9HIBAE307eQbW/JZJ ijd1prqvCUMtGpwgSZpllG0yq2lkwZwM1HWV4QZVRiNHFlEs0mYbsdif0SEXWhbV8S NJysNL94iId7dPQv/LH+4R7bNAt4602XrvBJk0Zo= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Suzuki K Poulose Subject: [PATCH v20 13/22] KVM: arm64: Mandate VGIC v3 for pKVM VMs and Realms Date: Thu, 24 Sep 2026 17:04:55 +0100 Message-ID: <20260924160504.853911-14-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" pKVM does not trust the host. Realm VMs follow a similar trust model, with the Realm Management Monitor owning the protected state instead of the host. Add a helper to identify VMs that run under a host-distrusting hypervisor. Use this for blocking ioremap of vgic-v2 into stage2 and prevent creation of VGIC other than v3. Reviewed-by: Jonathan Cameron Tested-by: Gavin Shan Signed-off-by: Suzuki K Poulose --- Changes since v18: - Cover pKVM guests for VGIC v3 mandate. - Merge the VGIC mandate check in here. --- arch/arm64/include/asm/kvm_host.h | 3 +++ arch/arm64/kvm/mmu.c | 2 +- arch/arm64/kvm/vgic/vgic-init.c | 2 ++ 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 871f503e9f164..4d75b8e6797bb 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -328,6 +328,8 @@ enum fgt_group_id { enum kvm_arm_vm_flavor { VM_NVHE, VM_VHE, + /* VMs running on a hyp that doesn't trust */ + MARKER(__VM_DISTRUSTING_HYP), VM_PKVM, /* Normal guests on pKVM */ MARKER(__VM_PROTECTED), VM_PROTECTED_PKVM, /* Protected VM */ @@ -1575,6 +1577,7 @@ struct kvm *kvm_arch_alloc_vm(void); #define kvm_vm_is_unprotected_pkvm(kvm) \ (is_protected_kvm_enabled() && ((kvm)->arch.vm_flavor =3D=3D VM_PKVM)) =20 +#define kvm_vm_hyp_is_distrusting(kvm) ((kvm)->arch.vm_flavor >=3D __VM_DI= STRUSTING_HYP) =20 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 8e092efdf0825..8f21652d3625c 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1252,7 +1252,7 @@ int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_= t guest_ipa, KVM_PGTABLE_PROT_R | (writable ? KVM_PGTABLE_PROT_W : 0); =20 - if (is_protected_kvm_enabled()) + if (kvm_vm_hyp_is_distrusting(kvm)) return -EPERM; =20 size +=3D offset_in_page(guest_ipa); diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-ini= t.c index 4012df6002ea6..874025513afcc 100644 --- a/arch/arm64/kvm/vgic/vgic-init.c +++ b/arch/arm64/kvm/vgic/vgic-init.c @@ -84,6 +84,8 @@ int kvm_vgic_create(struct kvm *kvm, u32 type) !kvm_vgic_global_state.can_emulate_gicv2) return -ENODEV; =20 + if (kvm_vm_hyp_is_distrusting(kvm) && type !=3D KVM_DEV_TYPE_ARM_VGIC_V3) + return -ENODEV; /* * Ensure mutual exclusion with vCPU creation and any vCPU ioctls by: * --=20 2.43.0 From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2305E4BA1CA; Thu, 24 Sep 2026 16:06:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265984; cv=none; b=o1o3dNdisT3oIkD4dNsRCgyPXQF7ajSA/9i+9JqRk+eQ1zu/40EohnlGltkJgm17tBHE9P/L6LfsyfYVkQSu0OoGJqUpOH1u7cpY45P15NW4h2Q1hXDtOU/CYRIfBPMD04mDIU1OWhUlly0rvUsDarYOfN73xxFuhjN+EcK3pmE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265984; c=relaxed/simple; bh=WsjSAf7iPMA/K8mPP8RhduMdKhLRQFgtRTlAA6Oernw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uDcRdWNJuXb/ol54j7KxKQ/IAM4fXjvIK1r1UyCYnXBH0NpQDUCKMk74cyQUHnE4CV2FeJpQLf8Qn0x9A4Y2nVpdPBl8raYiwygsmk1lz2olIvn0C3RisR/O6YB1IrFRLco8bcKDexAXMCxYv9btFVV0nSWFLOwPpMvDyTYBf94= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=pU5ymd75; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="pU5ymd75" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EDFD01E8D; Thu, 24 Sep 2026 09:06:18 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 34F253F86C; Thu, 24 Sep 2026 09:06:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790265982; bh=WsjSAf7iPMA/K8mPP8RhduMdKhLRQFgtRTlAA6Oernw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pU5ymd75t/CsfpLogXNdcKPi6/IkzjunVpNkSNjU+ftoujdOrGrACqvP69o+M6ac+ um4onCJbRh8aczQEMbtQSNjCYHd2ujS9M06fe1S+T3jKJNIHKJ6dveCrxCvHkHkTCs 7FlWfo8P4z5mDotM95yfp6eRbdPk17QbNI4JNMV8= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Suzuki K Poulose Subject: [PATCH v20 14/22] KVM: arm64: CCA: Add a new mode for supporting Realm guests Date: Thu, 24 Sep 2026 17:04:56 +0100 Message-ID: <20260924160504.853911-15-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add an explicit mode to support Arm CCA guests. Reviewed-by: Jonathan Cameron Signed-off-by: Suzuki K Poulose --- Documentation/admin-guide/kernel-parameters.txt | 3 +++ arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/arm.c | 5 +++++ 3 files changed, 9 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 68647ff4bdd24..1afe3df3b923e 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -3256,6 +3256,9 @@ Kernel parameters nested: VHE-based mode with support for nested virtualization. Requires at least ARMv8.4 hardware (with FEAT_NV2). + rmm: Support for running confidential guests in Realm + world using RMM, as defined by Arm Confidential + Compute Architecture (CCA) =20 Defaults to VHE/nVHE based on hardware support. Setting mode to "protected" will disable kexec and hibernation diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 4d75b8e6797bb..4516594d90462 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -69,6 +69,7 @@ enum kvm_mode { KVM_MODE_DEFAULT, KVM_MODE_PROTECTED, KVM_MODE_NV, + KVM_MODE_RMM, KVM_MODE_NONE, }; #ifdef CONFIG_KVM diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index bcb78fc7676c5..3ab722f2af7c8 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -3277,6 +3277,11 @@ static int __init early_kvm_mode_cfg(char *arg) return 0; } =20 + if (strcmp(arg, "rmm") =3D=3D 0 && !WARN_ON(!is_kernel_in_hyp_mode())) { + kvm_mode =3D KVM_MODE_RMM; + return 0; + } + return -EINVAL; } early_param("kvm-arm.mode", early_kvm_mode_cfg); --=20 2.43.0 From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9D7FE4BA1FB; Thu, 24 Sep 2026 16:06:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265989; cv=none; b=qZaKZQpNGIlS7gvfmtRHC3MzQrv10UadPCNq9EYcFcvsTCFvu1VhOivgLLCei9o02CQdm5yZB9FNvADEmr/IEaz5Q5321auU/dQldS3dGWuqMnGtTuGjpsLvcCwZLRhKhRp1BgPLLif5KU9+l1mMZ6JYMzEI7SPsTBnffONfrMk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265989; c=relaxed/simple; bh=p+zcxg7BECsR89IwYH5uWpbzH4ouiCsroF6MFra80bY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JbZ1TFvOr6OluqE1hmN+3Ssxt648sPO1FAo8XGA+JHVZ4iNfEWDhctLG9rPU0gqxoYb+QqNrd0QjtXcPX2CoBGxBCZff963LMbyY65Ch1qqKCLznrGNw87mxpm46hUvCCRh15zuhkQ1KMUBDFyHNREISLIdYkGqL3f0LxiRlwK8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=JlgDOHtG; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="JlgDOHtG" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 868011E8D; Thu, 24 Sep 2026 09:06:23 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C8CDB3F86C; Thu, 24 Sep 2026 09:06:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790265987; bh=p+zcxg7BECsR89IwYH5uWpbzH4ouiCsroF6MFra80bY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JlgDOHtGK5OW9l4IiNRluCiZPy2X9nhDgQdxRJ8KAdYTzJLRgF5nKtkOZcg6uy1wM +dqjqhMhNb2RFXTjwH+ZhqvEZQacUUpjLYkBDuzYNRhwXclEi0Df59hBlowtj//9I0 e8ekQNgKHRo+YTzD+I/9kRcNwjQkoHXjbPHQPrQ4= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Suzuki K Poulose Subject: [PATCH v20 15/22] KVM: arm64: CCA: Add VCPU load/put for Realms Date: Thu, 24 Sep 2026 17:04:57 +0100 Message-ID: <20260924160504.853911-16-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RMM controls the VCPU settings and most are hidden from the KVM, except for the VGIC and timer bits. A later patch would add syncing the VCPU state into the Realm REC related SMC parameters. Signed-off-by: Suzuki K Poulose --- arch/arm64/kvm/arm.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 3ab722f2af7c8..8b1beddd80ea5 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -802,6 +802,13 @@ static void pkvm_vcpu_load(struct kvm_vcpu *vcpu) &vcpu->arch.vgic_cpu.vgic_v3); } =20 +static void realm_vcpu_load(struct kvm_vcpu *vcpu) +{ + kvm_timer_vcpu_load(vcpu); + kvm_vgic_load(vcpu); + vcpu_set_wfx_traps(vcpu); +} + void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) { vcpu->cpu =3D cpu; @@ -854,6 +861,12 @@ static void pkvm_vcpu_put(struct kvm_vcpu *vcpu) kvm_vcpu_pmu_restore_host(vcpu); } =20 +static void realm_vcpu_put(struct kvm_vcpu *vcpu) +{ + kvm_timer_vcpu_put(vcpu); + kvm_vgic_put(vcpu); +} + void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) { vcpu->arch.vcpu_ops->vcpu_put(vcpu); @@ -2211,6 +2224,11 @@ static const struct kvm_vcpu_ops pkvm_vcpu_ops =3D { .vcpu_put =3D pkvm_vcpu_put, }; =20 +static const struct kvm_vcpu_ops realm_vcpu_ops =3D { + .vcpu_load =3D realm_vcpu_load, + .vcpu_put =3D realm_vcpu_put, +}; + #define KVM_VCPU_OPS(flavor, ops) \ [(flavor)] =3D (ops) =20 --=20 2.43.0 From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 16EA14BB281; Thu, 24 Sep 2026 16:06:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265993; cv=none; b=GM+44lLRqbSNHZZRNR83o4M3+a25Xj1jUKnJc8GWS6E6mvyKWXWL5fZ/8fV3rYAnrjHZPlXtxPenuWwPf3VXDTzNtu1m4laNgqhTj8Din5HIhiTHO6SVpyj7lYlXBrKiIWUMfxSGKqppXf3SaSyHNyzJRqdr2m6mvFVSvJMXhZU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265993; c=relaxed/simple; bh=J4qcShf5sghV5L5Y2wcHcCrDh9c4LPadyYpHFo9qgwE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RtQXvyoZ3u2K44i6u9OOm8zeSY8CDffXqTyxnRMBzjzitJxTXFoPuP0U+bk+qRTXonMyZ3f6Z9nEdYF/GixYNiqSL/2TdQpQgibeK/dmpnvCK18+gHqQvHnb1SnMt5VKtoh8jQNZYh/jcw6HD/y6BNdIjXSgzozOnGPPJhaWSX0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=aVuot4se; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="aVuot4se" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1BFEA1E7D; Thu, 24 Sep 2026 09:06:28 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 64CBF3FAB1; Thu, 24 Sep 2026 09:06:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790265991; bh=J4qcShf5sghV5L5Y2wcHcCrDh9c4LPadyYpHFo9qgwE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aVuot4serLCoRiU+s6wSR2runjB+8k9giQ14cbikSaWMXrY/Ru9b+Y4oTOX6lUyp9 1fllwkIVQxlBTs1OZVU3E6g96MI0pa54Bpf3hHH/CiDRdwC9StDwTk+MfRxBGnKs6i 1Vl4dZDxf7l0oBa2Uyoj1TKRpIrk5NylkBzZXOs8= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Suzuki K Poulose Subject: [PATCH v20 16/22] KVM: arm64: CCA: Add bare minimal S2 operations for Realm Date: Thu, 24 Sep 2026 17:04:58 +0100 Message-ID: <20260924160504.853911-17-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add bare minimal MMU operation hooks for Realms. The mem_abort handling is chosen as the default KVM variant. However this cannot be reached for Realms yet and we would need real RMI command support to make it fully functional. RMM takes care of the TLB flushing as required, when the Stage2 is modified. So host doesn't need to do anything explicitly. RMM doesn't support access flags for the stage2, even for the shared IPA. Signed-off-by: Suzuki K Poulose --- arch/arm64/kvm/mmu.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 8f21652d3625c..1d2265801e7aa 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -180,6 +180,12 @@ static int kvm_vm_flush_remote_tlbs(struct kvm *kvm) return 0; } =20 +static int realm_vm_flush_remote_tlbs(struct kvm *kvm) +{ + /* Nothing to do here, RMM takes care of this */ + return 0; +} + /** * kvm_arch_flush_remote_tlbs() - flush all VM TLB entries for v7/8 * @kvm: pointer to kvm structure. @@ -210,6 +216,13 @@ static int kvm_vm_flush_remote_tlbs_range(struct kvm *= kvm, return 0; } =20 +static int realm_vm_flush_remote_tlbs_range(struct kvm *kvm, + gfn_t gfn, u64 nr_pages) +{ + /* Nothing to do here, RMM takes care of this */ + return 0; +} + int kvm_arch_flush_remote_tlbs_range(struct kvm *kvm, gfn_t gfn, u64 nr_pages) { @@ -2880,6 +2893,17 @@ static const struct kvm_vm_s2_ops kvm_default_vm_s2_= ops =3D { .vm_mem_abort =3D kvm_vm_mem_abort, }; =20 +static const struct kvm_vm_s2_ops realm_vm_s2_ops =3D { + .vm_flush_remote_tlbs =3D realm_vm_flush_remote_tlbs, + .vm_flush_remote_tlbs_range =3D realm_vm_flush_remote_tlbs_range, + .vm_mem_abort =3D kvm_vm_mem_abort, + /* + * Not supported for Realms + * .vm_age_gfn =3D realm_vm_age_gfn, + * .vm_test_age_gfn =3D realm_vm_test_age_gfn, + */ +}; + #define KVM_VM_S2_OPS(flavor, ops) \ [flavor] =3D ops static const struct kvm_vm_s2_ops *arm64_vm_s2_ops[] =3D { --=20 2.43.0 From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BEF904AA586; Thu, 24 Sep 2026 16:06:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790265998; cv=none; b=lwM79sZkqA+jSvdXjubQhaumuqC4ZQTy5/OM18KP5mTY+c3rkqS9L3Q41KUkiaH6jT9mPuNRX84UV6ghNOCT2f6uBV0pd0HuA18wgwecfqMWRZ1k+tZgxg//62jxPcDeJWfxoMrNtACkAnetw6ACjkAfsBoxOU19qSGBQdIxJ08= ARC-Message-Signature: i=1; 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Thu, 24 Sep 2026 09:06:32 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id F20F83F86C; Thu, 24 Sep 2026 09:06:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790265996; bh=BM89Q9V6ocI5DXYHAW82EU89jCBnsdhkyTNrWtCCZCY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WtqhBJeq3NM182+Wl9zn6MmWbh5D/c18CDNgFixTtrt0fkbueLz53dgq8Fq+/zWlb zaitDW+WCEtacy4cEwbRd3ILU+yoxos8Gh7tuGc5lx8Axy/ng4AdST421AKup+vsnx 12/dqb++iDxXsbEDmXjF4q6M/ziwrNcxzB76EnEM= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Suzuki K Poulose Subject: [PATCH v20 17/22] KVM: arm64: CCA: Introduce Realms Date: Thu, 24 Sep 2026 17:04:59 +0100 Message-ID: <20260924160504.853911-18-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Steven Price Add foundational work for supporting Realms. - Add a new VM flavor. - At KVM init, check if the KVM can support Realms (though not functional = yet) and will be advertised by static key kvm_rmi_is_available. This will be turned on in a later patches, once we have all the bits and pieces ready. For now check if we are blessed with KVM_MODE_RMM. - Add realm specific tracking in kvm_arch. Since Realm and protected pKVM states are mutually exclusive, move them into a union. Please note that we cannot create Realm VMs yet. This requires further chan= ges to the UABI and core RMI driver support, which will come later. Reviewed-by: Jonathan Cameron Signed-off-by: Steven Price Co-developed-by: Suzuki K Poulose Signed-off-by: Suzuki K Poulose --- Changes since v16: * Share mutually exclusive pKVM and Realm per-VM storage in a union. * Move to the new VM flavor infrastructure, split bits out. Trimmed down * Move in Realm state and basic boiler plates Changes since v13: * Most of the init has been moved out of the 'kvm' directory so this is much more basic now. Changes since v12: * Drop check for 4k page size. Changes since v11: * Reword slightly the comments on the realm states. Changes since v10: * kvm_is_realm() no longer has a NULL check. * Rename from "rme" to "rmi" when referring to the RMM interface. * Check for RME (hardware) support before probing for RMI support. Changes since v8: * No need to guard kvm_init_rme() behind 'in_hyp_mode'. Changes since v6: * Improved message for an unsupported RMI ABI version. Changes since v5: * Reword "unsupported" message from "host supports" to "we want" to clarify that 'we' are the 'host'. Changes since v2: * Drop return value from kvm_init_rme(), it was always 0. * Rely on the RMM return value to identify whether the RSI ABI is compatible. --- arch/arm64/include/asm/kvm_emulate.h | 16 ++++++++ arch/arm64/include/asm/kvm_host.h | 18 +++++--- arch/arm64/include/asm/kvm_rmi.h | 61 ++++++++++++++++++++++++++++ arch/arm64/include/asm/virt.h | 1 + arch/arm64/kvm/Makefile | 2 +- arch/arm64/kvm/arm.c | 6 +++ arch/arm64/kvm/mmu.c | 1 + arch/arm64/kvm/rmi.c | 18 ++++++++ 8 files changed, 117 insertions(+), 6 deletions(-) create mode 100644 arch/arm64/include/asm/kvm_rmi.h create mode 100644 arch/arm64/kvm/rmi.c diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index a3c1928bdf743..d360a8b05b8bf 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -793,4 +793,20 @@ static inline void kvm_reset_vcpu_psci(struct kvm_vcpu= *vcpu, vcpu_set_reg(vcpu, 0, reset_state->r0); } =20 +static inline enum realm_state kvm_realm_state(struct kvm *kvm) +{ + return READ_ONCE(kvm->arch.realm.state); +} + +static inline void kvm_set_realm_state(struct kvm *kvm, + enum realm_state new_state) +{ + WRITE_ONCE(kvm->arch.realm.state, new_state); +} + +static inline bool kvm_realm_is_created(struct kvm *kvm) +{ + return kvm_vm_is_realm(kvm) && kvm_realm_state(kvm) !=3D REALM_STATE_NONE; +} + #endif /* __ARM64_KVM_EMULATE_H__ */ diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 4516594d90462..c60e1ee8d1644 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -27,6 +27,7 @@ #include #include #include +#include #include =20 #define __KVM_HAVE_ARCH_INTC_INITIALIZED @@ -334,6 +335,7 @@ enum kvm_arm_vm_flavor { VM_PKVM, /* Normal guests on pKVM */ MARKER(__VM_PROTECTED), VM_PROTECTED_PKVM, /* Protected VM */ + VM_REALM, /* CCA */ VM_FLAVOR_MAX }; =20 @@ -451,11 +453,14 @@ struct kvm_arch { /* Count the number of VNCR_EL2 TLBs */ atomic_t vncr_tlb_count; =20 - /* - * For an untrusted host VM, 'pkvm.handle' is used to lookup - * the associated pKVM instance in the hypervisor. - */ - struct kvm_protected_vm pkvm; + union { + /* + * For an untrusted host VM, 'pkvm.handle' is used to lookup + * the associated pKVM instance in the hypervisor. + */ + struct kvm_protected_vm pkvm; + struct realm realm; + }; =20 #ifdef CONFIG_PTDUMP_STAGE2_DEBUGFS /* Nested virtualization info */ @@ -1578,6 +1583,9 @@ struct kvm *kvm_arch_alloc_vm(void); #define kvm_vm_is_unprotected_pkvm(kvm) \ (is_protected_kvm_enabled() && ((kvm)->arch.vm_flavor =3D=3D VM_PKVM)) =20 +#define kvm_vm_is_realm(kvm) ((kvm)->arch.vm_flavor =3D=3D VM_REALM) +#define vcpu_is_rec(vcpu) kvm_vm_is_realm((vcpu)->kvm) + #define kvm_vm_hyp_is_distrusting(kvm) ((kvm)->arch.vm_flavor >=3D __VM_DI= STRUSTING_HYP) =20 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); diff --git a/arch/arm64/include/asm/kvm_rmi.h b/arch/arm64/include/asm/kvm_= rmi.h new file mode 100644 index 0000000000000..44f5c75a27b5b --- /dev/null +++ b/arch/arm64/include/asm/kvm_rmi.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023-2026 ARM Ltd. + */ + +#ifndef __ASM_KVM_RMI_H +#define __ASM_KVM_RMI_H + +/** + * enum realm_state - State of a Realm + * + * Mirrors the RMM's Realm lifecycle states where they are meaningful to K= VM, + * with REALM_STATE_DYING being a KVM-internal state used to prevent furth= er + * requests while teardown is in progress. KVM does not track REALM_SYSTEM= _OFF + * or REALM_ZOMBIE separately as they naturally lead to teardown. + */ +enum realm_state { + /** + * @REALM_STATE_NONE: + * Realm has not yet been created. rmi_realm_create() has not + * yet been called. + */ + REALM_STATE_NONE, + /** + * @REALM_STATE_NEW: + * Realm is under construction, rmi_realm_create() has been + * called, but it is not yet activated. Pages may be populated. + */ + REALM_STATE_NEW, + /** + * @REALM_STATE_ACTIVE: + * Realm has been created and is eligible for execution with + * rmi_rec_enter(). Pages may no longer be populated with + * rmi_data_create(). + */ + REALM_STATE_ACTIVE, + /** + * @REALM_STATE_DYING: + * Realm is in the process of being destroyed or has already been + * destroyed. + */ + REALM_STATE_DYING, + /** + * @REALM_STATE_DEAD: + * Realm has been destroyed. + */ + REALM_STATE_DEAD +}; + +/** + * struct realm - Additional per VM data for a Realm + * + * @state: The lifetime state machine for the realm + */ +struct realm { + enum realm_state state; +}; + +void kvm_init_rmi(void); + +#endif /* __ASM_KVM_RMI_H */ diff --git a/arch/arm64/include/asm/virt.h b/arch/arm64/include/asm/virt.h index b546703c3ab9a..92cec42952f42 100644 --- a/arch/arm64/include/asm/virt.h +++ b/arch/arm64/include/asm/virt.h @@ -87,6 +87,7 @@ void __hyp_reset_vectors(void); bool is_kvm_arm_initialised(void); =20 DECLARE_STATIC_KEY_FALSE(kvm_protected_mode_initialized); +DECLARE_STATIC_KEY_FALSE(kvm_rmi_is_available); =20 static inline bool is_pkvm_initialized(void) { diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile index 59612d2f277c1..ed3cf30eb06e7 100644 --- a/arch/arm64/kvm/Makefile +++ b/arch/arm64/kvm/Makefile @@ -16,7 +16,7 @@ CFLAGS_handle_exit.o +=3D -Wno-override-init kvm-y +=3D arm.o mmu.o mmio.o psci.o hypercalls.o pvtime.o \ inject_fault.o va_layout.o handle_exit.o config.o \ guest.o debug.o reset.o sys_regs.o stacktrace.o \ - vgic-sys-reg-v3.o fpsimd.o pkvm.o \ + vgic-sys-reg-v3.o fpsimd.o pkvm.o rmi.o \ arch_timer.o trng.o vmid.o emulate-nested.o nested.o at.o \ vgic/vgic.o vgic/vgic-init.o \ vgic/vgic-irqfd.o vgic/vgic-v2.o \ diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 8b1beddd80ea5..0e77f59ded6d9 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -42,6 +42,7 @@ #include #include #include +#include #include #include =20 @@ -112,6 +113,8 @@ long kvm_get_cap_for_kvm_ioctl(unsigned int ioctl, long= *ext) return -EINVAL; } =20 +DEFINE_STATIC_KEY_FALSE(kvm_rmi_is_available); + DECLARE_KVM_HYP_PER_CPU(unsigned long, kvm_hyp_vector); =20 DEFINE_PER_CPU(unsigned long, kvm_arm_hyp_stack_base); @@ -2237,6 +2240,7 @@ static const struct kvm_vcpu_ops *arm64_vcpu_ops[] = =3D { KVM_VCPU_OPS(VM_VHE, &vhe_vcpu_ops), KVM_VCPU_OPS(VM_PKVM, &pkvm_vcpu_ops), KVM_VCPU_OPS(VM_PROTECTED_PKVM, &pkvm_vcpu_ops), + KVM_VCPU_OPS(VM_REALM, &realm_vcpu_ops), }; =20 static void kvm_init_vcpu_ops(struct kvm_vcpu *vcpu) @@ -3190,6 +3194,8 @@ static __init int kvm_arm_init(void) =20 in_hyp_mode =3D is_kernel_in_hyp_mode(); =20 + kvm_init_rmi(); + if (cpus_have_final_cap(ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) || cpus_have_final_cap(ARM64_WORKAROUND_1508412)) kvm_info("Guests without required CPU erratum workarounds can deadlock s= ystem!\n" \ diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 1d2265801e7aa..bea252bf49f6a 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -2911,6 +2911,7 @@ static const struct kvm_vm_s2_ops *arm64_vm_s2_ops[] = =3D { KVM_VM_S2_OPS(VM_NVHE, &kvm_default_vm_s2_ops), KVM_VM_S2_OPS(VM_PKVM, &pkvm_vm_s2_ops), KVM_VM_S2_OPS(VM_PROTECTED_PKVM, &protected_pkvm_vm_s2_ops), + KVM_VM_S2_OPS(VM_REALM, &realm_vm_s2_ops), }; =20 static int kvm_vm_init_vm_s2_ops(struct kvm *kvm) diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c new file mode 100644 index 0000000000000..5ecc8b3498698 --- /dev/null +++ b/arch/arm64/kvm/rmi.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023-2026 ARM Ltd. + */ + +#include + +#include + +void kvm_init_rmi(void) +{ + if (kvm_get_mode() !=3D KVM_MODE_RMM) + return; + + /* TODO: Check if the RMI is available */ + + /* Future patch will enable static branch kvm_rmi_is_available */ +} --=20 2.43.0 From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 45B894BEE27; Thu, 24 Sep 2026 16:06:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790266003; cv=none; b=dExblgXWazfY47xj6XJmh0MqCsbPBgto/JBe+TshSkDV50PcBZK7v0esizPb6tiMl1G5FBwUIERzYJjgeAIW+gV/q1szgDMk8ytM5FFfMcvgopgIwvNcXcUMuZ+QP+WFKzUXKpb7OtfWKMgD3emoFfeLrZgvr0lunbwebTN2QCY= ARC-Message-Signature: i=1; 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Thu, 24 Sep 2026 09:06:36 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 654013F86C; Thu, 24 Sep 2026 09:06:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790266000; bh=qqIjAm5se+qNeiPgYmrOoah+WsJiOdR/osHb0Swv+J8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nDu7cat3hBgepiWbiMSkO3kfnWAYWqPsbHIYDWOKfPWjgvpVMpXzhxHYvT13Vjc18 xzo2b1WLRJ5740MBkNbq/FXR2fnvp+6Jq1Ll3IIvd4451VnlKLxdS5taIHyRxxhYGn 2E3D69CdxmjtXN46A6OK0dTJbpgsG4l9Sq5BaewU= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Suzuki K Poulose Subject: [PATCH v20 18/22] KVM: arm64: CCA: Don't expose unsupported capabilities for realm guests Date: Thu, 24 Sep 2026 17:05:00 +0100 Message-ID: <20260924160504.853911-19-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Limit the capabilities that are allowed for Realm VMs. Similarly block the vm_ioctls backed by the capabilities. Repurpose the kvm_pkvm_ioctl_allowed() to support both pKVM and Realm ioctls. Rename the helper to kvm_vm_ioctl_allowed() and move it into arch/arm64/kvm/arm.c. Also add a generic kvm_vm_ext_allowed() to handle pKVM and Realm capability filtering and route them accordingly. Signed-off-by: Suzuki K Poulose --- Changes since v18: * Bail out early for !pKVM && !Realm vms. Use kvm_vm_hyp_is_distrusting() * WARN_ON_ONCE(!kvm), we are only called from kvm_arch_vm_ioctl() with a valid kvm instance. * Move the kvm_realm_ext_allowed() to asm/kvm_rmi.h - Fuad * Rename kvm_arch_vm_*allowed =3D> kvm_vm_*_allowed - Fuad Changes since v17: * Drop superfluous !kvm check from kvm_vm_ioctl_enable_cap() - Sashiko * Drop KVM_CAP_CREATE_IRQCHIP, as we don't support VGIC_V2 for Realms * Filter out the vm_ioctls that are based on blocked cap. * Repurpose the pkvm plumbing for filtering the caps and ioctl to generic and plumb the Realm support in Changes since v13: * Add missing check in kvm_vm_ioctl_enable_cap(). Changes since v10: * Add a kvm_realm_ext_allowed() function which limits which extensions are exposed to an allowlist. This removes the need for special casing various extensions. Changes since v7: * Remove the helper functions and inline the kvm_is_realm() check with a ternary operator. * Rewrite the commit message to explain this patch. --- arch/arm64/include/asm/kvm_pkvm.h | 19 ------------ arch/arm64/include/asm/kvm_rmi.h | 23 +++++++++++++++ arch/arm64/kvm/arm.c | 49 +++++++++++++++++++++++++++++-- 3 files changed, 69 insertions(+), 22 deletions(-) diff --git a/arch/arm64/include/asm/kvm_pkvm.h b/arch/arm64/include/asm/kvm= _pkvm.h index e4ea80711bec6..1bc4fe2726e9b 100644 --- a/arch/arm64/include/asm/kvm_pkvm.h +++ b/arch/arm64/include/asm/kvm_pkvm.h @@ -53,25 +53,6 @@ static inline bool kvm_pkvm_ext_allowed(struct kvm *kvm,= long ext) } } =20 -/* - * Check whether the KVM VM IOCTL is allowed in pKVM. - * - * Certain features are allowed only for non-protected VMs in pKVM, which = is why - * this takes the VM (kvm) as a parameter. - */ -static inline bool kvm_pkvm_ioctl_allowed(struct kvm *kvm, unsigned int io= ctl) -{ - long ext; - int r; - - r =3D kvm_get_cap_for_kvm_ioctl(ioctl, &ext); - - if (WARN_ON_ONCE(r < 0)) - return false; - - return kvm_pkvm_ext_allowed(kvm, ext); -} - extern struct memblock_region kvm_nvhe_sym(hyp_memory)[]; extern unsigned int kvm_nvhe_sym(hyp_memblock_nr); =20 diff --git a/arch/arm64/include/asm/kvm_rmi.h b/arch/arm64/include/asm/kvm_= rmi.h index 44f5c75a27b5b..6b8b9ee9ea245 100644 --- a/arch/arm64/include/asm/kvm_rmi.h +++ b/arch/arm64/include/asm/kvm_rmi.h @@ -6,6 +6,8 @@ #ifndef __ASM_KVM_RMI_H #define __ASM_KVM_RMI_H =20 +#include + /** * enum realm_state - State of a Realm * @@ -58,4 +60,25 @@ struct realm { =20 void kvm_init_rmi(void); =20 +static inline bool kvm_realm_ext_allowed(long ext) +{ + switch (ext) { + case KVM_CAP_IRQCHIP: + case KVM_CAP_ARM_PSCI: + case KVM_CAP_ARM_PSCI_0_2: + case KVM_CAP_NR_VCPUS: + case KVM_CAP_MAX_VCPUS: + case KVM_CAP_MAX_VCPU_ID: + case KVM_CAP_MSI_DEVID: + case KVM_CAP_ARM_VM_IPA_SIZE: + case KVM_CAP_ARM_SVE: + case KVM_CAP_ONE_REG: + case KVM_CAP_ARM_PTRAUTH_ADDRESS: + case KVM_CAP_ARM_PTRAUTH_GENERIC: + case KVM_CAP_SYNC_MMU: + return true; + } + return false; +} + #endif /* __ASM_KVM_RMI_H */ diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 0e77f59ded6d9..106b52e556e20 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -136,6 +136,49 @@ int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) return kvm_vcpu_exiting_guest_mode(vcpu) =3D=3D IN_GUEST_MODE; } =20 +static inline bool kvm_vm_ext_allowed(struct kvm *kvm, long ext) +{ + /* + * We could be called with kvm as NULL, so can't use kvm_vm_* for pKVM + * flavors + */ + if (is_protected_kvm_enabled()) + return kvm_pkvm_ext_allowed(kvm, ext); + else if (kvm && kvm_vm_is_realm(kvm)) + return kvm_realm_ext_allowed(ext); + else + return true; +} + +/* + * Check whether the KVM VM IOCTL is allowed. For pKVM and Realm VMs, cert= ain + * ioctls are not allowed. Further, certain features are allowed only for + * non-protected VMs in pKVM. + */ +static inline bool kvm_vm_ioctl_allowed(struct kvm *kvm, unsigned int ioct= l) +{ + long ext; + int r; + + /* + * We are guaranteed to be called with a valid kvm instance, as the + * only caller is kvm_arch_vm_ioctl(). Catch any deviations, as we + * rely on the kvm instance below. + */ + if (WARN_ON_ONCE(!kvm)) + return false; + + /* Cover both pKVM host and Realm VMs */ + if (!kvm_vm_hyp_is_distrusting(kvm)) + return true; + + r =3D kvm_get_cap_for_kvm_ioctl(ioctl, &ext); + if (WARN_ON_ONCE(r < 0)) + return false; + + return kvm_vm_ext_allowed(kvm, ext); +} + int kvm_vm_ioctl_enable_cap(struct kvm *kvm, struct kvm_enable_cap *cap) { @@ -144,7 +187,7 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm, if (cap->flags) return -EINVAL; =20 - if (is_protected_kvm_enabled() && !kvm_pkvm_ext_allowed(kvm, cap->cap)) + if (!kvm_vm_ext_allowed(kvm, cap->cap)) return -EINVAL; =20 switch (cap->cap) { @@ -403,7 +446,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long = ext) { int r; =20 - if (is_protected_kvm_enabled() && !kvm_pkvm_ext_allowed(kvm, ext)) + if (!kvm_vm_ext_allowed(kvm, ext)) return 0; =20 switch (ext) { @@ -2144,7 +2187,7 @@ int kvm_arch_vm_ioctl(struct file *filp, unsigned int= ioctl, unsigned long arg) void __user *argp =3D (void __user *)arg; struct kvm_device_attr attr; =20 - if (is_protected_kvm_enabled() && !kvm_pkvm_ioctl_allowed(kvm, ioctl)) + if (!kvm_vm_ioctl_allowed(kvm, ioctl)) return -EINVAL; =20 switch (ioctl) { --=20 2.43.0 From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 88ED14AAC5F; Thu, 24 Sep 2026 16:06:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790266008; cv=none; b=u+jcJLOB5H8ocP1fGRQs+4mwWcr4hWoxLo0xuux68Wi3Gxf/xT9NJ+Tiiab2tYjjzTimnVjy/X0etfGEoI3Tl/mbEVeuEU3kVj8juc3AkCS/fXOB6RFSgLVFZtMjc0Js1x1i/QVKyMUAWcxUUfZgoR9c9XSYd7XYfnNY2WAz2Y8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790266008; c=relaxed/simple; bh=1DYRIPe8PKoi5a5tSzSos3MNlYuYMYyYfWo3uNo+uDk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kNMmZFEWk7cGNSgC7kxeMDWzi7d1mjJ4eK2oE1RMMqJDN+V37BGa9BGsb2H/dmUbzd88wGw5CsrfuwVtfrWPezHsNvMTws4eGbDngRyarwp0za1tBXuKRm2oaJg4e7aaUAeyHQwoKtrlJE3BVW+85jVlPX3pO/vF1Tpk2S5QzyM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=ILdBX9Bp; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="ILdBX9Bp" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 555781EDB; Thu, 24 Sep 2026 09:06:41 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B34573F86C; Thu, 24 Sep 2026 09:06:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790266004; bh=1DYRIPe8PKoi5a5tSzSos3MNlYuYMYyYfWo3uNo+uDk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ILdBX9BpTIh+oUiiBaKCiAb+ZwBfDuI3rKINORMCNIssuj6sl0+xbySKHrSSSTSku aSNvR0h1OXbbamKGJ4LYWYZWT11lP+Ys+fIGibACCerX5URmZCH06BNHAbtILOkpY9 PQ2x5RdGXYaI7KEs1E1CPVeUHO6TCzXi70Y9zZL4= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Suzuki K Poulose Subject: [PATCH v20 19/22] KVM: arm64: CCA: WARN on injected undef exceptions Date: Thu, 24 Sep 2026 17:05:01 +0100 Message-ID: <20260924160504.853911-20-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Steven Price The RMM doesn't allow injection of a undefined exception into a realm guest. Add a WARN to catch if this ever happens. Reviewed-by: Jonathan Cameron Signed-off-by: Steven Price Signed-off-by: Suzuki K Poulose --- Changes since v15: * Switch to KVM_BUG() to mark the VM as bugged as well. Changes since v6: * if (x) WARN(1, ...) makes no sense, just WARN(x, ...)! --- arch/arm64/kvm/inject_fault.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c index d6c4fc16f8795..d61a3ff04fabb 100644 --- a/arch/arm64/kvm/inject_fault.c +++ b/arch/arm64/kvm/inject_fault.c @@ -317,6 +317,7 @@ void kvm_inject_size_fault(struct kvm_vcpu *vcpu) */ void kvm_inject_undefined(struct kvm_vcpu *vcpu) { + KVM_BUG(vcpu_is_rec(vcpu), vcpu->kvm, "Unexpected undefined exception inj= ection to REC"); if (vcpu_el1_is_32bit(vcpu)) inject_undef32(vcpu); else --=20 2.43.0 From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 328064BF941; Thu, 24 Sep 2026 16:06:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790266012; cv=none; b=izk+keW4//jd8F42EL7s9HqvF2sC+tBhd6dM0jt3YQpgNoGfmXpsI7CB21lDL7i6lDaZdIpyqulSzdF+zxmin4XxY/eyCLu48RIf9AEIJPOo1e5F2wJGHZHhgUAoj8PPUEl7Ck8o+I/OrVLvbCwtf8hguK9xnrHs9WsVunr+3KM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790266012; c=relaxed/simple; bh=AOVF4a7/lSQM973EMT8NHAVecCRsdK6HnC8EakUQ6v8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=V0jJpiqoWr+7+lC3m0n2h2JbgjDWVwerRuvtNt3v1od2Po/bfpAYsnaRZiKbZQvpC/XjiLY7ihs10w8wcSLj+BjnyPzDXZi8chROosNA8csqsjPlzOP7wldwKZj++hNI4qsIJdDxEkqwbjgdg8OLMkIhhcm4QBzVbez12KfJtBQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=c0xQePF8; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="c0xQePF8" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0B7E01E7D; Thu, 24 Sep 2026 09:06:46 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 336423F86C; Thu, 24 Sep 2026 09:06:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790266009; bh=AOVF4a7/lSQM973EMT8NHAVecCRsdK6HnC8EakUQ6v8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=c0xQePF8K8BIkkwjEMa/T14N2DrxNqAl1tYgapuew6Ngvufv5IkFv8BcKeayZV2Uy zvbP8yAPIp9oYCYJPORP8lsd5V9TAhDkPv12RVRZTd8VXSsqgUQUOOaKbRwUKAFCyr lfdMK3i5Pq6K7r+a+AOKoM0YUmRAFzEiG/tWMVdw= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Suzuki K Poulose Subject: [PATCH v20 20/22] KVM: arm64: CCA: Support timers in realm RECs Date: Thu, 24 Sep 2026 17:05:02 +0100 Message-ID: <20260924160504.853911-21-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Steven Price The RMM keeps track of the timer while the realm REC is running, but on exit to the normal world KVM is responsible for handling the timers. A later patch adds the support for propagating the timer values from the exit data structure and making sure the values are in sync for KVM. Also, RMM doesn't support injecting virtual interrupts backed by Physical interrupts. So, use the existing software resampling mechanims for Realm timer interrupts. Signed-off-by: Steven Price Signed-off-by: Suzuki K Poulose --- arch/arm64/kvm/arch_timer.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c index a45845f4ae4ea..428709f499205 100644 --- a/arch/arm64/kvm/arch_timer.c +++ b/arch/arm64/kvm/arch_timer.c @@ -56,11 +56,25 @@ static unsigned long kvm_arch_timer_get_irq_flags(void) return kvm_vgic_global_state.no_hw_deactivation ? VGIC_IRQ_SW_RESAMPLE : = 0; } =20 +static unsigned long kvm_realm_timer_get_irq_flags(void) +{ + /* + * RMI_REC_ENTER rejects LRs with the HW bit set, so use the existing + * software resampling mechanism for Realm timer interrupts. + */ + return VGIC_IRQ_SW_RESAMPLE; +} + static const struct irq_ops arch_timer_irq_ops =3D { .get_flags =3D kvm_arch_timer_get_irq_flags, .get_input_level =3D kvm_arch_timer_get_input_level, }; =20 +static const struct irq_ops realm_timer_irq_ops =3D { + .get_flags =3D kvm_realm_timer_get_irq_flags, + .get_input_level =3D kvm_arch_timer_get_input_level, +}; + static const struct irq_ops arch_timer_irq_ops_vgic_v5 =3D { .get_input_level =3D kvm_arch_timer_get_input_level, .queue_irq_unlock =3D vgic_v5_ppi_queue_irq_unlock, @@ -1617,8 +1631,12 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) =20 get_timer_map(vcpu, &map); =20 - ops =3D vgic_is_v5(vcpu->kvm) ? &arch_timer_irq_ops_vgic_v5 : - &arch_timer_irq_ops; + if (vcpu_is_rec(vcpu)) + ops =3D &realm_timer_irq_ops; + else if (vgic_is_v5(vcpu->kvm)) + ops =3D &arch_timer_irq_ops_vgic_v5; + else + ops =3D &arch_timer_irq_ops; =20 for (int i =3D 0; i < nr_timers(vcpu); i++) kvm_vgic_set_irq_ops(vcpu, timer_irq(vcpu_get_timer(vcpu, i)), ops); --=20 2.43.0 From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 35DC94C10C9; Thu, 24 Sep 2026 16:06:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790266016; cv=none; b=sDNSQs+N+FvJxIY9EQ8ynExLpLMEkTrwA/cu309aubLanZr6y5VAs/pi9aoT8VALmNkidsOKBm2cU5B4/74ejXttGqzyEgGGcnAyDjY4UDcdu4zOXN5vWm2gEo4My27af88hMqKso+FsFcaoKWas/JSMA3r3QrFGxBsOOKUgcx4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790266016; c=relaxed/simple; bh=TFdgNv3iG+ctrPX/QQJPXB7nuYKqem8iJ6RlcQWAE28=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rTr8Ii+fpCjEI0l+Dky4epW7NV8ucpCCevsGYGGJlyulYuVgMzloPjevoN9X7qNvCCvTrxHDRr3VoYxnA+mj4eO6jP6x1HUtLLOftsT2FynWUONJIP+eOtPcCGsm67rnd64mYXAJwnhZk05DwZ8kinhr5v9sK5q/qwCKRJmyZ6M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=caQmpVfc; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="caQmpVfc" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2C4001E8D; Thu, 24 Sep 2026 09:06:51 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D4A083F86C; Thu, 24 Sep 2026 09:06:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790266014; bh=TFdgNv3iG+ctrPX/QQJPXB7nuYKqem8iJ6RlcQWAE28=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=caQmpVfc6PFQmwawXUg2rhLqAznOzYT+E1IXGsXXzE9xr/5LMl+d15AWUTKgoBCbH AZGp5RF6vxrK1B6OvMZC+hTHFXfxVn3hq9Wwr9C4eymrO4AU7saINl8VRrugjjb8r7 iMDEhRBEGNrZ9V+KaCw2yv4XBvjkuWm2xkl8otjA= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Jean-Philippe Brucker , Suzuki K Poulose Subject: [PATCH v20 21/22] KVM: arm64: CCA: Expose SVE VL register before VCPU finalization Date: Thu, 24 Sep 2026 17:05:03 +0100 Message-ID: <20260924160504.853911-22-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jean-Philippe Brucker Userspace must configure the SVE vector length before the Realm is created (as it is part of the parameter for Realm creation), but the Realm VCPUs cannot be finalized until after the Realm Descriptor has been created. KVM_GET_REG_LIST currently rejects the unfinalized VCPUs, which prevents the userspace from discovering and configuring the VLs for the Realm. Allow KVM_GET_REG_LIST for unfinalized RECs and make the SVE register enumeration handle the unfinalized case explicitly. i.e., only expose KVM_REG_ARM64_SVE_VLS before SVE is finalized. One adverse side effect of this change is that a KVM_GET_REG_LIST call that only probes for the array size will now succeed even if SVE is not finalized, but that seems harmless since the following KVM_GET_REG_LIST with the full array will fail. Signed-off-by: Jean-Philippe Brucker Signed-off-by: Steven Price Signed-off-by: Suzuki K Poulose --- Changes since v17: - Rewrite the commit description to clearly describe the purpose --- arch/arm64/kvm/arm.c | 15 ++++++++++++++- arch/arm64/kvm/guest.c | 10 +++++----- 2 files changed, 19 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 106b52e556e20..fbd5784e481b6 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -2002,6 +2002,19 @@ static int kvm_arm_vcpu_set_events(struct kvm_vcpu *= vcpu, return __kvm_arm_vcpu_set_events(vcpu, events); } =20 +/* + * Realm VCPUs can be finalized only after the Realm descriptor is created. + * But in order to seal the SVE VL, we need to allow the userspace to read= /write + * to the SVE_VL, before everything is finalized. + * Allow the register list for RECs before the VCPUs are finalized. + */ +static bool kvm_arm_vcpu_reg_list_allowed(struct kvm_vcpu *vcpu) +{ + if (kvm_arm_vcpu_is_finalized(vcpu)) + return true; + return vcpu_is_rec(vcpu); +} + long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) { @@ -2057,7 +2070,7 @@ long kvm_arch_vcpu_ioctl(struct file *filp, break; =20 r =3D -EPERM; - if (!kvm_arm_vcpu_is_finalized(vcpu)) + if (!kvm_arm_vcpu_reg_list_allowed(vcpu)) break; =20 r =3D -EFAULT; diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index b01d6622b8720..c3ca369882273 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -598,8 +598,8 @@ static unsigned long num_sve_regs(const struct kvm_vcpu= *vcpu) if (!vcpu_has_sve(vcpu)) return 0; =20 - /* Policed by KVM_GET_REG_LIST: */ - WARN_ON(!kvm_arm_vcpu_sve_finalized(vcpu)); + if (!kvm_arm_vcpu_sve_finalized(vcpu)) + return 1; /* KVM_REG_ARM64_SVE_VLS */ =20 return slices * (SVE_NUM_PREGS + SVE_NUM_ZREGS + 1 /* FFR */) + 1; /* KVM_REG_ARM64_SVE_VLS */ @@ -616,9 +616,6 @@ static int copy_sve_reg_indices(const struct kvm_vcpu *= vcpu, if (!vcpu_has_sve(vcpu)) return 0; =20 - /* Policed by KVM_GET_REG_LIST: */ - WARN_ON(!kvm_arm_vcpu_sve_finalized(vcpu)); - /* * Enumerate this first, so that userspace can save/restore in * the order reported by KVM_GET_REG_LIST: @@ -628,6 +625,9 @@ static int copy_sve_reg_indices(const struct kvm_vcpu *= vcpu, return -EFAULT; ++num_regs; =20 + if (!kvm_arm_vcpu_sve_finalized(vcpu)) + return num_regs; + for (i =3D 0; i < slices; i++) { for (n =3D 0; n < SVE_NUM_ZREGS; n++) { reg =3D KVM_REG_ARM64_SVE_ZREG(n, i); --=20 2.43.0 From nobody Thu Sep 24 20:37:27 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D22264C10C9; Thu, 24 Sep 2026 16:06:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790266022; cv=none; b=rgd0oQBcM3upZqYOdX6Cajn9M5RTbCXPSE0Uw/FCebblzhmYL9I5ysbO32Z2WOjoUDa4wegv46vUX4yQHHGMbfgqPCvYrT2Li9Qf34o+zoJTE4qprZMOzAHczPXVgW+s1cpYF8XEcQZegaNrslSBZFLPiVISCRWK0DEI1kv2EGA= ARC-Message-Signature: i=1; a=rsa-sha256; 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Thu, 24 Sep 2026 09:06:55 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0F3143F86C; Thu, 24 Sep 2026 09:06:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790266019; bh=R3BsMhC0mgk8LVwQeMdpKSdNGy7KjowhtkEPEVBEHiM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Jmac1LN2HajPWG9/HdjG1dbXidngcnNiWri1MgQAuMcIb6gtBG/GyXnxCil6GJUCr /qBMPK/a0dTbtD3yTTcwR6UzNrBWJ5jYlnhiZwe5KPwsEL5FFPegdnHc+w16OVM60i 3XFw3VqFRbFzXXVNfuKEbRe3QGI/+pyBjEtyKrCE= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com, Jean-Philippe Brucker , Suzuki K Poulose Subject: [PATCH v20 22/22] KVM: arm64: CCA: Control user register access for Realms Date: Thu, 24 Sep 2026 17:05:04 +0100 Message-ID: <20260924160504.853911-23-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924160504.853911-1-suzuki.poulose@arm.com> References: <20260924160504.853911-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jean-Philippe Brucker The RMM restricts the access to the register states that the host can read/modify for a given Realm. e.g., At VCPU creation, can modify GPRS (x0-x30) and PC. While servicing SMCCC calls via RSI_HOST_CALL or servicing PSCI requests. MMIO emulation in the unprotected space. Additionally we use the sysreg configuration to advertise/configure the following Realm parameters, which are required before the Realm Descriptor :w is created: - SVE Vector Length - Number of HW Breakpoints/Watchpoints - PMU Counters. Thus KVM also additionally allows access to ID_AA64DFR0_EL1 and SVE_VLS for the configuration of Realm creation parameters. We don't support PMUs for the Realm VMs yet, so PMCR is not exposed. The RMM makes similar restrictions for reading of the guest's registers (this is *confidential* compute after all), however we don't impose the restriction here. This allows the VMM to read (stale) values from the registers which might be useful to read back the initial values even if the RMM doesn't provide the latest version. For migration of a realm VM, a new interface will be needed so that the VMM can receive an (encrypted) blob of the VM's state. Reflect the above in KVM_GET_REG_LIST, KVM_SET_ONE_REG calls. Signed-off-by: Jean-Philippe Brucker Co-developed-by: Steven Price Signed-off-by: Steven Price Co-developed-by: Suzuki K Poulose Signed-off-by: Suzuki K Poulose --- Changes since v18: - Don't expose PMCR_EL0 to the userspace now, we could do that when we support PMU - Fix check patch warnings Changes since v17: - Merge related changes into one single patch for the user set/get regist= ers I have retained the Review tags, as the code hasn't changed, just the p= atches were merged into a single one with the same tags. - Limit KVM_GET_REG_LIST to the allowed CORE registers. --- arch/arm64/kvm/guest.c | 63 +++++++++++++++++++++++++++++++++++++ arch/arm64/kvm/hypercalls.c | 4 +-- arch/arm64/kvm/sys_regs.c | 28 +++++++++++++---- 3 files changed, 87 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index c3ca369882273..ffe3f5ce4b3cf 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -73,6 +73,25 @@ static u64 core_reg_offset_from_id(u64 id) return id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE); } =20 +static bool kvm_realm_validate_core_reg(u64 off) +{ + /* + * Note that GPRs can only sometimes be controlled by the VMM. + * For PSCI only X0-X6 are used, higher registers are ignored (restored + * from the REC). + * For HOST_CALL all of X0-X30 are copied to the RsiHostCall structure. + * For emulated MMIO X0 is always used. + * PC can only be set before the realm is activated. + */ + switch (off) { + case KVM_REG_ARM_CORE_REG(regs.regs[0]) ... + KVM_REG_ARM_CORE_REG(regs.regs[30]): + case KVM_REG_ARM_CORE_REG(regs.pc): + return true; + } + return false; +} + static int core_reg_size_from_offset(const struct kvm_vcpu *vcpu, u64 off) { int size; @@ -553,6 +572,9 @@ static int copy_core_reg_indices(const struct kvm_vcpu = *vcpu, u64 reg =3D KVM_REG_ARM64 | KVM_REG_ARM_CORE | i; int size =3D core_reg_size_from_offset(vcpu, i); =20 + if (vcpu_is_rec(vcpu) && !kvm_realm_validate_core_reg(i)) + continue; + if (size < 0) continue; =20 @@ -598,6 +620,9 @@ static unsigned long num_sve_regs(const struct kvm_vcpu= *vcpu) if (!vcpu_has_sve(vcpu)) return 0; =20 + if (kvm_vm_is_realm(vcpu->kvm)) + return 1; /* KVM_REG_ARM64_SVE_VLS */ + if (!kvm_arm_vcpu_sve_finalized(vcpu)) return 1; /* KVM_REG_ARM64_SVE_VLS */ =20 @@ -625,6 +650,10 @@ static int copy_sve_reg_indices(const struct kvm_vcpu = *vcpu, return -EFAULT; ++num_regs; =20 + /* For Realms only support SVE_VLS */ + if (kvm_vm_is_realm(vcpu->kvm)) + return num_regs; + if (!kvm_arm_vcpu_sve_finalized(vcpu)) return num_regs; =20 @@ -705,6 +734,11 @@ int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struc= t kvm_one_reg *reg) if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 !=3D KVM_REG_ARM64 >> 32) return -EINVAL; =20 + /* + * We don't filter out the register reads for Realms, like we do for + * the user writes. We expose junk data for the VMM instead of + * denying the requests. + */ switch (reg->id & KVM_REG_ARM_COPROC_MASK) { case KVM_REG_ARM_CORE: return get_core_reg(vcpu, reg); case KVM_REG_ARM_FW: @@ -716,12 +750,41 @@ int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const stru= ct kvm_one_reg *reg) return kvm_arm_sys_reg_get_reg(vcpu, reg); } =20 +#define KVM_REG_ARM_ID_AA64DFR0_EL1 ARM64_SYS_REG(3, 0, 0, 5, 0) +/* + * The RMI ABI only enables setting some GPRs and PC. The selection of GPRs + * that are available depends on the Realm state and the reason for the la= st + * exit. All other registers are reset to architectural or otherwise defi= ned + * reset values by the RMM, except for a few configuration fields that + * correspond to Realm parameters. + */ +static bool validate_realm_set_reg(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg) +{ + if ((reg->id & KVM_REG_ARM_COPROC_MASK) =3D=3D KVM_REG_ARM_CORE) { + u64 off =3D core_reg_offset_from_id(reg->id); + + return kvm_realm_validate_core_reg(off); + } + + switch (reg->id) { + case KVM_REG_ARM_ID_AA64DFR0_EL1: + case KVM_REG_ARM64_SVE_VLS: + return true; + } + + return false; +} + int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) { /* We currently use nothing arch-specific in upper 32 bits */ if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 !=3D KVM_REG_ARM64 >> 32) return -EINVAL; =20 + if (kvm_vm_is_realm(vcpu->kvm) && !validate_realm_set_reg(vcpu, reg)) + return -EINVAL; + switch (reg->id & KVM_REG_ARM_COPROC_MASK) { case KVM_REG_ARM_CORE: return set_core_reg(vcpu, reg); case KVM_REG_ARM_FW: diff --git a/arch/arm64/kvm/hypercalls.c b/arch/arm64/kvm/hypercalls.c index b11b8821c9fbc..2b1e6fdeb4d5c 100644 --- a/arch/arm64/kvm/hypercalls.c +++ b/arch/arm64/kvm/hypercalls.c @@ -414,14 +414,14 @@ void kvm_arm_teardown_hypercalls(struct kvm *kvm) =20 int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu) { - return ARRAY_SIZE(kvm_arm_fw_reg_ids); + return vcpu_is_rec(vcpu) ? 0 : ARRAY_SIZE(kvm_arm_fw_reg_ids); } =20 int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindice= s) { int i; =20 - for (i =3D 0; i < ARRAY_SIZE(kvm_arm_fw_reg_ids); i++) { + for (i =3D 0; i < kvm_arm_get_fw_num_regs(vcpu); i++) { if (put_user(kvm_arm_fw_reg_ids[i], uindices++)) return -EFAULT; } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 44aae52c473d7..47ebde943a09e 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -5638,18 +5638,18 @@ int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, = const struct kvm_one_reg *reg sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); } =20 -static unsigned int num_demux_regs(void) +static inline unsigned int num_demux_regs(struct kvm_vcpu *vcpu) { - return CSSELR_MAX; + return vcpu_is_rec(vcpu) ? 0 : CSSELR_MAX; } =20 -static int write_demux_regids(u64 __user *uindices) +static int write_demux_regids(struct kvm_vcpu *vcpu, u64 __user *uindices) { u64 val =3D KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; unsigned int i; =20 val |=3D KVM_REG_ARM_DEMUX_ID_CCSIDR; - for (i =3D 0; i < CSSELR_MAX; i++) { + for (i =3D 0; i < num_demux_regs(vcpu); i++) { if (put_user(val | i, uindices)) return -EFAULT; uindices++; @@ -5693,11 +5693,27 @@ static bool copy_reg_to_user(const struct sys_reg_d= esc *reg, u64 __user **uind) return true; } =20 +static inline bool kvm_realm_sys_reg_hidden_user(const struct kvm_vcpu *vc= pu, + u64 reg) +{ + if (!vcpu_is_rec(vcpu)) + return false; + + switch (reg) { + case SYS_ID_AA64DFR0_EL1: + return false; + } + return true; +} + static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, u64 __user **uind, unsigned int *total) { + if (kvm_realm_sys_reg_hidden_user(vcpu, reg_to_encoding(rd))) + return 0; + /* * Ignore registers we trap but don't save, * and for which no custom user accessor is provided. @@ -5735,7 +5751,7 @@ static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 _= _user *uind) =20 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) { - return num_demux_regs() + return num_demux_regs(vcpu) + walk_sys_regs(vcpu, (u64 __user *)NULL); } =20 @@ -5748,7 +5764,7 @@ int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcp= u, u64 __user *uindices) return err; uindices +=3D err; =20 - return write_demux_regids(uindices); + return write_demux_regids(vcpu, uindices); } =20 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \ --=20 2.43.0