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charset="utf-8" Add HSMP client support for the Family 1Ah client platforms, Models 80h-8Fh and E0h-E3h. These parts speak the Ryzen Master SMC (RMSMC) message set instead of the server HSMP messages, and probe via ACPI _CRS/_DSD like a server socket. Add the client message set to the UAPI header. Introduce struct hsmp_plat_desc to select the test message and protocol-version message at runtime, based on the ACPI-reported PM profile (is_client_platform()) rather than a fixed set of family/model ranges. The client set has no per-message descriptor table. validate_message() and hsmp_ioctl_msg() therefore skip msg_id range validation, array_index_nospec() sanitization, and the /dev/hsmp GET/SET fd-mode gate for client messages, leaving msg_id validity to firmware's response status; validate_message() still bounds client num_args and response_sz to HSMP_CLIENT_MAX_MSG_LEN. Server platforms keep every check, and get_msg_desc() now also enforces a lower msg_id bound there. Register /dev/hsmp at 0600 on client platforms, since hsmp_ioctl_msg() has no GET/SET gate there and any opener could otherwise issue destructive SET messages; server platforms keep 0644 because that gate still applies. Add hsmp_msg_response_sz(), returning the descriptor table entry on server and the client protocol max otherwise, used by hsmp_cache_proto_ver() since firmware returns only args[0] for client. validate_message() and hsmp_ioctl_msg() distinguish the two sets via the already-resolved hsmp_plat_desc/ hsmp_msg_desc pointers, not a second is_client_platform() call. Document the client models in amd_hsmp.rst. Signed-off-by: Muralidhara M K Reviewed-by: Mario Limonciello (AMD) --- Documentation/arch/x86/amd_hsmp.rst | 10 +- arch/x86/include/uapi/asm/amd_hsmp.h | 154 ++++++++++++++++++ drivers/platform/x86/amd/hsmp/hsmp.c | 235 ++++++++++++++++++++------- drivers/platform/x86/amd/hsmp/hsmp.h | 23 +++ 4 files changed, 364 insertions(+), 58 deletions(-) diff --git a/Documentation/arch/x86/amd_hsmp.rst b/Documentation/arch/x86/a= md_hsmp.rst index fa1fc240e212..b95f09945193 100644 --- a/Documentation/arch/x86/amd_hsmp.rst +++ b/Documentation/arch/x86/amd_hsmp.rst @@ -8,6 +8,13 @@ Newer Fam19h(model 0x00-0x1f, 0x30-0x3f, 0x90-0x9f, 0xa0-0= xaf), Fam1Ah(model 0x00-0x1f) EPYC server line of processors from AMD support system management functionality via HSMP (Host System Management Port). =20 +The Fam1Ah(model 0x80-0x8f, 0xe0-0xe3) client line of processors is +supported as well. Those models share one mailbox and speak the Ryzen +Master SMC message set instead of the server HSMP message set, so the +message IDs accepted on them are the HSMP_CLIENT_* ones listed in +arch/x86/include/uapi/asm/amd_hsmp.h. The character device and ioctl +interface described below are the same. + The Host System Management Port (HSMP) is an interface to provide OS-level software with access to system management functions via a set of mailbox registers. @@ -17,7 +24,8 @@ More details on the interface can be found in chapter Eg: https://docs.amd.com/v/u/en-US/55898_B1_pub_0_50 =20 =20 -HSMP interface is supported on EPYC line of server CPUs and MI300A (APU). +HSMP interface is supported on EPYC line of server CPUs, MI300A (APU) and +the Fam1Ah client models listed above. =20 =20 HSMP device diff --git a/arch/x86/include/uapi/asm/amd_hsmp.h b/arch/x86/include/uapi/a= sm/amd_hsmp.h index eda336bfd3e9..7274cf040a66 100644 --- a/arch/x86/include/uapi/asm/amd_hsmp.h +++ b/arch/x86/include/uapi/asm/amd_hsmp.h @@ -9,6 +9,12 @@ =20 #define HSMP_MAX_MSG_LEN 8 =20 +/* + * HSMP client platforms (Ryzen Master SMC) accept at most four input + * argument words and four output/response words per message. + */ +#define HSMP_CLIENT_MAX_MSG_LEN 4 + /* * HSMP Messages supported */ @@ -71,6 +77,11 @@ enum hsmp_message_ids { HSMP_MSG_ID_MAX, }; =20 +/* + * The driver validates num_args and response_sz before sending a message. + * HSMP client platforms are bound to HSMP_CLIENT_MAX_MSG_LEN in each + * direction; server platforms are bound per-message by hsmp_msg_desc_tabl= e[]. + */ struct hsmp_message { __u32 msg_id; /* Message ID */ __u16 num_args; /* Number of input argument words in message */ @@ -664,4 +675,147 @@ struct hsmp_telemetry_data { #define HSMP_IOCTL_GET_TELEMETRY_DATA \ _IOW(HSMP_BASE_IOCTL_NR, 1, struct hsmp_telemetry_data) =20 +/** + * enum hsmp_client_message_ids - Ryzen Master SMC (RMSMC) message IDs + * @HSMP_CLIENT_TEST: 01h. Test message. input: args[0] =3D xx. output: + * args[0] =3D xx + 1. + * @HSMP_CLIENT_GET_SMU_VER: 02h. Get MP1 firmware version. output: + * args[0] =3D MP1 firmware version. + * @HSMP_CLIENT_GET_INTERFACE_VER: 03h. Get interface version. output: + * args[0] =3D interface version. + * @HSMP_CLIENT_GET_METRICS_TABLE_VER: 04h. Get metrics table version. + * output: args[0] =3D metrics table version. + * @HSMP_CLIENT_GET_METRICS_TABLE: 05h. Get metrics table. No arguments. + * Success means firmware has written the metrics table to the DRAM + * address reported by @HSMP_CLIENT_GET_METRICS_TABLE_DRAM_ADDR. + * @HSMP_CLIENT_GET_METRICS_TABLE_DRAM_ADDR: 06h. Get metrics table DRAM + * address. output: args[0] =3D address[31:0], args[1] =3D address[63:32], + * args[2] =3D table size in bytes. + * @HSMP_CLIENT_SET_CORE_PSM_MARGIN: 07h. Set core voltage margin. input: + * args[0] =3D ccx number[31:28] + core number[27:20] + reserved[19:16] + + * margin in mV[15:0]. + * @HSMP_CLIENT_SET_ALL_CORE_PSM_MARGIN: 08h. Set voltage margin for all + * cores. input: args[0] =3D margin in mV[15:0]. + * @HSMP_CLIENT_SET_FAST_PPT_LIMIT: 09h. Set APU fast PPT limit. input: + * args[0] =3D limit in mW. + * @HSMP_CLIENT_SET_VRM_VDD_CURRENT_LIMIT: 0Ah. Set VDDCR_VDD TDC. input: + * args[0] =3D limit in mA. + * @HSMP_CLIENT_SET_VRM_VDD_MAX_CURRENT_LIMIT: 0Bh. Set VDDCR_VDD EDC. + * input: args[0] =3D limit in mA. + * @HSMP_CLIENT_SET_TJ_MAX: 0Ch. Set maximum junction temperature. input: + * args[0] =3D temperature in degrees C. + * @HSMP_CLIENT_SET_FIT_LIMIT_SCALAR: 0Dh. Set failures-in-time limit + * scalar. input: args[0] =3D scalar (0 to 100). + * @HSMP_CLIENT_ENABLE_OVERCLOCKING: 0Eh. Enable overclocking. No + * arguments. + * @HSMP_CLIENT_DISABLE_OVERCLOCKING: 0Fh. Disable overclocking. No + * arguments. + * @HSMP_CLIENT_SET_OVERCLOCK_FREQ_ALL_CORES: 10h. Set all-core overclock + * frequency. input: args[0] =3D frequency in MHz[15:0]. + * @HSMP_CLIENT_SET_OVERCLOCK_FREQ_PER_CORE: 11h. Set per-core overclock + * frequency. input: args[0] =3D ccd number[31:28] + ccx number[27:24] + + * core number[23:20] + frequency in MHz[19:0]. + * @HSMP_CLIENT_SET_OVERCLOCK_VID: 12h. Set overclock VID. input: + * args[0] =3D reserved[31:17] + vid[16:8] + pstate[7:0]. + * @HSMP_CLIENT_SPARE_0X13: 13h. Reserved. + * @HSMP_CLIENT_GET_CORE_PERF_ORDER: 14h. Get core performance order. + * input: args[0] =3D core performance rank index[31:0] (0 to Enabled + * cores-1). output: args[0] =3D voltage in mV[31:21] + frequency in + * MHz[20:9] + fll[8:6] + core number[5:2] + ccx number[1:0]. + * @HSMP_CLIENT_SET_SUSTAINED_POWER_LIMIT: 15h. Set SOC sustained power + * limit. input: args[0] =3D limit in mW. + * @HSMP_CLIENT_SET_SLOW_PPT_LIMIT: 16h. Set APU slow PPT limit. input: + * args[0] =3D limit in mW. + * @HSMP_CLIENT_SET_VRM_GFX_MAX_CURRENT_LIMIT: 17h. Set VDDCR_GFX EDC. + * input: args[0] =3D limit in mA. + * @HSMP_CLIENT_SET_VRM_SOC_CURRENT_LIMIT: 18h. Set VDDCR_SOC TDC. input: + * args[0] =3D limit in mA. + * @HSMP_CLIENT_SET_FAST_SPM_LIMIT: 19h. Set fast SPM limit. input: + * args[0] =3D limit in mW. + * @HSMP_CLIENT_SET_SLOW_SPM_LIMIT: 1Ah. Set slow SPM limit. input: + * args[0] =3D limit in mW. + * @HSMP_CLIENT_GET_CORE_PSM_MARGIN: 1Bh. Get core voltage margin. input: + * args[0] =3D ccx number[31:28] + core number[27:20] + reserved[19:0]. + * output: args[0] =3D ccx number[31:28] + core number[27:20] + + * reserved[19:16] + margin in mV[15:0]. + * @HSMP_CLIENT_GET_GFX_PSM_MARGIN: 1Ch. Get graphics voltage margin. + * output: args[0] =3D margin in mV[15:0]. + * @HSMP_CLIENT_SPARE_0X1D: 1Dh. Reserved. + * @HSMP_CLIENT_SPARE_0X1E: 1Eh. Reserved. + * @HSMP_CLIENT_SPARE_0X1F: 1Fh. Reserved. + * @HSMP_CLIENT_SPARE_0X20: 20h. Reserved. + * @HSMP_CLIENT_SET_GFXCLK_OVERDRIVE_BY_FREQ_VID: 21h. Set GfxClk + * overdrive by frequency/VID. input: args[0] =3D reserved[31:25] + + * vid[24:16] + frequency in MHz[15:0]. + * @HSMP_CLIENT_DISABLE_GFXCLK_OVERDRIVE: 22h. Disable GfxClk overdrive. + * No arguments. + * @HSMP_CLIENT_SET_GFX_PSM_MARGIN: 23h. Set graphics voltage margin. + * input: args[0] =3D margin in mV[15:0]. + * @HSMP_CLIENT_SET_CCLK_FMAX_OFFSET: 24h. Set CCLK Fmax offset. input: + * args[0] =3D maximum frequency in MHz[15:0]. + * @HSMP_CLIENT_SET_CORE_POWER_LIMIT_OFFSET: 25h. Set core power limit + * offset. input: args[0] =3D limit in mW. + * @HSMP_CLIENT_ADD_EXTRA_PSM_GUARDBAND: 26h. Add extra core PSM + * guardband. input: args[0] =3D PsmGuardband[2][31:24] + + * PsmGuardband[1][23:16] + PsmGuardband[0][15:8] + TriggerUpdate[7] + + * AvfsType[6:4] + frequency index[3:0]. + * @HSMP_CLIENT_ADD_EXTRA_PSM_GUARDBAND_GFX: 27h. Add extra graphics PSM + * guardband. input: args[0] =3D PsmGuardband[2][31:24] + + * PsmGuardband[1][23:16] + PsmGuardband[0][15:8] + TriggerUpdate[7] + + * frequency index[6:0]. + * @HSMP_CLIENT_SET_GFXCLK_FMAX: 28h. Set GfxClk Fmax. input: args[0] =3D + * maximum frequency in MHz[15:0]. + * @HSMP_CLIENT_MSG_ID_MAX: Number of message IDs, not a valid ID itself. + * + * Message IDs accepted on the Family 1Ah client platforms, Models 80h-8Fh + * and E0h-E3h. These parts drive one mailbox and speak the Ryzen Master + * SMC message set instead of the server HSMP message set enumerated in + * &enum hsmp_message_ids. Not all platforms support all messages; consult + * the supported list of messages in the HSMP chapter of the respective + * family/model PPR. Unsupported messages return -ENOMSG. + */ +enum hsmp_client_message_ids { + HSMP_CLIENT_TEST =3D 1, + HSMP_CLIENT_GET_SMU_VER, + HSMP_CLIENT_GET_INTERFACE_VER, + HSMP_CLIENT_GET_METRICS_TABLE_VER, + HSMP_CLIENT_GET_METRICS_TABLE, + HSMP_CLIENT_GET_METRICS_TABLE_DRAM_ADDR, + HSMP_CLIENT_SET_CORE_PSM_MARGIN, + HSMP_CLIENT_SET_ALL_CORE_PSM_MARGIN, + HSMP_CLIENT_SET_FAST_PPT_LIMIT, + HSMP_CLIENT_SET_VRM_VDD_CURRENT_LIMIT, + HSMP_CLIENT_SET_VRM_VDD_MAX_CURRENT_LIMIT, + HSMP_CLIENT_SET_TJ_MAX, + HSMP_CLIENT_SET_FIT_LIMIT_SCALAR, + HSMP_CLIENT_ENABLE_OVERCLOCKING, + HSMP_CLIENT_DISABLE_OVERCLOCKING, + HSMP_CLIENT_SET_OVERCLOCK_FREQ_ALL_CORES, + HSMP_CLIENT_SET_OVERCLOCK_FREQ_PER_CORE, + HSMP_CLIENT_SET_OVERCLOCK_VID, + HSMP_CLIENT_SPARE_0X13, + HSMP_CLIENT_GET_CORE_PERF_ORDER, + HSMP_CLIENT_SET_SUSTAINED_POWER_LIMIT, + HSMP_CLIENT_SET_SLOW_PPT_LIMIT, + HSMP_CLIENT_SET_VRM_GFX_MAX_CURRENT_LIMIT, + HSMP_CLIENT_SET_VRM_SOC_CURRENT_LIMIT, + HSMP_CLIENT_SET_FAST_SPM_LIMIT, + HSMP_CLIENT_SET_SLOW_SPM_LIMIT, + HSMP_CLIENT_GET_CORE_PSM_MARGIN, + HSMP_CLIENT_GET_GFX_PSM_MARGIN, + HSMP_CLIENT_SPARE_0X1D, + HSMP_CLIENT_SPARE_0X1E, + HSMP_CLIENT_SPARE_0X1F, + HSMP_CLIENT_SPARE_0X20, + HSMP_CLIENT_SET_GFXCLK_OVERDRIVE_BY_FREQ_VID, + HSMP_CLIENT_DISABLE_GFXCLK_OVERDRIVE, + HSMP_CLIENT_SET_GFX_PSM_MARGIN, + HSMP_CLIENT_SET_CCLK_FMAX_OFFSET, + HSMP_CLIENT_SET_CORE_POWER_LIMIT_OFFSET, + HSMP_CLIENT_ADD_EXTRA_PSM_GUARDBAND, + HSMP_CLIENT_ADD_EXTRA_PSM_GUARDBAND_GFX, + HSMP_CLIENT_SET_GFXCLK_FMAX, + HSMP_CLIENT_MSG_ID_MAX, +}; + #endif /*_ASM_X86_AMD_HSMP_H_*/ diff --git a/drivers/platform/x86/amd/hsmp/hsmp.c b/drivers/platform/x86/am= d/hsmp/hsmp.c index 5e123a4ecea9..cf33c874096b 100644 --- a/drivers/platform/x86/amd/hsmp/hsmp.c +++ b/drivers/platform/x86/amd/hsmp/hsmp.c @@ -10,7 +10,10 @@ #include =20 #include +#include +#include #include +#include #include #include #include @@ -45,8 +48,87 @@ */ #define CHECK_GET_BIT BIT(31) =20 +/* Catch a table left out of sync with its enum at build time */ +static_assert(ARRAY_SIZE(hsmp_msg_desc_table) =3D=3D HSMP_MSG_ID_MAX); + +/* Per-platform message set: which table to use, and driver-issued msg IDs= */ +struct hsmp_plat_desc { + const struct hsmp_msg_desc *msg_desc; + u32 num_msgs; + u32 test_msg; + u32 proto_ver_msg; +}; + +static const struct hsmp_plat_desc hsmp_desc_server =3D { + .msg_desc =3D hsmp_msg_desc_table, + .num_msgs =3D HSMP_MSG_ID_MAX, + .test_msg =3D HSMP_TEST, + .proto_ver_msg =3D HSMP_GET_PROTO_VER, +}; + +/* + * The client drives a different mailbox with the Ryzen Master SMC message + * set. It has no per-message descriptor table: num_args/response_sz are + * bounded generically instead (see validate_message()), and an unsupported + * or malformed msg_id is rejected by firmware with its own SMU status cod= e. + */ +static const struct hsmp_plat_desc hsmp_desc_client =3D { + .msg_desc =3D NULL, + .num_msgs =3D HSMP_CLIENT_MSG_ID_MAX, + .test_msg =3D HSMP_CLIENT_TEST, + .proto_ver_msg =3D HSMP_CLIENT_GET_INTERFACE_VER, +}; + static struct hsmp_plat_device hsmp_pdev; =20 +/* Cached on first use; READ_ONCE()/WRITE_ONCE() avoid a torn access */ +static const struct hsmp_plat_desc *hsmp_desc_cache; + +static const struct hsmp_plat_desc *hsmp_desc(void) +{ + const struct hsmp_plat_desc *desc =3D READ_ONCE(hsmp_desc_cache); + + if (likely(desc)) + return desc; + + desc =3D is_client_platform() ? &hsmp_desc_client : &hsmp_desc_server; + WRITE_ONCE(hsmp_desc_cache, desc); + + return desc; +} + +/* Returns NULL if the platform has no descriptor table, or msg_id is out = of range or reserved */ +static const struct hsmp_msg_desc *get_msg_desc(u32 msg_id) +{ + const struct hsmp_plat_desc *desc =3D hsmp_desc(); + + if (!desc->msg_desc) + return NULL; + + if (msg_id < desc->test_msg || msg_id >=3D desc->num_msgs) + return NULL; + + if (desc->msg_desc[msg_id].type =3D=3D HSMP_RSVD) + return NULL; + + return &desc->msg_desc[msg_id]; +} + +/* + * Response size for a message the driver issues directly, such as the + * probe-time test, protocol-version and metric-table messages: the + * descriptor table entry for server, since these fixed, well-known message + * IDs always have one; the client protocol max otherwise, since the client + * set has no descriptor table and firmware reports no response length. + * Callers only consume the response words they expect. + */ +static u32 hsmp_msg_response_sz(u32 msg_id) +{ + const struct hsmp_msg_desc *desc =3D get_msg_desc(msg_id); + + return desc ? desc->response_sz : HSMP_CLIENT_MAX_MSG_LEN; +} + /* * Gates the AMD HSMP data plane against socket bring-up and teardown. * @@ -184,30 +266,46 @@ static int __hsmp_send_message(struct hsmp_socket *so= ck, struct hsmp_message *ms =20 static int validate_message(struct hsmp_message *msg) { - /* msg_id against valid range of message IDs */ - if (msg->msg_id < HSMP_TEST || msg->msg_id >=3D HSMP_MSG_ID_MAX) - return -ENOMSG; + const struct hsmp_plat_desc *plat_desc =3D hsmp_desc(); + const struct hsmp_msg_desc *desc; + + if (!plat_desc->msg_desc) { + /* + * The client message set has no per-message descriptor + * table and no msg_id range to validate against; cap + * num_args/response_sz to what the Ryzen Master mailbox + * supports in each direction and leave msg_id correctness, + * such as an unsupported or out-of-range value, to the SMU + * status code __hsmp_send_message() already translates. + */ + if (msg->num_args > HSMP_CLIENT_MAX_MSG_LEN || + msg->response_sz > HSMP_CLIENT_MAX_MSG_LEN) + return -EINVAL; + + return 0; + } =20 - /* msg_id is a reserved message ID */ - if (hsmp_msg_desc_table[msg->msg_id].type =3D=3D HSMP_RSVD) + /* Out-of-range or reserved message ID for this platform */ + desc =3D get_msg_desc(msg->msg_id); + if (!desc) return -ENOMSG; =20 /* * num_args passed by user should match the num_args specified in * message description table. */ - if (msg->num_args !=3D hsmp_msg_desc_table[msg->msg_id].num_args) + if (msg->num_args !=3D desc->num_args) return -EINVAL; =20 /* * As the HSMP protocol evolves, newer platforms may define more * response arguments for existing messages. Use an upper-bound * check so that older userspace callers requesting fewer response - * words than what the current hsmp_msg_desc_table[] defines are - * still accepted, while rejecting requests that exceed the - * hardware capability. + * words than what the current descriptor table defines are still + * accepted, while rejecting requests that exceed the hardware + * capability. */ - if (msg->response_sz > hsmp_msg_desc_table[msg->msg_id].response_sz) + if (msg->response_sz > desc->response_sz) return -EINVAL; =20 return 0; @@ -316,7 +414,7 @@ int hsmp_test(u16 sock_ind, u32 value) * Test the hsmp port by performing TEST command. The test message * takes one argument and returns the value of that argument + 1. */ - msg.msg_id =3D HSMP_TEST; + msg.msg_id =3D hsmp_desc()->test_msg; msg.num_args =3D 1; msg.response_sz =3D 1; msg.args[0] =3D value; @@ -338,13 +436,12 @@ int hsmp_test(u16 sock_ind, u32 value) } EXPORT_SYMBOL_NS_GPL(hsmp_test, "AMD_HSMP"); =20 -static bool is_get_msg(struct hsmp_message *msg) +static bool is_get_msg(const struct hsmp_msg_desc *desc, struct hsmp_messa= ge *msg) { - if (hsmp_msg_desc_table[msg->msg_id].type =3D=3D HSMP_GET) + if (desc->type =3D=3D HSMP_GET) return true; =20 - if (hsmp_msg_desc_table[msg->msg_id].type =3D=3D HSMP_SET_GET && - (msg->args[0] & CHECK_GET_BIT)) + if (desc->type =3D=3D HSMP_SET_GET && (msg->args[0] & CHECK_GET_BIT)) return true; =20 return false; @@ -354,63 +451,82 @@ static long hsmp_ioctl_msg(struct file *fp, unsigned = long arg) { int __user *arguser =3D (int __user *)arg; struct hsmp_message msg =3D { 0 }; + const struct hsmp_plat_desc *plat_desc =3D hsmp_desc(); + const struct hsmp_msg_desc *desc =3D NULL; int ret; =20 if (copy_struct_from_user(&msg, sizeof(msg), arguser, sizeof(struct hsmp_= message))) return -EFAULT; =20 /* - * Check msg_id is within the range of supported msg ids - * i.e within the array bounds of hsmp_msg_desc_table + * The client message set has no per-message descriptor table to + * bounds-check msg_id against or index into, and no per-message + * type to gate fd mode on, so none of that applies here. + * validate_message() (called via hsmp_send_message() below) still + * bounds num_args/response_sz generically, and firmware is the + * final arbiter of msg_id validity via its own response status. */ - if (msg.msg_id < HSMP_TEST || msg.msg_id >=3D HSMP_MSG_ID_MAX) - return -ENOMSG; - - /* - * Sanitize the user-controlled msg_id against speculative - * execution. The bounds check above retires the out-of-range - * case with -ENOMSG, but a mispredicted branch can still let the - * CPU speculatively use msg_id as an index into - * hsmp_msg_desc_table[] (here and in validate_message() / - * is_get_msg() called downstream via hsmp_send_message()), and - * pull arbitrary kernel memory into the cache (Spectre v1, - * CVE-2017-5753). Clamp once into msg.msg_id so every downstream - * dereference sees the sanitized value. - */ - msg.msg_id =3D array_index_nospec(msg.msg_id, HSMP_MSG_ID_MAX); - - switch (fp->f_mode & (FMODE_WRITE | FMODE_READ)) { - case FMODE_WRITE: + if (plat_desc->msg_desc) { /* - * Device is opened in O_WRONLY mode - * Execute only set/configure commands + * Check msg_id is within the range of supported msg ids + * i.e within the array bounds of the platform's descriptor table */ - if (is_get_msg(&msg)) - return -EPERM; - break; - case FMODE_READ: + if (msg.msg_id < plat_desc->test_msg || msg.msg_id >=3D plat_desc->num_m= sgs) + return -ENOMSG; + /* - * Device is opened in O_RDONLY mode - * Execute only get/monitor commands + * Sanitize the user-controlled msg_id against speculative + * execution. The bounds check above retires the out-of-range + * case with -ENOMSG, but a mispredicted branch can still let the + * CPU speculatively use msg_id as an index into the message + * descriptor table, here and again in validate_message() called + * downstream via hsmp_send_message(). */ - if (!is_get_msg(&msg)) + msg.msg_id =3D array_index_nospec(msg.msg_id, plat_desc->num_msgs); + + /* Rejects the reserved IDs the table describes as such */ + desc =3D get_msg_desc(msg.msg_id); + if (!desc) + return -ENOMSG; + + switch (fp->f_mode & (FMODE_WRITE | FMODE_READ)) { + case FMODE_WRITE: + /* + * Device is opened in O_WRONLY mode + * Execute only set/configure commands. + */ + if (is_get_msg(desc, &msg)) + return -EPERM; + break; + case FMODE_READ: + /* + * Device is opened in O_RDONLY mode + * Execute only get/monitor commands. + */ + if (!is_get_msg(desc, &msg)) + return -EPERM; + break; + case FMODE_READ | FMODE_WRITE: + /* + * Device is opened in O_RDWR mode + * Execute both get/monitor and set/configure commands + */ + break; + default: return -EPERM; - break; - case FMODE_READ | FMODE_WRITE: - /* - * Device is opened in O_RDWR mode - * Execute both get/monitor and set/configure commands - */ - break; - default: - return -EPERM; + } } =20 ret =3D hsmp_send_message(&msg); if (ret) return ret; =20 - if (hsmp_msg_desc_table[msg.msg_id].response_sz > 0) { + /* + * The client message set has no per-message response_sz to check + * here (desc is NULL); validate_message() already bounded + * msg.response_sz. + */ + if ((desc ? desc->response_sz : msg.response_sz) > 0) { /* Copy results back to user for get/monitor commands */ if (copy_to_user(arguser, &msg, sizeof(struct hsmp_message))) return -EFAULT; @@ -687,9 +803,9 @@ int hsmp_cache_proto_ver(u16 sock_ind) struct hsmp_message msg =3D { 0 }; int ret; =20 - msg.msg_id =3D HSMP_GET_PROTO_VER; + msg.msg_id =3D hsmp_desc()->proto_ver_msg; + msg.response_sz =3D hsmp_msg_response_sz(msg.msg_id); msg.sock_ind =3D sock_ind; - msg.response_sz =3D hsmp_msg_desc_table[HSMP_GET_PROTO_VER].response_sz; =20 ret =3D hsmp_send_message_locked(&msg); if (!ret) @@ -720,7 +836,12 @@ int hsmp_misc_register(struct device *dev) */ hsmp_pdev.mdev.parent =3D dev; hsmp_pdev.mdev.nodename =3D HSMP_DEVNODE_NAME; - hsmp_pdev.mdev.mode =3D 0644; + /* + * hsmp_ioctl_msg() gates a server fd's mode against the message's + * GET/SET type; the client set has no per-message type to gate on. + * Restrict /dev/hsmp to root on client platforms. + */ + hsmp_pdev.mdev.mode =3D is_client_platform() ? 0600 : 0644; =20 return misc_register(&hsmp_pdev.mdev); } diff --git a/drivers/platform/x86/amd/hsmp/hsmp.h b/drivers/platform/x86/am= d/hsmp/hsmp.h index 8dbff16a87b1..62ba795dc8c5 100644 --- a/drivers/platform/x86/amd/hsmp/hsmp.h +++ b/drivers/platform/x86/amd/hsmp/hsmp.h @@ -10,6 +10,9 @@ #ifndef HSMP_H #define HSMP_H =20 +#include + +#include #include #include #include @@ -17,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -32,6 +36,25 @@ =20 #define DRIVER_VERSION "2.6" =20 +/* True when the ACPI-reported PM profile indicates a client platform */ +static inline bool is_client_platform(void) +{ + if (!IS_ENABLED(CONFIG_ACPI)) + return false; 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charset="utf-8" Wire the client metric table and metric table DRAM address messages into the metric table read path for the Family 1Ah client platforms, and fetch the DRAM base for them during ACPI probe. Add metric_tbl_msg and metric_dram_msg to struct hsmp_plat_desc, and have hsmp_metric_tbl_read_locked() and hsmp_get_tbl_dram_base() take the message ID from there instead of a shared constant, since the client set numbers these messages differently from the server set (05h/06h vs 24h/25h). Have hsmp_get_tbl_dram_base() take response_sz from hsmp_msg_response_sz() too, since the client set has no descriptor table to take it from directly. Add enum ryzen_master_proto_versions, and split the single unconditional proto_ver check gating the hsmp_get_tbl_dram_base() call in init_acpi() into a RYZEN_MASTER_PROTO_VER1 clause for client platforms and a HSMP_PROTO_VER6 clause for server. proto_ver holds the Ryzen Master interface version on client platforms, a separate numbering space from enum hsmp_proto_versions; the single check happened to skip client today only because RYZEN_MASTER_PROTO_VER1 is numerically below HSMP_PROTO_VER6, and would misread a higher future client interface version as HSMP_PROTO_VER6 without the explicit split. Signed-off-by: Muralidhara M K Reviewed-by: Mario Limonciello (AMD) --- arch/x86/include/uapi/asm/amd_hsmp.h | 9 +++++++++ drivers/platform/x86/amd/hsmp/acpi.c | 3 ++- drivers/platform/x86/amd/hsmp/hsmp.c | 14 ++++++++++---- 3 files changed, 21 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/uapi/asm/amd_hsmp.h b/arch/x86/include/uapi/a= sm/amd_hsmp.h index 7274cf040a66..b4f64b2407b6 100644 --- a/arch/x86/include/uapi/asm/amd_hsmp.h +++ b/arch/x86/include/uapi/asm/amd_hsmp.h @@ -106,6 +106,15 @@ enum hsmp_proto_versions { HSMP_PROTO_VER7 }; =20 +/* + * Ryzen Master SMC interface version, reported by + * HSMP_CLIENT_GET_INTERFACE_VER. Separate numbering space from enum + * hsmp_proto_versions, which applies to the server set only. + */ +enum ryzen_master_proto_versions { + RYZEN_MASTER_PROTO_VER1 =3D 1, +}; + struct hsmp_msg_desc { int num_args; int response_sz; diff --git a/drivers/platform/x86/amd/hsmp/acpi.c b/drivers/platform/x86/am= d/hsmp/acpi.c index 8257cd1da48e..8b4bf57c3485 100644 --- a/drivers/platform/x86/amd/hsmp/acpi.c +++ b/drivers/platform/x86/amd/hsmp/acpi.c @@ -557,7 +557,8 @@ static int init_acpi(struct device *dev) return ret; } =20 - if (hsmp_pdev->proto_ver >=3D HSMP_PROTO_VER6) { + if ((is_client_platform() && hsmp_pdev->proto_ver >=3D RYZEN_MASTER_PROTO= _VER1) || + (!is_client_platform() && hsmp_pdev->proto_ver >=3D HSMP_PROTO_VER6))= { ret =3D hsmp_get_tbl_dram_base(sock_ind); if (ret) dev_info(dev, "Failed to init metric table\n"); diff --git a/drivers/platform/x86/amd/hsmp/hsmp.c b/drivers/platform/x86/am= d/hsmp/hsmp.c index cf33c874096b..ecfd2f92a531 100644 --- a/drivers/platform/x86/amd/hsmp/hsmp.c +++ b/drivers/platform/x86/amd/hsmp/hsmp.c @@ -57,6 +57,8 @@ struct hsmp_plat_desc { u32 num_msgs; u32 test_msg; u32 proto_ver_msg; + u32 metric_tbl_msg; + u32 metric_dram_msg; }; =20 static const struct hsmp_plat_desc hsmp_desc_server =3D { @@ -64,6 +66,8 @@ static const struct hsmp_plat_desc hsmp_desc_server =3D { .num_msgs =3D HSMP_MSG_ID_MAX, .test_msg =3D HSMP_TEST, .proto_ver_msg =3D HSMP_GET_PROTO_VER, + .metric_tbl_msg =3D HSMP_GET_METRIC_TABLE, + .metric_dram_msg =3D HSMP_GET_METRIC_TABLE_DRAM_ADDR, }; =20 /* @@ -77,6 +81,8 @@ static const struct hsmp_plat_desc hsmp_desc_client =3D { .num_msgs =3D HSMP_CLIENT_MSG_ID_MAX, .test_msg =3D HSMP_CLIENT_TEST, .proto_ver_msg =3D HSMP_CLIENT_GET_INTERFACE_VER, + .metric_tbl_msg =3D HSMP_CLIENT_GET_METRICS_TABLE, + .metric_dram_msg =3D HSMP_CLIENT_GET_METRICS_TABLE_DRAM_ADDR, }; =20 static struct hsmp_plat_device hsmp_pdev; @@ -681,11 +687,11 @@ static ssize_t hsmp_metric_tbl_read_locked(struct hsm= p_socket *sock, char *buf, return -EINVAL; } =20 - msg.msg_id =3D HSMP_GET_METRIC_TABLE; + msg.msg_id =3D hsmp_desc()->metric_tbl_msg; msg.sock_ind =3D sock->sock_ind; =20 /* - * HSMP_GET_METRIC_TABLE makes firmware refill this socket's shared + * The metric table message makes firmware refill this socket's shared * metric DRAM region, which is then copied out below. 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charset="utf-8" Most ACPI sysfs device attributes are wired to hardcoded server message IDs (HSMP_GET_SOCKET_POWER and friends); hwmon power attributes registered from init_acpi() have the same problem. On a Family 1Ah client platform these numeric IDs resolve against enum hsmp_client_message_ids instead, and mostly collide with unrelated client commands, e.g. HSMP_GET_SOCKET_POWER (4) is HSMP_CLIENT_GET_METRICS_TABLE_VER on the client side. Hide the affected ACPI sysfs attributes on client platforms except smu_fw_version and protocol_version, which report the same data in both tables. Forward-declare hattr_smu_fw_version and hattr_protocol_version ahead of their HSMP_DEV_ATTR() definitions. Skip hsmp_create_sensor() in init_acpi() on client platforms for the same reason. The metrics_bin sysfs binary attribute has the same visibility problem: hsmp_is_sock_attr_visible() gates it on hsmp_pdev->proto_ver against HSMP_PROTO_VER6 with no is_client_platform() check. Exclude client platforms outright there too, matching the ACPI sysfs attributes above: the client set has its own telemetry table, read only through HSMP_IOCTL_GET_TELEMETRY_DATA. Signed-off-by: Muralidhara M K --- drivers/platform/x86/amd/hsmp/acpi.c | 29 ++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/platform/x86/amd/hsmp/acpi.c b/drivers/platform/x86/am= d/hsmp/acpi.c index 8b4bf57c3485..d775ea8ba603 100644 --- a/drivers/platform/x86/amd/hsmp/acpi.c +++ b/drivers/platform/x86/amd/hsmp/acpi.c @@ -300,16 +300,31 @@ static umode_t hsmp_is_sock_attr_visible(struct kobje= ct *kobj, * so that userspace which expects the file to exist gets a clear * -EOPNOTSUPP from the read handler instead of -ENOENT, and is * pointed at HSMP_IOCTL_GET_TELEMETRY_DATA as the supported path. + * The client set has its own telemetry table, read only through + * HSMP_IOCTL_GET_TELEMETRY_DATA; never show this file there. */ - if (hsmp_pdev->proto_ver >=3D HSMP_PROTO_VER6) + if (!is_client_platform() && hsmp_pdev->proto_ver >=3D HSMP_PROTO_VER6) return battr->attr.mode; =20 return 0; } =20 +/* Defined below by HSMP_DEV_ATTR(); same message ID in both message table= s */ +static struct hsmp_sys_attr hattr_smu_fw_version; +static struct hsmp_sys_attr hattr_protocol_version; + static umode_t hsmp_is_sock_dev_attr_visible(struct kobject *kobj, struct attribute *attr, int id) { + /* + * smu_fw_version and protocol_version map to the same data in both + * message tables. Every other attribute here uses server-only + * message IDs that resolve to unrelated client commands. + */ + if (is_client_platform() && attr !=3D &hattr_smu_fw_version.dattr.attr && + attr !=3D &hattr_protocol_version.dattr.attr) + return 0; + return attr->mode; } =20 @@ -564,9 +579,15 @@ static int init_acpi(struct device *dev) dev_info(dev, "Failed to init metric table\n"); } =20 - ret =3D hsmp_create_sensor(dev, sock_ind); - if (ret) - dev_info(dev, "Failed to register HSMP sensors with hwmon\n"); + /* + * hwmon attributes use server-only message IDs, which resolve to + * unrelated client commands on client platforms. + */ + if (!is_client_platform()) { + ret =3D hsmp_create_sensor(dev, sock_ind); + if (ret) + dev_info(dev, "Failed to register HSMP sensors with hwmon\n"); + } =20 dev_set_drvdata(dev, &hsmp_pdev->sock[sock_ind]); =20 --=20 2.34.1 From nobody Sat Sep 26 13:50:00 2026 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011023.outbound.protection.outlook.com [40.93.194.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 585AA4A498F; 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charset="utf-8" Add struct hsmp_telemetry_table_rm to the UAPI header, describing the Ryzen Master SMC telemetry table (table version 5, as reported by HSMP_CLIENT_GET_METRICS_TABLE_VER) returned by HSMP_CLIENT_GET_METRICS_TABLE on the Family 1Ah client models. Point amd_hsmp.rst at struct hsmp_telemetry_table_rm instead of duplicating the layout in prose. The Public PPR for the model in use remains the reference for units and encodings. Signed-off-by: Muralidhara M K Reviewed-by: Mario Limonciello (AMD) --- Documentation/arch/x86/amd_hsmp.rst | 14 ++ arch/x86/include/uapi/asm/amd_hsmp.h | 257 +++++++++++++++++++++++++++ 2 files changed, 271 insertions(+) diff --git a/Documentation/arch/x86/amd_hsmp.rst b/Documentation/arch/x86/a= md_hsmp.rst index b95f09945193..c483c68dcfad 100644 --- a/Documentation/arch/x86/amd_hsmp.rst +++ b/Documentation/arch/x86/amd_hsmp.rst @@ -221,9 +221,23 @@ The following IOCTLs are defined: ``sizeof(struct hsmp_metric_table)``. Later version metrics table layout is documented in the Public PPR. =20 + The Family 1Ah client models carry their own telemetry table instead, + described in `Family 1Ah client telemetry table`_ below. + The ioctl would return a non-zero on failure; you can read errno to see what happened. The transaction returns 0 on success. =20 +Family 1Ah client telemetry table +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D +On the Family 1Ah client models, ``HSMP_CLIENT_GET_METRICS_TABLE`` (05h) +returns the Ryzen Master SMC telemetry table, table version 5 as +reported by ``HSMP_CLIENT_GET_METRICS_TABLE_VER`` (04h). This is the +Telemetry Table RM layout, defined as ``struct hsmp_telemetry_table_rm`` +in amd_hsmp.h. The driver copies the table out without interpreting it. + +See the telemetry table chapter of the AMD Public PPR for the model in +use for the units and encodings of its fields. + More details on the interface and message definitions can be found in chap= ter "7 Host System Management Port (HSMP)" of the respective family/model PPR eg: https://docs.amd.com/v/u/en-US/55898_B1_pub_0_50 diff --git a/arch/x86/include/uapi/asm/amd_hsmp.h b/arch/x86/include/uapi/a= sm/amd_hsmp.h index b4f64b2407b6..dcbe89dc4d2b 100644 --- a/arch/x86/include/uapi/asm/amd_hsmp.h +++ b/arch/x86/include/uapi/asm/amd_hsmp.h @@ -827,4 +827,261 @@ enum hsmp_client_message_ids { HSMP_CLIENT_MSG_ID_MAX, }; =20 +#define HSMP_TELEMETRY_RM_MAX_CCX 4 +#define HSMP_TELEMETRY_RM_CORES_PER_CCX 12 +#define HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE 8 +#define HSMP_TELEMETRY_RM_NPU_BUSY_DOMAINS 3 +#define HSMP_TELEMETRY_RM_OC_DOMAINS 5 +#define HSMP_TELEMETRY_RM_OC_SUBDOMAINS 5 +#define HSMP_TELEMETRY_RM_OC_GUARDBANDS 3 + +/* Firmware packs this table to a 4-byte boundary */ +#pragma pack(push, 4) + +/* + * struct hsmp_telemetry_table_rm_iod - I/O die counters for RM telemetry. + * + * Accumulator (*_acc) fields are monotonic counters; consumers derive + * deltas across two snapshots and normalise by accumulation_counter. + */ +struct hsmp_telemetry_table_rm_iod { + __u32 accumulation_counter; + + /* SET VOLTAGES */ + __u64 vddcr_set_voltage; + __u64 vddcr_soc_set_voltage; + __u64 vddcr_npu_set_voltage; + __u64 vddcr_lp_set_voltage; + __u64 vddcr_gfx_set_voltage; + __u64 vdd_misc_set_voltage; + + /* TELEMETRY VOLTAGES */ + __u64 vddcr_telemetry_voltage; + __u64 vddcr_soc_telemetry_voltage; + __u64 vddcr_npu_telemetry_voltage; + __u64 vddcr_lp_telemetry_voltage; + __u64 vddcr_gfx_telemetry_voltage; + __u64 vdd_misc_telemetry_voltage; + + /* TELEMETRY POWERS */ + __u64 vddcr_telemetry_power; + __u64 vddcr_soc_telemetry_power; + __u64 vddcr_npu_telemetry_power; + __u64 vddcr_lp_telemetry_power; + __u64 vddcr_gfx_telemetry_power; + __u64 vdd_misc_telemetry_power; + + /* THROTTLERS - FAST PPT */ + __u32 fppt_fused_limit; + __u32 fppt_max_irm_limit; + __u32 fppt_max_pbo_limit; + __u32 fppt_limit; + __u64 fppt_value_acc; + __u32 fppt_residency_acc; + + /* THROTTLERS - SLOW PPT */ + __u32 sppt_fused_limit; + __u32 sppt_max_irm_limit; + __u32 sppt_max_pbo_limit; + __u32 sppt_limit; + __u64 sppt_value_acc; + __u32 sppt_residency_acc; + + /* THROTTLERS - SPL */ + __u32 spl_fused_limit; + __u32 spl_max_irm_limit; + __u32 spl_max_pbo_limit; + __u32 spl_limit; + __u64 spl_value_acc; + __u32 spl_residency_acc; + + /* THROTTLERS - TDC VDDCR */ + __u32 tdc_vddcr_fused_limit; + __u32 tdc_vddcr_max_irm_limit; + __u32 tdc_vddcr_max_pbo_limit; + __u32 tdc_vddcr_limit; + __u64 tdc_vddcr_value_acc; + __u32 tdc_vddcr_residency_acc; + + /* THROTTLERS - TDC VDDCR SOC */ + __u32 tdc_vddcr_soc_fused_limit; + __u32 tdc_vddcr_soc_max_irm_limit; + __u32 tdc_vddcr_soc_max_pbo_limit; + __u32 tdc_vddcr_soc_limit; + __u64 tdc_vddcr_soc_value_acc; + __u32 tdc_vddcr_soc_residency_acc; + + /* THROTTLERS - TDC VDDCR NPU */ + __u32 tdc_vddcr_npu_fused_limit; + __u32 tdc_vddcr_npu_max_irm_limit; + __u32 tdc_vddcr_npu_max_pbo_limit; + __u32 tdc_vddcr_npu_limit; + __u64 tdc_vddcr_npu_value_acc; + __u32 tdc_vddcr_npu_residency_acc; + + /* THROTTLERS - TDC VDDCR LP */ + __u32 tdc_vddcr_lp_fused_limit; + __u32 tdc_vddcr_lp_max_irm_limit; + __u32 tdc_vddcr_lp_max_pbo_limit; + __u32 tdc_vddcr_lp_limit; + __u64 tdc_vddcr_lp_value_acc; + __u32 tdc_vddcr_lp_residency_acc; + + /* THROTTLERS - TDC VDDCR GFX */ + __u32 tdc_vddcr_gfx_fused_limit; + __u32 tdc_vddcr_gfx_max_irm_limit; + __u32 tdc_vddcr_gfx_max_pbo_limit; + __u32 tdc_vddcr_gfx_limit; + __u64 tdc_vddcr_gfx_value_acc; + __u32 tdc_vddcr_gfx_residency_acc; + + /* THROTTLERS - EDC VDDCR */ + __u32 edc_vddcr_fused_limit; + __u32 edc_vddcr_max_irm_limit; + __u32 edc_vddcr_max_pbo_limit; + __u32 edc_vddcr_limit; + + /* THROTTLERS - THERMAL */ + __u32 thm_fused_limit; + __u32 thm_limit; + __u64 thm_value_acc; + __u32 thm_residency_acc; + __u32 prochot_residency_acc; + __u64 gfx_temp_acc; + __u64 soc_temp_acc; + __u32 p3t_fused_limit; + __u64 p3t_value_acc; + + /* POWER */ + __u64 system_power_acc; + __u64 apu_power_acc; + __u64 dgpu_power_acc; + __u64 npu_power_acc; + + /* FREQUENCIES */ + __u64 fclk_freq_eff_acc; + __u64 memclk_freq_eff_acc; + __u64 lclk_freq_eff_acc; + __u64 gfxclk_freq_eff_acc; + __u64 socclk_freq_eff_acc; + __u64 vclk_freq_eff_acc; + __u64 vpeclk_freq_eff_acc; + __u64 aieclk_freq_eff_acc; + __u64 npuhclk_freq_eff_acc; + + /* BANDWIDTH */ + __u64 dram_read_bandwidth; + __u64 dram_write_bandwidth; + + /* ACTIVITY MONITORS */ + __u64 gfx_busy_acc; + __u64 vcn_busy_acc; + __u64 npu_busy_acc[HSMP_TELEMETRY_RM_NPU_BUSY_DOMAINS]; + + /* STT (Skin Temperature Tracking) */ + __u32 stt_min_limit; + __u64 stt_apu_hot_spot_temp_acc; + __u64 stt_hs2_hot_spot_temp_acc; + __u32 stt_apu_temp_limit; + __u64 stt_apu_skin_temp_acc; + + /* RESIDENCIES - per-CCX CPU off */ + __u64 cpu_off_residency[HSMP_TELEMETRY_RM_MAX_CCX]; + + /* DF P-STATES */ + __u32 fclk_freq_table[HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE]; + __u32 uclk_freq_table[HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE]; + __u32 ddr_rate_table[HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE]; + __u8 df_pstate_source[HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE]; + + /* SYSTEM */ + __u8 gfx_disabled; + __u8 spare2[3]; + __u32 gfxclk_fmax; + __u8 cclk_core_fuse_enable[HSMP_TELEMETRY_RM_MAX_CCX][HSMP_TELEMETRY_RM_= CORES_PER_CCX]; + __u8 cclk_core_enabled[HSMP_TELEMETRY_RM_MAX_CCX][HSMP_TELEMETRY_RM_CORE= S_PER_CCX]; + __u32 cclk_fmax[HSMP_TELEMETRY_RM_MAX_CCX][HSMP_TELEMETRY_RM_CORES_PER_CC= X]; + + /* OVERCLOCK CAPABLE */ + __u8 cpu_precise_and_direct_oc_capable; + __u8 gfx_precise_and_direct_oc_capable; + __u8 pbo_basic_oc_capable; + __u8 pbo_advanced_oc_capable; + __u8 pbo_nitro_oc_capable; + __u8 memory_and_fabric_oc_capable; + __u8 misc_oc_capable; + __u8 extreme_cold_oc_capable; + __u8 down_config_control_capable; + __u8 spare0[3]; + + /* OVERCLOCK STATUS */ + __u32 fit_limit_scalar; + __u8 ln2_enabled; + __u8 cpu_precise_and_direct_oc_enabled; + __u8 gfx_precise_and_direct_oc_enabled; + __u8 spare1[2]; + __s8 psm_guardband[HSMP_TELEMETRY_RM_OC_DOMAINS] + [HSMP_TELEMETRY_RM_OC_SUBDOMAINS] + [HSMP_TELEMETRY_RM_OC_GUARDBANDS]; + __s32 core_power_limit_offset; + __u32 max_freq_offset[HSMP_TELEMETRY_RM_OC_DOMAINS]; + + __u64 npu_temp_acc; + __u64 df_pstate_residency_acc[HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE]; + __u32 cclk_fboost; + + /* PMF */ + __u32 pmf_fast_apu_ppt_limit; + __u64 pmf_fast_apu_ppt_value_acc; + __u32 pmf_fast_apu_ppt_residency_acc; + + __u32 pmf_slow_apu_ppt_limit; + __u64 pmf_slow_apu_ppt_value_acc; + __u32 pmf_slow_apu_ppt_residency_acc; + + __u32 pmf_fast_spm_limit; + __u64 pmf_fast_spm_value_acc; + __u32 pmf_fast_spm_residency_acc; + + __u32 pmf_slow_spm_limit; + __u64 pmf_slow_spm_value_acc; + __u32 pmf_slow_spm_residency_acc; + + __u32 spare3[5]; +}; + +/* + * struct hsmp_telemetry_table_rm_ccx - Per-CCX core counters for RM telem= etry. + * + * Arrays are sized for the maximum cores per CCX; use the + * cclk_core_enabled[] mask in struct hsmp_telemetry_table_rm_iod to tell + * which entries are valid. + */ +struct hsmp_telemetry_table_rm_ccx { + __u64 core_c0[HSMP_TELEMETRY_RM_CORES_PER_CCX]; + __u64 core_cc6[HSMP_TELEMETRY_RM_CORES_PER_CCX]; + __u64 core_freq[HSMP_TELEMETRY_RM_CORES_PER_CCX]; + __u64 core_freq_eff[HSMP_TELEMETRY_RM_CORES_PER_CCX]; + __u64 core_temp[HSMP_TELEMETRY_RM_CORES_PER_CCX]; + __u64 core_power[HSMP_TELEMETRY_RM_CORES_PER_CCX]; +}; + +/** + * struct hsmp_telemetry_table_rm - Top-level RM telemetry table. + * @iod: I/O die counters and per-rail/per-throttler/SYSTEM telemetry. + * @ccx: Per-CCX core counters, one entry per CCX. + * + * Layout of the table returned by HSMP_CLIENT_GET_METRICS_TABLE on the + * Family 1Ah client (Models 80h-8Fh and E0h-E3h), reported as table + * version 5 by HSMP_CLIENT_GET_METRICS_TABLE_VER. Units are + * firmware-defined; see the AMD HSMP/Ryzen Master SMC spec. Spare + * fields are firmware padding and must be preserved. + */ +struct hsmp_telemetry_table_rm { + struct hsmp_telemetry_table_rm_iod iod; + struct hsmp_telemetry_table_rm_ccx ccx[HSMP_TELEMETRY_RM_MAX_CCX]; +}; + +#pragma pack(pop) + #endif /*_ASM_X86_AMD_HSMP_H_*/ --=20 2.34.1