From nobody Thu Sep 24 12:02:45 2026 Received: from mail-wr1-f71.google.com (mail-wr1-f71.google.com [209.85.221.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD3BE41F5D1 for ; Thu, 24 Sep 2026 08:56:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.71 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790240189; cv=none; b=X8NAJdr2+vzQ2m59sODNpVJLzw2+ThdNg1Km0RV29P745IFrX/PDBcjbzrYMYapnJQZfb8xiy45sNES8UiZdrHHjoZTVUsCvi68jXVnpDhG9DDXAoXQAWR+bYm04i+y6D0DkwbXPvhLHPWh9Powv9Zo0HeTyXgsC4pxxqoR8zxc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790240189; c=relaxed/simple; bh=bxdeOguzyBUWg5FmS/ooCmP0SBlbym7Li6q+GIcu2c0=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=XKRfwqtn4a62RCchW+iknC7uflj8rose997kNKEdqduDq4kHMj+D6SitREh6eFdmLXx2uCiwWquixoQ+is60qhA3r6Vjwb6/4TTvyGYy3OXJ4xbK5VEYTgpQ4rMDNufOFzp9iXo/3ZVXt+nVxdioWTarijTU3wxRaCdW/x79dy0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--smostafa.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=Xfc7BHUw; arc=none smtp.client-ip=209.85.221.71 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--smostafa.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="Xfc7BHUw" Received: by mail-wr1-f71.google.com with SMTP id ffacd0b85a97d-485866e0066so840231f8f.2 for ; Thu, 24 Sep 2026 01:56:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1790240186; x=1790844986; darn=vger.kernel.org; h=content-type:cc:to:from:subject:message-id:references:mime-version :in-reply-to:date:from:to:cc:subject:date:message-id:reply-to :content-type; bh=gvYNwuZspYmqJYkW4Kvv5dJobx9eOS6NsDNgvr2VGvU=; b=Xfc7BHUwUYhT/g69SAb3GujhYDAOJRD5mIk8Sjfv0BS9jJaFxhW8cDcRk09IuOg4A8 o5bwe3waMj/fqEa4vz7d2S5JFcpqJs4FFBg+cMlPzOCT8besur7XB+BJR6zmnzEU9AJz hvNU2JFtRPglYnsXi66eyrU/0UCV8/SxuDpQaC1sK+bt8nCdGwH5Y6pMz8huP0j4rW0a BFixo7G0CMPgAmXSP4g+DiuEI6ZBgkF4LxhpR9MOw/oKPYaH6Y9SkK6kWObtyOsbS2aq I7KXVAtkZ8vf5GTjG9ozsYlKGTo6gPsAUH6I0RBRr6/HeCW9G43J43EbF6WTubI1cnxN et8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1790240186; x=1790844986; h=content-type:cc:to:from:subject:message-id:references:mime-version :in-reply-to:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to:content-type; bh=gvYNwuZspYmqJYkW4Kvv5dJobx9eOS6NsDNgvr2VGvU=; b=t53mu200PIFQnr3wRmz1Uo/OWrWIDVwHQfJKUay0rmA4vfgNXYb9ccLOhA5SEL8FjM YWe2haY9XCinR6uWIoRqghaJHksj2JlibvdV3YhECrur8ar0BVPUHnc9YJzQPMzB4scx ppQp0W1Z56OyM8hqphUYCGeI3DC7kLeCARiSzJTwpZe30lqEUwpX7fCz4Qn99Y67G18f pzWrDx/TFt2/e5WJ6iopMg7gexZ7+W4/gfyiTaRb+qzdnxUU7h4pzGAD7py5Vy6KV5i+ /JedVmt2Oo8juOeXMLIku6NzaU8IhTGOV3hP+pqv9kG/k18+4J9edJzMWtr3Az9It13L +RGg== X-Gm-Message-State: AFuF++k88KIV4nJnRtkZzLE8+xE/mU+8LCtfYNbX4D1FdnrEIgsYPcRl CtWeAOACqWZicbxHmdz2G3AKDXcbkM2OZ6xZOvox8ScG9vpZf+2GU6Fpl4TeypP6VghNOxErUTO GhpZj6SM+ivpMZIJ8XqFJOdm0JzJtMZYlr6MPKjRrdStRRM/30SjlRtGcdsKbx1HXk0SsARMa79 p5jYFBJ2izNk5Whpo6SWGVQqmQr4SFGhKNSXwJlKI9GPiyNkiZ+8kY3bI= X-Received: from wrbft16.prod.google.com ([2002:a05:6000:2b10:b0:47f:74c9:84ee]) (user=smostafa job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6000:310a:b0:486:f980:2367 with SMTP id ffacd0b85a97d-488716aaa53mr3150067f8f.48.1790240185585; Thu, 24 Sep 2026 01:56:25 -0700 (PDT) Date: Thu, 24 Sep 2026 08:56:12 +0000 In-Reply-To: <20260924085616.300650-1-smostafa@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260924085616.300650-1-smostafa@google.com> X-Mailer: git-send-email 2.56.0.rc1.315.gc6ed9934b7-goog Message-ID: <20260924085616.300650-2-smostafa@google.com> Subject: [PATCH v2 1/5] iommu/arm-smmu-v3: Ensure L2 tables are visible before L1 ptrs From: Mostafa Saleh To: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, jgg@ziepe.ca, nicolinc@nvidia.com, praan@google.com, Mostafa Saleh , Jason Gunthorpe Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit 6fabce53f6b9 ("iommu/arm-smmu-v3: Add a missing dma_wmb() for hitles= s STE update") adds a dma_wmb() to arm_smmu_write_entry() to make sure stream tables and context descriptors are observed first. However, STE L1 table descriptors are configured directly via WRITE_ONCE(), where before that they were zeroed with memset() inside dma_direct_alloc() then written to abort in via memset() also in arm_smmu_init_initial_stes() without a barrier in both cases which means that the SMMUv3 can observe the allocated table before the written descriptors causing it to fetch random data. Similarly in arm_smmu_write_cd_l1_desc() where the L1 CD is written after dma_alloc_coherent() with no barriers. Add dma_wmb() in both cases. Fixes: 48ec83bcbcf5 ("iommu/arm-smmu: Add initial driver support for ARM SM= MUv3 devices") Reported-by: Sashiko <> Reviewed-by: Nicolin Chen Reviewed-by: Jason Gunthorpe Signed-off-by: Mostafa Saleh --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 5732f3ba0122..494bbfd2869f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1515,6 +1515,9 @@ static void arm_smmu_write_cd_l1_desc(struct arm_smmu= _cdtab_l1 *dst, { u64 val =3D (l2ptr_dma & CTXDESC_L1_DESC_L2PTR_MASK) | CTXDESC_L1_DESC_V; =20 + /* Ensure the zero-cleared L2 table is fully visible. */ + dma_wmb(); + /* The HW has 64 bit atomicity with stores to the L2 CD table */ WRITE_ONCE(dst->l2ptr, cpu_to_le64(val)); } @@ -1804,6 +1807,9 @@ static void arm_smmu_write_strtab_l1_desc(struct arm_= smmu_strtab_l1 *dst, val |=3D FIELD_PREP(STRTAB_L1_DESC_SPAN, STRTAB_SPLIT + 1); val |=3D l2ptr_dma & STRTAB_L1_DESC_L2PTR_MASK; =20 + /* Ensure the new L2 table is fully visible. */ + dma_wmb(); + /* The HW has 64 bit atomicity with stores to the L2 STE table */ WRITE_ONCE(dst->l2ptr, cpu_to_le64(val)); } --=20 2.56.0.rc1.315.gc6ed9934b7-goog From nobody Thu Sep 24 12:02:45 2026 Received: from mail-ed1-f72.google.com (mail-ed1-f72.google.com [209.85.208.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0A9644238A for ; Thu, 24 Sep 2026 08:56:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790240191; cv=none; b=JSZkWqBbYIjBvV7cDQjvTTfWjOGtkfZwTuTrte0nHsM+zhSLNJ33JuX6AjzouKY2ndbP3EFeHPtBu6edOOa+nv62DasRcLGq/Qkk4yOuY93zXlQ6HSkIyjOVBbBbEdA1tCjUrgvqgHRlXuPGYXezIvqZBLscCoevqKhs6lDt+gM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" arm_smmu_v3_test_debug_print_used_bits() hardcodes arm_smmu_get_ste_used() instead of using the provided writer->ops->get_used() callback. This caused Context Descriptors to be incorrectly parsed as STEs. Fixes: 56e1a4cc2588 ("iommu/arm-smmu-v3: Add unit tests for arm_smmu_write_= entry") Reported-by: Sashiko <> Reviewed-by: Nicolin Chen Reviewed-by: Jason Gunthorpe Signed-off-by: Mostafa Saleh --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index add671363c82..eae08d4d77ec 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -125,8 +125,8 @@ arm_smmu_v3_test_debug_print_used_bits(struct arm_smmu_= entry_writer *writer, { __le64 used_bits[NUM_ENTRY_QWORDS] =3D {}; =20 - arm_smmu_get_ste_used(ste, used_bits); - pr_debug("STE used bits: "); + writer->ops->get_used(ste, used_bits); + pr_debug("Entry used bits: "); print_hex_dump_debug(" ", DUMP_PREFIX_NONE, 16, 8, used_bits, sizeof(used_bits), false); } --=20 2.56.0.rc1.315.gc6ed9934b7-goog From nobody Thu Sep 24 12:02:45 2026 Received: from mail-ej1-f71.google.com (mail-ej1-f71.google.com [209.85.218.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B45B2443AAB for ; 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Thu, 24 Sep 2026 01:56:28 -0700 (PDT) Date: Thu, 24 Sep 2026 08:56:14 +0000 In-Reply-To: <20260924085616.300650-1-smostafa@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260924085616.300650-1-smostafa@google.com> X-Mailer: git-send-email 2.56.0.rc1.315.gc6ed9934b7-goog Message-ID: <20260924085616.300650-4-smostafa@google.com> Subject: [PATCH v2 3/5] iommu/arm-smmu-v3-test: Add missing error checks for inv array From: Mostafa Saleh To: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, jgg@ziepe.ca, nicolinc@nvidia.com, praan@google.com, Mostafa Saleh Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" arm_smmu_invs_merge() and arm_smmu_invs_alloc() can return NULL or errors which are checked by the driver but not the test. Add KUNIT_ASSERT_NOT_ERR_OR_NULL() after calling them to fail the test instead of accessing NULL or ERR pointers. Fixes: 15a2a5645ad7 ("iommu/arm-smmu-v3: Introduce a per-domain arm_smmu_in= vs array") Reported-by: Sashiko <> Signed-off-by: Mostafa Saleh --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index eae08d4d77ec..366dcb2b5554 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -704,17 +704,20 @@ static void arm_smmu_v3_invs_test(struct kunit *test) =20 /* New array */ test_a =3D arm_smmu_invs_alloc(0); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, test_a); KUNIT_EXPECT_EQ(test, test_a->num_invs, 0); =20 /* Test1: merge invs1 (new array) */ test_b =3D arm_smmu_invs_merge(test_a, &invs1); kfree(test_a); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, test_b); arm_smmu_v3_invs_test_verify(test, test_b, ARRAY_SIZE(results1[0]), 0, results1[0], results1[1], results1[2]); =20 /* Test2: merge invs2 (new array) */ test_a =3D arm_smmu_invs_merge(test_b, &invs2); kfree(test_b); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, test_a); arm_smmu_v3_invs_test_verify(test, test_a, ARRAY_SIZE(results2[0]), 0, results2[0], results2[1], results2[2]); =20 @@ -726,6 +729,7 @@ static void arm_smmu_v3_invs_test(struct kunit *test) /* Test4: merge invs3 (new array) */ test_b =3D arm_smmu_invs_merge(test_a, &invs3); kfree(test_a); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, test_b); arm_smmu_v3_invs_test_verify(test, test_b, ARRAY_SIZE(results4[0]), 0, results4[0], results4[1], results4[2]); =20 @@ -737,6 +741,7 @@ static void arm_smmu_v3_invs_test(struct kunit *test) /* Test6: purge test_b (new array) */ test_a =3D arm_smmu_invs_purge(test_b); kfree(test_b); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, test_a); arm_smmu_v3_invs_test_verify(test, test_a, ARRAY_SIZE(results6[0]), 0, results6[0], results6[1], results6[2]); =20 @@ -748,12 +753,14 @@ static void arm_smmu_v3_invs_test(struct kunit *test) /* Test8: merge invs4 (new array) */ test_b =3D arm_smmu_invs_merge(test_a, &invs4); kfree(test_a); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, test_b); arm_smmu_v3_invs_test_verify(test, test_b, ARRAY_SIZE(results7[0]), 0, results7[0], results7[1], results7[2]); =20 /* Test9: merge invs5 (new array) */ test_a =3D arm_smmu_invs_merge(test_b, &invs5); kfree(test_b); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, test_a); arm_smmu_v3_invs_test_verify(test, test_a, ARRAY_SIZE(results8[0]), 0, results8[0], results8[1], results8[2]); =20 @@ -765,6 +772,7 @@ static void arm_smmu_v3_invs_test(struct kunit *test) /* Test11: purge test_a (new array) */ test_b =3D arm_smmu_invs_purge(test_a); kfree(test_a); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, test_b); arm_smmu_v3_invs_test_verify(test, test_b, ARRAY_SIZE(results10[0]), 0, results10[0], results10[1], results10[2]); =20 --=20 2.56.0.rc1.315.gc6ed9934b7-goog From nobody Thu Sep 24 12:02:45 2026 Received: from mail-ed1-f72.google.com (mail-ed1-f72.google.com [209.85.208.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA351442B15 for ; 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Thu, 24 Sep 2026 01:56:29 -0700 (PDT) Date: Thu, 24 Sep 2026 08:56:15 +0000 In-Reply-To: <20260924085616.300650-1-smostafa@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260924085616.300650-1-smostafa@google.com> X-Mailer: git-send-email 2.56.0.rc1.315.gc6ed9934b7-goog Message-ID: <20260924085616.300650-5-smostafa@google.com> Subject: [PATCH v2 4/5] iommu/arm-smmu-v3-test: Fix OOB in arm_smmu_v3_invs_test_verify() From: Mostafa Saleh To: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, jgg@ziepe.ca, nicolinc@nvidia.com, praan@google.com, Mostafa Saleh , Jason Gunthorpe Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" arm_smmu_v3_invs_test_verify() validates the array bounds using KUNIT_EXPECT_EQ(), which triggers a failure and continues execution. If invs->num_invs was smaller than expected, the next loop over num_invs would blindly read past the end of the invs->inv[] array. Switch to KUNIT_ASSERT_EQ() to fail and stop the test on bound errors. Fixes: 15a2a5645ad7 ("iommu/arm-smmu-v3: Introduce a per-domain arm_smmu_in= vs array") Reported-by: Sashiko <> Reviewed-by: Nicolin Chen Reviewed-by: Jason Gunthorpe Signed-off-by: Mostafa Saleh --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index 366dcb2b5554..244cf34e5a0b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -643,7 +643,7 @@ static void arm_smmu_v3_invs_test_verify(struct kunit *= test, const int *ids, const int *users, const int *ssids) { - KUNIT_EXPECT_EQ(test, invs->num_invs, num_invs); + KUNIT_ASSERT_EQ(test, invs->num_invs, num_invs); KUNIT_EXPECT_EQ(test, invs->num_trashes, num_trashes); while (num_invs--) { KUNIT_EXPECT_EQ(test, invs->inv[num_invs].id, ids[num_invs]); --=20 2.56.0.rc1.315.gc6ed9934b7-goog From nobody Thu Sep 24 12:02:45 2026 Received: from mail-wm1-f70.google.com (mail-wm1-f70.google.com [209.85.128.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF4DC443C21 for ; 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Thu, 24 Sep 2026 01:56:30 -0700 (PDT) Date: Thu, 24 Sep 2026 08:56:16 +0000 In-Reply-To: <20260924085616.300650-1-smostafa@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260924085616.300650-1-smostafa@google.com> X-Mailer: git-send-email 2.56.0.rc1.315.gc6ed9934b7-goog Message-ID: <20260924085616.300650-6-smostafa@google.com> Subject: [PATCH v2 5/5] iommu/arm-smmu-v3-test: Fix UBSAN error From: Mostafa Saleh To: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, jgg@ziepe.ca, nicolinc@nvidia.com, praan@google.com, Mostafa Saleh , Jason Gunthorpe Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" struct arm_smmu_invs marks its flexible array member inv[] with the __counted_by(max_invs). arm_smmu_v3_invs_test() uses invs1 to invs5 which has num_invs =3D 3 but omit max_invs. This causes the following UBSAN error: [ 2.333240] UBSAN: array-index-out-of-bounds in drivers/iommu/arm/arm-sm= mu-v3/arm-smmu-v3.c:1116:21 [ 2.333604] # arm_smmu_v3_invs_test: lib/ubsan.c:228: array-index-ou= t-of-bounds in drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c [ 2.334129] index 1 is out of range for type 'struct arm_smmu_inv[] __co= unted_by(max_invs)' (aka 'struct arm_smmu_inv[]') [ 2.335375] CPU: 6 UID: 0 PID: 155 Comm: kunit_try_catch Tainted: G = N 7.2.0-g8dcb331fbb72 #2 PREEMPT [ 2.335759] Tainted: [N]=3DTEST [ 2.335791] Hardware name: linux,dummy-virt (DT) [ 2.336254] Call trace: [ 2.336932] show_stack+0x18/0x24 (C) [ 2.338443] __dump_stack+0x28/0x38 [ 2.338494] dump_stack_lvl+0x54/0x6c [ 2.338518] dump_stack+0x18/0x24 [ 2.338541] ubsan_epilogue+0x10/0x44 [ 2.338565] __ubsan_handle_out_of_bounds+0xb8/0xbc [ 2.338834] arm_smmu_invs_merge+0x688/0x8ac [ 2.338862] arm_smmu_v3_invs_test+0xd4/0x598 [ 2.338890] kunit_try_run_case+0x64/0x160 [ 2.338914] kunit_generic_run_threadfn_adapter+0x28/0x4c [ 2.338955] kthread+0x10c/0x12c [ 2.338984] ret_from_fork+0x10/0x20 [ 2.339433] ---[ end trace ]--- Explicitly set max_invs =3D 3 on the test arrays to match the number of elements. Fixes: 15a2a5645ad7 ("iommu/arm-smmu-v3: Introduce a per-domain arm_smmu_in= vs array") Reviewed-by: Nicolin Chen Reviewed-by: Jason Gunthorpe Signed-off-by: Mostafa Saleh --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index 244cf34e5a0b..e52a7d95c919 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -654,6 +654,7 @@ static void arm_smmu_v3_invs_test_verify(struct kunit *= test, } =20 static struct arm_smmu_invs invs1 =3D { + .max_invs =3D 3, .num_invs =3D 3, .inv =3D { { .type =3D INV_TYPE_S2_VMID, .id =3D 1, }, { .type =3D INV_TYPE_S2_VMID_S1_CLEAR, .id =3D 1, }, @@ -661,6 +662,7 @@ static struct arm_smmu_invs invs1 =3D { }; =20 static struct arm_smmu_invs invs2 =3D { + .max_invs =3D 3, .num_invs =3D 3, .inv =3D { { .type =3D INV_TYPE_S2_VMID, .id =3D 1, }, /* duplicated */ { .type =3D INV_TYPE_ATS, .id =3D 4, }, @@ -668,6 +670,7 @@ static struct arm_smmu_invs invs2 =3D { }; =20 static struct arm_smmu_invs invs3 =3D { + .max_invs =3D 3, .num_invs =3D 3, .inv =3D { { .type =3D INV_TYPE_S2_VMID, .id =3D 1, }, /* duplicated */ { .type =3D INV_TYPE_ATS, .id =3D 5, }, /* recover a trash */ @@ -675,6 +678,7 @@ static struct arm_smmu_invs invs3 =3D { }; =20 static struct arm_smmu_invs invs4 =3D { + .max_invs =3D 3, .num_invs =3D 3, .inv =3D { { .type =3D INV_TYPE_ATS, .id =3D 10, .ssid =3D 1 }, { .type =3D INV_TYPE_ATS, .id =3D 10, .ssid =3D 3 }, @@ -682,6 +686,7 @@ static struct arm_smmu_invs invs4 =3D { }; =20 static struct arm_smmu_invs invs5 =3D { + .max_invs =3D 3, .num_invs =3D 3, .inv =3D { { .type =3D INV_TYPE_ATS, .id =3D 10, .ssid =3D 2 }, { .type =3D INV_TYPE_ATS, .id =3D 10, .ssid =3D 3 }, /* duplicate */ --=20 2.56.0.rc1.315.gc6ed9934b7-goog