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(unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id BFEB15B6950; Thu, 24 Sep 2026 01:26:21 -0700 (PDT) From: Ratheesh Kannoth To: , CC: , , , , , , "Ratheesh Kannoth" Subject: [PATCH v3 net-next] octeontx2-af: pass devlink switch id and cache representor map Date: Thu, 24 Sep 2026 13:56:14 +0530 Message-ID: <20260924082614.1947742-1-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI0MDAzNSBTYWx0ZWRfX67vcAB6uZ93m i7VgjB1/2zEZQ2Rd7QEJrrKhqCmElie3GrkbZdU/7bE3kHJ3RXIjSph0RAmdv9AQ7DqMuA9kgFM t1x8fjaViNJ/tnehsd7hZ3veQL5ib6Q= X-Authority-Analysis: v=2.4 cv=fcI4WEQF c=1 sm=1 tr=0 ts=6ab4deb2 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=VdqzKS8jKosA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=qit2iCtTFQkLgVSMPQTB:22 a=VwQbUJbxAAAA:8 a=QyXUC8HyAAAA:8 a=M5GUcnROAAAA:8 a=gqSagxGxYvX-DtDPPjEA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI0MDAzNSBTYWx0ZWRfXwdF08/qnpfhD bDeB7WKCKNcKBXk9U/rcAxRUNjqqA7AJKjzNAglHGMlHc4HV0k494wrgp3lgU0BbZhb2H4OBilX 7HMNd2PbRo65awIpRULE4y3h3Ws47JCPeZaxK/XXnBfcPkdkXnuJebt/tCzwBywh6G8FI7qPcSU Q5fGZt32c+X8bIqgJ7+qnsJ2t7m/wznIsP5zdpFCpLOuKymPddWXfgCCLR8ARYPawNiGT4Ud8Nt 5OKtx6A8pM30CPuQnGxMA/si/iHclPg00aGoIloN0tOtyIqDDpOQs4H5teWH0ywABHeOZbKhVvL jLoRW93aYmKgSw5OMqXLk1EE+Dr/Q633rtHu/np1nOBubhYa82Xewq55xdLwfTsTHRHph7oT+bW 2Ucylpf4K9AHg+CJVSdJBZhlt9DLPdSYA+sLJCopWPdxqL2RZovXrSSSCg7bzL74O73lf0AmHWA 9dsTkqqlK6LTNgJgmfA== X-Proofpoint-GUID: Xm2j5ZUcs6lQjr7EKHT8XuMhEapxVJY4 X-Proofpoint-ORIG-GUID: Xm2j5ZUcs6lQjr7EKHT8XuMhEapxVJY4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-24_02,2026-09-21_02,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Extend MBOX_MSG_ESW_CFG with the representor devlink switch_id and store it in the AF. Build rep2pfvf_map once on GET_REP_CNT, always refresh rep_pcifunc, and protect map access with rsrc_lock. Reset the cache on eswitch disable and representor FLR. Add rvu_sw_port_id() and share the representor index lookup with rvu_rep_get_vlan_id(). Signed-off-by: Ratheesh Kannoth --- v2 -> v3: - Fix compilation issue. https://lore.kernel.org/netdev/202609241557.82GuIoAK-lkp@intel.com/ v1 -> v2: - Always refresh rep_pcifunc on GET_REP_CNT instead of pinning it to the first caller. - Replace the READ_ONCE/WRITE_ONCE rep2pfvf_map fast path with rvu_rep_lookup_id() lookups under rsrc_lock. - Add rvu_rep_cache_reset() and call it on eswitch disable and representor FLR so the cached map and switch_id are torn down. - Ignore redundant ESW_CFG enable/disable requests when the mode is already in the requested state. - Validate switch_id length before allocating the ESW_CFG mailbox message. - Build the representor map from rvu_rep_create() via rvu_get_rep_cnt(). - Drop the ESW_CFG wire-format comment block; the layout change is carried only by the struct fields. - Factor rvu_rep_get_vlan_id() and rvu_sw_port_id() through a shared rvu_rep_lookup_id() helper. https://lore.kernel.org/netdev/20260918050021.1359606-1-rkannoth@marvell.= com/ --- .../net/ethernet/marvell/octeontx2/af/mbox.h | 2 + .../net/ethernet/marvell/octeontx2/af/rvu.c | 3 + .../net/ethernet/marvell/octeontx2/af/rvu.h | 9 ++ .../ethernet/marvell/octeontx2/af/rvu_rep.c | 117 +++++++++++++++--- .../net/ethernet/marvell/octeontx2/nic/rep.c | 81 ++++++------ 5 files changed, 160 insertions(+), 52 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index cece197d1074..45c03f9294a5 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -1788,6 +1788,8 @@ struct esw_cfg_req { struct mbox_msghdr hdr; u8 ena; u64 rsvd; + unsigned char switch_id[MAX_PHYS_ITEM_ID_LEN]; + u8 switch_id_len; }; =20 struct rep_evt_data { diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.c index 30e148291581..aeb6b4917f45 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c @@ -2924,6 +2924,9 @@ static void __rvu_flr_handler(struct rvu *rvu, u16 pc= ifunc) if (rvu->mcs_blk_cnt) rvu_mcs_flr_handler(rvu, pcifunc); =20 + if (is_rep_dev(rvu, pcifunc)) + rvu_rep_cache_reset(rvu); + mutex_unlock(&rvu->flr_lock); } =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.h index fb4870cd18e9..d5f69cba6d41 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -570,6 +570,7 @@ struct npc_kpu_profile_adapter { }; =20 #define RVU_SWITCH_LBK_CHAN 63 +#define RVU_SW_INVALID_PORT_ID ((u32)~0U) =20 struct rvu_switch { struct mutex switch_lock; /* Serialize flow installation */ @@ -577,6 +578,11 @@ struct rvu_switch { u16 *entry2pcifunc; u16 mode; u16 start_entry; + unsigned char switch_id[MAX_PHYS_ITEM_ID_LEN]; + u8 switch_id_len; +#define RVU_SWITCH_FLAG_FW_READY BIT_ULL(0) + u64 flags; + u16 pcifunc; }; =20 struct rep_evtq_ent { @@ -1194,9 +1200,12 @@ void rvu_mcs_ptp_cfg(struct rvu *rvu, u8 rpm_id, u8 = lmac_id, bool ena); void rvu_mcs_exit(struct rvu *rvu); =20 /* Representor APIs */ +void rvu_rep_cache_reset(struct rvu *rvu); int rvu_rep_pf_init(struct rvu *rvu); int rvu_rep_install_mcam_rules(struct rvu *rvu); void rvu_rep_update_rules(struct rvu *rvu, u16 pcifunc, bool ena); int rvu_rep_notify_pfvf_state(struct rvu *rvu, u16 pcifunc, bool enable); int npc_mcam_verify_entry(struct npc_mcam *mcam, u16 pcifunc, int entry); +u16 rvu_rep_get_vlan_id(struct rvu *rvu, u16 pcifunc); +u32 rvu_sw_port_id(struct rvu *rvu, u16 pcifunc); #endif /* RVU_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_rep.c index a2781e0f504e..a3ad45f46742 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c @@ -6,6 +6,7 @@ */ =20 #include +#include #include #include #include @@ -189,14 +190,47 @@ int rvu_mbox_handler_nix_lf_stats(struct rvu *rvu, return 0; } =20 -static u16 rvu_rep_get_vlan_id(struct rvu *rvu, u16 pcifunc) +static bool rvu_rep_lookup_id(struct rvu *rvu, u16 pcifunc, u16 *rep_id) { - int id; + u16 *map; + int id, cnt; + bool found =3D false; + + mutex_lock(&rvu->rsrc_lock); + map =3D rvu->rep2pfvf_map; + cnt =3D rvu->rep_cnt; + if (map && cnt) { + for (id =3D 0; id < cnt; id++) { + if (map[id] =3D=3D pcifunc) { + *rep_id =3D id; + found =3D true; + break; + } + } + } + mutex_unlock(&rvu->rsrc_lock); =20 - for (id =3D 0; id < rvu->rep_cnt; id++) - if (rvu->rep2pfvf_map[id] =3D=3D pcifunc) - return id; - return 0; + return found; +} + +u16 rvu_rep_get_vlan_id(struct rvu *rvu, u16 pcifunc) +{ + u16 rep_id; + + if (!rvu_rep_lookup_id(rvu, pcifunc, &rep_id)) + return 0; + return rep_id; +} + +u32 rvu_sw_port_id(struct rvu *rvu, u16 pcifunc) +{ + u16 rep_id; + + if (!rvu_rep_lookup_id(rvu, pcifunc, &rep_id)) + return RVU_SW_INVALID_PORT_ID; + + return FIELD_PREP(GENMASK_ULL(31, 16), rep_id) | + FIELD_PREP(GENMASK_ULL(15, 0), pcifunc); } =20 static int rvu_rep_tx_vlan_cfg(struct rvu *rvu, u16 pcifunc, @@ -429,16 +463,48 @@ int rvu_rep_pf_init(struct rvu *rvu) return 0; } =20 +void rvu_rep_cache_reset(struct rvu *rvu) +{ + u16 *map; + + mutex_lock(&rvu->rsrc_lock); + rvu->rep_mode =3D 0; + rvu->rep_pcifunc =3D 0; + map =3D rvu->rep2pfvf_map; + rvu->rep_cnt =3D 0; + rvu->rep2pfvf_map =3D NULL; + memset(rvu->rswitch.switch_id, 0, sizeof(rvu->rswitch.switch_id)); + rvu->rswitch.switch_id_len =3D 0; + mutex_unlock(&rvu->rsrc_lock); + + devm_kfree(rvu->dev, map); +} + int rvu_mbox_handler_esw_cfg(struct rvu *rvu, struct esw_cfg_req *req, struct msg_rsp *rsp) { if (req->hdr.pcifunc !=3D rvu->rep_pcifunc) return 0; =20 + if (rvu->rep_mode && req->ena) + return 0; + + if (!rvu->rep_mode && !req->ena) + return 0; + rvu->rep_mode =3D req->ena; + memset(rvu->rswitch.switch_id, 0, sizeof(rvu->rswitch.switch_id)); + rvu->rswitch.switch_id_len =3D 0; + if (req->switch_id_len && req->switch_id_len <=3D MAX_PHYS_ITEM_ID_LEN) { + memcpy(rvu->rswitch.switch_id, req->switch_id, + req->switch_id_len); + rvu->rswitch.switch_id_len =3D req->switch_id_len; + } =20 - if (!rvu->rep_mode) + if (!rvu->rep_mode) { rvu_npc_free_mcam_entries(rvu, req->hdr.pcifunc, -1); + rvu_rep_cache_reset(rvu); + } =20 return 0; } @@ -447,31 +513,48 @@ int rvu_mbox_handler_get_rep_cnt(struct rvu *rvu, str= uct msg_req *req, struct get_rep_cnt_rsp *rsp) { int pf, vf, numvfs, hwvf, rep =3D 0; - u16 pcifunc; + u16 pcifunc, rep_cnt; + u16 *map; + + mutex_lock(&rvu->rsrc_lock); =20 rvu->rep_pcifunc =3D req->hdr.pcifunc; - rsp->rep_cnt =3D rvu->cgx_mapped_pfs + rvu->cgx_mapped_vfs; - rvu->rep_cnt =3D rsp->rep_cnt; =20 - rvu->rep2pfvf_map =3D devm_kzalloc(rvu->dev, rvu->rep_cnt * - sizeof(u16), GFP_KERNEL); - if (!rvu->rep2pfvf_map) + if (rvu->rep2pfvf_map) { + rsp->rep_cnt =3D rvu->rep_cnt; + for (rep =3D 0; rep < rvu->rep_cnt; rep++) + rsp->rep_pf_map[rep] =3D rvu->rep2pfvf_map[rep]; + mutex_unlock(&rvu->rsrc_lock); + return 0; + } + + rep_cnt =3D rvu->cgx_mapped_pfs + rvu->cgx_mapped_vfs; + map =3D devm_kzalloc(rvu->dev, rep_cnt * sizeof(u16), GFP_KERNEL); + if (!map) { + mutex_unlock(&rvu->rsrc_lock); return -ENOMEM; + } =20 for (pf =3D 0; pf < rvu->hw->total_pfs; pf++) { if (!is_pf_cgxmapped(rvu, pf)) continue; pcifunc =3D rvu_make_pcifunc(rvu->pdev, pf, 0); - rvu->rep2pfvf_map[rep] =3D pcifunc; + map[rep] =3D pcifunc; rsp->rep_pf_map[rep] =3D pcifunc; rep++; rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); for (vf =3D 0; vf < numvfs; vf++) { - rvu->rep2pfvf_map[rep] =3D pcifunc | - ((vf + 1) & RVU_PFVF_FUNC_MASK); - rsp->rep_pf_map[rep] =3D rvu->rep2pfvf_map[rep]; + map[rep] =3D pcifunc | ((vf + 1) & RVU_PFVF_FUNC_MASK); + rsp->rep_pf_map[rep] =3D map[rep]; rep++; } } + + rvu->rep_cnt =3D rep_cnt; + rvu->rep2pfvf_map =3D map; + rsp->rep_cnt =3D rep_cnt; + + mutex_unlock(&rvu->rsrc_lock); + return 0; } diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c b/drivers/net= /ethernet/marvell/octeontx2/nic/rep.c index 0f5d5642d3f7..80b47bb333b7 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/rep.c @@ -399,8 +399,13 @@ static void rvu_rep_get_stats64(struct net_device *dev, =20 static int rvu_eswitch_config(struct otx2_nic *priv, u8 ena) { + struct devlink_port_attrs attrs =3D {}; struct esw_cfg_req *req; =20 + rvu_rep_devlink_set_switch_id(priv, &attrs.switch_id); + if (attrs.switch_id.id_len > MAX_PHYS_ITEM_ID_LEN) + return -EINVAL; + mutex_lock(&priv->mbox.lock); req =3D otx2_mbox_alloc_msg_esw_cfg(&priv->mbox); if (!req) { @@ -408,6 +413,8 @@ static int rvu_eswitch_config(struct otx2_nic *priv, u8= ena) return -ENOMEM; } req->ena =3D ena; + req->switch_id_len =3D attrs.switch_id.id_len; + memcpy(req->switch_id, attrs.switch_id.id, req->switch_id_len); otx2_sync_mbox_msg(&priv->mbox); mutex_unlock(&priv->mbox.lock); return 0; @@ -645,6 +652,41 @@ void rvu_rep_destroy(struct otx2_nic *priv) rvu_rep_rsrc_free(priv); } =20 +static int rvu_get_rep_cnt(struct otx2_nic *priv) +{ + struct get_rep_cnt_rsp *rsp; + struct mbox_msghdr *msghdr; + struct msg_req *req; + int err, rep; + + mutex_lock(&priv->mbox.lock); + req =3D otx2_mbox_alloc_msg_get_rep_cnt(&priv->mbox); + if (!req) { + mutex_unlock(&priv->mbox.lock); + return -ENOMEM; + } + err =3D otx2_sync_mbox_msg(&priv->mbox); + if (err) + goto exit; + + msghdr =3D otx2_mbox_get_rsp(&priv->mbox.mbox, 0, &req->hdr); + if (IS_ERR(msghdr)) { + err =3D PTR_ERR(msghdr); + goto exit; + } + + rsp =3D (struct get_rep_cnt_rsp *)msghdr; + priv->hw.tx_queues =3D rsp->rep_cnt; + priv->hw.rx_queues =3D rsp->rep_cnt; + priv->rep_cnt =3D rsp->rep_cnt; + for (rep =3D 0; rep < priv->rep_cnt; rep++) + priv->rep_pf_map[rep] =3D rsp->rep_pf_map[rep]; + +exit: + mutex_unlock(&priv->mbox.lock); + return err; +} + int rvu_rep_create(struct otx2_nic *priv, struct netlink_ext_ack *extack) { int rep_cnt =3D priv->rep_cnt; @@ -653,6 +695,10 @@ int rvu_rep_create(struct otx2_nic *priv, struct netli= nk_ext_ack *extack) int rep_id, err; u16 pcifunc; =20 + err =3D rvu_get_rep_cnt(priv); + if (err) + return err; + err =3D rvu_rep_rsrc_init(priv); if (err) return -ENOMEM; @@ -730,41 +776,6 @@ int rvu_rep_create(struct otx2_nic *priv, struct netli= nk_ext_ack *extack) return err; } =20 -static int rvu_get_rep_cnt(struct otx2_nic *priv) -{ - struct get_rep_cnt_rsp *rsp; - struct mbox_msghdr *msghdr; - struct msg_req *req; - int err, rep; - - mutex_lock(&priv->mbox.lock); - req =3D otx2_mbox_alloc_msg_get_rep_cnt(&priv->mbox); - if (!req) { - mutex_unlock(&priv->mbox.lock); - return -ENOMEM; - } - err =3D otx2_sync_mbox_msg(&priv->mbox); - if (err) - goto exit; - - msghdr =3D otx2_mbox_get_rsp(&priv->mbox.mbox, 0, &req->hdr); - if (IS_ERR(msghdr)) { - err =3D PTR_ERR(msghdr); - goto exit; - } - - rsp =3D (struct get_rep_cnt_rsp *)msghdr; - priv->hw.tx_queues =3D rsp->rep_cnt; - priv->hw.rx_queues =3D rsp->rep_cnt; - priv->rep_cnt =3D rsp->rep_cnt; - for (rep =3D 0; rep < priv->rep_cnt; rep++) - priv->rep_pf_map[rep] =3D rsp->rep_pf_map[rep]; - -exit: - mutex_unlock(&priv->mbox.lock); - return err; -} - static int rvu_rep_probe(struct pci_dev *pdev, const struct pci_device_id = *id) { struct device *dev =3D &pdev->dev; --=20 2.43.0