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charset="utf-8" Subsequent patch adds IBS Memory Profiler driver that is independent of the perf subsystem but needs the CPUID 0x8000001B capability bits. Hence move those bit definitions out of asm/perf_event.h into a dedicated header so the new driver can consume them without pulling in perf. Signed-off-by: Bharata B Rao --- arch/x86/include/asm/ibs-caps.h | 85 +++++++++++++++++++++++++++++++ arch/x86/include/asm/perf_event.h | 81 +---------------------------- 2 files changed, 86 insertions(+), 80 deletions(-) create mode 100644 arch/x86/include/asm/ibs-caps.h diff --git a/arch/x86/include/asm/ibs-caps.h b/arch/x86/include/asm/ibs-cap= s.h new file mode 100644 index 000000000000..ddf6c512c8f9 --- /dev/null +++ b/arch/x86/include/asm/ibs-caps.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_IBS_CAPS_H +#define _ASM_X86_IBS_CAPS_H + +/* + * IBS cpuid feature detection + */ + +#define IBS_CPUID_FEATURES 0x8000001b + +/* + * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but + * bit 0 is used to indicate the existence of IBS. + */ +#define IBS_CAPS_AVAIL (1U<<0) +#define IBS_CAPS_FETCHSAM (1U<<1) +#define IBS_CAPS_OPSAM (1U<<2) +#define IBS_CAPS_RDWROPCNT (1U<<3) +#define IBS_CAPS_OPCNT (1U<<4) +#define IBS_CAPS_BRNTRGT (1U<<5) +#define IBS_CAPS_OPCNTEXT (1U<<6) +#define IBS_CAPS_RIPINVALIDCHK (1U<<7) +#define IBS_CAPS_OPBRNFUSE (1U<<8) +#define IBS_CAPS_FETCHCTLEXTD (1U<<9) +#define IBS_CAPS_OPDATA4 (1U<<10) +#define IBS_CAPS_ZEN4 (1U<<11) +#define IBS_CAPS_OPLDLAT (1U<<12) +#define IBS_CAPS_DIS (1U<<13) +#define IBS_CAPS_FETCHLAT (1U<<14) +#define IBS_CAPS_BIT63_FILTER (1U<<15) +#define IBS_CAPS_STRMST_RMTSOCKET (1U<<16) +#define IBS_CAPS_OPDTLBPGSIZE (1U<<19) + +#define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \ + | IBS_CAPS_FETCHSAM \ + | IBS_CAPS_OPSAM) + +/* + * IBS APIC setup + */ +#define IBSCTL 0x1cc +#define IBSCTL_LVT_OFFSET_VALID (1ULL<<8) +#define IBSCTL_LVT_OFFSET_MASK 0x0F + +/* IBS fetch bits/masks */ +#define IBS_FETCH_L3MISSONLY (1ULL << 59) +#define IBS_FETCH_RAND_EN (1ULL << 57) +#define IBS_FETCH_VAL (1ULL << 49) +#define IBS_FETCH_ENABLE (1ULL << 48) +#define IBS_FETCH_CNT 0xFFFF0000ULL +#define IBS_FETCH_MAX_CNT 0x0000FFFFULL + +#define IBS_FETCH_2_DIS (1ULL << 0) +#define IBS_FETCH_2_FETCHLAT_FILTER (0xFULL << 1) +#define IBS_FETCH_2_FETCHLAT_FILTER_SHIFT (1) +#define IBS_FETCH_2_EXCL_RIP_63_EQ_1 (1ULL << 5) +#define IBS_FETCH_2_EXCL_RIP_63_EQ_0 (1ULL << 6) + +/* + * IBS op bits/masks + * The lower 7 bits of the current count are random bits + * preloaded by hardware and ignored in software + */ +#define IBS_OP_LDLAT_EN (1ULL << 63) +#define IBS_OP_LDLAT_THRSH (0xFULL << 59) +#define IBS_OP_LDLAT_THRSH_SHIFT (59) +#define IBS_OP_CUR_CNT (0xFFF80ULL << 32) +#define IBS_OP_CUR_CNT_RAND (0x0007FULL << 32) +#define IBS_OP_CUR_CNT_EXT_MASK (0x7FULL << 52) +#define IBS_OP_CNT_CTL (1ULL << 19) +#define IBS_OP_VAL (1ULL << 18) +#define IBS_OP_ENABLE (1ULL << 17) +#define IBS_OP_L3MISSONLY (1ULL << 16) +#define IBS_OP_MAX_CNT 0x0000FFFFULL +#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask = */ +#define IBS_OP_MAX_CNT_EXT_MASK (0x7FULL << 20) /* separate upper 7 bi= ts */ +#define IBS_RIP_INVALID (1ULL << 38) + +#define IBS_OP_2_DIS (1ULL << 0) +#define IBS_OP_2_EXCL_RIP_63_EQ_0 (1ULL << 1) +#define IBS_OP_2_EXCL_RIP_63_EQ_1 (1ULL << 2) +#define IBS_OP_2_STRM_ST_FILTER (1ULL << 3) +#define IBS_OP_2_STRM_ST_FILTER_SHIFT (3) + +#endif /* _ASM_X86_IBS_CAPS_H */ diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 1eb13673e889..de18e63c5c3e 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -3,6 +3,7 @@ #define _ASM_X86_PERF_EVENT_H =20 #include +#include =20 /* * Performance event hw details: @@ -622,86 +623,6 @@ struct arch_pebs_cntr_header { */ #define EXT_PERFMON_DEBUG_FEATURES 0x80000022 =20 -/* - * IBS cpuid feature detection - */ - -#define IBS_CPUID_FEATURES 0x8000001b - -/* - * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but - * bit 0 is used to indicate the existence of IBS. - */ -#define IBS_CAPS_AVAIL (1U<<0) -#define IBS_CAPS_FETCHSAM (1U<<1) -#define IBS_CAPS_OPSAM (1U<<2) -#define IBS_CAPS_RDWROPCNT (1U<<3) -#define IBS_CAPS_OPCNT (1U<<4) -#define IBS_CAPS_BRNTRGT (1U<<5) -#define IBS_CAPS_OPCNTEXT (1U<<6) -#define IBS_CAPS_RIPINVALIDCHK (1U<<7) -#define IBS_CAPS_OPBRNFUSE (1U<<8) -#define IBS_CAPS_FETCHCTLEXTD (1U<<9) -#define IBS_CAPS_OPDATA4 (1U<<10) -#define IBS_CAPS_ZEN4 (1U<<11) -#define IBS_CAPS_OPLDLAT (1U<<12) -#define IBS_CAPS_DIS (1U<<13) -#define IBS_CAPS_FETCHLAT (1U<<14) -#define IBS_CAPS_BIT63_FILTER (1U<<15) -#define IBS_CAPS_STRMST_RMTSOCKET (1U<<16) -#define IBS_CAPS_OPDTLBPGSIZE (1U<<19) - -#define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \ - | IBS_CAPS_FETCHSAM \ - | IBS_CAPS_OPSAM) - -/* - * IBS APIC setup - */ -#define IBSCTL 0x1cc -#define IBSCTL_LVT_OFFSET_VALID (1ULL<<8) -#define IBSCTL_LVT_OFFSET_MASK 0x0F - -/* IBS fetch bits/masks */ -#define IBS_FETCH_L3MISSONLY (1ULL << 59) -#define IBS_FETCH_RAND_EN (1ULL << 57) -#define IBS_FETCH_VAL (1ULL << 49) -#define IBS_FETCH_ENABLE (1ULL << 48) -#define IBS_FETCH_CNT 0xFFFF0000ULL -#define IBS_FETCH_MAX_CNT 0x0000FFFFULL - -#define IBS_FETCH_2_DIS (1ULL << 0) -#define IBS_FETCH_2_FETCHLAT_FILTER (0xFULL << 1) -#define IBS_FETCH_2_FETCHLAT_FILTER_SHIFT (1) -#define IBS_FETCH_2_EXCL_RIP_63_EQ_1 (1ULL << 5) -#define IBS_FETCH_2_EXCL_RIP_63_EQ_0 (1ULL << 6) - -/* - * IBS op bits/masks - * The lower 7 bits of the current count are random bits - * preloaded by hardware and ignored in software - */ -#define IBS_OP_LDLAT_EN (1ULL << 63) -#define IBS_OP_LDLAT_THRSH (0xFULL << 59) -#define IBS_OP_LDLAT_THRSH_SHIFT (59) -#define IBS_OP_CUR_CNT (0xFFF80ULL << 32) -#define IBS_OP_CUR_CNT_RAND (0x0007FULL << 32) -#define IBS_OP_CUR_CNT_EXT_MASK (0x7FULL << 52) -#define IBS_OP_CNT_CTL (1ULL << 19) -#define IBS_OP_VAL (1ULL << 18) -#define IBS_OP_ENABLE (1ULL << 17) -#define IBS_OP_L3MISSONLY (1ULL << 16) -#define IBS_OP_MAX_CNT 0x0000FFFFULL -#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask = */ -#define IBS_OP_MAX_CNT_EXT_MASK (0x7FULL << 20) /* separate upper 7 bi= ts */ -#define IBS_RIP_INVALID (1ULL << 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da4a502f-616c-4ddf-1f53-08df1a04514a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F43.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7616 Content-Type: text/plain; charset="utf-8" Use IBS (Instruction Based Sampling) Memory Profiler feature present in AMD Zen6 processors for memory access tracking. The access information obtained from IBS Memory Profiler is fed to pghot sub-system for further action using pghot_record_access(PGHOT_HWHINTS, ...) API. IBS Memory Profiler as page hotness source is enabled by the new config option HWMEM_PROFILER. New system vector 0xea is used for memprofiler interrupt. This commit adds the driver infrastructure (interrupt setup, per-CPU ring, workqueue, cpuhp state, pghot call site etc) but the profiler isn't armed yet and that is done in the next commit. Register cpuhp on CPUHP_AP_ONLINE_DYN (after workqueue online) so offline teardown disarms the producer and flush_work() runs while the per-CPU worker is still bound, before workqueue unbind. More details about IBS Memory Profiler can be obtained from the AMD document titled "AMD64 Zen6 Instruction Based Sampling (IBS) Extensions and Features". Signed-off-by: Bharata B Rao --- Documentation/admin-guide/mm/pghot.rst | 42 +++ arch/x86/Kconfig | 16 + arch/x86/entry/entry_fred.c | 1 + arch/x86/include/asm/hardirq.h | 3 + arch/x86/include/asm/ibs-caps.h | 8 + arch/x86/include/asm/ibs-mprof.h | 47 +++ arch/x86/include/asm/idtentry.h | 6 + arch/x86/include/asm/irq_vectors.h | 4 +- arch/x86/include/asm/msr-index.h | 8 + arch/x86/kernel/idt.c | 3 + arch/x86/kernel/irq.c | 3 + arch/x86/mm/Makefile | 1 + arch/x86/mm/ibs-mprof.c | 482 +++++++++++++++++++++++++ include/linux/vm_event_item.h | 8 + mm/Kconfig | 9 + mm/vmstat.c | 8 + 16 files changed, 648 insertions(+), 1 deletion(-) create mode 100644 arch/x86/include/asm/ibs-mprof.h create mode 100644 arch/x86/mm/ibs-mprof.c diff --git a/Documentation/admin-guide/mm/pghot.rst b/Documentation/admin-g= uide/mm/pghot.rst index c7242dc04ea2..df8316175207 100644 --- a/Documentation/admin-guide/mm/pghot.rst +++ b/Documentation/admin-guide/mm/pghot.rst @@ -117,3 +117,45 @@ This source is enabled by default through the hint fau= lts bit (0x1) of to promote hot pages. It can be disabled at runtime by clearing that bit: =20 # echo 0x0 > /proc/sys/vm/pghot_enabled_sources + +Hardware Hints Source +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +pghot can consume memory access samples reported by hardware profilers. +This "hardware hints" (hwhints) source feeds hardware-observed accesses +into pghot for hot page detection and promotion. + +Generic in-kernel support for such profilers is controlled by the +HWMEM_PROFILER config option. It is not enabled directly by the user; +an in-kernel driver that forwards hardware-observed accesses to pghot +selects it. + +The AMD IBS Memory Profiler (config AMD_IBS_MEMPROF, available on Zen6 +and later AMD CPUs) is one such driver. It uses the AMD Instruction +Based Sampling (IBS) Memory Profiler facility to sample user memory +accesses and record them with pghot. + +This source can be activated at runtime through the hardware +hints bit (0x2) of **pghot_enabled_sources**. + +# echo 0x2 > /proc/sys/vm/pghot_enabled_sources + +HWHINTS Vmstat Counters +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Following vmstat counters provide some stats about hardware hints source. + +Path: /proc/vmstat + +1. **hwhint_total_events** + - Number of total hwhint events recorded by hwhints source. + +2. **hwhint_useful_events** + - Number of actionable events from hwhints source. + +3. **hwhint_dropped_events** + - Number of events that were dropped due to buffer overrun. + +4. **hwhint_dram_accesses** + - Number of DRAM accesses reported by hwhints source. + +5. **hwhint_extmem_accesses** + - Number of external memory (like CXL) accesses reported by hwhints sou= rce. diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 15fd9ec5ecac..a25fbe201840 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1505,6 +1505,22 @@ config AMD_MEM_ENCRYPT This requires an AMD processor that supports Secure Memory Encryption (SME). =20 +config AMD_IBS_MEMPROF + bool "AMD IBS Memory Profiler" + depends on X86_64 && CPU_SUP_AMD + depends on PGHOT + select HWMEM_PROFILER + help + Use the AMD Instruction Based Sampling (IBS) Memory Profiler + facility (present on Zen6 and later AMD CPUs) to feed + hardware-observed memory accesses into the pghot subsystem + for hot-page detection and promotion. + + When disabled, no IBS Memory Profiler MSRs are programmed and + the corresponding interrupt handler is not installed. + + If unsure, say N. + # Common NUMA Features config NUMA bool "NUMA Memory Allocation and Scheduler Support" diff --git a/arch/x86/entry/entry_fred.c b/arch/x86/entry/entry_fred.c index fb3594ddf731..f52099e3fa85 100644 --- a/arch/x86/entry/entry_fred.c +++ b/arch/x86/entry/entry_fred.c @@ -120,6 +120,7 @@ static idtentry_t sysvec_table[NR_SYSTEM_VECTORS] __ro_= after_init =3D { SYSVEC(POSTED_INTR_NESTED_VECTOR, kvm_posted_intr_nested_ipi), =20 SYSVEC(POSTED_MSI_NOTIFICATION_VECTOR, posted_msi_notification), + SYSVEC(IBS_MEMPROF_VECTOR, ibs_memprof), }; =20 static bool fred_setup_done __initdata; diff --git a/arch/x86/include/asm/hardirq.h b/arch/x86/include/asm/hardirq.h index dea60d66d976..2da4930ea399 100644 --- a/arch/x86/include/asm/hardirq.h +++ b/arch/x86/include/asm/hardirq.h @@ -49,6 +49,9 @@ enum irq_stat_counts { #endif #ifdef CONFIG_X86_POSTED_MSI IRQ_COUNT_POSTED_MSI_NOTIFICATION, +#endif +#ifdef CONFIG_AMD_IBS_MEMPROF + IRQ_COUNT_IBS_MEMPROF, #endif IRQ_COUNT_PIC_APIC_ERROR, #ifdef CONFIG_X86_IO_APIC diff --git a/arch/x86/include/asm/ibs-caps.h b/arch/x86/include/asm/ibs-cap= s.h index ddf6c512c8f9..1f6c4058a0e3 100644 --- a/arch/x86/include/asm/ibs-caps.h +++ b/arch/x86/include/asm/ibs-caps.h @@ -29,6 +29,7 @@ #define IBS_CAPS_FETCHLAT (1U<<14) #define IBS_CAPS_BIT63_FILTER (1U<<15) #define IBS_CAPS_STRMST_RMTSOCKET (1U<<16) +#define IBS_CAPS_MEM_PROFILER (1U<<18) #define IBS_CAPS_OPDTLBPGSIZE (1U<<19) =20 #define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \ @@ -42,6 +43,13 @@ #define IBSCTL_LVT_OFFSET_VALID (1ULL<<8) #define IBSCTL_LVT_OFFSET_MASK 0x0F =20 +/* + * IBS Memprofiler setup + */ +#define IBSCTL_MPROF_LVT_OFFSET_VALID (1ULL << 24) +#define IBSCTL_MPROF_LVT_OFFSET_SHIFT 16 +#define IBSCTL_MPROF_LVT_OFFSET_MASK (0xFULL << IBSCTL_MPROF_LVT_OFFSET_SH= IFT) + /* IBS fetch bits/masks */ #define IBS_FETCH_L3MISSONLY (1ULL << 59) #define IBS_FETCH_RAND_EN (1ULL << 57) diff --git a/arch/x86/include/asm/ibs-mprof.h b/arch/x86/include/asm/ibs-mp= rof.h new file mode 100644 index 000000000000..3de1880c4126 --- /dev/null +++ b/arch/x86/include/asm/ibs-mprof.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_IBS_MPROF_H +#define _ASM_X86_IBS_MPROF_H + +/* + * All bits are documented here for clarity even if the current + * driver doesn't use all of them. + */ + +/* MSR_AMD64_IBS_MPROF_DATA2 bits */ +#define IBS_MPROF_DATA2_DATASRC_MASK 0x7 +#define IBS_MPROF_DATA2_DATASRC_MASK_HIGH 0xC0 +#define IBS_MPROF_DATA2_DATASRC_MASK_HIGH_SHIFT 0x3 +#define IBS_MPROF_DATA2_DATASRC_LCL_CCX 0x1 +#define IBS_MPROF_DATA2_DATASRC_PEER_CCX_NEAR 0x2 +#define IBS_MPROF_DATA2_DATASRC_DRAM 0x3 +#define IBS_MPROF_DATA2_DATASRC_CCX_FAR 0x5 +#define IBS_MPROF_DATA2_DATASRC_DRAM_FAR 0x7 +#define IBS_MPROF_DATA2_DATASRC_EXT_MEM 0x8 +#define IBS_MPROF_DATA2_RMT_NODE BIT_ULL(4) +#define IBS_MPROF_DATA2_RMT_SOCKET BIT_ULL(9) + +/* MSR_AMD64_IBS_MPROF_DATA3 bits */ +#define IBS_MPROF_DATA3_LDOP BIT_ULL(0) +#define IBS_MPROF_DATA3_STOP BIT_ULL(1) +#define IBS_MPROF_DATA3_DCMISS BIT_ULL(7) +#define IBS_MPROF_DATA3_LADDR_VALID BIT_ULL(17) +#define IBS_MPROF_DATA3_PADDR_VALID BIT_ULL(18) +#define IBS_MPROF_DATA3_L2MISS BIT_ULL(20) +#define IBS_MPROF_DATA3_SW_PREFETCH BIT_ULL(21) + +/* MSR_AMD64_IBS_MPROF_CTL bits */ +#define IBS_MPROF_CTL_CNT_CTL BIT_ULL(19) +#define IBS_MPROF_CTL_VAL BIT_ULL(18) +#define IBS_MPROF_CTL_ENABLE BIT_ULL(17) +#define IBS_MPROF_CTL_L3MISSONLY BIT_ULL(16) +#define IBS_MPROF_CTL_MAXCNT_MASK 0x0000FFFFULL +#define IBS_MPROF_CTL_MAXCNT_EXT_MASK (0x7FULL << 20) /* separate upper 7 = bits */ + +/* MSR_AMD64_IBS_MPROF_CTL2 bits */ +#define IBS_MPROF_CTL2_DISABLE BIT_ULL(0) +#define IBS_MPROF_CTL2_EXCLUDE_USER BIT_ULL(1) +#define IBS_MPROF_CTL2_EXCLUDE_KERNEL BIT_ULL(2) + +#define IBS_MPROF_SAMPLE_PERIOD 10000 + +#endif /* _ASM_X86_IBS_MPROF_H */ diff --git a/arch/x86/include/asm/idtentry.h b/arch/x86/include/asm/idtentr= y.h index f400cfac69a6..c98833f64a4f 100644 --- a/arch/x86/include/asm/idtentry.h +++ b/arch/x86/include/asm/idtentry.h @@ -735,6 +735,12 @@ DECLARE_IDTENTRY_SYSVEC(POSTED_MSI_NOTIFICATION_VECTOR= , sysvec_posted_msi_notifi # define fred_sysvec_posted_msi_notification NULL # endif =20 +# ifdef CONFIG_AMD_IBS_MEMPROF +DECLARE_IDTENTRY_SYSVEC(IBS_MEMPROF_VECTOR, sysvec_ibs_memprof); +#else +# define fred_sysvec_ibs_memprof NULL +#endif + #if IS_ENABLED(CONFIG_HYPERV) DECLARE_IDTENTRY_SYSVEC(HYPERVISOR_CALLBACK_VECTOR, sysvec_hyperv_callback= ); DECLARE_IDTENTRY_SYSVEC(HYPERV_REENLIGHTENMENT_VECTOR, sysvec_hyperv_reenl= ightenment); diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_= vectors.h index 85253fc8e384..575f880cb147 100644 --- a/arch/x86/include/asm/irq_vectors.h +++ b/arch/x86/include/asm/irq_vectors.h @@ -105,10 +105,12 @@ */ #define POSTED_MSI_NOTIFICATION_VECTOR 0xeb =20 +#define IBS_MEMPROF_VECTOR 0xea + #define NR_VECTORS 256 =20 #ifdef CONFIG_X86_LOCAL_APIC -#define FIRST_SYSTEM_VECTOR POSTED_MSI_NOTIFICATION_VECTOR +#define FIRST_SYSTEM_VECTOR IBS_MEMPROF_VECTOR #else #define FIRST_SYSTEM_VECTOR NR_VECTORS #endif diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 3a8e51a0c9e8..6e13f53143b0 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1319,4 +1319,12 @@ * a #GP */ =20 +/* AMD IBS Memory Profiler MSRs */ +#define MSR_AMD64_IBS_MPROF_CTL 0xc0010380 +#define MSR_AMD64_IBS_MPROF_CTL2 0xc0010381 +#define MSR_AMD64_IBS_MPROF_DATA2 0xc0010382 +#define MSR_AMD64_IBS_MPROF_DATA3 0xc0010383 +#define MSR_AMD64_IBS_MPROF_LINADDR 0xc0010384 +#define MSR_AMD64_IBS_MPROF_PHYADDR 0xc0010385 + #endif /* _ASM_X86_MSR_INDEX_H */ diff --git a/arch/x86/kernel/idt.c b/arch/x86/kernel/idt.c index 90a22e24a9eb..50ec5fc82619 100644 --- a/arch/x86/kernel/idt.c +++ b/arch/x86/kernel/idt.c @@ -169,6 +169,9 @@ static const __initconst struct idt_data apic_idts[] = =3D { # ifdef CONFIG_X86_POSTED_MSI INTG(POSTED_MSI_NOTIFICATION_VECTOR, asm_sysvec_posted_msi_notification), # endif +#ifdef CONFIG_AMD_IBS_MEMPROF + INTG(IBS_MEMPROF_VECTOR, asm_sysvec_ibs_memprof), +#endif #endif }; =20 diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c index 30122f0b3af9..c59a474d9202 100644 --- a/arch/x86/kernel/irq.c +++ b/arch/x86/kernel/irq.c @@ -121,6 +121,9 @@ static const struct irq_stat_info irq_stat_info[IRQ_COU= NT_MAX] =3D { #endif #ifdef CONFIG_X86_POSTED_MSI ISS(POSTED_MSI_NOTIFICATION, "PMN", " Posted MSI notification event\n"), +#endif +#ifdef CONFIG_AMD_IBS_MEMPROF + ISS(IBS_MEMPROF, "IMP", " IBS Memory Profiler interrupts\n"), #endif IDS(PIC_APIC_ERROR, "ERR", " PIC/APIC error interrupts\n"), #ifdef CONFIG_X86_IO_APIC diff --git a/arch/x86/mm/Makefile b/arch/x86/mm/Makefile index 3a5364853eab..050a7379d9f7 100644 --- a/arch/x86/mm/Makefile +++ b/arch/x86/mm/Makefile @@ -59,3 +59,4 @@ obj-$(CONFIG_X86_MEM_ENCRYPT) +=3D mem_encrypt.o obj-$(CONFIG_AMD_MEM_ENCRYPT) +=3D mem_encrypt_amd.o =20 obj-$(CONFIG_AMD_MEM_ENCRYPT) +=3D mem_encrypt_boot.o +obj-$(CONFIG_AMD_IBS_MEMPROF) +=3D ibs-mprof.o diff --git a/arch/x86/mm/ibs-mprof.c b/arch/x86/mm/ibs-mprof.c new file mode 100644 index 000000000000..a455fdc60d8e --- /dev/null +++ b/arch/x86/mm/ibs-mprof.c @@ -0,0 +1,482 @@ +// SPDX-License-Identifier: GPL-2.0 + +#define pr_fmt(fmt) "amd_ibs_memprof: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#define IBS_NR_SAMPLES 150 /* Percpu sample buffer size */ + +static DEFINE_PER_CPU(bool, mprof_work_pending); + +/* + * Basic access info captured for each memory access. + */ +struct mprof_sample { + unsigned long pfn; + unsigned long time; /* jiffies when accessed */ + int nid; /* Accessing node ID, if known */ +}; + +/* + * Percpu buffer of access samples. Samples are accumulated here + * before pushing them to pghot sub-system for further action. + */ +struct mprof_sample_pcpu { + struct mprof_sample samples[IBS_NR_SAMPLES]; + int head, tail; +}; + +static struct mprof_sample_pcpu __percpu *mprof_s; + +/* + * Per-CPU work for pushing the percpu access samples to pghot sub-system. + * + * @cpu records which CPU's sample ring this work item is responsible for + * draining. + */ +struct mprof_worker { + struct work_struct work; + unsigned int cpu; +}; +static DEFINE_PER_CPU(struct mprof_worker, mprof_work); +static int mprof_cpuhp_state =3D CPUHP_INVALID; + +/* + * Record the IBS-reported access sample in percpu buffer. + * Called from IBS interrupt handler. + */ +static bool mprof_push_sample(unsigned long pfn, int nid, unsigned long ti= me) +{ + struct mprof_sample_pcpu *pcpu =3D raw_cpu_ptr(mprof_s); + int head =3D READ_ONCE(pcpu->head); + int tail =3D READ_ONCE(pcpu->tail); + int next =3D head + 1; + + if (next >=3D IBS_NR_SAMPLES) + next =3D 0; + + if (next =3D=3D tail) { + count_vm_event(HWHINT_DROPPED_EVENTS); + return false; + } + + pcpu->samples[head].pfn =3D pfn; + pcpu->samples[head].time =3D time; + pcpu->samples[head].nid =3D nid; + + /* + * Publish the sample slot stores before advancing head; pairs + * with the smp_load_acquire() of head in mprof_pop_sample(). + */ + smp_store_release(&pcpu->head, next); + return true; +} + +static bool mprof_pop_sample(struct mprof_sample_pcpu *pcpu, struct mprof_= sample *s) +{ + int tail =3D READ_ONCE(pcpu->tail); + /* + * Pairs with the smp_store_release() of head in mprof_push_sample(); + * ensures the sample slot stores are visible before we read the slot. + */ + int head =3D smp_load_acquire(&pcpu->head); + int next =3D tail + 1; + + if (head =3D=3D tail) + return false; + + if (next >=3D IBS_NR_SAMPLES) + next =3D 0; + + *s =3D pcpu->samples[tail]; + + /* + * Publish the freed slot via tail with release semantics so the plain + * sample read above cannot be reordered past it. The ring's one-empty- + * slot invariant already keeps the producer from ever writing the slot + * being read, so this is not strictly required on x86; it makes the + * ordering explicit and symmetric with the head release/acquire, at no + * runtime cost (compiler barrier only). + */ + smp_store_release(&pcpu->tail, next); + return true; +} + +/* + * Drain any samples remaining in @cpu's ring into pghot. Called from the + * cpuhp offline callback after flush_work(), with the producer silenced. + */ +static void mprof_drain_ring(unsigned int cpu) +{ + struct mprof_sample_pcpu *pcpu =3D per_cpu_ptr(mprof_s, cpu); + struct mprof_sample s; + + while (mprof_pop_sample(pcpu, &s)) + pghot_record_access(s.pfn, s.nid, PGHOT_HWHINTS, s.time); +} + +/* + * Remove access samples from percpu buffer and send them + * to pghot sub-system for further action. + */ +static void mprof_work_handler(struct work_struct *work) +{ + struct mprof_worker *mw =3D container_of(work, struct mprof_worker, work); + unsigned int cpu =3D mw->cpu; + struct mprof_sample_pcpu *pcpu =3D per_cpu_ptr(mprof_s, cpu); + struct mprof_sample s; + + for (;;) { + while (mprof_pop_sample(pcpu, &s)) + pghot_record_access(s.pfn, s.nid, PGHOT_HWHINTS, + s.time); + + /* + * Publish the cleared pending flag before re-checking the + * ring so a racing IRQ cannot leave a just-pushed sample + * unprocessed. + */ + WRITE_ONCE(per_cpu(mprof_work_pending, cpu), false); + + if (READ_ONCE(pcpu->head) =3D=3D READ_ONCE(pcpu->tail)) + return; + + /* + * A sample was pushed after we exited the drain loop; the + * producer may have skipped re-queuing because pending was + * still set. Keep draining until the ring is observably empty + * with pending cleared. + */ + } +} + +/* + * L3MissOnly + Exclude kernel RIP + */ +static void mprof_enable_profiling(void) +{ + u64 mprof_config =3D IBS_MPROF_CTL_CNT_CTL | IBS_MPROF_CTL_L3MISSONLY; + unsigned int period =3D IBS_MPROF_SAMPLE_PERIOD; + u64 ctl, ctl2; + + /* + * Assemble bits 26:20 and 19:4 of periodic op counter in ctl. + * The lower 4 bits are always 0000b. + */ + ctl =3D (period >> 4) & IBS_MPROF_CTL_MAXCNT_MASK; + ctl |=3D (period & IBS_MPROF_CTL_MAXCNT_EXT_MASK); + ctl |=3D mprof_config; + wrmsrq(MSR_AMD64_IBS_MPROF_CTL, ctl); + + /* + * Exclude samples that have bit 63 of their RIP set. + */ + ctl2 =3D IBS_MPROF_CTL2_EXCLUDE_KERNEL; + wrmsrq(MSR_AMD64_IBS_MPROF_CTL2, ctl2); +} + +static void mprof_disable_profiling(u64 mem_ctl) +{ + mem_ctl &=3D ~IBS_MPROF_CTL_ENABLE; + mem_ctl &=3D ~IBS_MPROF_CTL_VAL; + wrmsrq(MSR_AMD64_IBS_MPROF_CTL, mem_ctl); + + wrmsrq(MSR_AMD64_IBS_MPROF_CTL2, IBS_MPROF_CTL2_DISABLE); +} + +/* + * IBS interrupt handler: Process the memory access info reported by IBS. + * + * Reads the MSRs to collect all the information about the reported + * memory access, validates the access, stores the valid sample and + * schedules the work on this CPU to further process the sample. + */ +static void mprof_overflow_handler(void) +{ + u64 mem_ctl, mem_data3, mem_data2, paddr, data_src; + struct work_struct *w =3D &this_cpu_ptr(&mprof_work)->work; + unsigned long pfn; + struct page *page; + + rdmsrq(MSR_AMD64_IBS_MPROF_CTL, mem_ctl); + if (!(mem_ctl & IBS_MPROF_CTL_VAL)) + return; + + mprof_disable_profiling(mem_ctl); + count_vm_event(HWHINT_TOTAL_EVENTS); + + rdmsrq(MSR_AMD64_IBS_MPROF_DATA3, mem_data3); + + /* Data source is valid only if the sample isn't an L1 or L2 hit */ + if (!(mem_data3 & (IBS_MPROF_DATA3_DCMISS | IBS_MPROF_DATA3_L2MISS))) { + count_vm_event(HWHINT_CACHE_ACCESSES); + } else { + rdmsrq(MSR_AMD64_IBS_MPROF_DATA2, mem_data2); + data_src =3D mem_data2 & IBS_MPROF_DATA2_DATASRC_MASK; + data_src |=3D ((mem_data2 & IBS_MPROF_DATA2_DATASRC_MASK_HIGH) >> + IBS_MPROF_DATA2_DATASRC_MASK_HIGH_SHIFT); + + switch (data_src) { + case IBS_MPROF_DATA2_DATASRC_DRAM: + case IBS_MPROF_DATA2_DATASRC_DRAM_FAR: + /* local and remote DRAM are both DRAM accesses */ + count_vm_event(HWHINT_DRAM_ACCESSES); + break; + case IBS_MPROF_DATA2_DATASRC_EXT_MEM: + count_vm_event(HWHINT_EXTMEM_ACCESSES); + break; + } + } + + /* Is linear addr valid? */ + if (!(mem_data3 & IBS_MPROF_DATA3_LADDR_VALID)) + goto handled; + + /* Is phys addr valid? */ + if (!(mem_data3 & IBS_MPROF_DATA3_PADDR_VALID)) + goto handled; + rdmsrq(MSR_AMD64_IBS_MPROF_PHYADDR, paddr); + + pfn =3D PHYS_PFN(paddr); + page =3D pfn_to_online_page(pfn); + if (!page) + goto handled; + + /* + * Use the accessing CPU's node as the migration target. On + * topologies where all CPUs reside on toptier nodes (the common + * case), this is the desired behaviour. + */ + if (!mprof_push_sample(pfn, numa_node_id(), jiffies)) + goto handled; + + if (!this_cpu_read(mprof_work_pending)) { + this_cpu_write(mprof_work_pending, true); + schedule_work_on(smp_processor_id(), w); + } + count_vm_event(HWHINT_USEFUL_EVENTS); + +handled: + mprof_enable_profiling(); +} + +DEFINE_IDTENTRY_SYSVEC(sysvec_ibs_memprof) +{ + inc_irq_stat(IBS_MEMPROF); + mprof_overflow_handler(); + apic_eoi(); +} + +static int get_mprof_lvt_offset(void) +{ + u64 val; + + rdmsrq(MSR_AMD64_IBSCTL, val); + if (!(val & IBSCTL_MPROF_LVT_OFFSET_VALID)) + return -EINVAL; + + return (val & IBSCTL_MPROF_LVT_OFFSET_MASK) >> + IBSCTL_MPROF_LVT_OFFSET_SHIFT; +} + +/* + * Confirm the IBS memory-profiler extended-LVT offset is valid and routab= le, + * mirroring the perf IBS driver's ibs_eilvt_valid(). The trial uses mask= =3D1 so + * it programs nothing that can fire; the per-CPU startup callback unmasks= it + * later. setup_APIC_eilvt() touches the local APIC, so this must run with + * preemption disabled. + */ +static bool mprof_eilvt_valid(void) +{ + int offset; + bool valid =3D false; + + preempt_disable(); + + offset =3D get_mprof_lvt_offset(); + if (offset < 0) + goto out; + + if (!setup_APIC_eilvt(offset, IBS_MEMPROF_VECTOR, APIC_DELIVERY_MODE_FIXE= D, 1)) + valid =3D true; +out: + preempt_enable(); + return valid; +} + +/* + * Arm the memory profiler on the current CPU: route the extended-LVT entry + * to IBS_MEMPROF_VECTOR and program IBS from the published config snapsho= t. + * Runs on the target CPU (cpuhp ONLINE callback and syscore resume). + */ +static int mprof_arm_cpu(void) +{ + int offset =3D get_mprof_lvt_offset(); + + if (offset < 0) { + pr_warn("offset not valid on cpu #%d\n", smp_processor_id()); + return -ENODEV; + } + + if (setup_APIC_eilvt(offset, IBS_MEMPROF_VECTOR, APIC_DELIVERY_MODE_FIXED= , 0)) { + pr_warn("APIC setup failed on cpu #%d\n", smp_processor_id()); + return -EBUSY; + } + + mprof_enable_profiling(); + return 0; +} + +/* + * Disarm the memory profiler on the current CPU: mask the extended-LVT en= try + * (silences the producer) and clear the IBS enable/valid bits. + */ +static void mprof_disarm_cpu(void) +{ + int offset =3D get_mprof_lvt_offset(); + u64 mem_ctl; + + if (offset >=3D 0) + setup_APIC_eilvt(offset, IBS_MEMPROF_VECTOR, APIC_DELIVERY_MODE_FIXED, 1= ); + + rdmsrq(MSR_AMD64_IBS_MPROF_CTL, mem_ctl); + mprof_disable_profiling(mem_ctl); +} + +static int x86_amd_ibs_mprof_online(unsigned int cpu) +{ + /* + * If profiler can't be armed, that must not stop + * CPU online. Hence ignoring the return value of + * mprof_arm_cpu(). + */ + mprof_arm_cpu(); + return 0; +} + +static int x86_amd_ibs_mprof_offline(unsigned int cpu) +{ + struct mprof_worker *mw =3D per_cpu_ptr(&mprof_work, cpu); + + WARN_ON(cpu !=3D smp_processor_id()); + + /* + * The teardown callback runs on this CPU before + * CPUHP_AP_WORKQUEUE_ONLINE offline, while this CPU's worker is still + * per-CPU bound. Silence the producer, flush the pending worker, then + * drain any remaining ring samples synchronously. + */ + local_irq_disable(); + mprof_disarm_cpu(); + local_irq_enable(); + flush_work(&mw->work); + mprof_drain_ring(cpu); + WRITE_ONCE(per_cpu(mprof_work_pending, cpu), false); + + return 0; +} + +#ifdef CONFIG_PM +/* + * The local APIC does not preserve the extended-LVT registers across S3/S4 + * (lapic_suspend()/lapic_resume() save only the architectural LVTs), and = the + * boot CPU never re-runs the cpuhp ONLINE callback on resume. Re-arm it v= ia + * syscore so the profiler survives suspend/resume; secondary CPUs are han= dled + * by their offline/online cpuhp callbacks. + */ +static int mprof_suspend(void *data) +{ + mprof_disarm_cpu(); + return 0; +} + +static void mprof_resume(void *data) +{ + mprof_arm_cpu(); +} + +static const struct syscore_ops mprof_syscore_ops =3D { + .resume =3D mprof_resume, + .suspend =3D mprof_suspend, +}; + +static struct syscore mprof_syscore =3D { + .ops =3D &mprof_syscore_ops, +}; + +static void mprof_pm_init(void) +{ + register_syscore(&mprof_syscore); +} +#else +static void mprof_pm_init(void) {} +#endif + +static int __init mprof_access_profiling_init(void) +{ + u32 mprof_caps; + int cpu, ret; + + if (!boot_cpu_has(X86_FEATURE_IBS)) + return -ENODEV; + + mprof_caps =3D cpuid_eax(IBS_CPUID_FEATURES); + if (!(mprof_caps & IBS_CAPS_MEM_PROFILER)) { + pr_info("capability is unavailable for access profiling\n"); + return -ENODEV; + } + + /* + * Don't initialize the profiler if EILVT offset can't be armed. + */ + if (!mprof_eilvt_valid()) { + pr_info("extended-LVT offset unavailable; access profiling disabled\n"); + return -EINVAL; + } + + mprof_s =3D alloc_percpu_gfp(struct mprof_sample_pcpu, GFP_KERNEL | __GFP= _ZERO); + if (!mprof_s) + return -ENOMEM; + + for_each_possible_cpu(cpu) { + struct mprof_worker *mw =3D per_cpu_ptr(&mprof_work, cpu); + + INIT_WORK(&mw->work, mprof_work_handler); + mw->cpu =3D cpu; + } + + ret =3D cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, + "x86/amd/ibs_mprof:online", + x86_amd_ibs_mprof_online, + x86_amd_ibs_mprof_offline); + if (ret < 0) + goto out_free; + mprof_cpuhp_state =3D ret; + + mprof_pm_init(); + + pr_info("IBS Memory Profiler is available for memory access profiling\n"); + return 0; + +out_free: + free_percpu(mprof_s); + pr_info("IBS Memory Profiler failed to initialize\n"); + return ret; +} + +device_initcall(mprof_access_profiling_init); diff --git a/include/linux/vm_event_item.h b/include/linux/vm_event_item.h index 90827e8b597f..ebd001fcf741 100644 --- a/include/linux/vm_event_item.h +++ b/include/linux/vm_event_item.h @@ -183,6 +183,14 @@ enum vm_event_item { PGPGIN, PGPGOUT, PSWPIN, PSWPOUT, PGHOT_RECORDED_ACCESSES, PGHOT_REPORTED_HINTFAULTS, PGHOT_REPORTED_HWHINTS, +#ifdef CONFIG_HWMEM_PROFILER + HWHINT_TOTAL_EVENTS, + HWHINT_DRAM_ACCESSES, + HWHINT_EXTMEM_ACCESSES, + HWHINT_CACHE_ACCESSES, + HWHINT_USEFUL_EVENTS, + HWHINT_DROPPED_EVENTS, +#endif /* CONFIG_HWMEM_PROFILER */ #endif /* CONFIG_PGHOT */ NR_VM_EVENT_ITEMS }; diff --git a/mm/Kconfig b/mm/Kconfig index 9237d54a6d8b..6ec71eb6f498 100644 --- a/mm/Kconfig +++ b/mm/Kconfig @@ -1536,6 +1536,15 @@ config PGHOT_PRECISE 4 bytes per page against the default one byte per page. Preferable to enable this on systems with multiple nodes in toptier. =20 +config HWMEM_PROFILER + bool + depends on PGHOT + help + Umbrella symbol enabled by any in-kernel driver that forwards + hardware-observed memory accesses to the pghot subsystem (for + example AMD_IBS_MEMPROF on x86_64). Drivers select this; users + do not enable it directly. + source "mm/damon/Kconfig" =20 endmenu diff --git a/mm/vmstat.c b/mm/vmstat.c index cbcbbbbbf297..570615d5f441 100644 --- a/mm/vmstat.c +++ b/mm/vmstat.c @@ -1511,6 +1511,14 @@ const char * const vmstat_text[] =3D { [I(PGHOT_RECORDED_ACCESSES)] =3D "pghot_recorded_accesses", [I(PGHOT_REPORTED_HINTFAULTS)] =3D "pghot_reported_hintfaults", [I(PGHOT_REPORTED_HWHINTS)] =3D "pghot_reported_hwhints", +#ifdef CONFIG_HWMEM_PROFILER + [I(HWHINT_TOTAL_EVENTS)] =3D "hwhint_total_events", + [I(HWHINT_DRAM_ACCESSES)] =3D "hwhint_dram_accesses", + [I(HWHINT_EXTMEM_ACCESSES)] =3D "hwhint_extmem_accesses", + [I(HWHINT_CACHE_ACCESSES)] =3D "hwhint_cache_accesses", + [I(HWHINT_USEFUL_EVENTS)] =3D "hwhint_useful_events", + [I(HWHINT_DROPPED_EVENTS)] =3D "hwhint_dropped_events", +#endif /* CONFIG_HWMEM_PROFILER */ #endif /* CONFIG_PGHOT */ #undef I #endif /* CONFIG_VM_EVENT_COUNTERS */ --=20 2.34.1 From nobody Thu Sep 24 12:53:01 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012023.outbound.protection.outlook.com [52.101.43.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD1BA42047A for ; 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charset="utf-8" Expose runtime tunables for IBS Memory profiler and arm the profiler. /ibs-mprof/l3miss-only - IbsMemL3MissOnly filter /ibs-mprof/period - op sample period (IbsMemMaxCnt) /ibs-mprof/lat-filter - IbsMemLatFltEn load-latency filter /ibs-mprof/lat-thresh - IbsMemLatThrsh (0x0..0xf) In addition, a kernel cmdline parameter (ibs-memprof) is introduced to enable profiling at boot time. /sys/devices/system/cpu/ibs-mprof/enabled can be used to turn the profiling on or off. Enabling the profiler will result in IBS Memory Profiler samples to be reported to pghot subsystem. pghot will act on these samples only if hwhints source is enabled explicilty using pghot/enabled_sources debugfs tunable. Signed-off-by: Bharata B Rao --- .../admin-guide/kernel-parameters.txt | 5 + Documentation/admin-guide/mm/pghot.rst | 47 ++ arch/x86/include/asm/ibs-mprof.h | 14 + arch/x86/mm/ibs-mprof.c | 415 +++++++++++++++++- 4 files changed, 466 insertions(+), 15 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 68647ff4bdd2..3ef091d86c33 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -2235,6 +2235,11 @@ Kernel parameters syscalls, essentially overriding IA32_EMULATION_DEFAULT_DISABLED at boot time. When false, unconditionally disables IA32 emulation. =20 + ibs-memprof=3D [X86-64] + Format: + When true, IBS Memory Profiler will be enabled at boottime + for memory access profiling. It can be changed at runtime too + using /sys/devices/system/cpu/ibs-mprof/enabled. =20 idle=3D [X86,EARLY] Format: idle=3Dpoll, idle=3Dhalt, idle=3Dnomwait diff --git a/Documentation/admin-guide/mm/pghot.rst b/Documentation/admin-g= uide/mm/pghot.rst index df8316175207..97142c2558cd 100644 --- a/Documentation/admin-guide/mm/pghot.rst +++ b/Documentation/admin-guide/mm/pghot.rst @@ -159,3 +159,50 @@ Path: /proc/vmstat =20 5. **hwhint_extmem_accesses** - Number of external memory (like CXL) accesses reported by hwhints sou= rce. + +AMD IBS Memory Profiler Tunables +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D +sysfs tunables +-------------- +1. enabled + +Path: /sys/devices/system/cpu/ibs-mprof/enabled + +- Enable (1) or disable (0) memory access profiling. Enabling here + would only arm the memory profiler and results in generation of IBS + samples. pghot will act on the reported samples only if hwhints source + is enabled in **pghot_enabled_sources**. +- Default: 0 (Disabled) + +Debugfs tunables +---------------- +Path: /sys/kernel/debug/ibs-mprof/ + +These tune the AMD IBS Memory Profiler hardware hints source and are +present only when AMD_IBS_MEMPROF is enabled. A write takes effect on +all CPUs immediately. + +1. **l3miss-only** + - When 1, only accesses that miss the L3 cache are sampled. It is + recommended to run the memory profiler with L3 miss filtering + enabled. + - Default: 1 + +2. **period** + - Sample period as the number of ops between samples (IbsMemMaxCnt). + - Range: 5008 to 134217712. The written value is rounded down to a + multiple of 16 (the low 4 bits of the hardware IbsMemMaxCnt field are + always zero), so a read-back may be up to 15 less than what was writt= en. + - Default: 10000 + +3. **lat-filter** + - When 1, enable load latency filtering: only loads whose latency + exceeds the **lat-thresh** threshold are reported. + - Default: 0 + +4. **lat-thresh** + - Load latency threshold, effective only when **lat-filter** is 1. A + sample is reported when the load latency exceeds + (lat-thresh + 1) * 128 core cycles. + - Range: 0x0 to 0xf + - Default: 0 diff --git a/arch/x86/include/asm/ibs-mprof.h b/arch/x86/include/asm/ibs-mp= rof.h index 3de1880c4126..5262a77645ef 100644 --- a/arch/x86/include/asm/ibs-mprof.h +++ b/arch/x86/include/asm/ibs-mprof.h @@ -30,6 +30,9 @@ #define IBS_MPROF_DATA3_SW_PREFETCH BIT_ULL(21) =20 /* MSR_AMD64_IBS_MPROF_CTL bits */ +#define IBS_MPROF_CTL_LATFLTEN BIT_ULL(63) /* IbsMemLatFltEn */ +#define IBS_MPROF_CTL_LATTHRSH_SHIFT 59 +#define IBS_MPROF_CTL_LATTHRSH_MASK (0xFULL << IBS_MPROF_CTL_LATTHRSH_SHIF= T) #define IBS_MPROF_CTL_CNT_CTL BIT_ULL(19) #define IBS_MPROF_CTL_VAL BIT_ULL(18) #define IBS_MPROF_CTL_ENABLE BIT_ULL(17) @@ -37,6 +40,17 @@ #define IBS_MPROF_CTL_MAXCNT_MASK 0x0000FFFFULL #define IBS_MPROF_CTL_MAXCNT_EXT_MASK (0x7FULL << 20) /* separate upper 7 = bits */ =20 +/* + * IbsMemMaxCnt is a 27-bit op count; the low 4 bits are always zero. + * The hardware minimum is 16, but such a short interval is impractical + * (interrupt storm), so restrict the sample period to a sensible floor. + */ +#define IBS_MPROF_MAXCNT_MIN 5008 +#define IBS_MPROF_MAXCNT_MAX ((1U << 27) - 1) + +/* IbsMemLatThrsh is a 4-bit field. */ +#define IBS_MPROF_LATTHRSH_MAX 0xF + /* MSR_AMD64_IBS_MPROF_CTL2 bits */ #define IBS_MPROF_CTL2_DISABLE BIT_ULL(0) #define IBS_MPROF_CTL2_EXCLUDE_USER BIT_ULL(1) diff --git a/arch/x86/mm/ibs-mprof.c b/arch/x86/mm/ibs-mprof.c index a455fdc60d8e..6f63f18cf474 100644 --- a/arch/x86/mm/ibs-mprof.c +++ b/arch/x86/mm/ibs-mprof.c @@ -10,7 +10,14 @@ #include #include #include +#include #include +#include +#include +#include +#include +#include +#include =20 #include #include @@ -56,6 +63,41 @@ struct mprof_worker { static DEFINE_PER_CPU(struct mprof_worker, mprof_work); static int mprof_cpuhp_state =3D CPUHP_INVALID; =20 +/* + * Runtime-configurable profiler parameters, exposed via debugfs. The + * interrupt handler consumes the published snapshot on every re-arm, so + * configuration changes need no locking on the fast path. Writers are + * serialized by mprof_cfg_lock and publish an immutable snapshot; the hot + * path only does an smp_load_acquire() of the pointer. + */ +struct mprof_config { + bool enabled; /* profiling enabled (IbsMemDis inverted) */ + bool l3miss_only; /* IbsMemL3MissOnly */ + bool lat_filter; /* IbsMemLatFltEn */ + u8 lat_thresh; /* IbsMemLatThrsh, 0x0 .. 0xf */ + u32 period; /* op sample period (IbsMemMaxCnt) */ + /* Precomputed register values for the interrupt fast path. */ + u64 ctl; + u64 ctl2; +}; + +static struct mprof_config mprof_cfg_slots[2]; +static struct mprof_config *mprof_cfg; +static DEFINE_MUTEX(mprof_cfg_lock); + +/* + * ibs-memprof: kernel cmdline parameter to arm IBS Memory + * Profiler right from boot time. + */ +static bool ibs_mprof_enabled __read_mostly; + +static int __init setup_ibs_mprof(char *str) +{ + return (kstrtobool(str, &ibs_mprof_enabled) =3D=3D 0); +} + +__setup("ibs-memprof=3D", setup_ibs_mprof); + /* * Record the IBS-reported access sample in percpu buffer. * Called from IBS interrupt handler. @@ -166,28 +208,60 @@ static void mprof_work_handler(struct work_struct *wo= rk) } =20 /* - * L3MissOnly + Exclude kernel RIP + * Translate the software config into IbsMemCtl / IbsMemCtl2 register valu= es. + * Kernel RIP is always excluded: the profiler only samples user memory + * accesses. */ -static void mprof_enable_profiling(void) +static void mprof_compose(struct mprof_config *cfg) { - u64 mprof_config =3D IBS_MPROF_CTL_CNT_CTL | IBS_MPROF_CTL_L3MISSONLY; - unsigned int period =3D IBS_MPROF_SAMPLE_PERIOD; - u64 ctl, ctl2; + u64 ctl; + + if (!cfg->enabled) { + /* + * Stop the sample generation only; leave the extended LVT + * routed so re-enable does not reprogram the APIC. LVT + * mask/unmask is done by mprof_arm_cpu / mprof_disarm_cpu. + */ + ctl =3D 0; + cfg->ctl =3D ctl; + cfg->ctl2 =3D IBS_MPROF_CTL2_DISABLE; + return; + } =20 /* - * Assemble bits 26:20 and 19:4 of periodic op counter in ctl. + * Assemble bits 26:20 and 19:4 of the periodic op counter in ctl. * The lower 4 bits are always 0000b. */ - ctl =3D (period >> 4) & IBS_MPROF_CTL_MAXCNT_MASK; - ctl |=3D (period & IBS_MPROF_CTL_MAXCNT_EXT_MASK); - ctl |=3D mprof_config; - wrmsrq(MSR_AMD64_IBS_MPROF_CTL, ctl); + ctl =3D (cfg->period >> 4) & IBS_MPROF_CTL_MAXCNT_MASK; + ctl |=3D cfg->period & IBS_MPROF_CTL_MAXCNT_EXT_MASK; + ctl |=3D IBS_MPROF_CTL_CNT_CTL | IBS_MPROF_CTL_ENABLE; =20 - /* - * Exclude samples that have bit 63 of their RIP set. - */ - ctl2 =3D IBS_MPROF_CTL2_EXCLUDE_KERNEL; - wrmsrq(MSR_AMD64_IBS_MPROF_CTL2, ctl2); + if (cfg->l3miss_only) + ctl |=3D IBS_MPROF_CTL_L3MISSONLY; + + if (cfg->lat_filter) { + ctl |=3D IBS_MPROF_CTL_LATFLTEN; + ctl |=3D ((u64)cfg->lat_thresh << IBS_MPROF_CTL_LATTHRSH_SHIFT) & + IBS_MPROF_CTL_LATTHRSH_MASK; + } + + cfg->ctl =3D ctl; + /* Exclude samples that have bit 63 of their RIP set (kernel). */ + cfg->ctl2 =3D IBS_MPROF_CTL2_EXCLUDE_KERNEL; +} + +/* + * Program the profiler from the currently published config snapshot. Call= ed + * at CPU startup, from the interrupt handler on every re-arm, and via + * on_each_cpu() when the config changes. + */ +static void mprof_enable_profiling(void) +{ + /* Acquire the snapshot; pairs with smp_store_release() in the writers. */ + struct mprof_config *cfg =3D smp_load_acquire(&mprof_cfg); + + wrmsrq(MSR_AMD64_IBS_MPROF_CTL, cfg->ctl); + wrmsrq(MSR_AMD64_IBS_MPROF_CTL2, cfg->ctl2); } =20 static void mprof_disable_profiling(u64 mem_ctl) @@ -199,6 +273,56 @@ static void mprof_disable_profiling(u64 mem_ctl) wrmsrq(MSR_AMD64_IBS_MPROF_CTL2, IBS_MPROF_CTL2_DISABLE); } =20 +static void mprof_reprogram_this_cpu(void *info) +{ + mprof_enable_profiling(); +} + +/* + * Publish a new config snapshot and program every online CPU. + * Callers must hold mprof_cfg_lock and cpus_read_lock. The latter + * keeps the online set stable so on_each_cpu() cannot race a CPU's + * ONLINE arm path, which might still be reading the previous slot + * as this publish overwrites it. + */ +static void mprof_publish(const struct mprof_config *newcfg) +{ + struct mprof_config *slot; + + lockdep_assert_cpus_held(); + lockdep_assert_held(&mprof_cfg_lock); + + /* Fill the slot that is not currently published, then flip to it. */ + slot =3D (mprof_cfg =3D=3D &mprof_cfg_slots[0]) ? + &mprof_cfg_slots[1] : &mprof_cfg_slots[0]; + *slot =3D *newcfg; + mprof_compose(slot); + /* Publish the fully composed slot; pairs with smp_load_acquire() in read= ers. */ + smp_store_release(&mprof_cfg, slot); + + /* + * on_each_cpu() with wait serializes against any in-flight interrupt + * handler on each CPU, so the previously published slot has no readers + * once this returns and can be safely reused by the next writer. + */ + on_each_cpu(mprof_reprogram_this_cpu, NULL, 1); +} + +static void mprof_config_init(void) +{ + struct mprof_config *cfg =3D &mprof_cfg_slots[0]; + + if (ibs_mprof_enabled) + cfg->enabled =3D true; + cfg->l3miss_only =3D true; + cfg->lat_filter =3D false; + cfg->lat_thresh =3D 0; + cfg->period =3D IBS_MPROF_SAMPLE_PERIOD; + mprof_compose(cfg); + /* Publish the initial snapshot; pairs with smp_load_acquire() in readers= . */ + smp_store_release(&mprof_cfg, cfg); +} + /* * IBS interrupt handler: Process the memory access info reported by IBS. * @@ -222,6 +346,13 @@ static void mprof_overflow_handler(void) =20 rdmsrq(MSR_AMD64_IBS_MPROF_DATA3, mem_data3); =20 + /* + * If L3 miss filtering is turned off, non load/store + * samples may get reported. Ignore them. + */ + if (!(mem_data3 & (IBS_MPROF_DATA3_LDOP | IBS_MPROF_DATA3_STOP))) + goto handled; + /* Data source is valid only if the sample isn't an L1 or L2 hit */ if (!(mem_data3 & (IBS_MPROF_DATA3_DCMISS | IBS_MPROF_DATA3_L2MISS))) { count_vm_event(HWHINT_CACHE_ACCESSES); @@ -423,10 +554,245 @@ static void mprof_pm_init(void) { register_syscore(&mprof_syscore); } + +static void mprof_pm_destroy(void) +{ + unregister_syscore(&mprof_syscore); +} #else static void mprof_pm_init(void) {} +static void mprof_pm_destroy(void) {} #endif =20 +/* + * debugfs interface. Each parameter is a separate file under + * /ibs-mprof/. A write validates the value, updates the current + * config and actively propagates it to all CPUs via mprof_publish(). + */ +enum mprof_field { + MPROF_L3MISS_ONLY, + MPROF_LAT_FILTER, + MPROF_LAT_THRESH, + MPROF_PERIOD, +}; + +static int mprof_parse_uint(const char __user *ubuf, size_t cnt, unsigned = int *val) +{ + char buf[16]; + + if (cnt >=3D sizeof(buf)) + return -EINVAL; + + if (copy_from_user(buf, ubuf, cnt)) + return -EFAULT; + buf[cnt] =3D '\0'; + if (kstrtouint(buf, 0, val)) + return -EINVAL; + return 0; +} + +static void mprof_store(enum mprof_field field, unsigned int val) +{ + struct mprof_config new; + + guard(cpus_read_lock)(); + guard(mutex)(&mprof_cfg_lock); + new =3D *mprof_cfg; + switch (field) { + case MPROF_L3MISS_ONLY: + new.l3miss_only =3D val; + break; + case MPROF_LAT_FILTER: + new.lat_filter =3D val; + break; + case MPROF_LAT_THRESH: + new.lat_thresh =3D val; + break; + case MPROF_PERIOD: + new.period =3D val; + break; + } + mprof_publish(&new); +} + +#define MPROF_SHOW(name, field) \ +static int mprof_##name##_show(struct seq_file *m, void *v) \ +{ \ + unsigned int val; \ + \ + mutex_lock(&mprof_cfg_lock); \ + val =3D mprof_cfg->field; \ + mutex_unlock(&mprof_cfg_lock); \ + seq_printf(m, "%u\n", val); \ + return 0; \ +} \ +static int mprof_##name##_open(struct inode *inode, struct file *filp) \ +{ \ + return single_open(filp, mprof_##name##_show, NULL); \ +} + +MPROF_SHOW(l3miss_only, l3miss_only) +MPROF_SHOW(lat_filter, lat_filter) +MPROF_SHOW(lat_thresh, lat_thresh) +MPROF_SHOW(period, period) + +static ssize_t mprof_l3miss_only_write(struct file *filp, const char __use= r *ubuf, + size_t cnt, loff_t *ppos) +{ + unsigned int val; + int ret; + + ret =3D mprof_parse_uint(ubuf, cnt, &val); + if (ret) + return ret; + if (val > 1) + return -EINVAL; + + mprof_store(MPROF_L3MISS_ONLY, val); + *ppos +=3D cnt; + return cnt; +} + +static ssize_t mprof_lat_filter_write(struct file *filp, const char __user= *ubuf, + size_t cnt, loff_t *ppos) +{ + unsigned int val; + int ret; + + ret =3D mprof_parse_uint(ubuf, cnt, &val); + if (ret) + return ret; + if (val > 1) + return -EINVAL; + + mprof_store(MPROF_LAT_FILTER, val); + *ppos +=3D cnt; + return cnt; +} + +static ssize_t mprof_lat_thresh_write(struct file *filp, const char __user= *ubuf, + size_t cnt, loff_t *ppos) +{ + unsigned int val; + int ret; + + ret =3D mprof_parse_uint(ubuf, cnt, &val); + if (ret) + return ret; + if (val > IBS_MPROF_LATTHRSH_MAX) + return -EINVAL; + + mprof_store(MPROF_LAT_THRESH, val); + *ppos +=3D cnt; + return cnt; +} + +static ssize_t mprof_period_write(struct file *filp, const char __user *ub= uf, + size_t cnt, loff_t *ppos) +{ + unsigned int val; + int ret; + + ret =3D mprof_parse_uint(ubuf, cnt, &val); + if (ret) + return ret; + + /* The lower 4 bits of IBSMemMaxCnt are always zero */ + val &=3D ~0xf; + if (val < IBS_MPROF_MAXCNT_MIN || val > IBS_MPROF_MAXCNT_MAX) + return -EINVAL; + + mprof_store(MPROF_PERIOD, val); + *ppos +=3D cnt; + return cnt; +} + +#define MPROF_FOPS(name) \ +static const struct file_operations mprof_##name##_fops =3D { \ + .open =3D mprof_##name##_open, \ + .read =3D seq_read, \ + .write =3D mprof_##name##_write, \ + .llseek =3D seq_lseek, \ + .release =3D single_release, \ +} + +MPROF_FOPS(l3miss_only); +MPROF_FOPS(lat_filter); +MPROF_FOPS(lat_thresh); +MPROF_FOPS(period); + +static void mprof_debugfs_init(void) +{ + struct dentry *dir =3D debugfs_create_dir("ibs-mprof", NULL); + + debugfs_create_file("l3miss-only", 0644, dir, NULL, &mprof_l3miss_only_fo= ps); + debugfs_create_file("lat-filter", 0644, dir, NULL, &mprof_lat_filter_fops= ); + debugfs_create_file("lat-thresh", 0644, dir, NULL, &mprof_lat_thresh_fops= ); + debugfs_create_file("period", 0644, dir, NULL, &mprof_period_fops); +} + +static ssize_t enabled_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + bool enabled; + + mutex_lock(&mprof_cfg_lock); + enabled =3D mprof_cfg->enabled; + mutex_unlock(&mprof_cfg_lock); + + return sysfs_emit(buf, "%s\n", str_enabled_disabled(enabled)); +} + +static ssize_t enabled_store(struct device *dev, struct device_attribute *= attr, + const char *buf, size_t count) +{ + struct mprof_config new; + bool enabled; + int ret; + + ret =3D kstrtobool(buf, &enabled); + if (ret) + return ret; + + guard(cpus_read_lock)(); + guard(mutex)(&mprof_cfg_lock); + new =3D *mprof_cfg; + new.enabled =3D enabled; + mprof_publish(&new); + + return count; +} + +static DEVICE_ATTR_RW(enabled); + +static struct attribute *ibs_mprof_attributes[] =3D { + &dev_attr_enabled.attr, + NULL +}; + +static const struct attribute_group ibs_mprof_attr_group =3D { + .name =3D "ibs-mprof", + .attrs =3D ibs_mprof_attributes, +}; + +static int mprof_tunables_init(void) +{ + struct device *dev_root; + int ret =3D -ENODEV; + + dev_root =3D bus_get_dev_root(&cpu_subsys); + if (!dev_root) + return ret; + + ret =3D sysfs_create_group(&dev_root->kobj, &ibs_mprof_attr_group); + put_device(dev_root); + if (ret) + return ret; + + mprof_debugfs_init(); + return 0; +} + static int __init mprof_access_profiling_init(void) { u32 mprof_caps; @@ -460,6 +826,9 @@ static int __init mprof_access_profiling_init(void) mw->cpu =3D cpu; } =20 + /* Publish the default config before the startup callback consumes it. */ + mprof_config_init(); + ret =3D cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/amd/ibs_mprof:online", x86_amd_ibs_mprof_online, @@ -470,10 +839,26 @@ static int __init mprof_access_profiling_init(void) =20 mprof_pm_init(); =20 + ret =3D mprof_tunables_init(); + if (ret) + goto out_hp; + pr_info("IBS Memory Profiler is available for memory access profiling\n"); return 0; =20 +out_hp: + mprof_pm_destroy(); + cpuhp_remove_state(mprof_cpuhp_state); out_free: + /* + * With ibs-memprof=3D1 the profiler was armed above, so an interrupt may + * have queued a worker that dereferences mprof_s. Producers are now + * silenced (cpuhp offline disarmed every CPU, or cpuhp_setup_state + * rolled back its arming), so nothing re-schedules; drain any queued or + * running worker before freeing the per-CPU buffer it uses. + */ + for_each_possible_cpu(cpu) + cancel_work_sync(&per_cpu_ptr(&mprof_work, cpu)->work); free_percpu(mprof_s); pr_info("IBS Memory Profiler failed to initialize\n"); return ret; --=20 2.34.1