From nobody Thu Sep 24 13:38:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4396B3624C5; Thu, 24 Sep 2026 05:51:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790229074; cv=none; b=ML92T53gkD6oYVZajF8OCCfsFqzLm3lDy20Knqa3xkrwljuzSxQEC0TRoXs0tyOJxSCYVgWexwNU1zzE0ZweKPOWe28cyB3CaWMaNGEyLm0frpb0MCVtrrXrVphfev23AgCwHW13nLBvnS8zWJnJ9mJpJe32ImvWojwoi/kyqVk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790229074; c=relaxed/simple; bh=A7pJRhG7NpywLWWaoMaC1pUfWSZ7AsdAS4qYr97/LYU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=G+hyQT8B4MbbEeIT3gcEvmu8dnmBkeHoPnwrVL3QNBebm/lLjDChuTKN/YK6+5T0b1i9/QEzE806YiO+bOeOx8+liMNYOpMRvjITvIsizTYbmhrJXgMalAJdHIzMjQ/cNk9bOqrvuSoO/ApRboval3EuueNI787ZTiqY/y8Ygjw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=i/PKkUWQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="i/PKkUWQ" Received: by smtp.kernel.org (Postfix) with ESMTPS id E4BE7C2BCF5; Thu, 24 Sep 2026 05:51:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790229074; bh=A7pJRhG7NpywLWWaoMaC1pUfWSZ7AsdAS4qYr97/LYU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=i/PKkUWQCRZeWuO/uJcScyhyJRSLsD5k/27RsQRzQZnnab/NxIN41Btoy0I+1OGv/ DK08GgTz7lxN6iuOZm2RAxVsOhX6ScgpFOxDwP2daTSLoICS5HgtWu3QEAH12fCre7 O6kTuAXPnYUOSdWch14qHeXP8J5YDquBu7XtV8Cs2C9h8l2nRGeTEpkb+KzfmoKutq 7sdAGqMjAZKA6iMyMAFPjdtfrLnMsy5VI8Xzx8KvR5+3XpK7DfENen7AUwxA8jRmAI ZPbpABZqkMsK21gmwgzPWLG/tBJ7nnnvFdtqX9R0G0R3MdP2zwKW316NSQyXw8qtWG 8rTdoB0kv+bHg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD13AC98310; Thu, 24 Sep 2026 05:51:13 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Thu, 24 Sep 2026 05:51:08 +0000 Subject: [PATCH v2 1/3] spi: dt-bindings: amlogic,meson-gx-spicc: add T7 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260924-t7-node-new-v2-1-319d3c19b4b2@amlogic.com> References: <20260924-t7-node-new-v2-0-319d3c19b4b2@amlogic.com> In-Reply-To: <20260924-t7-node-new-v2-0-319d3c19b4b2@amlogic.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790229071; l=1575; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=Cr+H2n7PINWdLBG8TQcHVSgRz7Rd2HsUY6kC9/oqBVw=; b=L8OZAvoJnP38zJl2OU6S+U61CNjL2hKNteVFl5Qj4MLNqx4kxoz1SHfp03/tNLBbTKSCMYOYC PfUe3ykqN4ZC+T5X392SZTEs6CCSZ6a/FBInRdr18naeFhtkGIlDhU7 X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Add the Amlogic T7 SPICC compatible to the device tree binding. The T7 controller is compatible with the existing G12A SPICC implementation, so require amlogic,meson-g12a-spicc as a fallback compatible for T7 devices. Signed-off-by: Xianwei Zhao --- .../devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml | 13 +++++++++= ---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.y= aml b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml index 4e28e6e9d8e0..f0ba15402a4c 100644 --- a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml +++ b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml @@ -16,10 +16,15 @@ description: | =20 properties: compatible: - enum: - - amlogic,meson-gx-spicc # SPICC controller on Amlogic GX and compat= ible SoCs - - amlogic,meson-axg-spicc # SPICC controller on Amlogic AXG and comp= atible SoCs - - amlogic,meson-g12a-spicc # SPICC controller on Amlogic G12A and co= mpatible SoCs + oneOf: + - items: + - enum: + - amlogic,t7-spicc + - const: amlogic,meson-g12a-spicc + - enum: + - amlogic,meson-gx-spicc # SPICC controller on Amlogic GX and co= mpatible SoCs + - amlogic,meson-axg-spicc # SPICC controller on Amlogic AXG and = compatible SoCs + - amlogic,meson-g12a-spicc # SPICC controller on Amlogic G12A an= d compatible SoCs =20 interrupts: maxItems: 1 --=20 2.52.0 From nobody Thu Sep 24 13:38:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 438AD3126C2; Thu, 24 Sep 2026 05:51:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790229074; cv=none; b=YtGS36o04KphiBa6F6a4mLj+8rlVYiKOJK7CiFbG1BTHB2siKDmTtpN/k4PGVvonFQCyTLjOiiYr5c9mZoEVbui6izo9oMjKrlvs6kcYWda3XsYqoqaChut74hOCktUtwo5B1audS+Q1LHx1L8fhJPX8NCENSkkfrohNwlsG0qE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790229074; c=relaxed/simple; bh=l41JS5K56S3JMbzVD/c0nALjK4wnkjK4/XwAbncRLKM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=W/lyF4sAnxAeaAk1uhbZ5D2y+i0WDttQXN9XmjBf4OMNcjrenWfME9ymZYIgE6ol7V0rJjtjvu3YL0xmNCN1cJxTde6IorrFpLN/041WVvUSjgUIPKJqJLpqDsQ/FSISw9ZLZS6kLfONLKR0WptHkrLBTCYaLlc0WnG4WkiyN5M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XIdPA8G+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XIdPA8G+" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1085DC2BCF6; Thu, 24 Sep 2026 05:51:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790229074; bh=l41JS5K56S3JMbzVD/c0nALjK4wnkjK4/XwAbncRLKM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=XIdPA8G+vv0RpHabyNFHTKbIjxeM0ZClNzAaqxDlurMYVKrI0LDCYRuohYwNwwfbG 20EDKdTw0ZGcDXSdmz2rHanrZuvNU0vJVC1LTfHw2vKAG8u4HwtVSlVDU8AtSbtpT+ J/ZKrvAhNI5Cu5xXNrvbRYj4164PT0QyvXXEuQPqgTmziyiFK6jWDuaVZ/FoZpupEl QZl1QHXNVFashO1QVRL9gHx4QRLgwwC97XqxoH13xaiBBBG5SroDCvv3UCg2zGh1/S l2dl5BsunVuGoZ/76I1gC/hBVgMTUJkdQ9p7m8SzG1Z+m+QT6dd4bdY9hbUJtFLRvG dw3SIGJ14h4aw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEBD8C982FD; Thu, 24 Sep 2026 05:51:13 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Thu, 24 Sep 2026 05:51:09 +0000 Subject: [PATCH v2 2/3] dt-bindings: net: meson-dwmac: add T7 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260924-t7-node-new-v2-2-319d3c19b4b2@amlogic.com> References: <20260924-t7-node-new-v2-0-319d3c19b4b2@amlogic.com> In-Reply-To: <20260924-t7-node-new-v2-0-319d3c19b4b2@amlogic.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790229071; l=2194; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=OuWtCvG4zrP01yJiFjTkY4chxxarHmWUIHB1zdrvrrw=; b=uOsEnSyIlN8J9zL2lHAk+qTRy4/RCF3TeOmRM09rdTe4uQU0D49uiM6TE1HvbeeTvVGRUoVG1 mGboAlM++RIA2XI3U47qg+ULRzkuiibd1WI5B66c3AlVk/+ne+Kisgr X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Add the T7 compatible to the Meson DWMAC binding. The T7 DWMAC controller requires the following compatible combination: amlogic,t7-dwmac amlogic,meson-axg-dwmac snps,dwmac-4.00 Add a conditional schema check to enforce this compatible combination when amlogic,t7-dwmac is used. Signed-off-by: Xianwei Zhao --- .../devicetree/bindings/net/amlogic,meson-dwmac.yaml | 17 +++++++++++++= ++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml= b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml index 5c91716d1f21..b529ca5577a9 100644 --- a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml @@ -23,11 +23,24 @@ select: - amlogic,meson-gxbb-dwmac - amlogic,meson-axg-dwmac - amlogic,meson-g12a-dwmac + - amlogic,t7-dwmac required: - compatible =20 allOf: - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + const: amlogic,t7-dwmac + then: + properties: + compatible: + items: + - const: amlogic,t7-dwmac + - const: amlogic,meson-axg-dwmac + - const: snps,dwmac-4.00 - if: properties: compatible: @@ -38,6 +51,7 @@ allOf: - amlogic,meson-gxbb-dwmac - amlogic,meson-axg-dwmac - amlogic,meson-g12a-dwmac + - amlogic,t7-dwmac =20 then: properties: @@ -93,6 +107,7 @@ allOf: - amlogic,meson8m2-dwmac - amlogic,meson-gxbb-dwmac - amlogic,meson-axg-dwmac + - amlogic,t7-dwmac then: properties: rx-internal-delay-ps: @@ -139,8 +154,10 @@ properties: - amlogic,meson-gxbb-dwmac - amlogic,meson-axg-dwmac - amlogic,meson-g12a-dwmac + - amlogic,t7-dwmac contains: enum: + - snps,dwmac-4.00 - snps,dwmac-3.70a - snps,dwmac =20 --=20 2.52.0 From nobody Thu Sep 24 13:38:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55D9B3D3D14; Thu, 24 Sep 2026 05:51:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790229074; cv=none; b=tnIFwCNP9UvPxjOtU3aaVlIKwlMD65ovTv8l2ul1UCjk8jl/rO1HV9Xn7qtDcEQtJNg69nMk7jiQKN2SxcDH+hhdBII8dSwWGG8kxw2sK0EB6qv4h3OfE3c7qoOaFBBQYbVuoKn+p/iVQJCS5FQBI0rGQRxl+gsRo+Y7Ufb93QU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790229074; c=relaxed/simple; bh=cOJhKPTRIhomPomIDLLJbzfUTWDuoaZiXnhUJl8tXEA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JpzwkM86aL/shyeb9dyDsbbjHCoqfL9nvKIp7USIIT/la6nAIiNtoXqnWA+myE7SOnnJMN9rpDusoBo+wlrNQPmVdRc4T/Uk8ykFxwWReQnrRTm/UOIgadi0laU/mQ5pTAj8jtvps1n+XtEAiycORdPuIkzqfBsQQmxVH8S3g+4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OtTbJos/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OtTbJos/" Received: by smtp.kernel.org (Postfix) with ESMTPS id 25F05C2BCFF; Thu, 24 Sep 2026 05:51:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790229074; bh=cOJhKPTRIhomPomIDLLJbzfUTWDuoaZiXnhUJl8tXEA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=OtTbJos/DC+BfzQgApfUzqbGg7wO2OprVF9jc9vaod0O/yEKyvy4Ln3bCUeRlMxo3 G8ve9JTba+Xt/4I7o/u3gC/oqg8cvVZwZF6lxUHGULWjAjryN58d8fkfuflP9NFZv7 b/aQ/8swminGrniJhb3HEfX273D2E0As4o6vQAFPQLLcbIc1lbJlhyyv4uXrU0I4jg BtBlJXBejEcMyXS/cy48Jhpl144MNZ0rj/ye6TSQ1lwqD2C2KojzEC4ywLcRIbh1TU HYOiV6p3SyxexqYDGKP9lMUJgEZz21ZGQNcw/Obm5mq02AlFLUZy+Yu7NPIqMAL6ZQ zeqY2oTahWW8Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DFB1C98314; Thu, 24 Sep 2026 05:51:14 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Thu, 24 Sep 2026 05:51:10 +0000 Subject: [PATCH v2 3/3] arm64: dts: amlogic: add T7 peripheral nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260924-t7-node-new-v2-3-319d3c19b4b2@amlogic.com> References: <20260924-t7-node-new-v2-0-319d3c19b4b2@amlogic.com> In-Reply-To: <20260924-t7-node-new-v2-0-319d3c19b4b2@amlogic.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790229071; l=19875; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=sUrOOPo5vZtzDxegxJJ40rDMF4d5JRSGveFPFVX+gGo=; b=eyHQ1oP3YSybEW8h/7CLa+kLf+7vjGa1iFd936sGjRlHUYXF4GA5UVw3ZxEe+mwzOHE5vVGUP FxNXgNqlW5wB0dIKnS2a/T7DBdWWebjYuPlxtIt2Lgy6FRAb693mKza X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Add device tree descriptions for the peripherals on the Amlogic T7 SoC and the T7 A311D2 AN400 board. Add support for the T7 Ethernet controller, SPI controllers, I2C controllers, UARTs, pinctrl groups, regulators, and reserved memory. Also enable the Ethernet controller on the AN400 board. Signed-off-by: Xianwei Zhao --- .../boot/dts/amlogic/amlogic-t7-a311d2-an400.dts | 153 +++++++ arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 462 +++++++++++++++++= ++++ 2 files changed, 615 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts b/arch= /arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts index ca7536f772ff..50df961fba75 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts @@ -24,12 +24,159 @@ memory@0 { 0x00000001 0x00000000 0x00000000 0x20000000>; }; =20 + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@5000000 { + reg =3D <0x0 0x05000000 0x0 0x300000>; + no-map; + }; + + /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ + secmon_reserved_bl32: secmon@5300000 { + reg =3D <0x0 0x05300000 0x0 0x2000000>; + no-map; + }; + }; + xtal: xtal-clk { compatible =3D "fixed-clock"; clock-frequency =3D <24000000>; clock-output-names =3D "xtal"; #clock-cells =3D <0>; }; + + dc_in: regulator-dc-in { + compatible =3D "regulator-fixed"; + regulator-name =3D "12V"; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_5v: regulator-vcc-5v { + compatible =3D "regulator-fixed"; + vin-supply =3D <&dc_in>; + regulator-name =3D "VCC5V"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio GPIOH_1 GPIO_ACTIVE_HIGH>; + startup-delay-us =3D <70000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + vddao_3v3: regulator-vddao-3v3 { + vin-supply =3D <&dc_in>; + compatible =3D "regulator-fixed"; + regulator-name =3D "VDDAO_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + startup-delay-us =3D <70000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd1v8_reg: regulator-vdd-1v8 { + vin-supply =3D <&dc_in>; + compatible =3D "regulator-fixed"; + regulator-name =3D "VDDIO_1V8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + startup-delay-us =3D <70000>; + regulator-boot-on; + regulator-always-on; + }; + + vddao_1v8: regulator-vddao-1v8 { + compatible =3D "regulator-fixed"; + vin-supply =3D <&vddao_3v3>; + regulator-name =3D "VDDAO_1V8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vddio_3v3: regulator-vddio-3v3 { + compatible =3D "regulator-fixed"; + vin-supply =3D <&vddao_3v3>; + regulator-name =3D "VDDIO_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&gpio GPIO_TEST_N GPIO_ACTIVE_HIGH>; + startup-delay-us =3D <70000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + sd_3v3: regulator-sd-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "SD_3V3: SD/TF"; + vin-supply =3D <&vddao_3v3>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&gpio GPIOD_11 GPIO_ACTIVE_LOW>; /* 0R */ + regulator-boot-on; + regulator-always-on; + }; + + vddio_c: regulator-sd-1v8-3v3 { + compatible =3D "regulator-gpio"; + vin-supply =3D <&vddio_3v3>; + regulator-name =3D "VDDIO_C: SD/TF."; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + gpios =3D <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>; + gpios-states =3D <1>; + + /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ + states =3D <1800000 1 + 3300000 0>; + }; + + vddq_1v1: regulator-vddq-1v1 { + compatible =3D "regulator-fixed"; + vin-supply =3D <&dc_in>; + regulator-name =3D "VDDQ_1V1"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + gpio =3D <&gpio GPIOD_10 GPIO_ACTIVE_HIGH>; + startup-delay-us =3D <70000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + vddqlp_0v6: regulator-vddqlp-0v6 { + vin-supply =3D <&dc_in>; + compatible =3D "regulator-fixed"; + regulator-name =3D "VDDQLP_0V6"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <600000>; + startup-delay-us =3D <70000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + vdd_ddr: regulator-vdd-ddr { + vin-supply =3D <&dc_in>; + compatible =3D "regulator-fixed"; + regulator-name =3D "VDD_DDR"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + startup-delay-us =3D <70000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; }; =20 &uart_a { @@ -37,3 +184,9 @@ &uart_a { clock-names =3D "xtal", "pclk", "baud"; status =3D "okay"; }; + +ðmac { + status =3D "okay"; + phy-handle =3D <&internal_ephy>; + phy-mode =3D "rmii"; +}; diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-t7.dtsi index 8f3f1c0579a0..33b0f09a85a4 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -5,10 +5,12 @@ =20 #include #include +#include #include "amlogic-t7-reset.h" #include #include #include +#include =20 / { interrupt-parent =3D <&gic>; @@ -238,6 +240,30 @@ soc { #size-cells =3D <2>; ranges; =20 + ethmac: ethernet@fdc00000 { + compatible =3D "amlogic,t7-dwmac", + "amlogic,meson-axg-dwmac", + "snps,dwmac-4.00"; + reg =3D <0x0 0xfdc00000 0x0 0x10000>, + <0x0 0xfe024000 0x0 0x8>; + interrupts =3D ; + interrupt-names =3D "macirq"; + power-domains =3D <&pwrc PWRC_T7_ETH_ID>; + clocks =3D <&clkc_periphs CLKID_SYS_ETH>, + <&scmi_clk CLKID_FCLK_DIV2>, + <&scmi_clk CLKID_FCLK_50M>; + clock-names =3D "stmmaceth", "clkin0", "clkin1"; + rx-fifo-depth =3D <4096>; + tx-fifo-depth =3D <2048>; + status =3D "disabled"; + + mdio0: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + gic: interrupt-controller@fff01000 { compatible =3D "arm,gic-400"; #interrupt-cells =3D <3>; @@ -386,6 +412,206 @@ mux { }; }; =20 + i2c0_ao_pins2: i2c0-ao-pins2 { + mux { + groups =3D "i2c0_ao_sda_e", + "i2c0_ao_sck_e"; + function =3D "i2c0_ao"; + drive-strength-microamp =3D <3000>; + bias-disable; + }; + }; + + i2c1_ao_pins: i2c1-ao-pins { + mux { + groups =3D "i2c1_ao_sda", + "i2c1_ao_sck"; + function =3D "i2c1_ao"; + drive-strength-microamp =3D <3000>; + bias-disable; + }; + }; + + i2c0_pins1: i2c0-pins1 { + mux { + groups =3D "i2c0_sda_t", + "i2c0_sck_t"; + function =3D "i2c0"; + drive-strength-microamp =3D <3000>; + bias-disable; + }; + }; + + i2c0_pins2: i2c0-pins2 { + mux { + groups =3D "i2c0_sda_h", + "i2c0_sck_h"; + function =3D "i2c0"; + drive-strength-microamp =3D <3000>; + bias-disable; + }; + }; + + i2c1_pins1: i2c1-pins1 { + mux { + groups =3D "i2c1_sda", + "i2c1_sck"; + function =3D "i2c1"; + drive-strength-microamp =3D <3000>; + bias-disable; + }; + }; + + i2c2_pins1: i2c2-pins1 { + mux { + groups =3D "i2c2_sda_x", + "i2c2_sck_x"; + function =3D "i2c2"; + drive-strength-microamp =3D <3000>; + bias-disable; + }; + }; + + i2c2_pins2: i2c2-pins2 { + mux { + groups =3D "i2c2_sda_t", + "i2c2_sck_t"; + function =3D "i2c2"; + drive-strength-microamp =3D <3000>; + bias-disable; + }; + }; + + i2c2_pins3: i2c2-pins3 { + mux { + groups =3D "i2c2_sda_m", + "i2c2_sck_m"; + function =3D "i2c2"; + drive-strength-microamp =3D <3000>; + bias-disable; + }; + }; + + i2c3_pins1: i2c3-pins1 { + mux { + groups =3D "i2c3_sda_m", + "i2c3_sck_m"; + function =3D "i2c3"; + drive-strength-microamp =3D <3000>; + bias-disable; + }; + }; + + i2c3_pins2: i2c3-pins2 { + mux { + groups =3D "i2c3_sda_h", + "i2c3_sck_h"; + function =3D "i2c3"; + drive-strength-microamp =3D <3000>; + bias-disable; + }; + }; + + i2c4_pins1: i2c4-pins1 { + mux { + groups =3D "i2c4_sda_y", + "i2c4_sck_y"; + function =3D "i2c4"; + drive-strength-microamp =3D <3000>; + bias-disable; + }; + }; + + i2c4_pins2: i2c4-pins2 { + mux { + groups =3D "i2c4_sda_h", + "i2c4_sck_h"; + function =3D "i2c4"; + drive-strength-microamp =3D <3000>; + bias-disable; + }; + }; + + i2c5_pins1: i2c5-pins1 { + mux { + groups =3D "i2c5_sda", + "i2c5_sck"; + function =3D "i2c5"; + drive-strength-microamp =3D <3000>; + bias-disable; + }; + }; + + spicc0_pins: spicc0-pins { + mux { + groups =3D "spi0_mosi", + "spi0_miso", + "spi0_sclk"; + function =3D "spi0"; + drive-strength-microamp =3D <2000>; + }; + }; + + spicc1_pins1: spicc1-pins1 { + mux { + groups =3D "spi1_mosi_c", + "spi1_miso_c", + "spi1_sclk_c"; + function =3D "spi1"; + drive-strength-microamp =3D <2000>; + }; + }; + + spicc1_pins2: spicc1-pins2 { + mux { + groups =3D "spi1_mosi_m", + "spi1_miso_m", + "spi1_sclk_m"; + function =3D "spi1"; + drive-strength-microamp =3D <2000>; + }; + }; + + spicc2_pins: spicc2-pins { + mux { + groups =3D "spi2_mosi", + "spi2_miso", + "spi2_sclk"; + function =3D "spi2"; + drive-strength-microamp =3D <2000>; + }; + }; + + spicc3_pins: spicc3-pins { + mux { + groups =3D "spi3_mosi", + "spi3_miso", + "spi3_sclk"; + function =3D "spi3"; + drive-strength-microamp =3D <2000>; + }; + }; + + spicc4_pins: spicc4-pins { + mux { + groups =3D "spi4_mosi", + "spi4_miso", + "spi4_sclk"; + function =3D "spi4"; + drive-strength-microamp =3D <2000>; + }; + }; + + spicc5_pins: spicc5-pins { + mux { + groups =3D "spi5_mosi", + "spi5_miso", + "spi5_sclk"; + function =3D "spi5"; + drive-strength-microamp =3D <2000>; + }; + }; + pwm_a_pins: pwm-a { mux { groups =3D "pwm_a"; @@ -622,6 +848,51 @@ uart_a: serial@78000 { status =3D "disabled"; }; =20 + uart_b: serial@7a000 { + compatible =3D "amlogic,t7-uart", "amlogic,meson-s4-uart"; + reg =3D <0x0 0x7a000 0x0 0x18>; + interrupts =3D ; + clocks =3D <&xtal>, <&clkc_periphs CLKID_SYS_UART_B>, <&xtal>; + clock-names =3D "xtal", "pclk", "baud"; + status =3D "disabled"; + }; + + uart_c: serial@7c000 { + compatible =3D "amlogic,t7-uart", "amlogic,meson-s4-uart"; + reg =3D <0x0 0x7c000 0x0 0x18>; + interrupts =3D ; + clocks =3D <&xtal>, <&clkc_periphs CLKID_SYS_UART_C>, <&xtal>; + clock-names =3D "xtal", "pclk", "baud"; + status =3D "disabled"; + }; + + uart_d: serial@7e000 { + compatible =3D "amlogic,t7-uart", "amlogic,meson-s4-uart"; + reg =3D <0x0 0x7e000 0x0 0x18>; + interrupts =3D ; + clocks =3D <&xtal>, <&clkc_periphs CLKID_SYS_UART_D>, <&xtal>; + clock-names =3D "xtal", "pclk", "baud"; + status =3D "disabled"; + }; + + uart_e: serial@80000 { + compatible =3D "amlogic,t7-uart", "amlogic,meson-s4-uart"; + reg =3D <0x0 0x80000 0x0 0x18>; + interrupts =3D ; + clocks =3D <&xtal>, <&clkc_periphs CLKID_SYS_UART_E>, <&xtal>; + clock-names =3D "xtal", "pclk", "baud"; + status =3D "disabled"; + }; + + uart_f: serial@82000 { + compatible =3D "amlogic,t7-uart", "amlogic,meson-s4-uart"; + reg =3D <0x0 0x82000 0x0 0x18>; + interrupts =3D ; + clocks =3D <&xtal>, <&clkc_periphs CLKID_SYS_UART_F>, <&xtal>; + clock-names =3D "xtal", "pclk", "baud"; + status =3D "disabled"; + }; + gp0: clock-controller@8080 { compatible =3D "amlogic,t7-gp0-pll"; reg =3D <0x0 0x8080 0x0 0x20>; @@ -688,6 +959,39 @@ sec_ao: ao-secure@10220 { amlogic,has-chip-id; }; =20 + eth_phy: mdio-multiplexer@28000 { + compatible =3D "amlogic,g12a-mdio-mux"; + reg =3D <0x0 0x28000 0x0 0xa4>; + + clocks =3D <&clkc_periphs CLKID_SYS_ETHPHY>, + <&xtal>, + <&scmi_clk CLKID_FCLK_50M>; + clock-names =3D "pclk", "clkin0", "clkin1"; + mdio-parent-bus =3D <&mdio0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ext_mdio: mdio@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + int_mdio: mdio@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + internal_ephy: ethernet-phy@8 { + compatible =3D "ethernet-phy-id0180.3301", + "ethernet-phy-ieee802.3-c22"; + interrupts =3D ; + reg =3D <8>; + max-speed =3D <100>; + }; + }; + }; + pwm_ao_ef: pwm@30000 { compatible =3D "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; reg =3D <0x0 0x30000 0x0 0x24>; @@ -711,6 +1015,84 @@ clock-measurer@48000 { reg =3D <0x0 0x48000 0x0 0x1c>; }; =20 + spicc3: spi@4a000 { + compatible =3D "amlogic,t7-spicc", "amlogic,meson-g12a-spicc"; + reg =3D <0x0 0x4a000 0x0 0x44>; + power-domains =3D <&pwrc PWRC_T7_SPICC3_ID>; + interrupts =3D ; + clocks =3D <&clkc_periphs CLKID_SYS_SPICC3>, + <&clkc_periphs CLKID_SPICC3>; + clock-names =3D "core", "pclk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spicc4: spi@4c000 { + compatible =3D "amlogic,t7-spicc", "amlogic,meson-g12a-spicc"; + reg =3D <0x0 0x4c000 0x0 0x44>; + power-domains =3D <&pwrc PWRC_T7_SPICC4_ID>; + interrupts =3D ; + clocks =3D <&clkc_periphs CLKID_SYS_SPICC4>, + <&clkc_periphs CLKID_SPICC4>; + clock-names =3D "core", "pclk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spicc5: spi@4e000 { + compatible =3D "amlogic,t7-spicc", "amlogic,meson-g12a-spicc"; + reg =3D <0x0 0x4e000 0x0 0x44>; + power-domains =3D <&pwrc PWRC_T7_SPICC5_ID>; + interrupts =3D ; + clocks =3D <&clkc_periphs CLKID_SYS_SPICC5>, + <&clkc_periphs CLKID_SPICC5>; + clock-names =3D "core", "pclk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spicc0: spi@50000 { + compatible =3D "amlogic,t7-spicc", "amlogic,meson-g12a-spicc"; + reg =3D <0x0 0x50000 0x0 0x44>; + power-domains =3D <&pwrc PWRC_T7_SPICC0_ID>; + interrupts =3D ; + clocks =3D <&clkc_periphs CLKID_SYS_SPICC0>, + <&clkc_periphs CLKID_SPICC0>; + clock-names =3D "core", "pclk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spicc1: spi@52000 { + compatible =3D "amlogic,t7-spicc", "amlogic,meson-g12a-spicc"; + reg =3D <0x0 0x52000 0x0 0x44>; + power-domains =3D <&pwrc PWRC_T7_SPICC1_ID>; + interrupts =3D ; + clocks =3D <&clkc_periphs CLKID_SYS_SPICC1>, + <&clkc_periphs CLKID_SPICC1>; + clock-names =3D "core", "pclk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spicc2: spi@54000 { + compatible =3D "amlogic,t7-spicc", "amlogic,meson-g12a-spicc"; + reg =3D <0x0 0x54000 0x0 0x44>; + power-domains =3D <&pwrc PWRC_T7_SPICC2_ID>; + interrupts =3D ; + clocks =3D <&clkc_periphs CLKID_SYS_SPICC2>, + <&clkc_periphs CLKID_SPICC2>; + clock-names =3D "core", "pclk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + pwm_ab: pwm@58000 { compatible =3D "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; reg =3D <0x0 0x58000 0x0 0x24>; @@ -756,6 +1138,86 @@ pwm_ao_cd: pwm@60000 { status =3D "disabled"; }; =20 + i2c0: i2c@66000 { + compatible =3D "amlogic,t7-i2c", "amlogic,meson-axg-i2c"; + reg =3D <0x0 0x66000 0x0 0x48>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clkc_periphs CLKID_SYS_I2C_M_A>; + status =3D "disabled"; + }; + + i2c1: i2c@68000 { + compatible =3D "amlogic,t7-i2c", "amlogic,meson-axg-i2c"; + reg =3D <0x0 0x68000 0x0 0x48>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clkc_periphs CLKID_SYS_I2C_M_B>; + status =3D "disabled"; + }; + + i2c2: i2c@6a000 { + compatible =3D "amlogic,t7-i2c", "amlogic,meson-axg-i2c"; + reg =3D <0x0 0x6a000 0x0 0x48>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clkc_periphs CLKID_SYS_I2C_M_C>; + status =3D "disabled"; + }; + + i2c3: i2c@6c000 { + compatible =3D "amlogic,t7-i2c", "amlogic,meson-axg-i2c"; + reg =3D <0x0 0x6c000 0x0 0x48>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clkc_periphs CLKID_SYS_I2C_M_D>; + status =3D "disabled"; + }; + + i2c4: i2c@6e000 { + compatible =3D "amlogic,t7-i2c", "amlogic,meson-axg-i2c"; + reg =3D <0x0 0x6e000 0x0 0x48>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clkc_periphs CLKID_SYS_I2C_M_E>; + status =3D "disabled"; + }; + + i2c5: i2c@70000 { + compatible =3D "amlogic,t7-i2c", "amlogic,meson-axg-i2c"; + reg =3D <0x0 0x070000 0x0 0x48>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clkc_periphs CLKID_SYS_I2C_M_F>; + status =3D "disabled"; + }; + + i2c_ao_a: i2c@76000 { + compatible =3D "amlogic,t7-i2c", "amlogic,meson-axg-i2c"; + reg =3D <0x0 0x076000 0x0 0x48>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clkc_periphs CLKID_SYS_I2C_AO_A>; + status =3D "disabled"; + }; + + i2c_ao_b: i2c@86000 { + compatible =3D "amlogic,t7-i2c", "amlogic,meson-axg-i2c"; + reg =3D <0x0 0x086000 0x0 0x48>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clkc_periphs CLKID_SYS_I2C_AO_B>; + status =3D "disabled"; + }; + sd_emmc_a: mmc@88000 { compatible =3D "amlogic,t7-mmc", "amlogic,meson-axg-mmc"; reg =3D <0x0 0x88000 0x0 0x800>; --=20 2.52.0