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Wed, 23 Sep 2026 12:21:48 -0700 (PDT) X-Received: by 2002:a05:7300:ea11:b0:33c:e82:70c8 with SMTP id 5a478bee46e88-34000c300c1mr119839eec.31.1790191308191; Wed, 23 Sep 2026 12:21:48 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33e9684d643sm17609309eec.18.2026.09.23.12.21.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 12:21:47 -0700 (PDT) From: Taniya Das Date: Thu, 24 Sep 2026 00:51:31 +0530 Subject: [PATCH v2 1/3] clk: qcom: clk-alpha-pll: support a 28-bit ALPHA_VAL width Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260924-nords_dprx-v2-1-fa4364e087ef@oss.qualcomm.com> References: <20260924-nords_dprx-v2-0-fa4364e087ef@oss.qualcomm.com> In-Reply-To: <20260924-nords_dprx-v2-0-fa4364e087ef@oss.qualcomm.com> To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Abel Vesa Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das , Abel Vesa X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-ORIG-GUID: sY52FG6dUAn6MkXS5-OtIdeBeCPZavaW X-Authority-Analysis: v=2.4 cv=J4s/fwnS c=1 sm=1 tr=0 ts=6ab426cd cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=iX_rjOfq5r2Sv1zA3QwA:9 a=+jEqtf1s3R9VXZ0wqowq2kgwd+I=:19 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIzMDA3NyBTYWx0ZWRfX9luXyjtdbv9i D8PXyNdnN2lCA2t/lyiVBGwHQabgEdLSr5C+43Txecsx2dp316vG7BtcZAbAdmSxv7lWLTVY3Kw VBmxly7ZP0chOPmKeHqdJ/UhRYjT/vwoovgNqv8GnZxu7ehTWyaJmFU53J81ZUQPXrWed/7tJ5J PFouZsohbw+gv5XFGjrtw9hOhSQWaScajYozwmn5sT9U3YuXff7K7AT2rugkqovKupRLSl0KjRT 73ouo3KXmtQFumqQ/D7k2LnjQOjSuwytxmBMvrEcYgJVz7tNVOucVPUUc8mCI4WMktIscKnLTx/ OyQFGnwx9R31gfhP05R7SuiuOoGyfuTAENXkd6paPlhxgvilopz8wmKto6WERGOcFLNZn4BZ961 lJUib/HnVOzLfFIdkUtk1GwatXBb6sIdlHJ323RGpfQQQ4px78eUFgVCWC8qeABv4elOzwSnKLX Pz0a6FHw5TnnN+HM16Q== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIzMDA3NyBTYWx0ZWRfX6YZVpMa63CoU oFjIBdZbNtDNDJlXlnlhY/vWEbdGHuVEBDlPInfKJZN8a4DEk/cGK/x7XPS9KVmQUhKS1AoJp9s XQ258YDyt48Tgz/wBPNQNSoG4NhMh9I= X-Proofpoint-GUID: sY52FG6dUAn6MkXS5-OtIdeBeCPZavaW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-23_06,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 spamscore=0 impostorscore=0 priorityscore=1501 phishscore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609230077 On some PLLs the PLL_ALPHA_VAL register has been increased to 28 bits to carry the fractional word at a finer resolution, for example the ZONDA_OLE instances on the Qualcomm Nord DPRX. The alpha-PLL core, however, derives the ALPHA_VAL width solely from the register-map layout and can only express 16 or 40 bits, so it programs and reads back the 28-bit configuration at the wrong scale on both the set_rate/slew and recalc_rate paths, making the PLL lock to and report the wrong rate. Add a way to identify the wider register: an optional alpha_width field in struct clk_alpha_pll that, when non-zero, supersedes the register-derived width. This feeds pll_alpha_width(), so the recalc_rate and round_rate math scale the fractional word correctly, and the Zonda set_rate L-adjust MSB check is derived from the active width instead of a hardcoded BIT(15). PLLs that leave the field zero retain the previous behaviour. Reviewed-by: Abel Vesa Signed-off-by: Taniya Das Reviewed-by: Shawn Guo --- drivers/clk/qcom/clk-alpha-pll.c | 8 ++++---- drivers/clk/qcom/clk-alpha-pll.h | 3 +++ 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-= pll.c index 60173b076cc5f16bb55343a1d1136eb07f3c050f..be5840600967942ea0d8df9e8ec= fa2da763c4d23 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -41,7 +41,6 @@ #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) # define PLL_POST_DIV_SHIFT 8 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width ? (p)->width - 1 : 3, 0) -# define PLL_ALPHA_MSB BIT(15) # define PLL_ALPHA_EN BIT(24) # define PLL_ALPHA_MODE BIT(25) # define PLL_VCO_SHIFT 20 @@ -382,8 +381,9 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); #define ZONDA_PLL_FREQ_LOCK_DET BIT(29) =20 #define pll_alpha_width(p) \ - ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) =3D=3D 4) ? \ - ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) + ((p)->alpha_width ? (p)->alpha_width : \ + ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) =3D=3D 4) ? \ + ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)) =20 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p))= =3D=3D 4) =20 @@ -2290,7 +2290,7 @@ static int clk_zonda_pll_set_rate(struct clk_hw *hw, = unsigned long rate, if (ret < 0) return ret; =20 - if (a & PLL_ALPHA_MSB) + if (a & BIT(alpha_width - 1)) zonda_pll_adjust_l_val(rate, prate, &l); =20 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-= pll.h index 3a2157bebc52cd15f55381a068953f21be18f6bb..ab3b4f4fc7501df0fa3f59d741d= 64646383e4cfd 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -86,6 +86,8 @@ struct pll_vco { * struct clk_alpha_pll - phase locked loop (PLL) * @offset: base address of registers * @regs: alpha pll register map (see @clk_alpha_pll_regs) + * @alpha_width: optional override of the ALPHA_VAL width in bits; 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Signed-off-by: Taniya Das --- .../bindings/clock/qcom,nord-dprxcc.yaml | 68 ++++++++++++++++++= ++++ include/dt-bindings/clock/qcom,nord-dprxcc.h | 27 +++++++++ 2 files changed, 95 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,nord-dprxcc.yaml = b/Documentation/devicetree/bindings/clock/qcom,nord-dprxcc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..e3553e0eecd5027155b4dca5c05= 96e3140641aa9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,nord-dprxcc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,nord-dprxcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm DPRX Clock & Reset Controller on Nord + +maintainers: + - Taniya Das + +description: | + Qualcomm dprx clock control module provides the clocks, and resets + domains on Nord. + + See also: + include/dt-bindings/clock/qcom,nord-dprxcc.h + +properties: + compatible: + enum: + - qcom,nord-dprxcc0 + - qcom,nord-dprxcc1 + + clocks: + items: + - description: XO clock source + - description: DPRX CFG AHB clock from NWGCC + - description: Sleep clock source + + power-domains: + description: + MMCX power domain. + maxItems: 1 + + required-opps: + description: + MMCX performance point. + maxItems: 1 + +required: + - compatible + - clocks + - power-domains + - required-opps + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + clock-controller@a940000 { + compatible =3D "qcom,nord-dprxcc0"; + reg =3D <0x0a940000 0xc000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&nwgcc NW_GCC_DPRX0_CFG_AHB_CLK>, + <&sleep_clk>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,nord-dprxcc.h b/include/dt-bind= ings/clock/qcom,nord-dprxcc.h new file mode 100644 index 0000000000000000000000000000000000000000..62c26b58ebef04f05ea1dc77664= c03aaad65baa4 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-dprxcc.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DPRX_CC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_DPRX_CC_NORD_H + +/* DPRX_CC clocks */ +#define DPRX_CC_AHB_CLK 0 +#define DPRX_CC_AUD_CLK 1 +#define DPRX_CC_AUDIO_CLK_SRC 2 +#define DPRX_CC_CORE_AHB_DIV_CLK_SRC 3 +#define DPRX_CC_CORE_AUD_DIV_CLK_SRC 4 +#define DPRX_CC_CORE_RCG0_CLK_SRC 5 +#define DPRX_CC_CORE_RCG2_CLK_SRC 6 +#define DPRX_CC_CORE_RCG3_CLK_SRC 7 +#define DPRX_CC_MDP_MEM_CLK 8 +#define DPRX_CC_MMCX_XO_CLK 9 +#define DPRX_CC_PLL0 10 +#define DPRX_CC_PLL1 11 +#define DPRX_CC_VID_MEM_CLK 12 + +/* DPRX_CC resets */ +#define DPRX_CC_DPRX_BLK_BCR 0 + +#endif --=20 2.34.1 From nobody Fri Sep 25 23:54:04 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1397A569F13 for ; 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Wed, 23 Sep 2026 12:22:00 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33e9684d643sm17609309eec.18.2026.09.23.12.21.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 12:22:00 -0700 (PDT) From: Taniya Das Date: Thu, 24 Sep 2026 00:51:33 +0530 Subject: [PATCH v2 3/3] clk: qcom: dprxcc: Add Nord DPRX clock controller support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260924-nords_dprx-v2-3-fa4364e087ef@oss.qualcomm.com> References: <20260924-nords_dprx-v2-0-fa4364e087ef@oss.qualcomm.com> In-Reply-To: <20260924-nords_dprx-v2-0-fa4364e087ef@oss.qualcomm.com> To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Abel Vesa Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das , Abel Vesa X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-ORIG-GUID: 5EuFTgt3HGFYi9--8tjZs7FNa92nwJfr X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIzMDA3NyBTYWx0ZWRfXwGfRm0UG6Am0 YPrkw7C0cN/k5HWfXPcwXN5lxTAKiqjUO940QHRPKwy1yvo1yzJhf+tDypToSdy5anL5fhkl576 0e/WqJIjr4OLdK1j/h9id7sRWvNZtANT0xglR477M6Tdv3Sg9dXWfGMcpgEbepG+i5gknxA/mYY n41h0/j4xAyE911KBcEfmNGK9s/ypWh4DLBpgvFSkvWzoGKRx79EkS6sIs9VDV13N+T8rYPTXgC ROuMtqN/rNQita81HOWzeSg8PEaeMKwkK7W2yPxHDSTNIAKI9hdRjtaz0AD/R1WLU0iTPhqVYG4 ptWjsNrcwjKbtEoy6Pydl2Up88Hqz12agHbSe/THZxWAiIcCGVIV16EEaqLQ9UK9oopwRLSpf3B mucsl17thZeb+R/RVe00nViJUhWcjfItBHO4kP46AC+ucKNGOAsIeU0zNhklrsK//rOlx/yAaOK gY7Ff8kLAc4sWKGyang== X-Proofpoint-GUID: 5EuFTgt3HGFYi9--8tjZs7FNa92nwJfr X-Authority-Analysis: v=2.4 cv=NLpAaE6g c=1 sm=1 tr=0 ts=6ab426da cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=0-BBk2c4bgoaTx3pdGQA:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIzMDA3NyBTYWx0ZWRfX9hKmqyVQzuXM AtcZToeO3DFnYMLEQYgAfQHXaUAeENXMG9oB7+hLERTg8uPv8X7/iUegym30YR1e/79YzYZZ1fI Op9pQDXwo7F3gmoSD8ykKZrWOsn5Qlg= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-23_06,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 adultscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609230077 Add support for the DisplayPort Receiver (DPRX) clock controllers on Nord devices. There are two identical DPRX clock controller instances (DPRX0 and DPRX1), each providing clocks for the DPRX core, audio, AHB and video memory paths, along with core PLLs. Reviewed-by: Abel Vesa Signed-off-by: Taniya Das Reviewed-by: Shawn Guo --- drivers/clk/qcom/Kconfig | 11 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/dprxcc0-nord.c | 434 ++++++++++++++++++++++++++++++++++++= ++++ drivers/clk/qcom/dprxcc1-nord.c | 433 ++++++++++++++++++++++++++++++++++++= +++ 4 files changed, 879 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 3bf39a2c54c85ee7d0c59608ad71b8ec6c899020..0fd6f5642db23599be8f0365e73= faec5451e6411 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -255,6 +255,17 @@ config CLK_NORD_CAMCC Say Y if you want to support camera devices and functionality such as capturing pictures. =20 +config CLK_NORD_DPRXCC + tristate "Nord DPRX Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_NORD_GCC + default m if ARCH_QCOM + help + Support for the Display Port Receiver (DPRX) clock controller on + Nord devices. The DPRX clock controller provides clocks for the + DPRX core, audio, AHB and video memory paths. + Say Y if you want to support DPRX functionality. + config CLK_NORD_GCC tristate "Nord Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index bd70e18a7118126fa20427b3366956075cecb00f..f5294bb67e9a8387c40e629c2ec= 150e4dd4848b2 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_CLK_KUNO_GCC) +=3D gcc-kuno.o obj-$(CONFIG_CLK_MAILI_VIDEOCC) +=3D videocc-maili.o obj-$(CONFIG_CLK_NORD_CAMCC) +=3D camcc-nord.o obj-$(CONFIG_CLK_NORD_DISPCC) +=3D dispcc0-nord.o dispcc1-nord.o +obj-$(CONFIG_CLK_NORD_DPRXCC) +=3D dprxcc0-nord.o dprxcc1-nord.o obj-$(CONFIG_CLK_NORD_GCC) +=3D gcc-nord.o negcc-nord.o nwgcc-nord.o segcc= -nord.o obj-$(CONFIG_CLK_NORD_GPUCC) +=3D gpucc-nord.o gpu2cc-nord.o obj-$(CONFIG_CLK_NORD_TCSRCC) +=3D tcsrcc-nord.o diff --git a/drivers/clk/qcom/dprxcc0-nord.c b/drivers/clk/qcom/dprxcc0-nor= d.c new file mode 100644 index 0000000000000000000000000000000000000000..d17b9338f33bf4864d8a5968ada= 3806a921fe68e --- /dev/null +++ b/drivers/clk/qcom/dprxcc0-nord.c @@ -0,0 +1,434 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_AHB_CLK, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_DPRX_0_DPRX_CC_PLL0_OUT_EVEN, + P_DPRX_0_DPRX_CC_PLL0_OUT_MAIN, + P_DPRX_0_DPRX_CC_PLL0_OUT_ODD, + P_DPRX_0_DPRX_CC_PLL1_OUT_EVEN, + P_DPRX_0_DPRX_CC_PLL1_OUT_MAIN, + P_SLEEP_CLK, +}; + +static const struct pll_vco lucid_ole_vco[] =3D { + { 249600000, 2300000000, 0 }, +}; + +static const struct pll_vco zonda_ole_vco[] =3D { + { 700000000, 3600000000, 0 }, +}; + +/* 550.0 MHz Configuration */ +static const struct alpha_pll_config dprx_0_dprx_cc_pll0_config =3D { + .l =3D 0x1c, + .alpha =3D 0xa555, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00400005, +}; + +static struct clk_alpha_pll dprx_0_dprx_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &dprx_0_dprx_cc_pll0_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +/* 1080.0 MHz Configuration */ +static const struct alpha_pll_config dprx_0_dprx_cc_pll1_config =3D { + .l =3D 0x38, + .alpha =3D 0x4000000, + .config_ctl_val =3D 0x08240800, + .config_ctl_hi_val =3D 0x05008001, + .config_ctl_hi1_val =3D 0x00000000, + .config_ctl_hi2_val =3D 0x00000000, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x02000080, +}; + +static struct clk_alpha_pll dprx_0_dprx_cc_pll1 =3D { + .offset =3D 0x1000, + .alpha_width =3D 28, + .config =3D &dprx_0_dprx_cc_pll1_config, + .vco_table =3D zonda_ole_vco, + .num_vco =3D ARRAY_SIZE(zonda_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_zonda_ole_ops, + }, + }, +}; + +static const struct parent_map dprx_cc_0_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_DPRX_0_DPRX_CC_PLL0_OUT_EVEN, 1 }, + { P_DPRX_0_DPRX_CC_PLL0_OUT_ODD, 2 }, + { P_DPRX_0_DPRX_CC_PLL0_OUT_MAIN, 4 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data dprx_cc_0_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &dprx_0_dprx_cc_pll0.clkr.hw }, + { .hw =3D &dprx_0_dprx_cc_pll0.clkr.hw }, + { .hw =3D &dprx_0_dprx_cc_pll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map dprx_cc_0_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_DPRX_0_DPRX_CC_PLL1_OUT_EVEN, 3 }, + { P_SLEEP_CLK, 5 }, + { P_DPRX_0_DPRX_CC_PLL1_OUT_MAIN, 6 }, +}; + +static const struct clk_parent_data dprx_cc_0_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &dprx_0_dprx_cc_pll1.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, + { .hw =3D &dprx_0_dprx_cc_pll1.clkr.hw }, +}; + +static const struct freq_tbl ftbl_dprx_0_dprx_cc_audio_clk_src[] =3D { + F(216000000, P_DPRX_0_DPRX_CC_PLL1_OUT_MAIN, 5, 0, 0), + F(300000000, P_DPRX_0_DPRX_CC_PLL1_OUT_MAIN, 5, 0, 0), + F(360000000, P_DPRX_0_DPRX_CC_PLL1_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 dprx_0_dprx_cc_audio_clk_src =3D { + .cmd_rcgr =3D 0x80c8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D dprx_cc_0_parent_map_1, + .freq_tbl =3D ftbl_dprx_0_dprx_cc_audio_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_audio_clk_src", + .parent_data =3D dprx_cc_0_parent_data_1, + .num_parents =3D ARRAY_SIZE(dprx_cc_0_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_dprx_0_dprx_cc_core_rcg0_clk_src[] =3D { + F(220000000, P_DPRX_0_DPRX_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + F(440000000, P_DPRX_0_DPRX_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 dprx_0_dprx_cc_core_rcg0_clk_src =3D { + .cmd_rcgr =3D 0x8004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D dprx_cc_0_parent_map_0, + .freq_tbl =3D ftbl_dprx_0_dprx_cc_core_rcg0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_core_rcg0_clk_src", + .parent_data =3D dprx_cc_0_parent_data_0, + .num_parents =3D ARRAY_SIZE(dprx_cc_0_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_dprx_0_dprx_cc_core_rcg2_clk_src[] =3D { + F(275000000, P_DPRX_0_DPRX_CC_PLL0_OUT_MAIN, 2, 0, 0), + F(440000000, P_DPRX_0_DPRX_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + F(550000000, P_DPRX_0_DPRX_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 dprx_0_dprx_cc_core_rcg2_clk_src =3D { + .cmd_rcgr =3D 0x8068, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D dprx_cc_0_parent_map_0, + .freq_tbl =3D ftbl_dprx_0_dprx_cc_core_rcg2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_core_rcg2_clk_src", + .parent_data =3D dprx_cc_0_parent_data_0, + .num_parents =3D ARRAY_SIZE(dprx_cc_0_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_dprx_0_dprx_cc_core_rcg3_clk_src[] =3D { + F(275000000, P_DPRX_0_DPRX_CC_PLL0_OUT_MAIN, 2, 0, 0), + F(550000000, P_DPRX_0_DPRX_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 dprx_0_dprx_cc_core_rcg3_clk_src =3D { + .cmd_rcgr =3D 0x8098, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D dprx_cc_0_parent_map_0, + .freq_tbl =3D ftbl_dprx_0_dprx_cc_core_rcg3_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_core_rcg3_clk_src", + .parent_data =3D dprx_cc_0_parent_data_0, + .num_parents =3D ARRAY_SIZE(dprx_cc_0_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div dprx_0_dprx_cc_core_ahb_div_clk_src =3D { + .reg =3D 0x80b0, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_core_ahb_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_0_dprx_cc_core_rcg3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div dprx_0_dprx_cc_core_aud_div_clk_src =3D { + .reg =3D 0x80d0, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_core_aud_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_0_dprx_cc_audio_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch dprx_0_dprx_cc_ahb_clk =3D { + .halt_reg =3D 0x80b4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80b4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80b4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_0_dprx_cc_core_ahb_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dprx_0_dprx_cc_aud_clk =3D { + .halt_reg =3D 0x80d4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80d4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_aud_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_0_dprx_cc_core_aud_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dprx_0_dprx_cc_mdp_mem_clk =3D { + .halt_reg =3D 0x8088, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8088, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8088, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_mdp_mem_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_0_dprx_cc_core_rcg2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dprx_0_dprx_cc_mmcx_xo_clk =3D { + .halt_reg =3D 0x80d8, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80d8, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80d8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_mmcx_xo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dprx_0_dprx_cc_vid_mem_clk =3D { + .halt_reg =3D 0x8028, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8028, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_vid_mem_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_0_dprx_cc_core_rcg0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *dprx_cc_0_nord_clocks[] =3D { + [DPRX_CC_AHB_CLK] =3D &dprx_0_dprx_cc_ahb_clk.clkr, + [DPRX_CC_AUD_CLK] =3D &dprx_0_dprx_cc_aud_clk.clkr, + [DPRX_CC_AUDIO_CLK_SRC] =3D &dprx_0_dprx_cc_audio_clk_src.clkr, + [DPRX_CC_CORE_AHB_DIV_CLK_SRC] =3D &dprx_0_dprx_cc_core_ahb_div_clk_src.c= lkr, + [DPRX_CC_CORE_AUD_DIV_CLK_SRC] =3D &dprx_0_dprx_cc_core_aud_div_clk_src.c= lkr, + [DPRX_CC_CORE_RCG0_CLK_SRC] =3D &dprx_0_dprx_cc_core_rcg0_clk_src.clkr, + [DPRX_CC_CORE_RCG2_CLK_SRC] =3D &dprx_0_dprx_cc_core_rcg2_clk_src.clkr, + [DPRX_CC_CORE_RCG3_CLK_SRC] =3D &dprx_0_dprx_cc_core_rcg3_clk_src.clkr, + + [DPRX_CC_MDP_MEM_CLK] =3D &dprx_0_dprx_cc_mdp_mem_clk.clkr, + [DPRX_CC_MMCX_XO_CLK] =3D &dprx_0_dprx_cc_mmcx_xo_clk.clkr, + [DPRX_CC_PLL0] =3D &dprx_0_dprx_cc_pll0.clkr, + [DPRX_CC_PLL1] =3D &dprx_0_dprx_cc_pll1.clkr, + [DPRX_CC_VID_MEM_CLK] =3D &dprx_0_dprx_cc_vid_mem_clk.clkr, +}; + +static const struct qcom_reset_map dprx_cc_0_nord_resets[] =3D { + [DPRX_CC_DPRX_BLK_BCR] =3D { 0x8000 }, +}; + +static struct clk_alpha_pll *dprx_cc_0_nord_plls[] =3D { + &dprx_0_dprx_cc_pll0, + &dprx_0_dprx_cc_pll1, +}; + +static const struct regmap_config dprx_cc_0_nord_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x8104, + .fast_io =3D true, +}; + +static void dprx_cc_0_nord_regs_configure(struct device *dev, struct regma= p *regmap) +{ + /* + * Configure cdiv 20 for core aud and 11 for core ahb clks of DPRX CC + */ + regmap_write(regmap, dprx_0_dprx_cc_core_aud_div_clk_src.reg, 0x13); + regmap_write(regmap, dprx_0_dprx_cc_core_ahb_div_clk_src.reg, 0x0A); +} + +static const struct qcom_cc_driver_data dprx_cc_0_nord_driver_data =3D { + .alpha_plls =3D dprx_cc_0_nord_plls, + .num_alpha_plls =3D ARRAY_SIZE(dprx_cc_0_nord_plls), + .clk_regs_configure =3D dprx_cc_0_nord_regs_configure, +}; + +static const struct qcom_cc_desc dprx_cc_0_nord_desc =3D { + .config =3D &dprx_cc_0_nord_regmap_config, + .clks =3D dprx_cc_0_nord_clocks, + .num_clks =3D ARRAY_SIZE(dprx_cc_0_nord_clocks), + .resets =3D dprx_cc_0_nord_resets, + .num_resets =3D ARRAY_SIZE(dprx_cc_0_nord_resets), + .driver_data =3D &dprx_cc_0_nord_driver_data, +}; + +static const struct of_device_id dprx_cc_0_nord_match_table[] =3D { + { .compatible =3D "qcom,nord-dprxcc0" }, + { } +}; +MODULE_DEVICE_TABLE(of, dprx_cc_0_nord_match_table); + +static int dprx_cc_0_nord_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &dprx_cc_0_nord_desc); +} + +static struct platform_driver dprx_cc_0_nord_driver =3D { + .probe =3D dprx_cc_0_nord_probe, + .driver =3D { + .name =3D "dprxcc0-nord", + .of_match_table =3D dprx_cc_0_nord_match_table, + }, +}; + +module_platform_driver(dprx_cc_0_nord_driver); + +MODULE_DESCRIPTION("QTI DPRXCC0 NORD Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/dprxcc1-nord.c b/drivers/clk/qcom/dprxcc1-nor= d.c new file mode 100644 index 0000000000000000000000000000000000000000..851a97c196c0ae3c022858bb18f= 62bf295199d68 --- /dev/null +++ b/drivers/clk/qcom/dprxcc1-nord.c @@ -0,0 +1,433 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_AHB_CLK, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_DPRX_1_DPRX_CC_PLL0_OUT_EVEN, + P_DPRX_1_DPRX_CC_PLL0_OUT_MAIN, + P_DPRX_1_DPRX_CC_PLL0_OUT_ODD, + P_DPRX_1_DPRX_CC_PLL1_OUT_EVEN, + P_DPRX_1_DPRX_CC_PLL1_OUT_MAIN, + P_SLEEP_CLK, +}; + +static const struct pll_vco lucid_ole_vco[] =3D { + { 249600000, 2300000000, 0 }, +}; + +static const struct pll_vco zonda_ole_vco[] =3D { + { 700000000, 3600000000, 0 }, +}; + +/* 550.0 MHz Configuration */ +static const struct alpha_pll_config dprx_1_dprx_cc_pll0_config =3D { + .l =3D 0x1c, + .alpha =3D 0xa555, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00400005, +}; + +static struct clk_alpha_pll dprx_1_dprx_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &dprx_1_dprx_cc_pll0_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +/* 1080.0 MHz Configuration */ +static const struct alpha_pll_config dprx_1_dprx_cc_pll1_config =3D { + .l =3D 0x38, + .alpha =3D 0x4000000, + .config_ctl_val =3D 0x08240800, + .config_ctl_hi_val =3D 0x05008001, + .config_ctl_hi1_val =3D 0x00000000, + .config_ctl_hi2_val =3D 0x00000000, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x02000080, +}; + +static struct clk_alpha_pll dprx_1_dprx_cc_pll1 =3D { + .offset =3D 0x1000, + .alpha_width =3D 28, + .config =3D &dprx_1_dprx_cc_pll1_config, + .vco_table =3D zonda_ole_vco, + .num_vco =3D ARRAY_SIZE(zonda_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_zonda_ole_ops, + }, + }, +}; + +static const struct parent_map dprx_cc_1_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_DPRX_1_DPRX_CC_PLL0_OUT_EVEN, 1 }, + { P_DPRX_1_DPRX_CC_PLL0_OUT_ODD, 2 }, + { P_DPRX_1_DPRX_CC_PLL0_OUT_MAIN, 4 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data dprx_cc_1_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &dprx_1_dprx_cc_pll0.clkr.hw }, + { .hw =3D &dprx_1_dprx_cc_pll0.clkr.hw }, + { .hw =3D &dprx_1_dprx_cc_pll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map dprx_cc_1_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_DPRX_1_DPRX_CC_PLL1_OUT_EVEN, 3 }, + { P_SLEEP_CLK, 5 }, + { P_DPRX_1_DPRX_CC_PLL1_OUT_MAIN, 6 }, +}; + +static const struct clk_parent_data dprx_cc_1_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &dprx_1_dprx_cc_pll1.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, + { .hw =3D &dprx_1_dprx_cc_pll1.clkr.hw }, +}; + +static const struct freq_tbl ftbl_dprx_1_dprx_cc_audio_clk_src[] =3D { + F(216000000, P_DPRX_1_DPRX_CC_PLL1_OUT_MAIN, 5, 0, 0), + F(300000000, P_DPRX_1_DPRX_CC_PLL1_OUT_MAIN, 5, 0, 0), + F(360000000, P_DPRX_1_DPRX_CC_PLL1_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 dprx_1_dprx_cc_audio_clk_src =3D { + .cmd_rcgr =3D 0x80c8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D dprx_cc_1_parent_map_1, + .freq_tbl =3D ftbl_dprx_1_dprx_cc_audio_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_audio_clk_src", + .parent_data =3D dprx_cc_1_parent_data_1, + .num_parents =3D ARRAY_SIZE(dprx_cc_1_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_dprx_1_dprx_cc_core_rcg0_clk_src[] =3D { + F(220000000, P_DPRX_1_DPRX_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + F(440000000, P_DPRX_1_DPRX_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 dprx_1_dprx_cc_core_rcg0_clk_src =3D { + .cmd_rcgr =3D 0x8004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D dprx_cc_1_parent_map_0, + .freq_tbl =3D ftbl_dprx_1_dprx_cc_core_rcg0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_core_rcg0_clk_src", + .parent_data =3D dprx_cc_1_parent_data_0, + .num_parents =3D ARRAY_SIZE(dprx_cc_1_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_dprx_1_dprx_cc_core_rcg2_clk_src[] =3D { + F(275000000, P_DPRX_1_DPRX_CC_PLL0_OUT_MAIN, 2, 0, 0), + F(440000000, P_DPRX_1_DPRX_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + F(550000000, P_DPRX_1_DPRX_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 dprx_1_dprx_cc_core_rcg2_clk_src =3D { + .cmd_rcgr =3D 0x8068, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D dprx_cc_1_parent_map_0, + .freq_tbl =3D ftbl_dprx_1_dprx_cc_core_rcg2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_core_rcg2_clk_src", + .parent_data =3D dprx_cc_1_parent_data_0, + .num_parents =3D ARRAY_SIZE(dprx_cc_1_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_dprx_1_dprx_cc_core_rcg3_clk_src[] =3D { + F(275000000, P_DPRX_1_DPRX_CC_PLL0_OUT_MAIN, 2, 0, 0), + F(550000000, P_DPRX_1_DPRX_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 dprx_1_dprx_cc_core_rcg3_clk_src =3D { + .cmd_rcgr =3D 0x8098, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D dprx_cc_1_parent_map_0, + .freq_tbl =3D ftbl_dprx_1_dprx_cc_core_rcg3_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_core_rcg3_clk_src", + .parent_data =3D dprx_cc_1_parent_data_0, + .num_parents =3D ARRAY_SIZE(dprx_cc_1_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div dprx_1_dprx_cc_core_ahb_div_clk_src =3D { + .reg =3D 0x80b0, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_core_ahb_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_1_dprx_cc_core_rcg3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div dprx_1_dprx_cc_core_aud_div_clk_src =3D { + .reg =3D 0x80d0, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_core_aud_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_1_dprx_cc_audio_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch dprx_1_dprx_cc_ahb_clk =3D { + .halt_reg =3D 0x80b4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80b4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80b4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_1_dprx_cc_core_ahb_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dprx_1_dprx_cc_aud_clk =3D { + .halt_reg =3D 0x80d4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80d4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_aud_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_1_dprx_cc_core_aud_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dprx_1_dprx_cc_mdp_mem_clk =3D { + .halt_reg =3D 0x8088, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8088, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8088, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_mdp_mem_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_1_dprx_cc_core_rcg2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dprx_1_dprx_cc_mmcx_xo_clk =3D { + .halt_reg =3D 0x80d8, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80d8, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80d8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_mmcx_xo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dprx_1_dprx_cc_vid_mem_clk =3D { + .halt_reg =3D 0x8028, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8028, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_vid_mem_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_1_dprx_cc_core_rcg0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *dprx_cc_1_nord_clocks[] =3D { + [DPRX_CC_AHB_CLK] =3D &dprx_1_dprx_cc_ahb_clk.clkr, + [DPRX_CC_AUD_CLK] =3D &dprx_1_dprx_cc_aud_clk.clkr, + [DPRX_CC_AUDIO_CLK_SRC] =3D &dprx_1_dprx_cc_audio_clk_src.clkr, + [DPRX_CC_CORE_AHB_DIV_CLK_SRC] =3D &dprx_1_dprx_cc_core_ahb_div_clk_src.c= lkr, + [DPRX_CC_CORE_AUD_DIV_CLK_SRC] =3D &dprx_1_dprx_cc_core_aud_div_clk_src.c= lkr, + [DPRX_CC_CORE_RCG0_CLK_SRC] =3D &dprx_1_dprx_cc_core_rcg0_clk_src.clkr, + [DPRX_CC_CORE_RCG2_CLK_SRC] =3D &dprx_1_dprx_cc_core_rcg2_clk_src.clkr, + [DPRX_CC_CORE_RCG3_CLK_SRC] =3D &dprx_1_dprx_cc_core_rcg3_clk_src.clkr, + [DPRX_CC_MDP_MEM_CLK] =3D &dprx_1_dprx_cc_mdp_mem_clk.clkr, + [DPRX_CC_MMCX_XO_CLK] =3D &dprx_1_dprx_cc_mmcx_xo_clk.clkr, + [DPRX_CC_PLL0] =3D &dprx_1_dprx_cc_pll0.clkr, + [DPRX_CC_PLL1] =3D &dprx_1_dprx_cc_pll1.clkr, + [DPRX_CC_VID_MEM_CLK] =3D &dprx_1_dprx_cc_vid_mem_clk.clkr, +}; + +static const struct qcom_reset_map dprx_cc_1_nord_resets[] =3D { + [DPRX_CC_DPRX_BLK_BCR] =3D { 0x8000 }, +}; + +static struct clk_alpha_pll *dprx_cc_1_nord_plls[] =3D { + &dprx_1_dprx_cc_pll0, + &dprx_1_dprx_cc_pll1, +}; + +static const struct regmap_config dprx_cc_1_nord_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x8104, + .fast_io =3D true, +}; + +static void dprx_cc_1_nord_regs_configure(struct device *dev, struct regma= p *regmap) +{ + /* + * Configure cdiv 20 for core aud and 11 for core ahb clks of DPRX CC + */ + regmap_write(regmap, dprx_1_dprx_cc_core_aud_div_clk_src.reg, 0x13); + regmap_write(regmap, dprx_1_dprx_cc_core_ahb_div_clk_src.reg, 0x0A); +} + +static const struct qcom_cc_driver_data dprx_cc_1_nord_driver_data =3D { + .alpha_plls =3D dprx_cc_1_nord_plls, + .num_alpha_plls =3D ARRAY_SIZE(dprx_cc_1_nord_plls), + .clk_regs_configure =3D dprx_cc_1_nord_regs_configure, +}; + +static const struct qcom_cc_desc dprx_cc_1_nord_desc =3D { + .config =3D &dprx_cc_1_nord_regmap_config, + .clks =3D dprx_cc_1_nord_clocks, + .num_clks =3D ARRAY_SIZE(dprx_cc_1_nord_clocks), + .resets =3D dprx_cc_1_nord_resets, + .num_resets =3D ARRAY_SIZE(dprx_cc_1_nord_resets), + .driver_data =3D &dprx_cc_1_nord_driver_data, +}; + +static const struct of_device_id dprx_cc_1_nord_match_table[] =3D { + { .compatible =3D "qcom,nord-dprxcc1" }, + { } +}; +MODULE_DEVICE_TABLE(of, dprx_cc_1_nord_match_table); + +static int dprx_cc_1_nord_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &dprx_cc_1_nord_desc); +} + +static struct platform_driver dprx_cc_1_nord_driver =3D { + .probe =3D dprx_cc_1_nord_probe, + .driver =3D { + .name =3D "dprxcc1-nord", + .of_match_table =3D dprx_cc_1_nord_match_table, + }, +}; + +module_platform_driver(dprx_cc_1_nord_driver); + +MODULE_DESCRIPTION("QTI DPRXCC1 NORD Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1