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Thu, 24 Sep 2026 02:40:20 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33e939fdabcsm13482354eec.3.2026.09.24.02.40.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2026 02:40:09 -0700 (PDT) From: Taniya Das Date: Thu, 24 Sep 2026 15:09:56 +0530 Subject: [PATCH] clk: qcom: gcc: Fix GPLL enable register offset for Nord SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260924-nord_gcc_offset_fix-v1-1-230ffad2dae9@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAOvvtGoC/x2MQQqAIBAAvyJ7Tigryb4SIeGuthcNjQiivycdZ 2DmgUKZqcAsHsh0ceEUK3SNALdvMZBkrAyqVbo1apAxZbTBOZu8L3Raz7dE3ZMbJ4UDGqjlkan q/7qs7/sBepfH3WUAAAA= X-Change-ID: 20260924-nord_gcc_offset_fix-d63ec582d4d9 To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Bartosz Golaszewski , Shawn Guo Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI0MDA0MCBTYWx0ZWRfX2by0zGzgid/J mfPw3dtT0cRh5m8Ak6stgYANkUaZWUDM5PwY0dmEQpVktEPoZBfcO/iIsv4pstm3lMqrOKjaeVA NRWwbmMECLcosRtEGhimxXXY2NZN1qg8TQyu3o+G3/v1EcdMa/6dyKg0c9gy5wMpvvVNNBpuarU 47u4kE9UE4cqqG3BWRmgW49p5+xyDIrJgTzWiMXRJhpRwnguoZNE/EndDAZrnzKZ6/9sYDr6m67 xGllgXM1oU1KSiBfWnQfdeFsXi7J7N+hMRWln8tH23leLKfbtiXN3ZNogcCYHv6XslaNvPJBTdr DzNnKMxh5TE18gLYu1rgo7ICZCcVPUf7QkJuurJMWAxB+oAaHsf3M9xw+fS8DA37TjnuB9NvKnt /VUgNLV4UbELr/m4+Tf80qDFG2Pjjuy9V72aDy/CgG1hndk3e1lDJw8eJ9cX9CMGLYUwZinaezo Hgbjqrr4qpL2M8L0n5w== X-Authority-Analysis: v=2.4 cv=TYwDJhQh c=1 sm=1 tr=0 ts=6ab4f006 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=tWc-dzksYj5tB7JG_AwA:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI0MDA0MCBTYWx0ZWRfXwnI9z/A9LgMA p+WcnlX0wLB1CQmbOEdvgFs2ygrNh0cyy7tbhjSVTW4hz5/+mcDVH97KXmvnK8xaWL0F6Y6tp9C Eo5eADyWtxGxnf4atSARaLpiIiv+w2g= X-Proofpoint-GUID: wX2JyUrXO5Ps3fpcnUanh6cB3M_HPrOO X-Proofpoint-ORIG-GUID: wX2JyUrXO5Ps3fpcnUanh6cB3M_HPrOO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-24_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 phishscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 adultscore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609240040 The GPLLs in the North-East, North-West and South-East global clock controllers on the Qualcomm Nord SoC were registered with a placeholder enable register offset of 0x0. As a result the shared PLL voting register was never programmed, leaving the PLLs' enable state uncontrolled. Point each GPLL at its actual GPLL_ENABLE register (0x57010 for the North-East and South-East controllers, 0x76008 for the North-West controller). Each PLL continues to select its own vote bit through enable_mask. Fixes: a4f780cd5c7a ("clk: qcom: gcc: Add multiple global clock controller = driver for Nord SoC") Signed-off-by: Taniya Das Reviewed-by: Abel Vesa Reviewed-by: Shawn Guo --- drivers/clk/qcom/negcc-nord.c | 4 ++-- drivers/clk/qcom/nwgcc-nord.c | 2 +- drivers/clk/qcom/segcc-nord.c | 8 ++++---- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/clk/qcom/negcc-nord.c b/drivers/clk/qcom/negcc-nord.c index 0db284edc4e41e960adaca8f10cbcd4197352e2d..ef9ff450bcd44baf71e57eaa4f2= c59a3c714b2cf 100644 --- a/drivers/clk/qcom/negcc-nord.c +++ b/drivers/clk/qcom/negcc-nord.c @@ -46,7 +46,7 @@ static struct clk_alpha_pll ne_gcc_gpll0 =3D { .offset =3D 0x0, .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr =3D { - .enable_reg =3D 0x0, + .enable_reg =3D 0x57010, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "ne_gcc_gpll0", @@ -85,7 +85,7 @@ static struct clk_alpha_pll ne_gcc_gpll2 =3D { .offset =3D 0x2000, .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr =3D { - .enable_reg =3D 0x0, + .enable_reg =3D 0x57010, .enable_mask =3D BIT(2), .hw.init =3D &(const struct clk_init_data) { .name =3D "ne_gcc_gpll2", diff --git a/drivers/clk/qcom/nwgcc-nord.c b/drivers/clk/qcom/nwgcc-nord.c index 280558f15748c95cfb373c09141b3023d7fcec5c..1eb8e53139120db4b872e7b7985= c63e85d6b2013 100644 --- a/drivers/clk/qcom/nwgcc-nord.c +++ b/drivers/clk/qcom/nwgcc-nord.c @@ -36,7 +36,7 @@ static struct clk_alpha_pll nw_gcc_gpll0 =3D { .offset =3D 0x0, .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr =3D { - .enable_reg =3D 0x0, + .enable_reg =3D 0x76008, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "nw_gcc_gpll0", diff --git a/drivers/clk/qcom/segcc-nord.c b/drivers/clk/qcom/segcc-nord.c index 51d7f83e21b6b2f2780088f26f547cc48801c6e4..98b53311d333c4ec4b7fcb69e6e= 2f6815c37319a 100644 --- a/drivers/clk/qcom/segcc-nord.c +++ b/drivers/clk/qcom/segcc-nord.c @@ -39,7 +39,7 @@ static struct clk_alpha_pll se_gcc_gpll0 =3D { .offset =3D 0x0, .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr =3D { - .enable_reg =3D 0x0, + .enable_reg =3D 0x57010, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "se_gcc_gpll0", @@ -78,7 +78,7 @@ static struct clk_alpha_pll se_gcc_gpll2 =3D { .offset =3D 0x2000, .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr =3D { - .enable_reg =3D 0x0, + .enable_reg =3D 0x57010, .enable_mask =3D BIT(2), .hw.init =3D &(const struct clk_init_data) { .name =3D "se_gcc_gpll2", @@ -95,7 +95,7 @@ static struct clk_alpha_pll se_gcc_gpll4 =3D { .offset =3D 0x4000, .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr =3D { - .enable_reg =3D 0x0, + .enable_reg =3D 0x57010, .enable_mask =3D BIT(4), .hw.init =3D &(const struct clk_init_data) { .name =3D "se_gcc_gpll4", @@ -112,7 +112,7 @@ static struct clk_alpha_pll se_gcc_gpll5 =3D { .offset =3D 0x5000, .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr =3D { - .enable_reg =3D 0x0, + .enable_reg =3D 0x57010, .enable_mask =3D BIT(5), .hw.init =3D &(const struct clk_init_data) { .name =3D "se_gcc_gpll5", --- base-commit: 3d7783543c2646af69ad65825e810060494bea21 change-id: 20260924-nord_gcc_offset_fix-d63ec582d4d9 Best regards, --=20 Taniya Das