From nobody Thu Sep 24 12:53:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CE9439CD1B; Thu, 24 Sep 2026 07:24:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790234665; cv=none; b=V3CotQJjJ51W9Lnk37+EnedYYOanabAh6Sx1/3bgymv4UMImCKIjl+dcGqaj1SKDc/RjC3yceZ/QKZEGmEgCRJOdIycJEz9Fn+NTUWAjs2hFfOrbdu8YvkA9ygvj3W9cZNGDL0TPHRH+2XcPT+BW43nfgAHFdwr5cFzgSyiCDF8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790234665; c=relaxed/simple; bh=9V9vHNIqjj/P3V/WD9pUW9DZXjV8gTIAVkCblvj1Xq4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KsayucT/pofLvtXydI1YvWFcxJNFeLq+QyBPikNlQeRATUSy0XlLOP4GovyVQHBWsFRxjyg6DmmpQv8zR9f4m1SQfePbLvKKFbqW5vizrkhCppM2l7Zn4j2ax2j8hApD9qqinLxehc3rKxtOb9AStD6MhjmpiakfGDaE35iFM2g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=iUeeeNxG; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="iUeeeNxG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1790234654; bh=9V9vHNIqjj/P3V/WD9pUW9DZXjV8gTIAVkCblvj1Xq4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=iUeeeNxGlLxhJrNz6Ckmi6E+lHfIUobG+yTsZBzxrQZ9X7ui2pdlMglCZAwsJCeSa ZqamKT9HAvUOOwFyFCosYeeQ+MKRaVpKD2lQsHChA4KstkHHN6HK91BMgzA/+eqaaa RnVXiXOfS9yNv2cj0H069w2XsByFnfTx21qFehHW8Dclew1qeCNsZ1HDGvyQPsnPaK dsF/eSembWhWj3IBQvb5B1SyXgueVcl2bW+4tbnnv9MKuGSEZWzwHuu2J2hvig9LY/ pZcmQccO2196W/2LyboQEyffS1hyGLimnrtZPJw3hoJ+hB4LMxaZ52GW63C9AC3BsK mEG71nyujNusA== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id 01F0E17E01D1; Thu, 24 Sep 2026 09:24:13 +0200 (CEST) From: Louis-Alexis Eyraud Date: Thu, 24 Sep 2026 09:23:24 +0200 Subject: [PATCH net-next v2 1/7] dt-bindings: net: mediatek-dwmac: add support for MT8189 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260924-dwmac-mediatek-mt8189-v2-1-430bd74d5ef9@collabora.com> References: <20260924-dwmac-mediatek-mt8189-v2-0-430bd74d5ef9@collabora.com> In-Reply-To: <20260924-dwmac-mediatek-mt8189-v2-0-430bd74d5ef9@collabora.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Matthias Brugger , AngeloGioacchino Del Regno , Biao Huang , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue Cc: kernel@collabora.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790234653; l=4693; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=9V9vHNIqjj/P3V/WD9pUW9DZXjV8gTIAVkCblvj1Xq4=; b=fGUZW/haDY37KjFlxcP6MBiJCPKTi48kpDtrvwtppr+sq9WcagdmC+gADaBPpSVMtHy8U1rND MR3cKuN5i+SDiXrPB7CuiqLLxyAyf6TYDOQl67cQgtplj9Af+1YvBKe X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add new compatible string and clock definitions for the Ethernet MAC IP found in MT8189 SoC. Also, update "mediatek,rx-delay-ps" and "mediatek,tx-delay-ps" property description to add MT8189 RX/TX delay stage divider values, as they differ from existing supported SoC. Signed-off-by: Louis-Alexis Eyraud --- .../devicetree/bindings/net/mediatek-dwmac.yaml | 87 +++++++++++++++---= ---- 1 file changed, 60 insertions(+), 27 deletions(-) diff --git a/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml b/Do= cumentation/devicetree/bindings/net/mediatek-dwmac.yaml index 3aab21b8e8de..6624dff015f0 100644 --- a/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml @@ -20,13 +20,11 @@ select: enum: - mediatek,mt2712-gmac - mediatek,mt8188-gmac + - mediatek,mt8189-gmac - mediatek,mt8195-gmac required: - compatible =20 -allOf: - - $ref: snps,dwmac.yaml# - properties: compatible: oneOf: @@ -36,6 +34,7 @@ properties: - const: snps,dwmac-4.20a - items: - enum: + - mediatek,mt8189-gmac - mediatek,mt8195-gmac - const: snps,dwmac-5.10a - items: @@ -44,26 +43,6 @@ properties: - const: mediatek,mt8195-gmac - const: snps,dwmac-5.10a =20 - clocks: - minItems: 5 - items: - - description: AXI clock - - description: APB clock - - description: MAC Main clock - - description: PTP clock - - description: RMII reference clock provided by MAC - - description: MAC clock gate - - clock-names: - minItems: 5 - items: - - const: axi - - const: apb - - const: mac_main - - const: ptp_ref - - const: rmii_internal - - const: mac_cg - interrupts: maxItems: 1 =20 @@ -86,8 +65,10 @@ properties: or will round down. Range 0~31*170. For MT2712 RMII/MII interface, Allowed value need to be a multiple o= f 550, or will round down. Range 0~31*550. - For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be= a multiple of 290, - or will round down. Range 0~31*290. + For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be= a + multiple of 290, or will round down. Range 0~31*290. + For MT8189 RGMII/RMII/MII interface, Allowed value need to + be a multiple of 180, or will round down. Range 0~31*180. =20 mediatek,rx-delay-ps: description: @@ -96,8 +77,10 @@ properties: or will round down. Range 0~31*170. For MT2712 RMII/MII interface, Allowed value need to be a multiple o= f 550, or will round down. Range 0~31*550. - For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be= a multiple - of 290, or will round down. Range 0~31*290. + For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be= a + multiple of 290, or will round down. Range 0~31*290. + For MT8189 RGMII/RMII/MII interface, Allowed value need to + be a multiple of 180, or will round down. Range 0~31*180. =20 mediatek,rmii-rxc: type: boolean @@ -147,6 +130,56 @@ required: - phy-mode - mediatek,pericfg =20 +allOf: + - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt2712-gmac + - mediatek,mt8188-gmac + - mediatek,mt8195-gmac + then: + properties: + clocks: + minItems: 5 + items: + - description: AXI clock + - description: APB clock + - description: MAC Main clock + - description: PTP clock + - description: RMII reference clock provided by MAC + - description: MAC clock gate + + clock-names: + minItems: 5 + items: + - const: axi + - const: apb + - const: mac_main + - const: ptp_ref + - const: rmii_internal + - const: mac_cg + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8189-gmac + then: + properties: + clocks: + items: + - description: MAC Main clock + - description: PTP clock + + clock-names: + items: + - const: mac_main + - const: ptp_ref + unevaluatedProperties: false =20 examples: --=20 2.55.0 From nobody Thu Sep 24 12:53:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79F61427FA0; Thu, 24 Sep 2026 07:24:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790234666; cv=none; b=p1CGjbSxQBJOwGoNng7XWbLykCX5x2mu2g9XXS0tlt3Gv4kF9+MkHBEnd9M+25nhnx+++9Ylkh2y2tth0AorztFPqBw0GU4oBnoZBlHru42RUyNxLr6YVxYAfkWtCfrkd7SycPfHaZS1q7JSmr6v1JYiSl0ujhsqDwaOnOo004c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790234666; c=relaxed/simple; bh=2ORlhhYALrGSA1AgsN6rxpeVUyxOrdA8goKrV/84zAA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jvnD6vHkp0s8+SXPE4DXYuDQUKpUIFDvtoDJj4gcFi/JwLo8hUEsVVrOj9O9ijDoX4lxb2De9zQT0tUYZkK3iWSS6e+3hUQl0dkdTFvMicv26jfVx+i6EpIl29VjzIOipO15q/RAcYSkLe2VnxH+WeMIKMwAs8UY5VXwayXJd50= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=GAi8HAJZ; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="GAi8HAJZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1790234655; bh=2ORlhhYALrGSA1AgsN6rxpeVUyxOrdA8goKrV/84zAA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=GAi8HAJZW4dJ/eZxh57pVtXWNrsjtYgpHN5lzKoAGrZoiLFr3aO3L3zAhhpjvh6sp rRgqg4H3i4/aVWRIAo0UrTtGu3wt39XCrjakyrXMzZH9mLhX6ByX48DcH0dYo2Ki8C RG++g7CDJDwD7qUvfS6Ap4YzcYic8XzcEkZnzJoII2x62jpAv4qRskvpLBqQpIMUp3 bZkr7f1P1KpyrtiECyhxFYu1fMeDQwEkD4ZrbS3a6WEmzl6jn35OwaeYiJJm/6RFMM ZI9e+FmZA19rf0K/fHwu1W1iEQSJ/yxkAcc/Ng7GFtKH0NweDKYVUv2nU7tstVbCsv o9W5wTMPrGbQA== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id D908A17E03B6; Thu, 24 Sep 2026 09:24:14 +0200 (CEST) From: Louis-Alexis Eyraud Date: Thu, 24 Sep 2026 09:23:25 +0200 Subject: [PATCH net-next v2 2/7] net: stmmac: mediatek: simplify TX/RX delay handling in mt8195_set_delay Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260924-dwmac-mediatek-mt8189-v2-2-430bd74d5ef9@collabora.com> References: <20260924-dwmac-mediatek-mt8189-v2-0-430bd74d5ef9@collabora.com> In-Reply-To: <20260924-dwmac-mediatek-mt8189-v2-0-430bd74d5ef9@collabora.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Matthias Brugger , AngeloGioacchino Del Regno , Biao Huang , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue Cc: kernel@collabora.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790234653; l=7277; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=2ORlhhYALrGSA1AgsN6rxpeVUyxOrdA8goKrV/84zAA=; b=BQNaGTp3qQDCSYKNHiXxwqfm/ctdsOLb2DUL/e4ZibGkq/NNtl6QP6f28JGgZtmSQZgzVu0WO 1/JPK7yHK34B+ZEb6euCs5aQaoTVHoZl7zDuwtgq7ZhtN+3OOepogV7 X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= The mt8195_set_delay function modifies at its beginning the TX and RX internal delay variables, located in the driver data, by dividing them by a constant (290) and restores their original values by multiplying them again at the function end. It is done in order to convert them into a step value, used by the hardware registers for setting these delays. But this is rather pointless to modify the driver data for that, while it could be done locally in the function. The original delay values cannot be used anymore (if needed) during mt8195_set_delay processing. Finally, they are altered after the function call if they are not a multiple of 290. So, simplify these delay variable handling by using local variables to convert them into the register value and use those in the write calls. Also, remove the two private conversion functions, that are not useful anymore and add definitions for MT8195 RX/TX delay maximum and divider values. Signed-off-by: Louis-Alexis Eyraud --- .../net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 77 ++++++++++--------= ---- 1 file changed, 36 insertions(+), 41 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers= /net/ethernet/stmicro/stmmac/dwmac-mediatek.c index 30ae0dba7fff..f7eb85110df0 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -63,6 +63,11 @@ #define MT8195_DLY_RMII_TXC_ENABLE BIT(5) #define MT8195_DLY_RMII_TXC_STAGES GENMASK(4, 0) =20 +#define MT8195_DLY_RXC_STAGE_DIV 290 /* 290ps per stage */ +#define MT8195_DLY_RXC_MAX 9280 /* 32 x 290ps */ +#define MT8195_DLY_TXC_STAGE_DIV 290 /* 290ps per stage */ +#define MT8195_DLY_TXC_MAX 9280 /* 32 x 290ps */ + struct mac_delay_struct { u32 tx_delay; u32 rx_delay; @@ -293,39 +298,27 @@ static int mt8195_set_interface(struct mediatek_dwmac= _plat_data *plat, return 0; } =20 -static void mt8195_delay_ps2stage(struct mediatek_dwmac_plat_data *plat) -{ - struct mac_delay_struct *mac_delay =3D &plat->mac_delay; - - /* 290ps per stage */ - mac_delay->tx_delay /=3D 290; - mac_delay->rx_delay /=3D 290; -} - -static void mt8195_delay_stage2ps(struct mediatek_dwmac_plat_data *plat) -{ - struct mac_delay_struct *mac_delay =3D &plat->mac_delay; - - /* 290ps per stage */ - mac_delay->tx_delay *=3D 290; - mac_delay->rx_delay *=3D 290; -} - static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat) { struct mac_delay_struct *mac_delay =3D &plat->mac_delay; - u32 gtxc_delay_val =3D 0, delay_val =3D 0, rmii_delay_val =3D 0; - - mt8195_delay_ps2stage(plat); + u32 rx_delay_stage_val =3D mac_delay->rx_delay / MT8195_DLY_RXC_STAGE_DIV; + u32 tx_delay_stage_val =3D mac_delay->tx_delay / MT8195_DLY_TXC_STAGE_DIV; + u32 gtxc_delay_val =3D 0; + u32 rmii_delay_val =3D 0; + u32 delay_val =3D 0; =20 switch (plat->phy_mode) { case PHY_INTERFACE_MODE_MII: - delay_val |=3D FIELD_PREP(MT8195_DLY_TXC_ENABLE, !!mac_delay->tx_delay); - delay_val |=3D FIELD_PREP(MT8195_DLY_TXC_STAGES, mac_delay->tx_delay); + delay_val |=3D FIELD_PREP(MT8195_DLY_TXC_ENABLE, + !!tx_delay_stage_val); + delay_val |=3D FIELD_PREP(MT8195_DLY_TXC_STAGES, + tx_delay_stage_val); delay_val |=3D FIELD_PREP(MT8195_DLY_TXC_INV, mac_delay->tx_inv); =20 - delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_ENABLE, !!mac_delay->rx_delay); - delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_STAGES, mac_delay->rx_delay); + delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_ENABLE, + !!rx_delay_stage_val); + delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_STAGES, + rx_delay_stage_val); delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay->rx_inv); break; case PHY_INTERFACE_MODE_RMII: @@ -336,16 +329,16 @@ static int mt8195_set_delay(struct mediatek_dwmac_pla= t_data *plat) * The ingress timing can be adjusted by RMII_RXC delay macro circuit. */ rmii_delay_val |=3D FIELD_PREP(MT8195_DLY_RMII_TXC_ENABLE, - !!mac_delay->tx_delay); + !!tx_delay_stage_val); rmii_delay_val |=3D FIELD_PREP(MT8195_DLY_RMII_TXC_STAGES, - mac_delay->tx_delay); + tx_delay_stage_val); rmii_delay_val |=3D FIELD_PREP(MT8195_DLY_RMII_TXC_INV, mac_delay->tx_inv); =20 rmii_delay_val |=3D FIELD_PREP(MT8195_DLY_RMII_RXC_ENABLE, - !!mac_delay->rx_delay); + !!rx_delay_stage_val); rmii_delay_val |=3D FIELD_PREP(MT8195_DLY_RMII_RXC_STAGES, - mac_delay->rx_delay); + rx_delay_stage_val); rmii_delay_val |=3D FIELD_PREP(MT8195_DLY_RMII_RXC_INV, mac_delay->rx_inv); } else { @@ -361,9 +354,9 @@ static int mt8195_set_delay(struct mediatek_dwmac_plat_= data *plat) * by RXC delay macro circuit. */ delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_ENABLE, - !!mac_delay->rx_delay); + !!rx_delay_stage_val); delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_STAGES, - mac_delay->rx_delay); + rx_delay_stage_val); delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay->rx_inv); } else { @@ -372,9 +365,9 @@ static int mt8195_set_delay(struct mediatek_dwmac_plat_= data *plat) * by TXC delay macro circuit. */ delay_val |=3D FIELD_PREP(MT8195_DLY_TXC_ENABLE, - !!mac_delay->rx_delay); + !!rx_delay_stage_val); delay_val |=3D FIELD_PREP(MT8195_DLY_TXC_STAGES, - mac_delay->rx_delay); + rx_delay_stage_val); delay_val |=3D FIELD_PREP(MT8195_DLY_TXC_INV, mac_delay->rx_inv); } @@ -384,12 +377,16 @@ static int mt8195_set_delay(struct mediatek_dwmac_pla= t_data *plat) case PHY_INTERFACE_MODE_RGMII_TXID: case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_ID: - gtxc_delay_val |=3D FIELD_PREP(MT8195_DLY_GTXC_ENABLE, !!mac_delay->tx_d= elay); - gtxc_delay_val |=3D FIELD_PREP(MT8195_DLY_GTXC_STAGES, mac_delay->tx_del= ay); + gtxc_delay_val |=3D FIELD_PREP(MT8195_DLY_GTXC_ENABLE, + !!tx_delay_stage_val); + gtxc_delay_val |=3D FIELD_PREP(MT8195_DLY_GTXC_STAGES, + tx_delay_stage_val); gtxc_delay_val |=3D FIELD_PREP(MT8195_DLY_GTXC_INV, mac_delay->tx_inv); =20 - delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_ENABLE, !!mac_delay->rx_delay); - delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_STAGES, mac_delay->rx_delay); + delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_ENABLE, + !!rx_delay_stage_val); + delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_STAGES, + rx_delay_stage_val); delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay->rx_inv); =20 break; @@ -408,8 +405,6 @@ static int mt8195_set_delay(struct mediatek_dwmac_plat_= data *plat) regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL1, delay_val); regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL2, rmii_delay_val); =20 - mt8195_delay_stage2ps(plat); - return 0; } =20 @@ -418,8 +413,8 @@ static const struct mediatek_dwmac_variant mt8195_gmac_= variant =3D { .dwmac_set_delay =3D mt8195_set_delay, .clk_list =3D mt8195_dwmac_clk_l, .num_clks =3D ARRAY_SIZE(mt8195_dwmac_clk_l), - .rx_delay_max =3D 9280, - .tx_delay_max =3D 9280, + .rx_delay_max =3D MT8195_DLY_RXC_MAX, + .tx_delay_max =3D MT8195_DLY_TXC_MAX, .dma_bit_mask =3D 35, }; =20 --=20 2.55.0 From nobody Thu Sep 24 12:53:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 814D1428495; Thu, 24 Sep 2026 07:24:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 24 Sep 2026 09:24:15 +0200 (CEST) From: Louis-Alexis Eyraud Date: Thu, 24 Sep 2026 09:23:26 +0200 Subject: [PATCH net-next v2 3/7] net: stmmac: mediatek: add RX/TX delay stage divider in platform data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260924-dwmac-mediatek-mt8189-v2-3-430bd74d5ef9@collabora.com> References: <20260924-dwmac-mediatek-mt8189-v2-0-430bd74d5ef9@collabora.com> In-Reply-To: <20260924-dwmac-mediatek-mt8189-v2-0-430bd74d5ef9@collabora.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Matthias Brugger , AngeloGioacchino Del Regno , Biao Huang , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue Cc: kernel@collabora.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790234653; l=2318; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=N/TxoDWtrODdxPgFFO47Jk5UcUQTz+ySRsrSGsPKRlI=; b=Uvn2opnW8bviX5JUagsn1W0mPrjlD74fIq07puFeIxjKwReWoTQEAA40ESXR4RpPa79eRNf96 YZhmbj6lcH4ATPcVdYDF6JjO2+olezj4P5nsxH5cRYiIizvl8WFynHH X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= In preparation of newer SoC support, that have like MT8189 SoC different RX and TX internal delay stage steps than MT8188/MT8195, add the RX and TX delay stage divider values in the variant platform data and replace the hardcoded value use in mt8195_set_delay. Signed-off-by: Louis-Alexis Eyraud --- drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 20 ++++++++++++++++= ++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers= /net/ethernet/stmicro/stmmac/dwmac-mediatek.c index f7eb85110df0..1c532cc3a975 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -100,6 +100,8 @@ struct mediatek_dwmac_variant { =20 u32 rx_delay_max; u32 tx_delay_max; + u16 rx_delay_stage_div; + u16 tx_delay_stage_div; u8 dma_bit_mask; }; =20 @@ -300,13 +302,25 @@ static int mt8195_set_interface(struct mediatek_dwmac= _plat_data *plat, =20 static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat) { + u16 rx_delay_stage_div =3D plat->variant->rx_delay_stage_div; + u16 tx_delay_stage_div =3D plat->variant->tx_delay_stage_div; struct mac_delay_struct *mac_delay =3D &plat->mac_delay; - u32 rx_delay_stage_val =3D mac_delay->rx_delay / MT8195_DLY_RXC_STAGE_DIV; - u32 tx_delay_stage_val =3D mac_delay->tx_delay / MT8195_DLY_TXC_STAGE_DIV; + u32 rx_delay_stage_val; + u32 tx_delay_stage_val; u32 gtxc_delay_val =3D 0; u32 rmii_delay_val =3D 0; u32 delay_val =3D 0; =20 + if (rx_delay_stage_div) + rx_delay_stage_val =3D mac_delay->rx_delay / rx_delay_stage_div; + else + rx_delay_stage_val =3D 0; + + if (tx_delay_stage_div) + tx_delay_stage_val =3D mac_delay->tx_delay / tx_delay_stage_div; + else + tx_delay_stage_val =3D 0; + switch (plat->phy_mode) { case PHY_INTERFACE_MODE_MII: delay_val |=3D FIELD_PREP(MT8195_DLY_TXC_ENABLE, @@ -415,6 +429,8 @@ static const struct mediatek_dwmac_variant mt8195_gmac_= variant =3D { .num_clks =3D ARRAY_SIZE(mt8195_dwmac_clk_l), .rx_delay_max =3D MT8195_DLY_RXC_MAX, .tx_delay_max =3D MT8195_DLY_TXC_MAX, + .rx_delay_stage_div =3D MT8195_DLY_RXC_STAGE_DIV, + .tx_delay_stage_div =3D MT8195_DLY_TXC_STAGE_DIV, .dma_bit_mask =3D 35, }; =20 --=20 2.55.0 From nobody Thu Sep 24 12:53:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79374425892; 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Thu, 24 Sep 2026 09:24:16 +0200 (CEST) From: Louis-Alexis Eyraud Date: Thu, 24 Sep 2026 09:23:27 +0200 Subject: [PATCH net-next v2 4/7] net: stmmac: mediatek: add PERI_ETH_CTRLx register offset in platform data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260924-dwmac-mediatek-mt8189-v2-4-430bd74d5ef9@collabora.com> References: <20260924-dwmac-mediatek-mt8189-v2-0-430bd74d5ef9@collabora.com> In-Reply-To: <20260924-dwmac-mediatek-mt8189-v2-0-430bd74d5ef9@collabora.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Matthias Brugger , AngeloGioacchino Del Regno , Biao Huang , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue Cc: kernel@collabora.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790234653; l=4264; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=DC2WPwwkSxFustL2AbY2SiFK+Z5ORnQdoEps56Vo9Cc=; b=uPDzdeapfq0daB0ImCHaKn26bU/bjTDUreJt1AlvlI/8INj/0jNdftzQ2JQK8LRqUc8RQhPJR AZSx2jkQyRXBbmilPgvazpF42swCx3pC8vN9CLq+jPH8jZ8f5DW8dBH X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= In preparation of newer SoC support, that use like MT8195 the Ethernet control registers from the peripheral configuration syscon but at a different base offset, add a new base offset in the variant platform data to access the PERI_ETH_CTRLx registers and use it in implemented methods. Reviewed-by: Maxime Chevallier Signed-off-by: Louis-Alexis Eyraud --- .../net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 26 ++++++++++++++++--= ---- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers= /net/ethernet/stmicro/stmmac/dwmac-mediatek.c index 1c532cc3a975..dee12cfa437d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -37,7 +37,9 @@ #define ETH_FINE_DLY_RXC BIT(0) =20 /* Peri Configuration register for mt8195 */ -#define MT8195_PERI_ETH_CTRL0 0xFD0 +#define MT8195_PERI_ETH_CTRL_OFFSET 0xFD0 + +#define MT8195_PERI_ETH_CTRL0 0x0 #define MT8195_RMII_CLK_SRC_INTERNAL BIT(28) #define MT8195_RMII_CLK_SRC_RXC BIT(27) #define MT8195_ETH_INTF_SEL GENMASK(26, 24) @@ -47,7 +49,7 @@ #define MT8195_DLY_GTXC_ENABLE BIT(5) #define MT8195_DLY_GTXC_STAGES GENMASK(4, 0) =20 -#define MT8195_PERI_ETH_CTRL1 0xFD4 +#define MT8195_PERI_ETH_CTRL1 0x4 #define MT8195_DLY_RXC_INV BIT(25) #define MT8195_DLY_RXC_ENABLE BIT(18) #define MT8195_DLY_RXC_STAGES GENMASK(17, 13) @@ -55,7 +57,7 @@ #define MT8195_DLY_TXC_ENABLE BIT(5) #define MT8195_DLY_TXC_STAGES GENMASK(4, 0) =20 -#define MT8195_PERI_ETH_CTRL2 0xFD8 +#define MT8195_PERI_ETH_CTRL2 0x8 #define MT8195_DLY_RMII_RXC_INV BIT(25) #define MT8195_DLY_RMII_RXC_ENABLE BIT(18) #define MT8195_DLY_RMII_RXC_STAGES GENMASK(17, 13) @@ -98,6 +100,7 @@ struct mediatek_dwmac_variant { const char * const *clk_list; int num_clks; =20 + u32 peri_eth_ctrl_offset; u32 rx_delay_max; u32 tx_delay_max; u16 rx_delay_stage_div; @@ -284,6 +287,7 @@ static int mt8195_set_interface(struct mediatek_dwmac_p= lat_data *plat, u8 phy_intf_sel) { u32 intf_val =3D FIELD_PREP(MT8195_ETH_INTF_SEL, phy_intf_sel); + u32 reg_offset =3D plat->variant->peri_eth_ctrl_offset; =20 if (phy_intf_sel =3D=3D PHY_INTF_SEL_RMII) { if (plat->rmii_clk_from_mac) @@ -295,7 +299,9 @@ static int mt8195_set_interface(struct mediatek_dwmac_p= lat_data *plat, /* MT8195 only support external PHY */ intf_val |=3D MT8195_EXT_PHY_MODE; =20 - regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL0, intf_val); + regmap_write(plat->peri_regmap, + reg_offset + MT8195_PERI_ETH_CTRL0, + intf_val); =20 return 0; } @@ -305,6 +311,7 @@ static int mt8195_set_delay(struct mediatek_dwmac_plat_= data *plat) u16 rx_delay_stage_div =3D plat->variant->rx_delay_stage_div; u16 tx_delay_stage_div =3D plat->variant->tx_delay_stage_div; struct mac_delay_struct *mac_delay =3D &plat->mac_delay; + u32 reg_offset =3D plat->variant->peri_eth_ctrl_offset; u32 rx_delay_stage_val; u32 tx_delay_stage_val; u32 gtxc_delay_val =3D 0; @@ -410,14 +417,18 @@ static int mt8195_set_delay(struct mediatek_dwmac_pla= t_data *plat) } =20 regmap_update_bits(plat->peri_regmap, - MT8195_PERI_ETH_CTRL0, + reg_offset + MT8195_PERI_ETH_CTRL0, MT8195_RGMII_TXC_PHASE_CTRL | MT8195_DLY_GTXC_INV | MT8195_DLY_GTXC_ENABLE | MT8195_DLY_GTXC_STAGES, gtxc_delay_val); - regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL1, delay_val); - regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL2, rmii_delay_val); + regmap_write(plat->peri_regmap, + reg_offset + MT8195_PERI_ETH_CTRL1, + delay_val); + regmap_write(plat->peri_regmap, + reg_offset + MT8195_PERI_ETH_CTRL2, + rmii_delay_val); =20 return 0; } @@ -432,6 +443,7 @@ static const struct mediatek_dwmac_variant mt8195_gmac_= variant =3D { .rx_delay_stage_div =3D MT8195_DLY_RXC_STAGE_DIV, .tx_delay_stage_div =3D MT8195_DLY_TXC_STAGE_DIV, .dma_bit_mask =3D 35, + .peri_eth_ctrl_offset =3D MT8195_PERI_ETH_CTRL_OFFSET, }; =20 static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat) --=20 2.55.0 From nobody Thu Sep 24 12:53:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3316E4349AF; Thu, 24 Sep 2026 07:24:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790234669; cv=none; b=Ku6JptqGl1XGt84xU1Dlso1I+8mhw/iUmorSr8gxnbv0W8y3znh1Ms0mbC4hVt0uadXJdYNX+6IjsnolEMP6+oRJv2r7Eg+sioBV0DISu4xOGEzMB8LO0jtKZ7HQ18A4imeMM0TepweapdXu4geJG+4FX+uSDkzXNj5d6DAU6vY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790234669; c=relaxed/simple; bh=/qugFssfEeT+3qD+5/NT5i6m9cPExsSU0aakzvtTvuo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Thu, 24 Sep 2026 09:24:17 +0200 (CEST) From: Louis-Alexis Eyraud Date: Thu, 24 Sep 2026 09:23:28 +0200 Subject: [PATCH net-next v2 5/7] net: stmmac: mediatek: use TX clock phase shift in RGMII mode with 1Gbps speed Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260924-dwmac-mediatek-mt8189-v2-5-430bd74d5ef9@collabora.com> References: <20260924-dwmac-mediatek-mt8189-v2-0-430bd74d5ef9@collabora.com> In-Reply-To: <20260924-dwmac-mediatek-mt8189-v2-0-430bd74d5ef9@collabora.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Matthias Brugger , AngeloGioacchino Del Regno , Biao Huang , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue Cc: kernel@collabora.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790234653; l=5129; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=/qugFssfEeT+3qD+5/NT5i6m9cPExsSU0aakzvtTvuo=; b=5dgREcK+FGftRfBysOjtCruh4RbIuUCC2+equHJFKZt5kbB7dyd9U85+jfIgt6sRXMwXEtL9J 87OjTY/0HcFB75S5ehg8P3vaUxitw3ugsgnJLTJBXjGkOJBjnxpOyUH X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Currently, if the devicetree of a board based on MT8195 (or compatible) configures the use of RGMII PHY mode and insert at MAC level additional delay on TX clock at MAC (with "mediatek,tx-delay-ps" vendor property presence), the driver inserts this delay by setting TX coarse delay bits (bit 0 to 5) of the Ethernet control 0 register from the peripheral configuration (pericfg) at probe time. The HW delay macro circuit, that these bits enable, can be affected by external factors such as environment temperature or vcore voltage and thus applied delay value can change. For 10/100M link speed cases the variations are not problematic, but it can be for 1G link speed cases, that require much precise and stable timings (around 2ns). The Ethernet control 0 register of MT8195 SoC has another bit (bit 22: MT8195_RGMII_TXC_PHASE_CTR) to enable the TX clock phase shift and insert a 2ns clock delay in a more consistence way, as it is not affected like the HW delay macro circuit under the same conditions. This only works though for 1G speed cases so it cannot be set unconditionally at probe time, thus needs to be set after link speed negotiation. In order to allow the TX clock phase shift use in the driver, add in the variant platform data and probe sequence the support of fix_mac_speed callback, provided by dwmac core. This callback allows driver configuration update when the link speed has been negotiated. Implement it for MT8195 so that, when a delay needs to be inserted for TX clock (due to the devicetree configuration), it enables the TX clock phase shift in Ethernet control 0 register only and only if the PHY mode allows it and negotiated link speed is 1G, and fallback to the HW delay macro circuit otherwise. Signed-off-by: Louis-Alexis Eyraud --- .../net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 59 ++++++++++++++++++= ++++ 1 file changed, 59 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers= /net/ethernet/stmicro/stmmac/dwmac-mediatek.c index dee12cfa437d..6123efbbaf02 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -96,6 +96,9 @@ struct mediatek_dwmac_variant { u8 phy_intf_sel); int (*dwmac_set_delay)(struct mediatek_dwmac_plat_data *plat); =20 + void (*dwmac_fix_mac_speed)(void *priv, phy_interface_t interface, + int speed, unsigned int mode); + /* clock ids to be requested */ const char * const *clk_list; int num_clks; @@ -433,9 +436,62 @@ static int mt8195_set_delay(struct mediatek_dwmac_plat= _data *plat) return 0; } =20 +static void mt8195_fix_mac_speed(void *priv, phy_interface_t interface, + int speed, unsigned int mode) +{ + struct mediatek_dwmac_plat_data *priv_plat =3D priv; + const struct mediatek_dwmac_variant *variant; + struct mac_delay_struct *mac_delay; + u32 tx_delay_stage_val, reg_offset; + u32 reg_val =3D 0; + + if (!priv_plat) + return; + + mac_delay =3D &priv_plat->mac_delay; + variant =3D priv_plat->variant; + + if (!mac_delay->tx_delay || + (interface !=3D PHY_INTERFACE_MODE_RGMII && + interface !=3D PHY_INTERFACE_MODE_RGMII_RXID)) + return; + + /* + * When link speed is 1Gbps with RGMII interface, and a TX internal + * delay needs to be applied on MAC, prefer to override the delay + * settings with a 2ns fixed delay which is controlled by + * RGMII_TXC_PHASE_CTRL. Otherwise, fallback to HW delay macro circuit + * for 10/100Mbps link speeds. + */ + if (speed =3D=3D SPEED_1000) { + reg_val =3D MT8195_RGMII_TXC_PHASE_CTRL; + } else { + if (variant->tx_delay_stage_div) + tx_delay_stage_val =3D mac_delay->tx_delay / + variant->tx_delay_stage_div; + + reg_val |=3D FIELD_PREP(MT8195_DLY_GTXC_ENABLE, + !!mac_delay->tx_delay); + reg_val |=3D FIELD_PREP(MT8195_DLY_GTXC_STAGES, + tx_delay_stage_val); + reg_val |=3D FIELD_PREP(MT8195_DLY_GTXC_INV, + mac_delay->tx_inv); + } + + reg_offset =3D variant->peri_eth_ctrl_offset + MT8195_PERI_ETH_CTRL0; + regmap_update_bits(priv_plat->peri_regmap, + reg_offset, + MT8195_RGMII_TXC_PHASE_CTRL | + MT8195_DLY_GTXC_ENABLE | + MT8195_DLY_GTXC_INV | + MT8195_DLY_GTXC_STAGES, + reg_val); +} + static const struct mediatek_dwmac_variant mt8195_gmac_variant =3D { .dwmac_set_phy_interface =3D mt8195_set_interface, .dwmac_set_delay =3D mt8195_set_delay, + .dwmac_fix_mac_speed =3D mt8195_fix_mac_speed, .clk_list =3D mt8195_dwmac_clk_l, .num_clks =3D ARRAY_SIZE(mt8195_dwmac_clk_l), .rx_delay_max =3D MT8195_DLY_RXC_MAX, @@ -594,6 +650,9 @@ static int mediatek_dwmac_common_data(struct platform_d= evice *pdev, plat->resume =3D mediatek_dwmac_init; plat->clks_config =3D mediatek_dwmac_clks_config; =20 + if (priv_plat->variant->dwmac_fix_mac_speed) + plat->fix_mac_speed =3D priv_plat->variant->dwmac_fix_mac_speed; + plat->safety_feat_cfg =3D devm_kzalloc(&pdev->dev, sizeof(*plat->safety_feat_cfg), GFP_KERNEL); --=20 2.55.0 From nobody Thu Sep 24 12:53:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCB68432E76; Thu, 24 Sep 2026 07:24:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790234669; cv=none; b=QhUtSC1WXATvwv1ux/XHJPU4wZbky72ZvVQGx05OmIEu0+UNoO7HfMsH4kufcAqxmF5coRCCf4iY0z5agvO14JRLsBSJrHUfw7AMXinfXwqG9+xy6msOsdH7fPb0vx+W4x4yBevtHkUoTaeL4aQaPJQUXFzVZd9an0Ulg6d2bVo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790234669; c=relaxed/simple; bh=Y/liZ6Nd49xG0Z70hXow1cO9D1/xUcVpQPjdNHMxRGI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Pun5HK2IV6SeLPn1GhrXKz0T1MxFKTGWYcCfS7ookNPO7EW9YAnxnBSL2nLI0YNoT8nWDd7h57a4NQKdcstSB64XJBaK79MU1usdnThpjgP23lGcqc+3OfiSuWwh6MAWWk+GN5wiRyAT9DwMX/HuDzWRb5PNpZeSI+luSXpogVo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=KZMzaAr3; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="KZMzaAr3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1790234659; bh=Y/liZ6Nd49xG0Z70hXow1cO9D1/xUcVpQPjdNHMxRGI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=KZMzaAr3OM/u9AaOR+Owqsi4v+jNGeH9WhXUqhADMJ0YbS4zNFxM1MI2SP/WQsEg4 cmZwYxMsRyDsQ/KZVzcNG3BqTCnM7bBhH2g8mbg/u9/3TEo0oXKpI9fgQ0vO6CQO0Q 8FIUCbJYIDiUQW/KkHNQkn+QFAkWfWy6OxMmXFH2yX5qUuKzz5SxLwJXCZjG7lV2fn GgMcdyk7v5C4u83Jtqn+b0s5E51sMlzdYjXnFUmvj2DncXVnOayinni6CGEsB/nTW6 hD0LWDApDiv+DrbwqXpRcSdAoz2oTt9uO2bdjAZ9wm3xIz/FVSyK6l+3WD7BI6tRUx B47jm0OcsbBuQ== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id 60E9817E12B9; Thu, 24 Sep 2026 09:24:18 +0200 (CEST) From: Louis-Alexis Eyraud Date: Thu, 24 Sep 2026 09:23:29 +0200 Subject: [PATCH net-next v2 6/7] net: stmmac: mediatek: add support for TX clock output enable feature Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260924-dwmac-mediatek-mt8189-v2-6-430bd74d5ef9@collabora.com> References: <20260924-dwmac-mediatek-mt8189-v2-0-430bd74d5ef9@collabora.com> In-Reply-To: <20260924-dwmac-mediatek-mt8189-v2-0-430bd74d5ef9@collabora.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Matthias Brugger , AngeloGioacchino Del Regno , Biao Huang , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue Cc: kernel@collabora.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790234653; l=1623; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=Y/liZ6Nd49xG0Z70hXow1cO9D1/xUcVpQPjdNHMxRGI=; b=i7c2i/75Fv9QVQvvay9feNu2kMA1up3QEFsBKmL9t3UVWxV10uQRa9y95XntFEaUvvym/H3gK e+8au2p88VuA2betdGitOBTrbc7EJ9TRoSvmCQgbQHPUheRP1JJ6EeF X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= The MT8189 SoC has in the Ethernet control 0 register from the peripheral configuration (pericfg) an additional bit to enable the TX clock signal output. In preparation of MT8189 SoC support, add its definition, use in the mt8195_set_interface callback, and a support flag in the platform data. Signed-off-by: Louis-Alexis Eyraud --- drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers= /net/ethernet/stmicro/stmmac/dwmac-mediatek.c index 6123efbbaf02..36599dc33b14 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -36,6 +36,9 @@ #define ETH_FINE_DLY_GTXC BIT(1) #define ETH_FINE_DLY_RXC BIT(0) =20 +/* Peri Configuration register for mt8189 */ +#define MT8189_CTRL0_TXC_OUT_OP_EN BIT(20) + /* Peri Configuration register for mt8195 */ #define MT8195_PERI_ETH_CTRL_OFFSET 0xFD0 =20 @@ -109,6 +112,7 @@ struct mediatek_dwmac_variant { u16 rx_delay_stage_div; u16 tx_delay_stage_div; u8 dma_bit_mask; + bool mac_txclk_out_en; }; =20 /* list of clocks required for mac */ @@ -302,6 +306,9 @@ static int mt8195_set_interface(struct mediatek_dwmac_p= lat_data *plat, /* MT8195 only support external PHY */ intf_val |=3D MT8195_EXT_PHY_MODE; =20 + if (plat->variant->mac_txclk_out_en) + intf_val |=3D MT8189_CTRL0_TXC_OUT_OP_EN; + regmap_write(plat->peri_regmap, reg_offset + MT8195_PERI_ETH_CTRL0, intf_val); --=20 2.55.0 From nobody Thu Sep 24 12:53:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3304A434999; Thu, 24 Sep 2026 07:24:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790234669; cv=none; b=hq3IUq7ULUDxBVhu3McKiT+52xADFafKpAECDLw0f9GD9db+RLpJKuiG9fw5Wtvps04KFiWFHszynmkTaKfIY/Hj39aASv5LDtixBx80OdGO/t0HHP3majKhSK/jq9MqnlggZEEhl/Qg9Tu0AtouC6H3KPxplexcumJZ/AuyQqk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790234669; c=relaxed/simple; bh=sSezKiaqxq23TTfadrJLUrsY2IKOxpyQqg9BJ2ukj9I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dDRn+hLqjl+47BkXww82CVjYlvzb3vblaiQWBfNRmEfl4w+woDSDq/lrGoG4AsGmtaK7qA6GBNrYnYEfTrCrda7fQl6y+W/N4iOL75fBOIrdbMu/Ji3ozlfYaYGxL/vGLuCAwqLNMjyRrAq4uS2nLgmHrje+lKIoT7RwfXXSSDU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=ZOC4rL3Z; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="ZOC4rL3Z" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1790234659; bh=sSezKiaqxq23TTfadrJLUrsY2IKOxpyQqg9BJ2ukj9I=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ZOC4rL3ZoeWu6ToY0V+sCwumqxwq2HszvCZfNc1v5BA9T4fSNkO0ggRnttjFDKCv9 D/0J4EzNg+jctAEOftWxzGM94OeYU7DQFwhlJqvd/v8jzDyastOsmjXUCextWXCo6B s1dTshsx8E/NcHAiBSIzm/IRW+QSIv9o7HaLmX/2oAsbkeuKz6g0ngHBwhDGS9371G Sw9c6CqgoPXjVvjBaXYbrTZmqeR6bLjb+HCEMqlk8KRc8CIaBHCWYz/G9ZVJpJQSjv cXjGT0+qhAeBvdWiERGduz2qOchcNwVSDKoHE1wLg52uAVzc+i4QAXPB4a8UFyFV3y S1VkdIkOvnC7g== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id 38EB317E13A8; Thu, 24 Sep 2026 09:24:19 +0200 (CEST) From: Louis-Alexis Eyraud Date: Thu, 24 Sep 2026 09:23:30 +0200 Subject: [PATCH net-next v2 7/7] net: stmmac: mediatek: add support for MT8189 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260924-dwmac-mediatek-mt8189-v2-7-430bd74d5ef9@collabora.com> References: <20260924-dwmac-mediatek-mt8189-v2-0-430bd74d5ef9@collabora.com> In-Reply-To: <20260924-dwmac-mediatek-mt8189-v2-0-430bd74d5ef9@collabora.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Matthias Brugger , AngeloGioacchino Del Regno , Biao Huang , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue Cc: kernel@collabora.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790234653; l=3069; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=sSezKiaqxq23TTfadrJLUrsY2IKOxpyQqg9BJ2ukj9I=; b=U11+BrDazUrWJMfChDYD11gT4cWzBGFKBe+D/h/Jnl0oEGPUv5EvB2DOfYHxLRJSilPGQLcf0 xty/mOQfMpTDNdpmZRoPAcnMls6X/sDd4+7gx/zkdMVQbZiOyuPZ3zG X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Like MT8195 SoC, MT8189 SoC uses the Ethernet control registers from the peripheral configuration (pericfg) but at a different offset. It also has different RX and TX internal delay stage dividers (290ps for MT8195, 180ps for MT8189), and by consequence a reduced value range for these delays. It finally needs additional feature such as the TX clock output enable one. Thus, add compatible, clock definitions and specific platform data to support the MT8189 SoC. Signed-off-by: Louis-Alexis Eyraud --- .../net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 28 ++++++++++++++++++= ++++ 1 file changed, 28 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers= /net/ethernet/stmicro/stmmac/dwmac-mediatek.c index 36599dc33b14..f07c331b029f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -37,8 +37,15 @@ #define ETH_FINE_DLY_RXC BIT(0) =20 /* Peri Configuration register for mt8189 */ +#define MT8189_PERI_ETH_CTRL_OFFSET 0x270 + #define MT8189_CTRL0_TXC_OUT_OP_EN BIT(20) =20 +#define MT8189_DLY_RXC_STAGE_DIV 180 /* 180ps per stage */ +#define MT8189_DLY_RXC_MAX 5760 /* 32 * 180ps */ +#define MT8189_DLY_TXC_STAGE_DIV 180 /* 180ps per stage */ +#define MT8189_DLY_TXC_MAX 5760 /* 32 * 180ps */ + /* Peri Configuration register for mt8195 */ #define MT8195_PERI_ETH_CTRL_OFFSET 0xFD0 =20 @@ -124,6 +131,10 @@ static const char * const mt8195_dwmac_clk_l[] =3D { "axi", "apb", "mac_cg", "mac_main", "ptp_ref" }; =20 +static const char * const mt8189_dwmac_clk_l[] =3D { + "mac_main", "ptp_ref" +}; + static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat, u8 phy_intf_sel) { @@ -495,6 +506,21 @@ static void mt8195_fix_mac_speed(void *priv, phy_inter= face_t interface, reg_val); } =20 +static const struct mediatek_dwmac_variant mt8189_gmac_variant =3D { + .dwmac_set_phy_interface =3D mt8195_set_interface, + .dwmac_set_delay =3D mt8195_set_delay, + .dwmac_fix_mac_speed =3D mt8195_fix_mac_speed, + .clk_list =3D mt8189_dwmac_clk_l, + .num_clks =3D ARRAY_SIZE(mt8189_dwmac_clk_l), + .dma_bit_mask =3D 35, + .rx_delay_max =3D MT8189_DLY_RXC_MAX, + .tx_delay_max =3D MT8189_DLY_TXC_MAX, + .rx_delay_stage_div =3D MT8189_DLY_RXC_STAGE_DIV, + .tx_delay_stage_div =3D MT8189_DLY_TXC_STAGE_DIV, + .peri_eth_ctrl_offset =3D MT8189_PERI_ETH_CTRL_OFFSET, + .mac_txclk_out_en =3D true, +}; + static const struct mediatek_dwmac_variant mt8195_gmac_variant =3D { .dwmac_set_phy_interface =3D mt8195_set_interface, .dwmac_set_delay =3D mt8195_set_delay, @@ -751,6 +777,8 @@ static void mediatek_dwmac_remove(struct platform_devic= e *pdev) static const struct of_device_id mediatek_dwmac_match[] =3D { { .compatible =3D "mediatek,mt2712-gmac", .data =3D &mt2712_gmac_variant }, + { .compatible =3D "mediatek,mt8189-gmac", + .data =3D &mt8189_gmac_variant }, { .compatible =3D "mediatek,mt8195-gmac", .data =3D &mt8195_gmac_variant }, { } --=20 2.55.0