From nobody Thu Sep 24 12:55:35 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44F1441F5D1; Thu, 24 Sep 2026 08:39:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790239190; cv=none; b=oD/JywBaV894k78hwiDFh9NgeoCGoZjvuTjclbOksmSgWOeN4yyfkkqLZPEV7Vn2ABzeQx6iMagviH79I7TH5a66wv7+77fGzqlICg69BYvER4HJ2WcvQc45S7H6bY05SPjHSPJ46TSUBm8lsO0JwV4cjzukSfc9nqeScDHRvPg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790239190; c=relaxed/simple; bh=cYUK43iCiJs1BaFfQJGKkrofjMlF4tYb1uCWfFvnQQ0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UrX2c+AV1p8IvEmOrVsemwHaGfYBIR317nRAkdq05ts37tnYhNjS0CE3ASl7KAZd1RGWM1Oa1gxmvIeKxex1VEZNv8Mra07QaTcrWsezIKyLxUZVZPnOrOLeeuNM7+TeIFEI4moRKJKWR1EICXITk7hK7hLEC/tEo1dmf2dX4C4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=E0NkFkTj; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="E0NkFkTj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1790239185; bh=cYUK43iCiJs1BaFfQJGKkrofjMlF4tYb1uCWfFvnQQ0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=E0NkFkTjKqABup8bv4dOW2l0ikzso12hKqPe8u4AbHjEccje5N8kD0maFXCI0fWxy KQy9dduaDLs0yo3A+IU+wg/0axzr6qe76A+nynOw+sL5lLJxvpd+bZK6nyNTKHRIrU EwHMtUH28pFuSCqGghf4azgybLK0cpVqpTMRhBlZUlyDwtOyw/8XsEpwIrROvHPmU/ lce9qoqT1MelxHSqGKRn7TzLzvJy8BQ6c3Xwe4sais7P8Rv6xI5oIfV4kjz2bZBkVH vMzHw1t16F8Kv3D5oG5c6hm5jFYvdBPe4Ku+DPYnxSXMzMgZH6XAcBjLpdG03MIxkc IuQjNAzdfw1tA== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id E308717E089A; Thu, 24 Sep 2026 10:39:44 +0200 (CEST) From: Louis-Alexis Eyraud Date: Thu, 24 Sep 2026 10:38:10 +0200 Subject: [PATCH v3 1/4] dt-bindings: serial: mediatek,uart: Add compatible for MT8189 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260924-add-mediatek-genio-520-720-evk-v3-1-2ec5c80677d4@collabora.com> References: <20260924-add-mediatek-genio-520-720-evk-v3-0-2ec5c80677d4@collabora.com> In-Reply-To: <20260924-add-mediatek-genio-520-720-evk-v3-0-2ec5c80677d4@collabora.com> To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Sean Wang Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Krzysztof Kozlowski , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790239184; l=1092; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=cYUK43iCiJs1BaFfQJGKkrofjMlF4tYb1uCWfFvnQQ0=; b=KiYuTMYZjTfU3jPelSHVM26FXdg1+kQzsEmORvAr1crEPpxvJNmNX9bR1bTGK09xy3XQrr+5J sQ28fMGgW09D4DSkQdcI5gsoE0Pr+Ewzkx3uAYZ9A9nZ/yqsjXl8IAd X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add a compatible string for the MT8189 SoC. The UART IPs in this chip are fully compatible with the one found in MT6577 SoC. Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- Documentation/devicetree/bindings/serial/mediatek,uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml b/= Documentation/devicetree/bindings/serial/mediatek,uart.yaml index 5bd8a8853ae0..3f0f4aea0a4c 100644 --- a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml +++ b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml @@ -47,6 +47,7 @@ properties: - mediatek,mt8183-uart - mediatek,mt8186-uart - mediatek,mt8188-uart + - mediatek,mt8189-uart - mediatek,mt8192-uart - mediatek,mt8195-uart - mediatek,mt8365-uart --=20 2.55.0 From nobody Thu Sep 24 12:55:35 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDFAD42376B; Thu, 24 Sep 2026 08:39:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790239189; cv=none; b=sx0BPkQmFxJYI/eWQiCoQlkLvZzbWVJs3DW4vjJhz7lYFO8qaUaN5gHqUrV+C9NMaBElma9XtnIMKxRVxdE+lO16cCQkffg974gGlY1wcDEUWPPqMxdt/E4ik6VNX2NQQOOVr9K/z/a6hQH0mqPUCuUFiTMdqxbGA+r2vla1Km4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790239189; c=relaxed/simple; bh=RlbXQftjDrzhO20EJi3wz+0Try3sBhIBS8ovCMKw7j8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VaLz6pJMmgnmWfiso8iYusMf32X4hBD12abcsheiK41wTDrS8oXeH9wjsBtNLwHIkIt9q2Vq2nE3vvIRk8d15Qs6TZCgwcpfUQQgfLafS0cj530XZhoY2GZr/gysUpl+Z5DQh+wcYItYgXaZTENskWZYGqZzPHPCOU1bglCcrYs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=DqDrNBNq; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="DqDrNBNq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1790239186; bh=RlbXQftjDrzhO20EJi3wz+0Try3sBhIBS8ovCMKw7j8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=DqDrNBNqqOoOSbolYQM4mPRjpKncTUZpLrwN7rg2N8Zses4Ffci2UPINvfSJyq0hB Q8YaQB+QLfbUNa62CEw6pURcNpsIF8lPYHSlKspC6vvm9W1w0VGivn16lrDymCbL9s /YWROhRHnwfELTHugfPXFYi0iMxOIi+CFSFj2ScaIyLn9R6d5hO/VG+v7vCGUt58Ft J20RnxmhnqzrZGll2klvHdARHa43WZtnfhIAwTNN2kqYelK/rlLhCp3OhN4xZjGMFY vDlMMkbceOGUTZykCLD6W3zmAAoOajFtfD/0GWN0z0tP9JZBGpz88gayY8VlBEMv74 4cy5BruxToqig== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id 92F0B17E0A66; Thu, 24 Sep 2026 10:39:45 +0200 (CEST) From: Louis-Alexis Eyraud Date: Thu, 24 Sep 2026 10:38:11 +0200 Subject: [PATCH v3 2/4] dt-bindings: arm: mediatek: add Mediatek Genio 520/720-EVK boards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260924-add-mediatek-genio-520-720-evk-v3-2-2ec5c80677d4@collabora.com> References: <20260924-add-mediatek-genio-520-720-evk-v3-0-2ec5c80677d4@collabora.com> In-Reply-To: <20260924-add-mediatek-genio-520-720-evk-v3-0-2ec5c80677d4@collabora.com> To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Sean Wang Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Krzysztof Kozlowski , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790239184; l=1623; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=RlbXQftjDrzhO20EJi3wz+0Try3sBhIBS8ovCMKw7j8=; b=Nc52S+/1q1xqeNFDx2eJFz9ixwipZS+krqdFKd/Acfp34dz95IJeVEqpNR64YlL94l9/k5hE7 2oc+wG1Z092DD3wEkVRtV0rU1ETejwLzxtF/Pt8oVAuTqe+RN/ZCVeM X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add compatible strings for the Mediatek Genio 520-EVK (based on MT8371 SoC) and Mediatek Genio 720-EVK (based on MT8391 SoC) boards. MT8391 and MT8371 SoC are less powerful variants of MT8189 SoC, with identical hardware register maps. Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- Documentation/devicetree/bindings/arm/mediatek.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Document= ation/devicetree/bindings/arm/mediatek.yaml index 180e6e4948e7..5a4779d9b06c 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -444,6 +444,11 @@ properties: - mediatek,mt8370-evk - const: mediatek,mt8370 - const: mediatek,mt8188 + - items: + - enum: + - mediatek,mt8371-evk + - const: mediatek,mt8371 + - const: mediatek,mt8189 - items: - enum: - ezurio,mt8390-tungsten-smarc @@ -451,6 +456,11 @@ properties: - mediatek,mt8390-evk - const: mediatek,mt8390 - const: mediatek,mt8188 + - items: + - enum: + - mediatek,mt8391-evk + - const: mediatek,mt8391 + - const: mediatek,mt8189 - items: - enum: - kontron,3-5-sbc-i1200 --=20 2.55.0 From nobody Thu Sep 24 12:55:35 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86FBA3DE44E; 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Thu, 24 Sep 2026 10:39:46 +0200 (CEST) From: Louis-Alexis Eyraud Date: Thu, 24 Sep 2026 10:38:12 +0200 Subject: [PATCH v3 3/4] arm64: dts: mediatek: add Genio 720-EVK board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260924-add-mediatek-genio-520-720-evk-v3-3-2ec5c80677d4@collabora.com> References: <20260924-add-mediatek-genio-520-720-evk-v3-0-2ec5c80677d4@collabora.com> In-Reply-To: <20260924-add-mediatek-genio-520-720-evk-v3-0-2ec5c80677d4@collabora.com> To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Sean Wang Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790239184; l=50418; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=2rIk7GmihKXYTYbfPRjc45AhpLzrlDwJNsILHp97t5o=; b=lXbD+srTLBeg3kwFyvKPhESOKpesGOjT1ewv2PsvzZO0YYL+Abz9EuWMauzOiH8M/4ryW00V3 p0cls7kb44rAsjvRuDqMjaHOOZFjilAOlRchiHRbelel46C3v4TlMGp X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add support for MediaTek MT8189 SoC and its variants, and a devicetree for the basic hardware enablement of the Genio 720-EVK board, based on MT8391 SoC. MT8391 SoC is a variant of MT8189 SoC with a difference for the Arm Cortex-A78 CPU core maximum frequency (2.6 Ghz for MT8391, 3 Ghz for MT8189). MT8391 hardware register maps are identical to MT8189. The Genio 720-EVK board has following features: - MT8391 SoC - MT6365 PMIC - MT6319 Buck IC - MT6375 Charger IC - 8GB LPDDR5 RAM - 64GB eMMC 5.1 - 128GB UFS - 20V DC Jack - USB Type-C Power Adapter - Micro SD card slot - Push Button x 4 (Power, Reset, Download and Home Key) - LED x 3 (System Power, Reset, DC-IN Power) - USB Type-C Connector (USB 3.2) x 2 - USB Type-C Connector (USB 2.0) x 1 - 3.5mm Earphone Jack x 1 (with Microphone Input) - 3.5mm Line Out Audio Jack x 1 - Analog Microphone x 1 - Digital Microphone x 2 - Gigabit Ethernet with RJ45 connector - DP x 1 (Mode over USB Type-C) - LVDS port x 1 - eDP port x 1 - UART x2 with serial-to-usb converters and USB Type-C connectors - UART Port x 2 on Pin Header - M.2 Slot x 2 - I2C Capacitive Touch Pad - 4-Lane DSI x 1 - 4-Data Lane CSI x 2 - I2S Pin header - 40-Pin 2.54mm Pin Header x 1 - CAN Bus x 1 (RS232 Connector) Signed-off-by: Louis-Alexis Eyraud --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8189.dtsi | 1009 ++++++++++++++++= ++++ .../boot/dts/mediatek/mt8391-genio-720-evk.dts | 27 + .../boot/dts/mediatek/mt8391-genio-common.dtsi | 798 ++++++++++++++++ 4 files changed, 1835 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index a86fb313b1a9..5c75ea1ef09a 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -173,6 +173,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-genio-1200-evk-= ufs.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8390-genio-700-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8390-grinn-genio-700-sbc.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8390-tungsten-smarc.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8391-genio-720-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-kontron-3-5-sbc-i1200.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-radxa-nio-12l.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-radxa-nio-12l-8-hd-panel.dtbo diff --git a/arch/arm64/boot/dts/mediatek/mt8189.dtsi b/arch/arm64/boot/dts= /mediatek/mt8189.dtsi new file mode 100644 index 000000000000..b64882a93151 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8189.dtsi @@ -0,0 +1,1009 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2025 MediaTek Inc. + * + * Copyright (c) 2025 Collabora Ltd. + * Author: Louis-Alexis Eyraud + */ + +#include +#include +#include +#include +#include + +/ { + compatible =3D "mediatek,mt8189"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + clk32k: clock-32k { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32000>; + clock-output-names =3D "clk32k"; + }; + + clk13m: clock-13m { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + clocks =3D <&clk26m>; + clock-mult =3D <1>; + clock-div =3D <2>; + clock-output-names =3D "clk13m"; + }; + + clk26m: clock-26m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + clock-output-names =3D "clk26m"; + }; + + clock-520m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <520000000>; + clock-output-names =3D "ulposc"; + }; + + clock-vow-26m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + clock-output-names =3D "vowpll"; + }; + + clock-auxadc-26m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + clock-output-names =3D "aud_adc_ext"; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x000>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <282>; + cpu-idle-states =3D <&cpu_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x100>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <282>; + cpu-idle-states =3D <&cpu_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x200>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <282>; + cpu-idle-states =3D <&cpu_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x300>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <282>; + cpu-idle-states =3D <&cpu_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x400>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <282>; + cpu-idle-states =3D <&cpu_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x500>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <282>; + cpu-idle-states =3D <&cpu_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x600>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + cpu-idle-states =3D <&cpu_off_b>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_1>; + performance-domains =3D <&performance 1>; + #cooling-cells =3D <2>; + }; + + cpu7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x700>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + cpu-idle-states =3D <&cpu_off_b>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_1>; + performance-domains =3D <&performance 1>; + #cooling-cells =3D <2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + + core4 { + cpu =3D <&cpu4>; + }; + + core5 { + cpu =3D <&cpu5>; + }; + + core6 { + cpu =3D <&cpu6>; + }; + + core7 { + cpu =3D <&cpu7>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + cpu_off_l: cpu-off-l { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x00010000>; + local-timer-stop; + entry-latency-us =3D <25>; + exit-latency-us =3D <57>; + min-residency-us =3D <5700>; + }; + + cpu_off_b: cpu-off-b { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x00010000>; + local-timer-stop; + entry-latency-us =3D <35>; + exit-latency-us =3D <82>; + min-residency-us =3D <1890>; + }; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <131072>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + next-level-cache =3D <&l3_0>; + cache-unified; + }; + + l2_1: l2-cache1 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <262144>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + next-level-cache =3D <&l3_0>; + cache-unified; + }; + + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-size =3D <1048576>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; + }; + }; + + dsu-pmu { + compatible =3D "arm,dsu-pmu"; + interrupts =3D ; + cpus =3D <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, + <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + status =3D "fail"; + }; + + fhctl: fhctl@1000ce00 { + compatible =3D "mediatek,mt8189-fhctl"; + clocks =3D <&apmixedsys CLK_APMIXED_APUPLL>, + <&apmixedsys CLK_APMIXED_APUPLL2>, + <&apmixedsys CLK_APMIXED_ARMPLL_LL>, + <&apmixedsys CLK_APMIXED_ARMPLL_BL>, + <&apmixedsys CLK_APMIXED_CCIPLL>, + <&apmixedsys CLK_APMIXED_EMIPLL>, + <&apmixedsys CLK_APMIXED_MAINPLL>, + <&apmixedsys CLK_APMIXED_MFGPLL>, + <&apmixedsys CLK_APMIXED_MMPLL>, + <&apmixedsys CLK_APMIXED_MSDCPLL>, + <&apmixedsys CLK_APMIXED_TVDPLL1>, + <&apmixedsys CLK_APMIXED_TVDPLL2>, + <&apmixedsys CLK_APMIXED_UFSPLL>; + reg =3D <0 0x1000ce00 0 0x200>; + status =3D "okay"; + }; + + memory: memory@40000000 { + device_type =3D "memory"; + /* This memory size is filled in by the bootloader */ + reg =3D <0 0x40000000 0 0>; + }; + + pmu-a55 { + compatible =3D "arm,cortex-a55-pmu"; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + pmu-a78 { + compatible =3D "arm,cortex-a78-pmu"; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + dma-ranges =3D <0x0 0x0 0x0 0x0 0x10 0x0>; + + performance: performance-controller@108d78 { + compatible =3D "mediatek,cpufreq-hw"; + reg =3D <0 0x00108d78 0 0x120>, <0 0x00108e98 0 0x120>; + #performance-domain-cells =3D <1>; + }; + + gic: interrupt-controller@c000000 { + compatible =3D "arm,gic-v3"; + reg =3D <0 0xc000000 0 0x40000>, /* distributor */ + <0 0xc040000 0 0x200000>; /* redistributor */ + interrupt-parent =3D <&gic>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <4>; + #redistributor-regions =3D <1>; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity =3D <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity =3D <&cpu6 &cpu7>; + }; + }; + }; + + clock-controller@d01a000 { + compatible =3D "mediatek,mt8189-dbg-ao"; + reg =3D <0 0xd01a000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@d0a0000 { + compatible =3D "mediatek,mt8189-dem"; + reg =3D <0 0xd0a0000 0 0x1000>; + #clock-cells =3D <1>; + }; + + topckgen: clock-controller@10000000 { + compatible =3D "mediatek,mt8189-topckgen", "syscon"; + reg =3D <0 0x10000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + infra_ao: clock-controller@10001000 { + compatible =3D "mediatek,mt8189-infra-ao", "syscon"; + reg =3D <0 0x10001000 0 0x1000>; + #clock-cells =3D <1>; + }; + + pio: pinctrl@10005000 { + compatible =3D "mediatek,mt8189-pinctrl"; + reg =3D <0 0x10005000 0 0x1000>, + <0 0x11b50000 0 0x1000>, + <0 0x11c50000 0 0x1000>, + <0 0x11c60000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11d30000 0 0x1000>, + <0 0x11d40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e30000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11ce0000 0 0x1000>, + <0 0x11de0000 0 0x1000>, + <0 0x11e60000 0 0x1000>, + <0 0x1c01e000 0 0x1000>, + <0 0x11f00000 0 0x1000>; + reg-names =3D "base", "lm", "rb0", "rb1", "bm0", "bm1", + "bm2", "lt0", "lt1", "rt", "eint0", "eint1", + "eint2", "eint3", "eint4"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pio 0 0 182>; + interrupt-controller; + interrupts =3D ; + #interrupt-cells =3D <2>; + }; + + apmixedsys: clock-controller@1000c000 { + compatible =3D "mediatek,mt8189-apmixedsys", "syscon"; + reg =3D <0 0x1000c000 0 0x1000>; + #clock-cells =3D <1>; + }; + + uart0: serial@11001000 { + compatible =3D "mediatek,mt8189-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11001000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&peri_ao CLK_PERAO_UART0>; + clock-names =3D "baud", "bus"; + dmas =3D <&apdma 0>, <&apdma 1>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + uart1: serial@11002000 { + compatible =3D "mediatek,mt8189-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11002000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&peri_ao CLK_PERAO_UART1>; + clock-names =3D "baud", "bus"; + dmas =3D <&apdma 2>, <&apdma 3>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + uart2: serial@11003000 { + compatible =3D "mediatek,mt8189-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11003000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&peri_ao CLK_PERAO_UART2>; + clock-names =3D "baud", "bus"; + dmas =3D <&apdma 4>, <&apdma 5>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + uart3: serial@11004000 { + compatible =3D "mediatek,mt8189-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11004000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&peri_ao CLK_PERAO_UART3>; + clock-names =3D "baud", "bus"; + dmas =3D <&apdma 6>, <&apdma 7>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + auxadc: adc@11019000 { + compatible =3D "mediatek,mt8189-auxadc", "mediatek,mt8173-auxadc"; + reg =3D <0 0x11019000 0 0x1000>; + clocks =3D <&peri_ao CLK_PERAO_AUXADC_26M>; + clock-names =3D "main"; + #io-channel-cells =3D <1>; + status =3D "disabled"; + }; + + eth: ethernet@1101a000 { + compatible =3D "mediatek,mt8189-gmac", "snps,dwmac-5.10a"; + reg =3D <0 0x1101a000 0 0x4000>; + assigned-clocks =3D <&topckgen CLK_TOP_ETH_250M_SEL>, + <&topckgen CLK_TOP_ETH_62P4M_PTP_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_ETHPLL_D2>, + <&topckgen CLK_TOP_ETHPLL_D8>; + clocks =3D <&topckgen CLK_TOP_ETH_250M_SEL>, + <&topckgen CLK_TOP_ETH_62P4M_PTP_SEL>; + clock-names =3D "mac_main", "ptp_ref"; + interrupts =3D ; + interrupt-names =3D "macirq"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_PCIE>; + mediatek,pericfg =3D <&peri_ao>; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + snps,txpbl =3D <16>; + snps,rxpbl =3D <16>; + snps,clk-csr =3D <0>; + status =3D "disabled"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,blen =3D <0 0 0 0 16 8 4>; + snps,rd_osr_lmt =3D <0x7>; + snps,wr_osr_lmt =3D <0x7>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + snps,tx-sched-wrr; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x0>; + snps,weight =3D <0x10>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + snps,weight =3D <0x11>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + snps,weight =3D <0x12>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x3>; + snps,weight =3D <0x13>; + }; + }; + }; + + peri_ao: clock-controller@11036000 { + compatible =3D "mediatek,mt8189-peri-ao", "syscon"; + reg =3D <0 0x11036000 0 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + mmc0: mmc@11230000 { + compatible =3D "mediatek,mt8189-mmc"; + reg =3D <0 0x11230000 0 0x10000>, <0 0x11e70000 0 0x1000>; + clocks =3D <&topckgen CLK_TOP_MSDC50_0_SEL>, + <&peri_ao CLK_PERAO_MSDC0_H>, + <&peri_ao CLK_PERAO_MSDC0>, + <&topckgen CLK_TOP_MSDC50_0_HCLK_SEL>, + <&peri_ao CLK_PERAO_MSDC0_SLV_H>, + <&peri_ao CLK_PERAO_MSDC0_MST_F>; + clock-names =3D "source", "hclk", "source_cg", + "bus_clk", "pclk_cg", "axi_cg"; + interrupts =3D ; + status =3D "disabled"; + }; + + mmc1: mmc@11240000 { + compatible =3D "mediatek,mt8189-mmc"; + reg =3D <0 0x11240000 0 0x1000>, <0 0x11d80000 0 0x1000>; + clocks =3D <&topckgen CLK_TOP_MSDC30_1_SEL>, + <&peri_ao CLK_PERAO_MSDC1_H>, + <&peri_ao CLK_PERAO_MSDC1>, + <&topckgen CLK_TOP_MSDC30_1_HCLK_SEL>, + <&peri_ao CLK_PERAO_MSDC1_SLV_H>, + <&peri_ao CLK_PERAO_MSDC1_MST_F>; + clock-names =3D "source", "hclk", "source_cg", + "bus_clk", "pclk_cg", "axi_cg"; + interrupts =3D ; + status =3D "disabled"; + }; + + clock-controller@112b8000 { + compatible =3D "mediatek,mt8189-ufscfg-ao"; + reg =3D <0 0x112b8000 0 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + clock-controller@112bb000 { + compatible =3D "mediatek,mt8189-ufscfg-pdn"; + reg =3D <0 0x112bb000 0 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + pcie: pcie@112f0000 { + compatible =3D "mediatek,mt8189-pcie", "mediatek,mt8192-pcie"; + reg =3D <0 0x112f0000 0 0x4000>; + reg-names =3D "pcie-mac"; + ranges =3D <0x82000000 0 0x30000000 0x0 0x30000000 0 0x04000000>; + bus-range =3D <0x00 0xff>; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + clocks =3D <&peri_ao CLK_PERAO_AHB_APB>, + <&topckgen CLK_TOP_F26M_CK_EN>, + <&peri_ao CLK_PERAO_TL>, + <&clk32k>, + <&peri_ao CLK_PERAO_REF>, + <&peri_ao CLK_PERAO_AXI>; + clock-names =3D "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "peri_mem"; + #interrupt-cells =3D <1>; + interrupts =3D ; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask =3D <0 0 0 7>; + phys =3D <&pcieport PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_PCIE>; + status =3D "disabled"; + + pcie_intc: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + apdma: dma-controller@11300b00 { + compatible =3D "mediatek,mt8189-uart-dma", "mediatek,mt6985-uart-dma"; + reg =3D <0 0x11300b00 0 0x80>, + <0 0x11300b80 0 0x80>, + <0 0x11300c00 0 0x80>, + <0 0x11300c80 0 0x80>, + <0 0x11300d00 0 0x80>, + <0 0x11300d80 0 0x80>, + <0 0x11300e00 0 0x80>, + <0 0x11300e80 0 0x80>; + interrupts =3D , + , + , + , + , + , + , + ; + clocks =3D <&peri_ao CLK_PERAO_DMA_B>; + clock-names =3D "apdma"; + dma-requests =3D <8>; + #dma-cells =3D <1>; + }; + + i2c2: i2c@11b20000 { + compatible =3D "mediatek,mt8189-i2c", "mediatek,mt8188-i2c"; + reg =3D <0 0x11b20000 0 0x1000>, <0 0x11300400 0 0x80>; + #address-cells =3D <1>; + clock-div =3D <1>; + clocks =3D <&iic_wrap_ws CLK_IMPWS_I2C2>, <&peri_ao CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + interrupts =3D ; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + iic_wrap_ws: clock-controller@11b21e00 { + compatible =3D "mediatek,mt8189-iic-wrap-ws"; + reg =3D <0 0x11b21e00 0 0x10>; + #clock-cells =3D <1>; + }; + + i2c0: i2c@11c20000 { + compatible =3D "mediatek,mt8189-i2c", "mediatek,mt8188-i2c"; + reg =3D <0 0x11c20000 0 0x1000>, <0 0x11300200 0 0x80>; + #address-cells =3D <1>; + clock-div =3D <1>; + clocks =3D <&iic_wrap_e CLK_IMPE_I2C0>, <&peri_ao CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + interrupts =3D ; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c1: i2c@11c21000 { + compatible =3D "mediatek,mt8189-i2c", "mediatek,mt8188-i2c"; + reg =3D <0 0x11c21000 0 0x1000>, <0 0x11300300 0 0x80>; + #address-cells =3D <1>; + clock-div =3D <1>; + clocks =3D <&iic_wrap_e CLK_IMPE_I2C1>, <&peri_ao CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + interrupts =3D ; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + iic_wrap_e: clock-controller@11c22e00 { + compatible =3D "mediatek,mt8189-iic-wrap-e"; + reg =3D <0 0x11c22e00 0 0x10>; + #clock-cells =3D <1>; + }; + + i2c3: i2c@11d70000 { + compatible =3D "mediatek,mt8189-i2c", "mediatek,mt8188-i2c"; + reg =3D <0 0x11d70000 0 0x1000>, <0 0x11300500 0 0x80>; + #address-cells =3D <1>; + clock-div =3D <1>; + clocks =3D <&iic_wrap_s CLK_IMPS_I2C3>, <&peri_ao CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + interrupts =3D ; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c4: i2c@11d71000 { + compatible =3D "mediatek,mt8189-i2c", "mediatek,mt8188-i2c"; + reg =3D <0 0x11d71000 0 0x1000>, <0 0x11300600 0 0x80>; + #address-cells =3D <1>; + clock-div =3D <1>; + clocks =3D <&iic_wrap_s CLK_IMPS_I2C4>, <&peri_ao CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + interrupts =3D ; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c5: i2c@11d72000 { + compatible =3D "mediatek,mt8189-i2c", "mediatek,mt8188-i2c"; + reg =3D <0 0x11d72000 0 0x1000>, <0 0x11300700 0 0x80>; + #address-cells =3D <1>; + clock-div =3D <1>; + clocks =3D <&iic_wrap_s CLK_IMPS_I2C5>, <&peri_ao CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + interrupts =3D ; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c6: i2c@11d73000 { + compatible =3D "mediatek,mt8189-i2c", "mediatek,mt8188-i2c"; + reg =3D <0 0x11d73000 0 0x1000>, <0 0x11300800 0 0x80>; + #address-cells =3D <1>; + clock-div =3D <1>; + clocks =3D <&iic_wrap_s CLK_IMPS_I2C6>, <&peri_ao CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + interrupts =3D ; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + iic_wrap_s: clock-controller@11d74e00 { + compatible =3D "mediatek,mt8189-iic-wrap-s"; + reg =3D <0 0x11d74e00 0 0x10>; + #clock-cells =3D <1>; + }; + + pciephy: t-phy@11e50700 { + compatible =3D "mediatek,mt8189-tphy", "mediatek,generic-tphy-v3"; + ranges =3D <0x0 0x0 0x11e50700 0x700>; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&spm MT8189_POWER_DOMAIN_PCIE_PHY>; + status =3D "disabled"; + + pcieport: pcie-phy@0 { + reg =3D <0 0x700>; + clocks =3D <&topckgen CLK_TOP_SSPXTP_F26M_CK_EN>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + }; + }; + + efuse@11f10000 { + compatible =3D "mediatek,mt8189-efuse", "mediatek,mt8186-efuse"; + reg =3D <0 0x11f10000 0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + socinfo-data1@7a0 { + reg =3D <0x7a0 0x4>; + }; + + socinfo-data2@7e0 { + reg =3D <0x7e0 0x4>; + }; + }; + + i2c7: i2c@11f30000 { + compatible =3D "mediatek,mt8189-i2c", "mediatek,mt8188-i2c"; + reg =3D <0 0x11f30000 0 0x1000>, <0 0x11300900 0 0x80>; + #address-cells =3D <1>; + clock-div =3D <1>; + clocks =3D <&iic_wrap_en CLK_IMPEN_I2C7>, <&peri_ao CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + interrupts =3D ; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c8: i2c@11f31000 { + compatible =3D "mediatek,mt8189-i2c", "mediatek,mt8188-i2c"; + reg =3D <0 0x11f31000 0 0x1000>, <0 0x11300a00 0 0x80>; + #address-cells =3D <1>; + clock-div =3D <1>; + clocks =3D <&iic_wrap_en CLK_IMPEN_I2C8>, <&peri_ao CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + interrupts =3D ; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + iic_wrap_en: clock-controller@11f32e00 { + compatible =3D "mediatek,mt8189-iic-wrap-en"; + reg =3D <0 0x11f32e00 0 0x10>; + #clock-cells =3D <1>; + }; + + clock-controller@1c000800 { + compatible =3D "mediatek,mt8189-vlpcfg-ao"; + reg =3D <0 0x1c000800 0 0x10>; + #clock-cells =3D <1>; + }; + + scpsys: syscon@1c001000 { + compatible =3D "mediatek,mt8189-scpsys", "syscon", "simple-mfd"; + reg =3D <0 0x1c001000 0 0x1000>; + + /* System Power Manager */ + spm: power-controller { + compatible =3D "mediatek,mt8189-power-controller"; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + /* power domain of the SoC */ + power-domain@MT8189_POWER_DOMAIN_CONN { + reg =3D ; + mediatek,infracfg =3D <&infra_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8189_POWER_DOMAIN_AUDIO { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_AUD_INTBUS_SEL>; + clock-names =3D "audio"; + mediatek,infracfg =3D <&infra_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8189_POWER_DOMAIN_ADSP_AO { + reg =3D ; + clocks =3D <&vlpckgen CLK_VLP_CK_VADSP_SEL>; + clock-names =3D "vadsp"; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8189_POWER_DOMAIN_ADSP_INFRA { + reg =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT { + reg =3D ; + #power-domain-cells =3D <0>; + }; + }; + }; + + power-domain@MT8189_POWER_DOMAIN_SSUSB { + reg =3D ; + mediatek,infracfg =3D <&infra_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8189_POWER_DOMAIN_PCIE { + reg =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8189_POWER_DOMAIN_PCIE_PHY { + reg =3D ; + #power-domain-cells =3D <0>; + }; + }; + }; + }; + + watchdog@1c00a000 { + compatible =3D "mediatek,mt8189-wdt", "mediatek,mt6589-wdt"; + reg =3D <0 0x1c00a000 0 0x100>; + #reset-cells =3D <1>; + }; + + vlpcfg: clock-controller@1c00c000 { + compatible =3D "mediatek,mt8189-vlpcfg"; + reg =3D <0 0x1c00c000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@1c00f000 { + compatible =3D "mediatek,mt8189-dvfsrc-top"; + reg =3D <0 0x1c00f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + vlpckgen: clock-controller@1c012000 { + compatible =3D "mediatek,mt8189-vlpckgen", "syscon"; + reg =3D <0 0x1c012000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@1c80ae10 { + compatible =3D "mediatek,mt8189-scp-i2c-clk"; + reg =3D <0 0x1c80ae10 0 0x10>; + #clock-cells =3D <1>; + }; + + clock-controller@1cb21150 { + compatible =3D "mediatek,mt8189-scp-clk"; + reg =3D <0 0x1cb21150 0 0x10>; + #clock-cells =3D <1>; + }; + + pwrap: pwrap@1cc04000 { + compatible =3D "mediatek,mt8189-pwrap", "mediatek,mt8195-pwrap", "sysco= n"; + reg =3D <0 0x1cc04000 0 0x1000>; + reg-names =3D "pwrap"; + assigned-clocks =3D <&vlpckgen CLK_VLP_CK_PWRAP_ULPOSC_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_OSC_D10>; + clocks =3D <&vlpcfg CLK_VLPCFG_REG_PMIF_SPMI_M_SYS>, + <&vlpcfg CLK_VLPCFG_REG_PMIF_SPMI_M_TMR>; + clock-names =3D "spi", "wrap"; + interrupts =3D ; + }; + + spmi: spmi@1cc06000 { + compatible =3D "mediatek,mt8189-spmi", "mediatek,mt8195-spmi"; + reg =3D <0 0x1cc06000 0 0x000e00>, <0 0x1cc00000 0 0x000100>; + reg-names =3D "pmif", "spmimst"; + clocks =3D <&vlpcfg CLK_VLPCFG_REG_PMIF_SPMI_P_SYS>, + <&vlpcfg CLK_VLPCFG_REG_PMIF_SPMI_P_TMR>, + <&vlpckgen CLK_VLP_CK_SPMI_P_MST_SEL>; + clock-names =3D "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + + timer@1cc10000 { + compatible =3D "mediatek,mt8189-timer", "mediatek,mt6765-timer"; + reg =3D <0 0x1cc10000 0 0x1000>; + clocks =3D <&clk13m>; + interrupts =3D ; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8391-genio-720-evk.dts b/arch/a= rm64/boot/dts/mediatek/mt8391-genio-720-evk.dts new file mode 100644 index 000000000000..717077806e24 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8391-genio-720-evk.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2025 Collabora Ltd. + * Author: Louis-Alexis Eyraud + */ +/dts-v1/; + +#include "mt8189.dtsi" +#include "mt8391-genio-common.dtsi" + +/ { + model =3D "MediaTek Genio 720 EVK"; + compatible =3D "mediatek,mt8391-evk", "mediatek,mt8391", + "mediatek,mt8189"; +}; + +&cpu6 { + cpu-supply =3D <&mt6319_sid7_vbuck1>; +}; + +&cpu7 { + cpu-supply =3D <&mt6319_sid7_vbuck1>; +}; + +&mt6319_sid7 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8391-genio-common.dtsi b/arch/a= rm64/boot/dts/mediatek/mt8391-genio-common.dtsi new file mode 100644 index 000000000000..00c9f3c078f5 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8391-genio-common.dtsi @@ -0,0 +1,798 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2025 Collabora Ltd. + * Author: Louis-Alexis Eyraud + */ + +#include "mt6365.dtsi" + +#include +#include +#include +#include +#include +#include "mt8189-pinfunc.h" + +/ { + aliases { + ethernet0 =3D ð + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + i2c4 =3D &i2c4; + i2c5 =3D &i2c5; + i2c6 =3D &i2c6; + i2c7 =3D &i2c7; + i2c8 =3D &i2c8; + mmc0 =3D &mmc0; + mmc1 =3D &mmc1; + serial0 =3D &uart0; + }; + + chosen: chosen { + stdout-path =3D "serial0:921600n8"; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: memory@54600000 { + reg =3D <0 0x54600000 0x0 0x200000>; + no-map; + }; + }; + + /* system wide 4.2V power rail from charger */ + reg_vsys: regulator-vsys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys"; + regulator-always-on; + regulator-boot-on; + }; + + /* used by PCIe Wi-Fi Module */ + reg_wifi_3v3: regulator-1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "wifi_3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&pio 79 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_3v3_en_pins>; + vin-supply =3D <®_vsys>; + }; +}; + +&auxadc { + status =3D "okay"; +}; + +&cpu0 { + cpu-supply =3D <&mt6359_vmodem_buck_reg>; +}; + +&cpu1 { + cpu-supply =3D <&mt6359_vmodem_buck_reg>; +}; + +&cpu2 { + cpu-supply =3D <&mt6359_vmodem_buck_reg>; +}; + +&cpu3 { + cpu-supply =3D <&mt6359_vmodem_buck_reg>; +}; + +&cpu4 { + cpu-supply =3D <&mt6359_vmodem_buck_reg>; +}; + +&cpu5 { + cpu-supply =3D <&mt6359_vmodem_buck_reg>; +}; + +ð { + phy-handle =3D <ð_phy0>; + phy-mode =3D"rgmii-id"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <ð_default_pins>; + pinctrl-1 =3D <ð_sleep_pins>; + mediatek,mac-wol; + snps,reset-delays-us =3D <0 10000 10000>; + snps,reset-gpio =3D <&pio 135 GPIO_ACTIVE_LOW>; + status =3D "okay"; + + mdio { + eth_phy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-idc0ff.0421"; + reg =3D <0x0>; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* LED_D5 */ + led@0 { + reg =3D <0>; + active-high; + color =3D ; + default-state =3D "keep"; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <0>; + }; + + /* LED_D6 */ + led@1 { + reg =3D <1>; + active-high; + color =3D ; + default-state =3D "keep"; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <2>; + }; + + /* LED_D7 */ + led@2 { + reg =3D <2>; + active-low; + color =3D ; + default-state =3D "keep"; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <1>; + }; + }; + }; + }; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; + status =3D "okay"; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; + status =3D "okay"; +}; + +&i2c2 { + clock-frequency =3D <1000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pins>; + status =3D "okay"; +}; + +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3_pins>; + status =3D "disabled"; +}; + +&i2c4 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c4_pins>; + status =3D "okay"; +}; + +&i2c5 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c5_pins>; + status =3D "okay"; +}; + +&i2c6 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c6_pins>; + status =3D "okay"; +}; + +&i2c7 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c7_pins>; + status =3D "okay"; +}; + +&i2c8 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c8_pins>; + status =3D "okay"; +}; + +&mmc0 { + bus-width =3D <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + hs400-ds-delay =3D <0x1481b>; + max-frequency =3D <200000000>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + supports-cqe; + pinctrl-names =3D "default", "state_uhs"; + pinctrl-0 =3D <&mmc0_default_pins>; + pinctrl-1 =3D <&mmc0_uhs_pins>; + vmmc-supply =3D <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply =3D <&mt6359_vufs_ldo_reg>; + status =3D "okay"; +}; + +&mmc1 { + bus-width =3D <4>; + cap-sd-highspeed; + cd-gpios =3D <&pio 2 GPIO_ACTIVE_HIGH>; + max-frequency =3D <200000000>; + no-mmc; + no-sdio; + sd-uhs-sdr50; + sd-uhs-sdr104; + pinctrl-names =3D "default", "state_uhs"; + pinctrl-0 =3D <&mmc1_default_pins>; + pinctrl-1 =3D <&mmc1_uhs_pins>; + vmmc-supply =3D <&mt6359_vpa_buck_reg>; + vqmmc-supply =3D <&mt6359_vsim1_ldo_reg>; + status =3D "okay"; +}; + +&mt6359_va09_ldo_reg{ + regulator-name =3D "dvdd_sram_vadsp"; + regulator-always-on; +}; + +&mt6359_vaux18_ldo_reg { + regulator-always-on; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcore_buck_reg { + regulator-name =3D "dvdd_apu"; + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-name =3D "dvdd_sram_core"; + regulator-always-on; +}; + +&mt6359_vmodem_buck_reg { + regulator-name =3D "dvdd_proc_l"; + regulator-always-on; +}; + +&mt6359_vproc1_buck_reg { + regulator-name =3D "vgpu"; +}; + +&mt6359_vproc2_buck_reg { + regulator-name =3D "dvdd_core"; + regulator-always-on; +}; + +&mt6359_vpu_buck_reg { + regulator-name =3D "avdd075_emi"; + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-name =3D "va12_abb2"; + regulator-always-on; +}; + +&mt6359_vrfck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_md_ldo_reg { + regulator-name =3D "dvdd_sram_proc_l"; + regulator-always-on; +}; + +&mt6359_vsram_proc1_ldo_reg { + regulator-name =3D "vsram_gpu"; +}; + +&mt6359_vsram_proc2_ldo_reg { + regulator-name =3D "dvdd_sram_proc_b"; + regulator-always-on; +}; + +&mt6359_vsram_others_ldo_reg { + regulator-name =3D "dvdd_sram_apu"; + regulator-always-on; +}; + +&mt6359_vufs_ldo_reg { + regulator-always-on; +}; + +&pcie { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&pcie_default_pins>; + pinctrl-1 =3D <&pcie_sleep_pins>; + status =3D "okay"; +}; + +&pciephy { + status =3D "okay"; +}; + +&pio { + eth_default_pins: eth-default-pins { + pins-cc { + pinmux =3D , + , + , + ; + drive-strength =3D <8>; + }; + + pins-mdio { + pinmux =3D , + ; + drive-strength =3D <8>; + input-enable; + }; + + pins-power { + pinmux =3D , + ; + output-high; + }; + + pins-rxd { + pinmux =3D , + , + , + ; + drive-strength =3D <8>; + }; + + pins-txd { + pinmux =3D , + , + , + ; + drive-strength =3D <8>; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-cc { + pinmux =3D , + , + , + ; + }; + + pins-mdio { + pinmux =3D , + ; + input-disable; + bias-disable; + }; + + pins-rxd { + pinmux =3D , + , + , + ; + }; + + pins-txd { + pinmux =3D , + , + , + ; + }; + }; + + i2c0_pins: i2c0-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + i2c1_pins: i2c1-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + i2c2_pins: i2c2-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + i2c3_pins: i2c3-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + i2c4_pins: i2c4-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + i2c5_pins: i2c5-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + i2c7_pins: i2c7-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + i2c8_pins: i2c8-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux =3D ; + drive-strength =3D <6>; + bias-pull-down =3D ; + }; + + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D <6>; + bias-pull-up =3D ; + }; + + pins-rst { + pinmux =3D ; + drive-strength =3D <6>; + bias-pull-up =3D ; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D <8>; + bias-pull-up =3D ; + }; + + pins-ds { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + + pins-rst { + pinmux =3D ; + bias-pull-up =3D ; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-clk { + pinmux =3D ; + drive-strength =3D <6>; + bias-pull-down =3D ; + }; + + pins-cmd-dat { + pinmux =3D , + , + , + , + ; + input-enable; + drive-strength =3D <6>; + bias-pull-up =3D ; + }; + + pins-insert { + pinmux =3D ; + bias-pull-up; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-clk { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + + pins-cmd-dat { + pinmux =3D , + , + , + , + ; + input-enable; + drive-strength =3D <8>; + bias-pull-up =3D ; + }; + }; + + pcie_default_pins: pcie-default-pins { + pins-bus { + pinmux =3D , + , + ; + bias-pull-up; + }; + }; + + pcie_sleep_pins: pcie-sleep-pins { + pins { + pinmux =3D ; + bias-disable; + output-low; + }; + }; + + pcie_3v3_en_pins: pcie-3v3-en-pins { + pins { + pinmux =3D ; + output-high; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + + pins-rtscts { + pinmux =3D , + ; + }; + }; + + uart3_pins: uart3-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + + pins-rtscts { + pinmux =3D , + ; + }; + }; +}; + +&pmic { + interrupts-extended =3D <&pio 194 IRQ_TYPE_LEVEL_HIGH>; + vsys-smps-supply =3D <®_vsys>; + vsys-vcore-supply =3D <®_vsys>; + vsys-vgpu11-supply =3D <®_vsys>; + vsys-vgpu12-supply =3D <®_vsys>; + vsys-vpa-supply =3D <®_vsys>; + vsys-vproc1-supply =3D <®_vsys>; + vsys-vproc2-supply =3D <®_vsys>; + vsys-vpu-supply =3D <®_vsys>; + vsys-vs1-supply =3D <®_vsys>; + vsys-vs2-supply =3D <®_vsys>; + vsys-vmodem-supply =3D <®_vsys>; + vsys-ldo1-supply =3D <®_vsys>; + vsys-ldo2-supply =3D <®_vsys>; + vs1-ldo1-supply =3D <&mt6359_vs1_buck_reg>; + vs1-ldo2-supply =3D <&mt6359_vs1_buck_reg>; + vs2-ldo1-supply =3D <&mt6359_vs2_buck_reg>; + vs2-ldo2-supply =3D <&mt6359_vs2_buck_reg>; + + keys { + compatible =3D "mediatek,mt6365-keys", "mediatek,mt6359-keys"; + mediatek,long-press-mode =3D <1>; + power-off-time-sec =3D <0>; + + power-key { + linux,keycodes =3D ; + wakeup-source; + }; + + home { + linux,keycodes =3D ; + }; + }; +}; + +&spmi { + /* + * MT6319 PMIC SID can change depending on the boards so add + * in this include file the nodes for the possible values, + * disabled by default to limit the code duplication. + */ + mt6319_sid6: pmic@6 { + compatible =3D "mediatek,mt6319-regulator", "mediatek,mt6315-regulator"; + reg =3D <0x6 SPMI_USID>; + + pvdd1-supply =3D <®_vsys>; + pvdd2-supply =3D <®_vsys>; + pvdd3-supply =3D <®_vsys>; + pvdd4-supply =3D <®_vsys>; + + status =3D "disabled"; + + regulators { + mt6319_sid6_vbuck1: vbuck1 { + regulator-name =3D "dvdd_proc_b"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1193750>; + regulator-enable-ramp-delay =3D <256>; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + + vbuck3 { + regulator-name =3D "vdd2h_emi"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1193750>; + regulator-enable-ramp-delay =3D <256>; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + + vbuck4 { + regulator-name =3D "avddq_emi"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1193750>; + regulator-enable-ramp-delay =3D <256>; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + }; + }; + + mt6319_sid7: pmic@7 { + compatible =3D "mediatek,mt6319-regulator", "mediatek,mt6315-regulator"; + reg =3D <0x7 SPMI_USID>; + + pvdd1-supply =3D <®_vsys>; + pvdd2-supply =3D <®_vsys>; + pvdd3-supply =3D <®_vsys>; + pvdd4-supply =3D <®_vsys>; + + status =3D "disabled"; + + regulators { + mt6319_sid7_vbuck1: vbuck1 { + regulator-name =3D "dvdd_proc_b"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1193750>; + regulator-enable-ramp-delay =3D <256>; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + + vbuck3 { + regulator-name =3D "vdd2h_emi"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1193750>; + regulator-enable-ramp-delay =3D <256>; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + + vbuck4 { + regulator-name =3D "avddq_emi"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1193750>; + regulator-enable-ramp-delay =3D <256>; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + }; + }; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart1 { + pinctrl-0 =3D <&uart1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart2 { + pinctrl-0 =3D <&uart2_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart3 { + pinctrl-0 =3D <&uart3_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; --=20 2.55.0 From nobody Thu Sep 24 12:55:35 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FE0B43BDC8; Thu, 24 Sep 2026 08:39:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790239190; cv=none; b=qkRiFtvJoQEJJhrJAK5JYDp6PDW7OmX+xSM/OY4H+FPB8jCdEqToLAl97eSDtGmnxhrC1+0NH2A5gKr5Z4UuVSFJPPP2TlgkFKfeRsKCbA7XtL1DfCqOwMSt/C9NEbJhUTxcrromWt3g6yOavqCGzdUydvKOt455Nz/7ppBb/7E= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260924-add-mediatek-genio-520-720-evk-v3-4-2ec5c80677d4@collabora.com> References: <20260924-add-mediatek-genio-520-720-evk-v3-0-2ec5c80677d4@collabora.com> In-Reply-To: <20260924-add-mediatek-genio-520-720-evk-v3-0-2ec5c80677d4@collabora.com> To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Sean Wang Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790239184; l=3368; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=EETdgEDLf9xnEdLLlR5xefqHysCkpeORLVvQGQ1eyMk=; b=TXovTYgd41NpTpxrSao0sRVf/zsni/cXGy69f9J/nwCaVk9DcyJtpMZ+qsJgluIP+6+/BabBX bDqHuILwm9RBaktDU5JwNv87o9wcrw+SkldMyaifzK+EaKNJViN/UDF X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add devicetree for the basic hardware enablement of the Genio 520-EVK board, based on MT8371 SoC. MT8371 SoC is a variant of MT8189 SoC with the following differences: - Arm Cortex-A78 CPU core maximum frequency (2.2 Ghz for MT8371, 3 Ghz for MT8189). - Arm Mali G57 MC2 GPU core maximum frequency (880 Mhz for MT8371, 1.1 Ghz for MT8189) - one ISP engine instead of two MT8371 hardware register maps are identical to MT8189. The Genio 520-EVK has following features: - MT8371 SoC - MT6365 PMIC - MT6319 Buck IC - MT6375 Charger IC - 8GB LPDDR5 RAM - 64GB eMMC 5.1 - 128GB UFS - 20V DC Jack - USB Type-C Power Adapter - Micro SD card slot - Push Button x 4 (Power, Reset, Download and Home Key) - LED x 3 (System Power, Reset, DC-IN Power) - USB Type-C Connector (USB 3.2) x 2 - USB Type-C Connector (USB 2.0) x 1 - 3.5mm Earphone Jack x 1 (with Microphone Input) - 3.5mm Line Out Audio Jack x 1 - Analog Microphone x 1 - Digital Microphone x 2 - Gigabit Ethernet with RJ45 connector - DP x 1 (Mode over USB Type-C) - LVDS port x 1 - eDP port x 1 - UART x2 with serial-to-usb converters and USB Type-C connectors - UART Port x 2 on Pin Header - M.2 Slot x 2 - I2C Capacitive Touch Pad - 4-Lane DSI x 1 - 4-Data Lane CSI x 2 - I2S Pin header - 40-Pin 2.54mm Pin Header x 1 - CAN Bus x 1 (RS232 Connector) Signed-off-by: Louis-Alexis Eyraud --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../boot/dts/mediatek/mt8371-genio-520-evk.dts | 32 ++++++++++++++++++= ++++ 2 files changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index 5c75ea1ef09a..e6a8109ffbaa 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -168,6 +168,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8370-genio-510-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8370-grinn-genio-510-sbc.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8370-tungsten-smarc.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8371-genio-520-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-genio-1200-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-genio-1200-evk-ufs.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8390-genio-700-evk.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8371-genio-520-evk.dts b/arch/a= rm64/boot/dts/mediatek/mt8371-genio-520-evk.dts new file mode 100644 index 000000000000..b4fd343bc08a --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8371-genio-520-evk.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2025 Collabora Ltd. + * Author: Louis-Alexis Eyraud + */ +/dts-v1/; + +#include "mt8189.dtsi" +#include "mt8391-genio-common.dtsi" + +/* + * MT8371 SoC is a variant of the MT8189 with only one ISP engine + * and lower maximum frequency on the big cores and on the Mali GPU. + */ + +/ { + model =3D "MediaTek Genio 520 EVK"; + compatible =3D "mediatek,mt8371-evk", "mediatek,mt8371", + "mediatek,mt8189"; +}; + +&cpu6 { + cpu-supply =3D <&mt6319_sid6_vbuck1>; +}; + +&cpu7 { + cpu-supply =3D <&mt6319_sid6_vbuck1>; +}; + +&mt6319_sid6 { + status =3D "okay"; +}; --=20 2.55.0