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[83.233.130.25]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae6dcf0dsm197647666b.61.2026.09.23.14.59.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 14:59:14 -0700 (PDT) From: Yongzhao Chen To: netdev@vger.kernel.org Cc: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Jonathan Corbet , Shuah Khan , Randy Dunlap , Florian Fainelli , Jonas Gorski , Andrew Lunn , Vladimir Oltean , Woojung Huh , UNGLinuxDriver@microchip.com, Russell King , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Ziyang Huang Subject: [RFC PATCH net-next v3 1/5] net: dsa: pass PHY flags when connecting shared ports Date: Wed, 23 Sep 2026 23:58:53 +0200 Message-ID: <20260923215858.1653-2-yongzhao.derek@gmail.com> X-Mailer: git-send-email 2.45.2.windows.1 In-Reply-To: <20260923215858.1653-1-yongzhao.derek@gmail.com> References: <20260923215858.1653-1-yongzhao.derek@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" DSA calls get_phy_flags() for user ports, but passes zero when connecting CPU or DSA port PHYs. Pass the callback result before PHY initialization for shared ports too. Drivers without the callback still pass zero. Keep bcm_sf2 and ksz88xx shared-port flags at zero, preserving their existing behavior. Document the extended callback scope. This lets qca8k pass revision information and a SmartSpeed quirk to an internal PHY used as a CPU link. The remaining patches supply that user. Assisted-by: LLM Signed-off-by: Yongzhao Chen Reviewed-by: Florian Fainelli --- Documentation/networking/dsa/dsa.rst | 2 ++ drivers/net/dsa/bcm_sf2.c | 4 ++++ drivers/net/dsa/microchip/ksz8.c | 4 ++++ net/dsa/port.c | 6 +++++- 4 files changed, 15 insertions(+), 1 deletion(-) diff --git a/Documentation/networking/dsa/dsa.rst b/Documentation/networkin= g/dsa/dsa.rst index 7edfdd555..647f952e3 100644 --- a/Documentation/networking/dsa/dsa.rst +++ b/Documentation/networking/dsa/dsa.rst @@ -668,6 +668,8 @@ PHY devices and link management on its own (e.g.: coming from switch memory mapped registers), this func= tion should return a 32-bit bitmask of "flags" that is private between the sw= itch driver and the Ethernet PHY driver in ``drivers/net/phy/\*``. + It is called when connecting PHYs for user, CPU and DSA ports. Drivers + should return zero for ports that do not need switch-specific PHY flags. =20 - ``phy_read``: Function invoked by the DSA user MDIO bus when attempting = to read the switch port MDIO registers. If unavailable, return 0xffff for each r= ead. diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c index 9e5713015..f516fc396 100644 --- a/drivers/net/dsa/bcm_sf2.c +++ b/drivers/net/dsa/bcm_sf2.c @@ -709,6 +709,10 @@ static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch = *ds, int port) { struct bcm_sf2_priv *priv =3D bcm_sf2_to_priv(ds); =20 + /* Shared ports previously received no PHY flags. */ + if (!dsa_is_user_port(ds, port)) + return 0; + /* The BCM7xxx PHY driver expects to find the integrated PHY revision * in bits 15:8 and the patch level in bits 7:0 which is exactly what * the REG_PHY_REVISION register layout is. diff --git a/drivers/net/dsa/microchip/ksz8.c b/drivers/net/dsa/microchip/k= sz8.c index d74981320..be8861a7a 100644 --- a/drivers/net/dsa/microchip/ksz8.c +++ b/drivers/net/dsa/microchip/ksz8.c @@ -3076,6 +3076,10 @@ static u32 ksz88xx_get_phy_flags(struct dsa_switch *= ds, int port) { struct ksz_device *dev =3D ds->priv; =20 + /* Shared ports previously received no PHY flags. */ + if (!dsa_is_user_port(ds, port)) + return 0; + switch (dev->chip_id) { case KSZ88X3_CHIP_ID: /* Silicon Errata Sheet (DS80000830A): diff --git a/net/dsa/port.c b/net/dsa/port.c index 1f5536c0d..4db7e6f9c 100644 --- a/net/dsa/port.c +++ b/net/dsa/port.c @@ -1666,6 +1666,7 @@ static int dsa_shared_port_phylink_register(struct ds= a_port *dp) { struct dsa_switch *ds =3D dp->ds; struct device_node *port_dn =3D dp->dn; + u32 phy_flags =3D 0; int err; =20 dp->pl_config.dev =3D ds->dev; @@ -1675,7 +1676,10 @@ static int dsa_shared_port_phylink_register(struct d= sa_port *dp) if (err) return err; =20 - err =3D phylink_of_phy_connect(dp->pl, port_dn, 0); + if (ds->ops->get_phy_flags) + phy_flags =3D ds->ops->get_phy_flags(ds, dp->index); + + err =3D phylink_of_phy_connect(dp->pl, port_dn, phy_flags); if (err && err !=3D -ENODEV) { pr_err("could not attach to PHY: %d\n", err); goto err_phy_connect; --=20 2.43.0 From nobody Thu Sep 24 14:25:43 2026 Received: from mail-ej2-f12.google.com (mail-ej2-f12.google.com [74.125.228.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9326C51993C for ; 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[83.233.130.25]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae6dcf0dsm197647666b.61.2026.09.23.14.59.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 14:59:16 -0700 (PDT) From: Yongzhao Chen To: netdev@vger.kernel.org Cc: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Florian Fainelli , Andrew Lunn , Vladimir Oltean , Christian Marangi , Russell King , linux-kernel@vger.kernel.org, Ziyang Huang Subject: [RFC PATCH net-next v3 2/5] net: dsa: qca8k: serialize CPU MAC pause during MTU changes Date: Wed, 23 Sep 2026 23:58:54 +0200 Message-ID: <20260923215858.1653-3-yongzhao.derek@gmail.com> X-Mailer: git-send-email 2.45.2.windows.1 In-Reply-To: <20260923215858.1653-1-yongzhao.derek@gmail.com> References: <20260923215858.1653-1-yongzhao.derek@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The global maximum frame size must be updated with CPU MACs disabled. The previous logic only paused ports 0 and 6, leaving an internal PHY CPU port enabled while modifying the register. Include enabled internal CPU ports in the pause sequence. Use the existing reg_mutex to serialize the MTU update against port enable, port disable, and phylink link-up and link-down transitions. Read and restore each port's original TXMAC and RXMAC bits, ensuring ports that were down remain down and preserving LINK_AUTO. Retain existing handling for ports 0 and 6. Abort before updating the frame size if reading port status or pausing the MAC fails. Attempt to restore all ports already modified, and report any restoration failures even if an earlier error occurred. The standalone qca8k MDIO error-propagation fix is a prerequisite for this series; that error-handling bug predates this locking change. Signed-off-by: Yongzhao Chen Assisted-by: LLM --- drivers/net/dsa/qca/qca8k-8xxx.c | 2 + drivers/net/dsa/qca/qca8k-common.c | 79 ++++++++++++++++++++++++------ 2 files changed, 66 insertions(+), 15 deletions(-) diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8= xxx.c index f9e2eb0b9..d8564001c 100644 --- a/drivers/net/dsa/qca/qca8k-8xxx.c +++ b/drivers/net/dsa/qca/qca8k-8xxx.c @@ -1488,7 +1488,9 @@ qca8k_phylink_mac_link_up(struct phylink_config *conf= ig, =20 reg |=3D QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC; =20 + mutex_lock(&priv->reg_mutex); qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg); + mutex_unlock(&priv->reg_mutex); } =20 static struct qca8k_pcs *pcs_to_qca8k_pcs(struct phylink_pcs *pcs) diff --git a/drivers/net/dsa/qca/qca8k-common.c b/drivers/net/dsa/qca/qca8k= -common.c index 13005f10e..6b32bdd75 100644 --- a/drivers/net/dsa/qca/qca8k-common.c +++ b/drivers/net/dsa/qca/qca8k-common.c @@ -463,7 +463,8 @@ int qca8k_mib_init(struct qca8k_priv *priv) return ret; } =20 -void qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable) +static void qca8k_port_set_status_locked(struct qca8k_priv *priv, int port, + int enable) { u32 mask =3D QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC; =20 @@ -477,6 +478,13 @@ void qca8k_port_set_status(struct qca8k_priv *priv, in= t port, int enable) regmap_clear_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask); } =20 +void qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable) +{ + mutex_lock(&priv->reg_mutex); + qca8k_port_set_status_locked(priv, port, enable); + mutex_unlock(&priv->reg_mutex); +} + void qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data) { @@ -751,8 +759,10 @@ int qca8k_port_enable(struct dsa_switch *ds, int port, { struct qca8k_priv *priv =3D ds->priv; =20 - qca8k_port_set_status(priv, port, 1); + mutex_lock(&priv->reg_mutex); + qca8k_port_set_status_locked(priv, port, 1); priv->port_enabled_map |=3D BIT(port); + mutex_unlock(&priv->reg_mutex); =20 if (dsa_is_user_port(ds, port)) phy_support_asym_pause(phy); @@ -764,14 +774,20 @@ void qca8k_port_disable(struct dsa_switch *ds, int po= rt) { struct qca8k_priv *priv =3D ds->priv; =20 - qca8k_port_set_status(priv, port, 0); + mutex_lock(&priv->reg_mutex); + qca8k_port_set_status_locked(priv, port, 0); priv->port_enabled_map &=3D ~BIT(port); + mutex_unlock(&priv->reg_mutex); } =20 int qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) { + u32 mask =3D QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC; struct qca8k_priv *priv =3D ds->priv; - int ret; + u32 status[QCA8K_NUM_PORTS] =3D { 0 }; + int ret, restore_ret, i; + u32 stopped =3D 0; + u32 ports; =20 /* We have only have a general MTU setting. * DSA always set the CPU port's MTU to the largest MTU of the user @@ -784,25 +800,58 @@ int qca8k_port_change_mtu(struct dsa_switch *ds, int = port, int new_mtu) =20 /* To change the MAX_FRAME_SIZE the cpu ports must be off or * the switch panics. - * Turn off both cpu ports before applying the new value to prevent - * this. + * Include internal PHY CPU ports as well as the two MAC-only ports. + * Toggle only MAC enables, preserving the phylink link-control mode. */ - if (priv->port_enabled_map & BIT(0)) - qca8k_port_set_status(priv, 0, 0); + ports =3D BIT(0) | BIT(6); + for (i =3D 1; i < 6; i++) + if (dsa_is_cpu_port(ds, i)) + ports |=3D BIT(i); =20 - if (priv->port_enabled_map & BIT(6)) - qca8k_port_set_status(priv, 6, 0); + mutex_lock(&priv->reg_mutex); + ports &=3D priv->port_enabled_map; + + for (i =3D 0; i < QCA8K_NUM_PORTS; i++) { + if (!(ports & BIT(i))) + continue; + + ret =3D regmap_read(priv->regmap, QCA8K_REG_PORT_STATUS(i), + &status[i]); + if (ret) + goto unlock; + } + + for (i =3D 0; i < QCA8K_NUM_PORTS; i++) { + if (!(ports & BIT(i)) || !(status[i] & mask)) + continue; + + stopped |=3D BIT(i); + ret =3D regmap_clear_bits(priv->regmap, QCA8K_REG_PORT_STATUS(i), + mask); + if (ret) + goto restore; + } =20 /* Include L2 header / FCS length */ ret =3D qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, new_mtu + ETH_HLEN + ETH_FCS_LEN); =20 - if (priv->port_enabled_map & BIT(0)) - qca8k_port_set_status(priv, 0, 1); - - if (priv->port_enabled_map & BIT(6)) - qca8k_port_set_status(priv, 6, 1); +restore: + for (i =3D 0; i < QCA8K_NUM_PORTS; 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[83.233.130.25]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae6dcf0dsm197647666b.61.2026.09.23.14.59.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 14:59:17 -0700 (PDT) From: Yongzhao Chen To: netdev@vger.kernel.org Cc: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Florian Fainelli , Andrew Lunn , Vladimir Oltean , Christian Marangi , Russell King , linux-kernel@vger.kernel.org, Ziyang Huang Subject: [RFC PATCH net-next v3 3/5] net: dsa: qca8k: support QCA8337 internal PHY CPU links Date: Wed, 23 Sep 2026 23:58:55 +0200 Message-ID: <20260923215858.1653-4-yongzhao.derek@gmail.com> X-Mailer: git-send-email 2.45.2.windows.1 In-Reply-To: <20260923215858.1653-1-yongzhao.derek@gmail.com> References: <20260923215858.1653-1-yongzhao.derek@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ziyang Huang A PHY-to-PHY CPU link connects the SoC PHY directly to an internal switch PHY. The QCA8337 supports header mode on these ports, and existing phylink callbacks already handle their internal interfaces. Allow QCA8337 CPU port selection to fall back to ports 1 through 5 after checking the dedicated MAC-only ports. Preserve the preference for CPU ports 0 and 6 across all switch models, limiting the internal-port fallback to QCA8337. Support for QCA8327 internal CPU links remains an open question in this RFC. Include internal CPU PHYs when selecting the PHY access method, without altering the handling of MAC-only or external user ports. This enables a single internal CPU PHY configured with an explicit phy-handle and phy-mode =3D "internal". The conduit interface uses its own PHY on the opposite side of the MDI connection. Existing single-CPU DSA forwarding uses the selected port for default flooding and membership without extra routing changes. Adapted from the OpenWrt PHY-to-PHY CPU link patch, narrowing the MDIO filter adjustments to preserve handling for external user ports. [yongzhao: preserve external user-port handling on port 6 and limit internal CPU PHY support to QCA8337] Assisted-by: LLM Signed-off-by: Ziyang Huang Signed-off-by: Yongzhao Chen --- drivers/net/dsa/qca/qca8k-8xxx.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8= xxx.c index d8564001c..07640ce4a 100644 --- a/drivers/net/dsa/qca/qca8k-8xxx.c +++ b/drivers/net/dsa/qca/qca8k-8xxx.c @@ -1019,7 +1019,8 @@ qca8k_setup_mdio_bus(struct qca8k_priv *priv) return ret; } =20 - if (!dsa_is_user_port(priv->ds, reg)) + if (!dsa_is_user_port(priv->ds, reg) && + !(reg > 0 && reg < 6 && dsa_is_cpu_port(priv->ds, reg))) continue; =20 of_get_phy_mode(port, &mode); @@ -1095,16 +1096,23 @@ qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv) static int qca8k_find_cpu_port(struct dsa_switch *ds) { struct qca8k_priv *priv =3D ds->priv; + int port; =20 - /* Find the connected cpu port. Valid port are 0 or 6 */ if (dsa_is_cpu_port(ds, 0)) return 0; =20 - dev_dbg(priv->dev, "port 0 is not the CPU port. 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[83.233.130.25]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae6dcf0dsm197647666b.61.2026.09.23.14.59.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 14:59:18 -0700 (PDT) From: Yongzhao Chen To: netdev@vger.kernel.org Cc: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Florian Fainelli , Andrew Lunn , Vladimir Oltean , Christian Marangi , Heiner Kallweit , Russell King , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Ziyang Huang Subject: [RFC PATCH net-next v3 4/5] net: dsa: qca8k: flag QCA8337 internal CPU PHYs for SmartSpeed Date: Wed, 23 Sep 2026 23:58:56 +0200 Message-ID: <20260923215858.1653-5-yongzhao.derek@gmail.com> X-Mailer: git-send-email 2.45.2.windows.1 In-Reply-To: <20260923215858.1653-1-yongzhao.derek@gmail.com> References: <20260923215858.1653-1-yongzhao.derek@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Flag QCA8337 internal PHYs used as CPU links for SmartSpeed suppression. SmartSpeed is the Qualcomm PHY driver downshift feature configured in register 0x14. Its enable and bypass-timer bits are cleared by a subsequent patch prior to software reset. In a diagnostic boot on one RA74, PHY4 initially advertised 1000BASE-T full duplex, but a later read showed that advertisement cleared. Clearing SmartSpeed before the initial reset preserved the 1 Gb/s link on that board. This observation does not establish the root cause of the advertisement loss or prove that a delayed conduit PHY caused it. Define a shared switch-to-PHY flag while preserving the hardware revision bits consumed by the PHY driver. Mask the revision before setting the flag to prevent revision values from mistakenly enabling the quirk on user ports. Only QCA8337 internal CPU ports 1 through 5 receive this flag. The hardware test covered PHY4 on one RA74; the other ports and boards selected by this code have not been validated. Signed-off-by: Yongzhao Chen Assisted-by: LLM --- MAINTAINERS | 1 + drivers/net/dsa/qca/qca8k-8xxx.c | 19 ++++++++++--------- drivers/net/phy/qcom/qca83xx.c | 3 +-- include/linux/qca83xx.h | 11 +++++++++++ 4 files changed, 23 insertions(+), 11 deletions(-) create mode 100644 include/linux/qca83xx.h diff --git a/MAINTAINERS b/MAINTAINERS index df8ab9b82..fa1da8031 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22336,6 +22336,7 @@ L: netdev@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/net/dsa/qca8k.yaml F: drivers/net/dsa/qca/qca8k* +F: include/linux/qca83xx.h F: net/dsa/tag_qca.c =20 QUALCOMM ATHEROS QCA7K ETHERNET DRIVER diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8= xxx.c index 07640ce4a..cd7adb2d9 100644 --- a/drivers/net/dsa/qca/qca8k-8xxx.c +++ b/drivers/net/dsa/qca/qca8k-8xxx.c @@ -8,6 +8,7 @@ =20 #include #include +#include #include #include #include @@ -1754,17 +1755,17 @@ qca8k_get_ethtool_stats_eth(struct dsa_switch *ds, = int port, u64 *data) static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port) { struct qca8k_priv *priv =3D ds->priv; + u32 flags; =20 - /* Communicate to the phy internal driver the switch revision. - * Based on the switch revision different values needs to be - * set to the dbg and mmd reg on the phy. - * The first 2 bit are used to communicate the switch revision - * to the phy driver. - */ - if (port > 0 && port < 6) - return priv->switch_revision; + if (port <=3D 0 || port >=3D 6) + return 0; =20 - return 0; + /* The PHY driver uses the switch revision for analog initialization. */ + flags =3D priv->switch_revision & QCA8K_DEVFLAGS_REVISION_MASK; + if (priv->switch_id =3D=3D QCA8K_ID_QCA8337 && dsa_is_cpu_port(ds, port)) + flags |=3D QCA8K_DEVFLAGS_NO_SMARTSPEED; + + return flags; } =20 static enum dsa_tag_protocol diff --git a/drivers/net/phy/qcom/qca83xx.c b/drivers/net/phy/qcom/qca83xx.c index bc70ed8ef..0f484cdfe 100644 --- a/drivers/net/phy/qcom/qca83xx.c +++ b/drivers/net/phy/qcom/qca83xx.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ =20 #include +#include #include =20 #include "qcom.h" @@ -16,8 +17,6 @@ #define QCA8327_B_PHY_ID 0x004dd034 #define QCA8337_PHY_ID 0x004dd036 =20 -#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) - static struct at803x_hw_stat qca83xx_hw_stats[] =3D { { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, diff --git a/include/linux/qca83xx.h b/include/linux/qca83xx.h new file mode 100644 index 000000000..f90ed80fb --- /dev/null +++ b/include/linux/qca83xx.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _LINUX_QCA83XX_H +#define _LINUX_QCA83XX_H + +#include + +/* QCA8K switch-to-PHY flags, carried through phy_device::dev_flags. */ +#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) +#define QCA8K_DEVFLAGS_NO_SMARTSPEED BIT(3) + +#endif --=20 2.43.0 From nobody Thu Sep 24 14:25:43 2026 Received: from mail-ed2-f35.google.com (mail-ed2-f35.google.com [74.125.228.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6ABAA5372F3 for ; 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[83.233.130.25]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae6dcf0dsm197647666b.61.2026.09.23.14.59.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 14:59:19 -0700 (PDT) From: Yongzhao Chen To: netdev@vger.kernel.org Cc: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Florian Fainelli , Andrew Lunn , Vladimir Oltean , Christian Marangi , Heiner Kallweit , Russell King , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Ziyang Huang Subject: [RFC PATCH net-next v3 5/5] net: phy: qca83xx: disable SmartSpeed before resetting CPU PHYs Date: Wed, 23 Sep 2026 23:58:57 +0200 Message-ID: <20260923215858.1653-6-yongzhao.derek@gmail.com> X-Mailer: git-send-email 2.45.2.windows.1 In-Reply-To: <20260923215858.1653-1-yongzhao.derek@gmail.com> References: <20260923215858.1653-1-yongzhao.derek@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For flagged QCA8337 CPU PHYs, clear the SmartSpeed enable and bypass-timer bits before invoking genphy_soft_reset(). The register update preserves all other bits, and an MDIO read or write error prevents the reset. Reapply the clear prior to soft reset on system resume. Unflagged QCA8337 PHYs and QCA8327 retain their standard reset sequence. The quirk flag is set on phydev before phy_init_hw() calls soft_reset(); config_init() executes after the reset completes, and generic config_aneg() remains in use. In the RA74 diagnostic trace, generic config_aneg() preserved CTRL1000 at 0x0600 and returned success, yet a later read returned 0x0400. The trace verified that no intervening writes occurred via the instrumented Clause 22 BMCR and CTRL1000 path, though it did not isolate the precise timing or cause of the change. A read value of 0x0400 reflects the advertised capability rather than an active negotiated link speed. Disabling SmartSpeed before the initial reset maintained a 1 Gb/s internal link during the tested RA74 boot sequence. The experiment did not establish a broken pair condition or a functional fallback to 100 Mb/s. Board support for the RA74 is not included in this series. Link: https://github.com/openwrt/openwrt/issues/24696 Signed-off-by: Yongzhao Chen Assisted-by: LLM --- drivers/net/phy/qcom/qca83xx.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/qcom/qca83xx.c b/drivers/net/phy/qcom/qca83xx.c index 0f484cdfe..21ab015f6 100644 --- a/drivers/net/phy/qcom/qca83xx.c +++ b/drivers/net/phy/qcom/qca83xx.c @@ -91,6 +91,28 @@ static int qca83xx_probe(struct phy_device *phydev) return 0; } =20 +static int qca8337_disable_smartspeed(struct phy_device *phydev) +{ + if (!(phydev->dev_flags & QCA8K_DEVFLAGS_NO_SMARTSPEED)) + return 0; + + /* SmartSpeed settings take effect at software reset. */ + return phy_clear_bits(phydev, AT803X_SMART_SPEED, + AT803X_SMART_SPEED_ENABLE | + AT803X_SMART_SPEED_BYPASS_TIMER); +} + +static int qca8337_soft_reset(struct phy_device *phydev) +{ + int ret; + + ret =3D qca8337_disable_smartspeed(phydev); + if (ret) + return ret; + + return genphy_soft_reset(phydev); +} + static int qca83xx_config_init(struct phy_device *phydev) { u8 switch_revision; @@ -160,6 +182,11 @@ static int qca83xx_resume(struct phy_device *phydev) /* Reinit the port, reset values set by suspend */ qca83xx_config_init(phydev); =20 + /* Reapply the CPU PHY quirk before the resume reset. */ + ret =3D qca8337_disable_smartspeed(phydev); + if (ret) + return ret; + /* Reset the port on port resume */ phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); =20 @@ -218,7 +245,7 @@ static struct phy_driver qca83xx_driver[] =3D { .probe =3D qca83xx_probe, .flags =3D PHY_IS_INTERNAL, .config_init =3D qca83xx_config_init, - .soft_reset =3D genphy_soft_reset, + .soft_reset =3D qca8337_soft_reset, .get_sset_count =3D qca83xx_get_sset_count, .get_strings =3D qca83xx_get_strings, .get_stats =3D qca83xx_get_stats, --=20 2.43.0