From nobody Thu Sep 24 13:47:18 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C89C847012D; Wed, 23 Sep 2026 09:03:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790154198; cv=none; b=S6o/3NIGlBOW0KdTOYZeSG94kgKOhDK1Yu4nDKC22utBRKeICn8oiQZyHPJ2VErs/Cm6PB7bHxmRjL+gvJfiGsFZkcgEdYai26yEmJfF2JbVA5sBDam8IWT3oKKp9cUr9Lo7qgyrDBAAU1rt7mcvJa9YoYubBpxeRP0Oj4Tt5J8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790154198; c=relaxed/simple; bh=KNcQLxsr1Ai2oFPUKlfQXhafD0SSWQp7nUDr8E0tm9w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ek/ft7CjHkjSpPfmbKr8z1+kWHhmsdPc03lMnrzgiHdRTENNMs42dyoz9CatuJaO2IPJhEzgLF7kqbGOt/OpsV4C9C0bm+3NXopnX5w2taxjR5UuXTWd+yOs9H7y4CuHyJXqISi9/qte6fLxQKAwvxK7W5Thl5kV8fz+tnq+S60= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=Lhyi7fAs; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="Lhyi7fAs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1790154193; bh=KNcQLxsr1Ai2oFPUKlfQXhafD0SSWQp7nUDr8E0tm9w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Lhyi7fAsG/N362P5ZxbnOzO9udXgFn+n3pAyjrnkWsSTHkJiO4uKB09hSvNkN2XPU EyStei4X7rUxom2pnUVa18uASj6x1BSSf76TOpR8GvGZ7RPggk/dCqgo+asvL+ZvkN Ag8JPVQCa9EgqdUyzn6O9FX7sPtkkkL7WfIPRYc9eBi+fnkIcpezrWzhLuJ8Wm58Xj I50BVXxBUMjjBAp31M+fZxZYovgQBoDrCQ8CyDkpY7i1lv9u99G0ksG+yVJgOpO5Qn QQ//DdItY88TCdvk7MTlJhHSiSfF4T7y0dEwV/dloZMUssC5CQb3D6pPpe5+JvUo84 5KMul1LCz3TYA== Received: from benjamin-XPS-13-9310 (unknown [100.64.1.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: benjamin.gaignard) by bali.collaboradmins.com (Postfix) with ESMTPSA id 1790117E047B; Wed, 23 Sep 2026 11:03:13 +0200 (CEST) From: Benjamin Gaignard To: nicolas.dufresne@collabora.com, benjamin.gaignard@collabora.com, p.zabel@pengutronix.de, mchehab@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, Frank.Li@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH 1/2] media: verisilicon: Remove deprecated variant Date: Wed, 23 Sep 2026 11:03:06 +0200 Message-ID: <20260923090307.49959-2-benjamin.gaignard@collabora.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260923090307.49959-1-benjamin.gaignard@collabora.com> References: <20260923090307.49959-1-benjamin.gaignard@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" "nxp,imx8mq-vpu" is tagged as deprecated since: commit f3116f2e52e6 ("media: dt-bindings: media: nxp, imx8mq-vpu: Split G1 = and G2 nodes") merged since v5.17-rc1. There is more reference to it since that. Remove for driver and Documentation to clean up the code. Signed-off-by: Benjamin Gaignard --- .../bindings/media/nxp,imx8mq-vpu.yaml | 2 - .../media/platform/verisilicon/hantro_drv.c | 1 - .../media/platform/verisilicon/imx8m_vpu_hw.c | 60 ------------------- 3 files changed, 63 deletions(-) diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/= Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml index 19528262810a5..504ea45355dbc 100644 --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml @@ -15,8 +15,6 @@ description: properties: compatible: oneOf: - - const: nxp,imx8mq-vpu - deprecated: true - const: nxp,imx8mq-vpu-g1 - const: nxp,imx8mq-vpu-g2 - const: nxp,imx8mm-vpu-g1 diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/medi= a/platform/verisilicon/hantro_drv.c index ad71c0402ef3b..70de47ddb023b 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -725,7 +725,6 @@ static const struct of_device_id of_hantro_match[] =3D { #endif #ifdef CONFIG_VIDEO_HANTRO_IMX8M { .compatible =3D "nxp,imx8mm-vpu-g1", .data =3D &imx8mm_vpu_g1_variant, = }, - { .compatible =3D "nxp,imx8mq-vpu", .data =3D &imx8mq_vpu_variant, }, { .compatible =3D "nxp,imx8mq-vpu-g1", .data =3D &imx8mq_vpu_g1_variant }, { .compatible =3D "nxp,imx8mq-vpu-g2", .data =3D &imx8mq_vpu_g2_variant }, #endif diff --git a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c b/drivers/me= dia/platform/verisilicon/imx8m_vpu_hw.c index fa4224de4b996..3b63f626d33f2 100644 --- a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c +++ b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c @@ -42,38 +42,6 @@ static void imx8m_soft_reset(struct hantro_dev *vpu, u32= reset_bits) writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); } =20 -static void imx8m_clk_enable(struct hantro_dev *vpu, u32 clock_bits) -{ - u32 val; - - val =3D readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE); - val |=3D clock_bits; - writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE); -} - -static int imx8mq_runtime_resume(struct hantro_dev *vpu) -{ - int ret; - - ret =3D clk_bulk_prepare_enable(vpu->variant->num_clocks, vpu->clocks); - if (ret) { - dev_err(vpu->dev, "Failed to enable clocks\n"); - return ret; - } - - imx8m_soft_reset(vpu, RESET_G1 | RESET_G2); - imx8m_clk_enable(vpu, CLOCK_G1 | CLOCK_G2); - - /* Set values of the fuse registers */ - writel(0xffffffff, vpu->ctrl_base + CTRL_G1_DEC_FUSE); - writel(0xffffffff, vpu->ctrl_base + CTRL_G1_PP_FUSE); - writel(0xffffffff, vpu->ctrl_base + CTRL_G2_DEC_FUSE); - - clk_bulk_disable_unprepare(vpu->variant->num_clocks, vpu->clocks); - - return 0; -} - /* * Supported formats. */ @@ -234,13 +202,6 @@ static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[]= =3D { }, }; =20 -static int imx8mq_vpu_hw_init(struct hantro_dev *vpu) -{ - vpu->ctrl_base =3D vpu->reg_bases[vpu->variant->num_regs - 1]; - - return 0; -} - static void imx8m_vpu_g1_reset(struct hantro_ctx *ctx) { struct hantro_dev *vpu =3D ctx->dev; @@ -319,30 +280,9 @@ static const struct hantro_irq imx8mq_g2_irqs[] =3D { { "g2", hantro_g2_irq }, }; =20 -static const char * const imx8mq_clk_names[] =3D { "g1", "g2", "bus" }; -static const char * const imx8mq_reg_names[] =3D { "g1", "g2", "ctrl" }; static const char * const imx8mq_g1_clk_names[] =3D { "g1" }; static const char * const imx8mq_g2_clk_names[] =3D { "g2" }; =20 -const struct hantro_variant imx8mq_vpu_variant =3D { - .dec_fmts =3D imx8m_vpu_dec_fmts, - .num_dec_fmts =3D ARRAY_SIZE(imx8m_vpu_dec_fmts), - .postproc_fmts =3D imx8m_vpu_postproc_fmts, - .num_postproc_fmts =3D ARRAY_SIZE(imx8m_vpu_postproc_fmts), - .postproc_ops =3D &hantro_g1_postproc_ops, - .codec =3D HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | - HANTRO_H264_DECODER, - .codec_ops =3D imx8mq_vpu_codec_ops, - .init =3D imx8mq_vpu_hw_init, - .runtime_resume =3D imx8mq_runtime_resume, - .irqs =3D imx8mq_irqs, - .num_irqs =3D ARRAY_SIZE(imx8mq_irqs), - .clk_names =3D imx8mq_clk_names, - .num_clocks =3D ARRAY_SIZE(imx8mq_clk_names), - .reg_names =3D imx8mq_reg_names, - .num_regs =3D ARRAY_SIZE(imx8mq_reg_names) -}; - static const struct of_device_id imx8mq_vpu_shared_resources[] =3D { { .compatible =3D "nxp,imx8mq-vpu-g1", }, { .compatible =3D "nxp,imx8mq-vpu-g2", }, --=20 2.53.0 From nobody Thu Sep 24 13:47:18 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C889C46EC7C; Wed, 23 Sep 2026 09:03:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790154197; cv=none; b=KoqZsDxqYdI5JhjGEawhWHwWiGrzvkwL9kJB6T3f+wbbp79wHEk9ZK4fde6PEVluLsqwi3PuVYo8Eaagr7vDH0PQkCa3l2siCdcAm7dzfoHJsrgQiSLYgdU4RBM/NDsMxzI+S8sFeKKAil9S7Y6ioTzY+R30kIQcdYLNKC67yl4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790154197; c=relaxed/simple; bh=lwOsIlMSIMMhxLqlYday9G0StXwsB4a3fRxpMnydcCQ=; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=R1EC5uSHoYqOk5zNTXJ8bxduiHuBK+/d4+xOGnoy8giM/8T4YjSj+ZHNkRkUNC9HK ZY/QHa9itCoVDvxd5K2SDyMC6KdGDYPzb36xsj7zFtmHViX3PzTE6qUQQjeWdtxrT4 Pzc1lXa4W/7e0URmfbAmywtR/EY+pfc7zmeJy3/OmjloSxEfy1/2XbmlpXJKr2ndKl TPCFC5LvjezZc4rflRxUEQWST+dBdRhbJvCGqEjCTWUToeYABmohLg4aLudOVmuWL8 mYtQvQbT+g6uLSedXwhu2DK0iGQSJ9ao1rcjHP3QBTnzI+suSaG5zeUWmZ0CHgcgc7 1yTD4y2YzKGUw== Received: from benjamin-XPS-13-9310 (unknown [100.64.1.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: benjamin.gaignard) by bali.collaboradmins.com (Postfix) with ESMTPSA id A73CC17E09ED; Wed, 23 Sep 2026 11:03:13 +0200 (CEST) From: Benjamin Gaignard To: nicolas.dufresne@collabora.com, benjamin.gaignard@collabora.com, p.zabel@pengutronix.de, mchehab@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, Frank.Li@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH 2/2] media: verisilicon: Remove useless internal fields Date: Wed, 23 Sep 2026 11:03:07 +0200 Message-ID: <20260923090307.49959-3-benjamin.gaignard@collabora.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260923090307.49959-1-benjamin.gaignard@collabora.com> References: <20260923090307.49959-1-benjamin.gaignard@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" No more variants are using multiple registers regions. Remove the useless fields and simplify driver code. Signed-off-by: Benjamin Gaignard --- drivers/media/platform/verisilicon/hantro.h | 8 ++------ .../media/platform/verisilicon/hantro_drv.c | 20 +++++-------------- 2 files changed, 7 insertions(+), 21 deletions(-) diff --git a/drivers/media/platform/verisilicon/hantro.h b/drivers/media/pl= atform/verisilicon/hantro.h index ffc214ff3438b..fc4eb2ae01430 100644 --- a/drivers/media/platform/verisilicon/hantro.h +++ b/drivers/media/platform/verisilicon/hantro.h @@ -75,8 +75,6 @@ struct hantro_irq { * @num_irqs: number of irqs in the array * @clk_names: array of clock names * @num_clocks: number of clocks in the array - * @reg_names: array of register range names - * @num_regs: number of register range names in the array * @double_buffer: core needs double buffering * @legacy_regs: core uses legacy register set * @late_postproc: postproc must be set up at the end of the job @@ -100,8 +98,6 @@ struct hantro_variant { int num_irqs; const char * const *clk_names; int num_clocks; - const char * const *reg_names; - int num_regs; unsigned int double_buffer : 1; unsigned int legacy_regs : 1; unsigned int late_postproc : 1; @@ -187,7 +183,7 @@ hantro_vdev_to_func(struct video_device *vdev) * dev_ macros. * @clocks: Array of clock handles. * @resets: Array of reset handles. - * @reg_bases: Mapped addresses of VPU registers. + * @reg_base: Mapped address of VPU registers. * @enc_base: Mapped address of VPU encoder register for convenience. * @dec_base: Mapped address of VPU decoder register for convenience. * @ctrl_base: Mapped address of VPU control block. @@ -207,7 +203,7 @@ struct hantro_dev { struct device *dev; struct clk_bulk_data *clocks; struct reset_control *resets; - void __iomem **reg_bases; + void __iomem *reg_base; void __iomem *enc_base; void __iomem *dec_base; void __iomem *ctrl_base; diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/medi= a/platform/verisilicon/hantro_drv.c index 70de47ddb023b..f418b04279856 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -1080,7 +1080,6 @@ static int hantro_probe(struct platform_device *pdev) { const struct of_device_id *match; struct hantro_dev *vpu; - int num_bases; int i, ret; =20 vpu =3D devm_kzalloc(&pdev->dev, sizeof(*vpu), GFP_KERNEL); @@ -1137,21 +1136,12 @@ static int hantro_probe(struct platform_device *pde= v) if (IS_ERR(vpu->resets)) return PTR_ERR(vpu->resets); =20 - num_bases =3D vpu->variant->num_regs ?: 1; - vpu->reg_bases =3D devm_kcalloc(&pdev->dev, num_bases, - sizeof(*vpu->reg_bases), GFP_KERNEL); - if (!vpu->reg_bases) - return -ENOMEM; + vpu->reg_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(vpu->reg_base)) + return PTR_ERR(vpu->reg_base); =20 - for (i =3D 0; i < num_bases; i++) { - vpu->reg_bases[i] =3D vpu->variant->reg_names ? - devm_platform_ioremap_resource_byname(pdev, vpu->variant->reg_name= s[i]) : - devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(vpu->reg_bases[i])) - return PTR_ERR(vpu->reg_bases[i]); - } - vpu->enc_base =3D vpu->reg_bases[0] + vpu->variant->enc_offset; - vpu->dec_base =3D vpu->reg_bases[0] + vpu->variant->dec_offset; + vpu->enc_base =3D vpu->reg_base + vpu->variant->enc_offset; + vpu->dec_base =3D vpu->reg_base + vpu->variant->dec_offset; =20 /** * TODO: Eventually allow taking advantage of full 64-bit address space. --=20 2.53.0