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charset="utf-8" Add complete bit masks for the DesignWare RAS-DES event counter fields so consumers can use FIELD_PREP() and FIELD_MODIFY() without open-coded shifts. Keep the existing shift-based definitions for now so current users keep building until their call sites are converted. Signed-off-by: Manikanta Maddireddy --- drivers/pci/controller/dwc/pcie-designware.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 0735ae940924..c4db241547be 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -278,14 +278,17 @@ #define EVENT_COUNTER_ALL_CLEAR 0x3 #define EVENT_COUNTER_ENABLE_ALL 0x7 #define EVENT_COUNTER_ENABLE_SHIFT 2 +#define EVENT_COUNTER_ENABLE_MASK GENMASK(4, 2) #define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0) #define EVENT_COUNTER_EVENT_SEL_SHIFT 16 +#define EVENT_COUNTER_EVENT_SEL_FIELD_MASK GENMASK(23, 16) #define EVENT_COUNTER_EVENT_Tx_L0S 0x2 #define EVENT_COUNTER_EVENT_Rx_L0S 0x3 #define EVENT_COUNTER_EVENT_L1 0x5 #define EVENT_COUNTER_EVENT_L1_1 0x7 #define EVENT_COUNTER_EVENT_L1_2 0x8 #define EVENT_COUNTER_GROUP_SEL_SHIFT 24 +#define EVENT_COUNTER_GROUP_SEL_MASK GENMASK(27, 24) #define EVENT_COUNTER_GROUP_5 0x5 =20 #define PCIE_RAS_DES_EVENT_COUNTER_DATA 0xc --=20 2.34.1 From nobody Thu Sep 24 13:39:04 2026 Received: from SA9PR02CU001.outbound.protection.outlook.com (mail-southcentralusazon11013045.outbound.protection.outlook.com [40.93.196.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 433E73FF8B6; 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charset="utf-8" Several Tegra194 APPL and DesignWare register fields are programmed with open-coded shifts, which makes the register programming more verbose than necessary. Use FIELD_PREP(), FIELD_MODIFY() and FIELD_GET() at the Tegra call sites where values are shifted into fields. The LTSSM state constants are converted from pre-shifted register values to unshifted field values for FIELD_GET(). Suggested-by: Bjorn Helgaas Link: https://lore.kernel.org/r/20260515070753.3852840-2-mmaddireddy@nvidia= .com Signed-off-by: Manikanta Maddireddy --- drivers/pci/controller/dwc/pcie-tegra194.c | 145 ++++++++++----------- 1 file changed, 71 insertions(+), 74 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 63a0f56cad8e..3cfb386dd433 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -50,8 +50,7 @@ #define APPL_CTRL_SYS_PRE_DET_STATE BIT(6) #define APPL_CTRL_LTSSM_EN BIT(7) #define APPL_CTRL_HW_HOT_RST_EN BIT(20) -#define APPL_CTRL_HW_HOT_RST_MODE_MASK GENMASK(1, 0) -#define APPL_CTRL_HW_HOT_RST_MODE_SHIFT 22 +#define APPL_CTRL_HW_HOT_RST_MODE_MASK GENMASK(23, 22) #define APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST 0x1 #define APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST_LTSSM_EN 0x2 =20 @@ -136,14 +135,13 @@ =20 #define APPL_DEBUG 0xD0 #define APPL_DEBUG_PM_LINKST_IN_L2_LAT BIT(21) -#define APPL_DEBUG_PM_LINKST_IN_L0 0x11 #define APPL_DEBUG_LTSSM_STATE_MASK GENMASK(8, 3) -#define APPL_DEBUG_LTSSM_STATE_SHIFT 3 -#define LTSSM_STATE_DETECT_QUIET 0x00 -#define LTSSM_STATE_DETECT_ACT 0x08 -#define LTSSM_STATE_PRE_DETECT_QUIET 0x28 -#define LTSSM_STATE_DETECT_WAIT 0x30 -#define LTSSM_STATE_L2_IDLE 0xa8 +#define LTSSM_STATE_DETECT_QUIET 0x0 +#define LTSSM_STATE_DETECT_ACT 0x1 +#define LTSSM_STATE_PRE_DETECT_QUIET 0x5 +#define LTSSM_STATE_DETECT_WAIT 0x6 +#define LTSSM_STATE_L0 0x11 +#define LTSSM_STATE_L2_IDLE 0x15 =20 #define APPL_RADM_STATUS 0xE4 #define APPL_PM_XMT_TURNOFF_STATE BIT(0) @@ -162,7 +160,6 @@ #define APPL_CFG_MISC 0x110 #define APPL_CFG_MISC_SLV_EP_MODE BIT(14) #define APPL_CFG_MISC_ARCACHE_MASK GENMASK(13, 10) -#define APPL_CFG_MISC_ARCACHE_SHIFT 10 #define APPL_CFG_MISC_ARCACHE_VAL 3 =20 #define APPL_CFG_SLCG_OVERRIDE 0x114 @@ -178,14 +175,14 @@ #define CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE BIT(16) =20 #define CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF 0x718 -#define CFG_TIMER_CTRL_ACK_NAK_SHIFT (19) +#define CFG_TIMER_CTRL_ACK_NAK_MASK GENMASK(23, 19) +#define CFG_TIMER_CTRL_ACK_NAK_VAL 1 =20 #define N_FTS_VAL 52 #define FTS_VAL 52 =20 #define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0 -#define AMBA_ERROR_RESPONSE_RRS_SHIFT 3 -#define AMBA_ERROR_RESPONSE_RRS_MASK GENMASK(1, 0) +#define AMBA_ERROR_RESPONSE_RRS_MASK GENMASK(4, 3) #define AMBA_ERROR_RESPONSE_RRS_OKAY 0 #define AMBA_ERROR_RESPONSE_RRS_OKAY_FFFFFFFF 1 #define AMBA_ERROR_RESPONSE_RRS_OKAY_FFFF0001 2 @@ -202,7 +199,6 @@ #define CAP_SPCIE_CAP_OFF 0x154 #define CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK GENMASK(3, 0) #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK GENMASK(11, 8) -#define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT 8 =20 #define LTSSM_DELAY_US 10000 /* 10 ms */ #define LTSSM_TIMEOUT_US 120000 /* 120 ms */ @@ -348,8 +344,8 @@ static void apply_bad_link_workaround(struct dw_pcie_rp= *pp) dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); val =3D dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL2); - val &=3D ~PCI_EXP_LNKCTL2_TLS; - val |=3D PCI_EXP_LNKCTL2_TLS_2_5GT; + FIELD_MODIFY(PCI_EXP_LNKCTL2_TLS, &val, + PCI_EXP_LNKCTL2_TLS_2_5GT); dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL2, val); =20 @@ -622,10 +618,9 @@ static inline u32 event_counter_prog(struct tegra_pcie= _dw *pcie, u32 event) =20 val =3D dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap + PCIE_RAS_DES_EVENT_COUNTER_CONTROL); - val &=3D ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT); - val |=3D EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT; - val |=3D event << EVENT_COUNTER_EVENT_SEL_SHIFT; - val |=3D EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT; + FIELD_MODIFY(EVENT_COUNTER_EVENT_SEL_FIELD_MASK, &val, event); + FIELD_MODIFY(EVENT_COUNTER_GROUP_SEL_MASK, &val, EVENT_COUNTER_GROUP_5); + FIELD_MODIFY(EVENT_COUNTER_ENABLE_MASK, &val, EVENT_COUNTER_ENABLE_ALL); dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap + PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val); val =3D dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap + @@ -661,8 +656,8 @@ static int aspm_state_cnt(struct seq_file *s, void *dat= a) EVENT_COUNTER_ALL_CLEAR); =20 /* Re-enable counting */ - val =3D EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT; - val |=3D EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT; + val =3D FIELD_PREP(EVENT_COUNTER_ENABLE_MASK, EVENT_COUNTER_ENABLE_ALL); + val |=3D FIELD_PREP(EVENT_COUNTER_GROUP_SEL_MASK, EVENT_COUNTER_GROUP_5); dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap + PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val); =20 @@ -680,16 +675,15 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie) PCI_EXT_CAP_ID_VNDR); =20 /* Enable ASPM counters */ - val =3D EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT; - val |=3D EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT; + val =3D FIELD_PREP(EVENT_COUNTER_ENABLE_MASK, EVENT_COUNTER_ENABLE_ALL); + val |=3D FIELD_PREP(EVENT_COUNTER_GROUP_SEL_MASK, EVENT_COUNTER_GROUP_5); dw_pcie_writel_dbi(pci, pcie->ras_des_cap + PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val); =20 /* Program T_cmrt and T_pwr_on values */ val =3D dw_pcie_readl_dbi(pci, l1ss + PCI_L1SS_CAP); - val &=3D ~(PCI_L1SS_CAP_CM_RESTORE_TIME | PCI_L1SS_CAP_P_PWR_ON_VALUE); - val |=3D (pcie->aspm_cmrt << 8); - val |=3D (pcie->aspm_pwr_on_t << 19); + FIELD_MODIFY(PCI_L1SS_CAP_CM_RESTORE_TIME, &val, pcie->aspm_cmrt); + FIELD_MODIFY(PCI_L1SS_CAP_P_PWR_ON_VALUE, &val, pcie->aspm_pwr_on_t); dw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, val); =20 if (pcie->supports_clkreq) @@ -714,10 +708,10 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie) =20 /* Program L0s and L1 entrance latencies */ val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); - val &=3D ~PORT_AFR_L0S_ENTRANCE_LAT_MASK; - val |=3D (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); - val &=3D ~PORT_AFR_L1_ENTRANCE_LAT_MASK; - val |=3D (pcie->aspm_l1_enter_lat << PORT_AFR_L1_ENTRANCE_LAT_SHIFT); + FIELD_MODIFY(PORT_AFR_L0S_ENTRANCE_LAT_MASK, &val, + pcie->aspm_l0s_enter_lat); + FIELD_MODIFY(PORT_AFR_L1_ENTRANCE_LAT_MASK, &val, + pcie->aspm_l1_enter_lat); val |=3D PORT_AFR_ENTER_ASPM; dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); } @@ -851,22 +845,20 @@ static void config_gen3_gen4_eq_presets(struct tegra_= pcie_dw *pcie) /* Program init preset */ for (i =3D 0; i < pcie->num_lanes; i++) { val =3D dw_pcie_readw_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2)); - val &=3D ~CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK; - val |=3D GEN3_GEN4_EQ_PRESET_INIT; - val &=3D ~CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK; - val |=3D (GEN3_GEN4_EQ_PRESET_INIT << - CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT); + FIELD_MODIFY(CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK, &val, + GEN3_GEN4_EQ_PRESET_INIT); + FIELD_MODIFY(CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK, &val, + GEN3_GEN4_EQ_PRESET_INIT); dw_pcie_writew_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2), val); =20 offset =3D dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_PL_16GT) + PCI_PL_16GT_LE_CTRL; val =3D dw_pcie_readb_dbi(pci, offset + i); - val &=3D ~PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK; - val |=3D GEN3_GEN4_EQ_PRESET_INIT; - val &=3D ~PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK; - val |=3D (GEN3_GEN4_EQ_PRESET_INIT << - PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT); + FIELD_MODIFY(PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK, &val, + GEN3_GEN4_EQ_PRESET_INIT); + FIELD_MODIFY(PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK, &val, + GEN3_GEN4_EQ_PRESET_INIT); dw_pcie_writeb_dbi(pci, offset + i, val); } =20 @@ -880,8 +872,7 @@ static void config_gen3_gen4_eq_presets(struct tegra_pc= ie_dw *pcie) dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); =20 val =3D dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &=3D ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; - val |=3D (0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT); + FIELD_MODIFY(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, &val, 0x1); dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); =20 val =3D dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); @@ -921,9 +912,8 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *p= p) =20 /* Enable as 0xFFFF0001 response for RRS */ val =3D dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT); - val &=3D ~(AMBA_ERROR_RESPONSE_RRS_MASK << AMBA_ERROR_RESPONSE_RRS_SHIFT); - val |=3D (AMBA_ERROR_RESPONSE_RRS_OKAY_FFFF0001 << - AMBA_ERROR_RESPONSE_RRS_SHIFT); + FIELD_MODIFY(AMBA_ERROR_RESPONSE_RRS_MASK, &val, + AMBA_ERROR_RESPONSE_RRS_OKAY_FFFF0001); dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val); =20 /* Clear Slot Clock Configuration bit if SRNS configuration */ @@ -947,7 +937,8 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *p= p) =20 if (pcie->update_fc_fixup) { val =3D dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); - val |=3D 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; + FIELD_MODIFY(CFG_TIMER_CTRL_ACK_NAK_MASK, &val, + CFG_TIMER_CTRL_ACK_NAK_VAL); dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val); } =20 @@ -1002,11 +993,10 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *= pci) * link up once again with DLF disabled. */ val =3D appl_readl(pcie, APPL_DEBUG); - val &=3D APPL_DEBUG_LTSSM_STATE_MASK; - val >>=3D APPL_DEBUG_LTSSM_STATE_SHIFT; + val =3D FIELD_GET(APPL_DEBUG_LTSSM_STATE_MASK, val); tmp =3D appl_readl(pcie, APPL_LINK_STATUS); tmp &=3D APPL_LINK_STATUS_RDLH_LINK_UP; - if (!(val =3D=3D 0x11 && !tmp)) { + if (!(val =3D=3D LTSSM_STATE_L0 && !tmp)) { /* Link is down for all good reasons */ return 0; } @@ -1419,10 +1409,8 @@ static int tegra_pcie_config_controller(struct tegra= _pcie_dw *pcie, if (en_hw_hot_rst || pcie->of_data->has_sbr_reset_fix) { /* Enable HW_HOT_RST mode */ val =3D appl_readl(pcie, APPL_CTRL); - val &=3D ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << - APPL_CTRL_HW_HOT_RST_MODE_SHIFT); - val |=3D (APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST_LTSSM_EN << - APPL_CTRL_HW_HOT_RST_MODE_SHIFT); + FIELD_MODIFY(APPL_CTRL_HW_HOT_RST_MODE_MASK, &val, + APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST_LTSSM_EN); val |=3D APPL_CTRL_HW_HOT_RST_EN; appl_writel(pcie, val, APPL_CTRL); } @@ -1446,7 +1434,8 @@ static int tegra_pcie_config_controller(struct tegra_= pcie_dw *pcie, appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL); =20 val =3D appl_readl(pcie, APPL_CFG_MISC); - val |=3D (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT); + FIELD_MODIFY(APPL_CFG_MISC_ARCACHE_MASK, &val, + APPL_CFG_MISC_ARCACHE_VAL); appl_writel(pcie, val, APPL_CFG_MISC); =20 if (pcie->enable_srns || pcie->enable_ext_refclk) { @@ -1605,10 +1594,14 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_= pcie_dw *pcie) appl_writel(pcie, data, APPL_PINMUX); =20 err =3D readl_poll_timeout(pcie->appl_base + APPL_DEBUG, data, - ((data & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_DETECT_QUIET) = || - ((data & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_DETECT_ACT) || - ((data & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_PRE_DETECT_QUI= ET) || - ((data & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_DETECT_WAIT), + (FIELD_GET(APPL_DEBUG_LTSSM_STATE_MASK, data) =3D=3D + LTSSM_STATE_DETECT_QUIET) || + (FIELD_GET(APPL_DEBUG_LTSSM_STATE_MASK, data) =3D=3D + LTSSM_STATE_DETECT_ACT) || + (FIELD_GET(APPL_DEBUG_LTSSM_STATE_MASK, data) =3D=3D + LTSSM_STATE_PRE_DETECT_QUIET) || + (FIELD_GET(APPL_DEBUG_LTSSM_STATE_MASK, data) =3D=3D + LTSSM_STATE_DETECT_WAIT), LTSSM_DELAY_US, LTSSM_TIMEOUT_US); if (err) dev_info(pcie->dev, "LTSSM state: 0x%x detect timeout: %d\n", data, err= ); @@ -1694,11 +1687,16 @@ static void pex_ep_event_pex_rst_assert(struct tegr= a_pcie_dw *pcie) return; =20 ret =3D readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, - ((val & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_DETECT_QUIET) || - ((val & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_DETECT_ACT) || - ((val & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_PRE_DETECT_QUIET= ) || - ((val & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_DETECT_WAIT) || - ((val & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_L2_IDLE), + (FIELD_GET(APPL_DEBUG_LTSSM_STATE_MASK, val) =3D=3D + LTSSM_STATE_DETECT_QUIET) || + (FIELD_GET(APPL_DEBUG_LTSSM_STATE_MASK, val) =3D=3D + LTSSM_STATE_DETECT_ACT) || + (FIELD_GET(APPL_DEBUG_LTSSM_STATE_MASK, val) =3D=3D + LTSSM_STATE_PRE_DETECT_QUIET) || + (FIELD_GET(APPL_DEBUG_LTSSM_STATE_MASK, val) =3D=3D + LTSSM_STATE_DETECT_WAIT) || + (FIELD_GET(APPL_DEBUG_LTSSM_STATE_MASK, val) =3D=3D + LTSSM_STATE_L2_IDLE), LTSSM_DELAY_US, LTSSM_TIMEOUT_US); if (ret) dev_info(pcie->dev, "LTSSM state: 0x%x detect timeout: %d\n", val, ret); @@ -1817,13 +1815,14 @@ static void pex_ep_event_pex_rst_deassert(struct te= gra_pcie_dw *pcie) val =3D appl_readl(pcie, APPL_CTRL); val |=3D APPL_CTRL_SYS_PRE_DET_STATE; val |=3D APPL_CTRL_HW_HOT_RST_EN; - val &=3D ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << APPL_CTRL_HW_HOT_RST_MODE_SH= IFT); - val |=3D (APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST_LTSSM_EN << APPL_CTRL_HW_HOT= _RST_MODE_SHIFT); + FIELD_MODIFY(APPL_CTRL_HW_HOT_RST_MODE_MASK, &val, + APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST_LTSSM_EN); appl_writel(pcie, val, APPL_CTRL); =20 val =3D appl_readl(pcie, APPL_CFG_MISC); val |=3D APPL_CFG_MISC_SLV_EP_MODE; - val |=3D (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT); + FIELD_MODIFY(APPL_CFG_MISC_ARCACHE_MASK, &val, + APPL_CFG_MISC_ARCACHE_VAL); appl_writel(pcie, val, APPL_CFG_MISC); =20 val =3D appl_readl(pcie, APPL_PINMUX); @@ -1875,7 +1874,8 @@ static void pex_ep_event_pex_rst_deassert(struct tegr= a_pcie_dw *pcie) =20 if (pcie->update_fc_fixup) { val =3D dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); - val |=3D 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; + FIELD_MODIFY(CFG_TIMER_CTRL_ACK_NAK_MASK, &val, + CFG_TIMER_CTRL_ACK_NAK_VAL); dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val); } =20 @@ -2390,8 +2390,7 @@ static int tegra_pcie_dw_suspend_late(struct device *= dev) /* Enable HW_HOT_RST mode */ if (!pcie->of_data->has_sbr_reset_fix) { val =3D appl_readl(pcie, APPL_CTRL); - val &=3D ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << - APPL_CTRL_HW_HOT_RST_MODE_SHIFT); + FIELD_MODIFY(APPL_CTRL_HW_HOT_RST_MODE_MASK, &val, 0); val |=3D APPL_CTRL_HW_HOT_RST_EN; appl_writel(pcie, val, APPL_CTRL); } @@ -2466,10 +2465,8 @@ static int tegra_pcie_dw_resume_early(struct device = *dev) /* Disable HW_HOT_RST mode */ if (!pcie->of_data->has_sbr_reset_fix) { val =3D appl_readl(pcie, APPL_CTRL); - val &=3D ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << - APPL_CTRL_HW_HOT_RST_MODE_SHIFT); - val |=3D APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST << - APPL_CTRL_HW_HOT_RST_MODE_SHIFT; + FIELD_MODIFY(APPL_CTRL_HW_HOT_RST_MODE_MASK, &val, + APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST); 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charset="utf-8" Tegra no longer uses the DesignWare field shift macros after converting the call sites to FIELD_PREP() and FIELD_MODIFY(). Remove the unused shift macros and the old narrow event-selector mask. Add the complete event-selector field with the standard mask name, and keep a temporary alias so existing users keep building until they are converted. Signed-off-by: Manikanta Maddireddy --- drivers/pci/controller/dwc/pcie-designware.h | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index c4db241547be..f70b7da97e07 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -82,9 +82,7 @@ #define PORT_AFR_CC_N_FTS_MASK GENMASK(23, 16) #define PORT_AFR_CC_N_FTS(n) FIELD_PREP(PORT_AFR_CC_N_FTS_MASK, n) #define PORT_AFR_ENTER_ASPM BIT(30) -#define PORT_AFR_L0S_ENTRANCE_LAT_SHIFT 24 #define PORT_AFR_L0S_ENTRANCE_LAT_MASK GENMASK(26, 24) -#define PORT_AFR_L1_ENTRANCE_LAT_SHIFT 27 #define PORT_AFR_L1_ENTRANCE_LAT_MASK GENMASK(29, 27) =20 #define PCIE_PORT_LINK_CONTROL 0x710 @@ -151,7 +149,6 @@ #define GEN3_RELATED_OFF_EQ_PHASE_2_3 BIT(9) #define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13) #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) -#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) =20 #define GEN3_EQ_CONTROL_OFF 0x8A8 @@ -277,17 +274,14 @@ #define PCIE_RAS_DES_EVENT_COUNTER_CONTROL 0x8 #define EVENT_COUNTER_ALL_CLEAR 0x3 #define EVENT_COUNTER_ENABLE_ALL 0x7 -#define EVENT_COUNTER_ENABLE_SHIFT 2 #define EVENT_COUNTER_ENABLE_MASK GENMASK(4, 2) -#define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0) -#define EVENT_COUNTER_EVENT_SEL_SHIFT 16 -#define EVENT_COUNTER_EVENT_SEL_FIELD_MASK GENMASK(23, 16) +#define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(23, 16) +#define EVENT_COUNTER_EVENT_SEL_FIELD_MASK EVENT_COUNTER_EVENT_SEL_MASK #define EVENT_COUNTER_EVENT_Tx_L0S 0x2 #define EVENT_COUNTER_EVENT_Rx_L0S 0x3 #define EVENT_COUNTER_EVENT_L1 0x5 #define EVENT_COUNTER_EVENT_L1_1 0x7 #define EVENT_COUNTER_EVENT_L1_2 0x8 -#define EVENT_COUNTER_GROUP_SEL_SHIFT 24 #define EVENT_COUNTER_GROUP_SEL_MASK GENMASK(27, 24) #define EVENT_COUNTER_GROUP_5 0x5 =20 --=20 2.34.1 From nobody Thu Sep 24 13:39:04 2026 Received: from SA9PR02CU001.outbound.protection.outlook.com (mail-southcentralusazon11013071.outbound.protection.outlook.com [40.93.196.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4E5E331EB7; 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charset="utf-8" Use the common DesignWare EVENT_COUNTER_EVENT_SEL_MASK name after the complete RAS-DES event selector field mask has replaced the old narrow value mask. Signed-off-by: Manikanta Maddireddy --- drivers/pci/controller/dwc/pcie-tegra194.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 3cfb386dd433..2462da8664e0 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -618,7 +618,7 @@ static inline u32 event_counter_prog(struct tegra_pcie_= dw *pcie, u32 event) =20 val =3D dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap + PCIE_RAS_DES_EVENT_COUNTER_CONTROL); - FIELD_MODIFY(EVENT_COUNTER_EVENT_SEL_FIELD_MASK, &val, event); + FIELD_MODIFY(EVENT_COUNTER_EVENT_SEL_MASK, &val, event); FIELD_MODIFY(EVENT_COUNTER_GROUP_SEL_MASK, &val, EVENT_COUNTER_GROUP_5); FIELD_MODIFY(EVENT_COUNTER_ENABLE_MASK, &val, EVENT_COUNTER_ENABLE_ALL); dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap + --=20 2.34.1 From nobody Thu Sep 24 13:39:04 2026 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012050.outbound.protection.outlook.com [40.93.195.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8A3D3E9C2B; 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charset="utf-8" Use the shared DesignWare RAS-DES event counter register offsets and field masks in the common debugfs code instead of carrying duplicate private definitions. Signed-off-by: Manikanta Maddireddy --- .../controller/dwc/pcie-designware-debugfs.c | 56 +++++++++++-------- drivers/pci/controller/dwc/pcie-designware.h | 1 - 2 files changed, 32 insertions(+), 25 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.c b/drivers= /pci/controller/dwc/pcie-designware-debugfs.c index be0b84665c9e..daabc6ff0d85 100644 --- a/drivers/pci/controller/dwc/pcie-designware-debugfs.c +++ b/drivers/pci/controller/dwc/pcie-designware-debugfs.c @@ -31,14 +31,8 @@ =20 #define ERR_INJ_ENABLE_REG 0x30 =20 -#define RAS_DES_EVENT_COUNTER_DATA_REG 0xc - -#define RAS_DES_EVENT_COUNTER_CTRL_REG 0x8 -#define EVENT_COUNTER_GROUP_SELECT GENMASK(27, 24) -#define EVENT_COUNTER_EVENT_SELECT GENMASK(23, 16) #define EVENT_COUNTER_LANE_SELECT GENMASK(11, 8) #define EVENT_COUNTER_STATUS BIT(7) -#define EVENT_COUNTER_ENABLE GENMASK(4, 2) #define PER_EVENT_ON 0x3 #define PER_EVENT_OFF 0x1 =20 @@ -356,11 +350,15 @@ static void set_event_number(struct dwc_pcie_rasdes_p= riv *pdata, { u32 val; =20 - val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUN= TER_CTRL_REG); - val &=3D ~EVENT_COUNTER_ENABLE; - FIELD_MODIFY(EVENT_COUNTER_GROUP_SELECT, &val, event_list[pdata->idx].gro= up_no); - FIELD_MODIFY(EVENT_COUNTER_EVENT_SELECT, &val, event_list[pdata->idx].eve= nt_no); - dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTR= L_REG, val); + val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + + PCIE_RAS_DES_EVENT_COUNTER_CONTROL); + val &=3D ~EVENT_COUNTER_ENABLE_MASK; + FIELD_MODIFY(EVENT_COUNTER_GROUP_SEL_MASK, &val, + event_list[pdata->idx].group_no); + FIELD_MODIFY(EVENT_COUNTER_EVENT_SEL_MASK, &val, + event_list[pdata->idx].event_no); + dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + + PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val); } =20 static ssize_t counter_enable_read(struct file *file, char __user *buf, @@ -375,13 +373,16 @@ static ssize_t counter_enable_read(struct file *file,= char __user *buf, =20 mutex_lock(&rinfo->reg_event_lock); set_event_number(pdata, pci, rinfo); - val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUN= TER_CTRL_REG); + val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + + PCIE_RAS_DES_EVENT_COUNTER_CONTROL); mutex_unlock(&rinfo->reg_event_lock); val =3D FIELD_GET(EVENT_COUNTER_STATUS, val); if (val) - pos =3D scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter Enabled\n"); + pos =3D scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, + "Counter Enabled\n"); else - pos =3D scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter Disabled\n"= ); + pos =3D scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, + "Counter Disabled\n"); =20 return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos); } @@ -401,13 +402,15 @@ static ssize_t counter_enable_write(struct file *file= , const char __user *buf, =20 mutex_lock(&rinfo->reg_event_lock); set_event_number(pdata, pci, rinfo); - val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUN= TER_CTRL_REG); + val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + + PCIE_RAS_DES_EVENT_COUNTER_CONTROL); if (enable) - val |=3D FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_ON); + val |=3D FIELD_PREP(EVENT_COUNTER_ENABLE_MASK, PER_EVENT_ON); else - val |=3D FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_OFF); + val |=3D FIELD_PREP(EVENT_COUNTER_ENABLE_MASK, PER_EVENT_OFF); =20 - dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTR= L_REG, val); + dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + + PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val); =20 /* * While enabling the counter, always read the status back to check if @@ -416,7 +419,7 @@ static ssize_t counter_enable_write(struct file *file, = const char __user *buf, */ if (enable) { val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + - RAS_DES_EVENT_COUNTER_CTRL_REG); + PCIE_RAS_DES_EVENT_COUNTER_CONTROL); if (!FIELD_GET(EVENT_COUNTER_STATUS, val)) { mutex_unlock(&rinfo->reg_event_lock); return -EOPNOTSUPP; @@ -440,7 +443,8 @@ static ssize_t counter_lane_read(struct file *file, cha= r __user *buf, =20 mutex_lock(&rinfo->reg_event_lock); set_event_number(pdata, pci, rinfo); - val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUN= TER_CTRL_REG); + val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + + PCIE_RAS_DES_EVENT_COUNTER_CONTROL); mutex_unlock(&rinfo->reg_event_lock); val =3D FIELD_GET(EVENT_COUNTER_LANE_SELECT, val); pos =3D scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Lane: %d\n", val); @@ -463,9 +467,11 @@ static ssize_t counter_lane_write(struct file *file, c= onst char __user *buf, =20 mutex_lock(&rinfo->reg_event_lock); set_event_number(pdata, pci, rinfo); - val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUN= TER_CTRL_REG); + val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + + PCIE_RAS_DES_EVENT_COUNTER_CONTROL); FIELD_MODIFY(EVENT_COUNTER_LANE_SELECT, &val, lane); - dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTR= L_REG, val); + dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + + PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val); mutex_unlock(&rinfo->reg_event_lock); =20 return count; @@ -483,9 +489,11 @@ static ssize_t counter_value_read(struct file *file, c= har __user *buf, =20 mutex_lock(&rinfo->reg_event_lock); set_event_number(pdata, pci, rinfo); - val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUN= TER_DATA_REG); + val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + + PCIE_RAS_DES_EVENT_COUNTER_DATA); mutex_unlock(&rinfo->reg_event_lock); - pos =3D scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter value: %d\n"= , val); + pos =3D scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, + "Counter value: %d\n", val); =20 return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index f70b7da97e07..4d55339750f0 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -276,7 +276,6 @@ #define EVENT_COUNTER_ENABLE_ALL 0x7 #define EVENT_COUNTER_ENABLE_MASK GENMASK(4, 2) #define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(23, 16) -#define EVENT_COUNTER_EVENT_SEL_FIELD_MASK EVENT_COUNTER_EVENT_SEL_MASK #define EVENT_COUNTER_EVENT_Tx_L0S 0x2 #define EVENT_COUNTER_EVENT_Rx_L0S 0x3 #define EVENT_COUNTER_EVENT_L1 0x5 --=20 2.34.1