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(unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id D8B4D3F7077; Tue, 22 Sep 2026 20:49:05 -0700 (PDT) From: Ratheesh Kannoth To: , CC: , , , , , , Suman Ghosh , Ratheesh Kannoth Subject: [PATCH v2 net-next] octeontx2-af: add tracepoints for NPC MCAM entry programming Date: Wed, 23 Sep 2026 09:18:58 +0530 Message-ID: <20260923034858.1764461-1-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 7vEq0x9wMlo5xbd8sVfg0h9KNLGb9KSD X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIzMDAxNCBTYWx0ZWRfX/Rfn9zxlMJox O8yHA53AlAJ+2qujScurL9LPlmzbjRTwXuQCxgExDQvsYQYhvA61Oz+6VRwCs12DxRNFDuhEFXO 5ZKXDpC2usm9HJVb54viNQJxwSqwOGI= X-Authority-Analysis: v=2.4 cv=b/UncdGx c=1 sm=1 tr=0 ts=6ab34c3c cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=VdqzKS8jKosA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=qit2iCtTFQkLgVSMPQTB:22 a=VwQbUJbxAAAA:8 a=M5GUcnROAAAA:8 a=GYVh84BQpdABKaSdmJcA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIzMDAxNCBTYWx0ZWRfX5CRZpxZ5EOi6 A9hgy9OgG6tmT8NUfiX1LPeDorYSS2zzypbAaYbNQO75S/qDUiQ4KABf64te4oCAofaw2kcg2Fw IBxEnKRiz/EzlAn1f7W3VFEQryvjtdaSg/3hvM35EYAzCs9ql130RwFoYxYJyN60YScGJ7Hf4Lo 5iIvH0pR8z+5/2p4Oowi8inWfcRO+K0EbZdp0BJvOIk9SPePhKvL4lhcLRKCZnjlghy8Wno9TYZ /ntVNyl+M0lD6jy90hM6/LNGahd3m7vgtzTboT6R+OcZOicjTQIjSotG+F5eZWfbXdW2MkB7TAC sHPG3YOKK4hZTL9uWhnFW1X1YkS8oCM3R9CqQAzJr+Tm8CXQDmGzzAa1HAs9t21Vvd0pYEcXWjQ JNuyMCGPl0F1OZmmj/ZfRQc4CIR6k5HHESQlHdZKqj7LDGzpIWsd2DY7HSmTvwah7FsiCmNs7n/ j1kn75yghEPvlxSGppw== X-Proofpoint-GUID: 7vEq0x9wMlo5xbd8sVfg0h9KNLGb9KSD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-23_02,2026-09-21_02,2025-10-01_01 Content-Type: text/plain; charset="utf-8" From: Suman Ghosh Add ftrace events for MCAM allocation, CAM keyword writes, action/tag programming, enable/disable, and entry copies. Emit them from the legacy and CN20K NPC alloc, config, read, and shift paths so mailbox-driven rule changes can be correlated with the programmed MCAM state. --- v1 -> v2: Addressed sashiko comments. - Assign pcifunc in otx2_npc_mcam_alloc_entries() and print it as 0x%x; record start_mcam_idx from rsp->entry_list[0] for non-contiguous allocations. - Pass absolute actindex to cam/action traces and mask tx_intf to 0x1 on TX interfaces so emitters agree on mcam_index and tx_intf semantics. - Add otx2_npc_mcam_copy and emit it from npc_copy_mcam_entry() to cover MCAM entry shifts; emit cam/action traces from the CN20K config path. - Drop redundant TP_printk newlines; zero npc_mcam_alloc_entry_req on stack in alloc-and-write mailbox handlers before tracing kw_type/virt. https://lore.kernel.org/netdev/20260915025014.928685-1-rkannoth@marvell.co= m/ Signed-off-by: Suman Ghosh Signed-off-by: Ratheesh Kannoth --- .../ethernet/marvell/octeontx2/af/cn20k/npc.c | 51 +++++--- .../ethernet/marvell/octeontx2/af/rvu_npc.c | 69 +++++++---- .../ethernet/marvell/octeontx2/af/rvu_trace.c | 5 + .../ethernet/marvell/octeontx2/af/rvu_trace.h | 114 ++++++++++++++++++ 4 files changed, 196 insertions(+), 43 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/npc.c index 7c829b1da3e5..0b485728f399 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c @@ -15,6 +15,7 @@ #include "cn20k/npc.h" #include "cn20k/reg.h" #include "rvu_npc_fs.h" +#include =20 static struct npc_priv_t *npc_priv; =20 @@ -973,13 +974,15 @@ static void npc_cn20k_config_kw_x2(struct rvu *rvu, s= truct npc_mcam *mcam, int blkaddr, int index, u8 intf, struct cn20k_mcam_entry *entry, int bank, u8 kw_type, int kw, - u8 req_kw_type) + u8 req_kw_type, u16 actindex) { + u64 w0_cam0, w0_cam1, w1_cam0, w1_cam1; + u64 w2_cam0, w2_cam1, w3_cam0, w3_cam1; u64 intf_ext =3D 0, intf_ext_mask =3D 0; u8 tx_intf_mask =3D ~intf & 0x3; u8 tx_intf =3D intf, kex_type; u8 kw_type_mask =3D ~kw_type; - u64 cam0, cam1, kex_cfg; + u64 kex_cfg; =20 if (is_npc_intf_tx(intf)) { /* Last bit must be set and rest don't care @@ -1018,43 +1021,46 @@ static void npc_cn20k_config_kw_x2(struct rvu *rvu,= struct npc_mcam *mcam, intf_ext_mask); =20 /* Set the match key */ - npc_cn20k_get_keyword(entry, kw, &cam0, &cam1); + npc_cn20k_get_keyword(entry, kw, &w0_cam0, &w0_cam1); rvu_write64(rvu, blkaddr, NPC_AF_CN20K_MCAMEX_BANKX_CAMX_W0_EXT(index, bank, 1), - cam1); + w0_cam1); rvu_write64(rvu, blkaddr, NPC_AF_CN20K_MCAMEX_BANKX_CAMX_W0_EXT(index, bank, 0), - cam0); + w0_cam0); =20 - npc_cn20k_get_keyword(entry, kw + 1, &cam0, &cam1); + npc_cn20k_get_keyword(entry, kw + 1, &w1_cam0, &w1_cam1); rvu_write64(rvu, blkaddr, NPC_AF_CN20K_MCAMEX_BANKX_CAMX_W1_EXT(index, bank, 1), - cam1); + w1_cam1); rvu_write64(rvu, blkaddr, NPC_AF_CN20K_MCAMEX_BANKX_CAMX_W1_EXT(index, bank, 0), - cam0); + w1_cam0); =20 - npc_cn20k_get_keyword(entry, kw + 2, &cam0, &cam1); + npc_cn20k_get_keyword(entry, kw + 2, &w2_cam0, &w2_cam1); rvu_write64(rvu, blkaddr, NPC_AF_CN20K_MCAMEX_BANKX_CAMX_W2_EXT(index, bank, 1), - cam1); + w2_cam1); rvu_write64(rvu, blkaddr, NPC_AF_CN20K_MCAMEX_BANKX_CAMX_W2_EXT(index, bank, 0), - cam0); + w2_cam0); =20 - npc_cn20k_get_keyword(entry, kw + 3, &cam0, &cam1); + npc_cn20k_get_keyword(entry, kw + 3, &w3_cam0, &w3_cam1); rvu_write64(rvu, blkaddr, NPC_AF_CN20K_MCAMEX_BANKX_CAMX_W3_EXT(index, bank, 1), - cam1); + w3_cam1); rvu_write64(rvu, blkaddr, NPC_AF_CN20K_MCAMEX_BANKX_CAMX_W3_EXT(index, bank, 0), - cam0); + w3_cam0); + + trace_otx2_npc_cam(actindex, bank, w0_cam0, w0_cam1, w1_cam0, w1_cam1); + trace_otx2_npc_cam(actindex, bank, w2_cam0, w2_cam1, w3_cam0, w3_cam1); } =20 static void npc_cn20k_config_kw_x4(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr, int index, u8 intf, struct cn20k_mcam_entry *entry, - u8 kw_type, u8 req_kw_type) + u8 kw_type, u8 req_kw_type, u16 actindex) { int kw =3D 0, bank; =20 @@ -1062,7 +1068,7 @@ static void npc_cn20k_config_kw_x4(struct rvu *rvu, s= truct npc_mcam *mcam, npc_cn20k_config_kw_x2(rvu, mcam, blkaddr, index, intf, entry, bank, kw_type, - kw, req_kw_type); + kw, req_kw_type, actindex); } =20 int npc_cn20k_config_mcam_entry(struct rvu *rvu, int blkaddr, int index, @@ -1071,10 +1077,11 @@ int npc_cn20k_config_mcam_entry(struct rvu *rvu, in= t blkaddr, int index, { struct npc_mcam *mcam =3D &rvu->hw->mcam; int mcam_idx =3D index % mcam->banksize; + int actbank =3D npc_get_bank(mcam, index); int bank =3D index / mcam->banksize; u64 bank_cfg =3D (u64)hw_prio << 24; + u8 kw_type, tx_intf =3D intf; int kw =3D 0; - u8 kw_type; =20 if (index < 0 || index >=3D mcam->total_entries) return -EINVAL; @@ -1097,7 +1104,7 @@ int npc_cn20k_config_mcam_entry(struct rvu *rvu, int = blkaddr, int index, npc_clear_x2_entry(rvu, blkaddr, bank, mcam_idx); npc_cn20k_config_kw_x2(rvu, mcam, blkaddr, mcam_idx, intf, entry, - bank, kw_type, kw, req_kw_type); + bank, kw_type, kw, req_kw_type, index); /* Set 'action' */ rvu_write64(rvu, blkaddr, NPC_AF_CN20K_MCAMEX_BANKX_ACTIONX_EXT(mcam_idx, @@ -1128,7 +1135,7 @@ int npc_cn20k_config_mcam_entry(struct rvu *rvu, int = blkaddr, int index, =20 npc_cn20k_config_kw_x4(rvu, mcam, blkaddr, mcam_idx, intf, entry, - kw_type, req_kw_type); + kw_type, req_kw_type, index); for (bank =3D 0; bank < mcam->banks_per_entry; bank++) { /* Set 'action' */ rvu_write64(rvu, blkaddr, @@ -1157,6 +1164,10 @@ int npc_cn20k_config_mcam_entry(struct rvu *rvu, int= blkaddr, int index, =20 /* TODO: */ /* PF installing VF rule */ + if (is_npc_intf_tx(intf)) + tx_intf &=3D 0x1; + trace_otx2_npc_action(index, actbank, tx_intf, (u8)enable, + entry->action, entry->vtag_action); if (npc_cn20k_enable_mcam_entry(rvu, blkaddr, index, enable)) return -EINVAL; =20 @@ -1434,7 +1445,7 @@ int rvu_mbox_handler_npc_cn20k_mcam_alloc_and_write_e= ntry(struct rvu *rvu, { struct rvu_pfvf *pfvf =3D rvu_get_pfvf(rvu, req->hdr.pcifunc); struct npc_mcam_free_entry_req free_req =3D { 0 }; - struct npc_mcam_alloc_entry_req entry_req; + struct npc_mcam_alloc_entry_req entry_req =3D { 0 }; struct npc_mcam_alloc_entry_rsp entry_rsp; struct npc_mcam *mcam =3D &rvu->hw->mcam; u16 entry =3D NPC_MCAM_ENTRY_INVALID; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_npc.c index 42a601976db3..fe8625ee4051 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c @@ -20,6 +20,7 @@ #include "rvu_npc.h" #include "cn20k/reg.h" #include "lmac_common.h" +#include =20 #define RSVD_MCAM_ENTRIES_PER_PF 3 /* Broadcast, Promisc and AllMulticast = */ #define RSVD_MCAM_ENTRIES_PER_NIXLF 1 /* Ucast for LFs */ @@ -259,6 +260,7 @@ void npc_enable_mcam_entry(struct rvu *rvu, struct npc_= mcam *mcam, int bank =3D npc_get_bank(mcam, index); int actbank =3D bank; =20 + trace_otx2_npc_enable_mcam_entry(index, (u8)enable); if (is_cn20k(rvu->pdev)) { if (npc_cn20k_enable_mcam_entry(rvu, blkaddr, index, enable)) dev_err(rvu->dev, "Error to %s mcam %u entry\n", @@ -521,10 +523,10 @@ static void npc_config_mcam_entry(struct rvu *rvu, st= ruct npc_mcam *mcam, struct mcam_entry *entry, bool enable) { int bank =3D npc_get_bank(mcam, index); + u64 w0_cam0, w0_cam1, w1_cam0, w1_cam1; int kw =3D 0, actbank, actindex; u8 tx_intf_mask =3D ~intf & 0x3; u8 tx_intf =3D intf; - u64 cam0, cam1; =20 actbank =3D bank; /* Save bank id, to set action later on */ actindex =3D index; @@ -561,17 +563,18 @@ static void npc_config_mcam_entry(struct rvu *rvu, st= ruct npc_mcam *mcam, tx_intf_mask); =20 /* Set the match key */ - npc_get_keyword(entry, kw, &cam0, &cam1); + npc_get_keyword(entry, kw, &w0_cam0, &w0_cam1); rvu_write64(rvu, blkaddr, - NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), cam1); + NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), w0_cam1); rvu_write64(rvu, blkaddr, - NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), cam0); + NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), w0_cam0); =20 - npc_get_keyword(entry, kw + 1, &cam0, &cam1); + npc_get_keyword(entry, kw + 1, &w1_cam0, &w1_cam1); rvu_write64(rvu, blkaddr, - NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), cam1); + NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), w1_cam1); rvu_write64(rvu, blkaddr, - NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), cam0); + NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), w1_cam0); + trace_otx2_npc_cam(actindex, bank, w0_cam0, w0_cam1, w1_cam0, w1_cam1); } =20 /* PF installing VF rule */ @@ -586,6 +589,10 @@ static void npc_config_mcam_entry(struct rvu *rvu, str= uct npc_mcam *mcam, rvu_write64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_TAG_ACT(index, actbank), entry->vtag_action); =20 + if (is_npc_intf_tx(intf)) + tx_intf &=3D 0x1; + trace_otx2_npc_action(actindex, actbank, tx_intf, (u8)enable, + entry->action, entry->vtag_action); /* Enable the entry */ if (enable) npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, true); @@ -596,24 +603,27 @@ void npc_read_mcam_entry(struct rvu *rvu, struct npc_= mcam *mcam, struct mcam_entry *entry, u8 *intf, u8 *ena) { int sbank =3D npc_get_bank(mcam, src); + u64 w0_cam0, w0_cam1, w1_cam0, w1_cam1; + u16 actindex =3D src; + u8 tx_intf; int bank, kw =3D 0; - u64 cam0, cam1; =20 src &=3D (mcam->banksize - 1); bank =3D sbank; =20 for (; bank < (sbank + mcam->banks_per_entry); bank++, kw =3D kw + 2) { - cam1 =3D rvu_read64(rvu, blkaddr, - NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 1)); - cam0 =3D rvu_read64(rvu, blkaddr, - NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 0)); - npc_fill_entryword(entry, kw, cam0, cam1); + w0_cam1 =3D rvu_read64(rvu, blkaddr, + NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 1)); + w0_cam0 =3D rvu_read64(rvu, blkaddr, + NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 0)); + npc_fill_entryword(entry, kw, w0_cam0, w0_cam1); =20 - cam1 =3D rvu_read64(rvu, blkaddr, - NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 1)); - cam0 =3D rvu_read64(rvu, blkaddr, - NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 0)); - npc_fill_entryword(entry, kw + 1, cam0, cam1); + w1_cam1 =3D rvu_read64(rvu, blkaddr, + NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 1)); + w1_cam0 =3D rvu_read64(rvu, blkaddr, + NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 0)); + npc_fill_entryword(entry, kw + 1, w1_cam0, w1_cam1); + trace_otx2_npc_cam(actindex, bank, w0_cam0, w0_cam1, w1_cam0, w1_cam1); } =20 entry->action =3D rvu_read64(rvu, blkaddr, @@ -625,18 +635,28 @@ void npc_read_mcam_entry(struct rvu *rvu, struct npc_= mcam *mcam, NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank, 1)) & 3; *ena =3D rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(src, sbank)) & 1; + tx_intf =3D *intf; + if (is_npc_intf_tx(tx_intf)) + tx_intf &=3D 0x1; + trace_otx2_npc_action(actindex, sbank, tx_intf, *ena, + entry->action, entry->vtag_action); } =20 static int npc_copy_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr, u16 src, u16 dest) { + u64 cfg, sreg, dreg; + u16 orig_src =3D src, orig_dest =3D dest; int dbank =3D npc_get_bank(mcam, dest); int sbank =3D npc_get_bank(mcam, src); - u64 cfg, sreg, dreg; - int bank, i; + int bank, i, err; =20 - if (is_cn20k(rvu->pdev)) - return npc_cn20k_copy_mcam_entry(rvu, blkaddr, src, dest); + if (is_cn20k(rvu->pdev)) { + err =3D npc_cn20k_copy_mcam_entry(rvu, blkaddr, src, dest); + if (!err) + trace_otx2_npc_mcam_copy(orig_src, orig_dest); + return err; + } =20 src &=3D (mcam->banksize - 1); dest &=3D (mcam->banksize - 1); @@ -668,6 +688,7 @@ static int npc_copy_mcam_entry(struct rvu *rvu, struct = npc_mcam *mcam, NPC_AF_MCAMEX_BANKX_CFG(src, sbank)); rvu_write64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(dest, dbank), cfg); + trace_otx2_npc_mcam_copy(orig_src, orig_dest); return 0; } =20 @@ -3198,6 +3219,7 @@ static int npc_mcam_alloc_entries(struct npc_mcam *mc= am, u16 pcifunc, rsp->free_count =3D -1; mutex_unlock(&mcam->lock); =20 + trace_otx2_npc_mcam_alloc_entries(pcifunc, req, rsp); return 0; =20 not_cn20k: @@ -3384,6 +3406,7 @@ static int npc_mcam_alloc_entries(struct npc_mcam *mc= am, u16 pcifunc, rsp->free_count =3D mcam->bmap_fcnt; =20 mutex_unlock(&mcam->lock); + trace_otx2_npc_mcam_alloc_entries(pcifunc, req, rsp); return 0; } =20 @@ -4043,7 +4066,7 @@ int rvu_mbox_handler_npc_mcam_alloc_and_write_entry(s= truct rvu *rvu, struct rvu_pfvf *pfvf =3D rvu_get_pfvf(rvu, req->hdr.pcifunc); struct npc_mcam_alloc_counter_req cntr_req; struct npc_mcam_alloc_counter_rsp cntr_rsp; - struct npc_mcam_alloc_entry_req entry_req; + struct npc_mcam_alloc_entry_req entry_req =3D { 0 }; struct npc_mcam_alloc_entry_rsp entry_rsp; struct npc_mcam *mcam =3D &rvu->hw->mcam; u16 entry =3D NPC_MCAM_ENTRY_INVALID; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_trace.c b/driver= s/net/ethernet/marvell/octeontx2/af/rvu_trace.c index 19e0d16b12f6..42797e7d13ba 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_trace.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_trace.c @@ -13,3 +13,8 @@ EXPORT_TRACEPOINT_SYMBOL(otx2_msg_interrupt); EXPORT_TRACEPOINT_SYMBOL(otx2_msg_process); EXPORT_TRACEPOINT_SYMBOL(otx2_msg_status); EXPORT_TRACEPOINT_SYMBOL(otx2_parse_dump); +EXPORT_TRACEPOINT_SYMBOL(otx2_npc_mcam_alloc_entries); +EXPORT_TRACEPOINT_SYMBOL(otx2_npc_mcam_copy); +EXPORT_TRACEPOINT_SYMBOL(otx2_npc_enable_mcam_entry); +EXPORT_TRACEPOINT_SYMBOL(otx2_npc_cam); +EXPORT_TRACEPOINT_SYMBOL(otx2_npc_action); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_trace.h b/driver= s/net/ethernet/marvell/octeontx2/af/rvu_trace.h index 4cd0fc4b0d20..ea1c5d7f1007 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_trace.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_trace.h @@ -159,6 +159,120 @@ TRACE_EVENT(otx2_parse_dump, __entry->w3, __entry->w4, __entry->w5) ); =20 +TRACE_EVENT(otx2_npc_mcam_alloc_entries, + TP_PROTO(u16 pcifunc, + struct npc_mcam_alloc_entry_req *req, + struct npc_mcam_alloc_entry_rsp *rsp), + TP_ARGS(pcifunc, req, rsp), + TP_STRUCT__entry(__field(u16, pcifunc) + __field(u8, contig) + __field(u8, ref_prio) + __field(u16, ref_entry) + __field(u16, req_count) + __field(u8, kw_type) + __field(u8, virt) + __field(u16, start_mcam_idx) + __field(u16, rsp_count) + __field(u16, free_count) + ), + TP_fast_assign(__entry->pcifunc =3D pcifunc; + __entry->contig =3D req->contig; + __entry->ref_prio =3D req->ref_prio; + __entry->ref_entry =3D req->ref_entry; + __entry->req_count =3D req->count; + __entry->kw_type =3D req->kw_type; + __entry->virt =3D req->virt; + __entry->start_mcam_idx =3D req->contig ? rsp->entry : + (rsp->count ? rsp->entry_list[0] : + NPC_MCAM_ENTRY_INVALID); + __entry->rsp_count =3D rsp->count; + __entry->free_count =3D rsp->free_count; + ), + TP_printk("pcifunc:0x%x req_contig:%d req_ref_prio:%d req->ref_entry:= %d req->req_count:%d req->kw_type:%d req->virt:%d rsp_start_mcam_idx:%d rsp= _count:%d rsp_free_count:%d", + __entry->pcifunc, __entry->contig, __entry->ref_prio, + __entry->ref_entry, __entry->req_count, __entry->kw_type, + __entry->virt, __entry->start_mcam_idx, __entry->rsp_count, + __entry->free_count) +); + +TRACE_EVENT(otx2_npc_mcam_copy, + TP_PROTO(u16 src, u16 dest), + TP_ARGS(src, dest), + TP_STRUCT__entry(__field(u16, src) + __field(u16, dest) + ), + TP_fast_assign(__entry->src =3D src; + __entry->dest =3D dest; + ), + TP_printk("src:%d dest:%d", __entry->src, __entry->dest) +); + +TRACE_EVENT(otx2_npc_enable_mcam_entry, + TP_PROTO(u16 index, u8 enable), + TP_ARGS(index, enable), + TP_STRUCT__entry(__field(u16, mcam_index) + __field(u8, ena) + ), + TP_fast_assign(__entry->mcam_index =3D index; + __entry->ena =3D enable; + ), + TP_printk("mcam_index:%d enable:%d", __entry->mcam_index, __entry->en= a) +); + +TRACE_EVENT(otx2_npc_cam, + TP_PROTO(u16 index, u8 bank, + u64 w0_cam0, + u64 w0_cam1, + u64 w1_cam0, + u64 w1_cam1), + TP_ARGS(index, bank, + w0_cam0, w0_cam1, + w1_cam0, w1_cam1), + TP_STRUCT__entry(__field(u16, mcam_index) + __field(u8, bank) + __field(u64, w0_cam0) + __field(u64, w0_cam1) + __field(u64, w1_cam0) + __field(u64, w1_cam1) + ), + TP_fast_assign(__entry->mcam_index =3D index; + __entry->bank =3D bank; + __entry->w0_cam0 =3D w0_cam0; + __entry->w0_cam1 =3D w0_cam1; + __entry->w1_cam0 =3D w1_cam0; + __entry->w1_cam1 =3D w1_cam1; + ), + TP_printk("mcam_index:%d bank:%d w0_cam0:0x%llx w0_cam1:0x%llx w1_cam= 0:0x%llx w1_cam1:0x%llx", + __entry->mcam_index, __entry->bank, __entry->w0_cam0, __entry->w0_= cam1, + __entry->w1_cam0, __entry->w1_cam1) +); + +TRACE_EVENT(otx2_npc_action, + TP_PROTO(u16 index, u8 bank, + u8 tx_intf, u8 enable, + u64 act, u64 vtag_act), + TP_ARGS(index, bank, + tx_intf, enable, + act, vtag_act), + TP_STRUCT__entry(__field(u16, mcam_index) + __field(u8, bank) + __field(u8, tx_intf) + __field(u8, enable) + __field(u64, act) + __field(u64, vtag_act) + ), + TP_fast_assign(__entry->mcam_index =3D index; + __entry->bank =3D bank; + __entry->tx_intf =3D tx_intf; + __entry->enable =3D enable; + __entry->act =3D act; + __entry->vtag_act =3D vtag_act; + ), + TP_printk("mcam_index:%d bank:%d tx_intf:%d enable:%d action:0x%llx v= tag_action:0x%llx", + __entry->mcam_index, __entry->bank, __entry->tx_intf, + __entry->enable, __entry->act, __entry->vtag_act) +); + #endif /* __RVU_TRACE_H */ =20 #undef TRACE_INCLUDE_PATH --=20 2.43.0