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Add the device binding for ti,tda54-gpio. Signed-off-by: Aniket Limaye Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/gpio/gpio-davinci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/gpio/gpio-davinci.yaml b/Doc= umentation/devicetree/bindings/gpio/gpio-davinci.yaml index 1434d08f8b74..02b6b9a436a6 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-davinci.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-davinci.yaml @@ -18,6 +18,7 @@ properties: - ti,am654-gpio - ti,j721e-gpio - ti,am64-gpio + - ti,tda54-gpio - const: ti,keystone-gpio =20 - items: --=20 2.53.0 From nobody Thu Sep 24 12:53:51 2026 Received: from mx0b-0002e601.pphosted.com (mx0b-0002e601.pphosted.com [148.163.154.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 560934A2058; Wed, 23 Sep 2026 12:58:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.154.28 ARC-Seal: i=2; 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Signed-off-by: Aniket Limaye --- drivers/gpio/gpio-davinci.c | 103 ++++++++++++++++++++++++++++++++++++++++= +--- 1 file changed, 97 insertions(+), 6 deletions(-) diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c index cccbaea1dec2..e5a3abe6b9d3 100644 --- a/drivers/gpio/gpio-davinci.c +++ b/drivers/gpio/gpio-davinci.c @@ -39,12 +39,20 @@ struct davinci_gpio_regs { u32 intstat; }; =20 +struct davinci_gpio_regs_ext { + u32 set_high; + u32 clr_high; + u32 set_low; + u32 clr_low; +}; + typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq); =20 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ =20 static void __iomem *gpio_base; static unsigned int offset_array[5] =3D {0x10, 0x38, 0x60, 0x88, 0xb0}; +static unsigned int offset_array_ext[5] =3D {0xd8, 0xe8, 0xf8, 0x108, 0x11= 8}; =20 struct davinci_gpio_irq_data { void __iomem *regs; @@ -58,9 +66,11 @@ struct davinci_gpio_controller { /* Serialize access to GPIO registers */ spinlock_t lock; void __iomem *regs[MAX_REGS_BANKS]; + void __iomem *regs_ext[MAX_REGS_BANKS]; int gpio_unbanked; int irqs[MAX_INT_PER_BANK]; struct davinci_gpio_regs context[MAX_REGS_BANKS]; + struct davinci_gpio_regs_ext context_ext[MAX_REGS_BANKS]; u32 binten_context; }; =20 @@ -168,6 +178,7 @@ static int davinci_gpio_probe(struct platform_device *p= dev) unsigned int ngpio, nbank, nirq, gpio_unbanked; struct davinci_gpio_controller *chips; struct device *dev =3D &pdev->dev; + bool ext_reg =3D false; =20 /* * The gpio banks conceptually expose a segmented bitmap, @@ -190,6 +201,9 @@ static int davinci_gpio_probe(struct platform_device *p= dev) if (ret) return dev_err_probe(dev, ret, "Failed to get the unbanked GPIOs propert= y\n"); =20 + if (device_is_compatible(dev, "ti,tda54-gpio")) + ext_reg =3D true; + if (gpio_unbanked) nirq =3D gpio_unbanked; else @@ -235,8 +249,11 @@ static int davinci_gpio_probe(struct platform_device *= pdev) chips->gpio_unbanked =3D gpio_unbanked; =20 nbank =3D DIV_ROUND_UP(ngpio, 32); - for (bank =3D 0; bank < nbank; bank++) + for (bank =3D 0; bank < nbank; bank++) { chips->regs[bank] =3D gpio_base + offset_array[bank]; + if (ext_reg) + chips->regs_ext[bank] =3D gpio_base + offset_array_ext[bank]; + } =20 ret =3D devm_gpiochip_add_data(dev, &chips->chip, chips); if (ret) @@ -267,10 +284,15 @@ static void gpio_irq_mask(struct irq_data *d) struct davinci_gpio_controller *chips =3D irq_data_get_irq_chip_data(d); irq_hw_number_t hwirq =3D irqd_to_hwirq(d); struct davinci_gpio_regs __iomem *g =3D chips->regs[hwirq / 32]; + struct davinci_gpio_regs_ext __iomem *g_ext =3D chips->regs_ext[hwirq / 3= 2]; uintptr_t mask =3D (uintptr_t)irq_data_get_irq_handler_data(d); =20 writel_relaxed(mask, &g->clr_falling); writel_relaxed(mask, &g->clr_rising); + if (g_ext) { + writel_relaxed(mask, &g_ext->clr_high); + writel_relaxed(mask, &g_ext->clr_low); + } =20 gpiochip_disable_irq(&chips->chip, hwirq); } @@ -280,12 +302,14 @@ static void gpio_irq_unmask(struct irq_data *d) struct davinci_gpio_controller *chips =3D irq_data_get_irq_chip_data(d); irq_hw_number_t hwirq =3D irqd_to_hwirq(d); struct davinci_gpio_regs __iomem *g =3D chips->regs[hwirq / 32]; + struct davinci_gpio_regs_ext __iomem *g_ext =3D chips->regs_ext[hwirq / 3= 2]; uintptr_t mask =3D (uintptr_t)irq_data_get_irq_handler_data(d); unsigned status =3D irqd_get_trigger_type(d); + unsigned int ext_status =3D g_ext ? (IRQ_TYPE_LEVEL_MASK) : 0; =20 gpiochip_enable_irq(&chips->chip, hwirq); =20 - status &=3D IRQ_TYPE_EDGE_BOTH; + status &=3D IRQ_TYPE_EDGE_BOTH | ext_status; if (!status) status =3D IRQ_TYPE_EDGE_BOTH; =20 @@ -293,6 +317,18 @@ static void gpio_irq_unmask(struct irq_data *d) writel_relaxed(mask, &g->set_falling); if (status & IRQ_TYPE_EDGE_RISING) writel_relaxed(mask, &g->set_rising); + if (status & IRQ_TYPE_LEVEL_HIGH) + writel_relaxed(mask, &g_ext->set_high); + if (status & IRQ_TYPE_LEVEL_LOW) + writel_relaxed(mask, &g_ext->set_low); +} + +static int gpio_irq_type_ext(struct irq_data *d, unsigned int trigger) +{ + if (trigger & ~(IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_MASK)) + return -EINVAL; + + return 0; } =20 static int gpio_irq_type(struct irq_data *d, unsigned trigger) @@ -303,6 +339,15 @@ static int gpio_irq_type(struct irq_data *d, unsigned = trigger) return 0; } =20 +static const struct irq_chip gpio_irqchip_ext =3D { + .name =3D "GPIO", + .irq_unmask =3D gpio_irq_unmask, + .irq_mask =3D gpio_irq_mask, + .irq_set_type =3D gpio_irq_type_ext, + .flags =3D IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED | IRQCHIP_SKIP_SE= T_WAKE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + static const struct irq_chip gpio_irqchip =3D { .name =3D "GPIO", .irq_unmask =3D gpio_irq_unmask, @@ -387,10 +432,13 @@ static int gpio_irq_type_unbanked(struct irq_data *da= ta, unsigned trigger) { struct davinci_gpio_controller *d; struct davinci_gpio_regs __iomem *g; + struct davinci_gpio_regs_ext __iomem *g_ext; u32 mask, i; + u32 ext_trigger; =20 d =3D (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(dat= a); g =3D (struct davinci_gpio_regs __iomem *)d->regs[0]; + g_ext =3D (struct davinci_gpio_regs_ext __iomem *)d->regs_ext[0]; for (i =3D 0; i < MAX_INT_PER_BANK; i++) if (data->irq =3D=3D d->irqs[i]) break; @@ -400,13 +448,21 @@ static int gpio_irq_type_unbanked(struct irq_data *da= ta, unsigned trigger) =20 mask =3D __gpio_mask(i); =20 - if (trigger & ~IRQ_TYPE_EDGE_BOTH) + ext_trigger =3D g_ext ? (IRQ_TYPE_LEVEL_MASK) : 0; + + if (trigger & ~(IRQ_TYPE_EDGE_BOTH | ext_trigger)) return -EINVAL; =20 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING) ? &g->set_falling : &g->clr_falling); writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING) ? &g->set_rising : &g->clr_rising); + if (ext_trigger) { + writel_relaxed(mask, (trigger & IRQ_TYPE_LEVEL_HIGH) + ? &g_ext->set_high : &g_ext->clr_high); + writel_relaxed(mask, (trigger & IRQ_TYPE_LEVEL_LOW) + ? &g_ext->set_low : &g_ext->clr_low); + } =20 return 0; } @@ -418,8 +474,12 @@ davinci_gpio_irq_map(struct irq_domain *d, unsigned in= t irq, struct davinci_gpio_controller *chips =3D (struct davinci_gpio_controller *)d->host_data; =20 - irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, - "davinci_gpio"); + if (chips->regs_ext[0]) + irq_set_chip_and_handler_name(irq, &gpio_irqchip_ext, handle_simple_irq, + "davinci_gpio"); + else + irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, + "davinci_gpio"); irq_set_irq_type(irq, IRQ_TYPE_NONE); irq_set_chip_data(irq, (__force void *)chips); irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw)); @@ -469,6 +529,7 @@ static int davinci_gpio_irq_setup(struct platform_devic= e *pdev) struct device *dev =3D &pdev->dev; struct davinci_gpio_controller *chips =3D platform_get_drvdata(pdev); struct davinci_gpio_regs __iomem *g; + struct davinci_gpio_regs_ext __iomem *g_ext; struct irq_domain *irq_domain =3D NULL; struct irq_chip *irq_chip; struct davinci_gpio_irq_data *irqdata; @@ -495,9 +556,9 @@ static int davinci_gpio_irq_setup(struct platform_devic= e *pdev) dev_err(dev, "Couldn't allocate IRQ numbers\n"); return irq; } - irq_domain =3D irq_domain_create_legacy(dev_fwnode(dev), ngpio, irq, 0, &davinci_gpio_irq_ops, chips); + if (!irq_domain) { dev_err(dev, "Couldn't register an IRQ domain\n"); return -ENODEV; @@ -534,6 +595,11 @@ static int davinci_gpio_irq_setup(struct platform_devi= ce *pdev) g =3D chips->regs[0]; writel_relaxed(~0, &g->set_falling); writel_relaxed(~0, &g->set_rising); + g_ext =3D chips->regs_ext[0]; + if (g_ext) { + writel_relaxed(~0, &g_ext->set_high); + writel_relaxed(~0, &g_ext->set_low); + } =20 /* set the direct IRQs up to use that irqchip */ for (gpio =3D 0; gpio < chips->gpio_unbanked; gpio++) { @@ -558,6 +624,12 @@ static int davinci_gpio_irq_setup(struct platform_devi= ce *pdev) g =3D chips->regs[bank / 2]; writel_relaxed(~0, &g->clr_falling); writel_relaxed(~0, &g->clr_rising); + g_ext =3D chips->regs_ext[bank / 2]; + if (g_ext) { + writel_relaxed(~0, &g_ext->clr_high); + writel_relaxed(~0, &g_ext->clr_low); + } + =20 /* * Each chip handles 32 gpios, and each irq bank consists of 16 @@ -597,7 +669,9 @@ static void davinci_gpio_save_context(struct davinci_gp= io_controller *chips, u32 nbank) { struct davinci_gpio_regs __iomem *g; + struct davinci_gpio_regs_ext __iomem *g_ext; struct davinci_gpio_regs *context; + struct davinci_gpio_regs_ext *context_ext; u32 bank; void __iomem *base; =20 @@ -611,6 +685,12 @@ static void davinci_gpio_save_context(struct davinci_g= pio_controller *chips, context->set_data =3D readl_relaxed(&g->set_data); context->set_rising =3D readl_relaxed(&g->set_rising); context->set_falling =3D readl_relaxed(&g->set_falling); + g_ext =3D chips->regs_ext[bank]; + if (g_ext) { + context_ext =3D &chips->context_ext[bank]; + context_ext->set_high =3D readl_relaxed(&g_ext->set_high); + context_ext->set_low =3D readl_relaxed(&g_ext->set_low); + } } =20 /* Clear all interrupt status registers */ @@ -621,7 +701,9 @@ static void davinci_gpio_restore_context(struct davinci= _gpio_controller *chips, u32 nbank) { struct davinci_gpio_regs __iomem *g; + struct davinci_gpio_regs_ext __iomem *g_ext; struct davinci_gpio_regs *context; + struct davinci_gpio_regs_ext *context_ext; u32 bank; void __iomem *base; =20 @@ -641,6 +723,14 @@ static void davinci_gpio_restore_context(struct davinc= i_gpio_controller *chips, writel_relaxed(context->set_rising, &g->set_rising); if (readl_relaxed(&g->set_falling) !=3D context->set_falling) writel_relaxed(context->set_falling, &g->set_falling); + g_ext =3D chips->regs_ext[bank]; + if (g_ext) { + context_ext =3D &chips->context_ext[bank]; + if (readl_relaxed(&g_ext->set_high) !=3D context_ext->set_high) + writel_relaxed(context_ext->set_high, &g_ext->set_high); + if (readl_relaxed(&g_ext->set_low) !=3D context_ext->set_low) + writel_relaxed(context_ext->set_low, &g_ext->set_low); + } } } =20 @@ -671,6 +761,7 @@ static const struct of_device_id davinci_gpio_ids[] =3D= { { .compatible =3D "ti,keystone-gpio", keystone_gpio_get_irq_chip}, { .compatible =3D "ti,am654-gpio", keystone_gpio_get_irq_chip}, { .compatible =3D "ti,dm6441-gpio", davinci_gpio_get_irq_chip}, + { .compatible =3D "ti,tda54-gpio", keystone_gpio_get_irq_chip}, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, davinci_gpio_ids); --=20 2.53.0