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Wed, 23 Sep 2026 05:16:38 -0700 (PDT) From: Neil Armstrong Date: Wed, 23 Sep 2026 14:16:32 +0200 Subject: [PATCH v2 1/2] dt-bindings: arm: qcom: document the Valve Deckard headset Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-topic-sm8650-deckard-initial-dt-v2-1-8361c4548efa@linaro.org> References: <20260923-topic-sm8650-deckard-initial-dt-v2-0-8361c4548efa@linaro.org> In-Reply-To: <20260923-topic-sm8650-deckard-initial-dt-v2-0-8361c4548efa@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kees Cook , Tony Luck , "Guilherme G. Piccoli" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=811; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=DRDBx8uJu/gmNOt8neF/NrrQZ8Y1qYuByeAf3Z74Z9c=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBqs8Mj5TJDcH5ec052eG5KgX9HZ7Ea/UFuN9GKHSfL YRIfyL6JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCarPDIwAKCRB33NvayMhJ0Q13D/ 9bdnhDVIsRT15xrCfzJ70ZyN2qHEoRoFvMbulhLAZXqZFJQT38TK5Lg3mrz7+UAyJGbvsR0tp+1O6l RdTJ+vhu0oRIsFzY8QWA12MmPcZuJeJFqScye8urN4Khv1bWjn0pKlrgB6er1HnlofE6sz9VCwmrI4 pskYBxxO6BGX35w7n5+VkPNFVT/y68M63loyEv438YAjLO0Vw1MkRMmLbtPPbWF4U9Kfi3PaBDQb5i x9bAX0r+HuAvW5l5NXfGykqamkgS9JBY8cqpijCQYmilIf/EJNvUPv59MXo9G/dx6tB6ASWE7dnR5c j9oENYfZfIpwdQU9Tcyy+4ZBpN/objqqWTRHoGGZIZ4GqSKTFWyWNg3EnuVnFByZ5giysL9Mq8pmo8 qi/mZJBftaZ/cdH+XE83qCuKAFtDy1pyYB/vNo1kpdJTJTD9xcWhPecQaGK05agiXk+Rnz9fzhs/6m FrN4xg57csDR0PTOSu49laN3xoOE/1Eb8mX7sp5/XatW3fLMIbXIrN8leQ79SiuVh7m51hfCgT3BZU ro68cmxLNNah2n9YvaXE5oQU2Oh8girZZVXgJAUWb+aSjsyka0AeWbSzESEuKEq9l1L4VOJGOxFkQE yEeBi0SXKB8KViQzSMXZyzw3Ow7LOo7d57dT3SaBgHVY5hjJmm6qH5VmnWvg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Document the Valve "Steam Frame" codename Deckard. The Steam Frame is a virtual reality headset based on the Qualcomm Snapdragon 8 Gen 3 SoC (SM8650). Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index ff8a35df7862..0130bf93987c 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1164,6 +1164,7 @@ properties: - qcom,sm8650-hdk - qcom,sm8650-mtp - qcom,sm8650-qrd + - valve,deckard - const: qcom,sm8650 =20 - items: --=20 2.34.1 From nobody Thu Sep 24 12:55:34 2026 Received: from mail-wr2-f12.google.com (mail-wr2-f12.google.com [74.125.225.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1183F50C2B3 for ; Wed, 23 Sep 2026 12:16:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.225.76 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Wed, 23 Sep 2026 05:16:39 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:106d:1080:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48868889376sm5410298f8f.33.2026.09.23.05.16.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 05:16:39 -0700 (PDT) From: Neil Armstrong Date: Wed, 23 Sep 2026 14:16:33 +0200 Subject: [PATCH v2 2/2] arm64: dts: qcom: sm8650: Add initial Valve Deckard devicetree Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-topic-sm8650-deckard-initial-dt-v2-2-8361c4548efa@linaro.org> References: <20260923-topic-sm8650-deckard-initial-dt-v2-0-8361c4548efa@linaro.org> In-Reply-To: <20260923-topic-sm8650-deckard-initial-dt-v2-0-8361c4548efa@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kees Cook , Tony Luck , "Guilherme G. Piccoli" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=33206; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=laZZkvnEKR8TTkNJqUY9dTSDj7jAN5+4xM9vg8LATzA=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBqs8MjarPEsflgF+rJuplBNMVQxit5K2MCL7VhJEdi VzhSF8aJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCarPDIwAKCRB33NvayMhJ0V/kD/ 4uOrKlV4X0pwzvgaLEB9SCZgRgj4CKE6NStVA7JOeWBFTkIVnvCDRlCT0M+uot4r2R+Q70In++2eX2 BPv5JwFZ2rFrdz6KG9X7E+pRqHYTXgb/0tuZnc16bxNT0yoFlNrPeGjjkOckNDrGi6moMwRKlSLKFL WoFdQGW5q+ZDQR5M6WHVHVDBjuaqrC+yTZF06ugFkS95LqaT3eOIcOVnI8l8mROnkXtjMgne8be0NG FbPQ/QKj8EMmoK6cMGOd0qRX2n+8prQMPEf63FJC1vnKi3SjxJEzcKyA2dsczUSbljsx9ApTAqRcbz QUvvt4IVugXvBxG5JHsc7hnceEVfuAk/8LZB3jarBF97zeYmq7ijVDjS+YPOxJAJj23Ly3nwQAL92p Ni9DbJkArSYBs11ZBW5CdpzH0u4dQe2TzIjWBSS2f17RQe5NeSeQ+ifVsntjtw7zQHIZsjoQvsvqFF gi5L0/h4IAcJh7XeBukft7O4mc8RtIwOkKofmcVOYmFk4elEtIbFdPla2zgLOdjo6jC7djgbWIrwPc UHrbqFsbl2L7x6UAxAtb5ERxi2p+K98+ScWQgAuc4Sp9SkP9KmwIFx0w0BV8qDBycCmnqyOgYmk90+ xWZaSFyb9Ei+6zI81cRHwGSLbnNg18BFV/s+F/6Rz+6rvDCthCfYJtFhqr5A== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add an initial DeviceTree for the Valve "Steam Frame" codename Deckard. The Steam Frame is a virtual reality headset based on the Qualcomm Snapdragon 8 Gen 3 SoC (SM8650). Providing initial support for: - System reserved memory, regulators, gpio keys, PMIC functions.. - PMIC ADC Channels - UFS Storage - USB Gadget - WCN7850 Wifi7 + Bluetooth - I2C + basic peripherals - SDCard slot The bootloader starts Linux in EL2, thus a bunch of EL1 & DSP related nodes needs to be removed and the reserved-memory mapping must be defined. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm8650-valve-deckard.dts | 1288 +++++++++++++++++= ++++ arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 +- 3 files changed, 1292 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 1c86e7e98f55..3de6d95135a7 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -406,6 +406,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-hdk-rear-camera-car= d.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-valve-deckard.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8750-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8750-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D talos-evk.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8650-valve-deckard.dts b/arch/arm64= /boot/dts/qcom/sm8650-valve-deckard.dts new file mode 100644 index 000000000000..d25a09e162dd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8650-valve-deckard.dts @@ -0,0 +1,1288 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Valve Software + */ + +/dts-v1/; + +#include +#include +#include +#include "sm8650.dtsi" +#include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 8 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" + +/* Remove nodes */ +/delete-node/ &ipa; +/delete-node/ &gpu_zap_shader; +/delete-node/ &lpass_wsa2macro; +/delete-node/ &lpass_rxmacro; +/delete-node/ &lpass_txmacro; +/delete-node/ &lpass_wsamacro; +/delete-node/ &lpass_vamacro; +/delete-node/ &lpass_tlmm; +/delete-node/ &remoteproc_adsp; +/delete-node/ &remoteproc_cdsp; +/delete-node/ &remoteproc_mpss; +/delete-node/ &reserved_memory; +/delete-node/ &smp2p_adsp; +/delete-node/ &smp2p_cdsp; +/delete-node/ &smp2p_modem; +/delete-node/ &swr0; +/delete-node/ &swr1; +/delete-node/ &swr2; +/delete-node/ &swr3; + +/ { + model =3D "Valve Deckard"; + compatible =3D "valve,deckard", "qcom,sm8650"; + + aliases { + serial0 =3D &uart15; + serial1 =3D &uart14; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + + framebuffer { + compatible =3D "simple-framebuffer"; + width =3D <4320>; + height =3D <2160>; + stride =3D <(4320 * 4)>; + format =3D "a8r8g8b8"; + memory-region =3D <&framebuffer_mem>; + + /* Bootloader will enable the node */ + status =3D "disabled"; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&volume_up_n>, <&select_n>; + pinctrl-names =3D "default"; + + key-volume-up { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + linux,can-disable; + }; + + key-select { + label =3D "Select"; + linux,code =3D ; + gpios =3D <&pm8550b_gpios 5 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + linux,can-disable; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + regulator-always-on; + regulator-boot-on; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + aop_mem: aop-region@81c00000 { + no-map; + reg =3D <0 0x81c00000 0 0x60000>; + }; + + ramoops: ramoops-region@84a00000 { + compatible =3D "ramoops"; + reg =3D <0 0x84a00000 0 0x100000>; + record-size =3D <0x40000>; + console-size =3D <0x40000>; + pmsg-size =3D <0x1000>; + ecc-size =3D <16>; + }; + + aop_cmd_db_mem: aop-cmd-db-region@81c60000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0 0x81c60000 0 0x20000>; + no-map; + }; + + /* merged aop_config, tme_crash_dump, tme_log */ + aop_config_merged_mem: aop-config-merged-region@81c80000 { + reg =3D <0 0x81c80000 0 0x75000>; + no-map; + }; + + smem: smem-region@81d00000 { + compatible =3D "qcom,smem"; + reg =3D <0 0x81d00000 0 0x200000>; + hwlocks =3D <&tcsr_mutex 3>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw-region@d8040000 { + reg =3D <0 0xd8040000 0 0x1b2000>; + no-map; + }; + + video_mem: video-region@9bb00000 { + reg =3D <0 0x9bb00000 0 0x800000>; + no-map; + }; + + tz_stat_mem: tz-stat-region@82700000 { + reg =3D <0 0x82700000 0 0x100000>; + no-map; + }; + + /* 2MB, 8 clocks to power on each 256KB block */ + lpass_lpi_tcm: lpm-region@6000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x06000000 0 0x00200000>; + no-map; + }; + + /* 64KB, 4 clocks to power on each 16KB block */ + lpass_audio_lpm: lpm-region@6c80000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x06c80000 0 0x10000>; + no-map; + }; + + /* 12KB, 1 clock */ + lpass_va_lpm: lpm-region@6d40000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x06d40000 0 0x3000>; + no-map; + }; + + lpass_lpm: lpm-region@7c10000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x07c10000 0 0x8000>; + no-map; + }; + + framebuffer_mem: framebuffer-region@af400000 { + reg =3D <0 0xaf400000 0 0x03000000>; + no-map; + }; + }; + + wcn7850-pmu { + compatible =3D "qcom,wcn7850-pmu"; + + pinctrl-0 =3D <&wlan_en>, <&bt_default>; + pinctrl-names =3D "default"; + + wlan-enable-gpios =3D <&tlmm 16 GPIO_ACTIVE_HIGH>; + bt-enable-gpios =3D <&tlmm 17 GPIO_ACTIVE_HIGH>; + + vdd-supply =3D <&vreg_s4i_0p85>; + vddio-supply =3D <&vreg_l15b_1p8>; + vddio1p2-supply =3D <&vreg_l3c_1p2>; + vddaon-supply =3D <&vreg_s2c_0p8>; + vdddig-supply =3D <&vreg_s3c_0p9>; + vddrfa1p2-supply =3D <&vreg_s1c_1p2>; + vddrfa1p8-supply =3D <&vreg_s6c_1p8>; + + clocks =3D <&rpmhcc RPMH_RF_CLK1>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name =3D "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name =3D "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name =3D "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name =3D "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name =3D "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name =3D "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name =3D "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name =3D "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name =3D "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name =3D "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8550-rpmh-regulators"; + + vdd-bob1-supply =3D <&vph_pwr>; + vdd-bob2-supply =3D <&vph_pwr>; + vdd-l1-l4-l10-supply =3D <&vreg_s6c_1p8>; + vdd-l2-l13-l14-supply =3D <&vreg_bob1>; + vdd-l3-supply =3D <&vreg_s1c_1p2>; + vdd-l5-l16-supply =3D <&vreg_bob1>; + vdd-l8-l9-supply =3D <&vreg_bob1>; + vdd-l12-supply =3D <&vreg_s6c_1p8>; + vdd-l15-supply =3D <&vreg_s6c_1p8>; + vdd-l17-supply =3D <&vreg_bob2>; + + qcom,pmic-id =3D "b"; + + vreg_bob1: bob1 { + regulator-name =3D "vreg_bob1"; + regulator-min-microvolt =3D <3296000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2: bob2 { + regulator-name =3D "vreg_bob2"; + regulator-min-microvolt =3D <2720000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name =3D "vreg_l1b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name =3D "vreg_l2b_3p0"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name =3D "vreg_l5b_3p1"; + regulator-min-microvolt =3D <3104000>; + regulator-max-microvolt =3D <3104000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name =3D "vreg_l8b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name =3D "vreg_l9b_2p9"; + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name =3D "vreg_l10b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name =3D "vreg_l12b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name =3D "vreg_l15b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name =3D "vreg_l17b_2p5"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s1c_1p2>; + vdd-l3-supply =3D <&vreg_s1c_1p2>; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + + qcom,pmic-id =3D "c"; + + vreg_s1c_1p2: smps1 { + regulator-name =3D "vreg_s1c_1p2"; + regulator-min-microvolt =3D <1224000>; + regulator-max-microvolt =3D <1348000>; + regulator-initial-mode =3D ; + }; + + vreg_s2c_0p8: smps2 { + regulator-name =3D "vreg_s2c_0p8"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1036000>; + regulator-initial-mode =3D ; + }; + + vreg_s3c_0p9: smps3 { + regulator-name =3D "vreg_s3c_0p9"; + regulator-min-microvolt =3D <904000>; + regulator-max-microvolt =3D <1064000>; + regulator-initial-mode =3D ; + }; + + vreg_s4c_1p2: smps4 { + regulator-name =3D "vreg_s4c_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1280000>; + regulator-initial-mode =3D ; + }; + + vreg_s5c_0p7: smps5 { + regulator-name =3D "vreg_s5c_0p7"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <900000>; + regulator-initial-mode =3D ; + }; + + vreg_s6c_1p8: smps6 { + regulator-name =3D "vreg_s6c_1p8"; + regulator-min-microvolt =3D <1856000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name =3D "vreg_l1c_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l3c_1p2: ldo3 { + regulator-name =3D "vreg_l3c_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s3c_0p9>; + + qcom,pmic-id =3D "d"; + + vreg_l1d_0p9: ldo1 { + regulator-name =3D "vreg_l1d_0p9"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-3 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + + vdd-l3-supply =3D <&vreg_s3c_0p9>; + + qcom,pmic-id =3D "e"; + + vreg_l3e_0p9: ldo3 { + regulator-name =3D "vreg_l3e_0p9"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-4 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s3c_0p9>; + vdd-l2-supply =3D <&vreg_s1c_1p2>; + vdd-l3-supply =3D <&vreg_s3c_0p9>; + + qcom,pmic-id =3D "g"; + + vreg_l1g_0p9: ldo1 { + regulator-name =3D "vreg_l1g_0p9"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + + vreg_l2g_1p1: ldo2 { + regulator-name =3D "vreg_l2g_1p1"; + regulator-min-microvolt =3D <1104000>; + regulator-max-microvolt =3D <1104000>; + regulator-initial-mode =3D ; + }; + + vreg_l3g_0p91: ldo3 { + regulator-name =3D "vreg_l3g_0p91"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-5 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s3c_0p9>; + vdd-l2-supply =3D <&vreg_s3c_0p9>; + vdd-l3-supply =3D <&vreg_s1c_1p2>; + vdd-s4-supply =3D <&vph_pwr>; + + qcom,pmic-id =3D "i"; + + vreg_s4i_0p85: smps4 { + regulator-name =3D "vreg_s4i_0p85"; + regulator-min-microvolt =3D <852000>; + regulator-max-microvolt =3D <1004000>; + regulator-initial-mode =3D ; + }; + + vreg_l1i_0p88: ldo1 { + regulator-name =3D "vreg_l1i_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2i_0p88: ldo2 { + regulator-name =3D "vreg_l2i_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3i_1p2: ldo3 { + regulator-name =3D "vreg_l3i_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-6 { + compatible =3D "qcom,pm8010-rpmh-regulators"; + + vdd-l1-l2-supply =3D <&vreg_s1c_1p2>; + vdd-l3-l4-supply =3D <&vreg_bob2>; + vdd-l5-supply =3D <&vreg_s6c_1p8>; + vdd-l6-supply =3D <&vreg_bob2>; + vdd-l7-supply =3D <&vreg_bob1>; + + qcom,pmic-id =3D "m"; + + vreg_l1m_1p1: ldo1 { + regulator-name =3D "vreg_l1m_1p1"; + regulator-min-microvolt =3D <1104000>; + regulator-max-microvolt =3D <1104000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2m_1p2: ldo2 { + regulator-name =3D "vreg_l2m_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name =3D "vreg_l3m_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l4m_2p8: ldo4 { + regulator-name =3D "vreg_l4m_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l5m_1p8: ldo5 { + regulator-name =3D "vreg_l5m_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l6m_2p8: ldo6 { + regulator-name =3D "vreg_l6m_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l7m_3p3: ldo7 { + regulator-name =3D "vreg_l7m_3p3"; + regulator-min-microvolt =3D <3304000>; + regulator-max-microvolt =3D <3304000>; + regulator-initial-mode =3D ; + + regulator-always-on; + }; + }; + + regulators-7 { + compatible =3D "qcom,pm8010-rpmh-regulators"; + + vdd-l1-l2-supply =3D <&vreg_s1c_1p2>; + vdd-l3-l4-supply =3D <&vreg_bob2>; + vdd-l5-supply =3D <&vreg_s6c_1p8>; + vdd-l6-supply =3D <&vreg_bob2>; + + qcom,pmic-id =3D "n"; + + vreg_l1n_1p1: ldo1 { + regulator-name =3D "vreg_l1n_1p1"; + regulator-min-microvolt =3D <1104000>; + regulator-max-microvolt =3D <1104000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2n_1p2: ldo2 { + regulator-name =3D "vreg_l2n_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3n_2p8: ldo3 { + regulator-name =3D "vreg_l3n_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l4n_2p8: ldo4 { + regulator-name =3D "vreg_l4n_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l5n_1p8: ldo5 { + regulator-name =3D "vreg_l5n_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l6n_2p8: ldo6 { + regulator-name =3D "vreg_l6n_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&dispcc { + status =3D "disabled"; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + +&gpi_dma2 { + status =3D "okay"; +}; + +&gpu { + status =3D "okay"; +}; + +&i2c_hub_8 { + clock-frequency =3D <100000>; + + status =3D "okay"; + + right_spkr_i2s: speaker@38 { + compatible =3D "maxim,max98390"; + reg =3D <0x38>; + + reset-gpios =3D <&tlmm 73 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&r_spkr_irq_default>; + pinctrl-names =3D "default"; + + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "Speaker Right"; + + maxim,temperature_calib =3D <1024>; + maxim,r0_calib =3D <100232>; + }; + + left_spkr_i2s: speaker@3d { + compatible =3D "maxim,max98390"; + reg =3D <0x3d>; + + reset-gpios =3D <&tlmm 161 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&l_spkr_irq_default>; + pinctrl-names =3D "default"; + + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "Speaker Left"; + + maxim,temperature_calib =3D <1024>; + maxim,r0_calib =3D <100232>; + }; + + light-sensor@60 { + compatible =3D "vishay,vcnl4040"; + reg =3D <0x60>; + + vdd-supply =3D <&vreg_l2b_3p0>; + vio-supply =3D <&vreg_l1b_1p8>; + + proximity-near-level =3D <220>; + }; +}; + +&i2c_master_hub_0 { + firmware-name =3D "qcom/sm8650/qupv3fw.elf"; + + status =3D "okay"; +}; + +&i2c2 { + clock-frequency =3D <100000>; + + status =3D "okay"; + + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + + label =3D "strap_eeprom"; + vcc-supply =3D <&vreg_l15b_1p8>; + }; + + eeprom@51 { + compatible =3D "atmel,24c04"; + reg =3D <0x51>; + + label =3D "strap_v2_eeprom"; + vcc-supply =3D <&vreg_l15b_1p8>; + }; +}; + +&i2c4 { + clock-frequency =3D <100000>; + + status =3D "okay"; + + magnetometer@6c { + compatible =3D "allegromicro,als31300-500"; + reg =3D <0x6c>; + + vcc-supply =3D <&vreg_l2b_3p0>; + }; +}; + +&i2c5 { + clock-frequency =3D <100000>; + + status =3D "okay"; + + eeprom@50 { + compatible =3D "atmel,24c64"; + reg =3D <0x50>; + label =3D "core_v2_eeprom"; + vcc-supply =3D <&vreg_l15b_1p8>; + pagesize =3D <32>; + size =3D <8192>; + address-width =3D <16>; + wp-gpios =3D <&tlmm 78 GPIO_ACTIVE_HIGH>; + }; +}; + +&pcie0 { + wake-gpios =3D <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios =3D <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcieport0 { + wifi@0 { + compatible =3D "pci17cb,1107"; + reg =3D <0x10000 0 0 0 0>; + + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn>; + vddaon-supply =3D <&vreg_pmu_aon_0p59>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply =3D <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply =3D <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l1i_0p88>; + vdda-pll-supply =3D <&vreg_l3i_1p2>; + + status =3D "okay"; +}; + +&pm8550_gpios { + sdc2_card_det_n: sdc2-card-det-state { + pins =3D "gpio12"; + function =3D "normal"; + bias-pull-up; + input-enable; + output-disable; + power-source =3D <1>; /* 1.8 V */ + }; + + volume_up_n: volume-up-n-state { + pins =3D "gpio6"; + function =3D "normal"; + bias-pull-up; + input-enable; + power-source =3D <1>; + }; +}; + +&pm8550_pwm { + status =3D "okay"; + + multi-led { + color =3D ; + function =3D LED_FUNCTION_STATUS; + default-state =3D "keep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@1 { + reg =3D <1>; + color =3D ; + }; + + led@2 { + reg =3D <2>; + color =3D ; + }; + + led@3 { + reg =3D <3>; + color =3D ; + }; + }; +}; + +&pm8550_temp_alarm { + io-channels =3D <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(1)>; + io-channel-names =3D "thermal"; +}; + +&pm8550b_gpios { + detect_n: detect-n-state { + pins =3D "gpio6"; + function =3D "normal"; + power-source =3D <1>; + bias-pull-up; + input-enable; + }; + + select_n: select-n-state { + pins =3D "gpio5"; + function =3D "normal"; + power-source =3D <1>; + bias-pull-up; + input-enable; + }; +}; + +&pm8550b_eusb2_repeater { + vdd18-supply =3D <&vreg_l15b_1p8>; + vdd3-supply =3D <&vreg_l5b_3p1>; +}; + +&pm8550b_temp_alarm { + io-channels =3D <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(7)>; + io-channel-names =3D "thermal"; +}; + +&pm8550vs_c { + status =3D "okay"; +}; + +&pm8550vs_c_temp_alarm { + io-channels =3D <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names =3D "thermal"; +}; + +&pm8550vs_d { + status =3D "okay"; +}; + +&pm8550vs_d_temp_alarm { + io-channels =3D <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(3)>; + io-channel-names =3D "thermal"; +}; + +&pm8550vs_e { + status =3D "okay"; +}; + +&pm8550vs_e_temp_alarm { + io-channels =3D <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names =3D "thermal"; +}; + +&pm8550vs_g { + status =3D "okay"; +}; + +&pm8550vs_g_temp_alarm { + io-channels =3D <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names =3D "thermal"; +}; + +&pm8550ve_temp_alarm { + io-channels =3D <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)>; + io-channel-names =3D "thermal"; +}; + +&pmk8550_rtc { + allow-set-time; + + status =3D "okay"; +}; + +&pmk8550_vadc { + /* PMK8550 Channel nodes */ + channel@44 { + reg =3D ; + label =3D "pmk8550_xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + }; + + channel@49 { + reg =3D ; + label =3D "display_left_therm"; + qcom,ratiometric; + qcom,hw-settle-time =3D <15>; + }; + + /* PM8550 Channel nodes */ + channel@100 { + reg =3D ; + label =3D "pm8550_offset_ref"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@101 { + reg =3D ; + label =3D "pm8550_vref_1p25"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@103 { + reg =3D ; + label =3D "pm8550_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@144 { + reg =3D ; + label =3D "pcba_at_fan_exhaust"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + }; + + channel@145 { + reg =3D ; + label =3D "pcba_at_40pin_connector"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + }; + + channel@146 { + reg =3D ; + label =3D "pcba_at_wifi"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + }; + + channel@147 { + reg =3D ; + label =3D "pcba_at_flash"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + }; + + channel@148 { + reg =3D ; + label =3D "pcba_at_nrf"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + }; + + channel@18e { + reg =3D ; + label =3D "pm8550_vph_pwr"; + qcom,pre-scaling =3D <1 3>; + }; + + /* PM8550VS_C Channel nodes */ + channel@203 { + reg =3D ; + label =3D "pm8550vs_c_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550VS_D Channel nodes */ + channel@303 { + reg =3D ; + label =3D "pm8550vs_d_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550VS_E Channel nodes */ + channel@403 { + reg =3D ; + label =3D "pm8550vs_e_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550VE Channel nodes */ + channel@503 { + reg =3D ; + label =3D "pm8550ve_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550VS_G Channel nodes */ + channel@603 { + reg =3D ; + label =3D "pm8550vs_g_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550B Channel nodes */ + channel@700 { + reg =3D ; + label =3D "pm8550b_offset_ref"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@701 { + reg =3D ; + label =3D "pm8550b_vref_1p25"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@703 { + reg =3D ; + label =3D "pm8550b_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@711 { + reg =3D ; + label =3D "pm8550b_usb_sns_v_div_16"; + qcom,pre-scaling =3D <1 16>; + }; + + channel@712 { + reg =3D ; + label =3D "pm8550b_wls_vin_div_16"; + qcom,pre-scaling =3D <1 16>; + }; + + channel@744 { + reg =3D ; + label =3D "battery_temp"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + }; + + channel@747 { + reg =3D ; + label =3D "pcba_at_heat_sink_fins"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + }; + + channel@78e { + reg =3D ; + label =3D "pm8550b_vph_pwr"; + qcom,pre-scaling =3D <1 3>; + }; + + channel@78f { + reg =3D ; + label =3D "pm8550b_vbat_sns_qbg"; + qcom,pre-scaling =3D <1 6>; + }; +}; + +&pon_pwrkey { + status =3D "okay"; +}; + +&pon_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&qupv3_id_0 { + firmware-name =3D "qcom/sm8650/qupv3fw.elf"; + + status =3D "okay"; +}; + +&qupv3_id_1 { + firmware-name =3D "qcom/sm8650/qupv3fw.elf"; + + status =3D "okay"; +}; + +&sdhc_2 { + cd-gpios =3D <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; + + vmmc-supply =3D <&vreg_l9b_2p9>; + vqmmc-supply =3D <&vreg_l8b_1p8>; + bus-width =3D <4>; + no-sdio; + no-mmc; + + pinctrl-0 =3D <&sdc2_default>, <&sdc2_card_det_n>; + pinctrl-1 =3D <&sdc2_sleep>, <&sdc2_card_det_n>; + pinctrl-names =3D "default", "sleep"; + + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32764>; +}; + +&tlmm { + bt_default: bt-default-state { + bt-en-pins { + pins =3D "gpio17"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + + sw-ctrl-pins { + pins =3D "gpio18"; + function =3D "gpio"; + bias-pull-down; + }; + }; + + i2c4_default: i2c4-default-state { + pins =3D "gpio48", "gpio49"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + i2c5_default: i2c5-default-state { + pins =3D "gpio52", "gpio53"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + l_spkr_irq_default: l-spkr-irq-state-state { + pins =3D "gpio77"; + function =3D "gpio"; + bias-pull-up; + }; + + r_spkr_irq_default: r-spkr-irq-default-state { + pins =3D "gpio186"; + function =3D "gpio"; + bias-pull-up; + }; + + wlan_en: wlan-en-state { + pins =3D "gpio16"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-down; + }; +}; + +&uart14 { + status =3D "okay"; + + bluetooth { + compatible =3D "qcom,wcn7850-bt"; + + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn>; + vddaon-supply =3D <&vreg_pmu_aon_0p59>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p8>; + + max-speed =3D <3200000>; + }; +}; + +&uart15 { + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l17b_2p5>; + vcc-max-microamp =3D <1300000>; + vccq-supply =3D <&vreg_l1c_1p2>; + vccq-max-microamp =3D <1200000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l1d_0p9>; + vdda-pll-supply =3D <&vreg_l3i_1p2>; + + status =3D "okay"; +}; + +&usb_1 { + dr_mode =3D "peripheral"; + + /* USB 2.0 only */ + qcom,select-utmi-as-pipe-clk; + maximum-speed =3D "high-speed"; + + /* Remove USB3 phy */ + phys =3D <&usb_1_hsphy>; + phy-names =3D "usb2-phy"; + + status =3D "okay"; +}; + +&usb_1_hsphy { + vdd-supply =3D <&vreg_l1i_0p88>; + vdda12-supply =3D <&vreg_l3i_1p2>; + + phys =3D <&pm8550b_eusb2_repeater>; + + status =3D "okay"; +}; + +&xo_board { + clock-frequency =3D <76800000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index b679fd8afb7d..9988b269b20f 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -1907,7 +1907,7 @@ llcc_lpi_mem: llcc-lpi@ff800000 { }; }; =20 - smp2p-adsp { + smp2p_adsp: smp2p-adsp { compatible =3D "qcom,smp2p"; =20 interrupts-extended =3D <&ipcc IPCC_CLIENT_LPASS @@ -1933,7 +1933,7 @@ smp2p_adsp_in: slave-kernel { }; }; =20 - smp2p-cdsp { + smp2p_cdsp: smp2p-cdsp { compatible =3D "qcom,smp2p"; =20 interrupts-extended =3D <&ipcc IPCC_CLIENT_CDSP @@ -1959,7 +1959,7 @@ smp2p_cdsp_in: slave-kernel { }; }; =20 - smp2p-modem { + smp2p_modem: smp2p-modem { compatible =3D "qcom,smp2p"; =20 interrupts-extended =3D <&ipcc IPCC_CLIENT_MPSS --=20 2.34.1