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The XPCS resides in an Ethernet power domain and requires its CSR clock for register access, so require the clock and power-domain resources for this compatible. Signed-off-by: Mohd Ayaan Anwar Tested-by: Zhangfei Gao --- .../devicetree/bindings/net/pcs/snps,dw-xpcs.yaml | 17 +++++++++++++= ++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/net/pcs/snps,dw-xpcs.yaml b/= Documentation/devicetree/bindings/net/pcs/snps,dw-xpcs.yaml index e77eec9ac9ee08d2e11a28975f61f8c36b4e0a95..68bb941cbb290d29bbd94d7280b= 89d2ad0f38e7a 100644 --- a/Documentation/devicetree/bindings/net/pcs/snps,dw-xpcs.yaml +++ b/Documentation/devicetree/bindings/net/pcs/snps,dw-xpcs.yaml @@ -22,6 +22,17 @@ description: by means of the APB3/MCI interfaces. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Serge Semin , Andrew Lunn , Heiner Kallweit , Russell King , Richard Cochran , Bjorn Andersson , Konrad Dybcio , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Maxime Chevallier , Maxime Coquelin Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Lorenzo Bianconi , Shawn Guo , Zhangfei Gao , Jitendra Vegiraju , Mohd Ayaan Anwar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790125674; l=7650; i=mohd.anwar@oss.qualcomm.com; s=20250907; h=from:subject:message-id; bh=ec5frk+YtDQMLnumPZGZWsIFPqUU4OVg7LaYLxO10tQ=; b=Oe2dGKX5HImnogO3tEsFXNOVtvfzBGrsRPstHAhtUaSNg2Y/WyV5elH2n/DazKr0XJ9avzejN NzAt93U2jOAD2PcZlv9wQDR54sdI4vmZyVYij5lJIyA/l013If1HqL/ X-Developer-Key: i=mohd.anwar@oss.qualcomm.com; a=ed25519; pk=7JNY72mz7r6hQstsamPYlUbLhQ5+W64pY4LgfSh9DJU= X-Proofpoint-GUID: Rn0m7KOMXuT-YVJEVprI8lfssUM2zH_e X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIzMDAwNCBTYWx0ZWRfX9j/10qfmfwAg /EPNaoV5+hqwyu9dT/zInPconozukFDaKdnGRKEMIuEBuL4g12pjwv2rNnOqRE1y5gJgwNacqBr OKs8qV51jOkoEBwixaYbnUgLHo0uf2k= X-Proofpoint-ORIG-GUID: Rn0m7KOMXuT-YVJEVprI8lfssUM2zH_e X-Authority-Analysis: v=2.4 cv=eIOGH3p1 c=1 sm=1 tr=0 ts=6ab32688 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=CxBzW-8FhjC1KXsKZjIA:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIzMDAwNCBTYWx0ZWRfXzvOA/J42mxfa t3B9qga2e9g0rEmRyUN2ZvUJh+OgqMPXC9Z5pKu0BrffqBm9ZffaoDXmjAFxb/+WDpkDujahb07 g4ctoDjrDpqucyF+WlD9DDPtZb2hEV80MqHAUf6n7SYibKAT9EgjIVC7ZsMPXNT3ycVaFZY5yoX qCQt6pl4jRmjeABYXl4gadYNgnU89rbMD+OiC26XYmumu8aQJUlh1H1t6Frhtjcb0zbb3t7Nqjp naHkNYN24MUeLhf0JHYIRsB7dp5/bWkMIm3/XztHf9ApZxZXB3mHcJby3MYsZ9wQ2x4WitfF9R1 iZVIEsD9b6AAaaKoHkFcbWn0X26fTABIsfAgFSbYcScZQR7orL5XDoi+OpsknxDqVgueJWHjJD2 MafUr1af+kTEeCiBnA+PihfWMMdEbCVmVuSmlAx3bpRiOazniYYB6EljPsdmDTvpaTA5Xfzmy+t Fr3KSNNQfwjSyeazTUA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-22_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609230004 The generic DesignWare XPCS support currently associates USXGMII with Clause 73 auto-negotiation. The XPCS integration on Qualcomm Nord instead uses the vendor MII register block and Clause 37 control and status for USXGMII. Add a separate Clause 37 USXGMII mode which configures the PCS for BASE-R, enables single-port 10G-SXGMII operation and enables PHY-side Clause 37 auto-negotiation. Also decode the negotiated link, speed and duplex from the vendor Clause 37 status register. This supports 10 Mbps through 10 Gbps link rates exposed by the USXGMII status fields. Signed-off-by: Mohd Ayaan Anwar Tested-by: Zhangfei Gao --- drivers/net/pcs/pcs-xpcs.c | 113 +++++++++++++++++++++++++++++++++++++++= ++++ drivers/net/pcs/pcs-xpcs.h | 15 ++++++ include/linux/pcs/pcs-xpcs.h | 1 + 3 files changed, 129 insertions(+) diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index 0337e2bcc01258e102a649e3b7fce41c65a3dd05..7f5c7a275630f2b064e4b9abdd6= c3619e9346cec 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -283,6 +283,7 @@ static int xpcs_soft_reset(struct dw_xpcs *xpcs, switch (compat->an_mode) { case DW_AN_C73: case DW_10GBASER: + case DW_AN_C37_USXGMII: dev =3D MDIO_MMD_PCS; break; case DW_AN_C37_SGMII: @@ -355,6 +356,54 @@ static int xpcs_read_fault_c73(struct dw_xpcs *xpcs, return 0; } =20 +static int xpcs_config_aneg_c37_usxgmii(struct dw_xpcs *xpcs) +{ + u16 mask, val; + int ret; + + /* Select BASE-R PCS mode. */ + ret =3D xpcs_modify(xpcs, MDIO_MMD_PCS, MDIO_CTRL2, + DW_PCS_TYPE_SEL, MDIO_PCS_CTRL2_10GBR); + if (ret < 0) + return ret; + + /* Enable USXGMII before accessing the MII MMD registers. */ + ret =3D xpcs_modify_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, + DW_USXGMII_EN, DW_USXGMII_EN); + if (ret < 0) + return ret; + + /* Select single-port 10G-SXGMII mode. */ + ret =3D xpcs_modify_vpcs(xpcs, DW_VR_XS_PCS_KR_CTRL, + DW_USXG_MODE_SEL, + FIELD_PREP(DW_USXG_MODE_SEL, + DW_USXG_MODE_10G_SXGMII)); + if (ret < 0) + return ret; + + /* Disable Clause 37 AN before changing its configuration. */ + ret =3D xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, + BMCR_ANENABLE, 0); + if (ret < 0) + return ret; + + /* Configure USXGMII per XPCS databook section 7.6. */ + mask =3D DW_VR_MII_AN_CTRL_8BIT | DW_VR_MII_SGMII_LINK_STS | + DW_VR_MII_TX_CONFIG_MASK | DW_VR_MII_PCS_MODE_MASK | + DW_VR_MII_AN_INTR_EN; + val =3D FIELD_PREP(DW_VR_MII_TX_CONFIG_MASK, + DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII) | + DW_VR_MII_SGMII_LINK_STS; + + ret =3D xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, + mask, val); + if (ret < 0) + return ret; + + return xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, + BMCR_ANENABLE, BMCR_ANENABLE); +} + static void xpcs_link_up_usxgmii(struct dw_xpcs *xpcs, int speed) { int ret, speed_sel; @@ -687,6 +736,7 @@ static unsigned int xpcs_inband_caps(struct phylink_pcs= *pcs, =20 case DW_10GBASER: case DW_2500BASEX: + case DW_AN_C37_USXGMII: return LINK_INBAND_DISABLE; =20 default: @@ -950,6 +1000,11 @@ static int xpcs_do_config(struct dw_xpcs *xpcs, phy_i= nterface_t interface, if (ret) return ret; break; + case DW_AN_C37_USXGMII: + ret =3D xpcs_config_aneg_c37_usxgmii(xpcs); + if (ret) + return ret; + break; case DW_2500BASEX: ret =3D xpcs_config_2500basex(xpcs); if (ret) @@ -1158,6 +1213,58 @@ static int xpcs_get_state_2500basex(struct dw_xpcs *= xpcs, return 0; } =20 +static int xpcs_get_state_c37_usxgmii(struct dw_xpcs *xpcs, + struct phylink_link_state *state) +{ + u16 speed; + int ret; + + state->link =3D false; + state->an_complete =3D false; + state->speed =3D SPEED_UNKNOWN; + state->duplex =3D DUPLEX_UNKNOWN; + state->pause =3D 0; + + ret =3D xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS); + if (ret < 0) + return ret; + + state->an_complete =3D !!(ret & DW_VR_MII_AN_STS_C37_ANCMPLT_INTR); + state->link =3D !!(ret & DW_VR_MII_USXG_LINK); + if (!state->link) + return 0; + + speed =3D FIELD_GET(DW_VR_MII_USXG_SPEED, ret); + switch (speed) { + case DW_VR_MII_USXG_SPEED_10: + state->speed =3D SPEED_10; + break; + case DW_VR_MII_USXG_SPEED_100: + state->speed =3D SPEED_100; + break; + case DW_VR_MII_USXG_SPEED_1000: + state->speed =3D SPEED_1000; + break; + case DW_VR_MII_USXG_SPEED_10000: + state->speed =3D SPEED_10000; + break; + case DW_VR_MII_USXG_SPEED_2500: + state->speed =3D SPEED_2500; + break; + case DW_VR_MII_USXG_SPEED_5000: + state->speed =3D SPEED_5000; + break; + default: + state->link =3D false; + return 0; + } + + state->duplex =3D ret & DW_VR_MII_USXG_FULL ? + DUPLEX_FULL : DUPLEX_HALF; + + return 0; +} + static void xpcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, struct phylink_link_state *state) { @@ -1191,6 +1298,12 @@ static void xpcs_get_state(struct phylink_pcs *pcs, = unsigned int neg_mode, dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", "xpcs_get_state_c37_1000basex", ERR_PTR(ret)); break; + case DW_AN_C37_USXGMII: + ret =3D xpcs_get_state_c37_usxgmii(xpcs, state); + if (ret) + dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", + "xpcs_get_state_c37_usxgmii", ERR_PTR(ret)); + break; case DW_2500BASEX: ret =3D xpcs_get_state_2500basex(xpcs, state); if (ret) diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h index 929fa238445ed550677850b9b89149e952ac9fd6..cbf583ff55ba0884efb9c8b63a0= 7154628ee5ea2 100644 --- a/drivers/net/pcs/pcs-xpcs.h +++ b/drivers/net/pcs/pcs-xpcs.h @@ -13,6 +13,7 @@ #define DW_VENDOR BIT(15) =20 /* VR_XS_PCS */ +#define DW_PCS_TYPE_SEL GENMASK(3, 0) #define DW_USXGMII_RST BIT(10) #define DW_USXGMII_EN BIT(9) #define DW_VR_XS_PCS_DIG_CTRL1 0x0000 @@ -20,6 +21,9 @@ #define DW_EN_VSMMD1 BIT(13) #define DW_CL37_BP BIT(12) #define DW_VR_XS_PCS_DIG_STS 0x0010 +#define DW_VR_XS_PCS_KR_CTRL 0x0007 +#define DW_USXG_MODE_SEL GENMASK(12, 10) +#define DW_USXG_MODE_10G_SXGMII 0 #define DW_RXFIFO_ERR GENMASK(6, 5) #define DW_PSEQ_ST GENMASK(4, 2) #define DW_PSEQ_ST_GOOD FIELD_PREP(GENMASK(4, 2), 0x4) @@ -68,6 +72,7 @@ #define DW_VR_MII_PCS_MODE_C37_1000BASEX 0x0 #define DW_VR_MII_PCS_MODE_C37_SGMII 0x2 #define DW_VR_MII_AN_INTR_EN BIT(0) +#define DW_VR_MII_SGMII_LINK_STS BIT(4) =20 #define DW_VR_MII_AN_INTR_STS 0x8002 #define DW_VR_MII_AN_STS_C37_ANCMPLT_INTR BIT(0) @@ -78,6 +83,16 @@ #define DW_VR_MII_C37_ANSGM_SP_1000 0x2 #define DW_VR_MII_C37_ANSGM_SP_LNKSTS BIT(4) =20 +#define DW_VR_MII_USXG_LINK BIT(14) +#define DW_VR_MII_USXG_FULL BIT(13) +#define DW_VR_MII_USXG_SPEED GENMASK(12, 10) +#define DW_VR_MII_USXG_SPEED_10 0 +#define DW_VR_MII_USXG_SPEED_100 1 +#define DW_VR_MII_USXG_SPEED_1000 2 +#define DW_VR_MII_USXG_SPEED_10000 3 +#define DW_VR_MII_USXG_SPEED_2500 4 +#define DW_VR_MII_USXG_SPEED_5000 5 + #define DW_VR_MII_EEE_MCTRL0 0x8006 #define DW_VR_MII_EEE_LTX_EN BIT(0) /* LPI Tx Enable */ #define DW_VR_MII_EEE_LRX_EN BIT(1) /* LPI Rx Enable */ diff --git a/include/linux/pcs/pcs-xpcs.h b/include/linux/pcs/pcs-xpcs.h index 36073f7b6bb40e02c523112f79b3c55838a778e2..4ea995b70150e33e1e1a47cc7aa= 324c53742fbdc 100644 --- a/include/linux/pcs/pcs-xpcs.h +++ b/include/linux/pcs/pcs-xpcs.h @@ -20,6 +20,7 @@ #define DW_2500BASEX 3 #define DW_AN_C37_1000BASEX 4 #define DW_10GBASER 5 +#define DW_AN_C37_USXGMII 6 =20 enum dw_xpcs_pcs_id { DW_XPCS_ID_NATIVE =3D 0, --=20 2.34.1 From nobody Thu Sep 24 14:28:11 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7ADF3331ED6 for ; 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Allow the platform driver to use optional register read and write callbacks for both Clause 22 and Clause 45 accesses, while retaining the existing access paths when no callbacks are supplied. Signed-off-by: Mohd Ayaan Anwar Tested-by: Zhangfei Gao --- drivers/net/pcs/pcs-xpcs-plat.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/net/pcs/pcs-xpcs-plat.c b/drivers/net/pcs/pcs-xpcs-pla= t.c index e669a7b248ac4677aeb5cd1874108f5c87f837d2..e78a233fb198d940951064a71e8= 597c6c666bc9d 100644 --- a/drivers/net/pcs/pcs-xpcs-plat.c +++ b/drivers/net/pcs/pcs-xpcs-plat.c @@ -24,8 +24,16 @@ /* Page select register for the indirect MMIO CSRs access */ #define DW_VR_CSR_VIEWPORT 0xff =20 +struct dw_xpcs_plat_ops { + int (*reg_read)(struct platform_device *pdev, void __iomem *reg_base, + int dev, int reg); + int (*reg_write)(struct platform_device *pdev, void __iomem *reg_base, + int dev, int reg, u16 val); +}; + struct dw_xpcs_plat { struct platform_device *pdev; + const struct dw_xpcs_plat_ops *ops; struct mii_bus *bus; bool reg_indir; int reg_width; @@ -169,6 +177,10 @@ static int xpcs_mmio_read_c22(struct mii_bus *bus, int= addr, int reg) if (addr !=3D 0) return -ENODEV; =20 + if (pxpcs->ops) + return pxpcs->ops->reg_read(pxpcs->pdev, pxpcs->reg_base, + MDIO_MMD_VEND2, reg); + if (pxpcs->reg_indir) return xpcs_mmio_read_reg_indirect(pxpcs, MDIO_MMD_VEND2, reg); else @@ -182,6 +194,10 @@ static int xpcs_mmio_write_c22(struct mii_bus *bus, in= t addr, int reg, u16 val) if (addr !=3D 0) return -ENODEV; =20 + if (pxpcs->ops) + return pxpcs->ops->reg_write(pxpcs->pdev, pxpcs->reg_base, + MDIO_MMD_VEND2, reg, val); + if (pxpcs->reg_indir) return xpcs_mmio_write_reg_indirect(pxpcs, MDIO_MMD_VEND2, reg, val); else @@ -195,6 +211,10 @@ static int xpcs_mmio_read_c45(struct mii_bus *bus, int= addr, int dev, int reg) if (addr !=3D 0) return -ENODEV; =20 + if (pxpcs->ops) + return pxpcs->ops->reg_read(pxpcs->pdev, pxpcs->reg_base, + dev, reg); + if (pxpcs->reg_indir) return xpcs_mmio_read_reg_indirect(pxpcs, dev, reg); else @@ -209,6 +229,10 @@ static int xpcs_mmio_write_c45(struct mii_bus *bus, in= t addr, int dev, if (addr !=3D 0) return -ENODEV; =20 + if (pxpcs->ops) + return pxpcs->ops->reg_write(pxpcs->pdev, pxpcs->reg_base, + dev, reg, val); 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Add accessors that translate MMD accesses to the Nord windows: MMD 3 (PCS), standard registers: SR_XS at 0x0000 MMD 3 (PCS), vendor registers: VR_XS at 0x2000 MMD 1 (PMA/PMD): SR_PMA at 0x3000 MMD 31 (VEND2), standard regs: SR_MII at 0x4000 MMD 31 (VEND2), vendor registers: VR_MII at 0x5000 Each register uses a 32-bit MMIO stride. The vendor bit is removed from the register index before calculating a vendor-window offset. Select these accessors using the Nord synthetic XPCS ID, allow its smaller direct-MMIO resource, and add the Nord USXGMII Clause 37 compatibility. Signed-off-by: Mohd Ayaan Anwar Tested-by: Zhangfei Gao --- drivers/net/pcs/Makefile | 3 +- drivers/net/pcs/pcs-xpcs-plat.c | 17 +++++++- drivers/net/pcs/pcs-xpcs-qcom.c | 86 +++++++++++++++++++++++++++++++++++++= ++++ drivers/net/pcs/pcs-xpcs-qcom.h | 16 ++++++++ drivers/net/pcs/pcs-xpcs.c | 13 +++++++ include/linux/pcs/pcs-xpcs.h | 1 + 6 files changed, 134 insertions(+), 2 deletions(-) diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile index 4f7920618b90051e839a74a7101aaaf055a77f74..3d7cf1a5cd0783078edcefc6dfe= c626af469495d 100644 --- a/drivers/net/pcs/Makefile +++ b/drivers/net/pcs/Makefile @@ -2,7 +2,8 @@ # Makefile for Linux PCS drivers =20 pcs_xpcs-$(CONFIG_PCS_XPCS) :=3D pcs-xpcs.o pcs-xpcs-plat.o \ - pcs-xpcs-nxp.o pcs-xpcs-wx.o + pcs-xpcs-nxp.o pcs-xpcs-qcom.o \ + pcs-xpcs-wx.o =20 obj-$(CONFIG_PCS_XPCS) +=3D pcs_xpcs.o obj-$(CONFIG_PCS_LYNX) +=3D pcs-lynx.o diff --git a/drivers/net/pcs/pcs-xpcs-plat.c b/drivers/net/pcs/pcs-xpcs-pla= t.c index e78a233fb198d940951064a71e8597c6c666bc9d..e013a5253a22651220e62352d03= faabc3a3c3658 100644 --- a/drivers/net/pcs/pcs-xpcs-plat.c +++ b/drivers/net/pcs/pcs-xpcs-plat.c @@ -20,6 +20,7 @@ #include =20 #include "pcs-xpcs.h" +#include "pcs-xpcs-qcom.h" =20 /* Page select register for the indirect MMIO CSRs access */ #define DW_VR_CSR_VIEWPORT 0xff @@ -239,8 +240,14 @@ static int xpcs_mmio_write_c45(struct mii_bus *bus, in= t addr, int dev, return xpcs_mmio_write_reg_direct(pxpcs, dev, reg, val); } =20 +static const struct dw_xpcs_plat_ops xpcs_qcom_ops =3D { + .reg_read =3D xpcs_qcom_reg_read, + .reg_write =3D xpcs_qcom_reg_write, +}; + static struct dw_xpcs_plat *xpcs_plat_create_data(struct platform_device *= pdev) { + const struct dw_xpcs_info *info; struct dw_xpcs_plat *pxpcs; =20 pxpcs =3D devm_kzalloc(&pdev->dev, sizeof(*pxpcs), GFP_KERNEL); @@ -248,6 +255,12 @@ static struct dw_xpcs_plat *xpcs_plat_create_data(stru= ct platform_device *pdev) return ERR_PTR(-ENOMEM); =20 pxpcs->pdev =3D pdev; + info =3D device_get_match_data(&pdev->dev); + if (!info) + return ERR_PTR(-EINVAL); + + if (info->pcs =3D=3D QCOM_NORD_XPCS_ID) + pxpcs->ops =3D &xpcs_qcom_ops; =20 dev_set_drvdata(&pdev->dev, pxpcs); =20 @@ -285,7 +298,7 @@ static int xpcs_plat_init_res(struct dw_xpcs_plat *pxpc= s) else spc_size =3D pxpcs->reg_width * SZ_2M; =20 - if (resource_size(res) < spc_size) { + if (!pxpcs->ops && resource_size(res) < spc_size) { dev_err(dev, "Invalid reg-space size\n"); return -EINVAL; } @@ -452,8 +465,10 @@ DW_XPCS_INFO_DECLARE(xpcs_pma_gen4_3g, DW_XPCS_ID_NATI= VE, DW_XPCS_PMA_GEN4_3G_ID DW_XPCS_INFO_DECLARE(xpcs_pma_gen4_6g, DW_XPCS_ID_NATIVE, DW_XPCS_PMA_GEN4= _6G_ID); DW_XPCS_INFO_DECLARE(xpcs_pma_gen5_10g, DW_XPCS_ID_NATIVE, DW_XPCS_PMA_GEN= 5_10G_ID); DW_XPCS_INFO_DECLARE(xpcs_pma_gen5_12g, DW_XPCS_ID_NATIVE, DW_XPCS_PMA_GEN= 5_12G_ID); +DW_XPCS_INFO_DECLARE(xpcs_qcom_nord, QCOM_NORD_XPCS_ID, DW_XPCS_PMA_ID_NAT= IVE); =20 static const struct of_device_id xpcs_of_ids[] =3D { + { .compatible =3D "qcom,nord-dw-xpcs", .data =3D &xpcs_qcom_nord }, { .compatible =3D "snps,dw-xpcs", .data =3D &xpcs_generic }, { .compatible =3D "snps,dw-xpcs-gen1-3g", .data =3D &xpcs_pma_gen1_3g }, { .compatible =3D "snps,dw-xpcs-gen2-3g", .data =3D &xpcs_pma_gen2_3g }, diff --git a/drivers/net/pcs/pcs-xpcs-qcom.c b/drivers/net/pcs/pcs-xpcs-qco= m.c new file mode 100644 index 0000000000000000000000000000000000000000..63c95c951454819b62eb3fd00ab= cc6b529e2004b --- /dev/null +++ b/drivers/net/pcs/pcs-xpcs-qcom.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Qualcomm DesignWare XPCS platform helpers + * + * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +#include "pcs-xpcs.h" +#include "pcs-xpcs-qcom.h" + +/* Qualcomm Nord direct MMIO XPCS windows. */ +#define QCOM_XPCS_SR_XS_BASE 0x0000 +#define QCOM_XPCS_VR_XS_BASE 0x2000 +#define QCOM_XPCS_SR_PMA_BASE 0x3000 +#define QCOM_XPCS_SR_MII_BASE 0x4000 +#define QCOM_XPCS_VR_MII_BASE 0x5000 + +static int xpcs_qcom_reg_offset(int dev, int reg) +{ + switch (dev) { + case MDIO_MMD_PCS: + if (reg & DW_VENDOR) + return QCOM_XPCS_VR_XS_BASE + + ((reg & ~DW_VENDOR) << 2); + + return QCOM_XPCS_SR_XS_BASE + (reg << 2); + + case MDIO_MMD_PMAPMD: + return QCOM_XPCS_SR_PMA_BASE + (reg << 2); + + case MDIO_MMD_VEND2: + if (reg >=3D DW_VENDOR) + return QCOM_XPCS_VR_MII_BASE + + ((reg - DW_VENDOR) << 2); + + return QCOM_XPCS_SR_MII_BASE + (reg << 2); + + default: + return -EOPNOTSUPP; + } +} + +int xpcs_qcom_reg_read(struct platform_device *pdev, void __iomem *reg_bas= e, + int dev, int reg) +{ + int offset, ret; + + offset =3D xpcs_qcom_reg_offset(dev, reg); + if (offset < 0) + return offset; + + ret =3D pm_runtime_resume_and_get(&pdev->dev); + if (ret < 0) + return ret; + + ret =3D readl(reg_base + offset) & 0xffff; + + pm_runtime_put(&pdev->dev); + + return ret; +} + +int xpcs_qcom_reg_write(struct platform_device *pdev, void __iomem *reg_ba= se, + int dev, int reg, u16 val) +{ + int offset, ret; + + offset =3D xpcs_qcom_reg_offset(dev, reg); + if (offset < 0) + return offset; + + ret =3D pm_runtime_resume_and_get(&pdev->dev); + if (ret < 0) + return ret; + + writel(val, reg_base + offset); + + pm_runtime_put(&pdev->dev); + + return 0; +} diff --git a/drivers/net/pcs/pcs-xpcs-qcom.h b/drivers/net/pcs/pcs-xpcs-qco= m.h new file mode 100644 index 0000000000000000000000000000000000000000..a1084f6a10a96baa8ba0d192ee6= 4cdaed90da125 --- /dev/null +++ b/drivers/net/pcs/pcs-xpcs-qcom.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __PCS_XPCS_QCOM_H +#define __PCS_XPCS_QCOM_H + +#include +#include + +struct platform_device; + +int xpcs_qcom_reg_read(struct platform_device *pdev, void __iomem *reg_bas= e, + int dev, int reg); +int xpcs_qcom_reg_write(struct platform_device *pdev, void __iomem *reg_ba= se, + int dev, int reg, u16 val); + +#endif /* __PCS_XPCS_QCOM_H */ diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index 7f5c7a275630f2b064e4b9abdd6c3619e9346cec..1f556b4f7c44f06f24a2f724734= d3a7d71424de3 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -1571,6 +1571,15 @@ static const struct dw_xpcs_compat nxp_sja1110_xpcs_= compat[] =3D { } }; =20 +static const struct dw_xpcs_compat qcom_nord_xpcs_compat[] =3D { + { + .interface =3D PHY_INTERFACE_MODE_USXGMII, + .supported =3D xpcs_usxgmii_features, + .an_mode =3D DW_AN_C37_USXGMII, + }, { + } +}; + static const struct dw_xpcs_desc xpcs_desc_list[] =3D { { .id =3D DW_XPCS_ID, @@ -1584,6 +1593,10 @@ static const struct dw_xpcs_desc xpcs_desc_list[] = =3D { .id =3D NXP_SJA1110_XPCS_ID, .mask =3D DW_XPCS_ID_MASK, .compat =3D nxp_sja1110_xpcs_compat, + }, { + .id =3D QCOM_NORD_XPCS_ID, + .mask =3D DW_XPCS_ID_MASK, + .compat =3D qcom_nord_xpcs_compat, }, }; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Serge Semin , Andrew Lunn , Heiner Kallweit , Russell King , Richard Cochran , Bjorn Andersson , Konrad Dybcio , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Maxime Chevallier , Maxime Coquelin Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Lorenzo Bianconi , Shawn Guo , Zhangfei Gao , Jitendra Vegiraju , Mohd Ayaan Anwar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790125674; l=1703; i=mohd.anwar@oss.qualcomm.com; s=20250907; h=from:subject:message-id; bh=6L0tBYyplIQ6seGPWW4VFRe9yuGstOvOQquYgeMV1tk=; b=z3cMy7Tu8YHBAgVXBHBIIhABLigrMPxhWRGWgadww+VwRWN+w7Titd/SaYgoc53VgWiAjo5Ar wlhZvZF5Eb2C7XVC7uM3dKyoY9gjV2ZuDMXUWq4G02oNKHRWgzghSxL X-Developer-Key: i=mohd.anwar@oss.qualcomm.com; a=ed25519; pk=7JNY72mz7r6hQstsamPYlUbLhQ5+W64pY4LgfSh9DJU= X-Proofpoint-GUID: odRcGLUve45YoAevuObO9A8GUclTjann X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIzMDAwNCBTYWx0ZWRfX5X4RgqCnH8lV 05dzmwRonZKjuTIYzXe0yEN+khmzoRIYEtOdQn7PhsgQOLsZlgoBdpxcCbIGmhHZD4uWNKc9gwJ gmGWgfa646uStV9M7ESrJEeZ/xhi29w0n7kTLcw8vUcNSyUYLFGqVcyfS572pIJcjx3Xlr4i/lK Y87m+if5Qbn3UljynGmw+ZELFGKwIQQ5Ytw+ewvVZl2gZByOvTJ7RxROrjUysZkaXChbyMToyRp E1bsbFlzhWeNkIZ7xbbUYgXRFR8/azN1kXXfLyo/xSRG4MMmCPaBlGpFY8VGXTkq8URCM3QIASL u5vNu5oNB9AUmvn0sdeAo0DBfIV9LbNvgAc+oSaB3Vp7YfJp26ETiK4LAjOoI3TqqsFKN/z+Ppx sEUCChVgxNN1gC9Qq/2a1eVa54qoBPumhsBMZrmJF5ePiQTAji5GCrsWgAuqyq0CmFmhOaHRDJC Zo2wpS1kl4YRM9lAm6g== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIzMDAwNCBTYWx0ZWRfX3xSHlqSa9E4g m3hiX8Sv/MQE3mQJ9ylMHUuMzBwMyQx5MqlICpZkp05FDy2YqfYUxoZupBlrAFsPll0LS/g8RAb szBe0Zr3glJThxcI0hmZlpFwZ7Gw4XY= X-Authority-Analysis: v=2.4 cv=QsDLTlyd c=1 sm=1 tr=0 ts=6ab326a4 cx=c_pps a=SvEPeNj+VMjHSW//kvnxuw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=_2kQZa-5yrNbEit3ZwwA:9 a=QEXdDO2ut3YA:10 a=Kq8ClHjjuc5pcCNDwlU0:22 X-Proofpoint-ORIG-GUID: odRcGLUve45YoAevuObO9A8GUclTjann X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-22_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 lowpriorityscore=0 phishscore=0 bulkscore=0 suspectscore=0 impostorscore=0 adultscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609230004 xpcs_plat_init_clk() acquires the optional CSR clock but does not prepare or enable it. Marking the device runtime-active at that point makes the PM core assume that the hardware is already powered. On Nord, once the XPCS CSR clock was described, the first pm_runtime_resume_and_get() accessed XPCS registers without invoking runtime_resume() to enable the clock. The matching runtime put then invoked runtime_suspend() and attempted to disable a clock which was never enabled, producing an already-disabled clock warning. Initialize the runtime-PM state as suspended instead. The first register access now runs the resume callback and enables the CSR clock, while the subsequent suspend callback performs the matching disable. Check and propagate the state-transition error as part of probe. Signed-off-by: Mohd Ayaan Anwar Tested-by: Zhangfei Gao --- drivers/net/pcs/pcs-xpcs-plat.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/pcs/pcs-xpcs-plat.c b/drivers/net/pcs/pcs-xpcs-pla= t.c index e013a5253a22651220e62352d03faabc3a3c3658..328c50940d46eb8e7bea06ecd1a= 20214e3cde61c 100644 --- a/drivers/net/pcs/pcs-xpcs-plat.c +++ b/drivers/net/pcs/pcs-xpcs-plat.c @@ -322,7 +322,11 @@ static int xpcs_plat_init_clk(struct dw_xpcs_plat *pxp= cs) return dev_err_probe(dev, PTR_ERR(pxpcs->cclk), "Failed to get CSR clock\n"); =20 - pm_runtime_set_active(dev); + ret =3D pm_runtime_set_suspended(dev); + if (ret) + return dev_err_probe(dev, ret, + "Failed to set runtime-PM suspended state\n"); + ret =3D devm_pm_runtime_enable(dev); if (ret) { dev_err(dev, "Failed to enable runtime-PM\n"); --=20 2.34.1 From nobody Thu Sep 24 14:28:11 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A7FC33374F for ; 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Each controller has five clocks, one power domain and ten SMMU stream mappings. Due to a hardware quirk, PCS link-up depends on the EEE clock being enabled. Add the Nord compatible and describe its platform-specific resource requirements. Also add Nord to the common DWMAC schema exceptions used by Qualcomm ETHQOS platforms. Signed-off-by: Mohd Ayaan Anwar Tested-by: Zhangfei Gao --- .../devicetree/bindings/net/qcom,ethqos.yaml | 57 +++++++++++++++++-= ---- .../devicetree/bindings/net/snps,dwmac.yaml | 2 + 2 files changed, 48 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/net/qcom,ethqos.yaml b/Docum= entation/devicetree/bindings/net/qcom,ethqos.yaml index 423959cb928d945aa3e758a3c803d12bd61ec42b..41de2ccd56458ed20620905d5d3= 716b3d2568531 100644 --- a/Documentation/devicetree/bindings/net/qcom,ethqos.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ethqos.yaml @@ -11,11 +11,33 @@ maintainers: - Konrad Dybcio =20 description: - dwmmac based Qualcomm ethernet devices which support Gigabit - ethernet (version v2.3.0 and onwards). + DWMAC and XGMAC based Qualcomm Ethernet devices supporting Gigabit and + multi-gigabit Ethernet. =20 allOf: - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + const: qcom,nord-ethqos + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + clock-names: + minItems: 5 + maxItems: 5 + iommus: + minItems: 10 + maxItems: 10 + required: + - power-domains + else: + properties: + iommus: + maxItems: 1 =20 properties: compatible: @@ -30,6 +52,7 @@ properties: - const: qcom,sa8775p-ethqos - enum: - qcom,qcs404-ethqos + - qcom,nord-ethqos - qcom,sa8775p-ethqos - qcom,sc8280xp-ethqos - qcom,sm8150-ethqos @@ -57,19 +80,31 @@ properties: - const: sfty =20 clocks: - maxItems: 4 + minItems: 4 + maxItems: 5 =20 clock-names: - items: - - const: stmmaceth - - const: pclk - - const: ptp_ref - - enum: - - rgmii - - phyaux + oneOf: + - items: + - const: stmmaceth + - const: pclk + - const: ptp_ref + - const: phyaux + - const: eee + description: | + Due to a hardware quirk, PCS link-up depends on the EEE clock + being enabled. + - items: + - const: stmmaceth + - const: pclk + - const: ptp_ref + - enum: + - rgmii + - phyaux =20 iommus: - maxItems: 1 + minItems: 1 + maxItems: 10 =20 dma-coherent: true =20 diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Docume= ntation/devicetree/bindings/net/snps,dwmac.yaml index 0ff9e3284a06124cb0a3ee62e2ea6d0b1f7f646d..e8c2911d9817cdf64e426a5a02d= 5f335a0fb8241 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -72,6 +72,7 @@ properties: - nuvoton,ma35d1-dwmac - nxp,s32g2-dwmac - qcom,qcs404-ethqos + - qcom,nord-ethqos - qcom,sa8775p-ethqos - qcom,sc8280xp-ethqos - qcom,sm8150-ethqos @@ -631,6 +632,7 @@ allOf: - ingenic,x1830-mac - ingenic,x2000-mac - qcom,qcs404-ethqos + - qcom,nord-ethqos - qcom,sa8775p-ethqos - qcom,sc8280xp-ethqos - qcom,sm8150-ethqos --=20 2.34.1 From nobody Thu Sep 24 14:28:11 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49572331EAB for ; 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Tue, 22 Sep 2026 18:09:08 -0700 (PDT) Received: from hu-mohdayaa-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-144f98ca0edsm1651831c88.15.2026.09.22.18.08.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 18:09:08 -0700 (PDT) From: Mohd Ayaan Anwar Date: Wed, 23 Sep 2026 06:37:33 +0530 Subject: [PATCH RFC net-next 7/9] net: stmmac: support custom XGMAC register layouts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-qcom_xpcs_nord_emac-v1-7-4b1c682af70f@oss.qualcomm.com> References: <20260923-qcom_xpcs_nord_emac-v1-0-4b1c682af70f@oss.qualcomm.com> In-Reply-To: <20260923-qcom_xpcs_nord_emac-v1-0-4b1c682af70f@oss.qualcomm.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Serge Semin , Andrew Lunn , Heiner Kallweit , Russell King , Richard Cochran , Bjorn Andersson , Konrad Dybcio , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Maxime Chevallier , Maxime Coquelin Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Lorenzo Bianconi , Shawn Guo , Zhangfei Gao , Jitendra Vegiraju , Mohd Ayaan Anwar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790125674; l=33913; i=mohd.anwar@oss.qualcomm.com; s=20250907; h=from:subject:message-id; bh=Q8l5Sr+CX7uKNMpGw/xh0jS3YpNEPwMl8DIF3WPxkQ0=; b=hVX85UDmYnKhUdVI/yfVKuTDe9rYYSJ0CWjwr7c7bHJLZxBjMMAixPjQJxxIykCjCNMarExtc MLA2rk9/JLaDgHmJF9b42AHz+WbFGBmiVHpkLuPREDaQAjyaY/4JTFe X-Developer-Key: i=mohd.anwar@oss.qualcomm.com; a=ed25519; pk=7JNY72mz7r6hQstsamPYlUbLhQ5+W64pY4LgfSh9DJU= X-Proofpoint-ORIG-GUID: SbzxKE0AWehIwGkgME3x4Jvtu1lcC4vm X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIzMDAwNCBTYWx0ZWRfXxzhEJx8QZI2M OTLH7cpLAVnbCNLrO2pwGN2ovyCTrSPcQb9vcWDEdMJeu+unqK2OUicOwcqHRFELa1taO9YCSbY weFXLVE2afafn3/UObaWRhkXwkDoqNc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIzMDAwNCBTYWx0ZWRfX2UXTR1shdUb6 9QClk/EVeAdyVcb2NpotbFPuRsXnQ9eRjxikJD117ICbrQpw1elF+xcvkXTKBZwt7f8aUM5dvqu sxTGMZnruVLRuyHoD56KHN9s/ZLjoGj8zdLhqi1rAd9/v25ZD571NyeE6jsXbI4QzsHi8Td1imX r471PZQ8mjGym0/U8eINL7GshprGn/PLBR0gtwvG0UjSw2X+l6jA/ORlzrSZ5PYJquJUE+2LJX9 oF3xyPmqnHn4W6SZj9SqFPAWqM5YGiwidJSFY+3JCwnlENNJdvnHHskiGgH9sWaIvV4qhiTFYXo jUmN15E3G6kkb8NrSVHoVg3Wyz7tvc3DQxoIt9N/cg/HzKqZQs+md+kt2ofH94Nz6KSizJLsWT5 ark77HYP5RGi2KVc4KHMXqzPSsWEC6SRDV+0i+HLZshJUHTMbcJp36LMTDV1odfWkHnnNfA8EdC IbZ6FULfJQPOrZ1qxBg== X-Authority-Analysis: v=2.4 cv=N828hG9B c=1 sm=1 tr=0 ts=6ab326b6 cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=5_JtQBAtEWauNnNKQqgA:9 a=QEXdDO2ut3YA:10 a=vr4QvYf-bLy2KjpDp97w:22 X-Proofpoint-GUID: SbzxKE0AWehIwGkgME3x4Jvtu1lcC4vm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-22_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 malwarescore=0 adultscore=0 spamscore=0 impostorscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609230004 Some XGMAC integrations place their MTL queues and DMA channels at different offsets from the standard register layout. Allow platform data to override these addresses while retaining the standard layout by default. This follows the approach used by commit 33719b57f52e ("net: stmmac: dwmac4: Allow platforms to specify some DMA/MTL offsets"). Qualcomm XGMAC hardware similarly uses differently aligned queue and channel registers. Also allow platforms to override the timestamp register base. Signed-off-by: Mohd Ayaan Anwar Tested-by: Zhangfei Gao --- drivers/net/ethernet/stmicro/stmmac/common.h | 1 + .../net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 2 +- drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 94 ++++++++++----- .../net/ethernet/stmicro/stmmac/dwxgmac2_core.c | 34 +++--- drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 128 +++++++++++++----= ---- drivers/net/ethernet/stmicro/stmmac/hwif.c | 5 +- .../net/ethernet/stmicro/stmmac/stmmac_ethtool.c | 5 +- drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c | 15 ++- include/linux/stmmac.h | 11 ++ 9 files changed, 193 insertions(+), 102 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/eth= ernet/stmicro/stmmac/common.h index 1729fb29ece3853584bc27ed541413bcba88c695..c6387cecaf5d93ef10c45475a53= 3bf1d0a4e0b45 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h @@ -622,6 +622,7 @@ struct mac_device_info { const struct stmmac_mmc_ops *mmc; const struct stmmac_est_ops *est; const struct stmmac_vlan_ops *vlan; + const struct dwxgmac_addrs *dwxgmac_addrs; struct dw_xpcs *xpcs; struct phylink_pcs *phylink_pcs; struct mii_regs mii; /* MII register Addresses */ diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/= net/ethernet/stmicro/stmmac/dwmac-socfpga.c index 1d7f0a57d28897005cdc1c5dcbd3c2f737a6c967..331ba38abae66f03b69c383b307= 62c9a09735a37 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c @@ -365,7 +365,7 @@ static int smtg_crosststamp(ktime_t *device, struct sys= tem_counterval_t *system, }; =20 num_snapshot =3D FIELD_GET(XGMAC_TIMESTAMP_ATSNS_MASK, - readl(ioaddr + XGMAC_TIMESTAMP_STATUS)); + readl(ioaddr + XGMAC_TIMESTAMP_STATUS(NULL))); =20 /* Repeat until the timestamps are from the FIFO last segment */ for (i =3D 0; i < num_snapshot; i++) { diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/e= thernet/stmicro/stmmac/dwxgmac2.h index f8ab347f7b5b9e1b2df662785bb25cf875456088..22b476358a2028de862186c3d38= 295b2d48d87d6 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -220,12 +220,21 @@ #define XGMAC_CT BIT(1) #define XGMAC_OB BIT(0) #define XGMAC_RSS_DATA 0x00000c8c -#define XGMAC_TIMESTAMP_STATUS 0x00000d20 + +/* Timestamp registers */ +#define XGMAC_TIMESTAMP_BASE_ADDR 0x00000d00 + +static inline u32 xgmac_timestamp_base_addr(const struct dwxgmac_addrs *ad= drs) +{ + return addrs ? addrs->timestamp_base : XGMAC_TIMESTAMP_BASE_ADDR; +} + +#define XGMAC_TIMESTAMP_STATUS(a) (xgmac_timestamp_base_addr(a) + 0x20) #define XGMAC_TIMESTAMP_ATSNS_MASK GENMASK(29, 25) #define XGMAC_TXTSC BIT(15) -#define XGMAC_TXTIMESTAMP_NSEC 0x00000d30 +#define XGMAC_TXTIMESTAMP_NSEC(a) (xgmac_timestamp_base_addr(a) + 0x30) #define XGMAC_TXTSSTSLO GENMASK(30, 0) -#define XGMAC_TXTIMESTAMP_SEC 0x00000d34 +#define XGMAC_TXTIMESTAMP_SEC(a) (xgmac_timestamp_base_addr(a) + 0x34) #define XGMAC_PPS_CONTROL 0x00000d70 #define XGMAC_PPS_MAXIDX(x) ((((x) + 1) * 8) - 1) #define XGMAC_PPS_MINIDX(x) ((x) * 8) @@ -285,37 +294,49 @@ #define XGMAC_MTL_ECC_INT_STATUS 0x000010cc #define XGMAC_MTL_DPP_CONTROL 0x000010e0 #define XGMAC_DPP_DISABLE BIT(0) -#define XGMAC_MTL_TXQ_OPMODE(x) (0x00001100 + (0x80 * (x))) + +/* MTL per-queue registers */ +#define XGMAC_MTL_CHAN_BASE_ADDR 0x00001100 +#define XGMAC_MTL_CHAN_OFFSET 0x80 + +static inline u32 +xgmac_mtl_chanx_base_addr(const struct dwxgmac_addrs *addrs, u32 x) +{ + return addrs ? addrs->mtl_chan_base + x * addrs->mtl_chan_offset + : XGMAC_MTL_CHAN_BASE_ADDR + x * XGMAC_MTL_CHAN_OFFSET; +} + +#define XGMAC_MTL_TXQ_OPMODE(a, x) xgmac_mtl_chanx_base_addr(a, x) #define XGMAC_TQS GENMASK(25, 16) #define XGMAC_Q2TCMAP GENMASK(10, 8) #define XGMAC_TTC GENMASK(6, 4) #define XGMAC_TXQEN GENMASK(3, 2) #define XGMAC_TSF BIT(1) -#define XGMAC_MTL_TCx_ETS_CONTROL(x) (0x00001110 + (0x80 * (x))) -#define XGMAC_MTL_TCx_QUANTUM_WEIGHT(x) (0x00001118 + (0x80 * (x))) -#define XGMAC_MTL_TCx_SENDSLOPE(x) (0x0000111c + (0x80 * (x))) -#define XGMAC_MTL_TCx_HICREDIT(x) (0x00001120 + (0x80 * (x))) -#define XGMAC_MTL_TCx_LOCREDIT(x) (0x00001124 + (0x80 * (x))) +#define XGMAC_MTL_TCx_ETS_CONTROL(a, x) (xgmac_mtl_chanx_base_addr(a, x) += 0x10) +#define XGMAC_MTL_TCx_QUANTUM_WEIGHT(a, x) (xgmac_mtl_chanx_base_addr(a, x= ) + 0x18) +#define XGMAC_MTL_TCx_SENDSLOPE(a, x) (xgmac_mtl_chanx_base_addr(a, x) + = 0x1c) +#define XGMAC_MTL_TCx_HICREDIT(a, x) (xgmac_mtl_chanx_base_addr(a, x) + 0= x20) +#define XGMAC_MTL_TCx_LOCREDIT(a, x) (xgmac_mtl_chanx_base_addr(a, x) + 0= x24) #define XGMAC_CC BIT(3) #define XGMAC_TSA GENMASK(1, 0) #define XGMAC_SP (0x0 << 0) #define XGMAC_CBS (0x1 << 0) #define XGMAC_ETS (0x2 << 0) -#define XGMAC_MTL_RXQ_OPMODE(x) (0x00001140 + (0x80 * (x))) +#define XGMAC_MTL_RXQ_OPMODE(a, x) (xgmac_mtl_chanx_base_addr(a, x) + 0x4= 0) #define XGMAC_RQS GENMASK(25, 16) #define XGMAC_EHFC BIT(7) #define XGMAC_RSF BIT(5) #define XGMAC_RTC GENMASK(1, 0) -#define XGMAC_MTL_RXQ_FLOW_CONTROL(x) (0x00001150 + (0x80 * (x))) +#define XGMAC_MTL_RXQ_FLOW_CONTROL(a, x) (xgmac_mtl_chanx_base_addr(a, x) = + 0x50) #define XGMAC_RFD GENMASK(31, 17) #define XGMAC_RFA GENMASK(15, 1) -#define XGMAC_MTL_QINTEN(x) (0x00001170 + (0x80 * (x))) +#define XGMAC_MTL_QINTEN(a, x) (xgmac_mtl_chanx_base_addr(a, x) + 0x70) #define XGMAC_RXOIE BIT(16) -#define XGMAC_MTL_QINT_STATUS(x) (0x00001174 + (0x80 * (x))) +#define XGMAC_MTL_QINT_STATUS(a, x) (xgmac_mtl_chanx_base_addr(a, x) + 0x= 74) #define XGMAC_RXOVFIS BIT(16) #define XGMAC_ABPSIS BIT(1) #define XGMAC_TXUNFIS BIT(0) -#define XGMAC_MAC_REGSIZE (XGMAC_MTL_QINT_STATUS(15) / 4) +#define XGMAC_MAC_REGSIZE(a) (XGMAC_MTL_QINT_STATUS(a, 15) / 4) =20 /* DMA Registers */ #define XGMAC_DMA_MODE 0x00003000 @@ -353,28 +374,43 @@ #define XGMAC_TCEIE BIT(0) #define XGMAC_DMA_ECC_INT_STATUS 0x0000306c #define XGMAC_DMA_DPP_INT_STATUS 0x00003074 -#define XGMAC_DMA_CH_CONTROL(x) (0x00003100 + (0x80 * (x))) + +/* DMA per-channel registers */ +#define XGMAC_DMA_CHAN_BASE_ADDR 0x00003100 +#define XGMAC_DMA_CHAN_OFFSET 0x80 + +static inline u32 +xgmac_dma_chanx_base_addr(const struct dwxgmac_addrs *addrs, u32 x) +{ + if (addrs && (x & 1)) + return addrs->dma_odd_chan_base + x * addrs->dma_chan_offset; + if (addrs) + return addrs->dma_even_chan_base + x * addrs->dma_chan_offset; + return XGMAC_DMA_CHAN_BASE_ADDR + x * XGMAC_DMA_CHAN_OFFSET; +} + +#define XGMAC_DMA_CH_CONTROL(a, x) (xgmac_dma_chanx_base_addr(a, x)) #define XGMAC_SPH BIT(24) #define XGMAC_PBLx8 BIT(16) -#define XGMAC_DMA_CH_TX_CONTROL(x) (0x00003104 + (0x80 * (x))) +#define XGMAC_DMA_CH_TX_CONTROL(a, x) (xgmac_dma_chanx_base_addr(a, x) + = 0x04) #define XGMAC_EDSE BIT(28) #define XGMAC_TxPBL GENMASK(21, 16) #define XGMAC_TSE BIT(12) #define XGMAC_OSP BIT(4) #define XGMAC_TXST BIT(0) -#define XGMAC_DMA_CH_RX_CONTROL(x) (0x00003108 + (0x80 * (x))) +#define XGMAC_DMA_CH_RX_CONTROL(a, x) (xgmac_dma_chanx_base_addr(a, x) + = 0x08) #define XGMAC_RxPBL GENMASK(21, 16) #define XGMAC_RBSZ GENMASK(14, 1) #define XGMAC_RXST BIT(0) -#define XGMAC_DMA_CH_TxDESC_HADDR(x) (0x00003110 + (0x80 * (x))) -#define XGMAC_DMA_CH_TxDESC_LADDR(x) (0x00003114 + (0x80 * (x))) -#define XGMAC_DMA_CH_RxDESC_HADDR(x) (0x00003118 + (0x80 * (x))) -#define XGMAC_DMA_CH_RxDESC_LADDR(x) (0x0000311c + (0x80 * (x))) -#define XGMAC_DMA_CH_TxDESC_TAIL_LPTR(x) (0x00003124 + (0x80 * (x))) -#define XGMAC_DMA_CH_RxDESC_TAIL_LPTR(x) (0x0000312c + (0x80 * (x))) -#define XGMAC_DMA_CH_TxDESC_RING_LEN(x) (0x00003130 + (0x80 * (x))) -#define XGMAC_DMA_CH_RxDESC_RING_LEN(x) (0x00003134 + (0x80 * (x))) -#define XGMAC_DMA_CH_INT_EN(x) (0x00003138 + (0x80 * (x))) +#define XGMAC_DMA_CH_TxDESC_HADDR(a, x) (xgmac_dma_chanx_base_addr(a, x) += 0x10) +#define XGMAC_DMA_CH_TxDESC_LADDR(a, x) (xgmac_dma_chanx_base_addr(a, x) += 0x14) +#define XGMAC_DMA_CH_RxDESC_HADDR(a, x) (xgmac_dma_chanx_base_addr(a, x) += 0x18) +#define XGMAC_DMA_CH_RxDESC_LADDR(a, x) (xgmac_dma_chanx_base_addr(a, x) += 0x1c) +#define XGMAC_DMA_CH_TxDESC_TAIL_LPTR(a, x) (xgmac_dma_chanx_base_addr(a, = x) + 0x24) +#define XGMAC_DMA_CH_RxDESC_TAIL_LPTR(a, x) (xgmac_dma_chanx_base_addr(a, = x) + 0x2c) +#define XGMAC_DMA_CH_TxDESC_RING_LEN(a, x) (xgmac_dma_chanx_base_addr(a, x= ) + 0x30) +#define XGMAC_DMA_CH_RxDESC_RING_LEN(a, x) (xgmac_dma_chanx_base_addr(a, x= ) + 0x34) +#define XGMAC_DMA_CH_INT_EN(a, x) (xgmac_dma_chanx_base_addr(a, x) + 0x38) #define XGMAC_NIE BIT(15) #define XGMAC_AIE BIT(14) #define XGMAC_RBUE BIT(7) @@ -385,9 +421,9 @@ XGMAC_RIE | XGMAC_TIE) #define XGMAC_DMA_INT_DEFAULT_RX (XGMAC_RIE) #define XGMAC_DMA_INT_DEFAULT_TX (XGMAC_TIE) -#define XGMAC_DMA_CH_Rx_WATCHDOG(x) (0x0000313c + (0x80 * (x))) +#define XGMAC_DMA_CH_Rx_WATCHDOG(a, x) (xgmac_dma_chanx_base_addr(a, x) += 0x3c) #define XGMAC_RWT GENMASK(7, 0) -#define XGMAC_DMA_CH_STATUS(x) (0x00003160 + (0x80 * (x))) +#define XGMAC_DMA_CH_STATUS(a, x) (xgmac_dma_chanx_base_addr(a, x) + 0x60) #define XGMAC_NIS BIT(15) #define XGMAC_AIS BIT(14) #define XGMAC_FBE BIT(12) @@ -396,7 +432,7 @@ #define XGMAC_TBU BIT(2) #define XGMAC_TPS BIT(1) #define XGMAC_TI BIT(0) -#define XGMAC_REGSIZE ((0x0000317c + (0x80 * 15)) / 4) +#define XGMAC_REGSIZE(a) ((xgmac_dma_chanx_base_addr(a, 15) + 0x7c) / 4) =20 #define XGMAC_DMA_STATUS_MSK_COMMON (XGMAC_NIS | XGMAC_AIS | XGMAC_FBE) #define XGMAC_DMA_STATUS_MSK_RX (XGMAC_RBU | XGMAC_RI | \ diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/= net/ethernet/stmicro/stmmac/dwxgmac2_core.c index 1a88cbaed70ca18bbb714681569ede863f7130e5..d1099a1cf9ea56661e2beceeaa3= f1938e51dfb3c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c @@ -234,11 +234,11 @@ static void dwxgmac2_prog_mtl_tx_algorithms(struct ma= c_device_info *hw, =20 /* Set ETS if desired */ for (i =3D 0; i < MTL_MAX_TX_QUEUES; i++) { - value =3D readl(ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(i)); + value =3D readl(ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(hw->dwxgmac_addrs, i)= ); value &=3D ~XGMAC_TSA; if (ets) value |=3D XGMAC_ETS; - writel(value, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(i)); + writel(value, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(hw->dwxgmac_addrs, i)); } } =20 @@ -246,9 +246,10 @@ static void dwxgmac2_set_mtl_tx_queue_weight(struct st= mmac_priv *priv, struct mac_device_info *hw, u32 weight, u32 queue) { + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; void __iomem *ioaddr =3D hw->pcsr; =20 - writel(weight, ioaddr + XGMAC_MTL_TCx_QUANTUM_WEIGHT(queue)); + writel(weight, ioaddr + XGMAC_MTL_TCx_QUANTUM_WEIGHT(addrs, queue)); } =20 static void dwxgmac2_map_mtl_to_dma(struct mac_device_info *hw, u32 queue, @@ -273,18 +274,19 @@ static void dwxgmac2_config_cbs(struct stmmac_priv *p= riv, u32 send_slope, u32 idle_slope, u32 high_credit, u32 low_credit, u32 queue) { + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; void __iomem *ioaddr =3D hw->pcsr; u32 value; =20 - writel(send_slope, ioaddr + XGMAC_MTL_TCx_SENDSLOPE(queue)); - writel(idle_slope, ioaddr + XGMAC_MTL_TCx_QUANTUM_WEIGHT(queue)); - writel(high_credit, ioaddr + XGMAC_MTL_TCx_HICREDIT(queue)); - writel(low_credit, ioaddr + XGMAC_MTL_TCx_LOCREDIT(queue)); + writel(send_slope, ioaddr + XGMAC_MTL_TCx_SENDSLOPE(addrs, queue)); + writel(idle_slope, ioaddr + XGMAC_MTL_TCx_QUANTUM_WEIGHT(addrs, queue)); + writel(high_credit, ioaddr + XGMAC_MTL_TCx_HICREDIT(addrs, queue)); + writel(low_credit, ioaddr + XGMAC_MTL_TCx_LOCREDIT(addrs, queue)); =20 - value =3D readl(ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(queue)); + value =3D readl(ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(addrs, queue)); value &=3D ~XGMAC_TSA; value |=3D XGMAC_CC | XGMAC_CBS; - writel(value, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(queue)); + writel(value, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(addrs, queue)); } =20 static void dwxgmac2_dump_regs(struct mac_device_info *hw, u32 *reg_space) @@ -292,7 +294,7 @@ static void dwxgmac2_dump_regs(struct mac_device_info *= hw, u32 *reg_space) void __iomem *ioaddr =3D hw->pcsr; int i; =20 - for (i =3D 0; i < XGMAC_MAC_REGSIZE; i++) + for (i =3D 0; i < XGMAC_MAC_REGSIZE(hw->dwxgmac_addrs); i++) reg_space[i] =3D readl(ioaddr + i * 4); } =20 @@ -336,18 +338,19 @@ static int dwxgmac2_host_irq_status(struct stmmac_pri= v *priv, static int dwxgmac2_host_mtl_irq_status(struct stmmac_priv *priv, struct mac_device_info *hw, u32 chan) { + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; void __iomem *ioaddr =3D hw->pcsr; int ret =3D 0; u32 status; =20 status =3D readl(ioaddr + XGMAC_MTL_INT_STATUS); if (status & BIT(chan)) { - u32 chan_status =3D readl(ioaddr + XGMAC_MTL_QINT_STATUS(chan)); + u32 chan_status =3D readl(ioaddr + XGMAC_MTL_QINT_STATUS(addrs, chan)); =20 if (chan_status & XGMAC_RXOVFIS) ret |=3D CORE_IRQ_MTL_RX_OVERFLOW; =20 - writel(~0x0, ioaddr + XGMAC_MTL_QINT_STATUS(chan)); + writel(~0x0, ioaddr + XGMAC_MTL_QINT_STATUS(addrs, chan)); } =20 return ret; @@ -1143,14 +1146,15 @@ static int dwxgmac3_rxp_config(void __iomem *ioaddr, static int dwxgmac2_get_mac_tx_timestamp(struct mac_device_info *hw, u64 *= ts) { void __iomem *ioaddr =3D hw->pcsr; + const struct dwxgmac_addrs *addrs =3D hw->dwxgmac_addrs; u32 value; =20 - if (readl_poll_timeout_atomic(ioaddr + XGMAC_TIMESTAMP_STATUS, + if (readl_poll_timeout_atomic(ioaddr + XGMAC_TIMESTAMP_STATUS(addrs), value, value & XGMAC_TXTSC, 100, 10000)) return -EBUSY; =20 - *ts =3D readl(ioaddr + XGMAC_TXTIMESTAMP_NSEC) & XGMAC_TXTSSTSLO; - *ts +=3D readl(ioaddr + XGMAC_TXTIMESTAMP_SEC) * 1000000000ULL; + *ts =3D readl(ioaddr + XGMAC_TXTIMESTAMP_NSEC(addrs)) & XGMAC_TXTSSTSLO; + *ts +=3D readl(ioaddr + XGMAC_TXTIMESTAMP_SEC(addrs)) * 1000000000ULL; return 0; } =20 diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/n= et/ethernet/stmicro/stmmac/dwxgmac2_dma.c index ff83858ebc1f33aa8092a2d83018bd5f96b7eead..65d5e2a828076563a1c7368124d= dda226bfffc7a 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -47,13 +47,14 @@ static void dwxgmac2_dma_init_chan(struct stmmac_priv *= priv, void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, u32 chan) { - u32 value =3D readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; + u32 value =3D readl(ioaddr + XGMAC_DMA_CH_CONTROL(addrs, chan)); =20 if (dma_cfg->pblx8) value |=3D XGMAC_PBLx8; =20 - writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan)); - writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); + writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(addrs, chan)); + writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(addrs, chan= )); } =20 static void dwxgmac2_dma_init_rx_chan(struct stmmac_priv *priv, @@ -61,15 +62,16 @@ static void dwxgmac2_dma_init_rx_chan(struct stmmac_pri= v *priv, struct stmmac_dma_cfg *dma_cfg, dma_addr_t phy, u32 chan) { + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; u32 rxpbl =3D dma_cfg->rxpbl ?: dma_cfg->pbl; u32 value; =20 - value =3D readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); + value =3D readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(addrs, chan)); value =3D u32_replace_bits(value, rxpbl, XGMAC_RxPBL); - writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); + writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(addrs, chan)); =20 - writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan)); - writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan)); + writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(addrs, chan= )); + writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(addrs, chan= )); } =20 static void dwxgmac2_dma_init_tx_chan(struct stmmac_priv *priv, @@ -77,15 +79,16 @@ static void dwxgmac2_dma_init_tx_chan(struct stmmac_pri= v *priv, struct stmmac_dma_cfg *dma_cfg, dma_addr_t phy, u32 chan) { + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; u32 txpbl =3D dma_cfg->txpbl ?: dma_cfg->pbl; u32 value; =20 - value =3D readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); + value =3D readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(addrs, chan)); value =3D u32_replace_bits(value, txpbl, XGMAC_TxPBL); - writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); + writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(addrs, chan)); =20 - writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan)); - writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan)); + writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(addrs, chan= )); + writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(addrs, chan= )); } =20 static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) @@ -118,16 +121,18 @@ static void dwxgmac2_dma_axi(void __iomem *ioaddr, st= ruct stmmac_axi *axi) static void dwxgmac2_dma_dump_regs(struct stmmac_priv *priv, void __iomem *ioaddr, u32 *reg_space) { + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; int i; =20 - for (i =3D (XGMAC_DMA_MODE / 4); i < XGMAC_REGSIZE; i++) + for (i =3D (XGMAC_DMA_MODE / 4); i < XGMAC_REGSIZE(addrs); i++) reg_space[i] =3D readl(ioaddr + i * 4); } =20 static void dwxgmac2_dma_rx_mode(struct stmmac_priv *priv, void __iomem *i= oaddr, int mode, u32 channel, int fifosz, u8 qmode) { - u32 value =3D readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; + u32 value =3D readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(addrs, channel)); unsigned int rqs =3D fifosz / 256 - 1; unsigned int rtc; =20 @@ -149,7 +154,7 @@ static void dwxgmac2_dma_rx_mode(struct stmmac_priv *pr= iv, void __iomem *ioaddr, value =3D u32_replace_bits(value, rqs, XGMAC_RQS); =20 if ((fifosz >=3D 4096) && (qmode !=3D MTL_QUEUE_AVB)) { - u32 flow =3D readl(ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel)); + u32 flow =3D readl(ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(addrs, channel)); unsigned int rfd, rfa; =20 value |=3D XGMAC_EHFC; @@ -178,16 +183,17 @@ static void dwxgmac2_dma_rx_mode(struct stmmac_priv *= priv, void __iomem *ioaddr, flow =3D u32_replace_bits(flow, rfd, XGMAC_RFD); flow =3D u32_replace_bits(flow, rfa, XGMAC_RFA); =20 - writel(flow, ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel)); + writel(flow, ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(addrs, channel)); } =20 - writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); + writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(addrs, channel)); } =20 static void dwxgmac2_dma_tx_mode(struct stmmac_priv *priv, void __iomem *i= oaddr, int mode, u32 channel, int fifosz, u8 qmode) { - u32 value =3D readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; + u32 value =3D readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(addrs, channel)); unsigned int tqs =3D fifosz / 256 - 1; unsigned int ttc, txqen; =20 @@ -225,45 +231,48 @@ static void dwxgmac2_dma_tx_mode(struct stmmac_priv *= priv, void __iomem *ioaddr, value =3D u32_replace_bits(value, txqen, XGMAC_TXQEN); value =3D u32_replace_bits(value, tqs, XGMAC_TQS); =20 - writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); + writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(addrs, channel)); } =20 static void dwxgmac2_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan, bool rx, bool tx) { - u32 value =3D readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan)); + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; + u32 value =3D readl(ioaddr + XGMAC_DMA_CH_INT_EN(addrs, chan)); =20 if (rx) value |=3D XGMAC_DMA_INT_DEFAULT_RX; if (tx) value |=3D XGMAC_DMA_INT_DEFAULT_TX; =20 - writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); + writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(addrs, chan)); } =20 static void dwxgmac2_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan, bool rx, bool tx) { - u32 value =3D readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan)); + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; + u32 value =3D readl(ioaddr + XGMAC_DMA_CH_INT_EN(addrs, chan)); =20 if (rx) value &=3D ~XGMAC_DMA_INT_DEFAULT_RX; if (tx) value &=3D ~XGMAC_DMA_INT_DEFAULT_TX; =20 - writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); + writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(addrs, chan)); } =20 static void dwxgmac2_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) { + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; u32 value; =20 - value =3D readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); + value =3D readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(addrs, chan)); value |=3D XGMAC_TXST; - writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); + writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(addrs, chan)); =20 value =3D readl(ioaddr + XGMAC_TX_CONFIG); value |=3D XGMAC_CONFIG_TE; @@ -273,11 +282,12 @@ static void dwxgmac2_dma_start_tx(struct stmmac_priv = *priv, static void dwxgmac2_dma_stop_tx(struct stmmac_priv *priv, void __iomem *i= oaddr, u32 chan) { + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; u32 value; =20 - value =3D readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); + value =3D readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(addrs, chan)); value &=3D ~XGMAC_TXST; - writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); + writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(addrs, chan)); =20 value =3D readl(ioaddr + XGMAC_TX_CONFIG); value &=3D ~XGMAC_CONFIG_TE; @@ -287,11 +297,12 @@ static void dwxgmac2_dma_stop_tx(struct stmmac_priv *= priv, void __iomem *ioaddr, static void dwxgmac2_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) { + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; u32 value; =20 - value =3D readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); + value =3D readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(addrs, chan)); value |=3D XGMAC_RXST; - writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); + writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(addrs, chan)); =20 value =3D readl(ioaddr + XGMAC_RX_CONFIG); value |=3D XGMAC_CONFIG_RE; @@ -301,11 +312,12 @@ static void dwxgmac2_dma_start_rx(struct stmmac_priv = *priv, static void dwxgmac2_dma_stop_rx(struct stmmac_priv *priv, void __iomem *i= oaddr, u32 chan) { + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; u32 value; =20 - value =3D readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); + value =3D readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(addrs, chan)); value &=3D ~XGMAC_RXST; - writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); + writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(addrs, chan)); } =20 static int dwxgmac2_dma_interrupt(struct stmmac_priv *priv, @@ -314,8 +326,9 @@ static int dwxgmac2_dma_interrupt(struct stmmac_priv *p= riv, u32 dir) { struct stmmac_pcpu_stats *stats =3D this_cpu_ptr(priv->xstats.pcpu_stats); - u32 intr_status =3D readl(ioaddr + XGMAC_DMA_CH_STATUS(chan)); - u32 intr_en =3D readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan)); + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; + u32 intr_status =3D readl(ioaddr + XGMAC_DMA_CH_STATUS(addrs, chan)); + u32 intr_en =3D readl(ioaddr + XGMAC_DMA_CH_INT_EN(addrs, chan)); int ret =3D 0; =20 if (dir =3D=3D DMA_DIR_RX) @@ -354,7 +367,7 @@ static int dwxgmac2_dma_interrupt(struct stmmac_priv *p= riv, } =20 /* Clear interrupts */ - writel(intr_en & intr_status, ioaddr + XGMAC_DMA_CH_STATUS(chan)); + writel(intr_en & intr_status, ioaddr + XGMAC_DMA_CH_STATUS(addrs, chan)); =20 return ret; } @@ -483,105 +496,120 @@ static int dwxgmac2_get_hw_feature(void __iomem *io= addr, static void dwxgmac2_rx_watchdog(struct stmmac_priv *priv, void __iomem *i= oaddr, u32 riwt, u32 queue) { - writel(riwt & XGMAC_RWT, ioaddr + XGMAC_DMA_CH_Rx_WATCHDOG(queue)); + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; + + writel(riwt & XGMAC_RWT, ioaddr + XGMAC_DMA_CH_Rx_WATCHDOG(addrs, queue)); } =20 static void dwxgmac2_set_rx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr, u32 len, u32 chan) { - writel(len, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(chan)); + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; + + writel(len, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(addrs, chan)); } =20 static void dwxgmac2_set_tx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr, u32 len, u32 chan) { - writel(len, ioaddr + XGMAC_DMA_CH_TxDESC_RING_LEN(chan)); + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; + + writel(len, ioaddr + XGMAC_DMA_CH_TxDESC_RING_LEN(addrs, chan)); } =20 static void dwxgmac2_set_rx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr, u32 ptr, u32 chan) { - writel(ptr, ioaddr + XGMAC_DMA_CH_RxDESC_TAIL_LPTR(chan)); + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; + + writel(ptr, ioaddr + XGMAC_DMA_CH_RxDESC_TAIL_LPTR(addrs, chan)); } =20 static void dwxgmac2_set_tx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr, u32 ptr, u32 chan) { - writel(ptr, ioaddr + XGMAC_DMA_CH_TxDESC_TAIL_LPTR(chan)); + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; + + writel(ptr, ioaddr + XGMAC_DMA_CH_TxDESC_TAIL_LPTR(addrs, chan)); } =20 static void dwxgmac2_enable_tso(struct stmmac_priv *priv, void __iomem *io= addr, bool en, u32 chan) { - u32 value =3D readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; + u32 value =3D readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(addrs, chan)); =20 if (en) value |=3D XGMAC_TSE; else value &=3D ~XGMAC_TSE; =20 - writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); + writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(addrs, chan)); } =20 static void dwxgmac2_qmode(struct stmmac_priv *priv, void __iomem *ioaddr, u32 channel, u8 qmode) { - u32 value =3D readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; + u32 value =3D readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(addrs, channel)); u32 flow =3D readl(ioaddr + XGMAC_RX_FLOW_CTRL); unsigned int txqen; =20 if (qmode !=3D MTL_QUEUE_AVB) { txqen =3D 0x2; - writel(0, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(channel)); + writel(0, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(addrs, channel)); } else { txqen =3D 0x1; writel(flow & (~XGMAC_RFE), ioaddr + XGMAC_RX_FLOW_CTRL); } =20 value =3D u32_replace_bits(value, txqen, XGMAC_TXQEN); - writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); + writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(addrs, channel)); } =20 static void dwxgmac2_set_bfsize(struct stmmac_priv *priv, void __iomem *io= addr, int bfsize, u32 chan) { + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; u32 value; =20 - value =3D readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); + value =3D readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(addrs, chan)); value =3D u32_replace_bits(value, bfsize, XGMAC_RBSZ); - writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); + writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(addrs, chan)); } =20 static void dwxgmac2_enable_sph(struct stmmac_priv *priv, void __iomem *io= addr, bool en, u32 chan) { + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; u32 value =3D readl(ioaddr + XGMAC_RX_CONFIG); =20 value &=3D ~XGMAC_CONFIG_HDSMS; value |=3D XGMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */ writel(value, ioaddr + XGMAC_RX_CONFIG); =20 - value =3D readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); + value =3D readl(ioaddr + XGMAC_DMA_CH_CONTROL(addrs, chan)); if (en) value |=3D XGMAC_SPH; else value &=3D ~XGMAC_SPH; - writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan)); + writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(addrs, chan)); } =20 static int dwxgmac2_enable_tbs(struct stmmac_priv *priv, void __iomem *ioa= ddr, bool en, u32 chan) { - u32 value =3D readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); + const struct dwxgmac_addrs *addrs =3D priv->plat->dwxgmac_addrs; + u32 value =3D readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(addrs, chan)); =20 if (en) value |=3D XGMAC_EDSE; else value &=3D ~XGMAC_EDSE; =20 - writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); + writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(addrs, chan)); =20 - value =3D readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)) & XGMAC_EDSE; + value =3D readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(addrs, chan)) & XGMAC_ED= SE; if (en && !value) return -EIO; =20 diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.c b/drivers/net/ether= net/stmicro/stmmac/hwif.c index 265671170bf6e3856263fdcf99afbf3eac79a211..fdae241e5cf49a8d7a15aadb67d= 40700ab5b4429 100644 --- a/drivers/net/ethernet/stmicro/stmmac/hwif.c +++ b/drivers/net/ethernet/stmicro/stmmac/hwif.c @@ -368,8 +368,11 @@ int stmmac_hwif_init(struct stmmac_priv *priv) mac->vlan =3D mac->vlan ? : entry->vlan; =20 priv->hw =3D mac; + mac->dwxgmac_addrs =3D priv->plat->dwxgmac_addrs; priv->fpe_cfg.reg =3D entry->regs.fpe_reg; - priv->ptpaddr =3D priv->ioaddr + entry->regs.ptp_off; + priv->ptpaddr =3D priv->ioaddr + + (priv->plat->dwxgmac_addrs ? + priv->plat->dwxgmac_addrs->timestamp_base : entry->regs.ptp_off); priv->mmcaddr =3D priv->ioaddr + entry->regs.mmc_off; memcpy(&priv->ptp_clock_ops, entry->ptp, sizeof(struct ptp_clock_info)); diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c b/drivers= /net/ethernet/stmicro/stmmac/stmmac_ethtool.c index 1cf0f8820b337a0d7a9aa23c7d9b34e3f5616dad..82ce81fb6a18b66f2028a5a7784= f0a3b9317b9bc 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c @@ -351,8 +351,9 @@ static int stmmac_ethtool_get_regs_len(struct net_devic= e *dev) { struct stmmac_priv *priv =3D netdev_priv(dev); =20 - if (priv->plat->core_type =3D=3D DWMAC_CORE_XGMAC) - return XGMAC_REGSIZE * 4; + if (priv->plat->core_type =3D=3D DWMAC_CORE_XGMAC || + priv->plat->core_type =3D=3D DWMAC_CORE_25GMAC) + return XGMAC_REGSIZE(priv->plat->dwxgmac_addrs) * 4; else if (priv->plat->core_type =3D=3D DWMAC_CORE_GMAC4) return GMAC4_REG_SPACE_SIZE; return REG_SPACE_SIZE; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c b/drivers/net= /ethernet/stmicro/stmmac/stmmac_fpe.c index c889204a7aa5d2e74f7834ed1a22252e6c51ca36..1190b8854132915905773796f07= 503a9bf1446a0 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c @@ -265,9 +265,12 @@ int dwxgmac3_fpe_map_preemption_class(struct net_devic= e *ndev, if (!num_tc) { /* Restore default TC:Queue mapping */ for (u32 i =3D 0; i < priv->plat->tx_queues_to_use; i++) { - val =3D readl(priv->ioaddr + XGMAC_MTL_TXQ_OPMODE(i)); + val =3D readl(priv->ioaddr + + XGMAC_MTL_TXQ_OPMODE(priv->plat->dwxgmac_addrs, + i)); writel(u32_replace_bits(val, i, XGMAC_Q2TCMAP), - priv->ioaddr + XGMAC_MTL_TXQ_OPMODE(i)); + priv->ioaddr + + XGMAC_MTL_TXQ_OPMODE(priv->plat->dwxgmac_addrs, i)); } } =20 @@ -288,9 +291,13 @@ int dwxgmac3_fpe_map_preemption_class(struct net_devic= e *ndev, preemptible_txqs |=3D GENMASK(offset + count - 1, offset); =20 for (u32 i =3D 0; i < count; i++) { - val =3D readl(priv->ioaddr + XGMAC_MTL_TXQ_OPMODE(offset + i)); + val =3D readl(priv->ioaddr + + XGMAC_MTL_TXQ_OPMODE(priv->plat->dwxgmac_addrs, + offset + i)); writel(u32_replace_bits(val, tc, XGMAC_Q2TCMAP), - priv->ioaddr + XGMAC_MTL_TXQ_OPMODE(offset + i)); + priv->ioaddr + + XGMAC_MTL_TXQ_OPMODE(priv->plat->dwxgmac_addrs, + offset + i)); } } =20 diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 00be2df63d2206a5865bd29333f2f3ba3442962a..5bb904030ef99ac91f66fabaa6c= 2159da1ec8811 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -188,6 +188,16 @@ struct dwmac4_addrs { u32 mtl_low_cred_offset; }; =20 +/* Address layout for XGMAC MTL, DMA, and timestamp registers */ +struct dwxgmac_addrs { + u32 dma_even_chan_base; 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Reject interfaces that are not supported by the selected PCS. Signed-off-by: Mohd Ayaan Anwar Tested-by: Zhangfei Gao --- .../net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 20 ++++++++++++++++= ++++ 1 file changed, 20 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/driv= ers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index ac7d6d3e205a1ab5b391def879d6f1033a0961b6..a99a78880c0fb7858e90b6212b3= 7ebfc7fccaf84 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "stmmac.h" #include "stmmac_platform.h" @@ -681,6 +683,21 @@ static void ethqos_ptp_clk_freq_config(struct stmmac_p= riv *priv) netdev_dbg(priv->dev, "PTP rate %lu\n", plat_dat->clk_ptp_rate); } =20 +static struct phylink_pcs * +qcom_ethqos_select_pcs(struct stmmac_priv *priv, phy_interface_t interface) +{ + struct phylink_pcs *pcs; + + if (!priv->hw->xpcs) + return ERR_PTR(-ENODEV); + + pcs =3D xpcs_to_phylink_pcs(priv->hw->xpcs); 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Serge Semin , Andrew Lunn , Heiner Kallweit , Russell King , Richard Cochran , Bjorn Andersson , Konrad Dybcio , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Maxime Chevallier , Maxime Coquelin Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Lorenzo Bianconi , Shawn Guo , Zhangfei Gao , Jitendra Vegiraju , Mohd Ayaan Anwar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790125674; l=12058; i=mohd.anwar@oss.qualcomm.com; s=20250907; h=from:subject:message-id; bh=8JCqwSbRwjzmhB8gNr/abKbRoR9Ocql+CHFLjJdWuPY=; b=XPuoKfGPn07fjZK/71e/KV5+X5ASAjWePOm1hrhsBul/IHARxgE0QWkbOocsV+BWlbydIn4fh P6vETEgK/ISCGdG/Z7aCliHPwIg3YENgz6awgJm0fQWrdyEBwhVgv9o X-Developer-Key: i=mohd.anwar@oss.qualcomm.com; a=ed25519; pk=7JNY72mz7r6hQstsamPYlUbLhQ5+W64pY4LgfSh9DJU= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIzMDAwNCBTYWx0ZWRfX7TYQKWz893cS c3qVaxSyMp5ySnnPYywu+gplKIY+vr2KUpf5ktoHjUBizRg3xDT469wI76yHR2bpYkPtqhWjaHY cqwmIGLh2sQ4qnIHykt4DbibePaY/M4qku9JprLplVeY/0GVVo6xB+AnxCgLXHaxsbxbeZ0hnF1 OJlUdY4aSSS4vD8zw4oSKC3i74eNlC/7vuVsgp1VbborKkcUqK88Zm18hsCwmHdrOzczBVROTxg 6DnpIih5huT0tDjF16R1qHAPAfxM27iW43WnW6NaiXKfarFgFDgecZopxRcpR67MfJR0zT2M4e3 bQEaN907tI9QSIaU+RhMFpfX238z6++BrYVxmkj7U4ZTa4D5WHX8B93UcFVqz1NGIKvGBnYG7tE EceNykFPl8ZLMUkEkeQ3PzARIlouojnMk2nLAsbkv0xRY8wQ3TKIMj2aTQFLVTm0++NhT9LXvwL kdROp2ulp+T7nr+/bVg== X-Authority-Analysis: v=2.4 cv=P9evFSAu c=1 sm=1 tr=0 ts=6ab326c8 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=5chfiMuH4t9yzvW4qJoA:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-ORIG-GUID: 2GJOi5sLd9vi7aAyESclDPDk4yrKZer5 X-Proofpoint-GUID: 2GJOi5sLd9vi7aAyESclDPDk4yrKZer5 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIzMDAwNCBTYWx0ZWRfX+v+0FHUm3Pqq BONbJSKJqF37mRCqVBPUkPtQcBOZ66m/oUqduA80z85cI0k/bNxlJfOm4Hwf30dZDlEfu+YSz59 v8Avmmvk4jI9W7zyp44OocoD7r3l4D0= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-22_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 phishscore=0 clxscore=1015 bulkscore=0 suspectscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609230004 Qualcomm Nord provides two ETHQOS controllers based on the Synopsys DesignWare 25GMAC IP. The Nord integration uses platform-specific MTL queue, DMA channel and timestamp register addresses. It also requires wrapper programming for USXGMII operation and an EEE clock vote for PCS link-up. Add the Nord platform data, select the DW25GMAC core, describe its register layout and configure the ETHQOS wrapper for USXGMII. Also add the platform-specific loopback control needed while the MAC is being initialized. Signed-off-by: Mohd Ayaan Anwar Tested-by: Zhangfei Gao --- .../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 142 +++++++++++++++++= +++- 1 file changed, 137 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/driv= ers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index a99a78880c0fb7858e90b6212b37ebfc7fccaf84..a03c8e203920a70238deff9f1f9= 70d29d1293893 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -23,8 +23,14 @@ #define RGMII_IO_MACRO_CONFIG2 0x1C #define RGMII_IO_MACRO_DEBUG1 0x20 #define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28 +#define RGMII_IO_MACRO_SCRATCH_2 0x44 #define EMAC_WRAPPER_SGMII_PHY_CNTRL1 0xf4 =20 +#define RGMII_IO_MACRO_BYPASS 0x16C +#define EMAC_WRAPPER_SGMII_PHY_CNTRL0 0x170 +#define EMAC_WRAPPER_SGMII_PHY_CNTRL1_V4 0x174 +#define EMAC_WRAPPER_USXGMII_MUX_SEL 0x1D0 + /* RGMII_IO_MACRO_CONFIG fields */ #define RGMII_CONFIG_FUNC_CLK_EN BIT(30) #define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23) @@ -77,6 +83,21 @@ #define RGMII_CONFIG2_RX_PROG_SWAP BIT(7) #define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6) #define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5) +#define RGMII_CONFIG2_MODE_EN_VIA_GMII BIT(21) + +/* EMAC_WRAPPER_SGMII_PHY_CNTRL0 fields */ +#define SGMII_PHY_CNTRL0_2P5G_1G_CLK_SEL GENMASK(6, 5) + +/* EMAC_WRAPPER_SGMII_PHY_CNTRL1_V4 fields */ +#define SGMII_PHY_CNTRL1_USXGMII_GMII_MASTER_CLK_MUX_SEL BIT(4) +#define SGMII_PHY_CNTRL1_RGMII_SGMII_CLK_MUX_SEL BIT(0) + +/* RGMII_IO_MACRO_BYPASS fields */ +#define RGMII_BYPASS_EN BIT(0) + +/* EMAC_WRAPPER_USXGMII_MUX_SEL fields */ +#define USXGMII_CLK_BLK_GMII_CLK_BLK_SEL BIT(1) +#define USXGMII_CLK_BLK_CLK_EN BIT(0) =20 /* EMAC_WRAPPER_SGMII_PHY_CNTRL1 bits */ #define SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN BIT(3) @@ -88,6 +109,8 @@ struct ethqos_emac_por { unsigned int value; }; =20 +struct qcom_ethqos; + struct ethqos_emac_driver_data { const struct ethqos_emac_por *rgmii_por; unsigned int num_rgmii_por; @@ -97,12 +120,16 @@ struct ethqos_emac_driver_data { const char *link_clk_name; struct dwmac4_addrs dwmac4_addrs; bool needs_sgmii_loopback; + struct dwxgmac_addrs dwxgmac_addrs; + enum dwmac_core_type core_type; + void (*set_sgmii_loopback)(struct qcom_ethqos *ethqos, bool enable); }; =20 struct qcom_ethqos { struct platform_device *pdev; void __iomem *rgmii_base; struct clk *link_clk; + struct clk *eee_clk; struct phy *serdes_phy; phy_interface_t phy_mode; =20 @@ -111,6 +138,7 @@ struct qcom_ethqos { bool rgmii_config_loopback_en; bool has_emac_ge_3; bool needs_sgmii_loopback; + void (*set_sgmii_loopback)(struct qcom_ethqos *ethqos, bool enable); }; =20 static u32 rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset) @@ -201,6 +229,15 @@ qcom_ethqos_set_sgmii_loopback(struct qcom_ethqos *eth= qos, bool enable) EMAC_WRAPPER_SGMII_PHY_CNTRL1); } =20 +static void +qcom_ethqos_set_sgmii_loopback_nord(struct qcom_ethqos *ethqos, bool enabl= e) +{ + rgmii_updatel(ethqos, + SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN, + enable ? SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN : 0, + EMAC_WRAPPER_SGMII_PHY_CNTRL1_V4); +} + static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos) { rgmii_setmask(ethqos, RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG); @@ -220,6 +257,7 @@ static const struct ethqos_emac_driver_data emac_v2_3_0= _data =3D { .num_rgmii_por =3D ARRAY_SIZE(emac_v2_3_0_por), .rgmii_config_loopback_en =3D true, .has_emac_ge_3 =3D false, + .core_type =3D DWMAC_CORE_GMAC4, }; =20 static const struct ethqos_emac_por emac_v2_1_0_por[] =3D { @@ -236,6 +274,7 @@ static const struct ethqos_emac_driver_data emac_v2_1_0= _data =3D { .num_rgmii_por =3D ARRAY_SIZE(emac_v2_1_0_por), .rgmii_config_loopback_en =3D false, .has_emac_ge_3 =3D false, + .core_type =3D DWMAC_CORE_GMAC4, }; =20 static const struct ethqos_emac_por emac_v3_0_0_por[] =3D { @@ -252,6 +291,7 @@ static const struct ethqos_emac_driver_data emac_v3_0_0= _data =3D { .num_rgmii_por =3D ARRAY_SIZE(emac_v3_0_0_por), .rgmii_config_loopback_en =3D false, .has_emac_ge_3 =3D true, + .core_type =3D DWMAC_CORE_GMAC4, .dwmac4_addrs =3D { .dma_chan =3D 0x00008100, .dma_chan_offset =3D 0x1000, @@ -286,6 +326,8 @@ static const struct ethqos_emac_driver_data emac_v4_0_0= _data =3D { .has_emac_ge_3 =3D true, .link_clk_name =3D "phyaux", .needs_sgmii_loopback =3D true, + .core_type =3D DWMAC_CORE_GMAC4, + .set_sgmii_loopback =3D qcom_ethqos_set_sgmii_loopback, .dma_addr_width =3D 36, .dwmac4_addrs =3D { .dma_chan =3D 0x00008100, @@ -485,6 +527,47 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos = *ethqos, int speed) return 0; } =20 +static void ethqos_configure_usxgmii(struct qcom_ethqos *ethqos) +{ + unsigned int i; + + for (i =3D 0; i < ethqos->num_rgmii_por; i++) + rgmii_writel(ethqos, ethqos->rgmii_por[i].value, + ethqos->rgmii_por[i].offset); + + ethqos_set_func_clk_en(ethqos); + + rgmii_updatel(ethqos, RGMII_BYPASS_EN, RGMII_BYPASS_EN, + RGMII_IO_MACRO_BYPASS); + rgmii_updatel(ethqos, RGMII_CONFIG2_MODE_EN_VIA_GMII, 0, + RGMII_IO_MACRO_CONFIG2); + rgmii_updatel(ethqos, SGMII_PHY_CNTRL0_2P5G_1G_CLK_SEL, BIT(5), + EMAC_WRAPPER_SGMII_PHY_CNTRL0); + rgmii_updatel(ethqos, SGMII_PHY_CNTRL1_RGMII_SGMII_CLK_MUX_SEL, 0, + EMAC_WRAPPER_SGMII_PHY_CNTRL1_V4); + rgmii_updatel(ethqos, SGMII_PHY_CNTRL1_USXGMII_GMII_MASTER_CLK_MUX_SEL, + SGMII_PHY_CNTRL1_USXGMII_GMII_MASTER_CLK_MUX_SEL, + EMAC_WRAPPER_SGMII_PHY_CNTRL1_V4); + + rgmii_updatel(ethqos, USXGMII_CLK_BLK_GMII_CLK_BLK_SEL, 0, + EMAC_WRAPPER_USXGMII_MUX_SEL); + rgmii_updatel(ethqos, USXGMII_CLK_BLK_CLK_EN, 0, + EMAC_WRAPPER_USXGMII_MUX_SEL); + + rgmii_updatel(ethqos, USXGMII_CLK_BLK_GMII_CLK_BLK_SEL, + USXGMII_CLK_BLK_GMII_CLK_BLK_SEL, + EMAC_WRAPPER_USXGMII_MUX_SEL); +} + +static void +ethqos_fix_mac_speed_usxgmii(void *bsp_priv, phy_interface_t interface, + int speed, unsigned int mode) +{ + struct qcom_ethqos *ethqos =3D bsp_priv; + + ethqos_configure_usxgmii(ethqos); +} + static void ethqos_fix_mac_speed_rgmii(void *bsp_priv, phy_interface_t interface, int speed, unsigned int mode) @@ -625,7 +708,8 @@ static int ethqos_mac_finish_serdes(struct net_device *= ndev, void *priv, struct qcom_ethqos *ethqos =3D priv; int ret =3D 0; =20 - qcom_ethqos_set_sgmii_loopback(ethqos, false); + if (ethqos->set_sgmii_loopback) + ethqos->set_sgmii_loopback(ethqos, false); =20 if (interface =3D=3D PHY_INTERFACE_MODE_SGMII || interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) @@ -647,14 +731,24 @@ static int ethqos_clks_config(void *priv, bool enable= d) return ret; } =20 + /* PCS link-up depends on the EEE clock due to a hardware quirk. */ + ret =3D clk_prepare_enable(ethqos->eee_clk); + if (ret) { + dev_err(ðqos->pdev->dev, "eee_clk enable failed\n"); + clk_disable_unprepare(ethqos->link_clk); + return ret; + } + /* Enable functional clock to prevent DMA reset to timeout due * to lacking PHY clock after the hardware block has been power * cycled. The actual configuration will be adjusted once * ethqos' fix_mac_speed() method is invoked. */ - qcom_ethqos_set_sgmii_loopback(ethqos, true); + if (ethqos->set_sgmii_loopback) + ethqos->set_sgmii_loopback(ethqos, true); ethqos_set_func_clk_en(ethqos); } else { + clk_disable_unprepare(ethqos->eee_clk); clk_disable_unprepare(ethqos->link_clk); } =20 @@ -738,6 +832,10 @@ static int qcom_ethqos_probe(struct platform_device *p= dev) plat_dat->fix_mac_speed =3D ethqos_fix_mac_speed_sgmii; plat_dat->mac_finish =3D ethqos_mac_finish_serdes; break; + case PHY_INTERFACE_MODE_USXGMII: + plat_dat->fix_mac_speed =3D ethqos_fix_mac_speed_usxgmii; + plat_dat->mac_finish =3D ethqos_mac_finish_serdes; + break; default: dev_err(dev, "Unsupported phy mode %s\n", phy_modes(ethqos->phy_mode)); @@ -756,12 +854,18 @@ static int qcom_ethqos_probe(struct platform_device *= pdev) ethqos->rgmii_config_loopback_en =3D data->rgmii_config_loopback_en; ethqos->has_emac_ge_3 =3D data->has_emac_ge_3; ethqos->needs_sgmii_loopback =3D data->needs_sgmii_loopback; + ethqos->set_sgmii_loopback =3D data->set_sgmii_loopback; =20 ethqos->link_clk =3D devm_clk_get(dev, data->link_clk_name ?: "rgmii"); if (IS_ERR(ethqos->link_clk)) return dev_err_probe(dev, PTR_ERR(ethqos->link_clk), "Failed to get link_clk\n"); =20 + ethqos->eee_clk =3D devm_clk_get_optional(dev, "eee"); + if (IS_ERR(ethqos->eee_clk)) + return dev_err_probe(dev, PTR_ERR(ethqos->eee_clk), + "Failed to get eee_clk\n"); + ret =3D ethqos_clks_config(ethqos, true); if (ret) return ret; @@ -778,7 +882,8 @@ static int qcom_ethqos_probe(struct platform_device *pd= ev) ethqos_set_clk_tx_rate(ethqos, NULL, plat_dat->phy_interface, SPEED_1000); =20 - qcom_ethqos_set_sgmii_loopback(ethqos, true); + if (ethqos->set_sgmii_loopback) + ethqos->set_sgmii_loopback(ethqos, true); ethqos_set_func_clk_en(ethqos); =20 /* The clocks are controlled by firmware, so we don't know for certain @@ -791,9 +896,11 @@ static int qcom_ethqos_probe(struct platform_device *p= dev) plat_dat->set_clk_tx_rate =3D ethqos_set_clk_tx_rate; plat_dat->dump_debug_regs =3D rgmii_dump; plat_dat->ptp_clk_freq_config =3D ethqos_ptp_clk_freq_config; - plat_dat->core_type =3D DWMAC_CORE_GMAC4; + plat_dat->core_type =3D data->core_type; if (ethqos->has_emac_ge_3) plat_dat->dwmac4_addrs =3D &data->dwmac4_addrs; + if (data->dwxgmac_addrs.dma_even_chan_base) + plat_dat->dwxgmac_addrs =3D &data->dwxgmac_addrs; plat_dat->pmt =3D true; if (of_property_read_bool(np, "snps,tso")) plat_dat->flags |=3D STMMAC_FLAG_TSO_EN; @@ -817,8 +924,33 @@ static int qcom_ethqos_probe(struct platform_device *p= dev) return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); } =20 +static const struct ethqos_emac_por emac_nord_por[] =3D { + { .offset =3D RGMII_IO_MACRO_CONFIG, .value =3D 0x00C04D03 }, + { .offset =3D SDCC_HC_REG_DLL_CONFIG, .value =3D 0x2004642C }, + { .offset =3D RGMII_IO_MACRO_CONFIG2, .value =3D 0x00222060 }, + { .offset =3D RGMII_IO_MACRO_SCRATCH_2, .value =3D 0x4c }, +}; + +static const struct ethqos_emac_driver_data emac_nord_data =3D { + .rgmii_por =3D emac_nord_por, + .num_rgmii_por =3D ARRAY_SIZE(emac_nord_por), + .dma_addr_width =3D 40, + .link_clk_name =3D "phyaux", + .core_type =3D DWMAC_CORE_25GMAC, + .set_sgmii_loopback =3D qcom_ethqos_set_sgmii_loopback_nord, + .dwxgmac_addrs =3D { + .dma_even_chan_base =3D 0x00008500, + .dma_odd_chan_base =3D 0x00008580, + .dma_chan_offset =3D 0x00001000, + .mtl_chan_base =3D 0x00008000, + .mtl_chan_offset =3D 0x00001000, + .timestamp_base =3D 0x00007000, + }, +}; + static const struct of_device_id qcom_ethqos_match[] =3D { - { .compatible =3D "qcom,qcs404-ethqos", .data =3D &emac_v2_3_0_data}, + { .compatible =3D "qcom,nord-ethqos", .data =3D &emac_nord_data }, + { .compatible =3D "qcom,qcs404-ethqos", .data =3D &emac_v2_3_0_data }, { .compatible =3D "qcom,sa8775p-ethqos", .data =3D &emac_v4_0_0_data}, { .compatible =3D "qcom,sc8280xp-ethqos", .data =3D &emac_v3_0_0_data}, { .compatible =3D "qcom,sm8150-ethqos", .data =3D &emac_v2_1_0_data}, --=20 2.34.1