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Signed-off-by: Mohd Ayaan Anwar Tested-by: Zhangfei Gao --- Documentation/devicetree/bindings/phy/qcom,sa8775p-dwmac-sgmii-phy.yaml | = 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sa8775p-dwmac-sgmii= -phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sa8775p-dwmac-sgmii-= phy.yaml index e573abcb937df914ced25ec87add7955bbba7b87..f2df9983d9536654e838bae4e1e= 23b832cdaea3c 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sa8775p-dwmac-sgmii-phy.ya= ml +++ b/Documentation/devicetree/bindings/phy/qcom,sa8775p-dwmac-sgmii-phy.ya= ml @@ -21,6 +21,7 @@ properties: - qcom,qcs8300-dwmac-sgmii-phy - const: qcom,sa8775p-dwmac-sgmii-phy - const: qcom,sa8775p-dwmac-sgmii-phy + - const: qcom,nord-dwmac-sgmii-phy =20 reg: items: --=20 2.34.1 From nobody Thu Sep 24 14:28:38 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 749F51E32D6 for ; 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a=ed25519-sha256; t=1790121872; l=5141; i=mohd.anwar@oss.qualcomm.com; s=20250907; h=from:subject:message-id; bh=pU4CKl40m2UEFuu7WP4zaSdVKJzbzXCSIogmQHSKiws=; b=e5w/ijuhu5rOqf/c++BwgYR9xCb2yyNNxSaZPVchajLFjhCQ8DQ5HPhC9HUijKp1AERqEKOwU kN3+ZKtTJqeD4ZLOP6MPw2a+XS3zUc3lTrYhgUpa8yEK3uY7g6SpKAs X-Developer-Key: i=mohd.anwar@oss.qualcomm.com; a=ed25519; pk=7JNY72mz7r6hQstsamPYlUbLhQ5+W64pY4LgfSh9DJU= X-Proofpoint-ORIG-GUID: F6OPmQue9hi_WTQSi8HUbufZ-0bnb67d X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIzMDAwMCBTYWx0ZWRfX3OZM+qS4403A kJtmCzD4KLRB+6cksn0FF7eZLbK4hWIFmPRLf27wvAAOyfyAXsuLGmcgimGlJ5znaAsL7qcLMeI 0HxmII8U9YR3RiZM+oMkaYF/WHOoWgQ= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIzMDAwMCBTYWx0ZWRfXzvqMS9PJLIlz jqJIGnfF9pMK09qEHK6K8dzdzEDdlbLMu4tMZpvwLFUkWS9AP5GPa5hAjcNEGLA/fsiq/j84agE koFCmsjCk/Wuf8kWKW7xKgAOksAISq9c8h2B0mYL1aJeBaO12Gd/0lwX1rY1/4F3CmyyAcG8kde Ic6iuld8mYJF7J+zLaKD14a2aR9SYk/89879FhQkiWmZD51eDS3RmUq5NnKc0zm7Ey4pjhmiB7N p0eRBKUqDRC6pwmvHsU5080zjUdZEcwCjdtFhu93IB1cfhu6bQqdjJ0RIYqLOuw2DwFkpbemPxb M/fZPvPIhKjD6OkfqeqvgmLAITTdVf3bboRVupCJJEoTb/58YjX8Uj6xVH6npuVzM6DP0gkJJt3 WsFZ7unuYeTAz8kYgjbe74AYc2n68Wb9KWPwTW2Z1uOYfC7T/y9RhOohI61OVa895AG03eWTM6i 3O4T62QyvL31SdFlhTQ== X-Authority-Analysis: v=2.4 cv=N828hG9B c=1 sm=1 tr=0 ts=6ab317a1 cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=jlbHTTSnYauNfDin9pkA:9 a=QEXdDO2ut3YA:10 a=vr4QvYf-bLy2KjpDp97w:22 X-Proofpoint-GUID: F6OPmQue9hi_WTQSi8HUbufZ-0bnb67d X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-22_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 malwarescore=0 adultscore=0 spamscore=0 impostorscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609230000 Prepare the SGMII Ethernet PHY driver for PHY modes that require a different SerDes programming sequence. Move the SGMII readiness checks into a helper so additional modes can provide their own status checks, and select the initial interface mode through per-compatible match data rather than hardcoding SGMII during probe. This does not change existing SA8775P behavior. Signed-off-by: Mohd Ayaan Anwar Tested-by: Zhangfei Gao --- drivers/phy/qualcomm/phy-qcom-sgmii-eth.c | 70 ++++++++++++++++++++-------= ---- 1 file changed, 46 insertions(+), 24 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c b/drivers/phy/qualco= mm/phy-qcom-sgmii-eth.c index 7137200c3f310a4d2642bb9bdbe3adb7589b2241..029dafacee7853648ef24afd0d9= c4b83a549badf 100644 --- a/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c +++ b/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c @@ -41,6 +41,10 @@ struct qcom_dwmac_sgmii_phy_data { phy_interface_t interface; }; =20 +struct qcom_dwmac_sgmii_phy_match_data { + phy_interface_t default_interface; +}; + static void qcom_dwmac_sgmii_phy_init_1g(struct regmap *regmap) { regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01); @@ -227,47 +231,31 @@ qcom_dwmac_sgmii_phy_poll_status(struct regmap *regma= p, unsigned int reg, val & bit, 1500, 750000); } =20 -static int qcom_dwmac_sgmii_phy_calibrate(struct phy *phy) +static int qcom_dwmac_sgmii_phy_poll_sgmii_ready(struct device *dev, + struct regmap *regmap) { - struct qcom_dwmac_sgmii_phy_data *data =3D phy_get_drvdata(phy); - struct device *dev =3D phy->dev.parent; - - switch (data->interface) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_1000BASEX: - /* 1.25Gbps mode */ - qcom_dwmac_sgmii_phy_init_1g(data->regmap); - break; - case PHY_INTERFACE_MODE_2500BASEX: - /* 3.125Gbps mode */ - qcom_dwmac_sgmii_phy_init_2p5g(data->regmap); - break; - default: - return -EINVAL; - } - - if (qcom_dwmac_sgmii_phy_poll_status(data->regmap, + if (qcom_dwmac_sgmii_phy_poll_status(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_C_READY_STATUS, QSERDES_COM_C_READY)) { dev_err(dev, "QSERDES_COM_C_READY_STATUS timed-out"); return -ETIMEDOUT; } =20 - if (qcom_dwmac_sgmii_phy_poll_status(data->regmap, + if (qcom_dwmac_sgmii_phy_poll_status(regmap, QSERDES_PCS + QPHY_PCS_PCS_READY_STATUS, QSERDES_PCS_READY)) { dev_err(dev, "PCS_READY timed-out"); return -ETIMEDOUT; } =20 - if (qcom_dwmac_sgmii_phy_poll_status(data->regmap, + if (qcom_dwmac_sgmii_phy_poll_status(regmap, QSERDES_PCS + QPHY_PCS_PCS_READY_STATUS, QSERDES_PCS_SGMIIPHY_READY)) { dev_err(dev, "SGMIIPHY_READY timed-out"); return -ETIMEDOUT; } =20 - if (qcom_dwmac_sgmii_phy_poll_status(data->regmap, + if (qcom_dwmac_sgmii_phy_poll_status(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CMN_STATUS, QSERDES_COM_C_PLL_LOCKED)) { dev_err(dev, "PLL Lock Status timed-out"); @@ -277,6 +265,28 @@ static int qcom_dwmac_sgmii_phy_calibrate(struct phy *= phy) return 0; } =20 +static int qcom_dwmac_sgmii_phy_calibrate(struct phy *phy) +{ + struct qcom_dwmac_sgmii_phy_data *data =3D phy_get_drvdata(phy); + struct device *dev =3D phy->dev.parent; + + switch (data->interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + /* 1.25Gbps mode */ + qcom_dwmac_sgmii_phy_init_1g(data->regmap); + break; + case PHY_INTERFACE_MODE_2500BASEX: + /* 3.125Gbps mode */ + qcom_dwmac_sgmii_phy_init_2p5g(data->regmap); + break; + default: + return -EINVAL; + } + + return qcom_dwmac_sgmii_phy_poll_sgmii_ready(dev, data->regmap); +} + static int qcom_dwmac_sgmii_phy_power_on(struct phy *phy) { struct qcom_dwmac_sgmii_phy_data *data =3D phy_get_drvdata(phy); @@ -374,6 +384,7 @@ static const struct regmap_config qcom_dwmac_sgmii_phy_= regmap_cfg =3D { =20 static int qcom_dwmac_sgmii_phy_probe(struct platform_device *pdev) { + const struct qcom_dwmac_sgmii_phy_match_data *match_data; struct qcom_dwmac_sgmii_phy_data *data; struct device *dev =3D &pdev->dev; struct phy_provider *provider; @@ -385,7 +396,11 @@ static int qcom_dwmac_sgmii_phy_probe(struct platform_= device *pdev) if (!data) return -ENOMEM; =20 - data->interface =3D PHY_INTERFACE_MODE_SGMII; + match_data =3D device_get_match_data(dev); + if (!match_data) + return -EINVAL; + + data->interface =3D match_data->default_interface; =20 base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) @@ -419,8 +434,15 @@ static int qcom_dwmac_sgmii_phy_probe(struct platform_= device *pdev) return 0; } =20 +static const struct qcom_dwmac_sgmii_phy_match_data sa8775p_match_data =3D= { + .default_interface =3D PHY_INTERFACE_MODE_SGMII, +}; + static const struct of_device_id qcom_dwmac_sgmii_phy_of_match[] =3D { - { .compatible =3D "qcom,sa8775p-dwmac-sgmii-phy" }, + { + .compatible =3D "qcom,sa8775p-dwmac-sgmii-phy", + .data =3D &sa8775p_match_data, + }, { }, }; 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a=ed25519-sha256; t=1790121872; l=17640; i=mohd.anwar@oss.qualcomm.com; s=20250907; h=from:subject:message-id; bh=ed4vbtYjyj1FMsT2CGuXKcms1U/AqYCuj5E6b3piyi8=; b=9iw1gS9LvwyAoNdKif9vwnYW2s9eBv5f8J589WCt1NJdKSWSH4zJpcGI+qF0ezsfDaE0sFnS1 UQOg/NmHgF3DWb36FwfkaIxoj87qJE6eVIZLxH93Qudjtao4cxN4pyu X-Developer-Key: i=mohd.anwar@oss.qualcomm.com; a=ed25519; pk=7JNY72mz7r6hQstsamPYlUbLhQ5+W64pY4LgfSh9DJU= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIzMDAwMCBTYWx0ZWRfXwpFSqGGQi+fj nyzPiJX7X+2Iu7drVR8Lmu1qEhxL/9eg1YmJmuTAGo2EI19mTECj8tMZhsF0DMNTsFlfwWBQrMs gkjuRdeDq8jLT9HIheoYcvELOltBK2LfpP4nFVla45Jb7Y9I3cs1Yxr92YSc6+/yGnQS0L6oJuC yB6LiVKonBJ9T2se2ryDznKyJUGb3J9L53dWrhhRKTBxeTNJLSTmuEVEx2dP8xqmGQwYOr4rGj+ EiEG6CDXJ1TUh+JZyxdaaRf93PLaPhtn1PXucZm6AifFSzotiqzoGT/75jllqchTa9lFIi744Ut ohApXuMU1uy0zF0sDlVj+MJEbUP/2a+tCtQhJh9YT1c6eFSe16crYZ8feClBu8EvJRdzRpqz8Xa 7pSiYmcf/PYXikmW1PdvNwJwETR38YM6QODDEYuLEzu3rnNDFFyJY08/gtBx0zeOOCWNC/k5Qje 0YRBvaXJSmq4WupVPyQ== X-Authority-Analysis: v=2.4 cv=feI4WEQF c=1 sm=1 tr=0 ts=6ab317a6 cx=c_pps a=JYo30EpNSr/tUYqK9jHPoA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=-j1QTKR700wLKSosX1UA:9 a=QEXdDO2ut3YA:10 a=Fk4IpSoW4aLDllm1B1p-:22 X-Proofpoint-GUID: sBX9baTZ8teqw2W76eajV-wI3oVcOdul X-Proofpoint-ORIG-GUID: sBX9baTZ8teqw2W76eajV-wI3oVcOdul X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIzMDAwMCBTYWx0ZWRfX11uHAxL2fpRy WyrqsthZgXtV4Rbj9BIkWtlpw8faEfEzDeDSVMqS6bEpjckSDL7oMU/67jrQb6s1pmJBNyfmkIE PqjK0dy18MN7xWno0RAlit8Q7l9MnaM= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-22_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 malwarescore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609230000 Nord uses a QMP v7 SerDes block which is an updated version of the SGMII SerDes PHY IP. The SGMII SerDes PHY supports multiple operating modes by programming different SerDes line rates. The driver currently handles SGMII and 2500BASE-X configurations only. Add support for configuring the SerDes to operate at 10.3125 Gbaud, enabling both USXGMII and 10GBASE-R PHY interface modes. Finally, add a driver compatible for Nord. Select USXGMII as the initial interface mode for Nord. phy_power_on() can run before the consumer calls set_mode(), so this ensures that the first calibration selects the 10.3125 Gbaud programming sequence. Signed-off-by: Mohd Ayaan Anwar Tested-by: Zhangfei Gao --- drivers/phy/qualcomm/phy-qcom-qmp-pcs-sgmii.h | 5 + drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v7.h | 2 + .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h | 9 ++ drivers/phy/qualcomm/phy-qcom-sgmii-eth.c | 166 +++++++++++++++++= +++- 4 files changed, 177 insertions(+), 5 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-sgmii.h b/drivers/phy/qu= alcomm/phy-qcom-qmp-pcs-sgmii.h index 4d8c962f5e0f52974f3edd5d1acdd8da535de200..67ab2fe085de3d90520cfc43cc0= ac7abaab1f21d 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-sgmii.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-sgmii.h @@ -10,11 +10,16 @@ #define QPHY_PCS_POWER_DOWN_CONTROL 0x004 #define QPHY_PCS_SW_RESET 0x008 #define QPHY_PCS_LINE_RESET_TIME 0x00c +#define QPHY_PCS_RETIME_BUFFER_EN 0x018 #define QPHY_PCS_TX_LARGE_AMP_DRV_LVL 0x020 +#define QPHY_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x024 #define QPHY_PCS_TX_SMALL_AMP_DRV_LVL 0x028 +#define QPHY_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x02c +#define QPHY_PCS_RX_SIGDET_CTRL2 0x08c #define QPHY_PCS_PCS_READY_STATUS 0x094 #define QPHY_PCS_TX_MID_TERM_CTRL1 0x0d8 #define QPHY_PCS_TX_MID_TERM_CTRL2 0x0dc +#define QPHY_PCS_SGMII_MISC_CTRL7 0x114 #define QPHY_PCS_SGMII_MISC_CTRL8 0x118 =20 #endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v7.h b/drivers/p= hy/qualcomm/phy-qcom-qmp-qserdes-com-v7.h index 7430f49214779855df1cf40acac96440957f9e6d..e8b4a26b361adab6e2b0bd3c91e= 719f84d1ffbc1 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v7.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v7.h @@ -58,6 +58,7 @@ #define QSERDES_V7_COM_CLK_ENABLE1 0xe0 #define QSERDES_V7_COM_SYS_CLK_CTRL 0xe4 #define QSERDES_V7_COM_SYSCLK_BUF_ENABLE 0xe8 +#define QSERDES_V7_COM_PLL_EN 0xec #define QSERDES_V7_COM_PLL_IVCO 0xf4 #define QSERDES_V7_COM_PLL_IVCO_MODE1 0xf8 #define QSERDES_V7_COM_SYSCLK_EN_SEL 0x110 @@ -75,6 +76,7 @@ #define QSERDES_V7_COM_CMN_MISC_1 0x184 #define QSERDES_V7_COM_CMN_MODE 0x188 #define QSERDES_V7_COM_PLL_VCO_DC_LEVEL_CTRL 0x198 +#define QSERDES_V7_COM_BIN_VCOCAL_HSCLK_SEL_1 0x19c #define QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a4 #define QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_2 0x1a8 #define QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_3 0x1ac diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h b/drivers/= phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h index 6ab943ff57ff666e4f23f4ad0b4eff211c6dbfd0..0c38d62284e4d0e64a27fb82c46= 8f47aee3760bb 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h @@ -7,9 +7,11 @@ #define QCOM_PHY_QMP_QSERDES_TXRX_V7_H_ =20 #define QSERDES_V7_TX_CLKBUF_ENABLE 0x08 +#define QSERDES_V7_TX_TX_EMP_POST1_LVL 0x0c #define QSERDES_V7_TX_RESET_TSYNC_EN 0x1c #define QSERDES_V7_TX_PRE_STALL_LDO_BOOST_EN 0x20 #define QSERDES_V7_TX_TX_BAND 0x24 +#define QSERDES_V7_TX_SLEW_CNTL 0x28 #define QSERDES_V7_TX_INTERFACE_SELECT 0x2c #define QSERDES_V7_TX_RES_CODE_LANE_TX 0x34 #define QSERDES_V7_TX_RES_CODE_LANE_RX 0x38 @@ -35,26 +37,32 @@ #define QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_LOW 0x3c #define QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_HIGH 0x40 #define QSERDES_V7_RX_UCDR_PI_CONTROLS 0x44 +#define QSERDES_V7_RX_UCDR_PI_CTRL2 0x48 #define QSERDES_V7_RX_UCDR_SB2_THRESH1 0x4c #define QSERDES_V7_RX_UCDR_SB2_THRESH2 0x50 #define QSERDES_V7_RX_UCDR_SB2_GAIN1 0x54 #define QSERDES_V7_RX_UCDR_SB2_GAIN2 0x58 #define QSERDES_V7_RX_AUX_DATA_TCOARSE_TFINE 0x60 +#define QSERDES_V7_RX_RX_TERM_BW 0x80 #define QSERDES_V7_RX_TX_ADAPT_PRE_THRESH1 0xc4 #define QSERDES_V7_RX_TX_ADAPT_PRE_THRESH2 0xc8 #define QSERDES_V7_RX_TX_ADAPT_POST_THRESH 0xcc #define QSERDES_V7_RX_VGA_CAL_CNTRL1 0xd4 #define QSERDES_V7_RX_VGA_CAL_CNTRL2 0xd8 #define QSERDES_V7_RX_GM_CAL 0xdc +#define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL1 0xe8 #define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL2 0xec #define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL3 0xf0 #define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL4 0xf4 #define QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW 0xf8 #define QSERDES_V7_RX_RX_IDAC_TSETTLE_HIGH 0xfc +#define QSERDES_V7_RX_RX_IDAC_MEASURE_TIME 0x100 #define QSERDES_V7_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 +#define QSERDES_V7_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 #define QSERDES_V7_RX_SIGDET_ENABLES 0x118 #define QSERDES_V7_RX_SIGDET_CNTRL 0x11c #define QSERDES_V7_RX_SIGDET_DEGLITCH_CNTRL 0x124 +#define QSERDES_V7_RX_RX_BAND 0x128 #define QSERDES_V7_RX_RX_MODE_00_LOW 0x15c #define QSERDES_V7_RX_RX_MODE_00_HIGH 0x160 #define QSERDES_V7_RX_RX_MODE_00_HIGH2 0x164 @@ -75,6 +83,7 @@ #define QSERDES_V7_RX_DCC_CTRL1 0x1a8 #define QSERDES_V7_RX_VTH_CODE 0x1b0 #define QSERDES_V7_RX_SIGDET_CAL_CTRL1 0x1e4 +#define QSERDES_V7_RX_SIGDET_CAL_CTRL2_AND_CDR_LOCK_EDGE 0x1e8 #define QSERDES_V7_RX_SIGDET_CAL_TRIM 0x1f8 =20 #endif diff --git a/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c b/drivers/phy/qualco= mm/phy-qcom-sgmii-eth.c index 029dafacee7853648ef24afd0d9c4b83a549badf..3c68bfe0ea443ef5cf7f17cead4= 974862dc04884 100644 --- a/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c +++ b/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c @@ -15,7 +15,9 @@ =20 #include "phy-qcom-qmp-pcs-sgmii.h" #include "phy-qcom-qmp-qserdes-com-v5.h" +#include "phy-qcom-qmp-qserdes-com-v7.h" #include "phy-qcom-qmp-qserdes-txrx-v5.h" +#include "phy-qcom-qmp-qserdes-txrx-v7.h" =20 #define QSERDES_QMP_PLL 0x0 #define QSERDES_RX 0x600 @@ -221,6 +223,114 @@ static void qcom_dwmac_sgmii_phy_init_2p5g(struct reg= map *regmap) regmap_write(regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01); } =20 +static void qcom_dwmac_sgmii_phy_init_10g(struct regmap *regmap) +{ + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_POWER_DOWN_CONTROL, 0x01); + + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_BG_TIMER, 0x0A); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_PLL_IVCO, 0x0F); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_PLL_BIAS_EN_CLK_BUF= LR_EN, 0x07); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_CLK_ENABLE1, 0x0F); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_CP_CTRL_MODE0, 0x08= ); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_PLL_RCTRL_MODE0, 0x= 16); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_PLL_CCTRL_MODE0, 0x= 36); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_INTEGLOOP_GAIN0_MOD= E0, 0x1F); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_INTEGLOOP_GAIN1_MOD= E0, 0x00); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_PLL_EN, 0x03); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_SYSCLK_EN_SEL, 0x1A= ); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_LOCK_CMP1_MODE0, 0x= 23); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_LOCK_CMP2_MODE0, 0x= 43); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_DEC_START_MODE0, 0x= 43); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_DIV_FRAC_START1_MOD= E0, 0x00); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_DIV_FRAC_START2_MOD= E0, 0x38); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_DIV_FRAC_START3_MOD= E0, 0x02); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_VCO_TUNE1_MODE0, 0x= E6); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_VCO_TUNE2_MODE0, 0x= 01); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_VCO_TUNE_INITVAL2, = 0x00); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_HSCLK_SEL_1, 0x00); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_HSCLK_HS_SWITCH_SEL= _1, 0x00); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_PLL_CORE_CLK_DIV_MO= DE0, 0x04); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_CORE_CLK_EN, 0x30); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_CMN_CONFIG_1, 0x16); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE= 1_MODE0, 0xD7); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE= 2_MODE0, 0x0F); + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V7_COM_BIN_VCOCAL_HSCLK_SE= L_1, 0x11); + + regmap_write(regmap, QSERDES_TX + QSERDES_V7_TX_CLKBUF_ENABLE, 0x0D); + regmap_write(regmap, QSERDES_TX + QSERDES_V7_TX_TX_BAND, 0x04); + regmap_write(regmap, QSERDES_TX + QSERDES_V7_TX_SLEW_CNTL, 0x08); + regmap_write(regmap, QSERDES_TX + QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX, = 0x09); + regmap_write(regmap, QSERDES_TX + QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX, = 0x09); + regmap_write(regmap, QSERDES_TX + QSERDES_V7_TX_LANE_MODE_1, 0xF5); + regmap_write(regmap, QSERDES_TX + QSERDES_V7_TX_LANE_MODE_2, 0x06); + regmap_write(regmap, QSERDES_TX + QSERDES_V7_TX_LANE_MODE_3, 0x3F); + regmap_write(regmap, QSERDES_TX + QSERDES_V7_TX_LANE_MODE_4, 0x3F); + regmap_write(regmap, QSERDES_TX + QSERDES_V7_TX_LANE_MODE_5, 0x5F); + regmap_write(regmap, QSERDES_TX + QSERDES_V7_TX_RCV_DETECT_LVL_2, 0x12); + regmap_write(regmap, QSERDES_TX + QSERDES_V7_TX_TRAN_DRVR_EMP_EN, 0x0F); + regmap_write(regmap, QSERDES_TX + QSERDES_V7_TX_TX_EMP_POST1_LVL, 0x2B); + + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_UCDR_FO_GAIN, 0x0D); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_UCDR_SO_GAIN, 0x03); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_UCDR_FASTLOCK_FO_GAIN, 0x= 0A); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_UCDR_SO_SATURATION_AND_EN= ABLE, 0x7F); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_LOW, = 0x00); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_HIGH,= 0x01); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_UCDR_PI_CONTROLS, 0x81); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_UCDR_PI_CTRL2, 0x81); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_UCDR_SB2_THRESH1, 0x11); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_UCDR_SB2_THRESH2, 0x22); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_TERM_BW, 0x03); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_VGA_CAL_CNTRL2, 0x08); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_GM_CAL, 0x0F); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL1, 0x= 04); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL2, 0x= 00); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL3, 0x= 4A); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL4, 0x= 5A); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW, 0x80= ); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_IDAC_TSETTLE_HIGH, 0x0= 1); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_IDAC_MEASURE_TIME, 0x2= 0); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_EQ_OFFSET_ADAPTOR_CNTR= L1, 0x17); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_OFFSET_ADAPTOR_CNTRL2,= 0x00); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_SIGDET_CNTRL, 0x0F); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_SIGDET_DEGLITCH_CNTRL, 0x= 1E); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_BAND, 0x18); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_MODE_00_LOW, 0x1F); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_MODE_00_HIGH, 0xBF); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_MODE_00_HIGH2, 0xFF); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_MODE_00_HIGH3, 0xDF); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_MODE_00_HIGH4, 0xEF); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_MODE_01_LOW, 0xE5); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_MODE_01_HIGH, 0xC8); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_MODE_01_HIGH2, 0xC8); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_MODE_01_HIGH3, 0x14); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_MODE_01_HIGH4, 0xB6); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_MODE_10_LOW, 0xE0); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_MODE_10_HIGH, 0xC8); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_MODE_10_HIGH2, 0xC8); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_MODE_10_HIGH3, 0x3B); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_RX_MODE_10_HIGH4, 0xB7); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_DCC_CTRL1, 0x0C); + + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_LINE_RESET_TIME, 0x00); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_SMALL_AMP_DRV_LVL, 0x03); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_LARGE_AMP_DRV_LVL, 0x1A); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_SMALL_AMP_POST_EMP_LVL, 0x= 00); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_LARGE_AMP_POST_EMP_LVL, 0x= 0B); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL1, 0x83); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_SIGDET_CAL_CTRL1, 0x00); + regmap_write(regmap, QSERDES_RX + QSERDES_V7_RX_SIGDET_CAL_CTRL2_AND_CDR_= LOCK_EDGE, 0x00); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_RX_SIGDET_CTRL2, 0xCC); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SGMII_MISC_CTRL7, 0x00); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SGMII_MISC_CTRL8, 0x14); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_RETIME_BUFFER_EN, 0x01); + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00); + + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01); +} + static inline int qcom_dwmac_sgmii_phy_poll_status(struct regmap *regmap, unsigned int reg, unsigned int bit) @@ -265,6 +375,40 @@ static int qcom_dwmac_sgmii_phy_poll_sgmii_ready(struc= t device *dev, return 0; } =20 +static int qcom_dwmac_sgmii_phy_poll_usxgmii_ready(struct device *dev, + struct regmap *regmap) +{ + if (qcom_dwmac_sgmii_phy_poll_status(regmap, + QSERDES_QMP_PLL + QSERDES_V7_COM_C_READY_STATUS, + QSERDES_COM_C_READY)) { + dev_err(dev, "QSERDES_COM_C_READY_STATUS timed-out"); + return -ETIMEDOUT; + } + + if (qcom_dwmac_sgmii_phy_poll_status(regmap, + QSERDES_PCS + QPHY_PCS_PCS_READY_STATUS, + QSERDES_PCS_READY)) { + dev_err(dev, "PCS_READY timed-out"); + return -ETIMEDOUT; + } + + if (qcom_dwmac_sgmii_phy_poll_status(regmap, + QSERDES_PCS + QPHY_PCS_PCS_READY_STATUS, + QSERDES_PCS_SGMIIPHY_READY)) { + dev_err(dev, "SGMIIPHY_READY timed-out"); + return -ETIMEDOUT; + } + + if (qcom_dwmac_sgmii_phy_poll_status(regmap, + QSERDES_QMP_PLL + QSERDES_V7_COM_CMN_STATUS, + QSERDES_COM_C_PLL_LOCKED)) { + dev_err(dev, "PLL Lock Status timed-out"); + return -ETIMEDOUT; + } + + return 0; +} + static int qcom_dwmac_sgmii_phy_calibrate(struct phy *phy) { struct qcom_dwmac_sgmii_phy_data *data =3D phy_get_drvdata(phy); @@ -275,16 +419,19 @@ static int qcom_dwmac_sgmii_phy_calibrate(struct phy = *phy) case PHY_INTERFACE_MODE_1000BASEX: /* 1.25Gbps mode */ qcom_dwmac_sgmii_phy_init_1g(data->regmap); - break; + return qcom_dwmac_sgmii_phy_poll_sgmii_ready(dev, data->regmap); case PHY_INTERFACE_MODE_2500BASEX: /* 3.125Gbps mode */ qcom_dwmac_sgmii_phy_init_2p5g(data->regmap); - break; + return qcom_dwmac_sgmii_phy_poll_sgmii_ready(dev, data->regmap); + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + /* 10.3125Gbps mode */ + qcom_dwmac_sgmii_phy_init_10g(data->regmap); + return qcom_dwmac_sgmii_phy_poll_usxgmii_ready(dev, data->regmap); default: return -EINVAL; } - - return qcom_dwmac_sgmii_phy_poll_sgmii_ready(dev, data->regmap); } =20 static int qcom_dwmac_sgmii_phy_power_on(struct phy *phy) @@ -340,7 +487,9 @@ static int qcom_dwmac_sgmii_phy_validate(struct phy *ph= y, enum phy_mode mode, =20 if (submode =3D=3D PHY_INTERFACE_MODE_SGMII || submode =3D=3D PHY_INTERFACE_MODE_1000BASEX || - submode =3D=3D PHY_INTERFACE_MODE_2500BASEX) + submode =3D=3D PHY_INTERFACE_MODE_2500BASEX || + submode =3D=3D PHY_INTERFACE_MODE_USXGMII || + submode =3D=3D PHY_INTERFACE_MODE_10GBASER) return 0; =20 return -EINVAL; @@ -434,12 +583,19 @@ static int qcom_dwmac_sgmii_phy_probe(struct platform= _device *pdev) return 0; } =20 +static const struct qcom_dwmac_sgmii_phy_match_data nord_match_data =3D { + .default_interface =3D PHY_INTERFACE_MODE_USXGMII, +}; + static const struct qcom_dwmac_sgmii_phy_match_data sa8775p_match_data =3D= { .default_interface =3D PHY_INTERFACE_MODE_SGMII, }; =20 static const struct of_device_id qcom_dwmac_sgmii_phy_of_match[] =3D { { + .compatible =3D "qcom,nord-dwmac-sgmii-phy", + .data =3D &nord_match_data, + }, { .compatible =3D "qcom,sa8775p-dwmac-sgmii-phy", .data =3D &sa8775p_match_data, }, --=20 2.34.1