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Fixes: 288a93200892 ("drm/msm/adreno: Introduce A8x GPU Support") Signed-off-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 ++++++-- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 6d49c51df1a2..baf77a620572 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1656,8 +1656,12 @@ static int a6xx_gmu_rpmh_bw_votes_init(struct adreno= _gpu *adreno_gpu, if (bcm->fixed) { u32 perfmode =3D 0; =20 - /* GMU on A6xx votes perfmode on all valid bandwidth */ - if (!adreno_is_a7xx(adreno_gpu) || + /* + * GMU on A6xx votes perfmode on all valid + * bandwidth. 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a=ed25519-sha256; t=1790159163; l=1636; i=akhilpo@oss.qualcomm.com; s=20240726; h=from:subject:message-id; bh=enyT8E+9AK26apYvWRrZ3yOlEE4CZOhJwCOlmwsJANs=; b=TM3drMHi0LUTT3rpKITA1yUMYkFSZ9baLFTe9nVutJch5tXY+aeUWa9EiMkQbSti9C6ozXpii JgQbn6qY5AcCZp00eIAT5DK8UQqAO2P7qIFPk3aYEhIZ26EavKJmxuP X-Developer-Key: i=akhilpo@oss.qualcomm.com; a=ed25519; pk=lmVtttSHmAUYFnJsQHX80IIRmYmXA4+CzpGcWOOsfKA= X-Proofpoint-GUID: izDlPs7sKjzhvpsIlVOkYujEGy7ZwfDO X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIzMDA0MSBTYWx0ZWRfX8wx6CsBUdt5D dcGg10JmVl40BqRI8wKhpVb47mWuy8OHmosmKQ3t86qguVNc8Xs4VUEsqfKuRHQeDQZjwzx2M+g dq25WDWIgrMWWarDRIZGxECOBAvXlxKQRL5qWvrSo8vgwe2Gnt1GPhKfsuvSLfYrPLbDY4cLBDc 7Z1meIMcGJ/IHbBTj2giTUmDZsdKEePayZ/LNKAU3HSUZUl+Itq0U1Q3/XEIinQtiae2orAP+ly JDb7jYGNoUzyj94T/DCXfvM0nQvlcya61kjfYNpSzGPvwu7kcZl+QjXqJA61NU2sbfKFbCdDtYy kR7p0IfxCy2qy0ru3UO+aChj2VYiC15BeFRxH6WGjdKY5kEsJNS8uOtORnY0kWcbRGLNTNOrh5e 9wo9syPhMKdwYorHUbvfajwSesys+GgZiv+9El1VAxiNeaTTTJa6RS+U6+72+/wpWc+ZSRj22BS 8qtOcUNi2G7HX3n0UjQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIzMDA0MSBTYWx0ZWRfX6Q85SxD9j4nR qd2eXeoKsyvoH7/chZjGbEkM9knhxjL0OqEtpqxvnnwCU2zTLF9OcUhlslTMyJVY2F9xCLUX7+i wDwfMvzgLPfIQyEYrX/O9W6hn8ysY0M= X-Authority-Analysis: v=2.4 cv=QsDLTlyd c=1 sm=1 tr=0 ts=6ab3a95a cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=eKBiAfeFZ4O-hnR0X2wA:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-ORIG-GUID: izDlPs7sKjzhvpsIlVOkYujEGy7ZwfDO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-23_04,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 lowpriorityscore=0 phishscore=0 bulkscore=0 suspectscore=0 impostorscore=0 adultscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609230041 a6xx_gmu_rpmh_dep_votes_init() iterates the GPU frequency list (gmu->gpu_freqs) but was passed gmu->dev to resolve each frequency to an arc level. This results in generation of incorrect dependency votes table. To fix this, pass gpu->pdev->dev, which owns the GPU OPP table. Also, reorder the dependency vote init to improve clarity. Fixes: 06cfbca0e1c6 ("drm/msm/a6xx: Share dependency vote table with GMU") Reviewed-by: Konrad Dybcio Signed-off-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index d072646093a1..161b360bf3eb 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1868,13 +1868,13 @@ static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu= *gmu) ret =3D a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes, gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl", sec_id); =20 + ret |=3D a6xx_gmu_rpmh_dep_votes_init(&gpu->pdev->dev, gmu->dep_arc_votes, + gmu->gpu_freqs, gmu->nr_gpu_freqs); + /* Build the CX votes */ ret |=3D a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl", "mx.lvl"); =20 - ret |=3D a6xx_gmu_rpmh_dep_votes_init(gmu->dev, gmu->dep_arc_votes, - gmu->gpu_freqs, gmu->nr_gpu_freqs); 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a=ed25519-sha256; t=1790159163; l=6066; i=akhilpo@oss.qualcomm.com; s=20240726; h=from:subject:message-id; bh=CHLjdgbBFmYAxDYgBcG23Bc5Mf99naNoUTb/q1yjs/w=; b=+Rp6S1IwhTCXU93ZAg8mgdTbPXp45wPbraxUZ/P1QOMC8I8WlimNA/tiubX2aEmtEVVidHQtk H++MFfIe+ZWBNB5U6dNCkDINdR2pBBg6Z0oonZgj5HTa+BTdrZZvthV X-Developer-Key: i=akhilpo@oss.qualcomm.com; a=ed25519; pk=lmVtttSHmAUYFnJsQHX80IIRmYmXA4+CzpGcWOOsfKA= X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIzMDA0MSBTYWx0ZWRfXxI1yWCgRWdI7 hT3s5gZUWrqu21UZsveUTkWTLjVjWaaYZmN0npJpoKSkuYIsylSO6f0l0A3Cm7rJPWtPdpffjAS OIAwAOF8NafZAdZ/UdXsEgQSFYV2e84= X-Authority-Analysis: v=2.4 cv=R/6WitRX c=1 sm=1 tr=0 ts=6ab3a961 cx=c_pps a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=5x2u8yzsEs7RXICRzdUA:9 a=QEXdDO2ut3YA:10 a=vBUdepa8ALXHeOFLBtFW:22 X-Proofpoint-GUID: wjq-YuFdavW21UXi9OPiYOYNlg2Z73H4 X-Proofpoint-ORIG-GUID: wjq-YuFdavW21UXi9OPiYOYNlg2Z73H4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIzMDA0MSBTYWx0ZWRfX5pj0aFzqtGG2 pXZfp1n9hxpwT2/aI9lbcdYb8o3WaR89gCB/+SiUDbDz0ONb1jcJ0pQZHACBMnCrq26e4uxXXRu UAPBsHzy/7GdbjEuIERIfbMS/SQkQ3Oo20TD/cuKs786SGqbThm78wCfRstV98DLQtLZu6F5XGK hczA02l2AyFYP6SFfbfOEwHsg0hNH0KWObO7Z2foEKWZbq12tIj/qa+QJ+QQ9ViMAOTZuyIayRl fskfoosJsMtAHPt4VXyDcHTMWEq2ubqtjMB6YAUMIYthiF3gIt6wvC9YBgCB4zy67SK+khGa4Ej EXSUGx6a8xsUUGa4d1LSsm/3o2UX6MoblCop/LMeHv1E5cE/g3YxRHoOnyfr4e8G618azAa/PJn gK2Rb2YrNQMvNQycbJsJGQHPZL+2r0b3b20GSXBqeyjrP8ZH1InqRbB4uVJO72/31jYBehKXurG 1N8tDUOcguV4ObgnomQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-23_04,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 malwarescore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 suspectscore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609230041 The GMU RPMh vote construction repeats two patterns across a6xx_gmu_rpmh_arc_votes_init() and a6xx_gmu_rpmh_dep_votes_init(): reading a cmd-db aux-data resource (with the same "halve the byte count and reject empty" handling), and scanning an arc level array for the first corner that satisfies a target level. Refactor out a6xx_gmu_rpmh_read_arc() and a6xx_gmu_rpmh_arc_index() to reduce code duplication and improve code readability. Assisted-by: LLM Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 138 ++++++++++++++++--------------= ---- 1 file changed, 63 insertions(+), 75 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 161b360bf3eb..0ed01ce1c5c5 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1711,74 +1711,85 @@ static unsigned int a6xx_gmu_get_arc_level(struct d= evice *dev, return val; } =20 +static const u16 *a6xx_gmu_rpmh_read_arc(const char *id, size_t *count) +{ + const u16 *vals; + + vals =3D cmd_db_read_aux_data(id, count); + if (IS_ERR(vals)) + return vals; + + *count >>=3D 1; + /* Exclude the trailing zero paddings if there are any */ + while (*count && !vals[*count - 1]) + (*count)--; + + if (!*count) + return ERR_PTR(-EINVAL); + + return vals; +} + +/* + * Find the first index in an arc level array whose level is greater than = or + * equal to the target. If no level is high enough, either clamp to the + * highest available level (@clamp) or fail, dumping the list. + */ +static int a6xx_gmu_rpmh_arc_index(struct device *dev, const u16 *arc, + size_t arc_count, unsigned int level, bool clamp) +{ + int j; + + for (j =3D 0; j < arc_count; j++) { + if (arc[j] >=3D level) + return j; + } + + if (clamp) + return arc_count - 1; + + DRM_DEV_ERROR(dev, "Level %u not found in the RPMh list\n", level); + DRM_DEV_ERROR(dev, "Available levels:\n"); + for (j =3D 0; j < arc_count; j++) + DRM_DEV_ERROR(dev, " %u\n", arc[j]); + + return -EINVAL; +} + static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, unsigned long *freqs, int freqs_count, const char *pri_id, const char *sec_id) { - int i, j; + int i; const u16 *pri, *sec; size_t pri_count, sec_count; =20 - pri =3D cmd_db_read_aux_data(pri_id, &pri_count); + pri =3D a6xx_gmu_rpmh_read_arc(pri_id, &pri_count); if (IS_ERR(pri)) return PTR_ERR(pri); - /* - * The data comes back as an array of unsigned shorts so adjust the - * count accordingly - */ - pri_count >>=3D 1; - if (!pri_count) - return -EINVAL; =20 - sec =3D cmd_db_read_aux_data(sec_id, &sec_count); + sec =3D a6xx_gmu_rpmh_read_arc(sec_id, &sec_count); if (IS_ERR(sec)) return PTR_ERR(sec); =20 - sec_count >>=3D 1; - if (!sec_count) - return -EINVAL; - /* Construct a vote for each frequency */ for (i =3D 0; i < freqs_count; i++) { - u8 pindex =3D 0, sindex =3D 0; unsigned int level =3D a6xx_gmu_get_arc_level(dev, freqs[i]); + int pindex, sindex; =20 - /* Get the primary index that matches the arc level */ - for (j =3D 0; j < pri_count; j++) { - if (pri[j] >=3D level) { - pindex =3D j; - break; - } - } - - if (j =3D=3D pri_count) { - DRM_DEV_ERROR(dev, - "Level %u not found in the RPMh list\n", - level); - DRM_DEV_ERROR(dev, "Available levels:\n"); - for (j =3D 0; j < pri_count; j++) - DRM_DEV_ERROR(dev, " %u\n", pri[j]); - - return -EINVAL; - } + pindex =3D a6xx_gmu_rpmh_arc_index(dev, pri, pri_count, level, false); + if (pindex < 0) + return pindex; =20 /* - * Look for a level in in the secondary list that matches. If - * nothing fits, use the maximum non zero vote - * - * The secondary rail depends on the primary rail, so match it - * against the quantized primary voltage (which is >=3D the - * requested level), not the requested level itself. + * Look for a matching level in the secondary list; if nothing + * fits, clamp to the highest available vote. The secondary rail + * depends on the primary rail, so match it against the selected + * primary voltage (which is >=3D the requested level), not the + * requested level itself. */ - - for (j =3D 0; j < sec_count; j++) { - if (sec[j] >=3D pri[pindex]) { - sindex =3D j; - break; - } else if (sec[j]) { - sindex =3D j; - } - } + sindex =3D a6xx_gmu_rpmh_arc_index(dev, sec, sec_count, + pri[pindex], true); =20 /* Construct the vote */ votes[i] =3D ((pri[pindex] & 0xffff) << 16) | @@ -1794,16 +1805,9 @@ static int a6xx_gmu_rpmh_dep_votes_init(struct devic= e *dev, u32 *votes, const u16 *mx; size_t count; =20 - mx =3D cmd_db_read_aux_data("mx.lvl", &count); + mx =3D a6xx_gmu_rpmh_read_arc("mx.lvl", &count); if (IS_ERR(mx)) return PTR_ERR(mx); - /* - * The data comes back as an array of unsigned shorts so adjust the - * count accordingly - */ - count >>=3D 1; - if (!count) - return -EINVAL; =20 /* Fix the vote for zero frequency */ votes[0] =3D 0xffffffff; @@ -1811,26 +1815,10 @@ static int a6xx_gmu_rpmh_dep_votes_init(struct devi= ce *dev, u32 *votes, /* Construct a vote for rest of the corners */ for (int i =3D 1; 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On these targets the GMU dependency vote carries a per-corner BX vote in bits 25:20, which otherwise default to all-ones (no BX constraint). Prepare BX vote field to pass this new voltage recommendation to GMU. Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 37 +++++++++++++++++++++++++++++++= ++-- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 0ed01ce1c5c5..2b66d6c7fd19 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1799,16 +1799,34 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct devi= ce *dev, u32 *votes, return 0; } =20 +#define GMU_BX_MASK GENMASK(25, 20) + static int a6xx_gmu_rpmh_dep_votes_init(struct device *dev, u32 *votes, unsigned long *freqs, int freqs_count) { - const u16 *mx; - size_t count; + const u16 *mx, *gx =3D NULL, *gbx; + size_t count, gx_count =3D 0, gbx_count =3D 0; =20 mx =3D a6xx_gmu_rpmh_read_arc("mx.lvl", &count); if (IS_ERR(mx)) return PTR_ERR(mx); =20 + /* + * Targets with a third memory rail (BX), in addition to GX and MX, + * expect a per-corner BX vote packed into the dependency vote. Detect + * such targets by the presence of the "gbx.lvl" RPMh resource. The BX + * corner is matched against the Gx rail level, so the "gfx.lvl" corners + * are needed as well. + */ + gbx =3D a6xx_gmu_rpmh_read_arc("gbx.lvl", &gbx_count); + if (IS_ERR(gbx)) { + gbx =3D NULL; + } else { + gx =3D a6xx_gmu_rpmh_read_arc("gfx.lvl", &gx_count); + if (IS_ERR(gx)) + return PTR_ERR(gx); + } + /* Fix the vote for zero frequency */ votes[0] =3D 0xffffffff; =20 @@ -1816,12 +1834,27 @@ static int a6xx_gmu_rpmh_dep_votes_init(struct devi= ce *dev, u32 *votes, for (int i =3D 1; i < freqs_count; i++) { unsigned int level =3D a6xx_gmu_get_arc_level(dev, freqs[i]); int index =3D a6xx_gmu_rpmh_arc_index(dev, mx, count, level, false); + int bx; =20 if (index < 0) return index; =20 /* Construct the vote */ votes[i] =3D (0x3fff << 14) | (index << 8) | (0xff); + + if (!gbx) + continue; + + index =3D a6xx_gmu_rpmh_arc_index(dev, gx, gx_count, level, false); + if (index < 0) + return index; + + /* + * Find the BX corner that satisfies that Gx level, falling + * back to the highest BX corner if none is high enough. + */ + bx =3D a6xx_gmu_rpmh_arc_index(dev, gbx, gbx_count, gx[index], true); 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Signed-off-by: Akhil P Oommen Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 2b66d6c7fd19..14d422d7ab95 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1833,7 +1833,7 @@ static int a6xx_gmu_rpmh_dep_votes_init(struct device= *dev, u32 *votes, /* Construct a vote for rest of the corners */ for (int i =3D 1; i < freqs_count; i++) { unsigned int level =3D a6xx_gmu_get_arc_level(dev, freqs[i]); - int index =3D a6xx_gmu_rpmh_arc_index(dev, mx, count, level, false); + int index =3D a6xx_gmu_rpmh_arc_index(dev, mx, count, level, true); int bx; =20 if (index < 0) --=20 2.55.0 From nobody Thu Sep 24 12:53:42 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E66F1485957 for ; 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a=ed25519-sha256; t=1790159163; l=25643; i=akhilpo@oss.qualcomm.com; s=20240726; h=from:subject:message-id; bh=ly4kXK3g4RHYieCcF9yXfKUK2bcBelfBx2mF2g4Vcok=; b=hfNxDemKXgbZhzpGe1zz3MmPE3P/bYP8sSjLTi/JRbcotg5DHnMU2D6Gb25r7oXYsIn1qKJlo gc3nYInZnqnDhHRO3/m9fHvfNztI10RXbKIGyi5yxF/H9rXCUTxCnLK X-Developer-Key: i=akhilpo@oss.qualcomm.com; a=ed25519; pk=lmVtttSHmAUYFnJsQHX80IIRmYmXA4+CzpGcWOOsfKA= X-Proofpoint-ORIG-GUID: g975lELBv28P-cJWLC7gLAR6yz_fo3Gp X-Authority-Analysis: v=2.4 cv=J4s/fwnS c=1 sm=1 tr=0 ts=6ab3a978 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=kGRJA6_3IbFtNegcoWYA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIzMDA0MSBTYWx0ZWRfX9zqxb65SeA3t LETA8ljTz61wk8ZZy4S9CbOyBikCvlnobleJHPzYuHAvK6gdZdQL1FFsNf3SC6Kgv9xiAcyO1M9 qFAOJMpTkEhh3aO8QBLOVU7kze0ijCAk3rwic6RtBxkxaoKzCyxayfJ7OQd1Rkgrzm/ZUEvLPvo qlkUPZWZTcMYKSQ+hl8t5+RkHIyZNxQn6uvSIlaV6GkBxpExcc2TrmPUPEYOeFH6jw6M8iXfgDw gHcaNyTu556GqBqmiv9QXH2N88gDdm/nmr9+bU+6P5BjfJwtoX6OxUEm+z7Zqf9atuaiKlx+auY ytbzb2KS6mAuS8ozEVAms3s/SGyvwpDl9YKysxWJz6B4cAQXbWFSqc/v8+/ljH7pbj/8RmwXRMv lUstruEE3+dBQQEY1MJGrUDS7DCyMIRhb3T+ySMaFT4paH8LAc9JYN9wtiq5E49LJ0C6QTaZMdf OjQfFe4vkHBNtGq5McQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIzMDA0MSBTYWx0ZWRfX4luFCJ8gVuwU CTSH9j81UYBHNIoOujDgB3moQdVOwn7TpngS92ZGtqYjIKgJUJgZ/bL7GJzkeu7C6A2sS6Ml20d ShmwzeBHOkNn/LRA5W0ai6ka3bBMEwE= X-Proofpoint-GUID: g975lELBv28P-cJWLC7gLAR6yz_fo3Gp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-23_04,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 spamscore=0 impostorscore=0 priorityscore=1501 phishscore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609230041 Adreno 850 is the next generation of A8x GPU present in Hawi SoC. It shares the ADRENO_8XX_GEN2 family and slice architecture with A840, but has many architectural improvements. There is a new block Matrix ALU (MALU) which helps to accelerate certain compute workloads. Also, there is a new Bx rail that powers a part of the GPU IP. GMU is now powered by a dedicated GDSC powered by MxG rail. Add a new catalog entry along with the necessary register lists and additional changes to support the aforementioned new features. Hawi SoC support UBWC v7.0, but GPU is unaffected by this upgrade. Assisted-by: LLM Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 343 ++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 50 +++- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 + drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 16 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 + drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 8 + 6 files changed, 414 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index 90a0c7ffb3c8..de576816ec7c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -2397,6 +2397,307 @@ static const struct adreno_reglist_pipe a840_dyn_pw= rup_reglist_regs[] =3D { }; DECLARE_ADRENO_REGLIST_PIPE_LIST(a840_dyn_pwrup_reglist); =20 +static const struct adreno_reglist_pipe a850_nonctxt_regs[] =3D { + { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, + { REG_A8XX_CP_MULTIDRAW_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x01000800, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_B= R) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR)= }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) |= BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0x00400000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_5, BIT(28), BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, BIT(10) | BIT(9), BIT(PIPE_BR) }, + { REG_A6XX_RB_DBG_ECO_CNTL, BIT(17), BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0x12000000, BIT(PIPE_BR) }, + { REG_A6XX_RB_RBP_CNTL, BIT(5) | BIT(6), BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) }, + { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_SLICE_PERFCTR_CNTL, BIT(0), BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_POWER_UP_RESET_SW_OVERRIDE, 0x70809060, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_POWER_UP_RESET_SW_BV_OVERRIDE, 0x30000000, BIT(PIPE_NONE)= }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) }, + { REG_A6XX_SP_CHICKEN_BITS, BIT(24), BIT(PIPE_NONE) }, + { REG_A7XX_SP_CHICKEN_BITS_2, 0x00820800, BIT(PIPE_NONE) }, + { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) }, + { REG_A8XX_SP_CHICKEN_BITS_5, BIT(3), BIT(PIPE_NONE) }, + { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) }, + { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, 0x04000000, BIT(PIPE_NONE) }, + { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, BIT(17), BIT(PIPE_NONE) }, + { REG_A8XX_SP_HLSQ_DBG_ECO_CNTL_3, BIT(1), BIT(PIPE_NONE) }, + { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) }, + { REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) }, + { REG_A8XX_SP_L0_PERF_TUNE, 0x00000024, BIT(PIPE_NONE) }, + { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10100000, BIT(PIPE_NONE) }, + { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000720, BIT(PIPE_NONE) }, + { REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_DBG_ECO_CNTL_0, BIT(31), BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_HW_DBG_CNTL, 0x01410000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00080020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_B= R) }, + { REG_A8XX_VSC_VISIBILITY_FLUSH_CNTL, 0x00080004, BIT(PIPE_NONE) }, + { }, +}; + +static const u32 a850_protect_regs[] =3D { + A6XX_PROTECT_RDONLY(0x00008, 0x039b), + A6XX_PROTECT_RDONLY(0x003b4, 0x008b), + A6XX_PROTECT_NORDWR(0x00440, 0x001f), + A6XX_PROTECT_RDONLY(0x00580, 0x005f), + A6XX_PROTECT_NORDWR(0x005e0, 0x011f), + A6XX_PROTECT_RDONLY(0x0074a, 0x0005), + A6XX_PROTECT_RDONLY(0x00759, 0x001b), + A6XX_PROTECT_NORDWR(0x00775, 0x000a), + A6XX_PROTECT_RDONLY(0x00789, 0x0000), + A6XX_PROTECT_RDONLY(0x0078c, 0x0013), + A6XX_PROTECT_NORDWR(0x00800, 0x0029), + A6XX_PROTECT_NORDWR(0x00837, 0x00af), + A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), + A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), + A6XX_PROTECT_NORDWR(0x009b1, 0x0250), + A6XX_PROTECT_NORDWR(0x00c07, 0x0008), + A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), + A6XX_PROTECT_RDONLY(0x00df0, 0x0000), + A6XX_PROTECT_NORDWR(0x00df1, 0x0000), + A6XX_PROTECT_NORDWR(0x00df5, 0x0003), + A6XX_PROTECT_RDONLY(0x00df9, 0x0007), + A6XX_PROTECT_NORDWR(0x00e01, 0x0000), + A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), + A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), + A6XX_PROTECT_RDONLY(0x03cc6, 0x0039), + A6XX_PROTECT_NORDWR(0x03d00, 0x1fff), + A6XX_PROTECT_NORDWR(0x08600, 0x01ff), + A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), + A6XX_PROTECT_RDONLY(0x08f00, 0x0000), + A6XX_PROTECT_NORDWR(0x08f01, 0x01be), + A6XX_PROTECT_NORDWR(0x09600, 0x01ff), + A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), + A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), + A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), + A6XX_PROTECT_NORDWR(0x0a82e, 0x0000), + A6XX_PROTECT_NORDWR(0x0ae00, 0x0000), + A6XX_PROTECT_NORDWR(0x0ae02, 0x0004), + A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), + A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf), + A6XX_PROTECT_RDONLY(0x0aed0, 0x002f), + A6XX_PROTECT_NORDWR(0x0af00, 0x027f), + A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), + A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), + A6XX_PROTECT_NORDWR(0x18400, 0x003f), + A6XX_PROTECT_RDONLY(0x18440, 0x013f), + A6XX_PROTECT_NORDWR(0x18580, 0x1fff), + A6XX_PROTECT_NORDWR(0x1ac00, 0x1fff), + A6XX_PROTECT_NORDWR(0x1cc00, 0x1fff), + A6XX_PROTECT_NORDWR(0x1f400, 0x0477), + A6XX_PROTECT_RDONLY(0x1f878, 0x0507), + A6XX_PROTECT_NORDWR(0x1f930, 0x0329), + A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff), + A6XX_PROTECT_NORDWR(0x27800, 0x007f), + A6XX_PROTECT_RDONLY(0x27880, 0x0385), + A6XX_PROTECT_NORDWR(0x27882, 0x0035), + A6XX_PROTECT_NORDWR(0x27c06, 0x0000), +}; +DECLARE_ADRENO_PROTECT(a850_protect, 15); + +static const u32 a850_pwrup_reglist_regs[] =3D { + REG_A8XX_RB_CMP_NC_MODE_CNTL, + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN, + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN + 1, + REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, + REG_A7XX_SP_READ_SEL, + REG_A8XX_CP_MULTIDRAW_CNTL, + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(5), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(6), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(7), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(8), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(9), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(10), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(11), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(12), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(13), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(14), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(15), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(16), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(17), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(18), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(19), + REG_A6XX_TPL1_DBG_ECO_CNTL, + REG_A6XX_TPL1_DBG_ECO_CNTL1, + REG_A6XX_TPL1_NC_MODE_CNTL, + REG_A6XX_UCHE_MODE_CNTL, + REG_A8XX_UCHE_CCHE_MODE_CNTL, + REG_A8XX_UCHE_HW_DBG_CNTL, + REG_A8XX_UCHE_CCHE_CACHE_WAYS, + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN, + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN + 1, + REG_A8XX_UCHE_CCHE_LPAC_GMEM_RANGE_MIN, + REG_A8XX_UCHE_CCHE_LPAC_GMEM_RANGE_MIN + 1, + REG_A8XX_UCHE_CCHE_TRAP_BASE, + REG_A8XX_UCHE_CCHE_TRAP_BASE + 1, + REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE, + REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE + 1, + REG_A8XX_UCHE_CLIENT_PF, + REG_A8XX_UCHE_DBG_ECO_CNTL_0, + REG_A8XX_UCHE_GBIF_GX_CONFIG, + REG_A8XX_UCHE_TRAP_BASE, + REG_A8XX_UCHE_TRAP_BASE + 1, + REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, + REG_A8XX_UCHE_WRITE_THRU_BASE, + REG_A8XX_UCHE_WRITE_THRU_BASE + 1, + REG_A8XX_VSC_VISIBILITY_FLUSH_CNTL, +}; +DECLARE_ADRENO_REGLIST_LIST(a850_pwrup_reglist); + +static const u32 a850_ifpc_reglist_regs[] =3D { + REG_A8XX_CP_INTERRUPT_STATUS_MASK_GLOBAL, + REG_A8XX_RBBM_NC_MODE_CNTL, + REG_A8XX_RBBM_SLICE_INTERFACE_HANG_INT_CNTL, + REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, + REG_A8XX_RBBM_SLICE_PERFCTR_CNTL, + REG_A6XX_SP_CHICKEN_BITS, + REG_A7XX_SP_CHICKEN_BITS_2, + REG_A7XX_SP_CHICKEN_BITS_3, + REG_A8XX_SP_CHICKEN_BITS_5, + REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, + REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, + REG_A8XX_SP_HLSQ_DBG_ECO_CNTL_3, + REG_A8XX_SP_HLSQ_LPAC_GMEM_RANGE_MIN, + REG_A8XX_SP_HLSQ_LPAC_GMEM_RANGE_MIN + 1, + REG_A6XX_SP_NC_MODE_CNTL, + REG_A6XX_SP_PERFCTR_SHADER_MASK, + REG_A8XX_SP_L0_PERF_TUNE, + REG_A8XX_CP_PROTECT_GLOBAL(0), + REG_A8XX_CP_PROTECT_GLOBAL(1), + REG_A8XX_CP_PROTECT_GLOBAL(2), + REG_A8XX_CP_PROTECT_GLOBAL(3), + REG_A8XX_CP_PROTECT_GLOBAL(4), + REG_A8XX_CP_PROTECT_GLOBAL(5), + REG_A8XX_CP_PROTECT_GLOBAL(6), + REG_A8XX_CP_PROTECT_GLOBAL(7), + REG_A8XX_CP_PROTECT_GLOBAL(8), + REG_A8XX_CP_PROTECT_GLOBAL(9), + REG_A8XX_CP_PROTECT_GLOBAL(10), + REG_A8XX_CP_PROTECT_GLOBAL(11), + REG_A8XX_CP_PROTECT_GLOBAL(12), + REG_A8XX_CP_PROTECT_GLOBAL(13), + REG_A8XX_CP_PROTECT_GLOBAL(14), + REG_A8XX_CP_PROTECT_GLOBAL(15), + REG_A8XX_CP_PROTECT_GLOBAL(16), + REG_A8XX_CP_PROTECT_GLOBAL(17), + REG_A8XX_CP_PROTECT_GLOBAL(18), + REG_A8XX_CP_PROTECT_GLOBAL(19), + REG_A8XX_CP_PROTECT_GLOBAL(20), + REG_A8XX_CP_PROTECT_GLOBAL(21), + REG_A8XX_CP_PROTECT_GLOBAL(22), + REG_A8XX_CP_PROTECT_GLOBAL(23), + REG_A8XX_CP_PROTECT_GLOBAL(24), + REG_A8XX_CP_PROTECT_GLOBAL(25), + REG_A8XX_CP_PROTECT_GLOBAL(26), + REG_A8XX_CP_PROTECT_GLOBAL(27), + REG_A8XX_CP_PROTECT_GLOBAL(28), + REG_A8XX_CP_PROTECT_GLOBAL(29), + REG_A8XX_CP_PROTECT_GLOBAL(30), + REG_A8XX_CP_PROTECT_GLOBAL(31), + REG_A8XX_CP_PROTECT_GLOBAL(32), + REG_A8XX_CP_PROTECT_GLOBAL(33), + REG_A8XX_CP_PROTECT_GLOBAL(34), + REG_A8XX_CP_PROTECT_GLOBAL(35), + REG_A8XX_CP_PROTECT_GLOBAL(36), + REG_A8XX_CP_PROTECT_GLOBAL(37), + REG_A8XX_CP_PROTECT_GLOBAL(38), + REG_A8XX_CP_PROTECT_GLOBAL(39), + REG_A8XX_CP_PROTECT_GLOBAL(40), + REG_A8XX_CP_PROTECT_GLOBAL(41), + REG_A8XX_CP_PROTECT_GLOBAL(42), + REG_A8XX_CP_PROTECT_GLOBAL(43), + REG_A8XX_CP_PROTECT_GLOBAL(44), + REG_A8XX_CP_PROTECT_GLOBAL(45), + REG_A8XX_CP_PROTECT_GLOBAL(46), + REG_A8XX_CP_PROTECT_GLOBAL(47), + REG_A8XX_CP_PROTECT_GLOBAL(48), + REG_A8XX_CP_PROTECT_GLOBAL(49), + REG_A8XX_CP_PROTECT_GLOBAL(50), + REG_A8XX_CP_PROTECT_GLOBAL(51), + REG_A8XX_CP_PROTECT_GLOBAL(52), + REG_A8XX_CP_PROTECT_GLOBAL(53), + REG_A8XX_CP_PROTECT_GLOBAL(54), + REG_A8XX_CP_PROTECT_GLOBAL(55), + REG_A8XX_CP_PROTECT_GLOBAL(63), +}; +DECLARE_ADRENO_REGLIST_LIST(a850_ifpc_reglist); + +static const struct adreno_reglist a850_gbif[] =3D { + { REG_A6XX_GBIF_QSB_SIDE0, 0x00071e20 }, + { REG_A6XX_GBIF_QSB_SIDE1, 0x00071e20 }, + { REG_A6XX_GBIF_QSB_SIDE2, 0x00071e20 }, + { REG_A6XX_GBIF_QSB_SIDE3, 0x00071e20 }, + { REG_A6XX_GBIF_CX_CONFIG, 0x20023020 }, + { }, +}; + +static const struct adreno_reglist_pipe a850_dyn_pwrup_reglist_regs[] =3D { + { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_5, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BV) | BIT(PIPE= _BR) }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0, BIT(PIPE_BR)}, + { REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, + { REG_A6XX_RB_RBP_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) }, + { REG_A6XX_RB_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_CP_HW_FAULT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) | + BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) | + BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) }, + { REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) | + BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) | + BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) }, + { REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIP= E_LPAC) }, + { REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE= _LPAC) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_LPAC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, + { REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) }, +}; +DECLARE_ADRENO_REGLIST_PIPE_LIST(a850_dyn_pwrup_reglist); + static const struct adreno_info a8xx_gpus[] =3D { { .chip_ids =3D ADRENO_CHIP_IDS(0x44070001), @@ -2524,6 +2825,48 @@ static const struct adreno_info a8xx_gpus[] =3D { { 242, 1 }, { 221, 2 }, ), + }, { + .chip_ids =3D ADRENO_CHIP_IDS(0x44051401), + .family =3D ADRENO_8XX_GEN2, + .fw =3D { + [ADRENO_FW_SQE] =3D "gen81100_sqe.fw", + [ADRENO_FW_GMU] =3D "gen81100_gmu.bin", + [ADRENO_FW_AQE] =3D "gen81100_aqe.fw", + }, + .gmem =3D 18 * SZ_1M, + .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, + .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION | + ADRENO_QUIRK_IFPC, + .funcs =3D &a8xx_gpu_funcs, + .a6xx =3D &(const struct a6xx_info) { + .protect =3D &a850_protect, + .nonctxt_reglist =3D a850_nonctxt_regs, + .pwrup_reglist =3D &a850_pwrup_reglist, + .dyn_pwrup_reglist =3D &a850_dyn_pwrup_reglist, + .ifpc_reglist =3D &a850_ifpc_reglist, + .gbif_cx =3D a850_gbif, + .max_slices =3D 3, + .gmu_chipid =3D 0x80b0100, + .bcms =3D (const struct a6xx_bcm[]) { + { .name =3D "SH0", .buswidth =3D 32 }, + { .name =3D "MC0", .buswidth =3D 4 }, + { + .name =3D "ACV", + .fixed =3D true, + .perfmode =3D BIT(2), + .perfmode_bw =3D 16500000, + }, + { /* sentinel */ }, + }, + }, + .preempt_record_size =3D 19708 * SZ_1K, + .speedbins =3D ADRENO_SPEEDBINS( + { 0, 0 }, + { 284, 2 }, + { 216, 3 }, + ), } }; =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 14d422d7ab95..f766e5e4c7b5 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -145,6 +145,19 @@ bool a8xx_gmu_gx_is_on(struct adreno_gpu *adreno_gpu) if (!gmu->initialized) return false; =20 + /* + * Use the CX_MISC_GFX_PWR_CLK_STATUS register instead of the GMUCX + * register to ensure correct GDSC and clock status reporting even + * when the GMU MX domain is powered off + */ + if (adreno_is_a850(adreno_gpu)) { + val =3D a6xx_cx_misc_read(a6xx_gpu, REG_A8XX_CX_MISC_GFX_PWR_CLK_STATUS); + + return !(val & + (A8XX_CX_MISC_GFX_PWR_CLK_STATUS_GX_GDSC_POWER_OFF | + A8XX_CX_MISC_GFX_PWR_CLK_STATUS_GX_CLK_OFF)); + } + val =3D gmu_read(gmu, REG_A8XX_GMU_PWR_CLK_STATUS); =20 return !(val & @@ -645,7 +658,7 @@ static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) if (!test_and_clear_bit(GMU_STATUS_FW_START, &gmu->status)) return; =20 - if (adreno_is_a840(adreno_gpu)) + if (adreno_is_a840(adreno_gpu) || adreno_is_a850(adreno_gpu)) bitmask =3D BIT(30); =20 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1); @@ -2170,6 +2183,9 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) dev_pm_domain_detach(gmu->gxpd, false); } =20 + if (!IS_ERR_OR_NULL(gmu->gmu_mxpd)) + dev_pm_domain_detach(gmu->gmu_mxpd, false); + if (!IS_ERR_OR_NULL(gmu->qmp)) qmp_put(gmu->qmp); =20 @@ -2314,7 +2330,8 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct d= evice_node *node) struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct msm_gpu *gpu =3D &adreno_gpu->base; struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; - struct device_link *link; + struct device_link *gmu_mx_link =3D NULL; + struct device_link *cx_link; resource_size_t start; struct resource *res; int ret; @@ -2461,12 +2478,27 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct= device_node *node) goto err_mmio; } =20 - link =3D device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME); - if (!link) { + cx_link =3D device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME); + if (!cx_link) { ret =3D -ENODEV; goto detach_cxpd; } =20 + /* Optionally attach the GMU MX power domain */ + gmu->gmu_mxpd =3D dev_pm_domain_attach_by_name(gmu->dev, "gmu_mx"); + if (IS_ERR(gmu->gmu_mxpd)) { + ret =3D PTR_ERR(gmu->gmu_mxpd); + goto detach_cxpd_link; + } + + if (gmu->gmu_mxpd) { + gmu_mx_link =3D device_link_add(gmu->dev, gmu->gmu_mxpd, DL_FLAG_PM_RUNT= IME); + if (!gmu_mx_link) { + ret =3D -ENODEV; + goto detach_gmu_mxpd; + } + } + /* Other errors are handled during GPU ACD probe */ gmu->qmp =3D qmp_get(gmu->dev); if (PTR_ERR_OR_ZERO(gmu->qmp) =3D=3D -EPROBE_DEFER) { @@ -2508,7 +2540,15 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct = device_node *node) if (!IS_ERR_OR_NULL(gmu->qmp)) qmp_put(gmu->qmp); =20 - device_link_del(link); + if (!IS_ERR_OR_NULL(gmu_mx_link)) + device_link_del(gmu_mx_link); + +detach_gmu_mxpd: + if (gmu->gmu_mxpd) + dev_pm_domain_detach(gmu->gmu_mxpd, false); + +detach_cxpd_link: + device_link_del(cx_link); =20 detach_cxpd: dev_pm_domain_detach(gmu->cxpd, false); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.h index 3f96b10b5f61..d3f6cd8b9741 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -77,6 +77,7 @@ struct a6xx_gmu { =20 struct device *gxpd; struct device *cxpd; + struct device *gmu_mxpd; =20 int idle_level; =20 diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c index add93c1fa039..a5b5e4286e4e 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -286,10 +286,11 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu) u32 hbb, hbb_hi, hbb_lo, mode; u8 uavflagprd_inv =3D 2; =20 - if (ubwc_version > UBWC_6_0) + if (ubwc_version > UBWC_7_0) dev_err(&gpu->pdev->dev, "Unknown UBWC version: 0x%x\n", ubwc_version); =20 - if (ubwc_version =3D=3D UBWC_6_0) + if (ubwc_version =3D=3D UBWC_6_0 || + ubwc_version =3D=3D UBWC_7_0) yuvnotcomptofc =3D true; =20 if (ubwc_version < UBWC_5_0 && @@ -726,6 +727,7 @@ static int hw_init(struct msm_gpu *gpu) =20 for (pipe_id =3D PIPE_BR; pipe_id <=3D PIPE_DDE_BV; pipe_id++) { u32 apriv_mask =3D A8XX_APRIV_MASK; + u32 int_mask =3D A8XX_CP_INTERRUPT_STATUS_MASK_PIPE; unsigned long flags; =20 if (pipe_id =3D=3D PIPE_LPAC) @@ -734,10 +736,16 @@ static int hw_init(struct msm_gpu *gpu) if (pipe_id =3D=3D PIPE_BR) apriv_mask =3D A8XX_BR_APRIV_MASK; =20 + /* + * A850's BV pipe raises a spurious RTWROVF fault interrupt; + * mask it off to avoid false fault recovery. + */ + if (adreno_is_a850(adreno_gpu) && pipe_id =3D=3D PIPE_BV) + int_mask &=3D ~A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_RTWROVF; + a8xx_aperture_acquire(gpu, pipe_id, &flags); gpu_write(gpu, REG_A8XX_CP_APRIV_CNTL_PIPE, apriv_mask); - gpu_write(gpu, REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE, - A8XX_CP_INTERRUPT_STATUS_MASK_PIPE); + gpu_write(gpu, REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE, int_mask); gpu_write(gpu, REG_A8XX_CP_HW_FAULT_STATUS_MASK_PIPE, A8XX_CP_HW_FAULT_STATUS_MASK_PIPE); a8xx_aperture_release(gpu, flags); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index bd5c440f1753..f99cf5962344 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -612,6 +612,11 @@ static inline int adreno_is_a840(struct adreno_gpu *gp= u) return gpu->info->chip_ids[0] =3D=3D 0x44050a01; } =20 +static inline int adreno_is_a850(struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] =3D=3D 0x44051401; +} + /* Put vm_start above 32b to catch issues with not setting xyz_BASE_HI */ #define ADRENO_VM_START 0x100000000ULL u64 adreno_private_vm_size(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/dr= m/msm/registers/adreno/a6xx.xml index 69dd0446f8d2..e6e56969a9b8 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml @@ -269,6 +269,7 @@ by a particular renderpass/blit. + =20 @@ -1326,6 +1327,7 @@ by a particular renderpass/blit. =20 + @@ -4352,6 +4354,7 @@ by a particular renderpass/blit. + =20