From nobody Thu Sep 24 14:28:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A374C309EE2; Wed, 23 Sep 2026 00:41:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790124087; cv=none; b=Pa9s70umcj1TckU0Uiuv7kFr4n8XbnixuoJb35teWoncRlmTAcyBhgoQuc8e02aR/l2nkC85QZ/gSHkSaRyQLiz9O1qkCd7DH1DBg0c+GGuPkzmmxYO1crfxPCIsDguxuDcGsigkS/DGwlCQa4zSSCHUmZV0uDKqnbc1lZWOMEs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790124087; c=relaxed/simple; bh=u2BQLYb5Pe7p9uQA31o/pds/NqQH0xcvLTkP6iycN5o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TfpQcl8t1Exe5qZsNcw/TmiS8jt4V1i1CykyIeHu0UcvuSCRCSKFztOsLvlvoSPAttrZJhJDV8k+Xg/6JIFuF9EJsVUkfrH6FjYpH4mBVCRp8JijhC/WN+sPSpMZG2HyQmKXltxkzqeDEgVu5DjxAUC0A4kVGlUYQauA04t9wtM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cMJh2vhA; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cMJh2vhA" Received: by smtp.kernel.org (Postfix) with ESMTPS id 61195C2BCF7; Wed, 23 Sep 2026 00:41:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790124087; bh=u2BQLYb5Pe7p9uQA31o/pds/NqQH0xcvLTkP6iycN5o=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=cMJh2vhAt5CnUwAnubJ51lVwF8c3p3AznYXc33gDO6G/3prfZ2embfgHHzBaHj6x8 AhHXJJaSk/JLOFb1WJ5PneiSp2XnlTWWZXtrGxRHK3dXI96cpP6MqYIWnClSx81xcb 78ghKXz8YeYOaziSWpCkdjSuRLVebm121WCQWHFxZ23symNwOXfCXAemkWd4rSN5TY fVl1B4U7q9sTNX5PnxoKXiErrBiZzRaD57InTe3GCbK1kUvyFrXeNfEngddjFGjDIn 8vBUfB/8PveHzPJIsjWRuEq4Wg42ql2QWCffchd8sCkinF27fJIXqllxL2Oos/HifE uv4WV186NUyag== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EDFAC982FA; Wed, 23 Sep 2026 00:41:27 +0000 (UTC) From: Antonin Malzieu Ridolfi via B4 Relay Date: Wed, 23 Sep 2026 02:41:07 +0200 Subject: [PATCH v2 1/4] gpu: nova-core: Extract PFSP register definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-b4-extract-pfsp-registers-to-falcon-mod-v2-1-74600fc068c4@nanonej.com> References: <20260923-b4-extract-pfsp-registers-to-falcon-mod-v2-0-74600fc068c4@nanonej.com> In-Reply-To: <20260923-b4-extract-pfsp-registers-to-falcon-mod-v2-0-74600fc068c4@nanonej.com> To: Danilo Krummrich , Alice Ryhl , Alexandre Courbot , David Airlie , Simona Vetter Cc: linux-kernel@vger.kernel.org, nova-gpu@lists.linux.dev, dri-devel@lists.freedesktop.org, Antonin Malzieu Ridolfi X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5168; i=dev@nanonej.com; h=from:subject:message-id; bh=QnqNTv24qeNXGniIj9tTorKIt90fuqIyOniUCAem2As=; b=owEBbQKS/ZANAwAKAWaH8SMKFRX9AcsmYgBqsyA1wdExC/qVxRtEpe3hRuhY/ZrHVs3jzJDWx lq08C4WPGeJAjMEAAEKAB0WIQSDtk+wfJEhL1KFIn1mh/EjChUV/QUCarMgNQAKCRBmh/EjChUV /cPED/0S9iD2+UbXTcVguvt5hBwa/Z2pcnMKFuiM+eaRkEwInFuNpFtlkFTWzxCOhSKm1tRz5I5 iEs6x2Ozrcx7YUaVUeOC9Ccyf5SYLz9hpWd/U9d6p6tQani0tDwRGutCuTDYw+vkZBO2rJQUAap dKk7qces0jt10wWMnYHA7cy+O4utJrUw6zU/MqlB02Xcv8/lrhKFfCOqOWZZZbXY860xKkkdKuX jEP0Rvl5Q2q6I4PKLq2rUbjVHbOT6xtvWC6+G+zDOCK99KS8Rkl1j95ffahl6wkTuQLkUNnPZqM VOV8F8l7KqY446Deabr1lHwEttWo4gAlOIXZplf3Wv5dhqKmIrbCuqQjnilRbZN88Vp5C1ItTlh amIZfTviBaP86bX+ikRx8V6AhVaBtRh4u/WErmbRo6/nWtrhV8gn3GJj4HKxm9XwLHyAv63YKCQ Q62t3HyB2nEtjC6ZcaV3RlrXdi50ICX9ube14WN6DFdF90P65BLf8d/ELlOIZ6ZQvXAdqX44QHZ 4R7nqd54PEX2C1N0JMTM3V7+aE26L74ZuvTjwzRIRSAovKheOBfcGHuRu7N2tDx9pWxjtyJojd9 QWuX9OX+NFjvoPOpTxDm4/Lss2aBJGybT+2uqcM/6ZiCyKGP1L8SJe9pctSW8df+FfeAyux389P oxDzQYo+OZS7Ulw== X-Developer-Key: i=dev@nanonej.com; a=openpgp; fpr=83B64FB07C91212F5285227D6687F1230A1515FD X-Endpoint-Received: by B4 Relay for dev@nanonej.com/default with auth_id=825 X-Original-From: Antonin Malzieu Ridolfi Reply-To: dev@nanonej.com From: Antonin Malzieu Ridolfi Move PFSP register definitions from the root regs.rs file into the falcon module that own them, in the new falcon/regs.rs file. This follows the same pattern established by previous commits for GSP, PDISP, PFB, PBUS and PMC registers: register definitions move to the module that interprets their service, visibility changes to pub(super). Since PFALCON registers are defined in the root regs.rs but are also part of the falcon interface, accessed by the whole falcon module. They are re-exported in falcon/regs.rs so falcon code can use a single regs:: prefix. Once the PFALCON family moves out of the root module, these re-exports will become plain definitions. Suggested-by: Alexandre Courbot Suggested-by: Danilo Krummrich Signed-off-by: Antonin Malzieu Ridolfi --- drivers/gpu/nova-core/falcon.rs | 4 ++-- drivers/gpu/nova-core/falcon/fsp.rs | 6 +++--- drivers/gpu/nova-core/falcon/regs.rs | 42 ++++++++++++++++++++++++++++++++= ++++ drivers/gpu/nova-core/regs.rs | 23 -------------------- 4 files changed, 47 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index 9015de965a53..1900d642baa1 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -31,13 +31,13 @@ num::{ self, FromSafeCast, // - }, - regs, + }, // }; =20 pub(crate) mod fsp; pub(crate) mod gsp; mod hal; +mod regs; pub(crate) mod sec2; =20 /// Alignment (in bytes) of falcon memory blocks. diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/fa= lcon/fsp.rs index 85f9c8c5d60e..2bd8674f27a1 100644 --- a/drivers/gpu/nova-core/falcon/fsp.rs +++ b/drivers/gpu/nova-core/falcon/fsp.rs @@ -17,7 +17,7 @@ }, prelude::*, sizes::SZ_1K, - time::Delta, + time::Delta, // }; =20 use crate::{ @@ -26,11 +26,11 @@ NovaRegisters, // }, falcon::{ + regs, Falcon, FalconEngine, // }, - num, - regs, // + num, // }; =20 /// FSP message timeout in milliseconds. diff --git a/drivers/gpu/nova-core/falcon/regs.rs b/drivers/gpu/nova-core/f= alcon/regs.rs new file mode 100644 index 000000000000..5ccb10946ec4 --- /dev/null +++ b/drivers/gpu/nova-core/falcon/regs.rs @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 + +use crate::driver::NovaRegisters; +use kernel::io::register; + +// FSP (Foundation Security Processor) queue registers for Hopper/Blackwel= l Chain of Trust. +// These registers manage falcon EMEM communication queues. + +register! { + base: NovaRegisters; + + pub(crate) NV_PFSP_QUEUE_HEAD(u32)[8] @ 0x008f2c00 { + 31:0 address =3D> u32; + } + + pub(crate) NV_PFSP_QUEUE_TAIL(u32)[8] @ 0x008f2c04 { + 31:0 address =3D> u32; + } + + pub(crate) NV_PFSP_MSGQ_HEAD(u32)[8] @ 0x008f2c80 { + 31:0 val =3D> u32; + } + + pub(crate) NV_PFSP_MSGQ_TAIL(u32)[8] @ 0x008f2c84 { + 31:0 val =3D> u32; + } +} + +// PFALCON registers are defined in the root `regs.rs` but are part of the= falcon +// interface, accessed by the whole falcon module. They are re-exported he= re so +// falcon code can use a single `regs::` prefix. +// Once the PFALCON family moves out of the root module, these re-exports = become +// plain definitions. +pub(super) use crate::regs::{ + NV_PFALCON_FALCON_BOOTVEC, NV_PFALCON_FALCON_CPUCTL, NV_PFALCON_FALCON= _CPUCTL_ALIAS, + NV_PFALCON_FALCON_DMACTL, NV_PFALCON_FALCON_DMATRFBASE, NV_PFALCON_FAL= CON_DMATRFBASE1, + NV_PFALCON_FALCON_DMATRFCMD, NV_PFALCON_FALCON_DMATRFFBOFFS, NV_PFALCO= N_FALCON_DMATRFMOFFS, + NV_PFALCON_FALCON_DMEMC, NV_PFALCON_FALCON_DMEMD, NV_PFALCON_FALCON_EM= EMC, + NV_PFALCON_FALCON_EMEMD, NV_PFALCON_FALCON_IMEMC, NV_PFALCON_FALCON_IM= EMD, + NV_PFALCON_FALCON_IMEMT, NV_PFALCON_FALCON_MAILBOX0, NV_PFALCON_FALCON= _MAILBOX1, + NV_PFALCON_FALCON_OS, NV_PFALCON_FALCON_RM, NV_PFALCON_FBIF_CTL, NV_PF= ALCON_FBIF_TRANSCFG, +}; diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 9978fb2803b0..693b5148b1d8 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -372,29 +372,6 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { } } =20 -// FSP (Foundation Security Processor) queue registers for Hopper/Blackwel= l Chain of Trust. -// These registers manage falcon EMEM communication queues. - -register! { - base: NovaRegisters; - - pub(crate) NV_PFSP_QUEUE_HEAD(u32)[8] @ 0x008f2c00 { - 31:0 address =3D> u32; - } - - pub(crate) NV_PFSP_QUEUE_TAIL(u32)[8] @ 0x008f2c04 { - 31:0 address =3D> u32; - } - - pub(crate) NV_PFSP_MSGQ_HEAD(u32)[8] @ 0x008f2c80 { - 31:0 val =3D> u32; - } - - pub(crate) NV_PFSP_MSGQ_TAIL(u32)[8] @ 0x008f2c84 { - 31:0 val =3D> u32; - } -} - // The modules below provide registers that are not identical on all suppo= rted chips. They should // only be used in HAL modules. =20 --=20 2.55.0 From nobody Thu Sep 24 14:28:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3627247291; Wed, 23 Sep 2026 00:41:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790124087; cv=none; b=jznwYxNOMN0u3I7h6GJ6zbAghxXzA8g89v+FVdDOMB/s/M5C90mrNxLeUu8jwA7yxcprGYxgO6OLvNTH10CaglV8zBhNOyaV3mMwRGZN/SctJNpS/weon3ngl1E47rg7vF88nGHaOCtwIQLtMHGFlkOepXu47vHja14txQbvg6Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790124087; c=relaxed/simple; bh=ePI4Y4eg/GDdzK+ll3duTQaWYEU9+rwzeCFYNV8BwNE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fVrgWdL04edJjZdbpj15/iwFgKcaHCZLZfXWFkrdKSSqA5e0BqTY27ALd59THrYyIuw/054UMvgKSJQ7YixllDizt+xv1Wi4RhWBZSfe1NXXBIUfcr4jA7ovlS4JIWMbwR4ZMMp6w3QlekR/HdwTfYLedxt9v6G85D0bP3trCqw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=k/LQklnT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="k/LQklnT" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6D7D6C2BCF6; Wed, 23 Sep 2026 00:41:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790124087; bh=ePI4Y4eg/GDdzK+ll3duTQaWYEU9+rwzeCFYNV8BwNE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=k/LQklnTXsuFKyBZiAWzFlH6ELbRkHA243uDoJFse8SjYgQdwHztNBuh50slNxt0w 6cKECIIDxWcNftj6wqWXrbr9wJD+ZHWY4KY3BGnk7mYIqVl8HVZzr199wESHVcEJfD 3YWckwTLMy2tHv9QTsXBcaGbF6CGqTNOeDG4R+kxrONVkdK0Vn9rJ5XtAl2RiQonY7 Y5l2PGg+f0qUBvOx0kyRatQlCmNoEk2118VJSYrEwNvfecJMAA3BIVJgeOljnFPS2f OCakagTpnwSA6gvyXikK3Rpx2ZSQUtea9k6cIiQqy6St0GB7DJXXiEZWczwAwvGgxr MP88C4fF0FT2Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F46EC982FE; Wed, 23 Sep 2026 00:41:27 +0000 (UTC) From: Antonin Malzieu Ridolfi via B4 Relay Date: Wed, 23 Sep 2026 02:41:08 +0200 Subject: [PATCH v2 2/4] gpu: nova-core: falcon: Extract PRISCV register Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-b4-extract-pfsp-registers-to-falcon-mod-v2-2-74600fc068c4@nanonej.com> References: <20260923-b4-extract-pfsp-registers-to-falcon-mod-v2-0-74600fc068c4@nanonej.com> In-Reply-To: <20260923-b4-extract-pfsp-registers-to-falcon-mod-v2-0-74600fc068c4@nanonej.com> To: Danilo Krummrich , Alice Ryhl , Alexandre Courbot , David Airlie , Simona Vetter Cc: linux-kernel@vger.kernel.org, nova-gpu@lists.linux.dev, dri-devel@lists.freedesktop.org, Antonin Malzieu Ridolfi X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7363; i=dev@nanonej.com; h=from:subject:message-id; bh=83HrUVKx49I1FnuN+G2/qv9yimAMXRc93HQElDM8cAo=; b=owEBbQKS/ZANAwAKAWaH8SMKFRX9AcsmYgBqsyA1I1GcsmJSnN2+cG9CxGW5pvYzxG7ghjA3b kxyH/ws3UWJAjMEAAEKAB0WIQSDtk+wfJEhL1KFIn1mh/EjChUV/QUCarMgNQAKCRBmh/EjChUV /dQQD/9unBePfilzVr/+zDXZA2HuIrtnfms7kaT8KHC588/aQlcXlSS7Kwa65xPF/RyUQMLow5u T8DRx+ZsypxpxhBs0LJDrzovOuxtcpHoT2c/3e7epnuJt1CeIfsIqVktDqouVy8zSAeFvxj+tMa LDVUFUdp8QmdLPeVpdZ/YYPSZVPA81ag88N5Zp/zxO4xoxa0EzwGYsvJWoKCUQVRVUwJNx0TdlB 2LNxrQONLXdAkr2FmJEpWTXDBa8Aqe9dHKc23PkcwFgPkJ5UPD94llBLGbeHjSo0jttFh0lLeB7 IArrvDpYWDqXLV0G5DDpChjDDbnmWAbZ4vBzicXP2npb4v9+NmQFvfbC0ACGMwVyI5u4eDQTaVH /Q9tQEqzySpZ3ktjsh620NwzVn34v3E2/phpmXNGGUHn8x4XNq/mu3Ucq+v+SEi7Zpz1hYM5MEN GDCm1ya9ZvJlpDvK6Ska0vqgjqJFjasLtTxTWq+Tdt/3gf4GxJh9kv50axMlPVsxRHHOKiVw0a/ kpnR76KGjBSACYcbM+ejf4fDfoIY3tcVOJAEoKr+ZjM/+LGpl8QN14tY+05UK3v1ALiRNtOBfO/ +JbDGuYZait+MYUHB48sRsBaK/omdlLp7eNNU+N9e9iF0qt8P6n+SWKLo/lFX62Hs36497uoHeO e9XRpXSyDdIB9Jg== X-Developer-Key: i=dev@nanonej.com; a=openpgp; fpr=83B64FB07C91212F5285227D6687F1230A1515FD X-Endpoint-Received: by B4 Relay for dev@nanonej.com/default with auth_id=825 X-Original-From: Antonin Malzieu Ridolfi Reply-To: dev@nanonej.com From: Antonin Malzieu Ridolfi Move PRISCV register definitions from the root regs.rs file into the falcon module that own them, in the existing falcon/regs.rs file. This follows the same pattern established by previous commits for GSP, PDISP, PFB, PBUS, PMC and PFSP registers: register definitions move to the module that interprets their service, visibility changes to pub(super). Since PFALCON, PFALCON2 and FUSE registers are defined in the root regs.rs but are also part of the falcon interface, accessed by the whole falcon module. They are re-exported in falcon/regs.rs so falcon code can use a single regs:: prefix. Once these families moves out of the root module, these re-exports will become plain definitions. Suggested-by: Alexandre Courbot Suggested-by: Danilo Krummrich Signed-off-by: Antonin Malzieu Ridolfi --- drivers/gpu/nova-core/falcon/hal/ga102.rs | 2 +- drivers/gpu/nova-core/falcon/hal/tu102.rs | 12 +++---- drivers/gpu/nova-core/falcon/regs.rs | 58 +++++++++++++++++++++++++--= ---- drivers/gpu/nova-core/regs.rs | 29 +--------------- 4 files changed, 54 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/nova-core/falcon/hal/ga102.rs b/drivers/gpu/nova-c= ore/falcon/hal/ga102.rs index f9a8444cf840..7323579a478d 100644 --- a/drivers/gpu/nova-core/falcon/hal/ga102.rs +++ b/drivers/gpu/nova-core/falcon/hal/ga102.rs @@ -18,6 +18,7 @@ driver::Bar0, falcon::{ hal::LoadMethod, + regs, // Falcon, FalconBromParams, FalconEngine, @@ -25,7 +26,6 @@ PFalcon2Registers, PeregrineCoreSelect, // }, - regs, }; =20 use super::FalconHal; diff --git a/drivers/gpu/nova-core/falcon/hal/tu102.rs b/drivers/gpu/nova-c= ore/falcon/hal/tu102.rs index 7fc6e83c2566..068258c69fd9 100644 --- a/drivers/gpu/nova-core/falcon/hal/tu102.rs +++ b/drivers/gpu/nova-core/falcon/hal/tu102.rs @@ -11,14 +11,12 @@ time::Delta, // }; =20 -use crate::{ - falcon::{ - hal::LoadMethod, - Falcon, - FalconBromParams, - FalconEngine, // - }, +use crate::falcon::{ + hal::LoadMethod, regs, // + Falcon, + FalconBromParams, + FalconEngine, }; =20 use super::FalconHal; diff --git a/drivers/gpu/nova-core/falcon/regs.rs b/drivers/gpu/nova-core/f= alcon/regs.rs index 5ccb10946ec4..2ac71a7a4ec2 100644 --- a/drivers/gpu/nova-core/falcon/regs.rs +++ b/drivers/gpu/nova-core/falcon/regs.rs @@ -3,6 +3,37 @@ use crate::driver::NovaRegisters; use kernel::io::register; =20 +use crate::falcon::{ + PFalcon2Registers, + PeregrineCoreSelect, // +}; + +// PRISCV + +register! { + base: PFalcon2Registers; + + /// RISC-V status register for debug (Turing and GA100 only). + /// Reflects current RISC-V core status. + pub(super) NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS(u32) @ 0x00000240 { + /// RISC-V core active/inactive status. + 0:0 active_stat =3D> bool; + } + + /// GA102 and later. + pub(super) NV_PRISCV_RISCV_CPUCTL(u32) @ 0x00000388 { + 7:7 active_stat =3D> bool; + 4:4 halted =3D> bool; + } + + /// GA102 and later. + pub(super) NV_PRISCV_RISCV_BCR_CTRL(u32) @ 0x00000668 { + 8:8 br_fetch =3D> bool; + 4:4 core_select =3D> PeregrineCoreSelect; + 0:0 valid =3D> bool; + } +} + // FSP (Foundation Security Processor) queue registers for Hopper/Blackwel= l Chain of Trust. // These registers manage falcon EMEM communication queues. =20 @@ -26,17 +57,22 @@ } } =20 -// PFALCON registers are defined in the root `regs.rs` but are part of the= falcon -// interface, accessed by the whole falcon module. They are re-exported he= re so -// falcon code can use a single `regs::` prefix. -// Once the PFALCON family moves out of the root module, these re-exports = become +// PFALCON, PFALCON2 and FUSE registers are defined in the root `regs.rs` = but +// are part of the falcon interface, accessed by the whole falcon module. = They +// are re-exported here so falcon code can use a single `regs::` prefix. +// Once these families move out of the root module, these re-exports become // plain definitions. pub(super) use crate::regs::{ - NV_PFALCON_FALCON_BOOTVEC, NV_PFALCON_FALCON_CPUCTL, NV_PFALCON_FALCON= _CPUCTL_ALIAS, - NV_PFALCON_FALCON_DMACTL, NV_PFALCON_FALCON_DMATRFBASE, NV_PFALCON_FAL= CON_DMATRFBASE1, - NV_PFALCON_FALCON_DMATRFCMD, NV_PFALCON_FALCON_DMATRFFBOFFS, NV_PFALCO= N_FALCON_DMATRFMOFFS, - NV_PFALCON_FALCON_DMEMC, NV_PFALCON_FALCON_DMEMD, NV_PFALCON_FALCON_EM= EMC, - NV_PFALCON_FALCON_EMEMD, NV_PFALCON_FALCON_IMEMC, NV_PFALCON_FALCON_IM= EMD, - NV_PFALCON_FALCON_IMEMT, NV_PFALCON_FALCON_MAILBOX0, NV_PFALCON_FALCON= _MAILBOX1, - NV_PFALCON_FALCON_OS, NV_PFALCON_FALCON_RM, NV_PFALCON_FBIF_CTL, NV_PF= ALCON_FBIF_TRANSCFG, + NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION, NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSI= ON, + NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION, NV_FUSE_OPT_FPF_SIZE, + NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID, NV_PFALCON2_FALCON_BROM_ENGIDMA= SK, + NV_PFALCON2_FALCON_BROM_PARAADDR, NV_PFALCON2_FALCON_MOD_SEL, NV_PFALC= ON_FALCON_BOOTVEC, + NV_PFALCON_FALCON_CPUCTL, NV_PFALCON_FALCON_CPUCTL_ALIAS, NV_PFALCON_F= ALCON_DMACTL, + NV_PFALCON_FALCON_DMATRFBASE, NV_PFALCON_FALCON_DMATRFBASE1, NV_PFALCO= N_FALCON_DMATRFCMD, + NV_PFALCON_FALCON_DMATRFFBOFFS, NV_PFALCON_FALCON_DMATRFMOFFS, NV_PFAL= CON_FALCON_DMEMC, + NV_PFALCON_FALCON_DMEMD, NV_PFALCON_FALCON_EMEMC, NV_PFALCON_FALCON_EM= EMD, + NV_PFALCON_FALCON_ENGINE, NV_PFALCON_FALCON_HWCFG2, NV_PFALCON_FALCON_= IMEMC, + NV_PFALCON_FALCON_IMEMD, NV_PFALCON_FALCON_IMEMT, NV_PFALCON_FALCON_MA= ILBOX0, + NV_PFALCON_FALCON_MAILBOX1, NV_PFALCON_FALCON_OS, NV_PFALCON_FALCON_RM= , NV_PFALCON_FBIF_CTL, + NV_PFALCON_FBIF_TRANSCFG, }; diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 693b5148b1d8..0a168b53236d 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -24,8 +24,7 @@ FalconModSelAlgo, FalconSecurityModel, PFalcon2Registers, - PFalconRegisters, - PeregrineCoreSelect, // + PFalconRegisters, // }, mm::tlb::TlbAckMode, // }; @@ -346,32 +345,6 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { } } =20 -// PRISCV - -register! { - base: PFalcon2Registers; - - /// RISC-V status register for debug (Turing and GA100 only). - /// Reflects current RISC-V core status. - pub(crate) NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS(u32) @ 0x00000240 { - /// RISC-V core active/inactive status. - 0:0 active_stat =3D> bool; - } - - /// GA102 and later. - pub(crate) NV_PRISCV_RISCV_CPUCTL(u32) @ 0x00000388 { - 7:7 active_stat =3D> bool; - 4:4 halted =3D> bool; - } - - /// GA102 and later. - pub(crate) NV_PRISCV_RISCV_BCR_CTRL(u32) @ 0x00000668 { - 8:8 br_fetch =3D> bool; - 4:4 core_select =3D> PeregrineCoreSelect; - 0:0 valid =3D> bool; - } -} - // The modules below provide registers that are not identical on all suppo= rted chips. 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This follows the same pattern established by previous commits for GSP, PDISP, PFB, PBUS, PMC, PFSP and PRISCV registers: register definitions move to the module that interprets their service, visibility changes to pub(super). Suggested-by: Alexandre Courbot Suggested-by: Danilo Krummrich Signed-off-by: Antonin Malzieu Ridolfi --- drivers/gpu/nova-core/falcon.rs | 4 ++-- drivers/gpu/nova-core/falcon/regs.rs | 33 ++++++++++++++++++++++++++++----- drivers/gpu/nova-core/regs.rs | 26 -------------------------- 3 files changed, 30 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index 1900d642baa1..60cbd742bad7 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -94,8 +94,8 @@ pub(crate) enum FalconSecurityModel with TryFrom> { =20 bounded_enum! { /// Signing algorithm for a given firmware, used in the - /// [`crate::regs::NV_PFALCON2_FALCON_MOD_SEL`] register. It is passed= to the Falcon Boot ROM - /// (BROM) as a parameter. + /// [`crate::falcon::regs::NV_PFALCON2_FALCON_MOD_SEL`] register. It i= s passed to the Falcon + /// Boot ROM (BROM) as a parameter. #[derive(Debug, Copy, Clone)] pub(crate) enum FalconModSelAlgo with TryFrom> { /// AES. diff --git a/drivers/gpu/nova-core/falcon/regs.rs b/drivers/gpu/nova-core/f= alcon/regs.rs index 2ac71a7a4ec2..09ebaf5424d9 100644 --- a/drivers/gpu/nova-core/falcon/regs.rs +++ b/drivers/gpu/nova-core/falcon/regs.rs @@ -4,10 +4,35 @@ use kernel::io::register; =20 use crate::falcon::{ + FalconModSelAlgo, PFalcon2Registers, PeregrineCoreSelect, // }; =20 +// PFALCON2 + +register! { + base: PFalcon2Registers; + + pub(super) NV_PFALCON2_FALCON_MOD_SEL(u32) @ 0x00000180 { + 7:0 algo ?=3D> FalconModSelAlgo; + } + + pub(super) NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID(u32) @ 0x00000198 { + 7:0 ucode_id =3D> u8; + } + + pub(super) NV_PFALCON2_FALCON_BROM_ENGIDMASK(u32) @ 0x0000019c { + 31:0 value =3D> u32; + } + + /// OpenRM defines this as a register array, but doesn't specify its s= ize and only uses its + /// first element. Be conservative until we know the actual size or ne= ed to use more registers. + pub(super) NV_PFALCON2_FALCON_BROM_PARAADDR(u32)[1] @ 0x00000210 { + 31:0 value =3D> u32; + } +} + // PRISCV =20 register! { @@ -57,16 +82,14 @@ } } =20 -// PFALCON, PFALCON2 and FUSE registers are defined in the root `regs.rs` = but -// are part of the falcon interface, accessed by the whole falcon module. = They +// PFALCON and FUSE registers are defined in the root `regs.rs` but are +// part of the falcon interface, accessed by the whole falcon module. They // are re-exported here so falcon code can use a single `regs::` prefix. // Once these families move out of the root module, these re-exports become // plain definitions. pub(super) use crate::regs::{ NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION, NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSI= ON, - NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION, NV_FUSE_OPT_FPF_SIZE, - NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID, NV_PFALCON2_FALCON_BROM_ENGIDMA= SK, - NV_PFALCON2_FALCON_BROM_PARAADDR, NV_PFALCON2_FALCON_MOD_SEL, NV_PFALC= ON_FALCON_BOOTVEC, + NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION, NV_FUSE_OPT_FPF_SIZE, NV_PFALCON_= FALCON_BOOTVEC, NV_PFALCON_FALCON_CPUCTL, NV_PFALCON_FALCON_CPUCTL_ALIAS, NV_PFALCON_F= ALCON_DMACTL, NV_PFALCON_FALCON_DMATRFBASE, NV_PFALCON_FALCON_DMATRFBASE1, NV_PFALCO= N_FALCON_DMATRFCMD, NV_PFALCON_FALCON_DMATRFFBOFFS, NV_PFALCON_FALCON_DMATRFMOFFS, NV_PFAL= CON_FALCON_DMEMC, diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 0a168b53236d..13ccfd429e05 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -21,9 +21,7 @@ FalconFbifMemType, FalconFbifTarget, FalconMem, - FalconModSelAlgo, FalconSecurityModel, - PFalcon2Registers, PFalconRegisters, // }, mm::tlb::TlbAckMode, // @@ -321,30 +319,6 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { } } =20 -/* PFALCON2 */ - -register! { - base: PFalcon2Registers; - - pub(crate) NV_PFALCON2_FALCON_MOD_SEL(u32) @ 0x00000180 { - 7:0 algo ?=3D> FalconModSelAlgo; - } - - pub(crate) NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID(u32) @ 0x00000198 { - 7:0 ucode_id =3D> u8; - } - - pub(crate) NV_PFALCON2_FALCON_BROM_ENGIDMASK(u32) @ 0x0000019c { - 31:0 value =3D> u32; - } - - /// OpenRM defines this as a register array, but doesn't specify its s= ize and only uses its - /// first element. Be conservative until we know the actual size or ne= ed to use more registers. - pub(crate) NV_PFALCON2_FALCON_BROM_PARAADDR(u32)[1] @ 0x00000210 { - 31:0 value =3D> u32; - } -} - // The modules below provide registers that are not identical on all suppo= rted chips. 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This follows the same pattern established by previous commits for GSP, PDISP, PFB, PBUS, PMC, PFSP, PRISCV and PFALCON2 registers: register definitions move to the module that interprets their service, visibility changes to pub(super). The firmware module still needs to configure the FBIF DMA index used by the bootloader to fetch the FWSEC firmware from system memory, so the falcon module now exposes a set_fbif_transcfg() helper on Falcon to access the NV_PFALCON_FBIF_TRANSCFG register. As the bootloader was the only user of the pfalcon field from outside the falcon module, the field can now be made private, resolving the corresponding TODO. Suggested-by: Alexandre Courbot Suggested-by: Danilo Krummrich Signed-off-by: Antonin Malzieu Ridolfi --- drivers/gpu/nova-core/falcon.rs | 13 +- drivers/gpu/nova-core/falcon/gsp.rs | 23 +- drivers/gpu/nova-core/falcon/regs.rs | 250 +++++++++++++++++= ++-- drivers/gpu/nova-core/firmware/fwsec/bootloader.rs | 18 +- drivers/gpu/nova-core/regs.rs | 222 +----------------- 5 files changed, 263 insertions(+), 263 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index 60cbd742bad7..95b5146af5b2 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -44,8 +44,8 @@ pub(crate) const MEM_BLOCK_ALIGNMENT: usize =3D 256; =20 bounded_enum! { - /// Revision number of a falcon core, used in the [`crate::regs::NV_PF= ALCON_FALCON_HWCFG1`] - /// register. + /// Revision number of a falcon core, used in the + /// [`crate::falcon::regs::NV_PFALCON_FALCON_HWCFG1`] register. #[derive(Debug, Copy, Clone)] pub(crate) enum FalconCoreRev with TryFrom> { Rev1 =3D 1, @@ -60,7 +60,7 @@ pub(crate) enum FalconCoreRev with TryFrom> { =20 bounded_enum! { /// Revision subversion number of a falcon core, used in the - /// [`crate::regs::NV_PFALCON_FALCON_HWCFG1`] register. + /// [`crate::falcon::regs::NV_PFALCON_FALCON_HWCFG1`] register. #[derive(Debug, Copy, Clone)] pub(crate) enum FalconCoreRevSubversion with From> { Subversion0 =3D 0, @@ -106,8 +106,8 @@ pub(crate) enum FalconModSelAlgo with TryFrom> { } =20 bounded_enum! { - /// Valid values for the `size` field of the [`crate::regs::NV_PFALCON= _FALCON_DMATRFCMD`] - /// register. + /// Valid values for the `size` field of the + /// [`crate::falcon::regs::NV_PFALCON_FALCON_DMATRFCMD`] register. #[derive(Debug, Copy, Clone)] pub(crate) enum DmaTrfCmdSize with TryFrom> { /// 256 bytes transfer. @@ -364,8 +364,7 @@ pub(crate) struct Falcon<'a, E: FalconEngine> { hal: KBox>, dev: &'a device::Device, bar: Bar0<'a>, - // TODO: make private - pub(crate) pfalcon: Mmio<'a, PFalconRegisters>, + pfalcon: Mmio<'a, PFalconRegisters>, pfalcon2: Mmio<'a, PFalcon2Registers>, } =20 diff --git a/drivers/gpu/nova-core/falcon/gsp.rs b/drivers/gpu/nova-core/fa= lcon/gsp.rs index 4c96ae325fda..a14795657c9e 100644 --- a/drivers/gpu/nova-core/falcon/gsp.rs +++ b/drivers/gpu/nova-core/falcon/gsp.rs @@ -5,6 +5,7 @@ io_project, poll::read_poll_timeout, register, + register::Array, Io, Mmio, // }, @@ -18,10 +19,12 @@ NovaRegisters, // }, falcon::{ + regs, Falcon, - FalconEngine, // + FalconEngine, + FalconFbifMemType, + FalconFbifTarget, // }, - regs, }; =20 /// Type specifying the `Gsp` falcon engine. Cannot be instantiated. @@ -57,7 +60,7 @@ pub(crate) fn clear_swgen0_intr(&self) { /// Checks if GSP reload/resume has completed during the boot process. pub(crate) fn check_reload_completed(&self, timeout: Delta) -> Result<= bool> { read_poll_timeout( - || Ok(self.bar.read(regs::NV_PGC6_BSI_SECURE_SCRATCH_14)), + || Ok(self.bar.read(crate::regs::NV_PGC6_BSI_SECURE_SCRATCH_14= )), |val| val.boot_stage_3_handoff(), Delta::ZERO, timeout, @@ -83,4 +86,18 @@ pub(crate) fn priv_target_mask_released(&self) -> bool { =20 hwcfg2 !=3D 0 && (hwcfg2 & LOCKED_MASK) !=3D LOCKED_PATTERN } + + /// Configures the FBIF translation registers for the given DMA contex= t. + pub(crate) fn set_fbif_transcfg( + &self, + ctx_dma: usize, + target: FalconFbifTarget, + mem_type: FalconFbifMemType, + ) -> Result { + self.pfalcon.update( + regs::NV_PFALCON_FBIF_TRANSCFG::try_at(ctx_dma).ok_or(EINVAL)?, + |v| v.with_target(target).with_mem_type(mem_type), + ); + Ok(()) + } } diff --git a/drivers/gpu/nova-core/falcon/regs.rs b/drivers/gpu/nova-core/f= alcon/regs.rs index 09ebaf5424d9..9ef3ffd0fa65 100644 --- a/drivers/gpu/nova-core/falcon/regs.rs +++ b/drivers/gpu/nova-core/falcon/regs.rs @@ -1,14 +1,234 @@ // SPDX-License-Identifier: GPL-2.0 =20 -use crate::driver::NovaRegisters; -use kernel::io::register; +use kernel::{ + io::{ + register, + Io, + Mmio, // + }, + time, // +}; =20 -use crate::falcon::{ - FalconModSelAlgo, - PFalcon2Registers, - PeregrineCoreSelect, // +use crate::{ + driver::NovaRegisters, + falcon::{ + DmaTrfCmdSize, + FalconCoreRev, + FalconCoreRevSubversion, + FalconFbifMemType, + FalconFbifTarget, + FalconMem, + FalconModSelAlgo, + FalconSecurityModel, + PFalcon2Registers, + PFalconRegisters, + PeregrineCoreSelect, // + }, }; =20 +// PFALCON + +register! { + base: PFalconRegisters; + + pub(super) NV_PFALCON_FALCON_IRQSCLR(u32) @ 0x00000004 { + 6:6 swgen0 =3D> bool; + 4:4 halt =3D> bool; + } + + pub(super) NV_PFALCON_FALCON_MAILBOX0(u32) @ 0x00000040 { + 31:0 value =3D> u32; + } + + pub(super) NV_PFALCON_FALCON_MAILBOX1(u32) @ 0x00000044 { + 31:0 value =3D> u32; + } + + /// Used to store version information about the firmware running + /// on the Falcon processor. + pub(super) NV_PFALCON_FALCON_OS(u32) @ 0x00000080 { + 31:0 value =3D> u32; + } + + pub(super) NV_PFALCON_FALCON_RM(u32) @ 0x00000084 { + 31:0 value =3D> u32; + } + + pub(super) NV_PFALCON_FALCON_HWCFG2(u32) @ 0x000000f4 { + /// Signal indicating that reset is completed (GA102+). + 31:31 reset_ready =3D> bool; + /// RISC-V branch privilege lockdown bit. + 13:13 riscv_br_priv_lockdown =3D> bool; + /// Set to 0 after memory scrubbing is completed. + 12:12 mem_scrubbing =3D> bool; + 10:10 riscv =3D> bool; + } + + pub(super) NV_PFALCON_FALCON_CPUCTL(u32) @ 0x00000100 { + 6:6 alias_en =3D> bool; + 4:4 halted =3D> bool; + 1:1 startcpu =3D> bool; + } + + pub(super) NV_PFALCON_FALCON_BOOTVEC(u32) @ 0x00000104 { + 31:0 value =3D> u32; + } + + pub(super) NV_PFALCON_FALCON_DMACTL(u32) @ 0x0000010c { + 7:7 secure_stat =3D> bool; + 6:3 dmaq_num; + 2:2 imem_scrubbing =3D> bool; + 1:1 dmem_scrubbing =3D> bool; + 0:0 require_ctx =3D> bool; + } + + pub(super) NV_PFALCON_FALCON_DMATRFBASE(u32) @ 0x00000110 { + 31:0 base =3D> u32; + } + + pub(super) NV_PFALCON_FALCON_DMATRFMOFFS(u32) @ 0x00000114 { + 23:0 offs; + } + + pub(super) NV_PFALCON_FALCON_DMATRFCMD(u32) @ 0x00000118 { + 16:16 set_dmtag; + 14:12 ctxdma; + 10:8 size ?=3D> DmaTrfCmdSize; + 5:5 is_write =3D> bool; + 4:4 imem =3D> bool; + 3:2 sec; + 1:1 idle =3D> bool; + 0:0 full =3D> bool; + } + + pub(super) NV_PFALCON_FALCON_DMATRFFBOFFS(u32) @ 0x0000011c { + 31:0 offs =3D> u32; + } + + pub(super) NV_PFALCON_FALCON_DMATRFBASE1(u32) @ 0x00000128 { + 8:0 base; + } + + pub(super) NV_PFALCON_FALCON_HWCFG1(u32) @ 0x0000012c { + /// Core revision subversion. + 7:6 core_rev_subversion =3D> FalconCoreRevSubversion; + /// Security model. + 5:4 security_model ?=3D> FalconSecurityModel; + /// Core revision. + 3:0 core_rev ?=3D> FalconCoreRev; + } + + pub(super) NV_PFALCON_FALCON_CPUCTL_ALIAS(u32) @ 0x00000130 { + 1:1 startcpu =3D> bool; + } + + /// IMEM access control register. Up to 4 ports are available for IMEM= access. + pub(super) NV_PFALCON_FALCON_IMEMC(u32)[4, stride =3D 16] @ 0x00000180= { + /// Access secure IMEM. + 28:28 secure =3D> bool; + /// Auto-increment on write. + 24:24 aincw =3D> bool; + /// IMEM block and word offset. + 15:0 offs; + } + + /// IMEM data register. Reading/writing this register accesses IMEM at= the address + /// specified by the corresponding IMEMC register. + pub(super) NV_PFALCON_FALCON_IMEMD(u32)[4, stride =3D 16] @ 0x00000184= { + 31:0 data; + } + + /// IMEM tag register. Used to set the tag for the current IMEM block. + pub(super) NV_PFALCON_FALCON_IMEMT(u32)[4, stride =3D 16] @ 0x00000188= { + 15:0 tag; + } + + /// DMEM access control register. Up to 8 ports are available for DMEM= access. + pub(super) NV_PFALCON_FALCON_DMEMC(u32)[8, stride =3D 8] @ 0x000001c0 { + /// Auto-increment on write. + 24:24 aincw =3D> bool; + /// DMEM block and word offset. + 15:0 offs; + } + + /// DMEM data register. Reading/writing this register accesses DMEM at= the address + /// specified by the corresponding DMEMC register. + pub(super) NV_PFALCON_FALCON_DMEMD(u32)[8, stride =3D 8] @ 0x000001c4 { + 31:0 data; + } + + /// Actually known as `NV_PSEC_FALCON_ENGINE` and `NV_PGSP_FALCON_ENGI= NE` depending on the + /// falcon instance. + pub(super) NV_PFALCON_FALCON_ENGINE(u32) @ 0x000003c0 { + 0:0 reset =3D> bool; + } + + pub(super) NV_PFALCON_FBIF_TRANSCFG(u32)[8] @ 0x00000600 { + 2:2 mem_type =3D> FalconFbifMemType; + 1:0 target ?=3D> FalconFbifTarget; + } + + pub(super) NV_PFALCON_FBIF_CTL(u32) @ 0x00000624 { + 7:7 allow_phys_no_ctx =3D> bool; + } + + // Falcon EMEM PIO registers (used by FSP on Hopper/Blackwell). + // These provide the falcon external memory communication interface. + + pub(super) NV_PFALCON_FALCON_EMEMC(u32) @ 0x00000ac0 { + /// EMEM byte offset (4-byte aligned) within the block. + 7:2 offs; + /// EMEM block to access. + 15:8 blk; + /// Auto-increment the offset after each write. + 24:24 aincw =3D> bool; + /// Auto-increment the offset after each read. + 25:25 aincr =3D> bool; + } + + pub(super) NV_PFALCON_FALCON_EMEMD(u32) @ 0x00000ac4 { + 31:0 data =3D> u32; + } +} + +impl NV_PFALCON_FALCON_DMACTL { + /// Returns `true` if memory scrubbing is completed. + pub(super) fn mem_scrubbing_done(self) -> bool { + !self.dmem_scrubbing() && !self.imem_scrubbing() + } +} + +impl NV_PFALCON_FALCON_DMATRFCMD { + /// Programs the `imem` and `sec` fields for the given FalconMem + pub(super) fn with_falcon_mem(self, mem: FalconMem) -> Self { + let this =3D self.with_imem(mem !=3D FalconMem::Dmem); + + match mem { + FalconMem::ImemSecure =3D> this.with_const_sec::<1>(), + _ =3D> this.with_const_sec::<0>(), + } + } +} + +impl NV_PFALCON_FALCON_ENGINE { + /// Resets the falcon + pub(super) fn reset_engine(pfalcon: Mmio<'_, PFalconRegisters>) { + pfalcon.update(NV_PFALCON_FALCON_ENGINE, |r| r.with_reset(true)); + + // TIMEOUT: falcon engine should not take more than 10us to reset. + time::delay::fsleep(time::Delta::from_micros(10)); + + pfalcon.update(NV_PFALCON_FALCON_ENGINE, |r| r.with_reset(false)); + } +} + +impl NV_PFALCON_FALCON_HWCFG2 { + /// Returns `true` if memory scrubbing is completed. + pub(super) fn mem_scrubbing_done(self) -> bool { + !self.mem_scrubbing() + } +} + // PFALCON2 =20 register! { @@ -82,20 +302,10 @@ } } =20 -// PFALCON and FUSE registers are defined in the root `regs.rs` but are -// part of the falcon interface, accessed by the whole falcon module. They -// are re-exported here so falcon code can use a single `regs::` prefix. -// Once these families move out of the root module, these re-exports become -// plain definitions. +// FUSE registers are defined in the root `regs.rs` but are part of the +// falcon interface, accessed by the whole falcon module. They are +// re-exported here so falcon code can use a single `regs::` prefix. pub(super) use crate::regs::{ NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION, NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSI= ON, - NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION, NV_FUSE_OPT_FPF_SIZE, NV_PFALCON_= FALCON_BOOTVEC, - NV_PFALCON_FALCON_CPUCTL, NV_PFALCON_FALCON_CPUCTL_ALIAS, NV_PFALCON_F= ALCON_DMACTL, - NV_PFALCON_FALCON_DMATRFBASE, NV_PFALCON_FALCON_DMATRFBASE1, NV_PFALCO= N_FALCON_DMATRFCMD, - NV_PFALCON_FALCON_DMATRFFBOFFS, NV_PFALCON_FALCON_DMATRFMOFFS, NV_PFAL= CON_FALCON_DMEMC, - NV_PFALCON_FALCON_DMEMD, NV_PFALCON_FALCON_EMEMC, NV_PFALCON_FALCON_EM= EMD, - NV_PFALCON_FALCON_ENGINE, NV_PFALCON_FALCON_HWCFG2, NV_PFALCON_FALCON_= IMEMC, - NV_PFALCON_FALCON_IMEMD, NV_PFALCON_FALCON_IMEMT, NV_PFALCON_FALCON_MA= ILBOX0, - NV_PFALCON_FALCON_MAILBOX1, NV_PFALCON_FALCON_OS, NV_PFALCON_FALCON_RM= , NV_PFALCON_FBIF_CTL, - NV_PFALCON_FBIF_TRANSCFG, + NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION, NV_FUSE_OPT_FPF_SIZE, }; diff --git a/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs b/drivers/g= pu/nova-core/firmware/fwsec/bootloader.rs index a87878fe2aec..db1cb4498acd 100644 --- a/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs +++ b/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs @@ -12,10 +12,6 @@ Device, // }, dma::Coherent, - io::{ - register::Array, - Io, // - }, prelude::*, ptr::{ Alignable, @@ -48,7 +44,6 @@ }, gpu::Chipset, num::FromSafeCast, // - regs, }; =20 /// Structure used by the boot-loader to load the rest of the code. @@ -247,14 +242,11 @@ pub(crate) fn run(&self, dev: &Device,= falcon: &Falcon<'_, Gsp>) .inspect_err(|e| dev_err!(dev, "Failed to load FWSEC firmware:= {:?}\n", e))?; =20 // Configure DMA index for the bootloader to fetch the FWSEC firmw= are from system memory. - falcon.pfalcon.update( - regs::NV_PFALCON_FBIF_TRANSCFG::try_at(usize::from_safe_cast(s= elf.dmem_desc.ctx_dma)) - .ok_or(EINVAL)?, - |v| { - v.with_target(FalconFbifTarget::CoherentSysmem) - .with_mem_type(FalconFbifMemType::Physical) - }, - ); + falcon.set_fbif_transcfg( + usize::from_safe_cast(self.dmem_desc.ctx_dma), + FalconFbifTarget::CoherentSysmem, + FalconFbifMemType::Physical, + )?; =20 let (mbox0, _) =3D falcon .boot(Some(0), None) diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 13ccfd429e05..34cf62b4c8f8 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -2,28 +2,13 @@ // SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AF= FILIATES. All rights reserved. =20 use kernel::{ - io::{ - register, - Io, - Mmio, // - }, - sizes::SizeConstants, - time, // + io::register, + sizes::SizeConstants, // }; use pin_init::Zeroable; =20 use crate::{ driver::NovaRegisters, - falcon::{ - DmaTrfCmdSize, - FalconCoreRev, - FalconCoreRevSubversion, - FalconFbifMemType, - FalconFbifTarget, - FalconMem, - FalconSecurityModel, - PFalconRegisters, // - }, mm::tlb::TlbAckMode, // }; =20 @@ -116,209 +101,6 @@ pub(crate) fn usable_fb_size(self) -> u64 { } } =20 -// PFALCON - -register! { - base: PFalconRegisters; - - pub(crate) NV_PFALCON_FALCON_IRQSCLR(u32) @ 0x00000004 { - 6:6 swgen0 =3D> bool; - 4:4 halt =3D> bool; - } - - pub(crate) NV_PFALCON_FALCON_MAILBOX0(u32) @ 0x00000040 { - 31:0 value =3D> u32; - } - - pub(crate) NV_PFALCON_FALCON_MAILBOX1(u32) @ 0x00000044 { - 31:0 value =3D> u32; - } - - /// Used to store version information about the firmware running - /// on the Falcon processor. - pub(crate) NV_PFALCON_FALCON_OS(u32) @ 0x00000080 { - 31:0 value =3D> u32; - } - - pub(crate) NV_PFALCON_FALCON_RM(u32) @ 0x00000084 { - 31:0 value =3D> u32; - } - - pub(crate) NV_PFALCON_FALCON_HWCFG2(u32) @ 0x000000f4 { - /// Signal indicating that reset is completed (GA102+). - 31:31 reset_ready =3D> bool; - /// RISC-V branch privilege lockdown bit. - 13:13 riscv_br_priv_lockdown =3D> bool; - /// Set to 0 after memory scrubbing is completed. - 12:12 mem_scrubbing =3D> bool; - 10:10 riscv =3D> bool; - } - - pub(crate) NV_PFALCON_FALCON_CPUCTL(u32) @ 0x00000100 { - 6:6 alias_en =3D> bool; - 4:4 halted =3D> bool; - 1:1 startcpu =3D> bool; - } - - pub(crate) NV_PFALCON_FALCON_BOOTVEC(u32) @ 0x00000104 { - 31:0 value =3D> u32; - } - - pub(crate) NV_PFALCON_FALCON_DMACTL(u32) @ 0x0000010c { - 7:7 secure_stat =3D> bool; - 6:3 dmaq_num; - 2:2 imem_scrubbing =3D> bool; - 1:1 dmem_scrubbing =3D> bool; - 0:0 require_ctx =3D> bool; - } - - pub(crate) NV_PFALCON_FALCON_DMATRFBASE(u32) @ 0x00000110 { - 31:0 base =3D> u32; - } - - pub(crate) NV_PFALCON_FALCON_DMATRFMOFFS(u32) @ 0x00000114 { - 23:0 offs; - } - - pub(crate) NV_PFALCON_FALCON_DMATRFCMD(u32) @ 0x00000118 { - 16:16 set_dmtag; - 14:12 ctxdma; - 10:8 size ?=3D> DmaTrfCmdSize; - 5:5 is_write =3D> bool; - 4:4 imem =3D> bool; - 3:2 sec; - 1:1 idle =3D> bool; - 0:0 full =3D> bool; - } - - pub(crate) NV_PFALCON_FALCON_DMATRFFBOFFS(u32) @ 0x0000011c { - 31:0 offs =3D> u32; - } - - pub(crate) NV_PFALCON_FALCON_DMATRFBASE1(u32) @ 0x00000128 { - 8:0 base; - } - - pub(crate) NV_PFALCON_FALCON_HWCFG1(u32) @ 0x0000012c { - /// Core revision subversion. - 7:6 core_rev_subversion =3D> FalconCoreRevSubversion; - /// Security model. - 5:4 security_model ?=3D> FalconSecurityModel; - /// Core revision. - 3:0 core_rev ?=3D> FalconCoreRev; - } - - pub(crate) NV_PFALCON_FALCON_CPUCTL_ALIAS(u32) @ 0x00000130 { - 1:1 startcpu =3D> bool; - } - - /// IMEM access control register. Up to 4 ports are available for IMEM= access. - pub(crate) NV_PFALCON_FALCON_IMEMC(u32)[4, stride =3D 16] @ 0x00000180= { - /// Access secure IMEM. - 28:28 secure =3D> bool; - /// Auto-increment on write. - 24:24 aincw =3D> bool; - /// IMEM block and word offset. - 15:0 offs; - } - - /// IMEM data register. Reading/writing this register accesses IMEM at= the address - /// specified by the corresponding IMEMC register. - pub(crate) NV_PFALCON_FALCON_IMEMD(u32)[4, stride =3D 16] @ 0x00000184= { - 31:0 data; - } - - /// IMEM tag register. Used to set the tag for the current IMEM block. - pub(crate) NV_PFALCON_FALCON_IMEMT(u32)[4, stride =3D 16] @ 0x00000188= { - 15:0 tag; - } - - /// DMEM access control register. Up to 8 ports are available for DMEM= access. - pub(crate) NV_PFALCON_FALCON_DMEMC(u32)[8, stride =3D 8] @ 0x000001c0 { - /// Auto-increment on write. - 24:24 aincw =3D> bool; - /// DMEM block and word offset. - 15:0 offs; - } - - /// DMEM data register. Reading/writing this register accesses DMEM at= the address - /// specified by the corresponding DMEMC register. - pub(crate) NV_PFALCON_FALCON_DMEMD(u32)[8, stride =3D 8] @ 0x000001c4 { - 31:0 data; - } - - /// Actually known as `NV_PSEC_FALCON_ENGINE` and `NV_PGSP_FALCON_ENGI= NE` depending on the - /// falcon instance. - pub(crate) NV_PFALCON_FALCON_ENGINE(u32) @ 0x000003c0 { - 0:0 reset =3D> bool; - } - - pub(crate) NV_PFALCON_FBIF_TRANSCFG(u32)[8] @ 0x00000600 { - 2:2 mem_type =3D> FalconFbifMemType; - 1:0 target ?=3D> FalconFbifTarget; - } - - pub(crate) NV_PFALCON_FBIF_CTL(u32) @ 0x00000624 { - 7:7 allow_phys_no_ctx =3D> bool; - } - - // Falcon EMEM PIO registers (used by FSP on Hopper/Blackwell). - // These provide the falcon external memory communication interface. - - pub(crate) NV_PFALCON_FALCON_EMEMC(u32) @ 0x00000ac0 { - /// EMEM byte offset (4-byte aligned) within the block. - 7:2 offs; - /// EMEM block to access. - 15:8 blk; - /// Auto-increment the offset after each write. - 24:24 aincw =3D> bool; - /// Auto-increment the offset after each read. - 25:25 aincr =3D> bool; - } - - pub(crate) NV_PFALCON_FALCON_EMEMD(u32) @ 0x00000ac4 { - 31:0 data =3D> u32; - } -} - -impl NV_PFALCON_FALCON_DMACTL { - /// Returns `true` if memory scrubbing is completed. - pub(crate) fn mem_scrubbing_done(self) -> bool { - !self.dmem_scrubbing() && !self.imem_scrubbing() - } -} - -impl NV_PFALCON_FALCON_DMATRFCMD { - /// Programs the `imem` and `sec` fields for the given FalconMem - pub(crate) fn with_falcon_mem(self, mem: FalconMem) -> Self { - let this =3D self.with_imem(mem !=3D FalconMem::Dmem); - - match mem { - FalconMem::ImemSecure =3D> this.with_const_sec::<1>(), - _ =3D> this.with_const_sec::<0>(), - } - } -} - -impl NV_PFALCON_FALCON_ENGINE { - /// Resets the falcon - pub(crate) fn reset_engine(pfalcon: Mmio<'_, PFalconRegisters>) { - pfalcon.update(NV_PFALCON_FALCON_ENGINE, |r| r.with_reset(true)); - - // TIMEOUT: falcon engine should not take more than 10us to reset. - time::delay::fsleep(time::Delta::from_micros(10)); - - pfalcon.update(NV_PFALCON_FALCON_ENGINE, |r| r.with_reset(false)); - } -} - -impl NV_PFALCON_FALCON_HWCFG2 { - /// Returns `true` if memory scrubbing is completed. - pub(crate) fn mem_scrubbing_done(self) -> bool { - !self.mem_scrubbing() - } -} - // The modules below provide registers that are not identical on all suppo= rted chips. They should // only be used in HAL modules. =20 --=20 2.55.0