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[82.67.6.57]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4886876c500sm9316780f8f.19.2026.09.23.13.47.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 13:47:43 -0700 (PDT) From: Jerome Brunet Date: Wed, 23 Sep 2026 22:47:31 +0200 Subject: [PATCH net-next v3 1/5] dt-bindings: net: sun8i-emac: Add A733 GMAC210 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-allwinner-a733-gmac-support-v3-1-15735155a789@baylibre.com> References: <20260923-allwinner-a733-gmac-support-v3-0-15735155a789@baylibre.com> In-Reply-To: <20260923-allwinner-a733-gmac-support-v3-0-15735155a789@baylibre.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Richard Cochran , Maxime Ripard , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Maxime Chevallier Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Andre Przywara , Jerome Brunet X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6760; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=2Rk7dcj1EIntxo1C/ioN2dfS7ZxOV+D+YaH7GClK4Vk=; b=owGbwMvMwCW2VtK+WnvWU3HG02pJDFlbrN5qaUf77BN3bJwfJC++VkBvYaWMbYWR1afZ6mJr4 ja++vSso4SFQYyLQVZMkaWGu1r8naTWl1nTdW7DzGFlAhnCwMUpABPZupHhxz517jN7T5x3alB1 N9/pM2vPwZOyh00kIpz4098WTOzczMgwY17a0wPyxufk71jW3GtatmaK+xmGP3+FGRsu27j4yvX xAwA= X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 The A733 GMAC210 is a DesignWare MAC 5.20 close to the A523 GMAC200, with the following differences: * The glue configuration registers are a dedicated MMIO region of the controller instead of a syscon register, so a second reg entry replaces the syscon phandle. * The DMA channels and the LPI event have their own interrupt lines. * A PTP reference clock and an AHB reset are needed. * Unlike the A523, the controller does not appear to belong to a power domain. * The TX clock delay field is 5 bits wide and both TX and RX delays use a 180ps step, allowing up to 5580ps. Add the new compatible and describe those differences. Declare the internal delay properties at the top level and keep their limits per compatible. Reviewed-by: Rob Herring (Arm) Signed-off-by: Jerome Brunet --- .../bindings/net/allwinner,sun8i-a83t-emac.yaml | 142 +++++++++++++++++= +--- 1 file changed, 126 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-ema= c.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.ya= ml index 323a669fa982..a4e0d9b760fe 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -22,6 +22,7 @@ select: - allwinner,sun8i-v3s-emac - allwinner,sun50i-a64-emac - allwinner,sun55i-a523-gmac200 + - allwinner,sun60i-a733-gmac210 required: - compatible =20 @@ -44,25 +45,38 @@ properties: - items: - const: allwinner,sun55i-a523-gmac200 - const: snps,dwmac-4.20a + - items: + - const: allwinner,sun60i-a733-gmac210 + - const: snps,dwmac-5.20 =20 reg: - maxItems: 1 + minItems: 1 + items: + - description: MAC controller registers + - description: Glue configuration registers =20 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 4 =20 interrupt-names: - const: macirq + minItems: 1 + items: + - const: macirq + - const: eth_lpi + - const: tx-queue-0 + - const: rx-queue-0 =20 clocks: minItems: 1 - maxItems: 2 + maxItems: 3 =20 clock-names: minItems: 1 items: - const: stmmaceth - const: mbus + - const: ptp_ref =20 phy-supply: description: PHY regulator @@ -76,6 +90,18 @@ properties: Phandle to the device containing the EMAC or GMAC clock register =20 + tx-internal-delay-ps: + default: 0 + minimum: 0 + description: + Internal RGMII PHY TX clock delay chain value in ps. + + rx-internal-delay-ps: + default: 0 + minimum: 0 + description: + Internal RGMII PHY RX clock delay chain value in ps. + required: - compatible - reg @@ -87,7 +113,6 @@ required: - reset-names - phy-handle - phy-mode - - syscon =20 allOf: - $ref: snps,dwmac.yaml# @@ -215,6 +240,34 @@ allOf: - mdio-parent-bus - mdio@1 =20 + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-a83t-emac + - allwinner,sun8i-h3-emac + - allwinner,sun8i-r40-gmac + - allwinner,sun8i-v3s-emac + - allwinner,sun50i-a64-emac + then: + properties: + reg: + maxItems: 1 + interrupts: + maxItems: 1 + interrupt-names: + maxItems: 1 + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + power-domains: false + tx-internal-delay-ps: false + rx-internal-delay-ps: false + required: + - syscon + - if: properties: compatible: @@ -222,32 +275,60 @@ allOf: const: allwinner,sun55i-a523-gmac200 then: properties: + reg: + maxItems: 1 + interrupts: + maxItems: 1 + interrupt-names: + maxItems: 1 clocks: minItems: 2 + maxItems: 2 clock-names: minItems: 2 + maxItems: 2 + resets: + maxItems: 1 + reset-names: + maxItems: 1 tx-internal-delay-ps: - default: 0 - minimum: 0 maximum: 700 multipleOf: 100 - description: - External RGMII PHY TX clock delay chain value in ps. rx-internal-delay-ps: - default: 0 - minimum: 0 maximum: 3100 multipleOf: 100 - description: - External RGMII PHY TX clock delay chain value in ps. required: - power-domains - else: + - syscon + + - if: properties: + compatible: + contains: + const: allwinner,sun60i-a733-gmac210 + then: + properties: + reg: + minItems: 2 + interrupts: + minItems: 4 + interrupt-names: + minItems: 4 clocks: - maxItems: 1 + minItems: 3 clock-names: - maxItems: 1 + minItems: 3 + resets: + minItems: 2 + reset-names: + minItems: 2 + tx-internal-delay-ps: + maximum: 5580 + multipleOf: 180 + rx-internal-delay-ps: + maximum: 5580 + multipleOf: 180 + syscon: false power-domains: false =20 unevaluatedProperties: false @@ -412,4 +493,33 @@ examples: }; }; }; + + - | + ethernet@4510000 { + compatible =3D "allwinner,sun60i-a733-gmac210", + "snps,dwmac-5.20"; + reg =3D <0x04510000 0x8000>, + <0x04518000 0x1000>; + clocks =3D <&ccu 58>, <&ccu 59>, <&ccu 60>; + clock-names =3D "stmmaceth", "mbus", "ptp_ref"; + resets =3D <&ccu 30>, <&ccu 31>; + reset-names =3D "stmmaceth", "ahb"; + interrupts =3D <0 175 4>, <0 179 4>, <0 176 4>, <0 177 4>; + interrupt-names =3D "macirq", "eth_lpi", "tx-queue-0", "rx-queue-0= "; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii1_pins>; + phy-handle =3D <&ext_rgmii_phy_2>; + phy-mode =3D "rgmii-id"; + snps,fixed-burst; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ext_rgmii_phy_2: ethernet-phy@1 { + reg =3D <1>; + }; + }; + }; ... --=20 2.53.0 From nobody Thu Sep 24 14:27:14 2026 Received: from mail-wm2-f12.google.com (mail-wm2-f12.google.com [74.125.225.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A62FA57D21F for ; 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[82.67.6.57]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49fe5df44f9sm11367675e9.11.2026.09.23.13.47.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 13:47:45 -0700 (PDT) From: Jerome Brunet Date: Wed, 23 Sep 2026 22:47:32 +0200 Subject: [PATCH net-next v3 2/5] net: stmmac: sun55i: Add per-compatible match data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-allwinner-a733-gmac-support-v3-2-15735155a789@baylibre.com> References: <20260923-allwinner-a733-gmac-support-v3-0-15735155a789@baylibre.com> In-Reply-To: <20260923-allwinner-a733-gmac-support-v3-0-15735155a789@baylibre.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Richard Cochran , Maxime Ripard , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Maxime Chevallier Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Andre Przywara , Jerome Brunet X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4588; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=DYM49ne6atEAPBbwp7MW6XIu2N107jKi+6HoBXrWSjs=; b=owGbwMvMwCW2VtK+WnvWU3HG02pJDFlbrN66bpWrmPz5JntSyopU3pdTNryr12g0buPx2RphV zNNfNP2jlIWBjEuBlkxRZYa7mrxd5JaX2ZN17kNM4eVCWQIAxenAEyEM5eRYf7qmbuZ5Q3skvb5 ZNtkmHIU7X2ubZlgtU9wQ6y2xfYHVxn+J69n1tIWZfwm0hWTqKwxVf0Y28P2zvazHA1199pWmxl wAgA= X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 The A733 GMAC210 glue registers are in a dedicated MMIO region of the controller rather than in a syscon, at a different offset. Add per-compatible match data holding the glue resource init callback, the stmmac flags and the glue register offset to prepare the support for the A733. Signed-off-by: Jerome Brunet --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c | 68 +++++++++++++++++-= ---- 1 file changed, 54 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c b/drivers/n= et/ethernet/stmicro/stmmac/dwmac-sun55i.c index 862df173d963..c4df53285007 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -23,8 +24,6 @@ #include "stmmac.h" #include "stmmac_platform.h" =20 -#define SYSCON_REG 0x34 - /* RMII specific bits */ #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ /* Generic system control EMAC_CLK bits */ @@ -37,18 +36,40 @@ #define SYSCON_ETCS_EXT_GMII 0x1 #define SYSCON_ETCS_INT_GMII 0x2 =20 -static int sun55i_gmac200_set_syscon(struct device *dev, - struct plat_stmmacenet_data *plat) +struct sun55i_gmac; + +struct sun55i_gmac_data { + int (*init_resources)(struct platform_device *pdev, + struct sun55i_gmac *gmac); + unsigned int flags; + u32 offset; +}; + +struct sun55i_gmac { + const struct sun55i_gmac_data *data; + struct regmap *regmap; +}; + +static int sun55i_gmac200_init_resources(struct platform_device *pdev, + struct sun55i_gmac *gmac) +{ + gmac->regmap =3D syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "syscon"); + if (IS_ERR(gmac->regmap)) + return dev_err_probe(&pdev->dev, PTR_ERR(gmac->regmap), + "Unable to map syscon\n"); + + return 0; +} + +static int sun55i_gmac200_setup(struct device *dev, + struct plat_stmmacenet_data *plat, + const struct sun55i_gmac *gmac) { struct device_node *node =3D dev->of_node; - struct regmap *regmap; u32 val, reg =3D 0; int ret; =20 - regmap =3D syscon_regmap_lookup_by_phandle(node, "syscon"); - if (IS_ERR(regmap)) - return dev_err_probe(dev, PTR_ERR(regmap), "Unable to map syscon\n"); - if (!of_property_read_u32(node, "tx-internal-delay-ps", &val)) { if (val % 100) return dev_err_probe(dev, -EINVAL, @@ -95,7 +116,7 @@ static int sun55i_gmac200_set_syscon(struct device *dev, phy_modes(plat->phy_interface)); } =20 - ret =3D regmap_write(regmap, SYSCON_REG, reg); + ret =3D regmap_write(gmac->regmap, gmac->data->offset, reg); if (ret < 0) return dev_err_probe(dev, ret, "Failed to write to syscon\n"); =20 @@ -107,22 +128,34 @@ static int sun55i_gmac200_probe(struct platform_devic= e *pdev) struct plat_stmmacenet_data *plat_dat; struct stmmac_resources stmmac_res; struct device *dev =3D &pdev->dev; + struct sun55i_gmac *gmac; struct clk *clk; int ret; =20 + gmac =3D devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); + if (!gmac) + return -ENOMEM; + + gmac->data =3D device_get_match_data(dev); + if (!gmac->data) + return -EINVAL; + ret =3D stmmac_get_platform_resources(pdev, &stmmac_res); if (ret) return ret; =20 + ret =3D gmac->data->init_resources(pdev, gmac); + if (ret) + return ret; + plat_dat =3D devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); if (IS_ERR(plat_dat)) return PTR_ERR(plat_dat); =20 - /* BSP disables it */ - plat_dat->flags |=3D STMMAC_FLAG_SPH_DISABLE; + plat_dat->flags |=3D gmac->data->flags; plat_dat->host_dma_width =3D 32; =20 - ret =3D sun55i_gmac200_set_syscon(dev, plat_dat); + ret =3D sun55i_gmac200_setup(dev, plat_dat, gmac); if (ret) return ret; =20 @@ -138,8 +171,15 @@ static int sun55i_gmac200_probe(struct platform_device= *pdev) return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); } =20 +static const struct sun55i_gmac_data sun55i_a523_gmac200_data =3D { + .init_resources =3D sun55i_gmac200_init_resources, + .flags =3D STMMAC_FLAG_SPH_DISABLE, + .offset =3D 0x34, +}; + static const struct of_device_id sun55i_gmac200_match[] =3D { - { .compatible =3D "allwinner,sun55i-a523-gmac200" }, + { .compatible =3D "allwinner,sun55i-a523-gmac200", + .data =3D &sun55i_a523_gmac200_data }, { } }; MODULE_DEVICE_TABLE(of, sun55i_gmac200_match); --=20 2.53.0 From nobody Thu Sep 24 14:27:14 2026 Received: from mail-wr2-f12.google.com (mail-wr2-f12.google.com [74.125.225.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0300157ED84 for ; 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[82.67.6.57]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48868889337sm9555748f8f.34.2026.09.23.13.47.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 13:47:46 -0700 (PDT) From: Jerome Brunet Date: Wed, 23 Sep 2026 22:47:33 +0200 Subject: [PATCH net-next v3 3/5] net: stmmac: sun55i: Make the delay step configurable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-allwinner-a733-gmac-support-v3-3-15735155a789@baylibre.com> References: <20260923-allwinner-a733-gmac-support-v3-0-15735155a789@baylibre.com> In-Reply-To: <20260923-allwinner-a733-gmac-support-v3-0-15735155a789@baylibre.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Richard Cochran , Maxime Ripard , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Maxime Chevallier Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Andre Przywara , Jerome Brunet X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3766; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=u9upVCC3m/gwC2XGPIk9ZtnVEycENGqh8TgoKKLgrfg=; b=owGbwMvMwCW2VtK+WnvWU3HG02pJDFlbrN5++fKN4ddvzswl7GeD9uxYOzue282oeJfBhyx2d Xbd7V47OkpZGMS4GGTFFFlquKvF30lqfZk1Xec2zBxWJpAhDFycAjCRaD1GhmnNNr1V5r77khQ4 HbX25/9bvu3Dzwuyn7OsgrnebXjtspyRYdbv72zn5HrC7edE8K44+fH1tYCm98+630TxzXNqrpr /ghEA X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 The driver assumes a 100ps step for both TX and RX clock delays, which does not match the A733 GMAC210. Move the TX and RX delay steps to the match data and factor the delay validation into a helper. The A523 keeps the 100ps step to preserve the DT ABI, although the vendor reports actual steps of 180ps for TX and 530ps for RX. Signed-off-by: Jerome Brunet --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c | 58 +++++++++++++++---= ---- 1 file changed, 39 insertions(+), 19 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c b/drivers/n= et/ethernet/stmicro/stmmac/dwmac-sun55i.c index c4df53285007..e759311f40fc 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c @@ -42,6 +42,8 @@ struct sun55i_gmac_data { int (*init_resources)(struct platform_device *pdev, struct sun55i_gmac *gmac); unsigned int flags; + u32 txdly_step_ps; + u32 rxdly_step_ps; u32 offset; }; =20 @@ -62,38 +64,47 @@ static int sun55i_gmac200_init_resources(struct platfor= m_device *pdev, return 0; } =20 +static int sun55i_gmac200_validate_delay(struct device *dev, const char *d= ir, + u32 *val, u32 step, u32 max) +{ + if (*val % step) + return dev_err_probe(dev, -EINVAL, + "%s-delay must be a multiple of %ups\n", dir, step); + max *=3D step; + if (*val > max) + return dev_err_probe(dev, -EINVAL, + "%s clock delay exceeds maximum (%ups > %ups)\n", + dir, *val, max); + *val /=3D step; + dev_dbg(dev, "set %s-delay to %x\n", dir, *val); + + return 0; +} + static int sun55i_gmac200_setup(struct device *dev, struct plat_stmmacenet_data *plat, const struct sun55i_gmac *gmac) { struct device_node *node =3D dev->of_node; - u32 val, reg =3D 0; + u32 val, step, max, reg =3D 0; int ret; =20 if (!of_property_read_u32(node, "tx-internal-delay-ps", &val)) { - if (val % 100) - return dev_err_probe(dev, -EINVAL, - "tx-delay must be a multiple of 100ps\n"); - val /=3D 100; - dev_dbg(dev, "set tx-delay to %x\n", val); - if (!FIELD_FIT(SYSCON_ETXDC_MASK, val)) - return dev_err_probe(dev, -EINVAL, - "TX clock delay exceeds maximum (%u00ps > %lu00ps)\n", - val, FIELD_MAX(SYSCON_ETXDC_MASK)); + step =3D gmac->data->txdly_step_ps; + max =3D FIELD_MAX(SYSCON_ETXDC_MASK); + ret =3D sun55i_gmac200_validate_delay(dev, "tx", &val, step, max); + if (ret) + return ret; =20 reg |=3D FIELD_PREP(SYSCON_ETXDC_MASK, val); } =20 if (!of_property_read_u32(node, "rx-internal-delay-ps", &val)) { - if (val % 100) - return dev_err_probe(dev, -EINVAL, - "rx-delay must be a multiple of 100ps\n"); - val /=3D 100; - dev_dbg(dev, "set rx-delay to %x\n", val); - if (!FIELD_FIT(SYSCON_ERXDC_MASK, val)) - return dev_err_probe(dev, -EINVAL, - "RX clock delay exceeds maximum (%u00ps > %lu00ps)\n", - val, FIELD_MAX(SYSCON_ERXDC_MASK)); + step =3D gmac->data->rxdly_step_ps; + max =3D FIELD_MAX(SYSCON_ERXDC_MASK); + ret =3D sun55i_gmac200_validate_delay(dev, "rx", &val, step, max); + if (ret) + return ret; =20 reg |=3D FIELD_PREP(SYSCON_ERXDC_MASK, val); } @@ -175,6 +186,15 @@ static const struct sun55i_gmac_data sun55i_a523_gmac2= 00_data =3D { .init_resources =3D sun55i_gmac200_init_resources, .flags =3D STMMAC_FLAG_SPH_DISABLE, .offset =3D 0x34, + /* + * The actual delay steps reported by the manufacturer are: + * - Tx: 180ps + * - Rx: 530ps + * + * Correcting them would break the DT ABI of the published DTs. + */ + .txdly_step_ps =3D 100, + .rxdly_step_ps =3D 100, }; =20 static const struct of_device_id sun55i_gmac200_match[] =3D { --=20 2.53.0 From nobody Thu Sep 24 14:27:14 2026 Received: from mail-wr2-f12.google.com (mail-wr2-f12.google.com [74.125.225.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D80957EDA7 for ; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Richard Cochran , Maxime Ripard , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Maxime Chevallier Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Andre Przywara , Jerome Brunet X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1789; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=B+n/07rbShxe+UCgpvoXo+3mb6MPP+M9H3khzu3hpGI=; b=owGbwMvMwCW2VtK+WnvWU3HG02pJDFlbrN6aX1BpNohN+nGv6lzKq6dxK0vWL1vyT8Xpckfx5 h8t31Imd5SyMIhxMciKKbLUcFeLv5PU+jJrus5tmDmsTCBDGLg4BWAiUxYzMizurl7xTPXxju68 fVyKXxfOCvqpquYo5qGe6ZfZve+E8X6Gf6r7XI+uWFA929e1/vyEne/vXV83L8NuGev7YM8Wfde 5XSwA X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 On the A733 GMAC210, the TX clock delay is 5 bits wide: the 3 low bits are in the ETXDC field and the 2 high bits in a separate field. Add an optional mask for the high bits to the match data and set it when necessary. Signed-off-by: Jerome Brunet --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c b/drivers/n= et/ethernet/stmicro/stmmac/dwmac-sun55i.c index e759311f40fc..49abbb248b61 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c @@ -42,6 +42,7 @@ struct sun55i_gmac_data { int (*init_resources)(struct platform_device *pdev, struct sun55i_gmac *gmac); unsigned int flags; + u32 etxdc_ext_mask; u32 txdly_step_ps; u32 rxdly_step_ps; u32 offset; @@ -86,17 +87,21 @@ static int sun55i_gmac200_setup(struct device *dev, const struct sun55i_gmac *gmac) { struct device_node *node =3D dev->of_node; - u32 val, step, max, reg =3D 0; + u32 val, step, max, low_bits, reg =3D 0; int ret; =20 if (!of_property_read_u32(node, "tx-internal-delay-ps", &val)) { + low_bits =3D hweight32(SYSCON_ETXDC_MASK); step =3D gmac->data->txdly_step_ps; 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[82.67.6.57]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49fe5b44db6sm14839105e9.0.2026.09.23.13.47.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 13:47:49 -0700 (PDT) From: Jerome Brunet Date: Wed, 23 Sep 2026 22:47:35 +0200 Subject: [PATCH net-next v3 5/5] net: stmmac: sun55i: Add support for Allwinner A733 GMAC210 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-allwinner-a733-gmac-support-v3-5-15735155a789@baylibre.com> References: <20260923-allwinner-a733-gmac-support-v3-0-15735155a789@baylibre.com> In-Reply-To: <20260923-allwinner-a733-gmac-support-v3-0-15735155a789@baylibre.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Richard Cochran , Maxime Ripard , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Maxime Chevallier Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Andre Przywara , Jerome Brunet X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4132; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=sjLoecwDQJXaWVmzvGOQ+F7IRuyAd48CcawjSycmYoQ=; b=owGbwMvMwCW2VtK+WnvWU3HG02pJDFlbrN669B39qPeAbW7OgdsplxQT71j87Zx16uqMiimtn Lp1lh6lHaUsDGJcDLJiiiw13NXi7yS1vsyarnMbZg4rE8gQBi5OAZiIihkjwyb31d8uyoQbH75s 9sfsjf4n69Uei5jkzL5psmk98r3+tIrhv7f6q8R7G+4cYbbpqebm5Ntqsd2bf3uH2dmQ2SHdm9s c+AA= X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 The A733 GMAC210 is a DesignWare MAC 5.20 using an Allwinner glue close to the A523 GMAC200 already supported by this driver, with the following differences to handle: * The glue configuration registers are a dedicated MMIO region of the controller instead of a syscon register. This region is in the AHB reset domain, so the glue driver releases the shared AHB reset before writing the configuration. * The TX clock delay value is 5 bits wide, split over 2 register fields. Both TX and RX delays use a 180ps step. * The DMA channels have their own interrupt lines, so the per-DMA-channel interrupt mode is enabled, as the vendor SDK does. * TX LPI clock gating is supported, as the vendor SDK indicates. Follow the PHY capability with STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP rather than forcing it on with the deprecated 'snps,en-tx-lpi-clockgating' DT property. Signed-off-by: Jerome Brunet --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c | 53 ++++++++++++++++++= +++- 1 file changed, 52 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c b/drivers/n= et/ethernet/stmicro/stmmac/dwmac-sun55i.c index 49abbb248b61..675b83cd52c8 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c @@ -19,6 +19,7 @@ #include #include #include +#include #include =20 #include "stmmac.h" @@ -65,6 +66,41 @@ static int sun55i_gmac200_init_resources(struct platform= _device *pdev, return 0; } =20 +static const struct regmap_config sun60i_a733_regmap_cfg =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + +static int sun60i_gmac210_init_resources(struct platform_device *pdev, + struct sun55i_gmac *gmac) +{ + struct device *dev =3D &pdev->dev; + struct reset_control *ahb_reset; + void __iomem *base; + + /* + * Get the configuration region out of reset before changing it. + * stmmac core holds the same shared reset but only deasserts it later. + */ + ahb_reset =3D devm_reset_control_get_shared_deasserted(dev, "ahb"); + if (IS_ERR(ahb_reset)) + return dev_err_probe(dev, PTR_ERR(ahb_reset), + "Failed to get ahb reset\n"); + + base =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(base)) + return dev_err_probe(dev, PTR_ERR(base), + "Unable to get config memory region\n"); + + gmac->regmap =3D devm_regmap_init_mmio(dev, base, &sun60i_a733_regmap_cfg= ); + if (IS_ERR(gmac->regmap)) + return dev_err_probe(dev, PTR_ERR(gmac->regmap), + "Unable to get regmap for config memory region\n"); + + return 0; +} + static int sun55i_gmac200_validate_delay(struct device *dev, const char *d= ir, u32 *val, u32 step, u32 max) { @@ -132,9 +168,11 @@ static int sun55i_gmac200_setup(struct device *dev, phy_modes(plat->phy_interface)); } =20 + /* The dwmac will sample this when stmmaceth reset is deasserted */ ret =3D regmap_write(gmac->regmap, gmac->data->offset, reg); if (ret < 0) - return dev_err_probe(dev, ret, "Failed to write to syscon\n"); + return dev_err_probe(dev, ret, + "Failed to write glue configuration\n"); =20 return 0; } @@ -202,9 +240,22 @@ static const struct sun55i_gmac_data sun55i_a523_gmac2= 00_data =3D { .rxdly_step_ps =3D 100, }; =20 +static const struct sun55i_gmac_data sun60i_a733_gmac210_data =3D { + .init_resources =3D sun60i_gmac210_init_resources, + .flags =3D (STMMAC_FLAG_SPH_DISABLE | + STMMAC_FLAG_MULTI_MSI_EN | + STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP), + .offset =3D 0x0, + .etxdc_ext_mask =3D GENMASK(17, 16), + .txdly_step_ps =3D 180, + .rxdly_step_ps =3D 180, +}; + static const struct of_device_id sun55i_gmac200_match[] =3D { { .compatible =3D "allwinner,sun55i-a523-gmac200", .data =3D &sun55i_a523_gmac200_data }, + { .compatible =3D "allwinner,sun60i-a733-gmac210", + .data =3D &sun60i_a733_gmac210_data }, { } }; MODULE_DEVICE_TABLE(of, sun55i_gmac200_match); --=20 2.53.0