From nobody Thu Sep 24 13:42:19 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5AA795452AB for ; Wed, 23 Sep 2026 15:19:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790176762; cv=none; b=skZBCx0rnnDrbbt05jheOoHhXMrcTD97Eb9xV6WQWLkaFo2W3NXLJhZ89rtHrkQ+MV9HGI5S5spzxexP1HK2cCnYRbGXNCLL5T56jqo5JSu77RXjLNLWzvCgbWi7430gs915YT4RxWrITk5EdGib723sT3GxyQ1LW3IdKRPnZnI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790176762; c=relaxed/simple; bh=KqbznSNrRUNcLevg4G3hWSR1TkMYShYp2Nbxiso8Buc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qPfTLObMnfuzZ2w7XdBdhi32twCAu7y1wD8V4E0mXqd9RbQdvBpHj0q0l0muA5P5qQtusCCcLHER1lsXUBj5cWKbYjbWDNm7zsqbDRFW2H73dRKvk6yTL91xiYu84i1Q/1FvL450FLUHkOrzeEprCs6nDrjda2MKv93ny3py4S4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=cFaOoJu6; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="cFaOoJu6" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id C33D1C21ABE; Wed, 23 Sep 2026 15:20:03 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id BCCC260580; Wed, 23 Sep 2026 15:19:16 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 0C7E0103293A6; Wed, 23 Sep 2026 17:19:14 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1790176756; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=AyknOeHh7SbRO//L4ZP7PUxtTmL07EXSJ8hj4BghVYg=; b=cFaOoJu6w/zYv9uzSIrJUnJA759i0r1XB/6qIAhcIl3+KbdT7kjlXhpygGsV7V+ELp6gho AUc5zbDG9XtMIMKPGNwv/sffXsAI3M9gNq80uWiGKee4lxajlFxfNo6abQkXRgoiT+0bw6 g3bcgLA/Lcb6Agy6Eac3pMeLgVirdot3/DXI91h3JMX8xLdmsre3JOlUEzC4zyUg/ceii2 GySnvcOXl2z16mCcue+y75ywCYt9F9cofyl4gmmYA/py0DKWvYjF9cigSfhE5s5lmVVaKL dkxxvRB4dFqGY50ydKTYWHPHAG1+QY3sG9RqOTZUV0HbR4c+bCBSR0UOOgn9Yg== From: Paul Louvel Date: Wed, 23 Sep 2026 17:18:37 +0200 Subject: [PATCH v7 01/20] crypto: talitos/hash - Use CRYPTO_AHASH_BLOCK_ONLY API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-7-3-rc2_talitos_cleanup-v7-1-9a45261fc097@bootlin.com> References: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> In-Reply-To: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> To: Herbert Xu , "David S. Miller" Cc: Paul Louvel , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Christophe Leroy X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790176746; l=16419; i=paul.louvel@bootlin.com; s=20260313; h=from:subject:message-id; bh=KqbznSNrRUNcLevg4G3hWSR1TkMYShYp2Nbxiso8Buc=; b=uDrqqXA5oeqnzDs9kjeL7LqRYUSizdraTe53xj404mgwHPqcV2C6YVyQhV2LUqi6VkgR9dtJ+ vJ1gswZl2AYD3Nu7uTD0pBGvsoaEsv/9zp1tz7QYz+RA7zC0cDPmPpn X-Developer-Key: i=paul.louvel@bootlin.com; a=ed25519; pk=eLW50NT18UAvUT5cAcYf88zNbBCZDLFXuptpyLVhVIU= X-Last-TLS-Session-Version: TLSv1.3 The hash implementation maintained a software buffer to accumulate partial blocks across update() calls, copying data to/from scatterlists with sg_copy_to_buffer()/sg_pcopy_to_buffer() and chaining in a virtual scatterlist entry. This is unnecessary now with CRYPTO_AHASH_ALG_BLOCK_ONLY flag. Remove unnecessary fields in the request and export structure. On completion, pass any remaining tail bytes back via ahash_request_complete() so that the core re-submits them with the next request. Signed-off-by: Paul Louvel --- drivers/crypto/talitos.c | 181 +++++++++++++++++++------------------------= ---- 1 file changed, 74 insertions(+), 107 deletions(-) diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c index fa96b6bf17e3..55ec5a46b71c 100644 --- a/drivers/crypto/talitos.c +++ b/drivers/crypto/talitos.c @@ -934,31 +934,26 @@ struct talitos_ctx { unsigned int authkeylen; }; =20 -#define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE #define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA= 512 =20 struct talitos_ahash_req_ctx { u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)]; + u8 padding_buf[64]; + u64 message_size; unsigned int hw_context_size; - u8 buf[2][HASH_MAX_BLOCK_SIZE]; - int buf_idx; unsigned int swinit; unsigned int first_request; unsigned int last_request; unsigned int to_hash_later; - unsigned int nbuf; - struct scatterlist bufsl[2]; - struct scatterlist *psrc; }; =20 struct talitos_export_state { u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)]; - u8 buf[HASH_MAX_BLOCK_SIZE]; + u64 message_size; unsigned int swinit; unsigned int first_request; unsigned int last_request; unsigned int to_hash_later; - unsigned int nbuf; }; =20 static int aead_setkey(struct crypto_aead *authenc, @@ -1825,14 +1820,8 @@ static void ahash_done(struct device *dev, struct talitos_edesc *next; =20 if (is_sec1) { - if (!req_ctx->last_request && req_ctx->to_hash_later) { - /* Position any partial block for next update/final/finup */ - req_ctx->buf_idx =3D (req_ctx->buf_idx + 1) & 1; - req_ctx->nbuf =3D req_ctx->to_hash_later; - } - free_edesc_list_from(areq, edesc); - ahash_request_complete(areq, err); + ahash_request_complete(areq, err ?: req_ctx->to_hash_later); } else { next =3D edesc->next_desc; =20 @@ -1850,14 +1839,9 @@ static void ahash_done(struct device *dev, return; } out: - if (!req_ctx->last_request && req_ctx->to_hash_later) { - /* Position any partial block for next update/final/finup */ - req_ctx->buf_idx =3D (req_ctx->buf_idx + 1) & 1; - req_ctx->nbuf =3D req_ctx->to_hash_later; - } if (err && next) free_edesc_list_from(areq, next); - ahash_request_complete(areq, err); + ahash_request_complete(areq, err ?: req_ctx->to_hash_later); } } =20 @@ -1865,21 +1849,27 @@ static void ahash_done(struct device *dev, * SEC1 doesn't like hashing of 0 sized message, so we do the padding * ourself and submit a padded block */ -static void talitos_handle_buggy_hash(struct talitos_ctx *ctx, - struct talitos_edesc *edesc, - struct talitos_ptr *ptr) +static void talitos_handle_buggy_hash(struct ahash_request *areq, + struct talitos_edesc *edesc, + struct talitos_ptr *ptr) { - static u8 padded_hash[64] =3D { - 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - }; + struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); + struct talitos_ctx *ctx =3D crypto_ahash_ctx(tfm); =20 + __be64 be_len =3D cpu_to_be64(req_ctx->message_size << 3); + __le64 le_len =3D cpu_to_le64(req_ctx->message_size << 3); + + memset(req_ctx->padding_buf, 0, sizeof(req_ctx->padding_buf)); + req_ctx->padding_buf[0] =3D 0x80; + if (crypto_ahash_digestsize(tfm) =3D=3D MD5_DIGEST_SIZE) + memcpy(&req_ctx->padding_buf[56], &le_len, sizeof(le_len)); + else + memcpy(&req_ctx->padding_buf[56], &be_len, sizeof(be_len)); pr_err_once("Bug in SEC1, padding ourself\n"); edesc->desc.hdr &=3D ~DESC_HDR_MODE0_MDEU_PAD; - map_single_talitos_ptr(ctx->dev, ptr, sizeof(padded_hash), - (char *)padded_hash, DMA_TO_DEVICE); + map_single_talitos_ptr(ctx->dev, ptr, sizeof(req_ctx->padding_buf), + (char *)req_ctx->padding_buf, DMA_TO_DEVICE); } =20 static void common_nonsnoop_hash(struct talitos_edesc *edesc, @@ -1944,7 +1934,7 @@ static void common_nonsnoop_hash(struct talitos_edesc= *edesc, /* last DWORD empty */ =20 if (is_sec1 && from_talitos_ptr_len(&desc->ptr[3], true) =3D=3D 0) - talitos_handle_buggy_hash(ctx, edesc, &desc->ptr[3]); + talitos_handle_buggy_hash(areq, edesc, &desc->ptr[3]); =20 if (sync_needed) dma_sync_single_for_device(dev, edesc->dma_link_tbl, @@ -1977,7 +1967,7 @@ ahash_process_req_prepare(struct ahash_request *areq,= unsigned int nbytes, size_t offset =3D 0; =20 do { - src =3D scatterwalk_ffwd(tmp, req_ctx->psrc, offset); + src =3D scatterwalk_ffwd(tmp, areq->src, offset); =20 to_hash_this_desc =3D min(nbytes, ALIGN_DOWN(desc_max, blocksize)); @@ -1990,8 +1980,7 @@ ahash_process_req_prepare(struct ahash_request *areq,= unsigned int nbytes, return edesc; } =20 - edesc->src =3D - scatterwalk_ffwd(edesc->bufsl, req_ctx->psrc, offset); + edesc->src =3D scatterwalk_ffwd(edesc->bufsl, areq->src, offset); edesc->desc.hdr =3D ctx->desc_hdr_template; edesc->first =3D offset =3D=3D 0; edesc->last =3D nbytes - to_hash_this_desc =3D=3D 0; @@ -2044,62 +2033,17 @@ static int ahash_process_req(struct ahash_request *= areq, unsigned int nbytes) bool is_sec1 =3D has_ftr_sec1(dev_get_drvdata(ctx->dev)); unsigned int nbytes_to_hash; unsigned int to_hash_later; - unsigned int nsg; - int nents; struct device *dev =3D ctx->dev; - u8 *ctx_buf =3D req_ctx->buf[req_ctx->buf_idx]; int ret; =20 - if (!req_ctx->last_request && (nbytes + req_ctx->nbuf <=3D blocksize)) { - /* Buffer up to one whole block */ - nents =3D sg_nents_for_len(areq->src, nbytes); - if (nents < 0) { - dev_err(dev, "Invalid number of src SG.\n"); - return nents; - } - sg_copy_to_buffer(areq->src, nents, - ctx_buf + req_ctx->nbuf, nbytes); - req_ctx->nbuf +=3D nbytes; - return 0; - } + nbytes_to_hash =3D ALIGN_DOWN(nbytes, blocksize); + to_hash_later =3D nbytes - nbytes_to_hash; =20 - /* At least (blocksize + 1) bytes are available to hash */ - nbytes_to_hash =3D nbytes + req_ctx->nbuf; - to_hash_later =3D nbytes_to_hash & (blocksize - 1); - - if (req_ctx->last_request) + if (req_ctx->last_request) { + nbytes_to_hash =3D nbytes; to_hash_later =3D 0; - else if (to_hash_later) - /* There is a partial block. Hash the full block(s) now */ - nbytes_to_hash -=3D to_hash_later; - else { - /* Keep one block buffered */ - nbytes_to_hash -=3D blocksize; - to_hash_later =3D blocksize; - } - - /* Chain in any previously buffered data */ - if (req_ctx->nbuf) { - nsg =3D (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1; - sg_init_table(req_ctx->bufsl, nsg); - sg_set_buf(req_ctx->bufsl, ctx_buf, req_ctx->nbuf); - if (nsg > 1) - sg_chain(req_ctx->bufsl, 2, areq->src); - req_ctx->psrc =3D req_ctx->bufsl; - } else - req_ctx->psrc =3D areq->src; - - if (to_hash_later) { - nents =3D sg_nents_for_len(areq->src, nbytes); - if (nents < 0) { - dev_err(dev, "Invalid number of src SG.\n"); - return nents; - } - sg_pcopy_to_buffer(areq->src, nents, - req_ctx->buf[(req_ctx->buf_idx + 1) & 1], - to_hash_later, - nbytes - to_hash_later); } + req_ctx->to_hash_later =3D to_hash_later; =20 edesc =3D ahash_process_req_prepare(areq, nbytes_to_hash, blocksize, @@ -2107,9 +2051,13 @@ static int ahash_process_req(struct ahash_request *a= req, unsigned int nbytes) if (IS_ERR(edesc)) return PTR_ERR(edesc); =20 + req_ctx->message_size +=3D nbytes_to_hash; + ret =3D talitos_submit(dev, ctx->ch, &edesc->desc, ahash_done, areq); - if (ret !=3D -EINPROGRESS) + if (ret !=3D -EINPROGRESS) { + req_ctx->message_size -=3D nbytes_to_hash; free_edesc_list_from(areq, edesc); + } =20 return ret; } @@ -2124,8 +2072,6 @@ static int ahash_init(struct ahash_request *areq) dma_addr_t dma; =20 /* Initialize the context */ - req_ctx->buf_idx =3D 0; - req_ctx->nbuf =3D 0; req_ctx->first_request =3D 1; req_ctx->swinit =3D 0; /* assume h/w init of context */ size =3D (crypto_ahash_digestsize(tfm) <=3D SHA256_DIGEST_SIZE) @@ -2133,6 +2079,7 @@ static int ahash_init(struct ahash_request *areq) : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512; req_ctx->hw_context_size =3D size; req_ctx->last_request =3D 0; + req_ctx->message_size =3D 0; =20 dma =3D dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size, DMA_TO_DEVICE); @@ -2222,12 +2169,11 @@ static int ahash_export(struct ahash_request *areq,= void *out) =20 memcpy(export->hw_context, req_ctx->hw_context, req_ctx->hw_context_size); - memcpy(export->buf, req_ctx->buf[req_ctx->buf_idx], req_ctx->nbuf); export->swinit =3D req_ctx->swinit; export->first_request =3D req_ctx->first_request; export->last_request =3D req_ctx->last_request; export->to_hash_later =3D req_ctx->to_hash_later; - export->nbuf =3D req_ctx->nbuf; + export->message_size =3D req_ctx->message_size; =20 return 0; } @@ -2248,12 +2194,11 @@ static int ahash_import(struct ahash_request *areq,= const void *in) : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512; req_ctx->hw_context_size =3D size; memcpy(req_ctx->hw_context, export->hw_context, size); - memcpy(req_ctx->buf[0], export->buf, export->nbuf); req_ctx->swinit =3D export->swinit; req_ctx->first_request =3D export->first_request; req_ctx->last_request =3D export->last_request; req_ctx->to_hash_later =3D export->to_hash_later; - req_ctx->nbuf =3D export->nbuf; + req_ctx->message_size =3D export->message_size; =20 dma =3D dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size, DMA_TO_DEVICE); @@ -2931,8 +2876,10 @@ static struct talitos_alg_template driver_algs[] =3D= { .cra_name =3D "md5", .cra_driver_name =3D "md5-talitos", .cra_blocksize =3D MD5_HMAC_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, } }, .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | @@ -2947,8 +2894,10 @@ static struct talitos_alg_template driver_algs[] =3D= { .cra_name =3D "sha1", .cra_driver_name =3D "sha1-talitos", .cra_blocksize =3D SHA1_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, } }, .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | @@ -2963,8 +2912,10 @@ static struct talitos_alg_template driver_algs[] =3D= { .cra_name =3D "sha224", .cra_driver_name =3D "sha224-talitos", .cra_blocksize =3D SHA224_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, } }, .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | @@ -2979,8 +2930,10 @@ static struct talitos_alg_template driver_algs[] =3D= { .cra_name =3D "sha256", .cra_driver_name =3D "sha256-talitos", .cra_blocksize =3D SHA256_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, } }, .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | @@ -2995,8 +2948,10 @@ static struct talitos_alg_template driver_algs[] =3D= { .cra_name =3D "sha384", .cra_driver_name =3D "sha384-talitos", .cra_blocksize =3D SHA384_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, } }, .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | @@ -3011,8 +2966,10 @@ static struct talitos_alg_template driver_algs[] =3D= { .cra_name =3D "sha512", .cra_driver_name =3D "sha512-talitos", .cra_blocksize =3D SHA512_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, } }, .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | @@ -3027,8 +2984,10 @@ static struct talitos_alg_template driver_algs[] =3D= { .cra_name =3D "hmac(md5)", .cra_driver_name =3D "hmac-md5-talitos", .cra_blocksize =3D MD5_HMAC_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, } }, .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | @@ -3043,8 +3002,10 @@ static struct talitos_alg_template driver_algs[] =3D= { .cra_name =3D "hmac(sha1)", .cra_driver_name =3D "hmac-sha1-talitos", .cra_blocksize =3D SHA1_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, } }, .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | @@ -3059,8 +3020,10 @@ static struct talitos_alg_template driver_algs[] =3D= { .cra_name =3D "hmac(sha224)", .cra_driver_name =3D "hmac-sha224-talitos", .cra_blocksize =3D SHA224_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, } }, .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | @@ -3075,8 +3038,10 @@ static struct talitos_alg_template driver_algs[] =3D= { .cra_name =3D "hmac(sha256)", .cra_driver_name =3D "hmac-sha256-talitos", .cra_blocksize =3D SHA256_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, } }, .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | @@ -3091,8 +3056,10 @@ static struct talitos_alg_template driver_algs[] =3D= { .cra_name =3D "hmac(sha384)", .cra_driver_name =3D "hmac-sha384-talitos", .cra_blocksize =3D SHA384_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, } }, .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | @@ -3107,8 +3074,10 @@ static struct talitos_alg_template driver_algs[] =3D= { .cra_name =3D "hmac(sha512)", .cra_driver_name =3D "hmac-sha512-talitos", .cra_blocksize =3D SHA512_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, } }, .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | @@ -3180,8 +3149,6 @@ static int talitos_cra_init_ahash(struct crypto_tfm *= tfm) algt.alg.hash); =20 ctx->keylen =3D 0; - crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), - sizeof(struct talitos_ahash_req_ctx)); =20 return talitos_init_common(ctx, talitos_alg); } --=20 2.55.0 From nobody Thu Sep 24 13:42:19 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1291C5452A7 for ; Wed, 23 Sep 2026 15:19:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790176763; cv=none; b=APKyihQQ8O3bKho4q/5PYoOyvmvUcDWN11KJim0be9+1WKdDoXVjAzQBtea5ILb7IYVDv5ZbbkiJ3HmFE+iZFbsA5yIoraS5qgLoVbkT7Bnza8laXnjL2OhT1SAhvIlQfiTlEl81jq3xzZmBzBLQWbp3UfNaDpN9pUiMCQKWHtA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790176763; c=relaxed/simple; bh=V2njShitigGLUuZBEVexmM3QyTjSvcUFwuqSqwbW5vw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=I0LZngzG6IIs5rTsnDfF1097BkE4GYCoL2xaFE2x0gEd7gerV0qWe0k9n2RcxDSXKpAyRT/Gw78OHSOVWQNq4eSWAuLKWRe1oBanAi2KQMwsQSNMti+vqhKxeTK4OXU2fwYJg77lFqwusmOrDOIM6F207P3tu9EFOs5Z1evfG+s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=zrc3/9Gw; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="zrc3/9Gw" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 5DF7B4E41047; Wed, 23 Sep 2026 15:19:19 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 2A4A860580; Wed, 23 Sep 2026 15:19:19 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 64BD5103293D7; Wed, 23 Sep 2026 17:19:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1790176757; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=L3miw9rDYFcpZUL3Fj8+pV42jq0wLlqwfAjnEEVvAO8=; b=zrc3/9GwB8v2uE8NF6RECdyPKzFkpzP7C5bGkz22wongYJ0J6kaa5d36J4QJeYkFNxhZND /Z6vLZs/lNWDIlCKDG+q8Tc4NKBonp2OJUfCiZfjtg5mqhy2CqORL75HcU8oYYcxtyXLFs Or86hfFwMzjjch7Mio0egryxwLGUmkHhQ1rcNhPgm00MC6fWVcKU6pZfzok5P4MPGwE9Le RtKTzAqp/6WLp1Vu6+G3OIHMoaHI0n4Yvyfn5LWgLTDsxV8A1c6ZCxhEDow2uCCll4b/U+ ySMG558hKbeJcY0r2smRuDM46KWljAOlOsR7fdNO29rAxhyF8j2JTwm8eHyLCQ== From: Paul Louvel Date: Wed, 23 Sep 2026 17:18:38 +0200 Subject: [PATCH v7 02/20] crypto: talitos - Move driver into dedicated directory Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-7-3-rc2_talitos_cleanup-v7-2-9a45261fc097@bootlin.com> References: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> In-Reply-To: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> To: Herbert Xu , "David S. Miller" Cc: Paul Louvel , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Christophe Leroy , "Christophe Leroy (CS GROUP)" X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790176746; l=4919; i=paul.louvel@bootlin.com; s=20260313; h=from:subject:message-id; bh=V2njShitigGLUuZBEVexmM3QyTjSvcUFwuqSqwbW5vw=; b=rhLzS9Cef3OP4d3+wmoV+zP6Jwl3wq19nYVy/3L1ZMA/OxUr/EsJBKt1lqMmTpGgg1wNlmtL4 8RiJyHOUz20Bph6aJAHwGcMly92bSugmY/oT1VJFJtJF8SMV6tHzgBM X-Developer-Key: i=paul.louvel@bootlin.com; a=ed25519; pk=eLW50NT18UAvUT5cAcYf88zNbBCZDLFXuptpyLVhVIU= X-Last-TLS-Session-Version: TLSv1.3 Move the talitos driver files from drivers/crypto/ into drivers/crypto/talitos/ to accommodate upcoming code reorganization. Reviewed-by: Christophe Leroy (CS GROUP) Signed-off-by: Paul Louvel --- drivers/crypto/Kconfig | 38 +-----------------= ---- drivers/crypto/Makefile | 2 +- drivers/crypto/talitos/Kconfig | 36 ++++++++++++++++++= ++ drivers/crypto/talitos/Makefile | 3 ++ .../crypto/{talitos.c =3D> talitos/talitos-core.c} | 0 drivers/crypto/{ =3D> talitos}/talitos.h | 0 6 files changed, 41 insertions(+), 38 deletions(-) diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 0189dfdcbbe1..13f09805851c 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -253,43 +253,7 @@ config CRYPTO_DEV_HIFN_795X_RNG on the HIFN 795x crypto adapters. =20 source "drivers/crypto/caam/Kconfig" - -config CRYPTO_DEV_TALITOS - tristate "Talitos Freescale Security Engine (SEC)" - select CRYPTO_AEAD - select CRYPTO_AUTHENC - select CRYPTO_SKCIPHER - select CRYPTO_HASH - select CRYPTO_LIB_DES - select HW_RANDOM - depends on FSL_SOC - help - Say 'Y' here to use the Freescale Security Engine (SEC) - to offload cryptographic algorithm computation. - - The Freescale SEC is present on PowerQUICC 'E' processors, such - as the MPC8349E and MPC8548E. - - To compile this driver as a module, choose M here: the module - will be called talitos. - -config CRYPTO_DEV_TALITOS1 - bool "SEC1 (SEC 1.0 and SEC Lite 1.2)" - depends on CRYPTO_DEV_TALITOS - depends on PPC_8xx || PPC_82xx - default y - help - Say 'Y' here to use the Freescale Security Engine (SEC) version 1.0 - found on MPC82xx or the Freescale Security Engine (SEC Lite) - version 1.2 found on MPC8xx - -config CRYPTO_DEV_TALITOS2 - bool "SEC2+ (SEC version 2.0 or upper)" - depends on CRYPTO_DEV_TALITOS - default y if !PPC_8xx - help - Say 'Y' here to use the Freescale Security Engine (SEC) - version 2 and following as found on MPC83xx, MPC85xx, etc ... +source "drivers/crypto/talitos/Kconfig" =20 config CRYPTO_DEV_PPC4XX tristate "Driver AMCC PPC4xx crypto accelerator" diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index 2c33b83f3cfa..e9522e94c20d 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -33,7 +33,7 @@ obj-$(CONFIG_CRYPTO_DEV_SA2UL) +=3D sa2ul.o obj-$(CONFIG_CRYPTO_DEV_SAHARA) +=3D sahara.o obj-$(CONFIG_CRYPTO_DEV_SL3516) +=3D gemini/ obj-y +=3D stm32/ -obj-$(CONFIG_CRYPTO_DEV_TALITOS) +=3D talitos.o +obj-$(CONFIG_CRYPTO_DEV_TALITOS) +=3D talitos/ obj-$(CONFIG_CRYPTO_DEV_TEGRA) +=3D tegra/ obj-$(CONFIG_CRYPTO_DEV_VIRTIO) +=3D virtio/ obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) +=3D bcm/ diff --git a/drivers/crypto/talitos/Kconfig b/drivers/crypto/talitos/Kconfig new file mode 100644 index 000000000000..c3470553a966 --- /dev/null +++ b/drivers/crypto/talitos/Kconfig @@ -0,0 +1,36 @@ +config CRYPTO_DEV_TALITOS + tristate "Talitos Freescale Security Engine (SEC)" + select CRYPTO_AEAD + select CRYPTO_AUTHENC + select CRYPTO_SKCIPHER + select CRYPTO_HASH + select CRYPTO_LIB_DES + select HW_RANDOM + depends on FSL_SOC + help + Say 'Y' here to use the Freescale Security Engine (SEC) + to offload cryptographic algorithm computation. + + The Freescale SEC is present on PowerQUICC 'E' processors, such + as the MPC8349E and MPC8548E. + + To compile this driver as a module, choose M here: the module + will be called talitos. + +config CRYPTO_DEV_TALITOS1 + bool "SEC1 (SEC 1.0 and SEC Lite 1.2)" + depends on CRYPTO_DEV_TALITOS + depends on PPC_8xx || PPC_82xx + default y + help + Say 'Y' here to use the Freescale Security Engine (SEC) version 1.0 + found on MPC82xx or the Freescale Security Engine (SEC Lite) + version 1.2 found on MPC8xx + +config CRYPTO_DEV_TALITOS2 + bool "SEC2+ (SEC version 2.0 or upper)" + depends on CRYPTO_DEV_TALITOS + default y if !PPC_8xx + help + Say 'Y' here to use the Freescale Security Engine (SEC) + version 2 and following as found on MPC83xx, MPC85xx, etc ... diff --git a/drivers/crypto/talitos/Makefile b/drivers/crypto/talitos/Makef= ile new file mode 100644 index 000000000000..98456167fe73 --- /dev/null +++ b/drivers/crypto/talitos/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_CRYPTO_DEV_TALITOS) +=3D talitos.o + +talitos-y +=3D talitos-core.o diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos/talitos-core= .c similarity index 100% rename from drivers/crypto/talitos.c rename to drivers/crypto/talitos/talitos-core.c diff --git a/drivers/crypto/talitos.h b/drivers/crypto/talitos/talitos.h similarity index 100% rename from drivers/crypto/talitos.h rename to drivers/crypto/talitos/talitos.h --=20 2.55.0 From nobody Thu Sep 24 13:42:19 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC9E55437C0 for ; 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bh=Ohbu6+DJKRUK4B2j2zUWdHaU347gQh155kgQ+RKBPHA=; b=wUnZxlP4uJo0ikEK8NhMiSA3Azt9kybQT7RLmyKOlqbk9gUNtSdBow+CApB/No+ZA95gYV 8vs5WGB++R2ti2gwUsMQEiCzUzixS1+i69Cbhy2+kTC03TWr70xSbHldLf6+uwAEE3yi9i 0iu7sbSVQiRgPY0zRJ9j8iqQr+P3tBwcB5VcEq/V/sbVyy7+v+Kw75Fhvxv7q77WmKP75f 3I6v1Mt/E+IQlpJ/shD6f/5l9pPGQFzDS6msyUKDBuL1Vxy+ySv+j6fi0zuXn/BC/T7BOW dH6+inaMnQgmPVrvVNb4GAb1aL50dzuZmkfAsEF/2U8uagbaKkco6FB2wyGidw== From: Paul Louvel Date: Wed, 23 Sep 2026 17:18:39 +0200 Subject: [PATCH v7 03/20] crypto: talitos - Add missing includes to driver header file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-7-3-rc2_talitos_cleanup-v7-3-9a45261fc097@bootlin.com> References: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> In-Reply-To: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> To: Herbert Xu , "David S. Miller" Cc: Paul Louvel , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Christophe Leroy , "Christophe Leroy (CS GROUP)" X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790176746; l=895; i=paul.louvel@bootlin.com; s=20260313; h=from:subject:message-id; bh=g7nzFkqbUuQylgPSSwpsCxIR9V3zNvMz072ZBgxP4hA=; b=yCfEJ96UZPUIGpUnabBiLRpMdKds3hgF15I8OgZkY1ubGyp2MXs37O/fahqwI9SEVvOV/dz1V tFfUdE/IRElD6yD+gs8OFtEw7oSgplOz0LcFvuRvSFwrljC01UUGQrz X-Developer-Key: i=paul.louvel@bootlin.com; a=ed25519; pk=eLW50NT18UAvUT5cAcYf88zNbBCZDLFXuptpyLVhVIU= X-Last-TLS-Session-Version: TLSv1.3 Add explicit includes for types used by the header file to make it self-contained and fix implicit include dependencies. Reviewed-by: Christophe Leroy (CS GROUP) Signed-off-by: Paul Louvel --- drivers/crypto/talitos/talitos.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/tali= tos.h index d4ff8d589f46..56e36a65ddcc 100644 --- a/drivers/crypto/talitos/talitos.h +++ b/drivers/crypto/talitos/talitos.h @@ -5,6 +5,12 @@ * Copyright (c) 2006-2011 Freescale Semiconductor, Inc. */ =20 +#include +#include +#include +#include +#include + #define TALITOS_TIMEOUT 100000 #define TALITOS1_MAX_DATA_LEN 32768 #define TALITOS2_MAX_DATA_LEN 65535 --=20 2.55.0 From nobody Thu Sep 24 13:42:19 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC1C0549376 for ; Wed, 23 Sep 2026 15:19:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790176765; cv=none; b=tlER0G8glP8TZIvqiX21/CQbbVuuExvtxzsbigrzRBFBm7IwEFoSq7EBQSLE8fx+9HdwoPb2zRhTCTatft8ldUSqlKoc0Cewt2uB5A238A/QtO9RgiCVpKCgvIrrYU5KPRsufPZ1Ead5gBLLBXiMmlMJ82+9dSPNczBT/nYBdAA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790176765; c=relaxed/simple; bh=u68fzDZ4Kzc8czfIN8juXm5b5s1oMV3zUUzURxZSUVM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gv6HnFe5FIcupaygDGLeZNAoh+U3u/K9AXkPb/xryPBCaTcSHwIvBvJkjJBw1ug4E8O8FEoWWauX5DjT9xyvw2v8R7R3KW5AV8dGR66BdYZbcpdledor+BeeuZmddOFHIS+PkdNwzkAx2zcgOTztdrRrGSI/2i1S9PZC0LJr/z4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=scmio8LF; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="scmio8LF" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 801221A0FE6; Wed, 23 Sep 2026 15:19:22 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 5442860580; Wed, 23 Sep 2026 15:19:22 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 861E7103292D1; Wed, 23 Sep 2026 17:19:20 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1790176761; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=90C61lT8CoK4yXoNiRA0d53exQL9dFzlgURXCa8Sd1A=; b=scmio8LFyRcn8o6Taru6q622dA8LzZVARIQjI+LqubVWI4x09ZTjlMmsGU3JlA2SUTrmh2 f2CK0pHD6J4s40xer9mHVBGgkFz3DGTVqu3oYNGWpEa+o529U64rqKbvoptPEAdqb3Gw5c KYVB7dbysyD1U6LZT1ibbWYegWQu9FOwtEMMblRKc2R5vMZbQmYo715B4Cmyxm4sK8UHtJ rkHHdXsh5gDhaDLprK3cDkqymOwGb4sOO8PqOpuC7936vjUMfM3mCC7coqo4RqrbPFxvWL mI1hNJc+DT0qGdQ1F+/vtYk8TvXyqOK6++wRFimuvHR5fIIDIGmhPezMYgtdTQ== From: Paul Louvel Date: Wed, 23 Sep 2026 17:18:40 +0200 Subject: [PATCH v7 04/20] crypto: talitos/hwrng - Move into separate file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-7-3-rc2_talitos_cleanup-v7-4-9a45261fc097@bootlin.com> References: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> In-Reply-To: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> To: Herbert Xu , "David S. Miller" Cc: Paul Louvel , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Christophe Leroy X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790176746; l=6481; i=paul.louvel@bootlin.com; s=20260313; h=from:subject:message-id; bh=u68fzDZ4Kzc8czfIN8juXm5b5s1oMV3zUUzURxZSUVM=; b=pXaAVEwCnI+FaNf7P9EyYGGJnIbG7eiioAMnmJNnKLrTXbANEaQ4hA3NAbCbJVPWqrWMO30H/ D/2T9Hpwo6DCH9rRZHW5SPC1WLyCajWJe7/HrQ/ItDSLteqPiQRHynq X-Developer-Key: i=paul.louvel@bootlin.com; a=ed25519; pk=eLW50NT18UAvUT5cAcYf88zNbBCZDLFXuptpyLVhVIU= X-Last-TLS-Session-Version: TLSv1.3 Move the hardware random number generator implementation from talitos.c into a dedicated talitos-rng.c file. Signed-off-by: Paul Louvel --- drivers/crypto/talitos/Makefile | 2 +- drivers/crypto/talitos/talitos-core.c | 83 ------------------------------- drivers/crypto/talitos/talitos-rng.c | 93 +++++++++++++++++++++++++++++++= ++++ drivers/crypto/talitos/talitos.h | 5 ++ 4 files changed, 99 insertions(+), 84 deletions(-) diff --git a/drivers/crypto/talitos/Makefile b/drivers/crypto/talitos/Makef= ile index 98456167fe73..8873a70045cc 100644 --- a/drivers/crypto/talitos/Makefile +++ b/drivers/crypto/talitos/Makefile @@ -1,3 +1,3 @@ obj-$(CONFIG_CRYPTO_DEV_TALITOS) +=3D talitos.o =20 -talitos-y +=3D talitos-core.o +talitos-y +=3D talitos-core.o talitos-rng.o diff --git a/drivers/crypto/talitos/talitos-core.c b/drivers/crypto/talitos= /talitos-core.c index 55ec5a46b71c..5e2dd4b7390f 100644 --- a/drivers/crypto/talitos/talitos-core.c +++ b/drivers/crypto/talitos/talitos-core.c @@ -822,89 +822,6 @@ DEF_TALITOS2_INTERRUPT(ch0_2, TALITOS2_ISR_CH_0_2_DONE= , TALITOS2_ISR_CH_0_2_ERR, DEF_TALITOS2_INTERRUPT(ch1_3, TALITOS2_ISR_CH_1_3_DONE, TALITOS2_ISR_CH_1_= 3_ERR, 1) =20 -/* - * hwrng - */ -static int talitos_rng_data_present(struct hwrng *rng, int wait) -{ - struct device *dev =3D (struct device *)rng->priv; - struct talitos_private *priv =3D dev_get_drvdata(dev); - u32 ofl; - int i; - - for (i =3D 0; i < 20; i++) { - ofl =3D in_be32(priv->reg_rngu + TALITOS_EUSR_LO) & - TALITOS_RNGUSR_LO_OFL; - if (ofl || !wait) - break; - udelay(10); - } - - return !!ofl; -} - -static int talitos_rng_data_read(struct hwrng *rng, u32 *data) -{ - struct device *dev =3D (struct device *)rng->priv; - struct talitos_private *priv =3D dev_get_drvdata(dev); - - /* rng fifo requires 64-bit accesses */ - *data =3D in_be32(priv->reg_rngu + TALITOS_EU_FIFO); - *data =3D in_be32(priv->reg_rngu + TALITOS_EU_FIFO_LO); - - return sizeof(u32); -} - -static int talitos_rng_init(struct hwrng *rng) -{ - struct device *dev =3D (struct device *)rng->priv; - struct talitos_private *priv =3D dev_get_drvdata(dev); - unsigned int timeout =3D TALITOS_TIMEOUT; - - setbits32(priv->reg_rngu + TALITOS_EURCR_LO, TALITOS_RNGURCR_LO_SR); - while (!(in_be32(priv->reg_rngu + TALITOS_EUSR_LO) - & TALITOS_RNGUSR_LO_RD) - && --timeout) - cpu_relax(); - if (timeout =3D=3D 0) { - dev_err(dev, "failed to reset rng hw\n"); - return -ENODEV; - } - - /* start generating */ - setbits32(priv->reg_rngu + TALITOS_EUDSR_LO, 0); - - return 0; -} - -static int talitos_register_rng(struct device *dev) -{ - struct talitos_private *priv =3D dev_get_drvdata(dev); - int err; - - priv->rng.name =3D dev_driver_string(dev); - priv->rng.init =3D talitos_rng_init; - priv->rng.data_present =3D talitos_rng_data_present; - priv->rng.data_read =3D talitos_rng_data_read; - priv->rng.priv =3D (unsigned long)dev; - - err =3D hwrng_register(&priv->rng); - if (!err) - priv->rng_registered =3D true; - - return err; -} - -static void talitos_unregister_rng(struct device *dev) -{ - struct talitos_private *priv =3D dev_get_drvdata(dev); - - if (!priv->rng_registered) - return; - - hwrng_unregister(&priv->rng); - priv->rng_registered =3D false; -} =20 /* * crypto alg diff --git a/drivers/crypto/talitos/talitos-rng.c b/drivers/crypto/talitos/= talitos-rng.c new file mode 100644 index 000000000000..3aa00de33b25 --- /dev/null +++ b/drivers/crypto/talitos/talitos-rng.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/* + * Freescale SEC (talitos) device hardware random number generator impleme= ntation + * + * Copyright (c) 2006-2011 Freescale Semiconductor, Inc. + */ + +#include +#include + +#include "talitos.h" + +static int talitos_rng_data_present(struct hwrng *rng, int wait) +{ + struct device *dev =3D (struct device *)rng->priv; + struct talitos_private *priv =3D dev_get_drvdata(dev); + u32 ofl; + int i; + + for (i =3D 0; i < 20; i++) { + ofl =3D in_be32(priv->reg_rngu + TALITOS_EUSR_LO) & + TALITOS_RNGUSR_LO_OFL; + if (ofl || !wait) + break; + udelay(10); + } + + return !!ofl; +} + +static int talitos_rng_data_read(struct hwrng *rng, u32 *data) +{ + struct device *dev =3D (struct device *)rng->priv; + struct talitos_private *priv =3D dev_get_drvdata(dev); + + /* rng fifo requires 64-bit accesses */ + *data =3D in_be32(priv->reg_rngu + TALITOS_EU_FIFO); + *data =3D in_be32(priv->reg_rngu + TALITOS_EU_FIFO_LO); + + return sizeof(u32); +} + +static int talitos_rng_init(struct hwrng *rng) +{ + struct device *dev =3D (struct device *)rng->priv; + struct talitos_private *priv =3D dev_get_drvdata(dev); + unsigned int timeout =3D TALITOS_TIMEOUT; + + setbits32(priv->reg_rngu + TALITOS_EURCR_LO, TALITOS_RNGURCR_LO_SR); + while (!(in_be32(priv->reg_rngu + TALITOS_EUSR_LO) + & TALITOS_RNGUSR_LO_RD) + && --timeout) + cpu_relax(); + if (timeout =3D=3D 0) { + dev_err(dev, "failed to reset rng hw\n"); + return -ENODEV; + } + + /* start generating */ + setbits32(priv->reg_rngu + TALITOS_EUDSR_LO, 0); + + return 0; +} + +int talitos_register_rng(struct device *dev) +{ + struct talitos_private *priv =3D dev_get_drvdata(dev); + int err; + + priv->rng.name =3D dev_driver_string(dev); + priv->rng.init =3D talitos_rng_init; + priv->rng.data_present =3D talitos_rng_data_present; + priv->rng.data_read =3D talitos_rng_data_read; + priv->rng.priv =3D (unsigned long)dev; + + err =3D hwrng_register(&priv->rng); + if (!err) + priv->rng_registered =3D true; + + return err; +} + +void talitos_unregister_rng(struct device *dev) +{ + struct talitos_private *priv =3D dev_get_drvdata(dev); + + if (!priv->rng_registered) + return; + + hwrng_unregister(&priv->rng); + priv->rng_registered =3D false; +} diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/tali= tos.h index 56e36a65ddcc..fa8c71b1f90f 100644 --- a/drivers/crypto/talitos/talitos.h +++ b/drivers/crypto/talitos/talitos.h @@ -431,3 +431,8 @@ static inline bool has_ftr_sec1(struct talitos_private = *priv) #define DESC_PTR_LNKTBL_JUMP 0x80 #define DESC_PTR_LNKTBL_RET 0x02 #define DESC_PTR_LNKTBL_NEXT 0x01 + +/* Hardware RNG */ + +int talitos_register_rng(struct device *dev); +void talitos_unregister_rng(struct device *dev); --=20 2.55.0 From nobody Thu Sep 24 13:42:19 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32A8C568542; Wed, 23 Sep 2026 15:19:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790176768; cv=none; b=oE02DmW2Sts5xS4ElXpT66UvW5Ok8T11v3LiVIXDOlbScSvqYip2Q6xNf+qARABUzCF0ZY34YL22pA6lIbY+C9s89ujJfmomkdqdx6pTuUrsaleEDXYrqo5icC8MzO1CtOYL9KpcTnx9MUYg1ac18YirkQUNWR4eYqNPf/iddQA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790176768; c=relaxed/simple; bh=uL+TWIlDnA4npzDhkekKYwA8Ugwtlb+GFUmoOw4TToE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Fi0qsx8OVCeCtj61q/KficY+RfEn2Z0rxM+jMy9IZZDHXq3F47aj5o7ZV0QyFi8yrYb3SKB1cQfW3z48gMeUzFHM+A15rZ1Tqb4SOFRxeoIPuXprC49D5VRVAOvK/yjZQox1k/A9AHD6eKHpMOQtCcDTfjXq7t89IBZaQ0h3OnI= ARC-Authentication-Results: i=1; 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Wed, 23 Sep 2026 17:19:22 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1790176763; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=AzScz52nVS/EpBBUPdPpzVZKTfPSusXq7DmIFEkFX/A=; b=Xdvzb192VfZZeiJTcE8btQITKN2an12PJvE4KiwbdlZTfieYgX/i0puAGDXilpkzQVxpZf Ii2L6TvwsUMER/SF/G4WA/Kuu//2FBlR6j5zB0Vkf9Xyf/r1NlY8Xr+F+qrzTcOD+d5Taw zTP/Oz5wqSKkGgpecEqg4XmMTacFSYvwepWwzwFvCZiv9j5AH8sBISxQwa9+hHZ55fEDEz iIPRxMuFcGOamRa70tEM9G24nY6BBW6k0U0ugExvcYg+kKGlwkaRx23TTzFnJiRKCYWF06 Kuk/ys54UkvruavJno7wwp7UorRkw28xCvhYLcweTBbxnePsn5GRGJ62tds6Uw== From: Paul Louvel Date: Wed, 23 Sep 2026 17:18:41 +0200 Subject: [PATCH v7 05/20] crypto: talitos - Prepare crypto implementation file splitting Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-7-3-rc2_talitos_cleanup-v7-5-9a45261fc097@bootlin.com> References: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> In-Reply-To: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> To: Herbert Xu , "David S. Miller" Cc: Paul Louvel , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Christophe Leroy X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790176746; l=16022; i=paul.louvel@bootlin.com; s=20260313; h=from:subject:message-id; bh=uL+TWIlDnA4npzDhkekKYwA8Ugwtlb+GFUmoOw4TToE=; b=rZPG+Zhe6f4lfiZmbaV9OHnEhX/q55R1k6YSfCuopFrrjKVqd6zvsiBeTGKc5vcH6PY9/HvKv b5QQSOg6w4JBG/i5/LigjvNRGysg6eClQvGkpdmmF94xeG2frxSMyn+ X-Developer-Key: i=paul.louvel@bootlin.com; a=ed25519; pk=eLW50NT18UAvUT5cAcYf88zNbBCZDLFXuptpyLVhVIU= X-Last-TLS-Session-Version: TLSv1.3 Move all talitos helpers and inline them inside the header file. Remove the static qualifier for the core functions of the driver, they will be called inside each crypto implementation file. Add the common structures too. Signed-off-by: Paul Louvel --- drivers/crypto/talitos/talitos-core.c | 182 +++++-------------------------= ---- drivers/crypto/talitos/talitos.h | 167 +++++++++++++++++++++++++++++++ 2 files changed, 194 insertions(+), 155 deletions(-) diff --git a/drivers/crypto/talitos/talitos-core.c b/drivers/crypto/talitos= /talitos-core.c index 5e2dd4b7390f..aa0a15f3c9da 100644 --- a/drivers/crypto/talitos/talitos-core.c +++ b/drivers/crypto/talitos/talitos-core.c @@ -42,99 +42,6 @@ =20 #include "talitos.h" =20 -static void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr, - unsigned int len, bool is_sec1) -{ - ptr->ptr =3D cpu_to_be32(lower_32_bits(dma_addr)); - if (is_sec1) { - ptr->len1 =3D cpu_to_be16(len); - } else { - ptr->len =3D cpu_to_be16(len); - ptr->eptr =3D upper_32_bits(dma_addr); - } -} - -static void copy_talitos_ptr(struct talitos_ptr *dst_ptr, - struct talitos_ptr *src_ptr, bool is_sec1) -{ - dst_ptr->ptr =3D src_ptr->ptr; - if (is_sec1) { - dst_ptr->len1 =3D src_ptr->len1; - } else { - dst_ptr->len =3D src_ptr->len; - dst_ptr->eptr =3D src_ptr->eptr; - } -} - -static unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr, - bool is_sec1) -{ - if (is_sec1) - return be16_to_cpu(ptr->len1); - else - return be16_to_cpu(ptr->len); -} - -static void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val, - bool is_sec1) -{ - if (!is_sec1) - ptr->j_extent =3D val; -} - -static void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val, bool is= _sec1) -{ - if (!is_sec1) - ptr->j_extent |=3D val; -} - -/* - * map virtual single (contiguous) pointer to h/w descriptor pointer - */ -static void __map_single_talitos_ptr(struct device *dev, - struct talitos_ptr *ptr, - unsigned int len, void *data, - enum dma_data_direction dir, - unsigned long attrs) -{ - dma_addr_t dma_addr =3D dma_map_single_attrs(dev, data, len, dir, attrs); - struct talitos_private *priv =3D dev_get_drvdata(dev); - bool is_sec1 =3D has_ftr_sec1(priv); - - to_talitos_ptr(ptr, dma_addr, len, is_sec1); -} - -static void map_single_talitos_ptr(struct device *dev, - struct talitos_ptr *ptr, - unsigned int len, void *data, - enum dma_data_direction dir) -{ - __map_single_talitos_ptr(dev, ptr, len, data, dir, 0); -} - -static void map_single_talitos_ptr_nosync(struct device *dev, - struct talitos_ptr *ptr, - unsigned int len, void *data, - enum dma_data_direction dir) -{ - __map_single_talitos_ptr(dev, ptr, len, data, dir, - DMA_ATTR_SKIP_CPU_SYNC); -} - -/* - * unmap bus single (contiguous) h/w descriptor pointer - */ -static void unmap_single_talitos_ptr(struct device *dev, - struct talitos_ptr *ptr, - enum dma_data_direction dir) -{ - struct talitos_private *priv =3D dev_get_drvdata(dev); - bool is_sec1 =3D has_ftr_sec1(priv); - - dma_unmap_single(dev, be32_to_cpu(ptr->ptr), - from_talitos_ptr_len(ptr, is_sec1), dir); -} - static int reset_channel(struct device *dev, int ch) { struct talitos_private *priv =3D dev_get_drvdata(dev); @@ -305,11 +212,11 @@ static void dma_map_request(struct device *dev, struc= t talitos_request *request, * callback must check err and feedback in descriptor header * for device processing status. */ -static int talitos_submit(struct device *dev, int ch, struct talitos_desc = *desc, - void (*callback)(struct device *dev, - struct talitos_desc *desc, - void *context, int error), - void *context) +int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc, + void (*callback)(struct device *dev, + struct talitos_desc *desc, + void *context, int error), + void *context) { struct talitos_private *priv =3D dev_get_drvdata(dev); struct talitos_request *request; @@ -832,24 +739,6 @@ DEF_TALITOS2_INTERRUPT(ch1_3, TALITOS2_ISR_CH_1_3_DONE= , TALITOS2_ISR_CH_1_3_ERR, * HMAC_SNOOP_NO_AFEA (HSNA) instead of type IPSEC_ESP */ #define TALITOS_CRA_PRIORITY_AEAD_HSNA (TALITOS_CRA_PRIORITY - 1) -#ifdef CONFIG_CRYPTO_DEV_TALITOS2 -#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA512_BLOCK_SIZE) -#else -#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA256_BLOCK_SIZE) -#endif -#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK= _SIZE */ - -struct talitos_ctx { - struct device *dev; - int ch; - __be32 desc_hdr_template; - u8 key[TALITOS_MAX_KEY_SIZE]; - u8 iv[TALITOS_MAX_IV_LENGTH]; - dma_addr_t dma_key; - unsigned int keylen; - unsigned int enckeylen; - unsigned int authkeylen; -}; =20 #define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA= 512 =20 @@ -943,7 +832,7 @@ static int aead_des3_setkey(struct crypto_aead *authenc, return err; } =20 -static void talitos_sg_unmap(struct device *dev, +void talitos_sg_unmap(struct device *dev, struct talitos_edesc *edesc, struct scatterlist *src, struct scatterlist *dst, @@ -1128,7 +1017,7 @@ static int sg_to_link_tbl_offset(struct scatterlist *= sg, int sg_count, return count; } =20 -static int talitos_sg_map_ext(struct device *dev, struct scatterlist *src, +int talitos_sg_map_ext(struct device *dev, struct scatterlist *src, unsigned int len, struct talitos_edesc *edesc, struct talitos_ptr *ptr, int sg_count, unsigned int offset, int tbl_off, int elen, @@ -1165,7 +1054,7 @@ static int talitos_sg_map_ext(struct device *dev, str= uct scatterlist *src, return sg_count; } =20 -static int talitos_sg_map(struct device *dev, struct scatterlist *src, +int talitos_sg_map(struct device *dev, struct scatterlist *src, unsigned int len, struct talitos_edesc *edesc, struct talitos_ptr *ptr, int sg_count, unsigned int offset, int tbl_off) @@ -1303,17 +1192,17 @@ static int ipsec_esp(struct talitos_edesc *edesc, s= truct aead_request *areq, /* * allocate and map the extended descriptor */ -static struct talitos_edesc *talitos_edesc_alloc(struct device *dev, - struct scatterlist *src, - struct scatterlist *dst, - u8 *iv, - unsigned int assoclen, - unsigned int cryptlen, - unsigned int authsize, - unsigned int ivsize, - int icv_stashing, - u32 cryptoflags, - bool encrypt) +struct talitos_edesc *talitos_edesc_alloc(struct device *dev, + struct scatterlist *src, + struct scatterlist *dst, + u8 *iv, + unsigned int assoclen, + unsigned int cryptlen, + unsigned int authsize, + unsigned int ivsize, + int icv_stashing, + u32 cryptoflags, + bool encrypt) { struct talitos_edesc *edesc; int src_nents, dst_nents, alloc_len, dma_len, src_len, dst_len; @@ -2189,18 +2078,6 @@ static int ahash_setkey(struct crypto_ahash *tfm, co= nst u8 *key, return 0; } =20 - -struct talitos_alg_template { - u32 type; - u32 priority; - union { - struct skcipher_alg skcipher; - struct ahash_alg hash; - struct aead_alg aead; - } alg; - __be32 desc_hdr_template; -}; - static struct talitos_alg_template driver_algs[] =3D { /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */ { .type =3D CRYPTO_ALG_TYPE_AEAD, @@ -3003,14 +2880,8 @@ static struct talitos_alg_template driver_algs[] =3D= { } }; =20 -struct talitos_crypto_alg { - struct list_head entry; - struct device *dev; - struct talitos_alg_template algt; -}; - -static int talitos_init_common(struct talitos_ctx *ctx, - struct talitos_crypto_alg *talitos_alg) +int talitos_init_common(struct talitos_ctx *ctx, + struct talitos_crypto_alg *talitos_alg) { struct talitos_private *priv; =20 @@ -3070,7 +2941,7 @@ static int talitos_cra_init_ahash(struct crypto_tfm *= tfm) return talitos_init_common(ctx, talitos_alg); } =20 -static void talitos_cra_exit(struct crypto_tfm *tfm) +void talitos_cra_exit(struct crypto_tfm *tfm) { struct talitos_ctx *ctx =3D crypto_tfm_ctx(tfm); struct device *dev =3D ctx->dev; @@ -3084,7 +2955,7 @@ static void talitos_cra_exit(struct crypto_tfm *tfm) * type and primary/secondary execution units required match the hw * capabilities description provided in the device tree node. */ -static int hw_supports(struct device *dev, __be32 desc_hdr_template) +int talitos_hw_supports(struct device *dev, __be32 desc_hdr_template) { struct talitos_private *priv =3D dev_get_drvdata(dev); int ret; @@ -3121,7 +2992,7 @@ static void talitos_remove(struct platform_device *of= dev) list_del(&t_alg->entry); } =20 - if (hw_supports(dev, DESC_HDR_SEL0_RNG)) + if (talitos_hw_supports(dev, DESC_HDR_SEL0_RNG)) talitos_unregister_rng(dev); =20 for (i =3D 0; i < 2; i++) @@ -3426,7 +3297,7 @@ static int talitos_probe(struct platform_device *ofde= v) } =20 /* register the RNG, if available */ - if (hw_supports(dev, DESC_HDR_SEL0_RNG)) { + if (talitos_hw_supports(dev, DESC_HDR_SEL0_RNG)) { err =3D talitos_register_rng(dev); if (err) { dev_err(dev, "failed to register hwrng: %d\n", err); @@ -3437,7 +3308,8 @@ static int talitos_probe(struct platform_device *ofde= v) =20 /* register crypto algorithms the device supports */ for (i =3D 0; i < ARRAY_SIZE(driver_algs); i++) { - if (hw_supports(dev, driver_algs[i].desc_hdr_template)) { + if (talitos_hw_supports(dev, + driver_algs[i].desc_hdr_template)) { struct talitos_crypto_alg *t_alg; struct crypto_alg *alg =3D NULL; =20 diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/tali= tos.h index fa8c71b1f90f..24b4d541df2c 100644 --- a/drivers/crypto/talitos/talitos.h +++ b/drivers/crypto/talitos/talitos.h @@ -5,7 +5,13 @@ * Copyright (c) 2006-2011 Freescale Semiconductor, Inc. */ =20 +#include +#include +#include +#include +#include #include +#include #include #include #include @@ -19,6 +25,13 @@ #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf) #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf) =20 +#ifdef CONFIG_CRYPTO_DEV_TALITOS2 +#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA512_BLOCK_SIZE) +#else +#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA256_BLOCK_SIZE) +#endif +#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK= _SIZE */ + /* descriptor pointer entry */ struct talitos_ptr { union { @@ -174,6 +187,35 @@ struct talitos_private { =20 }; =20 +struct talitos_ctx { + struct device *dev; + int ch; + __be32 desc_hdr_template; + u8 key[TALITOS_MAX_KEY_SIZE]; + u8 iv[TALITOS_MAX_IV_LENGTH]; + dma_addr_t dma_key; + unsigned int keylen; + unsigned int enckeylen; + unsigned int authkeylen; +}; + +struct talitos_alg_template { + u32 type; + u32 priority; + union { + struct skcipher_alg skcipher; + struct ahash_alg hash; + struct aead_alg aead; + } alg; + __be32 desc_hdr_template; +}; + +struct talitos_crypto_alg { + struct list_head entry; + struct device *dev; + struct talitos_alg_template algt; +}; + /* .features flag */ #define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001 #define TALITOS_FTR_HW_AUTH_CHECK 0x00000002 @@ -432,6 +474,131 @@ static inline bool has_ftr_sec1(struct talitos_privat= e *priv) #define DESC_PTR_LNKTBL_RET 0x02 #define DESC_PTR_LNKTBL_NEXT 0x01 =20 +static inline void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_= addr, + unsigned int len, bool is_sec1) +{ + ptr->ptr =3D cpu_to_be32(lower_32_bits(dma_addr)); + if (is_sec1) { + ptr->len1 =3D cpu_to_be16(len); + } else { + ptr->len =3D cpu_to_be16(len); + ptr->eptr =3D upper_32_bits(dma_addr); + } +} + +static inline void copy_talitos_ptr(struct talitos_ptr *dst_ptr, + struct talitos_ptr *src_ptr, bool is_sec1) +{ + dst_ptr->ptr =3D src_ptr->ptr; + if (is_sec1) { + dst_ptr->len1 =3D src_ptr->len1; + } else { + dst_ptr->len =3D src_ptr->len; + dst_ptr->eptr =3D src_ptr->eptr; + } +} + +static inline unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr, + bool is_sec1) +{ + if (is_sec1) + return be16_to_cpu(ptr->len1); + else + return be16_to_cpu(ptr->len); +} + +static inline void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val, + bool is_sec1) +{ + if (!is_sec1) + ptr->j_extent =3D val; +} + +static inline void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val, + bool is_sec1) +{ + if (!is_sec1) + ptr->j_extent |=3D val; +} + +/* + * map virtual single (contiguous) pointer to h/w descriptor pointer + */ +static inline void __map_single_talitos_ptr(struct device *dev, + struct talitos_ptr *ptr, unsigned int len, + void *data, enum dma_data_direction dir, + unsigned long attrs) +{ + dma_addr_t dma_addr =3D dma_map_single_attrs(dev, data, len, dir, attrs); + struct talitos_private *priv =3D dev_get_drvdata(dev); + bool is_sec1 =3D has_ftr_sec1(priv); + + to_talitos_ptr(ptr, dma_addr, len, is_sec1); +} + +static inline void map_single_talitos_ptr(struct device *dev, + struct talitos_ptr *ptr, + unsigned int len, void *data, + enum dma_data_direction dir) +{ + __map_single_talitos_ptr(dev, ptr, len, data, dir, 0); +} + +static inline void map_single_talitos_ptr_nosync(struct device *dev, + struct talitos_ptr *ptr, + unsigned int len, void *data, + enum dma_data_direction dir) +{ + __map_single_talitos_ptr(dev, ptr, len, data, dir, + DMA_ATTR_SKIP_CPU_SYNC); +} + +/* + * unmap bus single (contiguous) h/w descriptor pointer + */ +static inline void unmap_single_talitos_ptr(struct device *dev, + struct talitos_ptr *ptr, + enum dma_data_direction dir) +{ + struct talitos_private *priv =3D dev_get_drvdata(dev); + bool is_sec1 =3D has_ftr_sec1(priv); + + dma_unmap_single(dev, be32_to_cpu(ptr->ptr), + from_talitos_ptr_len(ptr, is_sec1), dir); +} + +int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc, + void (*callback)(struct device *dev, + struct talitos_desc *desc, void *context, + int error), + void *context); + +void talitos_sg_unmap(struct device *dev, struct talitos_edesc *edesc, + struct scatterlist *src, struct scatterlist *dst, + unsigned int len, unsigned int offset); +int talitos_sg_map_ext(struct device *dev, struct scatterlist *src, + unsigned int len, struct talitos_edesc *edesc, + struct talitos_ptr *ptr, int sg_count, + unsigned int offset, int tbl_off, int elen, bool force, + int align); +int talitos_sg_map(struct device *dev, struct scatterlist *src, + unsigned int len, struct talitos_edesc *edesc, + struct talitos_ptr *ptr, int sg_count, unsigned int offset, + int tbl_off); + +struct talitos_edesc * +talitos_edesc_alloc(struct device *dev, struct scatterlist *src, + struct scatterlist *dst, u8 *iv, unsigned int assoclen, + unsigned int cryptlen, unsigned int authsize, + unsigned int ivsize, int icv_stashing, u32 cryptoflags, + bool encrypt); + +int talitos_hw_supports(struct device *dev, __be32 desc_hdr_template); + +int talitos_init_common(struct talitos_ctx *ctx, + struct talitos_crypto_alg *talitos_alg); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-7-3-rc2_talitos_cleanup-v7-6-9a45261fc097@bootlin.com> References: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> In-Reply-To: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> To: Herbert Xu , "David S. Miller" Cc: Paul Louvel , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Christophe Leroy , "Christophe Leroy (CS GROUP)" X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790176746; l=57996; i=paul.louvel@bootlin.com; s=20260313; h=from:subject:message-id; bh=vo3c6aGYCIrcgdU0TS0pvAAU7y7w6f0Kk5CV4Hd95uA=; b=wn/46HS/yvlJp0i6VSnZcuaiBQmbUpQafiUThu7cKf0ROYtAr21/QyfCAsCFz31usXjxM0rql CQBahdfnWcHCMk1CpZtYfupTZpFWzMw5mY2bT5whRXnBq1aPHa6oJ7s X-Developer-Key: i=paul.louvel@bootlin.com; a=ed25519; pk=eLW50NT18UAvUT5cAcYf88zNbBCZDLFXuptpyLVhVIU= X-Last-TLS-Session-Version: TLSv1.3 Move the ahash algorithm implementations from talitos.c into a dedicated talitos-hash.c file. Add a helper that will be called in each crypto implementation file for registration. Reviewed-by: Christophe Leroy (CS GROUP) Signed-off-by: Paul Louvel --- drivers/crypto/talitos/Makefile | 2 +- drivers/crypto/talitos/talitos-core.c | 861 +++---------------------------= ---- drivers/crypto/talitos/talitos-hash.c | 835 ++++++++++++++++++++++++++++++= +++ drivers/crypto/talitos/talitos.h | 7 + 4 files changed, 905 insertions(+), 800 deletions(-) diff --git a/drivers/crypto/talitos/Makefile b/drivers/crypto/talitos/Makef= ile index 8873a70045cc..2a0e93614f2b 100644 --- a/drivers/crypto/talitos/Makefile +++ b/drivers/crypto/talitos/Makefile @@ -1,3 +1,3 @@ obj-$(CONFIG_CRYPTO_DEV_TALITOS) +=3D talitos.o =20 -talitos-y +=3D talitos-core.o talitos-rng.o +talitos-y +=3D talitos-core.o talitos-rng.o talitos-hash.o diff --git a/drivers/crypto/talitos/talitos-core.c b/drivers/crypto/talitos= /talitos-core.c index aa0a15f3c9da..25265d8dd9b4 100644 --- a/drivers/crypto/talitos/talitos-core.c +++ b/drivers/crypto/talitos/talitos-core.c @@ -740,28 +740,6 @@ DEF_TALITOS2_INTERRUPT(ch1_3, TALITOS2_ISR_CH_1_3_DONE= , TALITOS2_ISR_CH_1_3_ERR, */ #define TALITOS_CRA_PRIORITY_AEAD_HSNA (TALITOS_CRA_PRIORITY - 1) =20 -#define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA= 512 - -struct talitos_ahash_req_ctx { - u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)]; - u8 padding_buf[64]; - u64 message_size; - unsigned int hw_context_size; - unsigned int swinit; - unsigned int first_request; - unsigned int last_request; - unsigned int to_hash_later; -}; - -struct talitos_export_state { - u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)]; - u64 message_size; - unsigned int swinit; - unsigned int first_request; - unsigned int last_request; - unsigned int to_hash_later; -}; - static int aead_setkey(struct crypto_aead *authenc, const u8 *key, unsigned int keylen) { @@ -1570,514 +1548,6 @@ static int skcipher_decrypt(struct skcipher_request= *areq) return common_nonsnoop(edesc, areq, skcipher_done); } =20 -static void common_nonsnoop_hash_unmap(struct device *dev, - struct talitos_edesc *edesc, - struct ahash_request *areq) -{ - struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); - struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); - struct talitos_private *priv =3D dev_get_drvdata(dev); - bool is_sec1 =3D has_ftr_sec1(priv); - struct talitos_desc *desc =3D &edesc->desc; - - unmap_single_talitos_ptr(dev, &desc->ptr[5], DMA_FROM_DEVICE); - - if (edesc->last && req_ctx->last_request) - memcpy(areq->result, req_ctx->hw_context, - crypto_ahash_digestsize(tfm)); - - if (edesc->src) - talitos_sg_unmap(dev, edesc, edesc->src, NULL, 0, 0); - - /* When using hashctx-in, must unmap it. */ - if (from_talitos_ptr_len(&desc->ptr[1], is_sec1)) - unmap_single_talitos_ptr(dev, &desc->ptr[1], - DMA_TO_DEVICE); - - if (edesc->dma_len) - dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len, - DMA_BIDIRECTIONAL); -} - -static void free_edesc_list_from(struct ahash_request *areq, struct talito= s_edesc *edesc) -{ - struct talitos_ctx *ctx =3D crypto_ahash_ctx(crypto_ahash_reqtfm(areq)); - struct talitos_edesc *next; - - while (edesc) { - next =3D edesc->next_desc; - common_nonsnoop_hash_unmap(ctx->dev, edesc, areq); - kfree(edesc); - edesc =3D next; - } -} - -static void ahash_done(struct device *dev, - struct talitos_desc *desc, void *context, - int err) -{ - struct ahash_request *areq =3D context; - struct talitos_edesc *edesc =3D - container_of(desc, struct talitos_edesc, desc); - struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); - struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); - bool is_sec1 =3D has_ftr_sec1(dev_get_drvdata(dev)); - struct talitos_ctx *ctx =3D crypto_ahash_ctx(tfm); - struct talitos_edesc *next; - - if (is_sec1) { - free_edesc_list_from(areq, edesc); - ahash_request_complete(areq, err ?: req_ctx->to_hash_later); - } else { - next =3D edesc->next_desc; - - common_nonsnoop_hash_unmap(dev, edesc, areq); - kfree(edesc); - - if (err) - goto out; - - if (next) { - err =3D talitos_submit(dev, ctx->ch, &next->desc, - ahash_done, areq); - if (err !=3D -EINPROGRESS) - goto out; - return; - } -out: - if (err && next) - free_edesc_list_from(areq, next); - ahash_request_complete(areq, err ?: req_ctx->to_hash_later); - } -} - -/* - * SEC1 doesn't like hashing of 0 sized message, so we do the padding - * ourself and submit a padded block - */ -static void talitos_handle_buggy_hash(struct ahash_request *areq, - struct talitos_edesc *edesc, - struct talitos_ptr *ptr) -{ - struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); - struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); - struct talitos_ctx *ctx =3D crypto_ahash_ctx(tfm); - - __be64 be_len =3D cpu_to_be64(req_ctx->message_size << 3); - __le64 le_len =3D cpu_to_le64(req_ctx->message_size << 3); - - memset(req_ctx->padding_buf, 0, sizeof(req_ctx->padding_buf)); - req_ctx->padding_buf[0] =3D 0x80; - if (crypto_ahash_digestsize(tfm) =3D=3D MD5_DIGEST_SIZE) - memcpy(&req_ctx->padding_buf[56], &le_len, sizeof(le_len)); - else - memcpy(&req_ctx->padding_buf[56], &be_len, sizeof(be_len)); - pr_err_once("Bug in SEC1, padding ourself\n"); - edesc->desc.hdr &=3D ~DESC_HDR_MODE0_MDEU_PAD; - map_single_talitos_ptr(ctx->dev, ptr, sizeof(req_ctx->padding_buf), - (char *)req_ctx->padding_buf, DMA_TO_DEVICE); -} - -static void common_nonsnoop_hash(struct talitos_edesc *edesc, - struct ahash_request *areq, - unsigned int length) -{ - struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); - struct talitos_ctx *ctx =3D crypto_ahash_ctx(tfm); - struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); - struct device *dev =3D ctx->dev; - struct talitos_desc *desc =3D &edesc->desc; - bool sync_needed =3D false; - struct talitos_private *priv =3D dev_get_drvdata(dev); - bool is_sec1 =3D has_ftr_sec1(priv); - int sg_count; - - /* first DWORD empty */ - - /* hash context in */ - if (!edesc->first || !req_ctx->first_request || req_ctx->swinit) { - map_single_talitos_ptr_nosync(dev, &desc->ptr[1], - req_ctx->hw_context_size, - req_ctx->hw_context, - DMA_TO_DEVICE); - req_ctx->swinit =3D 0; - } - /* Indicate next op is not the first. */ - req_ctx->first_request =3D 0; - - /* HMAC key */ - if (ctx->keylen) - to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen, - is_sec1); - - sg_count =3D edesc->src_nents ?: 1; - if (is_sec1 && sg_count > 1) - sg_copy_to_buffer(edesc->src, sg_count, edesc->buf, length); - else if (length) - sg_count =3D dma_map_sg(dev, edesc->src, sg_count, DMA_TO_DEVICE); - - /* - * data in - */ - sg_count =3D talitos_sg_map(dev, edesc->src, length, edesc, &desc->ptr[3], - sg_count, 0, 0); - if (sg_count > 1) - sync_needed =3D true; - - /* fifth DWORD empty */ - - /* hash/HMAC out -or- hash context out */ - if (edesc->last && req_ctx->last_request) - map_single_talitos_ptr(dev, &desc->ptr[5], - crypto_ahash_digestsize(tfm), - req_ctx->hw_context, DMA_FROM_DEVICE); - else - map_single_talitos_ptr_nosync(dev, &desc->ptr[5], - req_ctx->hw_context_size, - req_ctx->hw_context, - DMA_FROM_DEVICE); - - /* last DWORD empty */ - - if (is_sec1 && from_talitos_ptr_len(&desc->ptr[3], true) =3D=3D 0) - talitos_handle_buggy_hash(areq, edesc, &desc->ptr[3]); - - if (sync_needed) - dma_sync_single_for_device(dev, edesc->dma_link_tbl, - edesc->dma_len, DMA_BIDIRECTIONAL); -} - -static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq, - struct scatterlist *src, - unsigned int nbytes) -{ - struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); - struct talitos_ctx *ctx =3D crypto_ahash_ctx(tfm); - - return talitos_edesc_alloc(ctx->dev, src, NULL, NULL, 0, - nbytes, 0, 0, 0, areq->base.flags, false); -} - -static struct talitos_edesc * -ahash_process_req_prepare(struct ahash_request *areq, unsigned int nbytes, - unsigned int blocksize, bool is_sec1) -{ - struct talitos_ctx *ctx =3D crypto_ahash_ctx(crypto_ahash_reqtfm(areq)); - struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); - struct talitos_edesc *first =3D NULL, *prev_edesc =3D NULL, *edesc; - size_t desc_max =3D is_sec1 ? TALITOS1_MAX_DATA_LEN : - TALITOS2_MAX_DATA_LEN; - struct scatterlist tmp[2]; - size_t to_hash_this_desc; - struct scatterlist *src; - size_t offset =3D 0; - - do { - src =3D scatterwalk_ffwd(tmp, areq->src, offset); - - to_hash_this_desc =3D - min(nbytes, ALIGN_DOWN(desc_max, blocksize)); - - /* Allocate extended descriptor */ - edesc =3D ahash_edesc_alloc(areq, src, to_hash_this_desc); - if (IS_ERR(edesc)) { - if (first) - free_edesc_list_from(areq, first); - return edesc; - } - - edesc->src =3D scatterwalk_ffwd(edesc->bufsl, areq->src, offset); - edesc->desc.hdr =3D ctx->desc_hdr_template; - edesc->first =3D offset =3D=3D 0; - edesc->last =3D nbytes - to_hash_this_desc =3D=3D 0; - - /* On last one, request SEC to pad; otherwise continue */ - if (req_ctx->last_request && edesc->last) - edesc->desc.hdr |=3D DESC_HDR_MODE0_MDEU_PAD; - else - edesc->desc.hdr |=3D DESC_HDR_MODE0_MDEU_CONT; - - /* request SEC to INIT hash. */ - if (req_ctx->first_request && edesc->first && !req_ctx->swinit) - edesc->desc.hdr |=3D DESC_HDR_MODE0_MDEU_INIT; - - /* - * When the tfm context has a keylen, it's an HMAC. - * A first or last (ie. not middle) descriptor must request HMAC. - */ - if (ctx->keylen && ((req_ctx->first_request && edesc->first) || - (req_ctx->last_request && edesc->last))) - edesc->desc.hdr |=3D DESC_HDR_MODE0_MDEU_HMAC; - - /* clear the DN bit */ - if (is_sec1 && !edesc->last) - edesc->desc.hdr &=3D ~DESC_HDR_DONE_NOTIFY; - - common_nonsnoop_hash(edesc, areq, to_hash_this_desc); - - offset +=3D to_hash_this_desc; - nbytes -=3D to_hash_this_desc; - - if (!prev_edesc) - first =3D edesc; - else - prev_edesc->next_desc =3D edesc; - prev_edesc =3D edesc; - } while (nbytes); - - return first; -} - -static int ahash_process_req(struct ahash_request *areq, unsigned int nbyt= es) -{ - struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); - struct talitos_ctx *ctx =3D crypto_ahash_ctx(tfm); - struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); - struct talitos_edesc *edesc; - unsigned int blocksize =3D - crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); - bool is_sec1 =3D has_ftr_sec1(dev_get_drvdata(ctx->dev)); - unsigned int nbytes_to_hash; - unsigned int to_hash_later; - struct device *dev =3D ctx->dev; - int ret; - - nbytes_to_hash =3D ALIGN_DOWN(nbytes, blocksize); - to_hash_later =3D nbytes - nbytes_to_hash; - - if (req_ctx->last_request) { - nbytes_to_hash =3D nbytes; - to_hash_later =3D 0; - } - - req_ctx->to_hash_later =3D to_hash_later; - - edesc =3D ahash_process_req_prepare(areq, nbytes_to_hash, blocksize, - is_sec1); - if (IS_ERR(edesc)) - return PTR_ERR(edesc); - - req_ctx->message_size +=3D nbytes_to_hash; - - ret =3D talitos_submit(dev, ctx->ch, &edesc->desc, ahash_done, areq); - if (ret !=3D -EINPROGRESS) { - req_ctx->message_size -=3D nbytes_to_hash; - free_edesc_list_from(areq, edesc); - } - - return ret; -} - -static int ahash_init(struct ahash_request *areq) -{ - struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); - struct talitos_ctx *ctx =3D crypto_ahash_ctx(tfm); - struct device *dev =3D ctx->dev; - struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); - unsigned int size; - dma_addr_t dma; - - /* Initialize the context */ - req_ctx->first_request =3D 1; - req_ctx->swinit =3D 0; /* assume h/w init of context */ - size =3D (crypto_ahash_digestsize(tfm) <=3D SHA256_DIGEST_SIZE) - ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 - : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512; - req_ctx->hw_context_size =3D size; - req_ctx->last_request =3D 0; - req_ctx->message_size =3D 0; - - dma =3D dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size, - DMA_TO_DEVICE); - dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_TO_DEVICE); - - return 0; -} - -/* - * on h/w without explicit sha224 support, we initialize h/w context - * manually with sha224 constants, and tell it to run sha256. - */ -static int ahash_init_sha224_swinit(struct ahash_request *areq) -{ - struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); - - req_ctx->hw_context[0] =3D SHA224_H0; - req_ctx->hw_context[1] =3D SHA224_H1; - req_ctx->hw_context[2] =3D SHA224_H2; - req_ctx->hw_context[3] =3D SHA224_H3; - req_ctx->hw_context[4] =3D SHA224_H4; - req_ctx->hw_context[5] =3D SHA224_H5; - req_ctx->hw_context[6] =3D SHA224_H6; - req_ctx->hw_context[7] =3D SHA224_H7; - - /* init 64-bit count */ - req_ctx->hw_context[8] =3D 0; - req_ctx->hw_context[9] =3D 0; - - ahash_init(areq); - req_ctx->swinit =3D 1;/* prevent h/w initting context with sha256 values*/ - - return 0; -} - -static int ahash_update(struct ahash_request *areq) -{ - struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); - - req_ctx->last_request =3D 0; - - return ahash_process_req(areq, areq->nbytes); -} - -static int ahash_final(struct ahash_request *areq) -{ - struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); - - req_ctx->last_request =3D 1; - - return ahash_process_req(areq, 0); -} - -static int ahash_finup(struct ahash_request *areq) -{ - struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); - - req_ctx->last_request =3D 1; - - return ahash_process_req(areq, areq->nbytes); -} - -static int ahash_digest(struct ahash_request *areq) -{ - ahash_init(areq); - return ahash_finup(areq); -} - -static int ahash_digest_sha224_swinit(struct ahash_request *areq) -{ - ahash_init_sha224_swinit(areq); - return ahash_finup(areq); -} - -static int ahash_export(struct ahash_request *areq, void *out) -{ - struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); - struct talitos_export_state *export =3D out; - struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); - struct talitos_ctx *ctx =3D crypto_ahash_ctx(tfm); - struct device *dev =3D ctx->dev; - dma_addr_t dma; - - dma =3D dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size, - DMA_FROM_DEVICE); - dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_FROM_DEVICE); - - memcpy(export->hw_context, req_ctx->hw_context, - req_ctx->hw_context_size); - export->swinit =3D req_ctx->swinit; - export->first_request =3D req_ctx->first_request; - export->last_request =3D req_ctx->last_request; - export->to_hash_later =3D req_ctx->to_hash_later; - export->message_size =3D req_ctx->message_size; - - return 0; -} - -static int ahash_import(struct ahash_request *areq, const void *in) -{ - struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); - struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); - struct talitos_ctx *ctx =3D crypto_ahash_ctx(tfm); - struct device *dev =3D ctx->dev; - const struct talitos_export_state *export =3D in; - unsigned int size; - dma_addr_t dma; - - memset(req_ctx, 0, sizeof(*req_ctx)); - size =3D (crypto_ahash_digestsize(tfm) <=3D SHA256_DIGEST_SIZE) - ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 - : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512; - req_ctx->hw_context_size =3D size; - memcpy(req_ctx->hw_context, export->hw_context, size); - req_ctx->swinit =3D export->swinit; - req_ctx->first_request =3D export->first_request; - req_ctx->last_request =3D export->last_request; - req_ctx->to_hash_later =3D export->to_hash_later; - req_ctx->message_size =3D export->message_size; - - dma =3D dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size, - DMA_TO_DEVICE); - dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_TO_DEVICE); - - return 0; -} - -static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int k= eylen, - u8 *hash) -{ - struct talitos_ctx *ctx =3D crypto_tfm_ctx(crypto_ahash_tfm(tfm)); - - struct scatterlist sg[1]; - struct ahash_request *req; - struct crypto_wait wait; - int ret; - - crypto_init_wait(&wait); - - req =3D ahash_request_alloc(tfm, GFP_KERNEL); - if (!req) - return -ENOMEM; - - /* Keep tfm keylen =3D=3D 0 during hash of the long key */ - ctx->keylen =3D 0; - ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, - crypto_req_done, &wait); - - sg_init_one(&sg[0], key, keylen); - - ahash_request_set_crypt(req, sg, hash, keylen); - ret =3D crypto_wait_req(crypto_ahash_digest(req), &wait); - - ahash_request_free(req); - - return ret; -} - -static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key, - unsigned int keylen) -{ - struct talitos_ctx *ctx =3D crypto_tfm_ctx(crypto_ahash_tfm(tfm)); - struct device *dev =3D ctx->dev; - unsigned int blocksize =3D - crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); - unsigned int digestsize =3D crypto_ahash_digestsize(tfm); - unsigned int keysize =3D keylen; - u8 hash[SHA512_DIGEST_SIZE]; - int ret; - - if (keylen <=3D blocksize) - memcpy(ctx->key, key, keysize); - else { - /* Must get the hash of the long key */ - ret =3D keyhash(tfm, key, keylen, hash); - - if (ret) - return -EINVAL; - - keysize =3D digestsize; - memcpy(ctx->key, hash, digestsize); - } - - if (ctx->keylen) - dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE); - - ctx->keylen =3D keysize; - ctx->dma_key =3D dma_map_single(dev, ctx->key, keysize, DMA_TO_DEVICE); - - return 0; -} - static struct talitos_alg_template driver_algs[] =3D { /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */ { .type =3D CRYPTO_ALG_TYPE_AEAD, @@ -2661,223 +2131,6 @@ static struct talitos_alg_template driver_algs[] = =3D { DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES, }, - /* AHASH algorithms. */ - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D MD5_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "md5", - .cra_driver_name =3D "md5-talitos", - .cra_blocksize =3D MD5_HMAC_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUA | - DESC_HDR_MODE0_MDEU_MD5, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D SHA1_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "sha1", - .cra_driver_name =3D "sha1-talitos", - .cra_blocksize =3D SHA1_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUA | - DESC_HDR_MODE0_MDEU_SHA1, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D SHA224_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "sha224", - .cra_driver_name =3D "sha224-talitos", - .cra_blocksize =3D SHA224_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUA | - DESC_HDR_MODE0_MDEU_SHA224, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D SHA256_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "sha256", - .cra_driver_name =3D "sha256-talitos", - .cra_blocksize =3D SHA256_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUA | - DESC_HDR_MODE0_MDEU_SHA256, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D SHA384_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "sha384", - .cra_driver_name =3D "sha384-talitos", - .cra_blocksize =3D SHA384_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUB | - DESC_HDR_MODE0_MDEUB_SHA384, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D SHA512_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "sha512", - .cra_driver_name =3D "sha512-talitos", - .cra_blocksize =3D SHA512_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUB | - DESC_HDR_MODE0_MDEUB_SHA512, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D MD5_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "hmac(md5)", - .cra_driver_name =3D "hmac-md5-talitos", - .cra_blocksize =3D MD5_HMAC_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUA | - DESC_HDR_MODE0_MDEU_MD5, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D SHA1_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "hmac(sha1)", - .cra_driver_name =3D "hmac-sha1-talitos", - .cra_blocksize =3D SHA1_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUA | - DESC_HDR_MODE0_MDEU_SHA1, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D SHA224_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "hmac(sha224)", - .cra_driver_name =3D "hmac-sha224-talitos", - .cra_blocksize =3D SHA224_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUA | - DESC_HDR_MODE0_MDEU_SHA224, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D SHA256_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "hmac(sha256)", - .cra_driver_name =3D "hmac-sha256-talitos", - .cra_blocksize =3D SHA256_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUA | - DESC_HDR_MODE0_MDEU_SHA256, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D SHA384_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "hmac(sha384)", - .cra_driver_name =3D "hmac-sha384-talitos", - .cra_blocksize =3D SHA384_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUB | - DESC_HDR_MODE0_MDEUB_SHA384, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D SHA512_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "hmac(sha512)", - .cra_driver_name =3D "hmac-sha512-talitos", - .cra_blocksize =3D SHA512_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUB | - DESC_HDR_MODE0_MDEUB_SHA512, - } }; =20 int talitos_init_common(struct talitos_ctx *ctx, @@ -2926,21 +2179,6 @@ static int talitos_cra_init_skcipher(struct crypto_s= kcipher *tfm) return talitos_init_common(ctx, talitos_alg); } =20 -static int talitos_cra_init_ahash(struct crypto_tfm *tfm) -{ - struct crypto_alg *alg =3D tfm->__crt_alg; - struct talitos_crypto_alg *talitos_alg; - struct talitos_ctx *ctx =3D crypto_tfm_ctx(tfm); - - talitos_alg =3D container_of(__crypto_ahash_alg(alg), - struct talitos_crypto_alg, - algt.alg.hash); - - ctx->keylen =3D 0; - - return talitos_init_common(ctx, talitos_alg); -} - void talitos_cra_exit(struct crypto_tfm *tfm) { struct talitos_ctx *ctx =3D crypto_tfm_ctx(tfm); @@ -3004,6 +2242,64 @@ static void talitos_remove(struct platform_device *o= fdev) tasklet_kill(&priv->done_task[1]); } =20 +static void talitos_alg_set_common(struct talitos_private *priv, + struct crypto_alg *alg, u32 custom_priority, + u32 type) +{ + alg->cra_module =3D THIS_MODULE; + if (custom_priority) + alg->cra_priority =3D custom_priority; + else + alg->cra_priority =3D TALITOS_CRA_PRIORITY; + if (has_ftr_sec1(priv) && type !=3D CRYPTO_ALG_TYPE_AHASH) + alg->cra_alignmask =3D 3; + else + alg->cra_alignmask =3D 0; + alg->cra_ctxsize =3D sizeof(struct talitos_ctx); + alg->cra_flags |=3D CRYPTO_ALG_KERN_DRIVER_ONLY; +} + +int talitos_register_common(struct device *dev, + struct talitos_alg_template *template) +{ + struct talitos_private *priv =3D dev_get_drvdata(dev); + struct talitos_crypto_alg *t_alg; + struct crypto_alg *alg; + int ret; + + t_alg =3D devm_kzalloc(dev, sizeof(struct talitos_crypto_alg), + GFP_KERNEL); + if (!t_alg) + return -ENOMEM; + + t_alg->algt =3D *template; + t_alg->dev =3D dev; + + switch (t_alg->algt.type) { + case CRYPTO_ALG_TYPE_AHASH: + alg =3D &t_alg->algt.alg.hash.halg.base; + talitos_alg_set_common(priv, alg, t_alg->algt.priority, + t_alg->algt.type); + ret =3D crypto_register_ahash(&t_alg->algt.alg.hash); + break; + default: + dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type); + devm_kfree(dev, t_alg); + return -EINVAL; + } + + if (ret) { + dev_err(dev, "%s alg registration failed\n", + alg->cra_driver_name); + devm_kfree(dev, t_alg); + return 0; + } + + list_add_tail(&t_alg->entry, &priv->alg_list); + + return 0; +} + static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev, struct talitos_alg_template *template) @@ -3049,37 +2345,6 @@ static struct talitos_crypto_alg *talitos_alg_alloc(= struct device *dev, return ERR_PTR(-ENOTSUPP); } break; - case CRYPTO_ALG_TYPE_AHASH: - alg =3D &t_alg->algt.alg.hash.halg.base; - alg->cra_init =3D talitos_cra_init_ahash; - alg->cra_exit =3D talitos_cra_exit; - t_alg->algt.alg.hash.init =3D ahash_init; - t_alg->algt.alg.hash.update =3D ahash_update; - t_alg->algt.alg.hash.final =3D ahash_final; - t_alg->algt.alg.hash.finup =3D ahash_finup; - t_alg->algt.alg.hash.digest =3D ahash_digest; - if (!strncmp(alg->cra_name, "hmac", 4)) - t_alg->algt.alg.hash.setkey =3D ahash_setkey; - t_alg->algt.alg.hash.import =3D ahash_import; - t_alg->algt.alg.hash.export =3D ahash_export; - - if (!(priv->features & TALITOS_FTR_HMAC_OK) && - !strncmp(alg->cra_name, "hmac", 4)) { - devm_kfree(dev, t_alg); - return ERR_PTR(-ENOTSUPP); - } - if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) && - (!strcmp(alg->cra_name, "sha224") || - !strcmp(alg->cra_name, "hmac(sha224)"))) { - t_alg->algt.alg.hash.init =3D ahash_init_sha224_swinit; - t_alg->algt.alg.hash.digest =3D - ahash_digest_sha224_swinit; - t_alg->algt.desc_hdr_template =3D - DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUA | - DESC_HDR_MODE0_MDEU_SHA256; - } - break; default: dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type); devm_kfree(dev, t_alg); @@ -3306,6 +2571,10 @@ static int talitos_probe(struct platform_device *ofd= ev) dev_info(dev, "hwrng\n"); } =20 + err =3D talitos_register_hash(dev); + if (err) + goto err_out; + /* register crypto algorithms the device supports */ for (i =3D 0; i < ARRAY_SIZE(driver_algs); i++) { if (talitos_hw_supports(dev, @@ -3333,12 +2602,6 @@ static int talitos_probe(struct platform_device *ofd= ev) &t_alg->algt.alg.aead); alg =3D &t_alg->algt.alg.aead.base; break; - - case CRYPTO_ALG_TYPE_AHASH: - err =3D crypto_register_ahash( - &t_alg->algt.alg.hash); - alg =3D &t_alg->algt.alg.hash.halg.base; - break; } if (err) { dev_err(dev, "%s alg registration failed\n", diff --git a/drivers/crypto/talitos/talitos-hash.c b/drivers/crypto/talitos= /talitos-hash.c new file mode 100644 index 000000000000..7ce4e68dd7a0 --- /dev/null +++ b/drivers/crypto/talitos/talitos-hash.c @@ -0,0 +1,835 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/* + * Freescale SEC (talitos) hash implementation + * + * Copyright (c) 2006-2011 Freescale Semiconductor, Inc. + */ + +#include + +#include +#include +#include +#include +#include + +#include "talitos.h" + +#define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA= 512 + +struct talitos_ahash_req_ctx { + u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)]; + u8 padding_buf[64]; + u64 message_size; + unsigned int hw_context_size; + unsigned int swinit; + unsigned int first_request; + unsigned int last_request; + unsigned int to_hash_later; +}; + +struct talitos_export_state { + u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)]; + u64 message_size; + unsigned int swinit; + unsigned int first_request; + unsigned int last_request; + unsigned int to_hash_later; +}; + +static void common_nonsnoop_hash_unmap(struct device *dev, + struct talitos_edesc *edesc, + struct ahash_request *areq) +{ + struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); + struct talitos_private *priv =3D dev_get_drvdata(dev); + bool is_sec1 =3D has_ftr_sec1(priv); + struct talitos_desc *desc =3D &edesc->desc; + + unmap_single_talitos_ptr(dev, &desc->ptr[5], DMA_FROM_DEVICE); + + if (edesc->last && req_ctx->last_request) + memcpy(areq->result, req_ctx->hw_context, + crypto_ahash_digestsize(tfm)); + + if (edesc->src) + talitos_sg_unmap(dev, edesc, edesc->src, NULL, 0, 0); + + /* When using hashctx-in, must unmap it. */ + if (from_talitos_ptr_len(&desc->ptr[1], is_sec1)) + unmap_single_talitos_ptr(dev, &desc->ptr[1], + DMA_TO_DEVICE); + + if (edesc->dma_len) + dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len, + DMA_BIDIRECTIONAL); +} + +static void free_edesc_list_from(struct ahash_request *areq, struct talito= s_edesc *edesc) +{ + struct talitos_ctx *ctx =3D crypto_ahash_ctx(crypto_ahash_reqtfm(areq)); + struct talitos_edesc *next; + + while (edesc) { + next =3D edesc->next_desc; + common_nonsnoop_hash_unmap(ctx->dev, edesc, areq); + kfree(edesc); + edesc =3D next; + } +} + +static void ahash_done(struct device *dev, + struct talitos_desc *desc, void *context, + int err) +{ + struct ahash_request *areq =3D context; + struct talitos_edesc *edesc =3D + container_of(desc, struct talitos_edesc, desc); + struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); + bool is_sec1 =3D has_ftr_sec1(dev_get_drvdata(dev)); + struct talitos_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct talitos_edesc *next; + + if (is_sec1) { + free_edesc_list_from(areq, edesc); + ahash_request_complete(areq, err ?: req_ctx->to_hash_later); + } else { + next =3D edesc->next_desc; + + common_nonsnoop_hash_unmap(dev, edesc, areq); + kfree(edesc); + + if (err) + goto out; + + if (next) { + err =3D talitos_submit(dev, ctx->ch, &next->desc, + ahash_done, areq); + if (err !=3D -EINPROGRESS) + goto out; + return; + } +out: + if (err && next) + free_edesc_list_from(areq, next); + ahash_request_complete(areq, err ?: req_ctx->to_hash_later); + } +} + +/* + * SEC1 doesn't like hashing of 0 sized message, so we do the padding + * ourself and submit a padded block + */ +static void talitos_handle_buggy_hash(struct ahash_request *areq, + struct talitos_edesc *edesc, + struct talitos_ptr *ptr) +{ + struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); + struct talitos_ctx *ctx =3D crypto_ahash_ctx(tfm); + + __be64 be_len =3D cpu_to_be64(req_ctx->message_size << 3); + __le64 le_len =3D cpu_to_le64(req_ctx->message_size << 3); + + memset(req_ctx->padding_buf, 0, sizeof(req_ctx->padding_buf)); + req_ctx->padding_buf[0] =3D 0x80; + if (crypto_ahash_digestsize(tfm) =3D=3D MD5_DIGEST_SIZE) + memcpy(&req_ctx->padding_buf[56], &le_len, sizeof(le_len)); + else + memcpy(&req_ctx->padding_buf[56], &be_len, sizeof(be_len)); + pr_err_once("Bug in SEC1, padding ourself\n"); + edesc->desc.hdr &=3D ~DESC_HDR_MODE0_MDEU_PAD; + map_single_talitos_ptr(ctx->dev, ptr, sizeof(req_ctx->padding_buf), + (char *)req_ctx->padding_buf, DMA_TO_DEVICE); +} + +static void common_nonsnoop_hash(struct talitos_edesc *edesc, + struct ahash_request *areq, + unsigned int length) +{ + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); + struct talitos_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); + struct device *dev =3D ctx->dev; + struct talitos_desc *desc =3D &edesc->desc; + bool sync_needed =3D false; + struct talitos_private *priv =3D dev_get_drvdata(dev); + bool is_sec1 =3D has_ftr_sec1(priv); + int sg_count; + + /* first DWORD empty */ + + /* hash context in */ + if (!edesc->first || !req_ctx->first_request || req_ctx->swinit) { + map_single_talitos_ptr_nosync(dev, &desc->ptr[1], + req_ctx->hw_context_size, + req_ctx->hw_context, + DMA_TO_DEVICE); + req_ctx->swinit =3D 0; + } + /* Indicate next op is not the first. */ + req_ctx->first_request =3D 0; + + /* HMAC key */ + if (ctx->keylen) + to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen, + is_sec1); + + sg_count =3D edesc->src_nents ?: 1; + if (is_sec1 && sg_count > 1) + sg_copy_to_buffer(edesc->src, sg_count, edesc->buf, length); + else if (length) + sg_count =3D dma_map_sg(dev, edesc->src, sg_count, DMA_TO_DEVICE); + + /* + * data in + */ + sg_count =3D talitos_sg_map(dev, edesc->src, length, edesc, &desc->ptr[3], + sg_count, 0, 0); + if (sg_count > 1) + sync_needed =3D true; + + /* fifth DWORD empty */ + + /* hash/HMAC out -or- hash context out */ + if (edesc->last && req_ctx->last_request) + map_single_talitos_ptr(dev, &desc->ptr[5], + crypto_ahash_digestsize(tfm), + req_ctx->hw_context, DMA_FROM_DEVICE); + else + map_single_talitos_ptr_nosync(dev, &desc->ptr[5], + req_ctx->hw_context_size, + req_ctx->hw_context, + DMA_FROM_DEVICE); + + /* last DWORD empty */ + + if (is_sec1 && from_talitos_ptr_len(&desc->ptr[3], true) =3D=3D 0) + talitos_handle_buggy_hash(areq, edesc, &desc->ptr[3]); + + if (sync_needed) + dma_sync_single_for_device(dev, edesc->dma_link_tbl, + edesc->dma_len, DMA_BIDIRECTIONAL); +} + +static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq, + struct scatterlist *src, + unsigned int nbytes) +{ + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); + struct talitos_ctx *ctx =3D crypto_ahash_ctx(tfm); + + return talitos_edesc_alloc(ctx->dev, src, NULL, NULL, 0, + nbytes, 0, 0, 0, areq->base.flags, false); +} + +static struct talitos_edesc * +ahash_process_req_prepare(struct ahash_request *areq, unsigned int nbytes, + unsigned int blocksize, bool is_sec1) +{ + struct talitos_ctx *ctx =3D crypto_ahash_ctx(crypto_ahash_reqtfm(areq)); + struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); + struct talitos_edesc *first =3D NULL, *prev_edesc =3D NULL, *edesc; + size_t desc_max =3D is_sec1 ? TALITOS1_MAX_DATA_LEN : + TALITOS2_MAX_DATA_LEN; + struct scatterlist tmp[2]; + size_t to_hash_this_desc; + struct scatterlist *src; + size_t offset =3D 0; + + do { + src =3D scatterwalk_ffwd(tmp, areq->src, offset); + + to_hash_this_desc =3D + min(nbytes, ALIGN_DOWN(desc_max, blocksize)); + + /* Allocate extended descriptor */ + edesc =3D ahash_edesc_alloc(areq, src, to_hash_this_desc); + if (IS_ERR(edesc)) { + if (first) + free_edesc_list_from(areq, first); + return edesc; + } + + edesc->src =3D scatterwalk_ffwd(edesc->bufsl, areq->src, offset); + edesc->desc.hdr =3D ctx->desc_hdr_template; + edesc->first =3D offset =3D=3D 0; + edesc->last =3D nbytes - to_hash_this_desc =3D=3D 0; + + /* On last one, request SEC to pad; otherwise continue */ + if (req_ctx->last_request && edesc->last) + edesc->desc.hdr |=3D DESC_HDR_MODE0_MDEU_PAD; + else + edesc->desc.hdr |=3D DESC_HDR_MODE0_MDEU_CONT; + + /* request SEC to INIT hash. */ + if (req_ctx->first_request && edesc->first && !req_ctx->swinit) + edesc->desc.hdr |=3D DESC_HDR_MODE0_MDEU_INIT; + + /* + * When the tfm context has a keylen, it's an HMAC. + * A first or last (ie. not middle) descriptor must request HMAC. + */ + if (ctx->keylen && ((req_ctx->first_request && edesc->first) || + (req_ctx->last_request && edesc->last))) + edesc->desc.hdr |=3D DESC_HDR_MODE0_MDEU_HMAC; + + /* clear the DN bit */ + if (is_sec1 && !edesc->last) + edesc->desc.hdr &=3D ~DESC_HDR_DONE_NOTIFY; + + common_nonsnoop_hash(edesc, areq, to_hash_this_desc); + + offset +=3D to_hash_this_desc; + nbytes -=3D to_hash_this_desc; + + if (!prev_edesc) + first =3D edesc; + else + prev_edesc->next_desc =3D edesc; + prev_edesc =3D edesc; + } while (nbytes); + + return first; +} + +static int ahash_process_req(struct ahash_request *areq, unsigned int nbyt= es) +{ + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); + struct talitos_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); + struct talitos_edesc *edesc; + unsigned int blocksize =3D + crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); + bool is_sec1 =3D has_ftr_sec1(dev_get_drvdata(ctx->dev)); + unsigned int nbytes_to_hash; + unsigned int to_hash_later; + struct device *dev =3D ctx->dev; + int ret; + + nbytes_to_hash =3D ALIGN_DOWN(nbytes, blocksize); + to_hash_later =3D nbytes - nbytes_to_hash; + + if (req_ctx->last_request) { + nbytes_to_hash =3D nbytes; + to_hash_later =3D 0; + } + + req_ctx->to_hash_later =3D to_hash_later; + + edesc =3D ahash_process_req_prepare(areq, nbytes_to_hash, blocksize, + is_sec1); + if (IS_ERR(edesc)) + return PTR_ERR(edesc); + + ret =3D talitos_submit(dev, ctx->ch, &edesc->desc, ahash_done, areq); + if (ret !=3D -EINPROGRESS) + free_edesc_list_from(areq, edesc); + else + req_ctx->message_size +=3D nbytes_to_hash; + + return ret; +} + +static int ahash_init(struct ahash_request *areq) +{ + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); + struct talitos_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct device *dev =3D ctx->dev; + struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); + unsigned int size; + dma_addr_t dma; + + /* Initialize the context */ + req_ctx->first_request =3D 1; + req_ctx->swinit =3D 0; /* assume h/w init of context */ + size =3D (crypto_ahash_digestsize(tfm) <=3D SHA256_DIGEST_SIZE) + ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 + : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512; + req_ctx->hw_context_size =3D size; + req_ctx->last_request =3D 0; + req_ctx->message_size =3D 0; + + dma =3D dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size, + DMA_TO_DEVICE); + dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_TO_DEVICE); + + return 0; +} + +/* + * on h/w without explicit sha224 support, we initialize h/w context + * manually with sha224 constants, and tell it to run sha256. + */ +static int ahash_init_sha224_swinit(struct ahash_request *areq) +{ + struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); + + req_ctx->hw_context[0] =3D SHA224_H0; + req_ctx->hw_context[1] =3D SHA224_H1; + req_ctx->hw_context[2] =3D SHA224_H2; + req_ctx->hw_context[3] =3D SHA224_H3; + req_ctx->hw_context[4] =3D SHA224_H4; + req_ctx->hw_context[5] =3D SHA224_H5; + req_ctx->hw_context[6] =3D SHA224_H6; + req_ctx->hw_context[7] =3D SHA224_H7; + + /* init 64-bit count */ + req_ctx->hw_context[8] =3D 0; + req_ctx->hw_context[9] =3D 0; + + ahash_init(areq); + req_ctx->swinit =3D 1;/* prevent h/w initting context with sha256 values*/ + + return 0; +} + +static int ahash_update(struct ahash_request *areq) +{ + struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); + + req_ctx->last_request =3D 0; + + return ahash_process_req(areq, areq->nbytes); +} + +static int ahash_final(struct ahash_request *areq) +{ + struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); + + req_ctx->last_request =3D 1; + + return ahash_process_req(areq, 0); +} + +static int ahash_finup(struct ahash_request *areq) +{ + struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); + + req_ctx->last_request =3D 1; + + return ahash_process_req(areq, areq->nbytes); +} + +static int ahash_digest(struct ahash_request *areq) +{ + ahash_init(areq); + return ahash_finup(areq); +} + +static int ahash_digest_sha224_swinit(struct ahash_request *areq) +{ + ahash_init_sha224_swinit(areq); + return ahash_finup(areq); +} + +static int ahash_export(struct ahash_request *areq, void *out) +{ + struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); + struct talitos_export_state *export =3D out; + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); + struct talitos_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct device *dev =3D ctx->dev; + dma_addr_t dma; + + dma =3D dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size, + DMA_FROM_DEVICE); + dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_FROM_DEVICE); + + memcpy(export->hw_context, req_ctx->hw_context, + req_ctx->hw_context_size); + export->swinit =3D req_ctx->swinit; + export->first_request =3D req_ctx->first_request; + export->last_request =3D req_ctx->last_request; + export->to_hash_later =3D req_ctx->to_hash_later; + export->message_size =3D req_ctx->message_size; + + return 0; +} + +static int ahash_import(struct ahash_request *areq, const void *in) +{ + struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); + struct talitos_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct device *dev =3D ctx->dev; + const struct talitos_export_state *export =3D in; + unsigned int size; + dma_addr_t dma; + + memset(req_ctx, 0, sizeof(*req_ctx)); + size =3D (crypto_ahash_digestsize(tfm) <=3D SHA256_DIGEST_SIZE) + ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 + : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512; + req_ctx->hw_context_size =3D size; + memcpy(req_ctx->hw_context, export->hw_context, size); + req_ctx->swinit =3D export->swinit; + req_ctx->first_request =3D export->first_request; + req_ctx->last_request =3D export->last_request; + req_ctx->to_hash_later =3D export->to_hash_later; + req_ctx->message_size =3D export->message_size; + + dma =3D dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size, + DMA_TO_DEVICE); + dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_TO_DEVICE); + + return 0; +} + +static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int k= eylen, + u8 *hash) +{ + struct talitos_ctx *ctx =3D crypto_tfm_ctx(crypto_ahash_tfm(tfm)); + + struct scatterlist sg[1]; + struct ahash_request *req; + struct crypto_wait wait; + int ret; + + crypto_init_wait(&wait); + + req =3D ahash_request_alloc(tfm, GFP_KERNEL); + if (!req) + return -ENOMEM; + + /* Keep tfm keylen =3D=3D 0 during hash of the long key */ + ctx->keylen =3D 0; + ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, + crypto_req_done, &wait); + + sg_init_one(&sg[0], key, keylen); + + ahash_request_set_crypt(req, sg, hash, keylen); + ret =3D crypto_wait_req(crypto_ahash_digest(req), &wait); + + ahash_request_free(req); + + return ret; +} + +static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key, + unsigned int keylen) +{ + struct talitos_ctx *ctx =3D crypto_tfm_ctx(crypto_ahash_tfm(tfm)); + struct device *dev =3D ctx->dev; + unsigned int blocksize =3D + crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); + unsigned int digestsize =3D crypto_ahash_digestsize(tfm); + unsigned int keysize =3D keylen; + u8 hash[SHA512_DIGEST_SIZE]; + int ret; + + if (keylen <=3D blocksize) + memcpy(ctx->key, key, keysize); + else { + /* Must get the hash of the long key */ + ret =3D keyhash(tfm, key, keylen, hash); + + if (ret) + return -EINVAL; + + keysize =3D digestsize; + memcpy(ctx->key, hash, digestsize); + } + + if (ctx->keylen) + dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE); + + ctx->keylen =3D keysize; + ctx->dma_key =3D dma_map_single(dev, ctx->key, keysize, DMA_TO_DEVICE); + + return 0; +} + +static int talitos_cra_init_ahash(struct crypto_tfm *tfm) +{ + struct crypto_alg *alg =3D tfm->__crt_alg; + struct talitos_crypto_alg *talitos_alg; + struct talitos_ctx *ctx =3D crypto_tfm_ctx(tfm); + + talitos_alg =3D container_of(__crypto_ahash_alg(alg), + struct talitos_crypto_alg, + algt.alg.hash); + + ctx->keylen =3D 0; + + return talitos_init_common(ctx, talitos_alg); +} + +static const struct talitos_alg_template hash_driver_algs[] =3D { + { .type =3D CRYPTO_ALG_TYPE_AHASH, + .alg.hash =3D { + .halg.digestsize =3D MD5_DIGEST_SIZE, + .halg.statesize =3D sizeof(struct talitos_export_state), + .halg.base =3D { + .cra_name =3D "md5", + .cra_driver_name =3D "md5-talitos", + .cra_blocksize =3D MD5_HMAC_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, + } + }, + .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUA | + DESC_HDR_MODE0_MDEU_MD5, + }, + { .type =3D CRYPTO_ALG_TYPE_AHASH, + .alg.hash =3D { + .halg.digestsize =3D SHA1_DIGEST_SIZE, + .halg.statesize =3D sizeof(struct talitos_export_state), + .halg.base =3D { + .cra_name =3D "sha1", + .cra_driver_name =3D "sha1-talitos", + .cra_blocksize =3D SHA1_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, + } + }, + .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUA | + DESC_HDR_MODE0_MDEU_SHA1, + }, + { .type =3D CRYPTO_ALG_TYPE_AHASH, + .alg.hash =3D { + .halg.digestsize =3D SHA224_DIGEST_SIZE, + .halg.statesize =3D sizeof(struct talitos_export_state), + .halg.base =3D { + .cra_name =3D "sha224", + .cra_driver_name =3D "sha224-talitos", + .cra_blocksize =3D SHA224_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, + } + }, + .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUA | + DESC_HDR_MODE0_MDEU_SHA224, + }, + { .type =3D CRYPTO_ALG_TYPE_AHASH, + .alg.hash =3D { + .halg.digestsize =3D SHA256_DIGEST_SIZE, + .halg.statesize =3D sizeof(struct talitos_export_state), + .halg.base =3D { + .cra_name =3D "sha256", + .cra_driver_name =3D "sha256-talitos", + .cra_blocksize =3D SHA256_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, + } + }, + .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUA | + DESC_HDR_MODE0_MDEU_SHA256, + }, + { .type =3D CRYPTO_ALG_TYPE_AHASH, + .alg.hash =3D { + .halg.digestsize =3D SHA384_DIGEST_SIZE, + .halg.statesize =3D sizeof(struct talitos_export_state), + .halg.base =3D { + .cra_name =3D "sha384", + .cra_driver_name =3D "sha384-talitos", + .cra_blocksize =3D SHA384_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, + } + }, + .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUB | + DESC_HDR_MODE0_MDEUB_SHA384, + }, + { .type =3D CRYPTO_ALG_TYPE_AHASH, + .alg.hash =3D { + .halg.digestsize =3D SHA512_DIGEST_SIZE, + .halg.statesize =3D sizeof(struct talitos_export_state), + .halg.base =3D { + .cra_name =3D "sha512", + .cra_driver_name =3D "sha512-talitos", + .cra_blocksize =3D SHA512_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, + } + }, + .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUB | + DESC_HDR_MODE0_MDEUB_SHA512, + }, + { .type =3D CRYPTO_ALG_TYPE_AHASH, + .alg.hash =3D { + .halg.digestsize =3D MD5_DIGEST_SIZE, + .halg.statesize =3D sizeof(struct talitos_export_state), + .halg.base =3D { + .cra_name =3D "hmac(md5)", + .cra_driver_name =3D "hmac-md5-talitos", + .cra_blocksize =3D MD5_HMAC_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, + } + }, + .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUA | + DESC_HDR_MODE0_MDEU_MD5, + }, + { .type =3D CRYPTO_ALG_TYPE_AHASH, + .alg.hash =3D { + .halg.digestsize =3D SHA1_DIGEST_SIZE, + .halg.statesize =3D sizeof(struct talitos_export_state), + .halg.base =3D { + .cra_name =3D "hmac(sha1)", + .cra_driver_name =3D "hmac-sha1-talitos", + .cra_blocksize =3D SHA1_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, + } + }, + .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUA | + DESC_HDR_MODE0_MDEU_SHA1, + }, + { .type =3D CRYPTO_ALG_TYPE_AHASH, + .alg.hash =3D { + .halg.digestsize =3D SHA224_DIGEST_SIZE, + .halg.statesize =3D sizeof(struct talitos_export_state), + .halg.base =3D { + .cra_name =3D "hmac(sha224)", + .cra_driver_name =3D "hmac-sha224-talitos", + .cra_blocksize =3D SHA224_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, + } + }, + .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUA | + DESC_HDR_MODE0_MDEU_SHA224, + }, + { .type =3D CRYPTO_ALG_TYPE_AHASH, + .alg.hash =3D { + .halg.digestsize =3D SHA256_DIGEST_SIZE, + .halg.statesize =3D sizeof(struct talitos_export_state), + .halg.base =3D { + .cra_name =3D "hmac(sha256)", + .cra_driver_name =3D "hmac-sha256-talitos", + .cra_blocksize =3D SHA256_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, + } + }, + .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUA | + DESC_HDR_MODE0_MDEU_SHA256, + }, + { .type =3D CRYPTO_ALG_TYPE_AHASH, + .alg.hash =3D { + .halg.digestsize =3D SHA384_DIGEST_SIZE, + .halg.statesize =3D sizeof(struct talitos_export_state), + .halg.base =3D { + .cra_name =3D "hmac(sha384)", + .cra_driver_name =3D "hmac-sha384-talitos", + .cra_blocksize =3D SHA384_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, + } + }, + .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUB | + DESC_HDR_MODE0_MDEUB_SHA384, + }, + { .type =3D CRYPTO_ALG_TYPE_AHASH, + .alg.hash =3D { + .halg.digestsize =3D SHA512_DIGEST_SIZE, + .halg.statesize =3D sizeof(struct talitos_export_state), + .halg.base =3D { + .cra_name =3D "hmac(sha512)", + .cra_driver_name =3D "hmac-sha512-talitos", + .cra_blocksize =3D SHA512_BLOCK_SIZE, + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY, + } + }, + .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUB | + DESC_HDR_MODE0_MDEUB_SHA512, + } +}; + +int talitos_register_hash(struct device *dev) +{ + struct talitos_private *priv =3D dev_get_drvdata(dev); + struct talitos_alg_template talitos_alg_template; + struct ahash_alg *ahash_alg; + struct crypto_alg *alg; + size_t i; + int ret; + + for (i =3D 0; i < ARRAY_SIZE(hash_driver_algs); i++) { + if (!talitos_hw_supports(dev, + hash_driver_algs[i].desc_hdr_template)) + continue; + + talitos_alg_template =3D hash_driver_algs[i]; + + ahash_alg =3D &talitos_alg_template.alg.hash; + alg =3D &ahash_alg->halg.base; + + alg->cra_init =3D talitos_cra_init_ahash; + alg->cra_exit =3D talitos_cra_exit; + ahash_alg->init =3D ahash_init; + ahash_alg->update =3D ahash_update; + ahash_alg->final =3D ahash_final; + ahash_alg->finup =3D ahash_finup; + ahash_alg->digest =3D ahash_digest; + if (!strncmp(alg->cra_name, "hmac", 4)) + ahash_alg->setkey =3D ahash_setkey; + ahash_alg->import =3D ahash_import; + ahash_alg->export =3D ahash_export; + + if (!(priv->features & TALITOS_FTR_HMAC_OK) && + !strncmp(alg->cra_name, "hmac", 4)) { + /* not supported */ + continue; + } + + if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) && + (!strcmp(alg->cra_name, "sha224") || + !strcmp(alg->cra_name, "hmac(sha224)"))) { + ahash_alg->init =3D ahash_init_sha224_swinit; + ahash_alg->digest =3D ahash_digest_sha224_swinit; + talitos_alg_template.desc_hdr_template =3D + DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUA | + DESC_HDR_MODE0_MDEU_SHA256; + } + + ret =3D talitos_register_common(dev, &talitos_alg_template); + if (ret) + return ret; + } + + return 0; +} diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/tali= tos.h index 24b4d541df2c..99584157837a 100644 --- a/drivers/crypto/talitos/talitos.h +++ b/drivers/crypto/talitos/talitos.h @@ -599,7 +599,14 @@ int talitos_init_common(struct talitos_ctx *ctx, struct talitos_crypto_alg *talitos_alg); void talitos_cra_exit(struct crypto_tfm *tfm); =20 +int talitos_register_common(struct device *dev, + struct talitos_alg_template *template); + /* Hardware RNG */ =20 int talitos_register_rng(struct device *dev); void talitos_unregister_rng(struct device *dev); + +/* Hash */ + +int talitos_register_hash(struct device *dev); --=20 2.55.0 From nobody Thu Sep 24 13:42:19 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net 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into separate file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-7-3-rc2_talitos_cleanup-v7-7-9a45261fc097@bootlin.com> References: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> In-Reply-To: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> To: Herbert Xu , "David S. Miller" Cc: Paul Louvel , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Christophe Leroy , "Christophe Leroy (CS GROUP)" X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790176746; l=28597; i=paul.louvel@bootlin.com; s=20260313; h=from:subject:message-id; bh=mNoAXjqCS8/+Nu+w+Ry/tnNz4HoslajvNeaQVi/+Q60=; b=Hkf6Z4L1gKpm5OGgWPmjUFpIkqemCFAnLFrpx2KXGGmIqe6TJJRovGYy0EhbIlpTEnQ2KYiAm UNLoe2RzxiAA5iz+AUyabvHI+6w5DGqDsaifh/+Gqyoj6do5st+DUOc X-Developer-Key: i=paul.louvel@bootlin.com; a=ed25519; pk=eLW50NT18UAvUT5cAcYf88zNbBCZDLFXuptpyLVhVIU= X-Last-TLS-Session-Version: TLSv1.3 Move the skcipher algorithm implementations from talitos.c into a dedicated talitos-skcipher.c file. Reviewed-by: Christophe Leroy (CS GROUP) Signed-off-by: Paul Louvel --- drivers/crypto/talitos/Makefile | 2 +- drivers/crypto/talitos/talitos-core.c | 377 +-------------------------= -- drivers/crypto/talitos/talitos-skcipher.c | 402 ++++++++++++++++++++++++++= ++++ drivers/crypto/talitos/talitos.h | 1 + 4 files changed, 414 insertions(+), 368 deletions(-) diff --git a/drivers/crypto/talitos/Makefile b/drivers/crypto/talitos/Makef= ile index 2a0e93614f2b..3319cdbce7e9 100644 --- a/drivers/crypto/talitos/Makefile +++ b/drivers/crypto/talitos/Makefile @@ -1,3 +1,3 @@ obj-$(CONFIG_CRYPTO_DEV_TALITOS) +=3D talitos.o =20 -talitos-y +=3D talitos-core.o talitos-rng.o talitos-hash.o +talitos-y +=3D talitos-core.o talitos-rng.o talitos-hash.o talitos-skciphe= r.o diff --git a/drivers/crypto/talitos/talitos-core.c b/drivers/crypto/talitos= /talitos-core.c index 25265d8dd9b4..7de4f384558d 100644 --- a/drivers/crypto/talitos/talitos-core.c +++ b/drivers/crypto/talitos/talitos-core.c @@ -1339,215 +1339,6 @@ static int aead_decrypt(struct aead_request *req) return ipsec_esp(edesc, req, false, ipsec_esp_decrypt_swauth_done); } =20 -static int skcipher_setkey(struct crypto_skcipher *cipher, - const u8 *key, unsigned int keylen) -{ - struct talitos_ctx *ctx =3D crypto_skcipher_ctx(cipher); - struct device *dev =3D ctx->dev; - - if (ctx->keylen) - dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE); - - memcpy(&ctx->key, key, keylen); - ctx->keylen =3D keylen; - - ctx->dma_key =3D dma_map_single(dev, ctx->key, keylen, DMA_TO_DEVICE); - - return 0; -} - -static int skcipher_des_setkey(struct crypto_skcipher *cipher, - const u8 *key, unsigned int keylen) -{ - return verify_skcipher_des_key(cipher, key) ?: - skcipher_setkey(cipher, key, keylen); -} - -static int skcipher_des3_setkey(struct crypto_skcipher *cipher, - const u8 *key, unsigned int keylen) -{ - return verify_skcipher_des3_key(cipher, key) ?: - skcipher_setkey(cipher, key, keylen); -} - -static int skcipher_aes_setkey(struct crypto_skcipher *cipher, - const u8 *key, unsigned int keylen) -{ - if (keylen =3D=3D AES_KEYSIZE_128 || keylen =3D=3D AES_KEYSIZE_192 || - keylen =3D=3D AES_KEYSIZE_256) - return skcipher_setkey(cipher, key, keylen); - - return -EINVAL; -} - -static void common_nonsnoop_unmap(struct device *dev, - struct talitos_edesc *edesc, - struct skcipher_request *areq) -{ - unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE); - - talitos_sg_unmap(dev, edesc, areq->src, areq->dst, areq->cryptlen, 0); - unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE); - - if (edesc->dma_len) - dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len, - DMA_BIDIRECTIONAL); -} - -static void skcipher_done(struct device *dev, - struct talitos_desc *desc, void *context, - int err) -{ - struct skcipher_request *areq =3D context; - struct crypto_skcipher *cipher =3D crypto_skcipher_reqtfm(areq); - struct talitos_ctx *ctx =3D crypto_skcipher_ctx(cipher); - unsigned int ivsize =3D crypto_skcipher_ivsize(cipher); - struct talitos_edesc *edesc; - - edesc =3D container_of(desc, struct talitos_edesc, desc); - - common_nonsnoop_unmap(dev, edesc, areq); - memcpy(areq->iv, ctx->iv, ivsize); - - kfree(edesc); - - skcipher_request_complete(areq, err); -} - -static int common_nonsnoop(struct talitos_edesc *edesc, - struct skcipher_request *areq, - void (*callback) (struct device *dev, - struct talitos_desc *desc, - void *context, int error)) -{ - struct crypto_skcipher *cipher =3D crypto_skcipher_reqtfm(areq); - struct talitos_ctx *ctx =3D crypto_skcipher_ctx(cipher); - struct device *dev =3D ctx->dev; - struct talitos_desc *desc =3D &edesc->desc; - unsigned int cryptlen =3D areq->cryptlen; - unsigned int ivsize =3D crypto_skcipher_ivsize(cipher); - int sg_count, ret; - bool sync_needed =3D false; - struct talitos_private *priv =3D dev_get_drvdata(dev); - bool is_sec1 =3D has_ftr_sec1(priv); - bool is_ctr =3D (desc->hdr & DESC_HDR_SEL0_MASK) =3D=3D DESC_HDR_SEL0_AES= U && - (desc->hdr & DESC_HDR_MODE0_AESU_MASK) =3D=3D DESC_HDR_MODE0_AESU_= CTR; - - /* first DWORD empty */ - - /* cipher iv */ - to_talitos_ptr(&desc->ptr[1], edesc->iv_dma, ivsize, is_sec1); - - /* cipher key */ - to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen, is_sec1); - - sg_count =3D edesc->src_nents ?: 1; - if (is_sec1 && sg_count > 1) - sg_copy_to_buffer(areq->src, sg_count, edesc->buf, - cryptlen); - else - sg_count =3D dma_map_sg(dev, areq->src, sg_count, - (areq->src =3D=3D areq->dst) ? - DMA_BIDIRECTIONAL : DMA_TO_DEVICE); - /* - * cipher in - */ - sg_count =3D talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->p= tr[3], - sg_count, 0, 0, 0, false, is_ctr ? 16 : 1); - if (sg_count > 1) - sync_needed =3D true; - - /* cipher out */ - if (areq->src !=3D areq->dst) { - sg_count =3D edesc->dst_nents ? : 1; - if (!is_sec1 || sg_count =3D=3D 1) - dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE); - } - - ret =3D talitos_sg_map(dev, areq->dst, cryptlen, edesc, &desc->ptr[4], - sg_count, 0, (edesc->src_nents + 1)); - if (ret > 1) - sync_needed =3D true; - - /* iv out */ - map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, - DMA_FROM_DEVICE); - - /* last DWORD empty */ - - if (sync_needed) - dma_sync_single_for_device(dev, edesc->dma_link_tbl, - edesc->dma_len, DMA_BIDIRECTIONAL); - - ret =3D talitos_submit(dev, ctx->ch, desc, callback, areq); - if (ret !=3D -EINPROGRESS) { - common_nonsnoop_unmap(dev, edesc, areq); - kfree(edesc); - } - return ret; -} - -static struct talitos_edesc *skcipher_edesc_alloc(struct skcipher_request * - areq, bool encrypt) -{ - struct crypto_skcipher *cipher =3D crypto_skcipher_reqtfm(areq); - struct talitos_ctx *ctx =3D crypto_skcipher_ctx(cipher); - unsigned int ivsize =3D crypto_skcipher_ivsize(cipher); - - return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, - areq->iv, 0, areq->cryptlen, 0, ivsize, 0, - areq->base.flags, encrypt); -} - -static int skcipher_encrypt(struct skcipher_request *areq) -{ - struct crypto_skcipher *cipher =3D crypto_skcipher_reqtfm(areq); - struct talitos_ctx *ctx =3D crypto_skcipher_ctx(cipher); - struct talitos_edesc *edesc; - unsigned int blocksize =3D - crypto_tfm_alg_blocksize(crypto_skcipher_tfm(cipher)); - - if (!areq->cryptlen) - return 0; - - if (areq->cryptlen % blocksize) - return -EINVAL; - - /* allocate extended descriptor */ - edesc =3D skcipher_edesc_alloc(areq, true); - if (IS_ERR(edesc)) - return PTR_ERR(edesc); - - /* set encrypt */ - edesc->desc.hdr =3D ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT; - - return common_nonsnoop(edesc, areq, skcipher_done); -} - -static int skcipher_decrypt(struct skcipher_request *areq) -{ - struct crypto_skcipher *cipher =3D crypto_skcipher_reqtfm(areq); - struct talitos_ctx *ctx =3D crypto_skcipher_ctx(cipher); - struct talitos_edesc *edesc; - unsigned int blocksize =3D - crypto_tfm_alg_blocksize(crypto_skcipher_tfm(cipher)); - - if (!areq->cryptlen) - return 0; - - if (areq->cryptlen % blocksize) - return -EINVAL; - - /* allocate extended descriptor */ - edesc =3D skcipher_edesc_alloc(areq, false); - if (IS_ERR(edesc)) - return PTR_ERR(edesc); - - edesc->desc.hdr =3D ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND; - - return common_nonsnoop(edesc, areq, skcipher_done); -} - static struct talitos_alg_template driver_algs[] =3D { /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */ { .type =3D CRYPTO_ALG_TYPE_AEAD, @@ -2006,131 +1797,6 @@ static struct talitos_alg_template driver_algs[] = =3D { DESC_HDR_MODE1_MDEU_PAD | DESC_HDR_MODE1_MDEU_MD5_HMAC, }, - /* SKCIPHER algorithms. */ - { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, - .alg.skcipher =3D { - .base.cra_name =3D "ecb(aes)", - .base.cra_driver_name =3D "ecb-aes-talitos", - .base.cra_blocksize =3D AES_BLOCK_SIZE, - .base.cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - .min_keysize =3D AES_MIN_KEY_SIZE, - .max_keysize =3D AES_MAX_KEY_SIZE, - .setkey =3D skcipher_aes_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_AESU, - }, - { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, - .alg.skcipher =3D { - .base.cra_name =3D "cbc(aes)", - .base.cra_driver_name =3D "cbc-aes-talitos", - .base.cra_blocksize =3D AES_BLOCK_SIZE, - .base.cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - .min_keysize =3D AES_MIN_KEY_SIZE, - .max_keysize =3D AES_MAX_KEY_SIZE, - .ivsize =3D AES_BLOCK_SIZE, - .setkey =3D skcipher_aes_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC, - }, - { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, - .alg.skcipher =3D { - .base.cra_name =3D "ctr(aes)", - .base.cra_driver_name =3D "ctr-aes-talitos", - .base.cra_blocksize =3D 1, - .base.cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - .min_keysize =3D AES_MIN_KEY_SIZE, - .max_keysize =3D AES_MAX_KEY_SIZE, - .ivsize =3D AES_BLOCK_SIZE, - .setkey =3D skcipher_aes_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_AESU_CTR_NONSNOOP | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CTR, - }, - { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, - .alg.skcipher =3D { - .base.cra_name =3D "ctr(aes)", - .base.cra_driver_name =3D "ctr-aes-talitos", - .base.cra_blocksize =3D 1, - .base.cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - .min_keysize =3D AES_MIN_KEY_SIZE, - .max_keysize =3D AES_MAX_KEY_SIZE, - .ivsize =3D AES_BLOCK_SIZE, - .setkey =3D skcipher_aes_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CTR, - }, - { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, - .alg.skcipher =3D { - .base.cra_name =3D "ecb(des)", - .base.cra_driver_name =3D "ecb-des-talitos", - .base.cra_blocksize =3D DES_BLOCK_SIZE, - .base.cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - .min_keysize =3D DES_KEY_SIZE, - .max_keysize =3D DES_KEY_SIZE, - .setkey =3D skcipher_des_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_DEU, - }, - { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, - .alg.skcipher =3D { - .base.cra_name =3D "cbc(des)", - .base.cra_driver_name =3D "cbc-des-talitos", - .base.cra_blocksize =3D DES_BLOCK_SIZE, - .base.cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - .min_keysize =3D DES_KEY_SIZE, - .max_keysize =3D DES_KEY_SIZE, - .ivsize =3D DES_BLOCK_SIZE, - .setkey =3D skcipher_des_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC, - }, - { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, - .alg.skcipher =3D { - .base.cra_name =3D "ecb(des3_ede)", - .base.cra_driver_name =3D "ecb-3des-talitos", - .base.cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .base.cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - .min_keysize =3D DES3_EDE_KEY_SIZE, - .max_keysize =3D DES3_EDE_KEY_SIZE, - .setkey =3D skcipher_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_3DES, - }, - { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, - .alg.skcipher =3D { - .base.cra_name =3D "cbc(des3_ede)", - .base.cra_driver_name =3D "cbc-3des-talitos", - .base.cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .base.cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - .min_keysize =3D DES3_EDE_KEY_SIZE, - .max_keysize =3D DES3_EDE_KEY_SIZE, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .setkey =3D skcipher_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES, - }, }; =20 int talitos_init_common(struct talitos_ctx *ctx, @@ -2167,18 +1833,6 @@ static int talitos_cra_init_aead(struct crypto_aead = *tfm) return talitos_init_common(ctx, talitos_alg); } =20 -static int talitos_cra_init_skcipher(struct crypto_skcipher *tfm) -{ - struct skcipher_alg *alg =3D crypto_skcipher_alg(tfm); - struct talitos_crypto_alg *talitos_alg; - struct talitos_ctx *ctx =3D crypto_skcipher_ctx(tfm); - - talitos_alg =3D container_of(alg, struct talitos_crypto_alg, - algt.alg.skcipher); - - return talitos_init_common(ctx, talitos_alg); -} - void talitos_cra_exit(struct crypto_tfm *tfm) { struct talitos_ctx *ctx =3D crypto_tfm_ctx(tfm); @@ -2282,6 +1936,12 @@ int talitos_register_common(struct device *dev, t_alg->algt.type); ret =3D crypto_register_ahash(&t_alg->algt.alg.hash); break; + case CRYPTO_ALG_TYPE_SKCIPHER: + alg =3D &t_alg->algt.alg.skcipher.base; + talitos_alg_set_common(priv, alg, t_alg->algt.priority, + t_alg->algt.type); + ret =3D crypto_register_skcipher(&t_alg->algt.alg.skcipher); + break; default: dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type); devm_kfree(dev, t_alg); @@ -2316,21 +1976,6 @@ static struct talitos_crypto_alg *talitos_alg_alloc(= struct device *dev, t_alg->algt =3D *template; =20 switch (t_alg->algt.type) { - case CRYPTO_ALG_TYPE_SKCIPHER: - alg =3D &t_alg->algt.alg.skcipher.base; - alg->cra_exit =3D talitos_cra_exit; - t_alg->algt.alg.skcipher.init =3D talitos_cra_init_skcipher; - t_alg->algt.alg.skcipher.setkey =3D - t_alg->algt.alg.skcipher.setkey ?: skcipher_setkey; - t_alg->algt.alg.skcipher.encrypt =3D skcipher_encrypt; - t_alg->algt.alg.skcipher.decrypt =3D skcipher_decrypt; - if (!strcmp(alg->cra_name, "ctr(aes)") && !has_ftr_sec1(priv) && - DESC_TYPE(t_alg->algt.desc_hdr_template) !=3D - DESC_TYPE(DESC_HDR_TYPE_AESU_CTR_NONSNOOP)) { - devm_kfree(dev, t_alg); - return ERR_PTR(-ENOTSUPP); - } - break; case CRYPTO_ALG_TYPE_AEAD: alg =3D &t_alg->algt.alg.aead.base; alg->cra_exit =3D talitos_cra_exit; @@ -2575,6 +2220,10 @@ static int talitos_probe(struct platform_device *ofd= ev) if (err) goto err_out; =20 + err =3D talitos_register_skcipher(dev); + if (err) + goto err_out; + /* register crypto algorithms the device supports */ for (i =3D 0; i < ARRAY_SIZE(driver_algs); i++) { if (talitos_hw_supports(dev, @@ -2591,12 +2240,6 @@ static int talitos_probe(struct platform_device *ofd= ev) } =20 switch (t_alg->algt.type) { - case CRYPTO_ALG_TYPE_SKCIPHER: - err =3D crypto_register_skcipher( - &t_alg->algt.alg.skcipher); - alg =3D &t_alg->algt.alg.skcipher.base; - break; - case CRYPTO_ALG_TYPE_AEAD: err =3D crypto_register_aead( &t_alg->algt.alg.aead); diff --git a/drivers/crypto/talitos/talitos-skcipher.c b/drivers/crypto/tal= itos/talitos-skcipher.c new file mode 100644 index 000000000000..e4e8bebdfb7b --- /dev/null +++ b/drivers/crypto/talitos/talitos-skcipher.c @@ -0,0 +1,402 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/* + * Freescale SEC (talitos) skcipher implementation + * + * Copyright (c) 2006-2011 Freescale Semiconductor, Inc. + */ + +#include +#include + +#include "talitos.h" + +static void common_nonsnoop_unmap(struct device *dev, + struct talitos_edesc *edesc, + struct skcipher_request *areq) +{ + unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE); + + talitos_sg_unmap(dev, edesc, areq->src, areq->dst, areq->cryptlen, 0); + unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE); + + if (edesc->dma_len) + dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len, + DMA_BIDIRECTIONAL); +} + +static void skcipher_done(struct device *dev, + struct talitos_desc *desc, void *context, + int err) +{ + struct skcipher_request *areq =3D context; + struct crypto_skcipher *cipher =3D crypto_skcipher_reqtfm(areq); + struct talitos_ctx *ctx =3D crypto_skcipher_ctx(cipher); + unsigned int ivsize =3D crypto_skcipher_ivsize(cipher); + struct talitos_edesc *edesc; + + edesc =3D container_of(desc, struct talitos_edesc, desc); + + common_nonsnoop_unmap(dev, edesc, areq); + memcpy(areq->iv, ctx->iv, ivsize); + + kfree(edesc); + + skcipher_request_complete(areq, err); +} + +static int common_nonsnoop(struct talitos_edesc *edesc, + struct skcipher_request *areq, + void (*callback) (struct device *dev, + struct talitos_desc *desc, + void *context, int error)) +{ + struct crypto_skcipher *cipher =3D crypto_skcipher_reqtfm(areq); + struct talitos_ctx *ctx =3D crypto_skcipher_ctx(cipher); + struct device *dev =3D ctx->dev; + struct talitos_desc *desc =3D &edesc->desc; + unsigned int cryptlen =3D areq->cryptlen; + unsigned int ivsize =3D crypto_skcipher_ivsize(cipher); + int sg_count, ret; + bool sync_needed =3D false; + struct talitos_private *priv =3D dev_get_drvdata(dev); + bool is_sec1 =3D has_ftr_sec1(priv); + bool is_ctr =3D (desc->hdr & DESC_HDR_SEL0_MASK) =3D=3D DESC_HDR_SEL0_AES= U && + (desc->hdr & DESC_HDR_MODE0_AESU_MASK) =3D=3D DESC_HDR_MODE0_AESU_= CTR; + + /* first DWORD empty */ + + /* cipher iv */ + to_talitos_ptr(&desc->ptr[1], edesc->iv_dma, ivsize, is_sec1); + + /* cipher key */ + to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen, is_sec1); + + sg_count =3D edesc->src_nents ?: 1; + if (is_sec1 && sg_count > 1) + sg_copy_to_buffer(areq->src, sg_count, edesc->buf, + cryptlen); + else + sg_count =3D dma_map_sg(dev, areq->src, sg_count, + (areq->src =3D=3D areq->dst) ? + DMA_BIDIRECTIONAL : DMA_TO_DEVICE); + /* + * cipher in + */ + sg_count =3D talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->p= tr[3], + sg_count, 0, 0, 0, false, is_ctr ? 16 : 1); + if (sg_count > 1) + sync_needed =3D true; + + /* cipher out */ + if (areq->src !=3D areq->dst) { + sg_count =3D edesc->dst_nents ? : 1; + if (!is_sec1 || sg_count =3D=3D 1) + dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE); + } + + ret =3D talitos_sg_map(dev, areq->dst, cryptlen, edesc, &desc->ptr[4], + sg_count, 0, (edesc->src_nents + 1)); + if (ret > 1) + sync_needed =3D true; + + /* iv out */ + map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, + DMA_FROM_DEVICE); + + /* last DWORD empty */ + + if (sync_needed) + dma_sync_single_for_device(dev, edesc->dma_link_tbl, + edesc->dma_len, DMA_BIDIRECTIONAL); + + ret =3D talitos_submit(dev, ctx->ch, desc, callback, areq); + if (ret !=3D -EINPROGRESS) { + common_nonsnoop_unmap(dev, edesc, areq); + kfree(edesc); + } + return ret; +} + +static int skcipher_setkey(struct crypto_skcipher *cipher, + const u8 *key, unsigned int keylen) +{ + struct talitos_ctx *ctx =3D crypto_skcipher_ctx(cipher); + struct device *dev =3D ctx->dev; + + if (ctx->keylen) + dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE); + + memcpy(&ctx->key, key, keylen); + ctx->keylen =3D keylen; + + ctx->dma_key =3D dma_map_single(dev, ctx->key, keylen, DMA_TO_DEVICE); + + return 0; +} + +static int skcipher_des_setkey(struct crypto_skcipher *cipher, + const u8 *key, unsigned int keylen) +{ + return verify_skcipher_des_key(cipher, key) ?: + skcipher_setkey(cipher, key, keylen); +} + +static int skcipher_des3_setkey(struct crypto_skcipher *cipher, + const u8 *key, unsigned int keylen) +{ + return verify_skcipher_des3_key(cipher, key) ?: + skcipher_setkey(cipher, key, keylen); +} + +static int skcipher_aes_setkey(struct crypto_skcipher *cipher, + const u8 *key, unsigned int keylen) +{ + if (keylen =3D=3D AES_KEYSIZE_128 || keylen =3D=3D AES_KEYSIZE_192 || + keylen =3D=3D AES_KEYSIZE_256) + return skcipher_setkey(cipher, key, keylen); + + return -EINVAL; +} + +static struct talitos_edesc *skcipher_edesc_alloc(struct skcipher_request * + areq, bool encrypt) +{ + struct crypto_skcipher *cipher =3D crypto_skcipher_reqtfm(areq); + struct talitos_ctx *ctx =3D crypto_skcipher_ctx(cipher); + unsigned int ivsize =3D crypto_skcipher_ivsize(cipher); + + return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, + areq->iv, 0, areq->cryptlen, 0, ivsize, 0, + areq->base.flags, encrypt); +} + +static int skcipher_encrypt(struct skcipher_request *areq) +{ + struct crypto_skcipher *cipher =3D crypto_skcipher_reqtfm(areq); + struct talitos_ctx *ctx =3D crypto_skcipher_ctx(cipher); + struct talitos_edesc *edesc; + unsigned int blocksize =3D + crypto_tfm_alg_blocksize(crypto_skcipher_tfm(cipher)); + + if (!areq->cryptlen) + return 0; + + if (areq->cryptlen % blocksize) + return -EINVAL; + + /* allocate extended descriptor */ + edesc =3D skcipher_edesc_alloc(areq, true); + if (IS_ERR(edesc)) + return PTR_ERR(edesc); + + /* set encrypt */ + edesc->desc.hdr =3D ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT; + + return common_nonsnoop(edesc, areq, skcipher_done); +} + +static int skcipher_decrypt(struct skcipher_request *areq) +{ + struct crypto_skcipher *cipher =3D crypto_skcipher_reqtfm(areq); + struct talitos_ctx *ctx =3D crypto_skcipher_ctx(cipher); + struct talitos_edesc *edesc; + unsigned int blocksize =3D + crypto_tfm_alg_blocksize(crypto_skcipher_tfm(cipher)); + + if (!areq->cryptlen) + return 0; + + if (areq->cryptlen % blocksize) + return -EINVAL; + + /* allocate extended descriptor */ + edesc =3D skcipher_edesc_alloc(areq, false); + if (IS_ERR(edesc)) + return PTR_ERR(edesc); + + edesc->desc.hdr =3D ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND; + + return common_nonsnoop(edesc, areq, skcipher_done); +} + +static int talitos_cra_init_skcipher(struct crypto_skcipher *tfm) +{ + struct skcipher_alg *alg =3D crypto_skcipher_alg(tfm); + struct talitos_crypto_alg *talitos_alg; + struct talitos_ctx *ctx =3D crypto_skcipher_ctx(tfm); + + talitos_alg =3D container_of(alg, struct talitos_crypto_alg, + algt.alg.skcipher); + + return talitos_init_common(ctx, talitos_alg); +} + +static const struct talitos_alg_template skcipher_driver_algs[] =3D { + { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, + .alg.skcipher =3D { + .base.cra_name =3D "ecb(aes)", + .base.cra_driver_name =3D "ecb-aes-talitos", + .base.cra_blocksize =3D AES_BLOCK_SIZE, + .base.cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + .min_keysize =3D AES_MIN_KEY_SIZE, + .max_keysize =3D AES_MAX_KEY_SIZE, + .setkey =3D skcipher_aes_setkey, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_AESU, + }, + { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, + .alg.skcipher =3D { + .base.cra_name =3D "cbc(aes)", + .base.cra_driver_name =3D "cbc-aes-talitos", + .base.cra_blocksize =3D AES_BLOCK_SIZE, + .base.cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + .min_keysize =3D AES_MIN_KEY_SIZE, + .max_keysize =3D AES_MAX_KEY_SIZE, + .ivsize =3D AES_BLOCK_SIZE, + .setkey =3D skcipher_aes_setkey, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC, + }, + { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, + .alg.skcipher =3D { + .base.cra_name =3D "ctr(aes)", + .base.cra_driver_name =3D "ctr-aes-talitos", + .base.cra_blocksize =3D 1, + .base.cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + .min_keysize =3D AES_MIN_KEY_SIZE, + .max_keysize =3D AES_MAX_KEY_SIZE, + .ivsize =3D AES_BLOCK_SIZE, + .setkey =3D skcipher_aes_setkey, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_AESU_CTR_NONSNOOP | + DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CTR, + }, + { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, + .alg.skcipher =3D { + .base.cra_name =3D "ctr(aes)", + .base.cra_driver_name =3D "ctr-aes-talitos", + .base.cra_blocksize =3D 1, + .base.cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + .min_keysize =3D AES_MIN_KEY_SIZE, + .max_keysize =3D AES_MAX_KEY_SIZE, + .ivsize =3D AES_BLOCK_SIZE, + .setkey =3D skcipher_aes_setkey, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CTR, + }, + { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, + .alg.skcipher =3D { + .base.cra_name =3D "ecb(des)", + .base.cra_driver_name =3D "ecb-des-talitos", + .base.cra_blocksize =3D DES_BLOCK_SIZE, + .base.cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + .min_keysize =3D DES_KEY_SIZE, + .max_keysize =3D DES_KEY_SIZE, + .setkey =3D skcipher_des_setkey, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_DEU, + }, + { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, + .alg.skcipher =3D { + .base.cra_name =3D "cbc(des)", + .base.cra_driver_name =3D "cbc-des-talitos", + .base.cra_blocksize =3D DES_BLOCK_SIZE, + .base.cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + .min_keysize =3D DES_KEY_SIZE, + .max_keysize =3D DES_KEY_SIZE, + .ivsize =3D DES_BLOCK_SIZE, + .setkey =3D skcipher_des_setkey, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC, + }, + { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, + .alg.skcipher =3D { + .base.cra_name =3D "ecb(des3_ede)", + .base.cra_driver_name =3D "ecb-3des-talitos", + .base.cra_blocksize =3D DES3_EDE_BLOCK_SIZE, + .base.cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + .min_keysize =3D DES3_EDE_KEY_SIZE, + .max_keysize =3D DES3_EDE_KEY_SIZE, + .setkey =3D skcipher_des3_setkey, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_3DES, + }, + { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, + .alg.skcipher =3D { + .base.cra_name =3D "cbc(des3_ede)", + .base.cra_driver_name =3D "cbc-3des-talitos", + .base.cra_blocksize =3D DES3_EDE_BLOCK_SIZE, + .base.cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + .min_keysize =3D DES3_EDE_KEY_SIZE, + .max_keysize =3D DES3_EDE_KEY_SIZE, + .ivsize =3D DES3_EDE_BLOCK_SIZE, + .setkey =3D skcipher_des3_setkey, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | + DESC_HDR_MODE0_DEU_3DES, + }, +}; + +int talitos_register_skcipher(struct device *dev) +{ + struct talitos_private *priv =3D dev_get_drvdata(dev); + struct talitos_alg_template talitos_alg_template; + struct skcipher_alg *skcipher_alg; + struct crypto_alg *alg; + size_t i; + int ret; + + for (i =3D 0; i < ARRAY_SIZE(skcipher_driver_algs); i++) { + if (!talitos_hw_supports( + dev, skcipher_driver_algs[i].desc_hdr_template)) + continue; + + talitos_alg_template =3D skcipher_driver_algs[i]; + + skcipher_alg =3D &talitos_alg_template.alg.skcipher; + alg =3D &skcipher_alg->base; + + alg->cra_exit =3D talitos_cra_exit; + if (has_ftr_sec1(priv)) + alg->cra_alignmask =3D 3; + + skcipher_alg->init =3D talitos_cra_init_skcipher; + skcipher_alg->setkey =3D skcipher_alg->setkey ?: skcipher_setkey; + skcipher_alg->encrypt =3D skcipher_encrypt; + skcipher_alg->decrypt =3D skcipher_decrypt; + + if (!strcmp(alg->cra_name, "ctr(aes)") && !has_ftr_sec1(priv) && + DESC_TYPE(talitos_alg_template.desc_hdr_template) !=3D + DESC_TYPE(DESC_HDR_TYPE_AESU_CTR_NONSNOOP)) { + continue; + } + + ret =3D talitos_register_common(dev, &talitos_alg_template); + if (ret) + return ret; + } + + return 0; +} diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/tali= tos.h index 99584157837a..07cdd6034883 100644 --- a/drivers/crypto/talitos/talitos.h +++ b/drivers/crypto/talitos/talitos.h @@ -610,3 +610,4 @@ void talitos_unregister_rng(struct device *dev); /* Hash */ =20 int talitos_register_hash(struct device *dev); +int talitos_register_skcipher(struct device *dev); --=20 2.55.0 From nobody Thu Sep 24 13:42:19 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B1A4560ADD; Wed, 23 Sep 2026 15:19:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790176777; 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spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="fdhB/sgR" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 827644E41047; Wed, 23 Sep 2026 15:19:28 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 5057260580; Wed, 23 Sep 2026 15:19:28 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id CE2371032929E; Wed, 23 Sep 2026 17:19:26 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1790176767; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=olG4V13JXor+Foq1tUYqsYUvQ1DfJCpun7cZr0PWgjg=; b=fdhB/sgRa+lCzQfa7cvdECOz1i0KxlqviaiSfnoMlJjWGvSeqHpgZhXjAO+aAwVCAVI27v YqKwFsRF58UZ5Lp9Ou8QF/RylyhwurqP/5YnP9S/l7nJCg92LfAtQc/CHZyHgPuKRv3E5u +b6/TZM7uBe+ME/dGYKpStY2IyD/YfimAHDVlxo/ihmuCKcs8t6aHSLb8GS9Zns1V5UnlP 4f4KWAuVHDmbhEgLBeJ7YsMi8X71lmmpQIoQkdZLYmD3y/L+d9CRjHNnM4+ZoLnjLB8Djt KuOxAikenTajF4+ZP7GOarWYbOj1AfToPNujcBVgH1EmwJJoZ4RLE2ZDMkqWVg== From: Paul Louvel Date: Wed, 23 Sep 2026 17:18:44 +0200 Subject: [PATCH v7 08/20] crypto: talitos/aead - Move into separate file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-7-3-rc2_talitos_cleanup-v7-8-9a45261fc097@bootlin.com> References: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> In-Reply-To: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> To: Herbert Xu , "David S. Miller" Cc: Paul Louvel , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Christophe Leroy , "Christophe Leroy (CS GROUP)" X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790176746; l=63564; i=paul.louvel@bootlin.com; s=20260313; h=from:subject:message-id; bh=dVbIdLcdMK0WJaR++xPlsUzeCdRgir7RPuTmzznhzbU=; b=cOLBRF3+AIfbdf6s8RYxb7Lv3bC+2vZVtxBLDYedqukvfbBVf6lesuDjkE/luW9dQ3jJ64pkq hQwFQYRj362Bl1YkwtWQE8PXGnwRWNVuPQAge4smUe+f98e41ofukbS X-Developer-Key: i=paul.louvel@bootlin.com; a=ed25519; pk=eLW50NT18UAvUT5cAcYf88zNbBCZDLFXuptpyLVhVIU= X-Last-TLS-Session-Version: TLSv1.3 Move the AEAD algorithm implementations from talitos.c into a dedicated talitos-aead.c file. Reviewed-by: Christophe Leroy (CS GROUP) Signed-off-by: Paul Louvel --- drivers/crypto/talitos/Makefile | 2 +- drivers/crypto/talitos/talitos-aead.c | 900 ++++++++++++++++++++++++++++++= ++ drivers/crypto/talitos/talitos-core.c | 947 +-----------------------------= ---- drivers/crypto/talitos/talitos.h | 3 + 4 files changed, 913 insertions(+), 939 deletions(-) diff --git a/drivers/crypto/talitos/Makefile b/drivers/crypto/talitos/Makef= ile index 3319cdbce7e9..a85228cda189 100644 --- a/drivers/crypto/talitos/Makefile +++ b/drivers/crypto/talitos/Makefile @@ -1,3 +1,3 @@ obj-$(CONFIG_CRYPTO_DEV_TALITOS) +=3D talitos.o =20 -talitos-y +=3D talitos-core.o talitos-rng.o talitos-hash.o talitos-skciphe= r.o +talitos-y +=3D talitos-core.o talitos-rng.o talitos-hash.o talitos-skciphe= r.o talitos-aead.o diff --git a/drivers/crypto/talitos/talitos-aead.c b/drivers/crypto/talitos= /talitos-aead.c new file mode 100644 index 000000000000..0236f152743b --- /dev/null +++ b/drivers/crypto/talitos/talitos-aead.c @@ -0,0 +1,900 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include +#include +#include +#include +#include +#include + +#include "talitos.h" + +/* + * Defines a priority for doing AEAD with descriptors type + * HMAC_SNOOP_NO_AFEA (HSNA) instead of type IPSEC_ESP + */ +#define TALITOS_CRA_PRIORITY_AEAD_HSNA (TALITOS_CRA_PRIORITY - 1) + +static int aead_setkey(struct crypto_aead *authenc, + const u8 *key, unsigned int keylen) +{ + struct talitos_ctx *ctx =3D crypto_aead_ctx(authenc); + struct device *dev =3D ctx->dev; + struct crypto_authenc_keys keys; + + if (crypto_authenc_extractkeys(&keys, key, keylen) !=3D 0) + goto badkey; + + if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE) + goto badkey; + + if (ctx->keylen) + dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE); + + memcpy(ctx->key, keys.authkey, keys.authkeylen); + memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen); + + ctx->keylen =3D keys.authkeylen + keys.enckeylen; + ctx->enckeylen =3D keys.enckeylen; + ctx->authkeylen =3D keys.authkeylen; + ctx->dma_key =3D dma_map_single(dev, ctx->key, ctx->keylen, + DMA_TO_DEVICE); + + memzero_explicit(&keys, sizeof(keys)); + return 0; + +badkey: + memzero_explicit(&keys, sizeof(keys)); + return -EINVAL; +} + +static int aead_des3_setkey(struct crypto_aead *authenc, + const u8 *key, unsigned int keylen) +{ + struct talitos_ctx *ctx =3D crypto_aead_ctx(authenc); + struct device *dev =3D ctx->dev; + struct crypto_authenc_keys keys; + int err; + + err =3D crypto_authenc_extractkeys(&keys, key, keylen); + if (unlikely(err)) + goto out; + + err =3D -EINVAL; + if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE) + goto out; + + err =3D verify_aead_des3_key(authenc, keys.enckey, keys.enckeylen); + if (err) + goto out; + + if (ctx->keylen) + dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE); + + memcpy(ctx->key, keys.authkey, keys.authkeylen); + memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen); + + ctx->keylen =3D keys.authkeylen + keys.enckeylen; + ctx->enckeylen =3D keys.enckeylen; + ctx->authkeylen =3D keys.authkeylen; + ctx->dma_key =3D dma_map_single(dev, ctx->key, ctx->keylen, + DMA_TO_DEVICE); + +out: + memzero_explicit(&keys, sizeof(keys)); + return err; +} + +static void ipsec_esp_unmap(struct device *dev, + struct talitos_edesc *edesc, + struct aead_request *areq, bool encrypt) +{ + struct crypto_aead *aead =3D crypto_aead_reqtfm(areq); + struct talitos_ctx *ctx =3D crypto_aead_ctx(aead); + unsigned int ivsize =3D crypto_aead_ivsize(aead); + unsigned int authsize =3D crypto_aead_authsize(aead); + unsigned int cryptlen =3D areq->cryptlen - (encrypt ? 0 : authsize); + bool is_ipsec_esp =3D edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP; + struct talitos_ptr *civ_ptr =3D &edesc->desc.ptr[is_ipsec_esp ? 2 : 3]; + + if (is_ipsec_esp) + unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], + DMA_FROM_DEVICE); + unmap_single_talitos_ptr(dev, civ_ptr, DMA_TO_DEVICE); + + talitos_sg_unmap(dev, edesc, areq->src, areq->dst, + cryptlen + authsize, areq->assoclen); + + if (edesc->dma_len) + dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len, + DMA_BIDIRECTIONAL); + + if (!is_ipsec_esp) { + unsigned int dst_nents =3D edesc->dst_nents ? : 1; + + sg_pcopy_to_buffer(areq->dst, dst_nents, ctx->iv, ivsize, + areq->assoclen + cryptlen - ivsize); + } +} + +/* + * ipsec_esp descriptor callbacks + */ +static void ipsec_esp_encrypt_done(struct device *dev, + struct talitos_desc *desc, void *context, + int err) +{ + struct aead_request *areq =3D context; + struct crypto_aead *authenc =3D crypto_aead_reqtfm(areq); + unsigned int ivsize =3D crypto_aead_ivsize(authenc); + struct talitos_edesc *edesc; + + edesc =3D container_of(desc, struct talitos_edesc, desc); + + ipsec_esp_unmap(dev, edesc, areq, true); + + dma_unmap_single(dev, edesc->iv_dma, ivsize, DMA_TO_DEVICE); + + kfree(edesc); + + aead_request_complete(areq, err); +} + +static void ipsec_esp_decrypt_swauth_done(struct device *dev, + struct talitos_desc *desc, + void *context, int err) +{ + struct aead_request *req =3D context; + struct crypto_aead *authenc =3D crypto_aead_reqtfm(req); + unsigned int authsize =3D crypto_aead_authsize(authenc); + struct talitos_edesc *edesc; + char *oicv, *icv; + + edesc =3D container_of(desc, struct talitos_edesc, desc); + + ipsec_esp_unmap(dev, edesc, req, false); + + if (!err) { + /* auth check */ + oicv =3D edesc->buf + edesc->dma_len; + icv =3D oicv - authsize; + + err =3D crypto_memneq(oicv, icv, authsize) ? -EBADMSG : 0; + } + + kfree(edesc); + + aead_request_complete(req, err); +} + +static void ipsec_esp_decrypt_hwauth_done(struct device *dev, + struct talitos_desc *desc, + void *context, int err) +{ + struct aead_request *req =3D context; + struct talitos_edesc *edesc; + + edesc =3D container_of(desc, struct talitos_edesc, desc); + + ipsec_esp_unmap(dev, edesc, req, false); + + /* check ICV auth status */ + if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=3D + DESC_HDR_LO_ICCR1_PASS)) + err =3D -EBADMSG; + + kfree(edesc); + + aead_request_complete(req, err); +} + +/* + * fill in and submit ipsec_esp descriptor + */ +static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *are= q, + bool encrypt, + void (*callback)(struct device *dev, + struct talitos_desc *desc, + void *context, int error)) +{ + struct crypto_aead *aead =3D crypto_aead_reqtfm(areq); + unsigned int authsize =3D crypto_aead_authsize(aead); + struct talitos_ctx *ctx =3D crypto_aead_ctx(aead); + struct device *dev =3D ctx->dev; + struct talitos_desc *desc =3D &edesc->desc; + unsigned int cryptlen =3D areq->cryptlen - (encrypt ? 0 : authsize); + unsigned int ivsize =3D crypto_aead_ivsize(aead); + int tbl_off =3D 0; + int sg_count, ret; + int elen =3D 0; + bool sync_needed =3D false; + struct talitos_private *priv =3D dev_get_drvdata(dev); + bool is_sec1 =3D has_ftr_sec1(priv); + bool is_ipsec_esp =3D desc->hdr & DESC_HDR_TYPE_IPSEC_ESP; + struct talitos_ptr *civ_ptr =3D &desc->ptr[is_ipsec_esp ? 2 : 3]; + struct talitos_ptr *ckey_ptr =3D &desc->ptr[is_ipsec_esp ? 3 : 2]; + dma_addr_t dma_icv =3D edesc->dma_link_tbl + edesc->dma_len - authsize; + + /* hmac key */ + to_talitos_ptr(&desc->ptr[0], ctx->dma_key, ctx->authkeylen, is_sec1); + + sg_count =3D edesc->src_nents ?: 1; + if (is_sec1 && sg_count > 1) + sg_copy_to_buffer(areq->src, sg_count, edesc->buf, + areq->assoclen + cryptlen); + else + sg_count =3D dma_map_sg(dev, areq->src, sg_count, + (areq->src =3D=3D areq->dst) ? + DMA_BIDIRECTIONAL : DMA_TO_DEVICE); + + /* hmac data */ + ret =3D talitos_sg_map(dev, areq->src, areq->assoclen, edesc, + &desc->ptr[1], sg_count, 0, tbl_off); + + if (ret > 1) { + tbl_off +=3D ret; + sync_needed =3D true; + } + + /* cipher iv */ + to_talitos_ptr(civ_ptr, edesc->iv_dma, ivsize, is_sec1); + + /* cipher key */ + to_talitos_ptr(ckey_ptr, ctx->dma_key + ctx->authkeylen, + ctx->enckeylen, is_sec1); + + /* + * cipher in + * map and adjust cipher len to aead request cryptlen. + * extent is bytes of HMAC postpended to ciphertext, + * typically 12 for ipsec + */ + if (is_ipsec_esp && (desc->hdr & DESC_HDR_MODE1_MDEU_CICV)) + elen =3D authsize; + + ret =3D talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->ptr[4], + sg_count, areq->assoclen, tbl_off, elen, + false, 1); + + if (ret > 1) { + tbl_off +=3D ret; + sync_needed =3D true; + } + + /* cipher out */ + if (areq->src !=3D areq->dst) { + sg_count =3D edesc->dst_nents ? : 1; + if (!is_sec1 || sg_count =3D=3D 1) + dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE); + } + + if (is_ipsec_esp && encrypt) + elen =3D authsize; + else + elen =3D 0; + ret =3D talitos_sg_map_ext(dev, areq->dst, cryptlen, edesc, &desc->ptr[5], + sg_count, areq->assoclen, tbl_off, elen, + is_ipsec_esp && !encrypt, 1); + tbl_off +=3D ret; + + if (!encrypt && is_ipsec_esp) { + struct talitos_ptr *tbl_ptr =3D &edesc->link_tbl[tbl_off]; + + /* Add an entry to the link table for ICV data */ + to_talitos_ptr_ext_set(tbl_ptr - 1, 0, is_sec1); + to_talitos_ptr_ext_set(tbl_ptr, DESC_PTR_LNKTBL_RET, is_sec1); + + /* icv data follows link tables */ + to_talitos_ptr(tbl_ptr, dma_icv, authsize, is_sec1); + to_talitos_ptr_ext_or(&desc->ptr[5], authsize, is_sec1); + sync_needed =3D true; + } else if (!encrypt) { + to_talitos_ptr(&desc->ptr[6], dma_icv, authsize, is_sec1); + sync_needed =3D true; + } else if (!is_ipsec_esp) { + talitos_sg_map(dev, areq->dst, authsize, edesc, &desc->ptr[6], + sg_count, areq->assoclen + cryptlen, tbl_off); + } + + /* iv out */ + if (is_ipsec_esp) + map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, + DMA_FROM_DEVICE); + + if (sync_needed) + dma_sync_single_for_device(dev, edesc->dma_link_tbl, + edesc->dma_len, + DMA_BIDIRECTIONAL); + + ret =3D talitos_submit(dev, ctx->ch, desc, callback, areq); + if (ret !=3D -EINPROGRESS) { + ipsec_esp_unmap(dev, edesc, areq, encrypt); + kfree(edesc); + } + return ret; +} + +static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u= 8 *iv, + int icv_stashing, bool encrypt) +{ + struct crypto_aead *authenc =3D crypto_aead_reqtfm(areq); + unsigned int authsize =3D crypto_aead_authsize(authenc); + struct talitos_ctx *ctx =3D crypto_aead_ctx(authenc); + unsigned int ivsize =3D crypto_aead_ivsize(authenc); + unsigned int cryptlen =3D areq->cryptlen - (encrypt ? 0 : authsize); + + return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, + iv, areq->assoclen, cryptlen, + authsize, ivsize, icv_stashing, + areq->base.flags, encrypt); +} + +static int aead_encrypt(struct aead_request *req) +{ + struct crypto_aead *authenc =3D crypto_aead_reqtfm(req); + struct talitos_ctx *ctx =3D crypto_aead_ctx(authenc); + struct talitos_edesc *edesc; + + /* allocate extended descriptor */ + edesc =3D aead_edesc_alloc(req, req->iv, 0, true); + if (IS_ERR(edesc)) + return PTR_ERR(edesc); + + /* set encrypt */ + edesc->desc.hdr =3D ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT; + + return ipsec_esp(edesc, req, true, ipsec_esp_encrypt_done); +} + +static int aead_decrypt(struct aead_request *req) +{ + struct crypto_aead *authenc =3D crypto_aead_reqtfm(req); + unsigned int authsize =3D crypto_aead_authsize(authenc); + struct talitos_ctx *ctx =3D crypto_aead_ctx(authenc); + struct talitos_private *priv =3D dev_get_drvdata(ctx->dev); + struct talitos_edesc *edesc; + void *icvdata; + + /* allocate extended descriptor */ + edesc =3D aead_edesc_alloc(req, req->iv, 1, false); + if (IS_ERR(edesc)) + return PTR_ERR(edesc); + + if ((edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP) && + (priv->features & TALITOS_FTR_HW_AUTH_CHECK) && + ((!edesc->src_nents && !edesc->dst_nents) || + priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) { + + /* decrypt and check the ICV */ + edesc->desc.hdr =3D ctx->desc_hdr_template | + DESC_HDR_DIR_INBOUND | + DESC_HDR_MODE1_MDEU_CICV; + + /* reset integrity check result bits */ + + return ipsec_esp(edesc, req, false, + ipsec_esp_decrypt_hwauth_done); + } + + /* Have to check the ICV with software */ + edesc->desc.hdr =3D ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND; + + /* stash incoming ICV for later cmp with ICV generated by the h/w */ + icvdata =3D edesc->buf + edesc->dma_len; + + sg_pcopy_to_buffer(req->src, edesc->src_nents ? : 1, icvdata, authsize, + req->assoclen + req->cryptlen - authsize); + + return ipsec_esp(edesc, req, false, ipsec_esp_decrypt_swauth_done); +} + +static int talitos_cra_init_aead(struct crypto_aead *tfm) +{ + struct aead_alg *alg =3D crypto_aead_alg(tfm); + struct talitos_crypto_alg *talitos_alg; + struct talitos_ctx *ctx =3D crypto_aead_ctx(tfm); + + talitos_alg =3D container_of(alg, struct talitos_crypto_alg, + algt.alg.aead); + + return talitos_init_common(ctx, talitos_alg); +} + +static const struct talitos_alg_template aead_driver_algs[] =3D { + { .type =3D CRYPTO_ALG_TYPE_AEAD, + .alg.aead =3D { + .base =3D { + .cra_name =3D "authenc(hmac(sha1),cbc(aes))", + .cra_driver_name =3D "authenc-hmac-sha1-" + "cbc-aes-talitos", + .cra_blocksize =3D AES_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + }, + .ivsize =3D AES_BLOCK_SIZE, + .maxauthsize =3D SHA1_DIGEST_SIZE, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | + DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC | + DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA1_HMAC, + }, + { .type =3D CRYPTO_ALG_TYPE_AEAD, + .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, + .alg.aead =3D { + .base =3D { + .cra_name =3D "authenc(hmac(sha1),cbc(aes))", + .cra_driver_name =3D "authenc-hmac-sha1-" + "cbc-aes-talitos-hsna", + .cra_blocksize =3D AES_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + }, + .ivsize =3D AES_BLOCK_SIZE, + .maxauthsize =3D SHA1_DIGEST_SIZE, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | + DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC | + DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA1_HMAC, + }, + { .type =3D CRYPTO_ALG_TYPE_AEAD, + .alg.aead =3D { + .base =3D { + .cra_name =3D "authenc(hmac(sha1)," + "cbc(des3_ede))", + .cra_driver_name =3D "authenc-hmac-sha1-" + "cbc-3des-talitos", + .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + }, + .ivsize =3D DES3_EDE_BLOCK_SIZE, + .maxauthsize =3D SHA1_DIGEST_SIZE, + .setkey =3D aead_des3_setkey, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | + DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | + DESC_HDR_MODE0_DEU_3DES | + DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA1_HMAC, + }, + { .type =3D CRYPTO_ALG_TYPE_AEAD, + .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, + .alg.aead =3D { + .base =3D { + .cra_name =3D "authenc(hmac(sha1)," + "cbc(des3_ede))", + .cra_driver_name =3D "authenc-hmac-sha1-" + "cbc-3des-talitos-hsna", + .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + }, + .ivsize =3D DES3_EDE_BLOCK_SIZE, + .maxauthsize =3D SHA1_DIGEST_SIZE, + .setkey =3D aead_des3_setkey, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | + DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | + DESC_HDR_MODE0_DEU_3DES | + DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA1_HMAC, + }, + { .type =3D CRYPTO_ALG_TYPE_AEAD, + .alg.aead =3D { + .base =3D { + .cra_name =3D "authenc(hmac(sha224),cbc(aes))", + .cra_driver_name =3D "authenc-hmac-sha224-" + "cbc-aes-talitos", + .cra_blocksize =3D AES_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + }, + .ivsize =3D AES_BLOCK_SIZE, + .maxauthsize =3D SHA224_DIGEST_SIZE, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | + DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC | + DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA224_HMAC, + }, + { .type =3D CRYPTO_ALG_TYPE_AEAD, + .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, + .alg.aead =3D { + .base =3D { + .cra_name =3D "authenc(hmac(sha224),cbc(aes))", + .cra_driver_name =3D "authenc-hmac-sha224-" + "cbc-aes-talitos-hsna", + .cra_blocksize =3D AES_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + }, + .ivsize =3D AES_BLOCK_SIZE, + .maxauthsize =3D SHA224_DIGEST_SIZE, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | + DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC | + DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA224_HMAC, + }, + { .type =3D CRYPTO_ALG_TYPE_AEAD, + .alg.aead =3D { + .base =3D { + .cra_name =3D "authenc(hmac(sha224)," + "cbc(des3_ede))", + .cra_driver_name =3D "authenc-hmac-sha224-" + "cbc-3des-talitos", + .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + }, + .ivsize =3D DES3_EDE_BLOCK_SIZE, + .maxauthsize =3D SHA224_DIGEST_SIZE, + .setkey =3D aead_des3_setkey, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | + DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | + DESC_HDR_MODE0_DEU_3DES | + DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA224_HMAC, + }, + { .type =3D CRYPTO_ALG_TYPE_AEAD, + .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, + .alg.aead =3D { + .base =3D { + .cra_name =3D "authenc(hmac(sha224)," + "cbc(des3_ede))", + .cra_driver_name =3D "authenc-hmac-sha224-" + "cbc-3des-talitos-hsna", + .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + }, + .ivsize =3D DES3_EDE_BLOCK_SIZE, + .maxauthsize =3D SHA224_DIGEST_SIZE, + .setkey =3D aead_des3_setkey, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | + DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | + DESC_HDR_MODE0_DEU_3DES | + DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA224_HMAC, + }, + { .type =3D CRYPTO_ALG_TYPE_AEAD, + .alg.aead =3D { + .base =3D { + .cra_name =3D "authenc(hmac(sha256),cbc(aes))", + .cra_driver_name =3D "authenc-hmac-sha256-" + "cbc-aes-talitos", + .cra_blocksize =3D AES_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + }, + .ivsize =3D AES_BLOCK_SIZE, + .maxauthsize =3D SHA256_DIGEST_SIZE, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | + DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC | + DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA256_HMAC, + }, + { .type =3D CRYPTO_ALG_TYPE_AEAD, + .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, + .alg.aead =3D { + .base =3D { + .cra_name =3D "authenc(hmac(sha256),cbc(aes))", + .cra_driver_name =3D "authenc-hmac-sha256-" + "cbc-aes-talitos-hsna", + .cra_blocksize =3D AES_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + }, + .ivsize =3D AES_BLOCK_SIZE, + .maxauthsize =3D SHA256_DIGEST_SIZE, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | + DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC | + DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA256_HMAC, + }, + { .type =3D CRYPTO_ALG_TYPE_AEAD, + .alg.aead =3D { + .base =3D { + .cra_name =3D "authenc(hmac(sha256)," + "cbc(des3_ede))", + .cra_driver_name =3D "authenc-hmac-sha256-" + "cbc-3des-talitos", + .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + }, + .ivsize =3D DES3_EDE_BLOCK_SIZE, + .maxauthsize =3D SHA256_DIGEST_SIZE, + .setkey =3D aead_des3_setkey, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | + DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | + DESC_HDR_MODE0_DEU_3DES | + DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA256_HMAC, + }, + { .type =3D CRYPTO_ALG_TYPE_AEAD, + .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, + .alg.aead =3D { + .base =3D { + .cra_name =3D "authenc(hmac(sha256)," + "cbc(des3_ede))", + .cra_driver_name =3D "authenc-hmac-sha256-" + "cbc-3des-talitos-hsna", + .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + }, + .ivsize =3D DES3_EDE_BLOCK_SIZE, + .maxauthsize =3D SHA256_DIGEST_SIZE, + .setkey =3D aead_des3_setkey, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | + DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | + DESC_HDR_MODE0_DEU_3DES | + DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA256_HMAC, + }, + { .type =3D CRYPTO_ALG_TYPE_AEAD, + .alg.aead =3D { + .base =3D { + .cra_name =3D "authenc(hmac(sha384),cbc(aes))", + .cra_driver_name =3D "authenc-hmac-sha384-" + "cbc-aes-talitos", + .cra_blocksize =3D AES_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + }, + .ivsize =3D AES_BLOCK_SIZE, + .maxauthsize =3D SHA384_DIGEST_SIZE, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | + DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC | + DESC_HDR_SEL1_MDEUB | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEUB_SHA384_HMAC, + }, + { .type =3D CRYPTO_ALG_TYPE_AEAD, + .alg.aead =3D { + .base =3D { + .cra_name =3D "authenc(hmac(sha384)," + "cbc(des3_ede))", + .cra_driver_name =3D "authenc-hmac-sha384-" + "cbc-3des-talitos", + .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + }, + .ivsize =3D DES3_EDE_BLOCK_SIZE, + .maxauthsize =3D SHA384_DIGEST_SIZE, + .setkey =3D aead_des3_setkey, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | + DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | + DESC_HDR_MODE0_DEU_3DES | + DESC_HDR_SEL1_MDEUB | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEUB_SHA384_HMAC, + }, + { .type =3D CRYPTO_ALG_TYPE_AEAD, + .alg.aead =3D { + .base =3D { + .cra_name =3D "authenc(hmac(sha512),cbc(aes))", + .cra_driver_name =3D "authenc-hmac-sha512-" + "cbc-aes-talitos", + .cra_blocksize =3D AES_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + }, + .ivsize =3D AES_BLOCK_SIZE, + .maxauthsize =3D SHA512_DIGEST_SIZE, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | + DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC | + DESC_HDR_SEL1_MDEUB | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEUB_SHA512_HMAC, + }, + { .type =3D CRYPTO_ALG_TYPE_AEAD, + .alg.aead =3D { + .base =3D { + .cra_name =3D "authenc(hmac(sha512)," + "cbc(des3_ede))", + .cra_driver_name =3D "authenc-hmac-sha512-" + "cbc-3des-talitos", + .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + }, + .ivsize =3D DES3_EDE_BLOCK_SIZE, + .maxauthsize =3D SHA512_DIGEST_SIZE, + .setkey =3D aead_des3_setkey, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | + DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | + DESC_HDR_MODE0_DEU_3DES | + DESC_HDR_SEL1_MDEUB | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEUB_SHA512_HMAC, + }, + { .type =3D CRYPTO_ALG_TYPE_AEAD, + .alg.aead =3D { + .base =3D { + .cra_name =3D "authenc(hmac(md5),cbc(aes))", + .cra_driver_name =3D "authenc-hmac-md5-" + "cbc-aes-talitos", + .cra_blocksize =3D AES_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + }, + .ivsize =3D AES_BLOCK_SIZE, + .maxauthsize =3D MD5_DIGEST_SIZE, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | + DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC | + DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_MD5_HMAC, + }, + { .type =3D CRYPTO_ALG_TYPE_AEAD, + .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, + .alg.aead =3D { + .base =3D { + .cra_name =3D "authenc(hmac(md5),cbc(aes))", + .cra_driver_name =3D "authenc-hmac-md5-" + "cbc-aes-talitos-hsna", + .cra_blocksize =3D AES_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + }, + .ivsize =3D AES_BLOCK_SIZE, + .maxauthsize =3D MD5_DIGEST_SIZE, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | + DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC | + DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_MD5_HMAC, + }, + { .type =3D CRYPTO_ALG_TYPE_AEAD, + .alg.aead =3D { + .base =3D { + .cra_name =3D "authenc(hmac(md5),cbc(des3_ede))", + .cra_driver_name =3D "authenc-hmac-md5-" + "cbc-3des-talitos", + .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + }, + .ivsize =3D DES3_EDE_BLOCK_SIZE, + .maxauthsize =3D MD5_DIGEST_SIZE, + .setkey =3D aead_des3_setkey, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | + DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | + DESC_HDR_MODE0_DEU_3DES | + DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_MD5_HMAC, + }, + { .type =3D CRYPTO_ALG_TYPE_AEAD, + .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, + .alg.aead =3D { + .base =3D { + .cra_name =3D "authenc(hmac(md5),cbc(des3_ede))", + .cra_driver_name =3D "authenc-hmac-md5-" + "cbc-3des-talitos-hsna", + .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_ALLOCATES_MEMORY, + }, + .ivsize =3D DES3_EDE_BLOCK_SIZE, + .maxauthsize =3D MD5_DIGEST_SIZE, + .setkey =3D aead_des3_setkey, + }, + .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | + DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | + DESC_HDR_MODE0_DEU_3DES | + DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_MD5_HMAC, + }, +}; + +int talitos_register_aead(struct device *dev) +{ + struct talitos_private *priv =3D dev_get_drvdata(dev); + struct talitos_alg_template talitos_alg_template; + struct aead_alg *aead_alg; + struct crypto_alg *alg; + size_t i; + int ret; + + for (i =3D 0; i < ARRAY_SIZE(aead_driver_algs); i++) { + if (!talitos_hw_supports(dev, + aead_driver_algs[i].desc_hdr_template)) + continue; + + talitos_alg_template =3D aead_driver_algs[i]; + + aead_alg =3D &talitos_alg_template.alg.aead; + alg =3D &aead_alg->base; + + alg->cra_exit =3D talitos_cra_exit; + if (has_ftr_sec1(priv)) + alg->cra_alignmask =3D 3; + + aead_alg->init =3D talitos_cra_init_aead; + aead_alg->setkey =3D aead_alg->setkey ?: aead_setkey; + aead_alg->encrypt =3D aead_encrypt; + aead_alg->decrypt =3D aead_decrypt; + if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) && + !strncmp(alg->cra_name, "authenc(hmac(sha224)", 20)) { + continue; + } + + ret =3D talitos_register_common(dev, &talitos_alg_template); + if (ret) + return ret; + } + + return 0; +} diff --git a/drivers/crypto/talitos/talitos-core.c b/drivers/crypto/talitos= /talitos-core.c index 7de4f384558d..85ce77dbc329 100644 --- a/drivers/crypto/talitos/talitos-core.c +++ b/drivers/crypto/talitos/talitos-core.c @@ -729,87 +729,6 @@ DEF_TALITOS2_INTERRUPT(ch0_2, TALITOS2_ISR_CH_0_2_DONE= , TALITOS2_ISR_CH_0_2_ERR, DEF_TALITOS2_INTERRUPT(ch1_3, TALITOS2_ISR_CH_1_3_DONE, TALITOS2_ISR_CH_1_= 3_ERR, 1) =20 - -/* - * crypto alg - */ -#define TALITOS_CRA_PRIORITY 3000 -/* - * Defines a priority for doing AEAD with descriptors type - * HMAC_SNOOP_NO_AFEA (HSNA) instead of type IPSEC_ESP - */ -#define TALITOS_CRA_PRIORITY_AEAD_HSNA (TALITOS_CRA_PRIORITY - 1) - -static int aead_setkey(struct crypto_aead *authenc, - const u8 *key, unsigned int keylen) -{ - struct talitos_ctx *ctx =3D crypto_aead_ctx(authenc); - struct device *dev =3D ctx->dev; - struct crypto_authenc_keys keys; - - if (crypto_authenc_extractkeys(&keys, key, keylen) !=3D 0) - goto badkey; - - if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE) - goto badkey; - - if (ctx->keylen) - dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE); - - memcpy(ctx->key, keys.authkey, keys.authkeylen); - memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen); - - ctx->keylen =3D keys.authkeylen + keys.enckeylen; - ctx->enckeylen =3D keys.enckeylen; - ctx->authkeylen =3D keys.authkeylen; - ctx->dma_key =3D dma_map_single(dev, ctx->key, ctx->keylen, - DMA_TO_DEVICE); - - memzero_explicit(&keys, sizeof(keys)); - return 0; - -badkey: - memzero_explicit(&keys, sizeof(keys)); - return -EINVAL; -} - -static int aead_des3_setkey(struct crypto_aead *authenc, - const u8 *key, unsigned int keylen) -{ - struct talitos_ctx *ctx =3D crypto_aead_ctx(authenc); - struct device *dev =3D ctx->dev; - struct crypto_authenc_keys keys; - int err; - - err =3D crypto_authenc_extractkeys(&keys, key, keylen); - if (unlikely(err)) - goto out; - - err =3D -EINVAL; - if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE) - goto out; - - err =3D verify_aead_des3_key(authenc, keys.enckey, keys.enckeylen); - if (err) - goto out; - - if (ctx->keylen) - dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE); - - memcpy(ctx->key, keys.authkey, keys.authkeylen); - memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen); - - ctx->keylen =3D keys.authkeylen + keys.enckeylen; - ctx->enckeylen =3D keys.enckeylen; - ctx->authkeylen =3D keys.authkeylen; - ctx->dma_key =3D dma_map_single(dev, ctx->key, ctx->keylen, - DMA_TO_DEVICE); - -out: - memzero_explicit(&keys, sizeof(keys)); - return err; -} - void talitos_sg_unmap(struct device *dev, struct talitos_edesc *edesc, struct scatterlist *src, @@ -838,109 +757,6 @@ void talitos_sg_unmap(struct device *dev, } } =20 -static void ipsec_esp_unmap(struct device *dev, - struct talitos_edesc *edesc, - struct aead_request *areq, bool encrypt) -{ - struct crypto_aead *aead =3D crypto_aead_reqtfm(areq); - struct talitos_ctx *ctx =3D crypto_aead_ctx(aead); - unsigned int ivsize =3D crypto_aead_ivsize(aead); - unsigned int authsize =3D crypto_aead_authsize(aead); - unsigned int cryptlen =3D areq->cryptlen - (encrypt ? 0 : authsize); - bool is_ipsec_esp =3D edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP; - struct talitos_ptr *civ_ptr =3D &edesc->desc.ptr[is_ipsec_esp ? 2 : 3]; - - if (is_ipsec_esp) - unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], - DMA_FROM_DEVICE); - unmap_single_talitos_ptr(dev, civ_ptr, DMA_TO_DEVICE); - - talitos_sg_unmap(dev, edesc, areq->src, areq->dst, - cryptlen + authsize, areq->assoclen); - - if (edesc->dma_len) - dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len, - DMA_BIDIRECTIONAL); - - if (!is_ipsec_esp) { - unsigned int dst_nents =3D edesc->dst_nents ? : 1; - - sg_pcopy_to_buffer(areq->dst, dst_nents, ctx->iv, ivsize, - areq->assoclen + cryptlen - ivsize); - } -} - -/* - * ipsec_esp descriptor callbacks - */ -static void ipsec_esp_encrypt_done(struct device *dev, - struct talitos_desc *desc, void *context, - int err) -{ - struct aead_request *areq =3D context; - struct crypto_aead *authenc =3D crypto_aead_reqtfm(areq); - unsigned int ivsize =3D crypto_aead_ivsize(authenc); - struct talitos_edesc *edesc; - - edesc =3D container_of(desc, struct talitos_edesc, desc); - - ipsec_esp_unmap(dev, edesc, areq, true); - - dma_unmap_single(dev, edesc->iv_dma, ivsize, DMA_TO_DEVICE); - - kfree(edesc); - - aead_request_complete(areq, err); -} - -static void ipsec_esp_decrypt_swauth_done(struct device *dev, - struct talitos_desc *desc, - void *context, int err) -{ - struct aead_request *req =3D context; - struct crypto_aead *authenc =3D crypto_aead_reqtfm(req); - unsigned int authsize =3D crypto_aead_authsize(authenc); - struct talitos_edesc *edesc; - char *oicv, *icv; - - edesc =3D container_of(desc, struct talitos_edesc, desc); - - ipsec_esp_unmap(dev, edesc, req, false); - - if (!err) { - /* auth check */ - oicv =3D edesc->buf + edesc->dma_len; - icv =3D oicv - authsize; - - err =3D crypto_memneq(oicv, icv, authsize) ? -EBADMSG : 0; - } - - kfree(edesc); - - aead_request_complete(req, err); -} - -static void ipsec_esp_decrypt_hwauth_done(struct device *dev, - struct talitos_desc *desc, - void *context, int err) -{ - struct aead_request *req =3D context; - struct talitos_edesc *edesc; - - edesc =3D container_of(desc, struct talitos_edesc, desc); - - ipsec_esp_unmap(dev, edesc, req, false); - - /* check ICV auth status */ - if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=3D - DESC_HDR_LO_ICCR1_PASS)) - err =3D -EBADMSG; - - kfree(edesc); - - aead_request_complete(req, err); -} - /* * convert scatterlist to SEC h/w link table format * stop at cryptlen bytes @@ -1041,132 +857,6 @@ int talitos_sg_map(struct device *dev, struct scatte= rlist *src, tbl_off, 0, false, 1); } =20 -/* - * fill in and submit ipsec_esp descriptor - */ -static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *are= q, - bool encrypt, - void (*callback)(struct device *dev, - struct talitos_desc *desc, - void *context, int error)) -{ - struct crypto_aead *aead =3D crypto_aead_reqtfm(areq); - unsigned int authsize =3D crypto_aead_authsize(aead); - struct talitos_ctx *ctx =3D crypto_aead_ctx(aead); - struct device *dev =3D ctx->dev; - struct talitos_desc *desc =3D &edesc->desc; - unsigned int cryptlen =3D areq->cryptlen - (encrypt ? 0 : authsize); - unsigned int ivsize =3D crypto_aead_ivsize(aead); - int tbl_off =3D 0; - int sg_count, ret; - int elen =3D 0; - bool sync_needed =3D false; - struct talitos_private *priv =3D dev_get_drvdata(dev); - bool is_sec1 =3D has_ftr_sec1(priv); - bool is_ipsec_esp =3D desc->hdr & DESC_HDR_TYPE_IPSEC_ESP; - struct talitos_ptr *civ_ptr =3D &desc->ptr[is_ipsec_esp ? 2 : 3]; - struct talitos_ptr *ckey_ptr =3D &desc->ptr[is_ipsec_esp ? 3 : 2]; - dma_addr_t dma_icv =3D edesc->dma_link_tbl + edesc->dma_len - authsize; - - /* hmac key */ - to_talitos_ptr(&desc->ptr[0], ctx->dma_key, ctx->authkeylen, is_sec1); - - sg_count =3D edesc->src_nents ?: 1; - if (is_sec1 && sg_count > 1) - sg_copy_to_buffer(areq->src, sg_count, edesc->buf, - areq->assoclen + cryptlen); - else - sg_count =3D dma_map_sg(dev, areq->src, sg_count, - (areq->src =3D=3D areq->dst) ? - DMA_BIDIRECTIONAL : DMA_TO_DEVICE); - - /* hmac data */ - ret =3D talitos_sg_map(dev, areq->src, areq->assoclen, edesc, - &desc->ptr[1], sg_count, 0, tbl_off); - - if (ret > 1) { - tbl_off +=3D ret; - sync_needed =3D true; - } - - /* cipher iv */ - to_talitos_ptr(civ_ptr, edesc->iv_dma, ivsize, is_sec1); - - /* cipher key */ - to_talitos_ptr(ckey_ptr, ctx->dma_key + ctx->authkeylen, - ctx->enckeylen, is_sec1); - - /* - * cipher in - * map and adjust cipher len to aead request cryptlen. - * extent is bytes of HMAC postpended to ciphertext, - * typically 12 for ipsec - */ - if (is_ipsec_esp && (desc->hdr & DESC_HDR_MODE1_MDEU_CICV)) - elen =3D authsize; - - ret =3D talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->ptr[4], - sg_count, areq->assoclen, tbl_off, elen, - false, 1); - - if (ret > 1) { - tbl_off +=3D ret; - sync_needed =3D true; - } - - /* cipher out */ - if (areq->src !=3D areq->dst) { - sg_count =3D edesc->dst_nents ? : 1; - if (!is_sec1 || sg_count =3D=3D 1) - dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE); - } - - if (is_ipsec_esp && encrypt) - elen =3D authsize; - else - elen =3D 0; - ret =3D talitos_sg_map_ext(dev, areq->dst, cryptlen, edesc, &desc->ptr[5], - sg_count, areq->assoclen, tbl_off, elen, - is_ipsec_esp && !encrypt, 1); - tbl_off +=3D ret; - - if (!encrypt && is_ipsec_esp) { - struct talitos_ptr *tbl_ptr =3D &edesc->link_tbl[tbl_off]; - - /* Add an entry to the link table for ICV data */ - to_talitos_ptr_ext_set(tbl_ptr - 1, 0, is_sec1); - to_talitos_ptr_ext_set(tbl_ptr, DESC_PTR_LNKTBL_RET, is_sec1); - - /* icv data follows link tables */ - to_talitos_ptr(tbl_ptr, dma_icv, authsize, is_sec1); - to_talitos_ptr_ext_or(&desc->ptr[5], authsize, is_sec1); - sync_needed =3D true; - } else if (!encrypt) { - to_talitos_ptr(&desc->ptr[6], dma_icv, authsize, is_sec1); - sync_needed =3D true; - } else if (!is_ipsec_esp) { - talitos_sg_map(dev, areq->dst, authsize, edesc, &desc->ptr[6], - sg_count, areq->assoclen + cryptlen, tbl_off); - } - - /* iv out */ - if (is_ipsec_esp) - map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, - DMA_FROM_DEVICE); - - if (sync_needed) - dma_sync_single_for_device(dev, edesc->dma_link_tbl, - edesc->dma_len, - DMA_BIDIRECTIONAL); - - ret =3D talitos_submit(dev, ctx->ch, desc, callback, areq); - if (ret !=3D -EINPROGRESS) { - ipsec_esp_unmap(dev, edesc, areq, encrypt); - kfree(edesc); - } - return ret; -} - /* * allocate and map the extended descriptor */ @@ -1265,540 +955,6 @@ struct talitos_edesc *talitos_edesc_alloc(struct dev= ice *dev, return edesc; } =20 -static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u= 8 *iv, - int icv_stashing, bool encrypt) -{ - struct crypto_aead *authenc =3D crypto_aead_reqtfm(areq); - unsigned int authsize =3D crypto_aead_authsize(authenc); - struct talitos_ctx *ctx =3D crypto_aead_ctx(authenc); - unsigned int ivsize =3D crypto_aead_ivsize(authenc); - unsigned int cryptlen =3D areq->cryptlen - (encrypt ? 0 : authsize); - - return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, - iv, areq->assoclen, cryptlen, - authsize, ivsize, icv_stashing, - areq->base.flags, encrypt); -} - -static int aead_encrypt(struct aead_request *req) -{ - struct crypto_aead *authenc =3D crypto_aead_reqtfm(req); - struct talitos_ctx *ctx =3D crypto_aead_ctx(authenc); - struct talitos_edesc *edesc; - - /* allocate extended descriptor */ - edesc =3D aead_edesc_alloc(req, req->iv, 0, true); - if (IS_ERR(edesc)) - return PTR_ERR(edesc); - - /* set encrypt */ - edesc->desc.hdr =3D ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT; - - return ipsec_esp(edesc, req, true, ipsec_esp_encrypt_done); -} - -static int aead_decrypt(struct aead_request *req) -{ - struct crypto_aead *authenc =3D crypto_aead_reqtfm(req); - unsigned int authsize =3D crypto_aead_authsize(authenc); - struct talitos_ctx *ctx =3D crypto_aead_ctx(authenc); - struct talitos_private *priv =3D dev_get_drvdata(ctx->dev); - struct talitos_edesc *edesc; - void *icvdata; - - /* allocate extended descriptor */ - edesc =3D aead_edesc_alloc(req, req->iv, 1, false); - if (IS_ERR(edesc)) - return PTR_ERR(edesc); - - if ((edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP) && - (priv->features & TALITOS_FTR_HW_AUTH_CHECK) && - ((!edesc->src_nents && !edesc->dst_nents) || - priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) { - - /* decrypt and check the ICV */ - edesc->desc.hdr =3D ctx->desc_hdr_template | - DESC_HDR_DIR_INBOUND | - DESC_HDR_MODE1_MDEU_CICV; - - /* reset integrity check result bits */ - - return ipsec_esp(edesc, req, false, - ipsec_esp_decrypt_hwauth_done); - } - - /* Have to check the ICV with software */ - edesc->desc.hdr =3D ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND; - - /* stash incoming ICV for later cmp with ICV generated by the h/w */ - icvdata =3D edesc->buf + edesc->dma_len; - - sg_pcopy_to_buffer(req->src, edesc->src_nents ? : 1, icvdata, authsize, - req->assoclen + req->cryptlen - authsize); - - return ipsec_esp(edesc, req, false, ipsec_esp_decrypt_swauth_done); -} - -static struct talitos_alg_template driver_algs[] =3D { - /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */ - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha1),cbc(aes))", - .cra_driver_name =3D "authenc-hmac-sha1-" - "cbc-aes-talitos", - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D AES_BLOCK_SIZE, - .maxauthsize =3D SHA1_DIGEST_SIZE, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA1_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha1),cbc(aes))", - .cra_driver_name =3D "authenc-hmac-sha1-" - "cbc-aes-talitos-hsna", - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D AES_BLOCK_SIZE, - .maxauthsize =3D SHA1_DIGEST_SIZE, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA1_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha1)," - "cbc(des3_ede))", - .cra_driver_name =3D "authenc-hmac-sha1-" - "cbc-3des-talitos", - .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .maxauthsize =3D SHA1_DIGEST_SIZE, - .setkey =3D aead_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA1_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha1)," - "cbc(des3_ede))", - .cra_driver_name =3D "authenc-hmac-sha1-" - "cbc-3des-talitos-hsna", - .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .maxauthsize =3D SHA1_DIGEST_SIZE, - .setkey =3D aead_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA1_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha224),cbc(aes))", - .cra_driver_name =3D "authenc-hmac-sha224-" - "cbc-aes-talitos", - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D AES_BLOCK_SIZE, - .maxauthsize =3D SHA224_DIGEST_SIZE, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA224_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha224),cbc(aes))", - .cra_driver_name =3D "authenc-hmac-sha224-" - "cbc-aes-talitos-hsna", - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D AES_BLOCK_SIZE, - .maxauthsize =3D SHA224_DIGEST_SIZE, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA224_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha224)," - "cbc(des3_ede))", - .cra_driver_name =3D "authenc-hmac-sha224-" - "cbc-3des-talitos", - .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .maxauthsize =3D SHA224_DIGEST_SIZE, - .setkey =3D aead_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA224_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha224)," - "cbc(des3_ede))", - .cra_driver_name =3D "authenc-hmac-sha224-" - "cbc-3des-talitos-hsna", - .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .maxauthsize =3D SHA224_DIGEST_SIZE, - .setkey =3D aead_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA224_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha256),cbc(aes))", - .cra_driver_name =3D "authenc-hmac-sha256-" - "cbc-aes-talitos", - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D AES_BLOCK_SIZE, - .maxauthsize =3D SHA256_DIGEST_SIZE, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA256_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha256),cbc(aes))", - .cra_driver_name =3D "authenc-hmac-sha256-" - "cbc-aes-talitos-hsna", - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D AES_BLOCK_SIZE, - .maxauthsize =3D SHA256_DIGEST_SIZE, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA256_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha256)," - "cbc(des3_ede))", - .cra_driver_name =3D "authenc-hmac-sha256-" - "cbc-3des-talitos", - .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .maxauthsize =3D SHA256_DIGEST_SIZE, - .setkey =3D aead_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA256_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha256)," - "cbc(des3_ede))", - .cra_driver_name =3D "authenc-hmac-sha256-" - "cbc-3des-talitos-hsna", - .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .maxauthsize =3D SHA256_DIGEST_SIZE, - .setkey =3D aead_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA256_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha384),cbc(aes))", - .cra_driver_name =3D "authenc-hmac-sha384-" - "cbc-aes-talitos", - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D AES_BLOCK_SIZE, - .maxauthsize =3D SHA384_DIGEST_SIZE, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC | - DESC_HDR_SEL1_MDEUB | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEUB_SHA384_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha384)," - "cbc(des3_ede))", - .cra_driver_name =3D "authenc-hmac-sha384-" - "cbc-3des-talitos", - .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .maxauthsize =3D SHA384_DIGEST_SIZE, - .setkey =3D aead_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES | - DESC_HDR_SEL1_MDEUB | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEUB_SHA384_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha512),cbc(aes))", - .cra_driver_name =3D "authenc-hmac-sha512-" - "cbc-aes-talitos", - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D AES_BLOCK_SIZE, - .maxauthsize =3D SHA512_DIGEST_SIZE, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC | - DESC_HDR_SEL1_MDEUB | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEUB_SHA512_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha512)," - "cbc(des3_ede))", - .cra_driver_name =3D "authenc-hmac-sha512-" - "cbc-3des-talitos", - .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .maxauthsize =3D SHA512_DIGEST_SIZE, - .setkey =3D aead_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES | - DESC_HDR_SEL1_MDEUB | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEUB_SHA512_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(md5),cbc(aes))", - .cra_driver_name =3D "authenc-hmac-md5-" - "cbc-aes-talitos", - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D AES_BLOCK_SIZE, - .maxauthsize =3D MD5_DIGEST_SIZE, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_MD5_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(md5),cbc(aes))", - .cra_driver_name =3D "authenc-hmac-md5-" - "cbc-aes-talitos-hsna", - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D AES_BLOCK_SIZE, - .maxauthsize =3D MD5_DIGEST_SIZE, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_MD5_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(md5),cbc(des3_ede))", - .cra_driver_name =3D "authenc-hmac-md5-" - "cbc-3des-talitos", - .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .maxauthsize =3D MD5_DIGEST_SIZE, - .setkey =3D aead_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_MD5_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(md5),cbc(des3_ede))", - .cra_driver_name =3D "authenc-hmac-md5-" - "cbc-3des-talitos-hsna", - .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .maxauthsize =3D MD5_DIGEST_SIZE, - .setkey =3D aead_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_MD5_HMAC, - }, -}; - int talitos_init_common(struct talitos_ctx *ctx, struct talitos_crypto_alg *talitos_alg) { @@ -1821,18 +977,6 @@ int talitos_init_common(struct talitos_ctx *ctx, return 0; } =20 -static int talitos_cra_init_aead(struct crypto_aead *tfm) -{ - struct aead_alg *alg =3D crypto_aead_alg(tfm); - struct talitos_crypto_alg *talitos_alg; - struct talitos_ctx *ctx =3D crypto_aead_ctx(tfm); - - talitos_alg =3D container_of(alg, struct talitos_crypto_alg, - algt.alg.aead); - - return talitos_init_common(ctx, talitos_alg); -} - void talitos_cra_exit(struct crypto_tfm *tfm) { struct talitos_ctx *ctx =3D crypto_tfm_ctx(tfm); @@ -1942,6 +1086,12 @@ int talitos_register_common(struct device *dev, t_alg->algt.type); ret =3D crypto_register_skcipher(&t_alg->algt.alg.skcipher); break; + case CRYPTO_ALG_TYPE_AEAD: + alg =3D &t_alg->algt.alg.aead.base; + talitos_alg_set_common(priv, alg, t_alg->algt.priority, + t_alg->algt.type); + ret =3D crypto_register_aead(&t_alg->algt.alg.aead); + break; default: dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type); devm_kfree(dev, t_alg); @@ -1960,59 +1110,6 @@ int talitos_register_common(struct device *dev, return 0; } =20 -static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev, - struct talitos_alg_template - *template) -{ - struct talitos_private *priv =3D dev_get_drvdata(dev); - struct talitos_crypto_alg *t_alg; - struct crypto_alg *alg; - - t_alg =3D devm_kzalloc(dev, sizeof(struct talitos_crypto_alg), - GFP_KERNEL); - if (!t_alg) - return ERR_PTR(-ENOMEM); - - t_alg->algt =3D *template; - - switch (t_alg->algt.type) { - case CRYPTO_ALG_TYPE_AEAD: - alg =3D &t_alg->algt.alg.aead.base; - alg->cra_exit =3D talitos_cra_exit; - t_alg->algt.alg.aead.init =3D talitos_cra_init_aead; - t_alg->algt.alg.aead.setkey =3D t_alg->algt.alg.aead.setkey ?: - aead_setkey; - t_alg->algt.alg.aead.encrypt =3D aead_encrypt; - t_alg->algt.alg.aead.decrypt =3D aead_decrypt; - if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) && - !strncmp(alg->cra_name, "authenc(hmac(sha224)", 20)) { - devm_kfree(dev, t_alg); - return ERR_PTR(-ENOTSUPP); - } - break; - default: - dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type); - devm_kfree(dev, t_alg); - return ERR_PTR(-EINVAL); - } - - alg->cra_module =3D THIS_MODULE; - if (t_alg->algt.priority) - alg->cra_priority =3D t_alg->algt.priority; - else - alg->cra_priority =3D TALITOS_CRA_PRIORITY; - if (has_ftr_sec1(priv) && t_alg->algt.type !=3D CRYPTO_ALG_TYPE_AHASH) - alg->cra_alignmask =3D 3; - else - alg->cra_alignmask =3D 0; - alg->cra_ctxsize =3D sizeof(struct talitos_ctx); - alg->cra_flags |=3D CRYPTO_ALG_KERN_DRIVER_ONLY; - - t_alg->dev =3D dev; - - return t_alg; -} - static int talitos_probe_irq(struct platform_device *ofdev) { struct device *dev =3D &ofdev->dev; @@ -2224,36 +1321,10 @@ static int talitos_probe(struct platform_device *of= dev) if (err) goto err_out; =20 - /* register crypto algorithms the device supports */ - for (i =3D 0; i < ARRAY_SIZE(driver_algs); i++) { - if (talitos_hw_supports(dev, - driver_algs[i].desc_hdr_template)) { - struct talitos_crypto_alg *t_alg; - struct crypto_alg *alg =3D NULL; - - t_alg =3D talitos_alg_alloc(dev, &driver_algs[i]); - if (IS_ERR(t_alg)) { - err =3D PTR_ERR(t_alg); - if (err =3D=3D -ENOTSUPP) - continue; - goto err_out; - } + err =3D talitos_register_aead(dev); + if (err) + goto err_out; =20 - switch (t_alg->algt.type) { - case CRYPTO_ALG_TYPE_AEAD: - err =3D crypto_register_aead( - &t_alg->algt.alg.aead); - alg =3D &t_alg->algt.alg.aead.base; - break; - } - if (err) { - dev_err(dev, "%s alg registration failed\n", - alg->cra_driver_name); - devm_kfree(dev, t_alg); - } else - list_add_tail(&t_alg->entry, &priv->alg_list); - } - } if (!list_empty(&priv->alg_list)) dev_info(dev, "%s algorithms registered in /proc/crypto\n", (char *)of_get_property(np, "compatible", NULL)); diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/tali= tos.h index 07cdd6034883..8aa3102e9935 100644 --- a/drivers/crypto/talitos/talitos.h +++ b/drivers/crypto/talitos/talitos.h @@ -21,6 +21,8 @@ #define TALITOS1_MAX_DATA_LEN 32768 #define TALITOS2_MAX_DATA_LEN 65535 =20 +#define TALITOS_CRA_PRIORITY 3000 + #define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f) #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf) #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf) @@ -611,3 +613,4 @@ void talitos_unregister_rng(struct device *dev); =20 int talitos_register_hash(struct device *dev); int talitos_register_skcipher(struct device *dev); +int talitos_register_aead(struct device *dev); --=20 2.55.0 From nobody Thu Sep 24 13:42:19 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E5B4568FB3; Wed, 23 Sep 2026 15:19:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790176773; cv=none; b=mu4jatxxKGDd3rdAWM3FZVMco1cxCx2q0MKQFuNtVGhOATl2DLrdLPYj/uwHL42dd9B+rSZREbGExswbtDYrNZ7yvXGz5Ojy6kdb8qbCcILp1xGqTdwmdhxTR8VQpWBTZ1dnmWyOZArXLwRCpwuhauYtBJ5cfepl29HYKTnLGgI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790176773; c=relaxed/simple; bh=cFvsG8eCjUgT2nbFx8V91OE0dxvivNp44m7kLEBtKtc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WPVSdVBhDNBkG/bVsbDH3/8fdRBoDhjVv61Gv902rV+rZ6tvrdveSN5Pu7Tp4w5ywZKUQb9GwF+ZGUdQdq0CLD6qoH9AP5YUcN9Aa8MJXCnF0YC91oYdWZgAbnUt9oIyoXXu8NnOuX5cEc9jzqVZAyEklTaFwdVzsFRY0kK8A3Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=KZ+FE4py; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="KZ+FE4py" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id B51BA1A0FE6; Wed, 23 Sep 2026 15:19:29 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 89F8B60580; Wed, 23 Sep 2026 15:19:29 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2642410329217; Wed, 23 Sep 2026 17:19:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1790176769; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=C6DQNv0+LZVrJwNDxVc3/0BqftE1SZpqze//+6WBsAE=; b=KZ+FE4pyYOelp/9Gy2bfPM0qh8BN8mEiieywiSJEcKr5WB9fA8Zi7MHVtJa3/NF9WXw3wY tbj3eQMFzw7W9Z9PpLfIStX1sDjBhyBcKerTh6H3+VGCTEK4T5Foa3edU1LggXWJy30wzZ 7F6yJgKvJkm5FaBMImJoXvY3oGnTXkH8I77wI+yMyPTP3UiIczKZCbsxrMXqPs93+fQJFm 15VLfsbZ/Jo0xKZ6TU058nf1ySeLDrrJ4V6p48hS1Uy15dHG2cYS8DOMXEQw8Z7cKkRuPl 3FgQMrXQfH+UA+vWtVvbNUB9mIDN/6cvspl3ne9pV3Bxee0Gf39FwRTWaI/vJw== From: Paul Louvel Date: Wed, 23 Sep 2026 17:18:45 +0200 Subject: [PATCH v7 09/20] crypto: talitos/hash - Convert to {init,exit}_tfm type-specific API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-7-3-rc2_talitos_cleanup-v7-9-9a45261fc097@bootlin.com> References: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> In-Reply-To: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> To: Herbert Xu , "David S. Miller" Cc: Paul Louvel , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Christophe Leroy , "Christophe Leroy (CS GROUP)" X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790176746; l=2077; i=paul.louvel@bootlin.com; s=20260313; h=from:subject:message-id; bh=cFvsG8eCjUgT2nbFx8V91OE0dxvivNp44m7kLEBtKtc=; b=1WtruxYIZq0vCCC38iYlbMU3Wvw686xhSp5FVB2w10RhmwUxAQc0PTqBWzIaj+r/jzD6N7jv6 x+lR4CVqB5pCeONpuSXYtjPxVg6dkbM5T32kyo6AC7ekouNt2xTU3QK X-Developer-Key: i=paul.louvel@bootlin.com; a=ed25519; pk=eLW50NT18UAvUT5cAcYf88zNbBCZDLFXuptpyLVhVIU= X-Last-TLS-Session-Version: TLSv1.3 Since commit 6eed1e3552fc0 ("crypto: api - Mark cra_init/cra_exit as deprecated"), both cra_{init,exit} are deprecated. Use {init,exit}_tfm instead. Reviewed-by: Christophe Leroy (CS GROUP) Signed-off-by: Paul Louvel --- drivers/crypto/talitos/talitos-hash.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/crypto/talitos/talitos-hash.c b/drivers/crypto/talitos= /talitos-hash.c index 7ce4e68dd7a0..97526c1ffbfd 100644 --- a/drivers/crypto/talitos/talitos-hash.c +++ b/drivers/crypto/talitos/talitos-hash.c @@ -544,13 +544,13 @@ static int ahash_setkey(struct crypto_ahash *tfm, con= st u8 *key, return 0; } =20 -static int talitos_cra_init_ahash(struct crypto_tfm *tfm) +static int talitos_cra_init_ahash(struct crypto_ahash *tfm) { - struct crypto_alg *alg =3D tfm->__crt_alg; + struct ahash_alg *alg =3D crypto_ahash_alg(tfm); struct talitos_crypto_alg *talitos_alg; - struct talitos_ctx *ctx =3D crypto_tfm_ctx(tfm); + struct talitos_ctx *ctx =3D crypto_ahash_ctx(tfm); =20 - talitos_alg =3D container_of(__crypto_ahash_alg(alg), + talitos_alg =3D container_of(alg, struct talitos_crypto_alg, algt.alg.hash); =20 @@ -559,6 +559,11 @@ static int talitos_cra_init_ahash(struct crypto_tfm *t= fm) return talitos_init_common(ctx, talitos_alg); } =20 +static void talitos_cra_exit_ahash(struct crypto_ahash *tfm) +{ + talitos_cra_exit(crypto_ahash_tfm(tfm)); +} + static const struct talitos_alg_template hash_driver_algs[] =3D { { .type =3D CRYPTO_ALG_TYPE_AHASH, .alg.hash =3D { @@ -797,8 +802,8 @@ int talitos_register_hash(struct device *dev) ahash_alg =3D &talitos_alg_template.alg.hash; alg =3D &ahash_alg->halg.base; =20 - alg->cra_init =3D talitos_cra_init_ahash; - alg->cra_exit =3D talitos_cra_exit; + ahash_alg->init_tfm =3D talitos_cra_init_ahash; + ahash_alg->exit_tfm =3D talitos_cra_exit_ahash; ahash_alg->init =3D ahash_init; ahash_alg->update =3D ahash_update; ahash_alg->final =3D ahash_final; --=20 2.55.0 From nobody Thu Sep 24 13:42:19 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 642F9549376 for ; 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bh=bcssHe3FUjbgo5c0WBhKNqn0JWGj8BDh2G8L/qXCQjk=; b=vlt+7vmN55In1Fn6BDdLA/ndT2MZJGnZEMy+YSLOnK2RlFsXQv18FaMSl732mjUN8p4kBo f+yfpOCKYLtmSFGwwZtVfvnNqKf5jEX/mIIcKQTNKit8oYqqZh53QvRH6S37R3mq9Oidx3 p1gSVhPRMApOY8XA11dYBYi2x7vT0gNaLv8mcxLIQIGg5f/9VeeiiDeKXPWV5jcgte8jB+ kvr2UWqp78/8+c7QzYaKIcszS9RvwTYb+eDAPz00KGBUKDePFaONgoHE+YatEreD/W88Ga QeetzmP5KqEEYapwqMDuqNg5BmqxLrHpQbjnxcC0D2EHjEbqSAXWa7mSV1NUBQ== From: Paul Louvel Date: Wed, 23 Sep 2026 17:18:46 +0200 Subject: [PATCH v7 10/20] crypto: talitos/skcipher - Convert to {init,exit}_tfm type-specific API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-7-3-rc2_talitos_cleanup-v7-10-9a45261fc097@bootlin.com> References: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> In-Reply-To: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> To: Herbert Xu , "David S. Miller" Cc: Paul Louvel , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Christophe Leroy , "Christophe Leroy (CS GROUP)" X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790176746; l=1565; i=paul.louvel@bootlin.com; s=20260313; h=from:subject:message-id; bh=tv/D1m+jWDZUaVM7vfSAa+Ud714zRZugQxwPlYEI8xc=; b=ZHV9j03CQR0jAjlwzOSqDtgBVrLJ7p66O9W7joDX5V7ufXejTBfNQOXbbMDdxunq4WJuFAsc0 75acFTL5m/FCqo89iu41oojXHHwmgMySn0EcTk0XMyoILHzp7Qg1DeK X-Developer-Key: i=paul.louvel@bootlin.com; a=ed25519; pk=eLW50NT18UAvUT5cAcYf88zNbBCZDLFXuptpyLVhVIU= X-Last-TLS-Session-Version: TLSv1.3 Since commit 6eed1e3552fc0 ("crypto: api - Mark cra_init/cra_exit as deprecated"), both cra_{init,exit} are deprecated. Use {init,exit}_tfm instead. Reviewed-by: Christophe Leroy (CS GROUP) Signed-off-by: Paul Louvel --- drivers/crypto/talitos/talitos-skcipher.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/talitos/talitos-skcipher.c b/drivers/crypto/tal= itos/talitos-skcipher.c index e4e8bebdfb7b..6c60ad6aa9be 100644 --- a/drivers/crypto/talitos/talitos-skcipher.c +++ b/drivers/crypto/talitos/talitos-skcipher.c @@ -232,6 +232,11 @@ static int talitos_cra_init_skcipher(struct crypto_skc= ipher *tfm) return talitos_init_common(ctx, talitos_alg); } =20 +static void talitos_cra_exit_skcipher(struct crypto_skcipher *tfm) +{ + talitos_cra_exit(crypto_skcipher_tfm(tfm)); +} + static const struct talitos_alg_template skcipher_driver_algs[] =3D { { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, .alg.skcipher =3D { @@ -378,11 +383,11 @@ int talitos_register_skcipher(struct device *dev) skcipher_alg =3D &talitos_alg_template.alg.skcipher; alg =3D &skcipher_alg->base; =20 - alg->cra_exit =3D talitos_cra_exit; if (has_ftr_sec1(priv)) alg->cra_alignmask =3D 3; =20 skcipher_alg->init =3D talitos_cra_init_skcipher; + skcipher_alg->exit =3D talitos_cra_exit_skcipher; skcipher_alg->setkey =3D skcipher_alg->setkey ?: skcipher_setkey; skcipher_alg->encrypt =3D skcipher_encrypt; skcipher_alg->decrypt =3D skcipher_decrypt; --=20 2.55.0 From nobody Thu Sep 24 13:42:19 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F51D542EE0; Wed, 23 Sep 2026 15:19:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790176776; cv=none; b=j81GVv3Y1lkxCkgH2BCndga2uGuV5T48MHihgB4jcIhrBSWjCkENvb1IjOBQ7J7LSL3oiwbdAXKEFNatjRAPGWK+Uejd0NpjyVsd3syCcA1qAvAq7Bd1SBa2d0uWkvDFcCGAY1a1tjjcEz1cnH31j8glzlvLiju0G6pMcMzPEFc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790176776; c=relaxed/simple; bh=vQcKrYP6k0j5wNodab0zb0g+Xj+k54TiujSaCIm7m8g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WIGM+QqGBs53QZ4XMdlL+oln9OMvyqBQaGl7QHGZ2tmmsvhxMfgjNmP5tSHVPbGnunB5R1bfjrafyIokj9JzrGFw0F4coNl/3s8MfMEZCfY1RVuQoUOSoHyx90WxWvLCuXqFCduJiR1mSAaNa80+N5A4SKODz//ZYqIKy4hqeqU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Thj/mIlS; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Thj/mIlS" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id F0E031A0FE4; Wed, 23 Sep 2026 15:19:32 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id C584160580; Wed, 23 Sep 2026 15:19:32 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id CFC51103293DD; Wed, 23 Sep 2026 17:19:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1790176771; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=HlsWSVvNlE3rAAAwzxFjv9sOhP6ooQFClSUhAwaPBys=; b=Thj/mIlSnbMX8z67um4WC1oerrnq3RZBhee1QuvcfT4deYIklZng4lkpgILUYcTesEi5MG cjT7g1RIAE296HI1XzxP59KBAfU5RbUdjsFHXRxpNl7/8RDsvDURSOeTXVYq2MAUlbGe9Q p3KskQeMuMme/3orFPKmAgqsZmWmTVoMqzagbqivCPO796quK1Lskkb4IqXXeJV2rcqPOW Btq5Z0dg/Vt466zHJATYyvYdv26AWX4Pb6Lmy8oNUlgLshPvWpj3VAyFRVkBy2fChfReQd ojeuE3qGzHb4DQ2wPRqoF+86RgEo2+FgnUSbe2evliT828fxU8sWdFd5DOhwHw== From: Paul Louvel Date: Wed, 23 Sep 2026 17:18:47 +0200 Subject: [PATCH v7 11/20] crypto: talitos/aead - Convert to {init,exit}_tfm type-specific API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-7-3-rc2_talitos_cleanup-v7-11-9a45261fc097@bootlin.com> References: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> In-Reply-To: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> To: Herbert Xu , "David S. Miller" Cc: Paul Louvel , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Christophe Leroy , "Christophe Leroy (CS GROUP)" X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790176746; l=1453; i=paul.louvel@bootlin.com; s=20260313; h=from:subject:message-id; bh=vQcKrYP6k0j5wNodab0zb0g+Xj+k54TiujSaCIm7m8g=; b=u+VZJ1miKTGNpguBjBVB1zrOMweUK1TcBG29u9qvHMFi8q5y7ZrhPrMLdIDkssKBLZz2k2Y9w DLjq4WrqtWCAk9mTBHyEkPrstdQ5yubEm86bmxYNrCnvydu4JH8ydr2 X-Developer-Key: i=paul.louvel@bootlin.com; a=ed25519; pk=eLW50NT18UAvUT5cAcYf88zNbBCZDLFXuptpyLVhVIU= X-Last-TLS-Session-Version: TLSv1.3 Since commit 6eed1e3552fc0 ("crypto: api - Mark cra_init/cra_exit as deprecated"), both cra_{init,exit} are deprecated. Use {init,exit}_tfm instead. Reviewed-by: Christophe Leroy (CS GROUP) Signed-off-by: Paul Louvel --- drivers/crypto/talitos/talitos-aead.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/talitos/talitos-aead.c b/drivers/crypto/talitos= /talitos-aead.c index 0236f152743b..40d048de0502 100644 --- a/drivers/crypto/talitos/talitos-aead.c +++ b/drivers/crypto/talitos/talitos-aead.c @@ -400,6 +400,11 @@ static int talitos_cra_init_aead(struct crypto_aead *t= fm) return talitos_init_common(ctx, talitos_alg); } =20 +static void talitos_cra_exit_aead(struct crypto_aead *tfm) +{ + talitos_cra_exit(crypto_aead_tfm(tfm)); +} + static const struct talitos_alg_template aead_driver_algs[] =3D { { .type =3D CRYPTO_ALG_TYPE_AEAD, .alg.aead =3D { @@ -878,11 +883,11 @@ int talitos_register_aead(struct device *dev) aead_alg =3D &talitos_alg_template.alg.aead; alg =3D &aead_alg->base; =20 - alg->cra_exit =3D talitos_cra_exit; if (has_ftr_sec1(priv)) alg->cra_alignmask =3D 3; =20 aead_alg->init =3D talitos_cra_init_aead; + aead_alg->exit =3D talitos_cra_exit_aead; aead_alg->setkey =3D aead_alg->setkey ?: aead_setkey; aead_alg->encrypt =3D aead_encrypt; aead_alg->decrypt =3D aead_decrypt; --=20 2.55.0 From nobody Thu Sep 24 13:42:19 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B755569F28 for ; Wed, 23 Sep 2026 15:19:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790176781; cv=none; b=oUaa81zgWdiSw2i0sM0uju2JSLL6ReORrpz3/s7/5sHSsZUC1MsXgLWAwWChxZFSkeiIY5P1pEfUGTQtbIpv/I89YJBf5zgt0egwKdxpd46z43R3KL3CScUmjNnKh4bsZ1eJrb+GFMiwGipM2oNmUQHs3VEppgUkRQS6btCkkNk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790176781; c=relaxed/simple; bh=ugrp6rp7/vIv3tTIv0Z5POQDNyMypDU7Q6S8RwqUDn0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jeQmNYp4DKzHp00GvkM+0dy+y/IDoIovbMloU05GuFcOpOJWkK2OEkE1rXksUQ249CXvr6S3PJsWLSCnClqGskjJo6FJZuGliNdFqvlWS+TvqfBD7QraDQwyrJqkt8GkKHpSO4QstrYMJH2fPfQfDp1Un3kaVzmYArRiCV2YUiQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Ec2IVQ9X; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Ec2IVQ9X" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id AC99F4E41045; Wed, 23 Sep 2026 15:19:34 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 8076160580; Wed, 23 Sep 2026 15:19:34 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id CDC91103282D3; Wed, 23 Sep 2026 17:19:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1790176773; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=bhKDBgkuoqKNDQ1olHzLDgfcCk7kPsy3+AK+xnf/SP0=; b=Ec2IVQ9XaH9u3wC/al4j3wXz8I0SwGmcxl+BBdc3t7gznuTYBJ+Oh+CJoNY1q/vAhBTNv1 LEJv+gPVq6ii9uIF9nu6yty393WwB2ifvjrLD2ieu6C2fagUQx47LrQqhIsGjDXyvyVt/T tZtSi6YjnY4ISgO6l3aeAC7y21YV3ntOxrSS4UcTOKDXeppPOklJNGvtfmxpWXZdAaN8gY VbdmTwBnlGmlYQB8b/8M5JGc9b8RJCdQHKtnOC6wzDxXq2BmKxTguEgxLwqj9LYJg4QQrg Xze1RlzIFK9wH3WtxvasSSzl1078IyiqExgrsQwOWM1ccuSRR6bqQr5BFW36RA== From: Paul Louvel Date: Wed, 23 Sep 2026 17:18:48 +0200 Subject: [PATCH v7 12/20] crypto: talitos - Remove alg settings in talitos_register_common() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-7-3-rc2_talitos_cleanup-v7-12-9a45261fc097@bootlin.com> References: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> In-Reply-To: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> To: Herbert Xu , "David S. Miller" Cc: Paul Louvel , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Christophe Leroy X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790176746; l=22604; i=paul.louvel@bootlin.com; s=20260313; h=from:subject:message-id; bh=ugrp6rp7/vIv3tTIv0Z5POQDNyMypDU7Q6S8RwqUDn0=; b=Icgjkhwp0JuwrbFQKeGoXCbFZvAeLTa5ihNMFi36YC07LNo5Xqiym/Yw+xL6+Js5xrLx0SJwJ eAiJG9agkGPDjTz0WgAFh4T2ahttnWo3byYfhOE7PE5K/nH5PELDOvr X-Developer-Key: i=paul.louvel@bootlin.com; a=ed25519; pk=eLW50NT18UAvUT5cAcYf88zNbBCZDLFXuptpyLVhVIU= X-Last-TLS-Session-Version: TLSv1.3 Algorithm properties are now set at compile time for those who are not dependent on runtime features. Remove now-unused function and struct member. --- drivers/crypto/talitos/talitos-aead.c | 128 ++++++++++++++++++++++++++----= ---- drivers/crypto/talitos/talitos-core.c | 23 ------ drivers/crypto/talitos/talitos-hash.c | 72 +++++++++++++++---- drivers/crypto/talitos/talitos.h | 1 - 4 files changed, 160 insertions(+), 64 deletions(-) diff --git a/drivers/crypto/talitos/talitos-aead.c b/drivers/crypto/talitos= /talitos-aead.c index 40d048de0502..0504b8575e26 100644 --- a/drivers/crypto/talitos/talitos-aead.c +++ b/drivers/crypto/talitos/talitos-aead.c @@ -413,7 +413,11 @@ static const struct talitos_alg_template aead_driver_a= lgs[] =3D { .cra_driver_name =3D "authenc-hmac-sha1-" "cbc-aes-talitos", .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY, }, .ivsize =3D AES_BLOCK_SIZE, @@ -428,14 +432,17 @@ static const struct talitos_alg_template aead_driver_= algs[] =3D { DESC_HDR_MODE1_MDEU_SHA1_HMAC, }, { .type =3D CRYPTO_ALG_TYPE_AEAD, - .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, .alg.aead =3D { .base =3D { .cra_name =3D "authenc(hmac(sha1),cbc(aes))", .cra_driver_name =3D "authenc-hmac-sha1-" "cbc-aes-talitos-hsna", .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY, }, .ivsize =3D AES_BLOCK_SIZE, @@ -457,7 +464,11 @@ static const struct talitos_alg_template aead_driver_a= lgs[] =3D { .cra_driver_name =3D "authenc-hmac-sha1-" "cbc-3des-talitos", .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY, }, .ivsize =3D DES3_EDE_BLOCK_SIZE, @@ -474,7 +485,6 @@ static const struct talitos_alg_template aead_driver_al= gs[] =3D { DESC_HDR_MODE1_MDEU_SHA1_HMAC, }, { .type =3D CRYPTO_ALG_TYPE_AEAD, - .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, .alg.aead =3D { .base =3D { .cra_name =3D "authenc(hmac(sha1)," @@ -482,7 +492,11 @@ static const struct talitos_alg_template aead_driver_a= lgs[] =3D { .cra_driver_name =3D "authenc-hmac-sha1-" "cbc-3des-talitos-hsna", .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY, }, .ivsize =3D DES3_EDE_BLOCK_SIZE, @@ -505,7 +519,11 @@ static const struct talitos_alg_template aead_driver_a= lgs[] =3D { .cra_driver_name =3D "authenc-hmac-sha224-" "cbc-aes-talitos", .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY, }, .ivsize =3D AES_BLOCK_SIZE, @@ -520,14 +538,17 @@ static const struct talitos_alg_template aead_driver_= algs[] =3D { DESC_HDR_MODE1_MDEU_SHA224_HMAC, }, { .type =3D CRYPTO_ALG_TYPE_AEAD, - .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, .alg.aead =3D { .base =3D { .cra_name =3D "authenc(hmac(sha224),cbc(aes))", .cra_driver_name =3D "authenc-hmac-sha224-" "cbc-aes-talitos-hsna", .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY, }, .ivsize =3D AES_BLOCK_SIZE, @@ -549,7 +570,11 @@ static const struct talitos_alg_template aead_driver_a= lgs[] =3D { .cra_driver_name =3D "authenc-hmac-sha224-" "cbc-3des-talitos", .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY, }, .ivsize =3D DES3_EDE_BLOCK_SIZE, @@ -566,7 +591,6 @@ static const struct talitos_alg_template aead_driver_al= gs[] =3D { DESC_HDR_MODE1_MDEU_SHA224_HMAC, }, { .type =3D CRYPTO_ALG_TYPE_AEAD, - .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, .alg.aead =3D { .base =3D { .cra_name =3D "authenc(hmac(sha224)," @@ -574,7 +598,11 @@ static const struct talitos_alg_template aead_driver_a= lgs[] =3D { .cra_driver_name =3D "authenc-hmac-sha224-" "cbc-3des-talitos-hsna", .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY, }, .ivsize =3D DES3_EDE_BLOCK_SIZE, @@ -597,7 +625,11 @@ static const struct talitos_alg_template aead_driver_a= lgs[] =3D { .cra_driver_name =3D "authenc-hmac-sha256-" "cbc-aes-talitos", .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY, }, .ivsize =3D AES_BLOCK_SIZE, @@ -612,14 +644,17 @@ static const struct talitos_alg_template aead_driver_= algs[] =3D { DESC_HDR_MODE1_MDEU_SHA256_HMAC, }, { .type =3D CRYPTO_ALG_TYPE_AEAD, - .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, .alg.aead =3D { .base =3D { .cra_name =3D "authenc(hmac(sha256),cbc(aes))", .cra_driver_name =3D "authenc-hmac-sha256-" "cbc-aes-talitos-hsna", .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY, }, .ivsize =3D AES_BLOCK_SIZE, @@ -641,7 +676,11 @@ static const struct talitos_alg_template aead_driver_a= lgs[] =3D { .cra_driver_name =3D "authenc-hmac-sha256-" "cbc-3des-talitos", .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY, }, .ivsize =3D DES3_EDE_BLOCK_SIZE, @@ -658,7 +697,6 @@ static const struct talitos_alg_template aead_driver_al= gs[] =3D { DESC_HDR_MODE1_MDEU_SHA256_HMAC, }, { .type =3D CRYPTO_ALG_TYPE_AEAD, - .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, .alg.aead =3D { .base =3D { .cra_name =3D "authenc(hmac(sha256)," @@ -666,7 +704,11 @@ static const struct talitos_alg_template aead_driver_a= lgs[] =3D { .cra_driver_name =3D "authenc-hmac-sha256-" "cbc-3des-talitos-hsna", .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY, }, .ivsize =3D DES3_EDE_BLOCK_SIZE, @@ -689,7 +731,11 @@ static const struct talitos_alg_template aead_driver_a= lgs[] =3D { .cra_driver_name =3D "authenc-hmac-sha384-" "cbc-aes-talitos", .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY, }, .ivsize =3D AES_BLOCK_SIZE, @@ -711,7 +757,11 @@ static const struct talitos_alg_template aead_driver_a= lgs[] =3D { .cra_driver_name =3D "authenc-hmac-sha384-" "cbc-3des-talitos", .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY, }, .ivsize =3D DES3_EDE_BLOCK_SIZE, @@ -734,7 +784,11 @@ static const struct talitos_alg_template aead_driver_a= lgs[] =3D { .cra_driver_name =3D "authenc-hmac-sha512-" "cbc-aes-talitos", .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY, }, .ivsize =3D AES_BLOCK_SIZE, @@ -756,7 +810,11 @@ static const struct talitos_alg_template aead_driver_a= lgs[] =3D { .cra_driver_name =3D "authenc-hmac-sha512-" "cbc-3des-talitos", .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY, }, .ivsize =3D DES3_EDE_BLOCK_SIZE, @@ -779,7 +837,11 @@ static const struct talitos_alg_template aead_driver_a= lgs[] =3D { .cra_driver_name =3D "authenc-hmac-md5-" "cbc-aes-talitos", .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY, }, .ivsize =3D AES_BLOCK_SIZE, @@ -794,14 +856,17 @@ static const struct talitos_alg_template aead_driver_= algs[] =3D { DESC_HDR_MODE1_MDEU_MD5_HMAC, }, { .type =3D CRYPTO_ALG_TYPE_AEAD, - .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, .alg.aead =3D { .base =3D { .cra_name =3D "authenc(hmac(md5),cbc(aes))", .cra_driver_name =3D "authenc-hmac-md5-" "cbc-aes-talitos-hsna", .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY, }, .ivsize =3D AES_BLOCK_SIZE, @@ -822,7 +887,11 @@ static const struct talitos_alg_template aead_driver_a= lgs[] =3D { .cra_driver_name =3D "authenc-hmac-md5-" "cbc-3des-talitos", .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY, }, .ivsize =3D DES3_EDE_BLOCK_SIZE, @@ -839,14 +908,17 @@ static const struct talitos_alg_template aead_driver_= algs[] =3D { DESC_HDR_MODE1_MDEU_MD5_HMAC, }, { .type =3D CRYPTO_ALG_TYPE_AEAD, - .priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, .alg.aead =3D { .base =3D { .cra_name =3D "authenc(hmac(md5),cbc(des3_ede))", .cra_driver_name =3D "authenc-hmac-md5-" "cbc-3des-talitos-hsna", .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY, }, .ivsize =3D DES3_EDE_BLOCK_SIZE, diff --git a/drivers/crypto/talitos/talitos-core.c b/drivers/crypto/talitos= /talitos-core.c index 85ce77dbc329..6d1063502285 100644 --- a/drivers/crypto/talitos/talitos-core.c +++ b/drivers/crypto/talitos/talitos-core.c @@ -1040,23 +1040,6 @@ static void talitos_remove(struct platform_device *o= fdev) tasklet_kill(&priv->done_task[1]); } =20 -static void talitos_alg_set_common(struct talitos_private *priv, - struct crypto_alg *alg, u32 custom_priority, - u32 type) -{ - alg->cra_module =3D THIS_MODULE; - if (custom_priority) - alg->cra_priority =3D custom_priority; - else - alg->cra_priority =3D TALITOS_CRA_PRIORITY; - if (has_ftr_sec1(priv) && type !=3D CRYPTO_ALG_TYPE_AHASH) - alg->cra_alignmask =3D 3; - else - alg->cra_alignmask =3D 0; - alg->cra_ctxsize =3D sizeof(struct talitos_ctx); - alg->cra_flags |=3D CRYPTO_ALG_KERN_DRIVER_ONLY; -} - int talitos_register_common(struct device *dev, struct talitos_alg_template *template) { @@ -1076,20 +1059,14 @@ int talitos_register_common(struct device *dev, switch (t_alg->algt.type) { case CRYPTO_ALG_TYPE_AHASH: alg =3D &t_alg->algt.alg.hash.halg.base; - talitos_alg_set_common(priv, alg, t_alg->algt.priority, - t_alg->algt.type); ret =3D crypto_register_ahash(&t_alg->algt.alg.hash); break; case CRYPTO_ALG_TYPE_SKCIPHER: alg =3D &t_alg->algt.alg.skcipher.base; - talitos_alg_set_common(priv, alg, t_alg->algt.priority, - t_alg->algt.type); ret =3D crypto_register_skcipher(&t_alg->algt.alg.skcipher); break; case CRYPTO_ALG_TYPE_AEAD: alg =3D &t_alg->algt.alg.aead.base; - talitos_alg_set_common(priv, alg, t_alg->algt.priority, - t_alg->algt.type); ret =3D crypto_register_aead(&t_alg->algt.alg.aead); break; default: diff --git a/drivers/crypto/talitos/talitos-hash.c b/drivers/crypto/talitos= /talitos-hash.c index 97526c1ffbfd..372b78650916 100644 --- a/drivers/crypto/talitos/talitos-hash.c +++ b/drivers/crypto/talitos/talitos-hash.c @@ -574,7 +574,11 @@ static const struct talitos_alg_template hash_driver_a= lgs[] =3D { .cra_driver_name =3D "md5-talitos", .cra_blocksize =3D MD5_HMAC_BLOCK_SIZE, .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY | CRYPTO_AHASH_ALG_BLOCK_ONLY, } @@ -592,7 +596,11 @@ static const struct talitos_alg_template hash_driver_a= lgs[] =3D { .cra_driver_name =3D "sha1-talitos", .cra_blocksize =3D SHA1_BLOCK_SIZE, .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY | CRYPTO_AHASH_ALG_BLOCK_ONLY, } @@ -610,7 +618,11 @@ static const struct talitos_alg_template hash_driver_a= lgs[] =3D { .cra_driver_name =3D "sha224-talitos", .cra_blocksize =3D SHA224_BLOCK_SIZE, .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY | CRYPTO_AHASH_ALG_BLOCK_ONLY, } @@ -628,7 +640,11 @@ static const struct talitos_alg_template hash_driver_a= lgs[] =3D { .cra_driver_name =3D "sha256-talitos", .cra_blocksize =3D SHA256_BLOCK_SIZE, .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY | CRYPTO_AHASH_ALG_BLOCK_ONLY, } @@ -646,7 +662,11 @@ static const struct talitos_alg_template hash_driver_a= lgs[] =3D { .cra_driver_name =3D "sha384-talitos", .cra_blocksize =3D SHA384_BLOCK_SIZE, .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY | CRYPTO_AHASH_ALG_BLOCK_ONLY, } @@ -664,7 +684,11 @@ static const struct talitos_alg_template hash_driver_a= lgs[] =3D { .cra_driver_name =3D "sha512-talitos", .cra_blocksize =3D SHA512_BLOCK_SIZE, .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY | CRYPTO_AHASH_ALG_BLOCK_ONLY, } @@ -682,7 +706,11 @@ static const struct talitos_alg_template hash_driver_a= lgs[] =3D { .cra_driver_name =3D "hmac-md5-talitos", .cra_blocksize =3D MD5_HMAC_BLOCK_SIZE, .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY | CRYPTO_AHASH_ALG_BLOCK_ONLY, } @@ -700,7 +728,11 @@ static const struct talitos_alg_template hash_driver_a= lgs[] =3D { .cra_driver_name =3D "hmac-sha1-talitos", .cra_blocksize =3D SHA1_BLOCK_SIZE, .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY | CRYPTO_AHASH_ALG_BLOCK_ONLY, } @@ -718,7 +750,11 @@ static const struct talitos_alg_template hash_driver_a= lgs[] =3D { .cra_driver_name =3D "hmac-sha224-talitos", .cra_blocksize =3D SHA224_BLOCK_SIZE, .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY | CRYPTO_AHASH_ALG_BLOCK_ONLY, } @@ -736,7 +772,11 @@ static const struct talitos_alg_template hash_driver_a= lgs[] =3D { .cra_driver_name =3D "hmac-sha256-talitos", .cra_blocksize =3D SHA256_BLOCK_SIZE, .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY | CRYPTO_AHASH_ALG_BLOCK_ONLY, } @@ -754,7 +794,11 @@ static const struct talitos_alg_template hash_driver_a= lgs[] =3D { .cra_driver_name =3D "hmac-sha384-talitos", .cra_blocksize =3D SHA384_BLOCK_SIZE, .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_flags =3D CRYPTO_ALG_ASYNC | + .cra_module =3D THIS_MODULE, + .cra_priority =3D TALITOS_CRA_PRIORITY, + .cra_ctxsize =3D sizeof(struct talitos_ctx), + .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY | CRYPTO_AHASH_ALG_BLOCK_ONLY, } @@ -772,7 +816,11 @@ static const struct talitos_alg_template hash_driver_a= lgs[] =3D { .cra_driver_name =3D "hmac-sha512-talitos", .cra_blocksize =3D SHA512_BLOCK_SIZE, .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - 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Use macro for algorithm definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-7-3-rc2_talitos_cleanup-v7-13-9a45261fc097@bootlin.com> References: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> In-Reply-To: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> To: Herbert Xu , "David S. Miller" Cc: Paul Louvel , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Christophe Leroy , "Christophe Leroy (CS GROUP)" X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790176746; l=15357; i=paul.louvel@bootlin.com; s=20260313; h=from:subject:message-id; bh=lkGpZleBnxJPiqLPQcB6XOPL3LRAKa4T9QpN0doKnks=; b=pnix5s3PLynIOsrnTMBDO5ZfFzp52nTYMdefT8uAr/zJa2qZIEa3Vu09zzkAox9ickFPTSlvJ JEbGLyVwuKnBWekynvddrAFtJbWbJB/RTteeXqcHDjVu+ilDaWq54Uk X-Developer-Key: i=paul.louvel@bootlin.com; a=ed25519; pk=eLW50NT18UAvUT5cAcYf88zNbBCZDLFXuptpyLVhVIU= X-Last-TLS-Session-Version: TLSv1.3 Replace the repetitive struct initializer entries with preprocessor macros. The HMAC setkey assignment, previously done by comparing the algorithm name at runtime, is now handled by passing ahash_setkey directly through the TALITOS_HMAC_HASH_ALG macro variant. Reviewed-by: Christophe Leroy (CS GROUP) Signed-off-by: Paul Louvel --- drivers/crypto/talitos/talitos-hash.c | 380 ++++++++++--------------------= ---- 1 file changed, 104 insertions(+), 276 deletions(-) diff --git a/drivers/crypto/talitos/talitos-hash.c b/drivers/crypto/talitos= /talitos-hash.c index 372b78650916..165ae9bb570e 100644 --- a/drivers/crypto/talitos/talitos-hash.c +++ b/drivers/crypto/talitos/talitos-hash.c @@ -564,271 +564,111 @@ static void talitos_cra_exit_ahash(struct crypto_ah= ash *tfm) talitos_cra_exit(crypto_ahash_tfm(tfm)); } =20 -static const struct talitos_alg_template hash_driver_algs[] =3D { - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D MD5_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "md5", - .cra_driver_name =3D "md5-talitos", - .cra_blocksize =3D MD5_HMAC_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUA | - DESC_HDR_MODE0_MDEU_MD5, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D SHA1_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "sha1", - .cra_driver_name =3D "sha1-talitos", - .cra_blocksize =3D SHA1_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUA | - DESC_HDR_MODE0_MDEU_SHA1, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D SHA224_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "sha224", - .cra_driver_name =3D "sha224-talitos", - .cra_blocksize =3D SHA224_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUA | - DESC_HDR_MODE0_MDEU_SHA224, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D SHA256_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "sha256", - .cra_driver_name =3D "sha256-talitos", - .cra_blocksize =3D SHA256_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUA | - DESC_HDR_MODE0_MDEU_SHA256, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D SHA384_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "sha384", - .cra_driver_name =3D "sha384-talitos", - .cra_blocksize =3D SHA384_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUB | - DESC_HDR_MODE0_MDEUB_SHA384, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D SHA512_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "sha512", - .cra_driver_name =3D "sha512-talitos", - .cra_blocksize =3D SHA512_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUB | - DESC_HDR_MODE0_MDEUB_SHA512, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D MD5_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "hmac(md5)", - .cra_driver_name =3D "hmac-md5-talitos", - .cra_blocksize =3D MD5_HMAC_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUA | - DESC_HDR_MODE0_MDEU_MD5, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D SHA1_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "hmac(sha1)", - .cra_driver_name =3D "hmac-sha1-talitos", - .cra_blocksize =3D SHA1_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUA | - DESC_HDR_MODE0_MDEU_SHA1, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D SHA224_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "hmac(sha224)", - .cra_driver_name =3D "hmac-sha224-talitos", - .cra_blocksize =3D SHA224_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUA | - DESC_HDR_MODE0_MDEU_SHA224, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D SHA256_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "hmac(sha256)", - .cra_driver_name =3D "hmac-sha256-talitos", - .cra_blocksize =3D SHA256_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUA | - DESC_HDR_MODE0_MDEU_SHA256, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D SHA384_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "hmac(sha384)", - .cra_driver_name =3D "hmac-sha384-talitos", - .cra_blocksize =3D SHA384_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUB | - DESC_HDR_MODE0_MDEUB_SHA384, - }, - { .type =3D CRYPTO_ALG_TYPE_AHASH, - .alg.hash =3D { - .halg.digestsize =3D SHA512_DIGEST_SIZE, - .halg.statesize =3D sizeof(struct talitos_export_state), - .halg.base =3D { - .cra_name =3D "hmac(sha512)", - .cra_driver_name =3D "hmac-sha512-talitos", - .cra_blocksize =3D SHA512_BLOCK_SIZE, - .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_AHASH_ALG_BLOCK_ONLY, - } - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_MDEUB | - DESC_HDR_MODE0_MDEUB_SHA512, +#define TALITOS_HASH_ALG_COMMON(name, driver_name, digest_size, block_size= , template, \ + set_key) \ + { \ + .type =3D CRYPTO_ALG_TYPE_AHASH, \ + .alg.hash =3D { \ + .init_tfm =3D talitos_cra_init_ahash, \ + .exit_tfm =3D talitos_cra_exit_ahash, \ + .init =3D ahash_init, \ + .update =3D ahash_update, \ + .final =3D ahash_final, \ + .finup =3D ahash_finup, \ + .digest =3D ahash_digest, \ + .setkey =3D set_key, \ + .import =3D ahash_import, \ + .export =3D ahash_export, \ + .halg.digestsize =3D digest_size, \ + .halg.statesize =3D sizeof(struct talitos_export_state), \ + .halg.base =3D { \ + .cra_name =3D name, \ + .cra_driver_name =3D driver_name"-talitos", \ + .cra_blocksize =3D block_size, \ + .cra_reqsize =3D sizeof(struct talitos_ahash_req_ctx), \ + .cra_flags =3D CRYPTO_ALG_ASYNC | \ + CRYPTO_ALG_ALLOCATES_MEMORY | \ + CRYPTO_ALG_KERN_DRIVER_ONLY | \ + CRYPTO_AHASH_ALG_BLOCK_ONLY, \ + .cra_priority =3D TALITOS_CRA_PRIORITY, \ + .cra_ctxsize =3D sizeof(struct talitos_ctx), \ + .cra_module =3D THIS_MODULE, \ + }, \ + }, \ + .desc_hdr_template =3D template, \ } + +#define TALITOS_HASH_ALG(name, digest_size, block_size, desc_hdr_template)= \ + TALITOS_HASH_ALG_COMMON(name, name, digest_size, block_size, \ + desc_hdr_template, NULL) + +#define TALITOS_HMAC_HASH_ALG(name, digest_size, block_size, = \ + desc_hdr_template) \ + TALITOS_HASH_ALG_COMMON("hmac(" name ")", "hmac-" name, \ + digest_size, block_size, \ + desc_hdr_template, ahash_setkey) + +static const struct talitos_alg_template hash_driver_algs[] =3D { + TALITOS_HASH_ALG("md5", MD5_DIGEST_SIZE, MD5_HMAC_BLOCK_SIZE, + DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUA | DESC_HDR_MODE0_MDEU_MD5), + + TALITOS_HASH_ALG("sha1", SHA1_DIGEST_SIZE, SHA1_BLOCK_SIZE, + DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUA | + DESC_HDR_MODE0_MDEU_SHA1), + + TALITOS_HASH_ALG("sha224", SHA224_DIGEST_SIZE, SHA224_BLOCK_SIZE, + DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUA | + DESC_HDR_MODE0_MDEU_SHA224), + + TALITOS_HASH_ALG("sha256", SHA256_DIGEST_SIZE, SHA256_BLOCK_SIZE, + DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUA | + DESC_HDR_MODE0_MDEU_SHA256), + + TALITOS_HASH_ALG("sha384", SHA384_DIGEST_SIZE, SHA384_BLOCK_SIZE, + DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUB | + DESC_HDR_MODE0_MDEUB_SHA384), + + TALITOS_HASH_ALG("sha512", SHA512_DIGEST_SIZE, SHA512_BLOCK_SIZE, + DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUB | + DESC_HDR_MODE0_MDEUB_SHA512), + + /* HMAC */ + + TALITOS_HMAC_HASH_ALG("md5", MD5_DIGEST_SIZE, MD5_HMAC_BLOCK_SIZE, + DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUA | + DESC_HDR_MODE0_MDEU_MD5), + + TALITOS_HMAC_HASH_ALG("sha1", SHA1_DIGEST_SIZE, SHA1_BLOCK_SIZE, + DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUA | + DESC_HDR_MODE0_MDEU_SHA1), + + TALITOS_HMAC_HASH_ALG("sha224", SHA224_DIGEST_SIZE, SHA224_BLOCK_SIZE, + DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUA | + DESC_HDR_MODE0_MDEU_SHA224), + + TALITOS_HMAC_HASH_ALG("sha256", SHA256_DIGEST_SIZE, SHA256_BLOCK_SIZE, + DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUA | + DESC_HDR_MODE0_MDEU_SHA256), + + TALITOS_HMAC_HASH_ALG("sha384", SHA384_DIGEST_SIZE, SHA384_BLOCK_SIZE, + DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUB | + DESC_HDR_MODE0_MDEUB_SHA384), + + TALITOS_HMAC_HASH_ALG("sha512", SHA512_DIGEST_SIZE, SHA512_BLOCK_SIZE, + DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_MDEUB | + DESC_HDR_MODE0_MDEUB_SHA512), }; =20 int talitos_register_hash(struct device *dev) @@ -850,18 +690,6 @@ int talitos_register_hash(struct device *dev) ahash_alg =3D &talitos_alg_template.alg.hash; alg =3D &ahash_alg->halg.base; =20 - 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Use macro for algorithm definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-7-3-rc2_talitos_cleanup-v7-14-9a45261fc097@bootlin.com> References: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> In-Reply-To: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> To: Herbert Xu , "David S. Miller" Cc: Paul Louvel , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Christophe Leroy , "Christophe Leroy (CS GROUP)" X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790176746; l=9109; i=paul.louvel@bootlin.com; s=20260313; h=from:subject:message-id; bh=brEGUYZKaNNO3u6r1PMA7TjGMwU57Zrw9OoF9YO2U04=; b=HUZikNYY8dsZCG3n/pSyoaGBIa07XVg8Qvhtw0uS9I7wIEVZcGCR/u5D1ydD+uq7Mu5fV6B/W xmf6ZONFbhlAY+dmMqmpHAO+u/S1M3k2HDiNfern6xII626+PzydtcR X-Developer-Key: i=paul.louvel@bootlin.com; a=ed25519; pk=eLW50NT18UAvUT5cAcYf88zNbBCZDLFXuptpyLVhVIU= X-Last-TLS-Session-Version: TLSv1.3 Replace the repetitive struct initializer entries with preprocessor macros. The fallback setkey assignment (skcipher_alg->setkey ?: skcipher_setkey) is no longer needed because each macro specifies the correct setkey handler directly. Reviewed-by: Christophe Leroy (CS GROUP) Signed-off-by: Paul Louvel --- drivers/crypto/talitos/talitos-skcipher.c | 212 ++++++++++++--------------= ---- 1 file changed, 82 insertions(+), 130 deletions(-) diff --git a/drivers/crypto/talitos/talitos-skcipher.c b/drivers/crypto/tal= itos/talitos-skcipher.c index 6c60ad6aa9be..8360181840f6 100644 --- a/drivers/crypto/talitos/talitos-skcipher.c +++ b/drivers/crypto/talitos/talitos-skcipher.c @@ -237,131 +237,89 @@ static void talitos_cra_exit_skcipher(struct crypto_= skcipher *tfm) talitos_cra_exit(crypto_skcipher_tfm(tfm)); } =20 +#define TALITOS_SKCIPHER_ALG_COMMON(name, driver_name, blk_sz, iv_sz, min_= ksz, max_ksz, \ + set_key, desc_template) \ + { \ + .type =3D CRYPTO_ALG_TYPE_SKCIPHER, \ + .alg.skcipher =3D { \ + .base.cra_name =3D name, \ + .base.cra_driver_name =3D driver_name"-talitos", \ + .base.cra_blocksize =3D blk_sz, \ + .base.cra_flags =3D CRYPTO_ALG_ASYNC | \ + CRYPTO_ALG_ALLOCATES_MEMORY | \ + CRYPTO_ALG_KERN_DRIVER_ONLY, \ + .base.cra_priority =3D TALITOS_CRA_PRIORITY, \ + .base.cra_ctxsize =3D sizeof(struct talitos_ctx), \ + .base.cra_module =3D THIS_MODULE, \ + .min_keysize =3D min_ksz, \ + .max_keysize =3D max_ksz, \ + .ivsize =3D iv_sz, \ + .setkey =3D set_key, \ + .init =3D talitos_cra_init_skcipher, \ + .exit =3D talitos_cra_exit_skcipher, \ + .encrypt =3D skcipher_encrypt, \ + .decrypt =3D skcipher_decrypt, \ + }, \ + .desc_hdr_template =3D desc_template, \ + } + +#define TALITOS_SKCIPHER_ALG_AES(name, driver_name, blk_sz, iv_sz, desc_te= mplate) \ + TALITOS_SKCIPHER_ALG_COMMON(name, driver_name, blk_sz, iv_sz, AES_MIN_KEY= _SIZE, \ + AES_MAX_KEY_SIZE, skcipher_aes_setkey, \ + desc_template) + +#define TALITOS_SKCIPHER_ALG_DES(name, driver_name, blk_sz, iv_sz, desc_te= mplate) \ + TALITOS_SKCIPHER_ALG_COMMON(name, driver_name, blk_sz, iv_sz, DES_KEY_SIZ= E, \ + DES_KEY_SIZE, skcipher_des_setkey, \ + desc_template) + +#define TALITOS_SKCIPHER_ALG_DES3(name, driver_name, blk_sz, iv_sz, desc_t= emplate) \ + TALITOS_SKCIPHER_ALG_COMMON(name, driver_name, blk_sz, iv_sz, DES3_EDE_KE= Y_SIZE, \ + DES3_EDE_KEY_SIZE, skcipher_des3_setkey, \ + desc_template) + static const struct talitos_alg_template skcipher_driver_algs[] =3D { - { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, - .alg.skcipher =3D { - .base.cra_name =3D "ecb(aes)", - .base.cra_driver_name =3D "ecb-aes-talitos", - .base.cra_blocksize =3D AES_BLOCK_SIZE, - .base.cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - .min_keysize =3D AES_MIN_KEY_SIZE, - .max_keysize =3D AES_MAX_KEY_SIZE, - .setkey =3D skcipher_aes_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_AESU, - }, - { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, - .alg.skcipher =3D { - .base.cra_name =3D "cbc(aes)", - .base.cra_driver_name =3D "cbc-aes-talitos", - .base.cra_blocksize =3D AES_BLOCK_SIZE, - .base.cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - .min_keysize =3D AES_MIN_KEY_SIZE, - .max_keysize =3D AES_MAX_KEY_SIZE, - .ivsize =3D AES_BLOCK_SIZE, - .setkey =3D skcipher_aes_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC, - }, - { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, - .alg.skcipher =3D { - .base.cra_name =3D "ctr(aes)", - .base.cra_driver_name =3D "ctr-aes-talitos", - .base.cra_blocksize =3D 1, - .base.cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - .min_keysize =3D AES_MIN_KEY_SIZE, - .max_keysize =3D AES_MAX_KEY_SIZE, - .ivsize =3D AES_BLOCK_SIZE, - .setkey =3D skcipher_aes_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_AESU_CTR_NONSNOOP | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CTR, - }, - { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, - .alg.skcipher =3D { - .base.cra_name =3D "ctr(aes)", - .base.cra_driver_name =3D "ctr-aes-talitos", - .base.cra_blocksize =3D 1, - .base.cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - .min_keysize =3D AES_MIN_KEY_SIZE, - .max_keysize =3D AES_MAX_KEY_SIZE, - .ivsize =3D AES_BLOCK_SIZE, - .setkey =3D skcipher_aes_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CTR, - }, - { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, - .alg.skcipher =3D { - .base.cra_name =3D "ecb(des)", - .base.cra_driver_name =3D "ecb-des-talitos", - .base.cra_blocksize =3D DES_BLOCK_SIZE, - .base.cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - .min_keysize =3D DES_KEY_SIZE, - .max_keysize =3D DES_KEY_SIZE, - .setkey =3D skcipher_des_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_DEU, - }, - { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, - .alg.skcipher =3D { - .base.cra_name =3D "cbc(des)", - .base.cra_driver_name =3D "cbc-des-talitos", - .base.cra_blocksize =3D DES_BLOCK_SIZE, - .base.cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - .min_keysize =3D DES_KEY_SIZE, - .max_keysize =3D DES_KEY_SIZE, - .ivsize =3D DES_BLOCK_SIZE, - .setkey =3D skcipher_des_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC, - }, - { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, - .alg.skcipher =3D { - .base.cra_name =3D "ecb(des3_ede)", - .base.cra_driver_name =3D "ecb-3des-talitos", - .base.cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .base.cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - .min_keysize =3D DES3_EDE_KEY_SIZE, - .max_keysize =3D DES3_EDE_KEY_SIZE, - .setkey =3D skcipher_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_3DES, - }, - { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, - .alg.skcipher =3D { - .base.cra_name =3D "cbc(des3_ede)", - .base.cra_driver_name =3D "cbc-3des-talitos", - .base.cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .base.cra_flags =3D CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - .min_keysize =3D DES3_EDE_KEY_SIZE, - .max_keysize =3D DES3_EDE_KEY_SIZE, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .setkey =3D skcipher_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES, - }, + /* AES */ + + TALITOS_SKCIPHER_ALG_AES("ecb(aes)", "ecb-aes", AES_BLOCK_SIZE, 0, + DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_AESU), + + TALITOS_SKCIPHER_ALG_AES("cbc(aes)", "cbc-aes", AES_BLOCK_SIZE, AES_BLOCK= _SIZE, + DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC), + + TALITOS_SKCIPHER_ALG_AES("ctr(aes)", "ctr-aes", 1, AES_BLOCK_SIZE, + DESC_HDR_TYPE_AESU_CTR_NONSNOOP | + DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CTR), + + TALITOS_SKCIPHER_ALG_AES("ctr(aes)", "ctr-aes", 1, AES_BLOCK_SIZE, + DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CTR), + /* DES */ + + TALITOS_SKCIPHER_ALG_DES("ecb(des)", "ecb-des", DES_BLOCK_SIZE, 0, + DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_DEU), + + TALITOS_SKCIPHER_ALG_DES("cbc(des)", "cbc-des", DES_BLOCK_SIZE, DES_BLOCK= _SIZE, + DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC), + /* DES3 */ + + TALITOS_SKCIPHER_ALG_DES3("ecb(des3_ede)", "ecb-3des", DES3_EDE_BLOCK_SIZ= E, 0, + DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | + DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_3DES), + + TALITOS_SKCIPHER_ALG_DES3( + "cbc(des3_ede)", "cbc-3des", DES3_EDE_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE, + DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES), }; =20 int talitos_register_skcipher(struct device *dev) @@ -386,12 +344,6 @@ int talitos_register_skcipher(struct device *dev) if (has_ftr_sec1(priv)) alg->cra_alignmask =3D 3; =20 - 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Use macro for algorithm definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-7-3-rc2_talitos_cleanup-v7-15-9a45261fc097@bootlin.com> References: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> In-Reply-To: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> To: Herbert Xu , "David S. Miller" Cc: Paul Louvel , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Christophe Leroy , "Christophe Leroy (CS GROUP)" X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790176746; l=28746; i=paul.louvel@bootlin.com; s=20260313; h=from:subject:message-id; bh=yl2oSYq28HHoD/I6T9naGGTG/87ynXJdLMVArr7HCWo=; b=wF0FMbpIImByGy4Ma7k00lJGZJb26mTu/usXjEBo/3M6MAjWcOINcrhDMeC6jDj0TsSZ0lvMJ Wuedj7TiXG3DxurBbHsZzDMUXBTYj0uHl1/TgHMU6xL47KaXL0Fk2PB X-Developer-Key: i=paul.louvel@bootlin.com; a=ed25519; pk=eLW50NT18UAvUT5cAcYf88zNbBCZDLFXuptpyLVhVIU= X-Last-TLS-Session-Version: TLSv1.3 Replace the repetitive struct initializer entries with preprocessor macros. The fallback setkey assignment (aead_alg->setkey ?: aead_setkey) is replaced by specifying the correct setkey handler directly in each macro invocation. Reviewed-by: Christophe Leroy (CS GROUP) Signed-off-by: Paul Louvel --- drivers/crypto/talitos/talitos-aead.c | 771 +++++++++++-------------------= ---- 1 file changed, 238 insertions(+), 533 deletions(-) diff --git a/drivers/crypto/talitos/talitos-aead.c b/drivers/crypto/talitos= /talitos-aead.c index 0504b8575e26..60bc727f76dc 100644 --- a/drivers/crypto/talitos/talitos-aead.c +++ b/drivers/crypto/talitos/talitos-aead.c @@ -405,535 +405,245 @@ static void talitos_cra_exit_aead(struct crypto_aea= d *tfm) talitos_cra_exit(crypto_aead_tfm(tfm)); } =20 +#define TALITOS_AEAD_ALG_COMMON(name, driver_name, name_prefix, set_key, b= lock_size, \ + max_auth_size, template, priority) \ + { \ + .type =3D CRYPTO_ALG_TYPE_AEAD, \ + .alg.aead =3D { \ + .base =3D { \ + .cra_name =3D name, \ + .cra_driver_name =3D driver_name"-talitos"name_prefix, \ + .cra_blocksize =3D block_size, \ + .cra_flags =3D CRYPTO_ALG_ASYNC | \ + CRYPTO_ALG_ALLOCATES_MEMORY | \ + CRYPTO_ALG_KERN_DRIVER_ONLY, \ + .cra_priority =3D (priority), \ + .cra_ctxsize =3D sizeof(struct talitos_ctx), \ + .cra_module =3D THIS_MODULE, \ + }, \ + .ivsize =3D block_size, \ + .maxauthsize =3D max_auth_size, \ + .setkey =3D set_key, \ + .init =3D talitos_cra_init_aead, \ + .exit =3D talitos_cra_exit_aead, \ + .encrypt =3D aead_encrypt, \ + .decrypt =3D aead_decrypt, \ + }, \ + .desc_hdr_template =3D template, \ + } + +#define TALITOS_AEAD_ALG(name, driver_name, set_key, block_size, max_auth_= size, template) \ + TALITOS_AEAD_ALG_COMMON(name, driver_name, "", set_key, block_size, max_a= uth_size, \ + template, TALITOS_CRA_PRIORITY) + +#define TALITOS_AEAD_ALG_HSNA(name, driver_name, set_key, block_size, max_= auth_size, \ + template) \ + TALITOS_AEAD_ALG_COMMON(name, driver_name, "-hsna", set_key, block_size, = \ + max_auth_size, template, \ + TALITOS_CRA_PRIORITY_AEAD_HSNA) + static const struct talitos_alg_template aead_driver_algs[] =3D { - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha1),cbc(aes))", - .cra_driver_name =3D "authenc-hmac-sha1-" - "cbc-aes-talitos", - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D AES_BLOCK_SIZE, - .maxauthsize =3D SHA1_DIGEST_SIZE, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA1_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha1),cbc(aes))", - .cra_driver_name =3D "authenc-hmac-sha1-" - "cbc-aes-talitos-hsna", - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D AES_BLOCK_SIZE, - .maxauthsize =3D SHA1_DIGEST_SIZE, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA1_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha1)," - "cbc(des3_ede))", - .cra_driver_name =3D "authenc-hmac-sha1-" - "cbc-3des-talitos", - .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .maxauthsize =3D SHA1_DIGEST_SIZE, - .setkey =3D aead_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA1_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha1)," - "cbc(des3_ede))", - .cra_driver_name =3D "authenc-hmac-sha1-" - "cbc-3des-talitos-hsna", - .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .maxauthsize =3D SHA1_DIGEST_SIZE, - .setkey =3D aead_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA1_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha224),cbc(aes))", - .cra_driver_name =3D "authenc-hmac-sha224-" - "cbc-aes-talitos", - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D AES_BLOCK_SIZE, - .maxauthsize =3D SHA224_DIGEST_SIZE, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA224_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha224),cbc(aes))", - .cra_driver_name =3D "authenc-hmac-sha224-" - "cbc-aes-talitos-hsna", - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D AES_BLOCK_SIZE, - .maxauthsize =3D SHA224_DIGEST_SIZE, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA224_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha224)," - "cbc(des3_ede))", - .cra_driver_name =3D "authenc-hmac-sha224-" - "cbc-3des-talitos", - .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .maxauthsize =3D SHA224_DIGEST_SIZE, - .setkey =3D aead_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA224_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha224)," - "cbc(des3_ede))", - .cra_driver_name =3D "authenc-hmac-sha224-" - "cbc-3des-talitos-hsna", - .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .maxauthsize =3D SHA224_DIGEST_SIZE, - .setkey =3D aead_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA224_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha256),cbc(aes))", - .cra_driver_name =3D "authenc-hmac-sha256-" - "cbc-aes-talitos", - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D AES_BLOCK_SIZE, - .maxauthsize =3D SHA256_DIGEST_SIZE, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA256_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha256),cbc(aes))", - .cra_driver_name =3D "authenc-hmac-sha256-" - "cbc-aes-talitos-hsna", - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D AES_BLOCK_SIZE, - .maxauthsize =3D SHA256_DIGEST_SIZE, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA256_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha256)," - "cbc(des3_ede))", - .cra_driver_name =3D "authenc-hmac-sha256-" - "cbc-3des-talitos", - .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .maxauthsize =3D SHA256_DIGEST_SIZE, - .setkey =3D aead_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA256_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha256)," - "cbc(des3_ede))", - .cra_driver_name =3D "authenc-hmac-sha256-" - "cbc-3des-talitos-hsna", - .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .maxauthsize =3D SHA256_DIGEST_SIZE, - .setkey =3D aead_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_SHA256_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha384),cbc(aes))", - .cra_driver_name =3D "authenc-hmac-sha384-" - "cbc-aes-talitos", - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D AES_BLOCK_SIZE, - .maxauthsize =3D SHA384_DIGEST_SIZE, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC | - DESC_HDR_SEL1_MDEUB | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEUB_SHA384_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha384)," - "cbc(des3_ede))", - .cra_driver_name =3D "authenc-hmac-sha384-" - "cbc-3des-talitos", - .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .maxauthsize =3D SHA384_DIGEST_SIZE, - .setkey =3D aead_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES | - DESC_HDR_SEL1_MDEUB | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEUB_SHA384_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha512),cbc(aes))", - .cra_driver_name =3D "authenc-hmac-sha512-" - "cbc-aes-talitos", - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D AES_BLOCK_SIZE, - .maxauthsize =3D SHA512_DIGEST_SIZE, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC | - DESC_HDR_SEL1_MDEUB | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEUB_SHA512_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(sha512)," - "cbc(des3_ede))", - .cra_driver_name =3D "authenc-hmac-sha512-" - "cbc-3des-talitos", - .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .maxauthsize =3D SHA512_DIGEST_SIZE, - .setkey =3D aead_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES | - DESC_HDR_SEL1_MDEUB | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEUB_SHA512_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(md5),cbc(aes))", - .cra_driver_name =3D "authenc-hmac-md5-" - "cbc-aes-talitos", - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D AES_BLOCK_SIZE, - .maxauthsize =3D MD5_DIGEST_SIZE, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_MD5_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(md5),cbc(aes))", - .cra_driver_name =3D "authenc-hmac-md5-" - "cbc-aes-talitos-hsna", - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D AES_BLOCK_SIZE, - .maxauthsize =3D MD5_DIGEST_SIZE, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | - DESC_HDR_SEL0_AESU | - DESC_HDR_MODE0_AESU_CBC | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_MD5_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(md5),cbc(des3_ede))", - .cra_driver_name =3D "authenc-hmac-md5-" - "cbc-3des-talitos", - .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .maxauthsize =3D MD5_DIGEST_SIZE, - .setkey =3D aead_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_IPSEC_ESP | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_MD5_HMAC, - }, - { .type =3D CRYPTO_ALG_TYPE_AEAD, - .alg.aead =3D { - .base =3D { - .cra_name =3D "authenc(hmac(md5),cbc(des3_ede))", - .cra_driver_name =3D "authenc-hmac-md5-" - "cbc-3des-talitos-hsna", - .cra_blocksize =3D DES3_EDE_BLOCK_SIZE, - .cra_module =3D THIS_MODULE, - .cra_priority =3D TALITOS_CRA_PRIORITY_AEAD_HSNA, - .cra_ctxsize =3D sizeof(struct talitos_ctx), - .cra_flags =3D CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC | - CRYPTO_ALG_ALLOCATES_MEMORY, - }, - .ivsize =3D DES3_EDE_BLOCK_SIZE, - .maxauthsize =3D MD5_DIGEST_SIZE, - .setkey =3D aead_des3_setkey, - }, - .desc_hdr_template =3D DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | - DESC_HDR_SEL0_DEU | - DESC_HDR_MODE0_DEU_CBC | - DESC_HDR_MODE0_DEU_3DES | - DESC_HDR_SEL1_MDEUA | - DESC_HDR_MODE1_MDEU_INIT | - DESC_HDR_MODE1_MDEU_PAD | - DESC_HDR_MODE1_MDEU_MD5_HMAC, - }, + /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */ + + /* sha1 auth */ + + TALITOS_AEAD_ALG("authenc(hmac(sha1),cbc(aes))", + "authenc-hmac-sha1-cbc-aes", aead_setkey, + AES_BLOCK_SIZE, SHA1_DIGEST_SIZE, + DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA1_HMAC), + + TALITOS_AEAD_ALG_HSNA( + "authenc(hmac(sha1),cbc(aes))", + "authenc-hmac-sha1-cbc-aes", aead_setkey, AES_BLOCK_SIZE, + SHA1_DIGEST_SIZE, + DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA1_HMAC), + + TALITOS_AEAD_ALG("authenc(hmac(sha1),cbc(des3_ede))", + "authenc-hmac-sha1-cbc-3des", aead_des3_setkey, + DES3_EDE_BLOCK_SIZE, SHA1_DIGEST_SIZE, + DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | + DESC_HDR_MODE0_DEU_3DES | DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA1_HMAC), + + TALITOS_AEAD_ALG_HSNA( + "authenc(hmac(sha1),cbc(des3_ede))", + "authenc-hmac-sha1-cbc-3des", aead_des3_setkey, + DES3_EDE_BLOCK_SIZE, SHA1_DIGEST_SIZE, + DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES | + DESC_HDR_SEL1_MDEUA | DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA1_HMAC), + + /* sha224 auth */ + + TALITOS_AEAD_ALG("authenc(hmac(sha224),cbc(aes))", + "authenc-hmac-sha224-cbc-aes", aead_setkey, + AES_BLOCK_SIZE, SHA224_DIGEST_SIZE, + DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA224_HMAC), + + TALITOS_AEAD_ALG_HSNA( + "authenc(hmac(sha224),cbc(aes))", + "authenc-hmac-sha224-cbc-aes", aead_setkey, AES_BLOCK_SIZE, + SHA224_DIGEST_SIZE, + DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA224_HMAC), + + TALITOS_AEAD_ALG( + "authenc(hmac(sha224),cbc(des3_ede))", + "authenc-hmac-sha224-cbc-3des", aead_des3_setkey, + DES3_EDE_BLOCK_SIZE, SHA224_DIGEST_SIZE, + DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES | + DESC_HDR_SEL1_MDEUA | DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA224_HMAC), + + TALITOS_AEAD_ALG_HSNA( + "authenc(hmac(sha224),cbc(des3_ede))", + "authenc-hmac-sha224-cbc-3des", aead_des3_setkey, + DES3_EDE_BLOCK_SIZE, SHA224_DIGEST_SIZE, + DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES | + DESC_HDR_SEL1_MDEUA | DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA224_HMAC), + + /* sha256 auth */ + + TALITOS_AEAD_ALG("authenc(hmac(sha256),cbc(aes))", + "authenc-hmac-sha256-cbc-aes", aead_setkey, + AES_BLOCK_SIZE, SHA256_DIGEST_SIZE, + DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA256_HMAC), + + TALITOS_AEAD_ALG_HSNA( + "authenc(hmac(sha256),cbc(aes))", + "authenc-hmac-sha256-cbc-aes", aead_setkey, AES_BLOCK_SIZE, + SHA256_DIGEST_SIZE, + DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA256_HMAC), + + TALITOS_AEAD_ALG( + "authenc(hmac(sha256),cbc(des3_ede))", + "authenc-hmac-sha256-cbc-3des", aead_des3_setkey, + DES3_EDE_BLOCK_SIZE, SHA256_DIGEST_SIZE, + DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES | + DESC_HDR_SEL1_MDEUA | DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA256_HMAC), + + TALITOS_AEAD_ALG_HSNA( + "authenc(hmac(sha256),cbc(des3_ede))", + "authenc-hmac-sha256-cbc-3des", aead_des3_setkey, + DES3_EDE_BLOCK_SIZE, SHA256_DIGEST_SIZE, + DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES | + DESC_HDR_SEL1_MDEUA | DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_SHA256_HMAC), + + /* sha384 auth */ + + TALITOS_AEAD_ALG("authenc(hmac(sha384),cbc(aes))", + "authenc-hmac-sha384-cbc-aes", aead_setkey, + AES_BLOCK_SIZE, SHA384_DIGEST_SIZE, + DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUB | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEUB_SHA384_HMAC), + + TALITOS_AEAD_ALG( + "authenc(hmac(sha384),cbc(des3_ede))", + "authenc-hmac-sha384-cbc-3des", aead_des3_setkey, + DES3_EDE_BLOCK_SIZE, SHA384_DIGEST_SIZE, + DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES | + DESC_HDR_SEL1_MDEUB | DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEUB_SHA384_HMAC), + + /* sha512 auth */ + + TALITOS_AEAD_ALG("authenc(hmac(sha512),cbc(aes))", + "authenc-hmac-sha512-cbc-aes", aead_setkey, + AES_BLOCK_SIZE, SHA512_DIGEST_SIZE, + DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUB | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEUB_SHA512_HMAC), + + TALITOS_AEAD_ALG( + "authenc(hmac(sha512),cbc(des3_ede))", + "authenc-hmac-sha512-cbc-3des", aead_des3_setkey, + DES3_EDE_BLOCK_SIZE, SHA512_DIGEST_SIZE, + DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES | + DESC_HDR_SEL1_MDEUB | DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEUB_SHA512_HMAC), + + /* md5 auth */ + + TALITOS_AEAD_ALG("authenc(hmac(md5),cbc(aes))", + "authenc-hmac-md5-cbc-aes", aead_setkey, + AES_BLOCK_SIZE, MD5_DIGEST_SIZE, + DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_MD5_HMAC), + + TALITOS_AEAD_ALG_HSNA( + "authenc(hmac(md5),cbc(aes))", + "authenc-hmac-md5-cbc-aes", aead_setkey, AES_BLOCK_SIZE, + MD5_DIGEST_SIZE, + DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_AESU | + DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA | + DESC_HDR_MODE1_MDEU_INIT | DESC_HDR_MODE1_MDEU_PAD | + DESC_HDR_MODE1_MDEU_MD5_HMAC), + + TALITOS_AEAD_ALG( + "authenc(hmac(md5),cbc(des3_ede))", + "authenc-hmac-md5-cbc-3des", aead_des3_setkey, + DES3_EDE_BLOCK_SIZE, MD5_DIGEST_SIZE, + DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES | + DESC_HDR_SEL1_MDEUA | DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | DESC_HDR_MODE1_MDEU_MD5_HMAC), + + TALITOS_AEAD_ALG_HSNA( + "authenc(hmac(md5),cbc(des3_ede))", + "authenc-hmac-md5-cbc-3des", aead_des3_setkey, + DES3_EDE_BLOCK_SIZE, MD5_DIGEST_SIZE, + DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_DEU | + DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES | + DESC_HDR_SEL1_MDEUA | DESC_HDR_MODE1_MDEU_INIT | + DESC_HDR_MODE1_MDEU_PAD | DESC_HDR_MODE1_MDEU_MD5_HMAC), }; =20 int talitos_register_aead(struct device *dev) @@ -958,11 +668,6 @@ int talitos_register_aead(struct device *dev) if (has_ftr_sec1(priv)) alg->cra_alignmask =3D 3; =20 - aead_alg->init =3D talitos_cra_init_aead; - aead_alg->exit =3D talitos_cra_exit_aead; - aead_alg->setkey =3D aead_alg->setkey ?: aead_setkey; - aead_alg->encrypt =3D aead_encrypt; - aead_alg->decrypt =3D aead_decrypt; if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) && !strncmp(alg->cra_name, "authenc(hmac(sha224)", 20)) { continue; --=20 2.55.0 From nobody Thu Sep 24 13:42:19 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with 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ESMTPSA id 816FE103293DD; Wed, 23 Sep 2026 17:19:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1790176783; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=MxFaqSud2FbxZOmjcku59Pam3q+0Cj3zDTCvy1pOz94=; b=OSsH+9psOQCJzhlRbrv3eRJ7U5G+AgYpcsHYwTRXOYUYT5O3BLudehAue1oBnr1hL+Zlyh MmLIoVYDm54QTNege0g/i58uR/0ocW/dhPo5MnV+//TkctANu5nC5GLLGQiLC/q9MFSbS+ APvLIvKNK1/RdiuJhGm7bLoF7RGzB2sr5GbDgPOQTHysbXC2hAZ4cDFlMG6LHs8KEm3rlv iXlLcbY3qbnfITBs9H7DzKNQSSsaa5GD2dYWSt00e8eOAq9vrD32o9alUtwBZhF+r670YI hDxEG7TEs6X9GaeryjjIFP0E6Bpdlex4mBiVuBd+cJ+UEEv+feKeQMXaPBBZFg== From: Paul Louvel Date: Wed, 23 Sep 2026 17:18:52 +0200 Subject: [PATCH v7 16/20] crypto: talitos - Introduce is_sec1() helper with static key support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-7-3-rc2_talitos_cleanup-v7-16-9a45261fc097@bootlin.com> References: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> In-Reply-To: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> To: Herbert Xu , "David S. Miller" Cc: Paul Louvel , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Christophe Leroy X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790176746; l=2782; i=paul.louvel@bootlin.com; s=20260313; h=from:subject:message-id; bh=7zAZ4YWhskjZWdVSZa3f4oJgUtaSBESE65CAzuiXhiA=; b=pGRCnVMfXduJtu+IPU7Rh8hThCPKBS1XYHPbpJ1tvaRTiKmzBBwA6hAQ2OYsNLs04kDLhua1n xLfI19ZY25NCB78LdsMZMPC/lAszcDrc1xQiTvmGAzWat26Vjlscb8g X-Developer-Key: i=paul.louvel@bootlin.com; a=ed25519; pk=eLW50NT18UAvUT5cAcYf88zNbBCZDLFXuptpyLVhVIU= X-Last-TLS-Session-Version: TLSv1.3 In preparation for per-SEC-version code paths, introduce an is_sec1() inline helper that abstracts the SEC version check behind a static key. The goal is to remove all bool is_sec1 parameters from the call chain via the is_sec1() helper. Signed-off-by: Paul Louvel --- drivers/crypto/talitos/talitos-core.c | 10 +++++++++- drivers/crypto/talitos/talitos.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/talitos/talitos-core.c b/drivers/crypto/talitos= /talitos-core.c index 6d1063502285..9450be5c80f3 100644 --- a/drivers/crypto/talitos/talitos-core.c +++ b/drivers/crypto/talitos/talitos-core.c @@ -1193,8 +1193,12 @@ static int talitos_probe(struct platform_device *ofd= ev) TALITOS_FTR_SHA224_HWINIT | TALITOS_FTR_HMAC_OK; =20 - if (of_device_is_compatible(np, "fsl,sec1.0")) + if (of_device_is_compatible(np, "fsl,sec1.0")) { priv->features |=3D TALITOS_FTR_SEC1; + talitos_init_branch(true); + } else { + talitos_init_branch(false); + } =20 if (of_device_is_compatible(np, "fsl,sec1.2")) { priv->reg_deu =3D priv->reg + TALITOS12_DEU; @@ -1314,6 +1318,10 @@ static int talitos_probe(struct platform_device *ofd= ev) return err; } =20 +#if defined(CONFIG_CRYPTO_DEV_TALITOS1) && defined(CONFIG_CRYPTO_DEV_TALIT= OS2) +DEFINE_STATIC_KEY_FALSE(talitos_is_sec1); +#endif + static const struct of_device_id talitos_match[] =3D { #ifdef CONFIG_CRYPTO_DEV_TALITOS1 { diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/tali= tos.h index c2fc71282c0b..5927dfe84770 100644 --- a/drivers/crypto/talitos/talitos.h +++ b/drivers/crypto/talitos/talitos.h @@ -14,6 +14,7 @@ #include #include #include +#include #include #include =20 @@ -224,6 +225,33 @@ struct talitos_crypto_alg { #define TALITOS_FTR_HMAC_OK 0x00000008 #define TALITOS_FTR_SEC1 0x00000010 =20 +#if defined(CONFIG_CRYPTO_DEV_TALITOS1) && defined(CONFIG_CRYPTO_DEV_TALIT= OS2) +DECLARE_STATIC_KEY_FALSE(talitos_is_sec1); + +static __always_inline bool is_sec1(void) +{ + return static_branch_unlikely(&talitos_is_sec1); +} + +static inline void talitos_init_branch(bool sec1) +{ + if (sec1) + static_branch_enable(&talitos_is_sec1); +} + +#else + +static __always_inline bool is_sec1(void) +{ + return IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS1); +} + +static inline void talitos_init_branch(bool sec1) +{ +} + +#endif + /* * If both CONFIG_CRYPTO_DEV_TALITOS1 and CONFIG_CRYPTO_DEV_TALITOS2 are * defined, we check the features which are set according to the device tr= ee. --=20 2.55.0 From nobody Thu Sep 24 13:42:19 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4FED53CA71 for ; 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bh=vUzf8M4+BRHObeqQhzmZ2daZo5o4k9LpigCyAZw87As=; b=syjqUUn6fZwBvImmYJgPYyI90ruEWp7ZCjA7BDPi5tHWQ6NzZZqeWpB8VD9zF4UennO2zQ obRUJ3jGhtMpJXNE8BlgJcQho/HACfZXPppsb6TqotAAe86AYkn6Wt2+M3Y3y0uc2EsPRt c6vBIa7QzYN+5ZgsGfbWgzbMKIvyl3vMEpOTrPDxAnhjx14VfWIe36aRMTYWjfESiKkPaa i7Ytt9vG3rst1JZkgR0PpOrBDxA/rZYuegNcTrggtlvNHZZhb2eE/4WVQ0Z6l9HPAiqjHa C0lgIyQdOwHgcbK5atT/pnX28gMZRz4h531F7IAh2qa3J228ZjjFQEpoDnocwQ== From: Paul Louvel Date: Wed, 23 Sep 2026 17:18:53 +0200 Subject: [PATCH v7 17/20] crypto: talitos - Replace has_ftr_sec1() with is_sec1() static key helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-7-3-rc2_talitos_cleanup-v7-17-9a45261fc097@bootlin.com> References: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> In-Reply-To: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> To: Herbert Xu , "David S. Miller" Cc: Paul Louvel , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Christophe Leroy X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790176746; l=28956; i=paul.louvel@bootlin.com; s=20260313; h=from:subject:message-id; bh=qk4PL0+Vf/AeYVc/Lic07hKlEMxBiBw7ekMeX9+IbN0=; b=UJzl55JZSquk3cu/6wluMaseB9kMeRZnkg6A0VdHxWHXmN+RZmxJwEzqlr2AG/Hct+BjSDe2+ 7/SfeLqn0GbAPaG6kB2OsrUHbDZc05D52fG6WmF1ayNWaye8vhM2bb+ X-Developer-Key: i=paul.louvel@bootlin.com; a=ed25519; pk=eLW50NT18UAvUT5cAcYf88zNbBCZDLFXuptpyLVhVIU= X-Last-TLS-Session-Version: TLSv1.3 Now that is_sec1() is available, replace all has_ftr_sec1(priv) calls and the local "bool is_sec1" variables with direct is_sec1() invocations. It removes the requirement that every caller has to either get struct talitos_private out of dev_get_drvdata() or/and pass the is_sec1 parameter to each inline helper. Drop the now-unused has_ftr_sec1() helper. Signed-off-by: Paul Louvel --- drivers/crypto/talitos/talitos-aead.c | 24 +++---- drivers/crypto/talitos/talitos-core.c | 113 +++++++++++++-------------= ---- drivers/crypto/talitos/talitos-hash.c | 26 +++---- drivers/crypto/talitos/talitos-skcipher.c | 15 ++-- drivers/crypto/talitos/talitos.h | 49 ++++--------- 5 files changed, 87 insertions(+), 140 deletions(-) diff --git a/drivers/crypto/talitos/talitos-aead.c b/drivers/crypto/talitos= /talitos-aead.c index 60bc727f76dc..d8058e75fb31 100644 --- a/drivers/crypto/talitos/talitos-aead.c +++ b/drivers/crypto/talitos/talitos-aead.c @@ -208,18 +208,16 @@ static int ipsec_esp(struct talitos_edesc *edesc, str= uct aead_request *areq, int sg_count, ret; int elen =3D 0; bool sync_needed =3D false; - struct talitos_private *priv =3D dev_get_drvdata(dev); - bool is_sec1 =3D has_ftr_sec1(priv); bool is_ipsec_esp =3D desc->hdr & DESC_HDR_TYPE_IPSEC_ESP; struct talitos_ptr *civ_ptr =3D &desc->ptr[is_ipsec_esp ? 2 : 3]; struct talitos_ptr *ckey_ptr =3D &desc->ptr[is_ipsec_esp ? 3 : 2]; dma_addr_t dma_icv =3D edesc->dma_link_tbl + edesc->dma_len - authsize; =20 /* hmac key */ - to_talitos_ptr(&desc->ptr[0], ctx->dma_key, ctx->authkeylen, is_sec1); + to_talitos_ptr(&desc->ptr[0], ctx->dma_key, ctx->authkeylen); =20 sg_count =3D edesc->src_nents ?: 1; - if (is_sec1 && sg_count > 1) + if (is_sec1() && sg_count > 1) sg_copy_to_buffer(areq->src, sg_count, edesc->buf, areq->assoclen + cryptlen); else @@ -237,11 +235,11 @@ static int ipsec_esp(struct talitos_edesc *edesc, str= uct aead_request *areq, } =20 /* cipher iv */ - to_talitos_ptr(civ_ptr, edesc->iv_dma, ivsize, is_sec1); + to_talitos_ptr(civ_ptr, edesc->iv_dma, ivsize); =20 /* cipher key */ to_talitos_ptr(ckey_ptr, ctx->dma_key + ctx->authkeylen, - ctx->enckeylen, is_sec1); + ctx->enckeylen); =20 /* * cipher in @@ -264,7 +262,7 @@ static int ipsec_esp(struct talitos_edesc *edesc, struc= t aead_request *areq, /* cipher out */ if (areq->src !=3D areq->dst) { sg_count =3D edesc->dst_nents ? : 1; - if (!is_sec1 || sg_count =3D=3D 1) + if (!is_sec1() || sg_count =3D=3D 1) dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE); } =20 @@ -281,15 +279,15 @@ static int ipsec_esp(struct talitos_edesc *edesc, str= uct aead_request *areq, struct talitos_ptr *tbl_ptr =3D &edesc->link_tbl[tbl_off]; =20 /* Add an entry to the link table for ICV data */ - to_talitos_ptr_ext_set(tbl_ptr - 1, 0, is_sec1); - to_talitos_ptr_ext_set(tbl_ptr, DESC_PTR_LNKTBL_RET, is_sec1); + to_talitos_ptr_ext_set(tbl_ptr - 1, 0); + to_talitos_ptr_ext_set(tbl_ptr, DESC_PTR_LNKTBL_RET); =20 /* icv data follows link tables */ - to_talitos_ptr(tbl_ptr, dma_icv, authsize, is_sec1); - to_talitos_ptr_ext_or(&desc->ptr[5], authsize, is_sec1); + to_talitos_ptr(tbl_ptr, dma_icv, authsize); + to_talitos_ptr_ext_or(&desc->ptr[5], authsize); sync_needed =3D true; } else if (!encrypt) { - to_talitos_ptr(&desc->ptr[6], dma_icv, authsize, is_sec1); + to_talitos_ptr(&desc->ptr[6], dma_icv, authsize); sync_needed =3D true; } else if (!is_ipsec_esp) { talitos_sg_map(dev, areq->dst, authsize, edesc, &desc->ptr[6], @@ -665,7 +663,7 @@ int talitos_register_aead(struct device *dev) aead_alg =3D &talitos_alg_template.alg.aead; alg =3D &aead_alg->base; =20 - if (has_ftr_sec1(priv)) + if (is_sec1()) alg->cra_alignmask =3D 3; =20 if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) && diff --git a/drivers/crypto/talitos/talitos-core.c b/drivers/crypto/talitos= /talitos-core.c index 9450be5c80f3..6fbaac923bef 100644 --- a/drivers/crypto/talitos/talitos-core.c +++ b/drivers/crypto/talitos/talitos-core.c @@ -46,9 +46,8 @@ static int reset_channel(struct device *dev, int ch) { struct talitos_private *priv =3D dev_get_drvdata(dev); unsigned int timeout =3D TALITOS_TIMEOUT; - bool is_sec1 =3D has_ftr_sec1(priv); =20 - if (is_sec1) { + if (is_sec1()) { setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS1_CCCR_LO_RESET); =20 @@ -73,7 +72,7 @@ static int reset_channel(struct device *dev, int ch) setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE | TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE); /* enable chaining descriptors */ - if (is_sec1) + if (is_sec1()) setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_NE); =20 @@ -89,8 +88,7 @@ static int reset_device(struct device *dev) { struct talitos_private *priv =3D dev_get_drvdata(dev); unsigned int timeout =3D TALITOS_TIMEOUT; - bool is_sec1 =3D has_ftr_sec1(priv); - u32 mcr =3D is_sec1 ? TALITOS1_MCR_SWR : TALITOS2_MCR_SWR; + u32 mcr =3D is_sec1() ? TALITOS1_MCR_SWR : TALITOS2_MCR_SWR; =20 setbits32(priv->reg + TALITOS_MCR, mcr); =20 @@ -118,7 +116,6 @@ static int init_device(struct device *dev) { struct talitos_private *priv =3D dev_get_drvdata(dev); int ch, err; - bool is_sec1 =3D has_ftr_sec1(priv); =20 /* * Master reset @@ -142,7 +139,7 @@ static int init_device(struct device *dev) } =20 /* enable channel done and error interrupts */ - if (is_sec1) { + if (is_sec1()) { clrbits32(priv->reg + TALITOS_IMR, TALITOS1_IMR_INIT); clrbits32(priv->reg + TALITOS_IMR_LO, TALITOS1_IMR_LO_INIT); /* disable parity error check in DEU (erroneous? test vect.) */ @@ -161,14 +158,14 @@ static int init_device(struct device *dev) } =20 static void dma_map_request(struct device *dev, struct talitos_request *re= quest, - struct talitos_desc *desc, bool is_sec1) + struct talitos_desc *desc) { struct talitos_edesc *edesc =3D container_of(desc, struct talitos_edesc, desc); dma_addr_t dma_desc, prev_dma_desc; struct talitos_edesc *prev_edesc =3D NULL; =20 - if (is_sec1) { + if (is_sec1()) { while (edesc) { edesc->desc.hdr1 =3D edesc->desc.hdr; =20 @@ -222,7 +219,6 @@ int talitos_submit(struct device *dev, int ch, struct t= alitos_desc *desc, struct talitos_request *request; unsigned long flags; int head; - bool is_sec1 =3D has_ftr_sec1(priv); =20 spin_lock_irqsave(&priv->chan[ch].head_lock, flags); =20 @@ -236,7 +232,7 @@ int talitos_submit(struct device *dev, int ch, struct t= alitos_desc *desc, request =3D &priv->chan[ch].fifo[head]; =20 /* map descriptor and save caller data */ - dma_map_request(dev, request, desc, is_sec1); + dma_map_request(dev, request, desc); request->callback =3D callback; request->context =3D context; =20 @@ -259,12 +255,12 @@ int talitos_submit(struct device *dev, int ch, struct= talitos_desc *desc, } =20 static __be32 get_request_hdr(struct device *dev, - struct talitos_request *request, bool is_sec1) + struct talitos_request *request) { struct talitos_edesc *edesc; dma_addr_t dma_desc; =20 - if (!is_sec1) { + if (!is_sec1()) { dma_sync_single_for_cpu(dev, request->dma_desc, TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL); =20 @@ -285,11 +281,11 @@ static __be32 get_request_hdr(struct device *dev, } =20 static void dma_unmap_request(struct device *dev, - struct talitos_request *request, bool is_sec1) + struct talitos_request *request) { struct talitos_edesc *edesc; =20 - if (is_sec1) { + if (is_sec1()) { dma_unmap_single(dev, request->dma_desc, TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL); edesc =3D container_of(request->desc, struct talitos_edesc, desc); @@ -314,7 +310,6 @@ static void flush_channel(struct device *dev, int ch, i= nt error, int reset_ch) struct talitos_request *request, saved_req; unsigned long flags; int tail, status; - bool is_sec1 =3D has_ftr_sec1(priv); =20 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags); =20 @@ -326,7 +321,7 @@ static void flush_channel(struct device *dev, int ch, i= nt error, int reset_ch) =20 /* descriptors with their done bits set don't get the error */ rmb(); - hdr =3D get_request_hdr(dev, request, is_sec1); + hdr =3D get_request_hdr(dev, request); =20 if ((hdr & DESC_HDR_DONE) =3D=3D DESC_HDR_DONE) status =3D 0; @@ -336,7 +331,7 @@ static void flush_channel(struct device *dev, int ch, i= nt error, int reset_ch) else status =3D error; =20 - dma_unmap_request(dev, request, is_sec1); + dma_unmap_request(dev, request); =20 /* copy entries so we can call callback outside lock */ saved_req.desc =3D request->desc; @@ -426,13 +421,13 @@ DEF_TALITOS2_DONE(ch0_2, TALITOS2_ISR_CH_0_2_DONE) DEF_TALITOS2_DONE(ch1_3, TALITOS2_ISR_CH_1_3_DONE) =20 static __be32 search_desc_hdr_in_request(struct talitos_request *request, - dma_addr_t cur_desc, bool is_sec1) + dma_addr_t cur_desc) { struct talitos_edesc *edesc; =20 if (request->dma_desc =3D=3D cur_desc) { return request->desc->hdr; - } else if (is_sec1) { + } else if (is_sec1()) { edesc =3D container_of(request->desc, struct talitos_edesc, desc); while (edesc->next_desc) { if (edesc->desc.next_desc =3D=3D cpu_to_be32(cur_desc)) @@ -449,7 +444,6 @@ static __be32 search_desc_hdr_in_request(struct talitos= _request *request, static __be32 current_desc_hdr(struct device *dev, int ch) { struct talitos_private *priv =3D dev_get_drvdata(dev); - bool is_sec1 =3D has_ftr_sec1(priv); struct talitos_request *request; int tail, iter; dma_addr_t cur_desc; @@ -468,7 +462,7 @@ static __be32 current_desc_hdr(struct device *dev, int = ch) do { request =3D &priv->chan[ch].fifo[iter]; =20 - hdr =3D search_desc_hdr_in_request(request, cur_desc, is_sec1); + hdr =3D search_desc_hdr_in_request(request, cur_desc); if (hdr) break; =20 @@ -565,12 +559,11 @@ static void talitos_error(struct device *dev, u32 isr= , u32 isr_lo) unsigned int timeout =3D TALITOS_TIMEOUT; int ch, error, reset_dev =3D 0; u32 v_lo; - bool is_sec1 =3D has_ftr_sec1(priv); - int reset_ch =3D is_sec1 ? 1 : 0; /* only SEC2 supports continuation */ + int reset_ch =3D is_sec1() ? 1 : 0; /* only SEC2 supports continuation */ =20 for (ch =3D 0; ch < priv->num_channels; ch++) { /* skip channels without errors */ - if (is_sec1) { + if (is_sec1()) { /* bits 29, 31, 17, 19 */ if (!(isr & (1 << (29 + (ch & 1) * 2 - (ch & 2) * 6)))) continue; @@ -596,19 +589,19 @@ static void talitos_error(struct device *dev, u32 isr= , u32 isr_lo) if (v_lo & TALITOS_CCPSR_LO_MDTE) dev_err(dev, "master data transfer error\n"); if (v_lo & TALITOS_CCPSR_LO_SGDLZ) - dev_err(dev, is_sec1 ? "pointer not complete error\n" + dev_err(dev, is_sec1() ? "pointer not complete error\n" : "s/g data length zero error\n"); if (v_lo & TALITOS_CCPSR_LO_FPZ) - dev_err(dev, is_sec1 ? "parity error\n" + dev_err(dev, is_sec1() ? "parity error\n" : "fetch pointer zero error\n"); if (v_lo & TALITOS_CCPSR_LO_IDH) dev_err(dev, "illegal descriptor header error\n"); if (v_lo & TALITOS_CCPSR_LO_IEU) - dev_err(dev, is_sec1 ? "static assignment error\n" + dev_err(dev, is_sec1() ? "static assignment error\n" : "invalid exec unit error\n"); if (v_lo & TALITOS_CCPSR_LO_EU) report_eu_error(dev, ch, current_desc_hdr(dev, ch)); - if (!is_sec1) { + if (!is_sec1()) { if (v_lo & TALITOS_CCPSR_LO_GB) dev_err(dev, "gather boundary error\n"); if (v_lo & TALITOS_CCPSR_LO_GRL) @@ -637,9 +630,9 @@ static void talitos_error(struct device *dev, u32 isr, = u32 isr_lo) } } } - if (reset_dev || (is_sec1 && isr & ~TALITOS1_ISR_4CHERR) || - (!is_sec1 && isr & ~TALITOS2_ISR_4CHERR) || isr_lo) { - if (is_sec1 && (isr_lo & TALITOS1_ISR_TEA_ERR)) + if (reset_dev || (is_sec1() && isr & ~TALITOS1_ISR_4CHERR) || + (!is_sec1() && isr & ~TALITOS2_ISR_4CHERR) || isr_lo) { + if (is_sec1() && (isr_lo & TALITOS1_ISR_TEA_ERR)) dev_err(dev, "TEA error: ISR 0x%08x_%08x\n", isr, isr_lo); else @@ -735,24 +728,22 @@ void talitos_sg_unmap(struct device *dev, struct scatterlist *dst, unsigned int len, unsigned int offset) { - struct talitos_private *priv =3D dev_get_drvdata(dev); - bool is_sec1 =3D has_ftr_sec1(priv); unsigned int src_nents =3D edesc->src_nents ? : 1; unsigned int dst_nents =3D edesc->dst_nents ? : 1; =20 - if (is_sec1 && dst && dst_nents > 1) { + if (is_sec1() && dst && dst_nents > 1) { dma_sync_single_for_device(dev, edesc->dma_link_tbl + offset, len, DMA_FROM_DEVICE); sg_pcopy_from_buffer(dst, dst_nents, edesc->buf + offset, len, offset); } if (src !=3D dst) { - if (src_nents =3D=3D 1 || !is_sec1) + if (src_nents =3D=3D 1 || !is_sec1()) dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE); =20 - if (dst && (dst_nents =3D=3D 1 || !is_sec1)) + if (dst && (dst_nents =3D=3D 1 || !is_sec1())) dma_unmap_sg(dev, dst, dst_nents, DMA_FROM_DEVICE); - } else if (src_nents =3D=3D 1 || !is_sec1) { + } else if (src_nents =3D=3D 1 || !is_sec1()) { dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL); } } @@ -785,15 +776,15 @@ static int sg_to_link_tbl_offset(struct scatterlist *= sg, int sg_count, =20 if (datalen > 0 && len > datalen) { to_talitos_ptr(link_tbl_ptr + count, - sg_dma_address(sg) + offset, datalen, 0); - to_talitos_ptr_ext_set(link_tbl_ptr + count, 0, 0); + sg_dma_address(sg) + offset, datalen); + to_talitos_ptr_ext_set(link_tbl_ptr + count, 0); count++; len -=3D datalen; offset +=3D datalen; } to_talitos_ptr(link_tbl_ptr + count, - sg_dma_address(sg) + offset, sg_next(sg) ? len : len + padding, = 0); - to_talitos_ptr_ext_set(link_tbl_ptr + count, 0, 0); + sg_dma_address(sg) + offset, sg_next(sg) ? len : len + padding); + to_talitos_ptr_ext_set(link_tbl_ptr + count, 0); count++; cryptlen -=3D len; datalen -=3D len; @@ -806,7 +797,7 @@ static int sg_to_link_tbl_offset(struct scatterlist *sg= , int sg_count, /* tag end of link table */ if (count > 0) to_talitos_ptr_ext_set(link_tbl_ptr + count - 1, - DESC_PTR_LNKTBL_RET, 0); + DESC_PTR_LNKTBL_RET); =20 return count; } @@ -817,33 +808,30 @@ int talitos_sg_map_ext(struct device *dev, struct sca= tterlist *src, unsigned int offset, int tbl_off, int elen, bool force, int align) { - struct talitos_private *priv =3D dev_get_drvdata(dev); - bool is_sec1 =3D has_ftr_sec1(priv); int aligned_len =3D ALIGN(len, align); =20 if (!src) { - to_talitos_ptr(ptr, 0, 0, is_sec1); + to_talitos_ptr(ptr, 0, 0); return 1; } - to_talitos_ptr_ext_set(ptr, elen, is_sec1); + to_talitos_ptr_ext_set(ptr, elen); if (sg_count =3D=3D 1 && !force) { - to_talitos_ptr(ptr, sg_dma_address(src) + offset, aligned_len, is_sec1); + to_talitos_ptr(ptr, sg_dma_address(src) + offset, aligned_len); return sg_count; } - if (is_sec1) { - to_talitos_ptr(ptr, edesc->dma_link_tbl + offset, aligned_len, is_sec1); + if (is_sec1()) { + to_talitos_ptr(ptr, edesc->dma_link_tbl + offset, aligned_len); return sg_count; } sg_count =3D sg_to_link_tbl_offset(src, sg_count, offset, len, elen, &edesc->link_tbl[tbl_off], align); if (sg_count =3D=3D 1 && !force) { - /* Only one segment now, so no link tbl needed*/ - copy_talitos_ptr(ptr, &edesc->link_tbl[tbl_off], is_sec1); + copy_talitos_ptr(ptr, &edesc->link_tbl[tbl_off]); return sg_count; } to_talitos_ptr(ptr, edesc->dma_link_tbl + - tbl_off * sizeof(struct talitos_ptr), aligned_len, is_sec1); - to_talitos_ptr_ext_or(ptr, DESC_PTR_LNKTBL_JUMP, is_sec1); + tbl_off * sizeof(struct talitos_ptr), aligned_len); + to_talitos_ptr_ext_or(ptr, DESC_PTR_LNKTBL_JUMP); =20 return sg_count; } @@ -877,9 +865,7 @@ struct talitos_edesc *talitos_edesc_alloc(struct device= *dev, dma_addr_t iv_dma =3D 0; gfp_t flags =3D cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL : GFP_ATOMIC; - struct talitos_private *priv =3D dev_get_drvdata(dev); - bool is_sec1 =3D has_ftr_sec1(priv); - int max_len =3D is_sec1 ? TALITOS1_MAX_DATA_LEN : TALITOS2_MAX_DATA_LEN; + int max_len =3D is_sec1() ? TALITOS1_MAX_DATA_LEN : TALITOS2_MAX_DATA_LEN; =20 if (cryptlen + authsize > max_len) { dev_err(dev, "length exceeds h/w max limit\n"); @@ -920,7 +906,7 @@ struct talitos_edesc *talitos_edesc_alloc(struct device= *dev, */ alloc_len =3D sizeof(struct talitos_edesc); if (src_nents || dst_nents || !encrypt) { - if (is_sec1) + if (is_sec1()) dma_len =3D (src_nents ? src_len : 0) + (dst_nents ? dst_len : 0) + authsize; else @@ -1092,13 +1078,12 @@ static int talitos_probe_irq(struct platform_device= *ofdev) struct device *dev =3D &ofdev->dev; struct talitos_private *priv =3D dev_get_drvdata(dev); int err; - bool is_sec1 =3D has_ftr_sec1(priv); =20 priv->irq[0] =3D platform_get_irq(ofdev, 0); if (priv->irq[0] < 0) return priv->irq[0]; =20 - if (is_sec1) { + if (is_sec1()) { err =3D request_irq(priv->irq[0], talitos1_interrupt_4ch, 0, dev_driver_string(dev), dev); goto primary_out; @@ -1193,12 +1178,10 @@ static int talitos_probe(struct platform_device *of= dev) TALITOS_FTR_SHA224_HWINIT | TALITOS_FTR_HMAC_OK; =20 - if (of_device_is_compatible(np, "fsl,sec1.0")) { - priv->features |=3D TALITOS_FTR_SEC1; + if (of_device_is_compatible(np, "fsl,sec1.0")) talitos_init_branch(true); - } else { + else talitos_init_branch(false); - } =20 if (of_device_is_compatible(np, "fsl,sec1.2")) { priv->reg_deu =3D priv->reg + TALITOS12_DEU; @@ -1229,7 +1212,7 @@ static int talitos_probe(struct platform_device *ofde= v) if (err) goto err_out; =20 - if (has_ftr_sec1(priv)) { + if (is_sec1()) { if (priv->num_channels =3D=3D 1) tasklet_init(&priv->done_task[0], talitos1_done_ch0, (unsigned long)dev); diff --git a/drivers/crypto/talitos/talitos-hash.c b/drivers/crypto/talitos= /talitos-hash.c index 165ae9bb570e..3c074eb1d825 100644 --- a/drivers/crypto/talitos/talitos-hash.c +++ b/drivers/crypto/talitos/talitos-hash.c @@ -44,8 +44,6 @@ static void common_nonsnoop_hash_unmap(struct device *dev, { struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); - struct talitos_private *priv =3D dev_get_drvdata(dev); - bool is_sec1 =3D has_ftr_sec1(priv); struct talitos_desc *desc =3D &edesc->desc; =20 unmap_single_talitos_ptr(dev, &desc->ptr[5], DMA_FROM_DEVICE); @@ -58,7 +56,7 @@ static void common_nonsnoop_hash_unmap(struct device *dev, talitos_sg_unmap(dev, edesc, edesc->src, NULL, 0, 0); =20 /* When using hashctx-in, must unmap it. */ - if (from_talitos_ptr_len(&desc->ptr[1], is_sec1)) + if (from_talitos_ptr_len(&desc->ptr[1])) unmap_single_talitos_ptr(dev, &desc->ptr[1], DMA_TO_DEVICE); =20 @@ -89,11 +87,10 @@ static void ahash_done(struct device *dev, container_of(desc, struct talitos_edesc, desc); struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); - bool is_sec1 =3D has_ftr_sec1(dev_get_drvdata(dev)); struct talitos_ctx *ctx =3D crypto_ahash_ctx(tfm); struct talitos_edesc *next; =20 - if (is_sec1) { + if (is_sec1()) { free_edesc_list_from(areq, edesc); ahash_request_complete(areq, err ?: req_ctx->to_hash_later); } else { @@ -156,8 +153,6 @@ static void common_nonsnoop_hash(struct talitos_edesc *= edesc, struct device *dev =3D ctx->dev; struct talitos_desc *desc =3D &edesc->desc; bool sync_needed =3D false; - struct talitos_private *priv =3D dev_get_drvdata(dev); - bool is_sec1 =3D has_ftr_sec1(priv); int sg_count; =20 /* first DWORD empty */ @@ -175,11 +170,10 @@ static void common_nonsnoop_hash(struct talitos_edesc= *edesc, =20 /* HMAC key */ if (ctx->keylen) - to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen, - is_sec1); + to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen); =20 sg_count =3D edesc->src_nents ?: 1; - if (is_sec1 && sg_count > 1) + if (is_sec1() && sg_count > 1) sg_copy_to_buffer(edesc->src, sg_count, edesc->buf, length); else if (length) sg_count =3D dma_map_sg(dev, edesc->src, sg_count, DMA_TO_DEVICE); @@ -207,7 +201,7 @@ static void common_nonsnoop_hash(struct talitos_edesc *= edesc, =20 /* last DWORD empty */ =20 - if (is_sec1 && from_talitos_ptr_len(&desc->ptr[3], true) =3D=3D 0) + if (is_sec1() && from_talitos_ptr_len(&desc->ptr[3]) =3D=3D 0) talitos_handle_buggy_hash(areq, edesc, &desc->ptr[3]); =20 if (sync_needed) @@ -228,12 +222,12 @@ static struct talitos_edesc *ahash_edesc_alloc(struct= ahash_request *areq, =20 static struct talitos_edesc * ahash_process_req_prepare(struct ahash_request *areq, unsigned int nbytes, - unsigned int blocksize, bool is_sec1) + unsigned int blocksize) { struct talitos_ctx *ctx =3D crypto_ahash_ctx(crypto_ahash_reqtfm(areq)); struct talitos_ahash_req_ctx *req_ctx =3D ahash_request_ctx(areq); struct talitos_edesc *first =3D NULL, *prev_edesc =3D NULL, *edesc; - size_t desc_max =3D is_sec1 ? TALITOS1_MAX_DATA_LEN : + size_t desc_max =3D is_sec1() ? TALITOS1_MAX_DATA_LEN : TALITOS2_MAX_DATA_LEN; struct scatterlist tmp[2]; size_t to_hash_this_desc; @@ -278,7 +272,7 @@ ahash_process_req_prepare(struct ahash_request *areq, u= nsigned int nbytes, edesc->desc.hdr |=3D DESC_HDR_MODE0_MDEU_HMAC; =20 /* clear the DN bit */ - if (is_sec1 && !edesc->last) + if (is_sec1() && !edesc->last) edesc->desc.hdr &=3D ~DESC_HDR_DONE_NOTIFY; =20 common_nonsnoop_hash(edesc, areq, to_hash_this_desc); @@ -304,7 +298,6 @@ static int ahash_process_req(struct ahash_request *areq= , unsigned int nbytes) struct talitos_edesc *edesc; unsigned int blocksize =3D crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); - bool is_sec1 =3D has_ftr_sec1(dev_get_drvdata(ctx->dev)); unsigned int nbytes_to_hash; unsigned int to_hash_later; struct device *dev =3D ctx->dev; @@ -320,8 +313,7 @@ static int ahash_process_req(struct ahash_request *areq= , unsigned int nbytes) =20 req_ctx->to_hash_later =3D to_hash_later; =20 - edesc =3D ahash_process_req_prepare(areq, nbytes_to_hash, blocksize, - is_sec1); + edesc =3D ahash_process_req_prepare(areq, nbytes_to_hash, blocksize); if (IS_ERR(edesc)) return PTR_ERR(edesc); =20 diff --git a/drivers/crypto/talitos/talitos-skcipher.c b/drivers/crypto/tal= itos/talitos-skcipher.c index 8360181840f6..d4762873d0cd 100644 --- a/drivers/crypto/talitos/talitos-skcipher.c +++ b/drivers/crypto/talitos/talitos-skcipher.c @@ -59,21 +59,19 @@ static int common_nonsnoop(struct talitos_edesc *edesc, unsigned int ivsize =3D crypto_skcipher_ivsize(cipher); int sg_count, ret; bool sync_needed =3D false; - struct talitos_private *priv =3D dev_get_drvdata(dev); - bool is_sec1 =3D has_ftr_sec1(priv); bool is_ctr =3D (desc->hdr & DESC_HDR_SEL0_MASK) =3D=3D DESC_HDR_SEL0_AES= U && (desc->hdr & DESC_HDR_MODE0_AESU_MASK) =3D=3D DESC_HDR_MODE0_AESU_= CTR; =20 /* first DWORD empty */ =20 /* cipher iv */ - to_talitos_ptr(&desc->ptr[1], edesc->iv_dma, ivsize, is_sec1); + to_talitos_ptr(&desc->ptr[1], edesc->iv_dma, ivsize); =20 /* cipher key */ - to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen, is_sec1); + to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen); =20 sg_count =3D edesc->src_nents ?: 1; - if (is_sec1 && sg_count > 1) + if (is_sec1() && sg_count > 1) sg_copy_to_buffer(areq->src, sg_count, edesc->buf, cryptlen); else @@ -91,7 +89,7 @@ static int common_nonsnoop(struct talitos_edesc *edesc, /* cipher out */ if (areq->src !=3D areq->dst) { sg_count =3D edesc->dst_nents ? : 1; - if (!is_sec1 || sg_count =3D=3D 1) + if (!is_sec1() || sg_count =3D=3D 1) dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE); } =20 @@ -324,7 +322,6 @@ static const struct talitos_alg_template skcipher_drive= r_algs[] =3D { =20 int talitos_register_skcipher(struct device *dev) { - struct talitos_private *priv =3D dev_get_drvdata(dev); struct talitos_alg_template talitos_alg_template; struct skcipher_alg *skcipher_alg; struct crypto_alg *alg; @@ -341,10 +338,10 @@ int talitos_register_skcipher(struct device *dev) skcipher_alg =3D &talitos_alg_template.alg.skcipher; alg =3D &skcipher_alg->base; =20 - if (has_ftr_sec1(priv)) + if (is_sec1()) alg->cra_alignmask =3D 3; =20 - if (!strcmp(alg->cra_name, "ctr(aes)") && !has_ftr_sec1(priv) && + if (!strcmp(alg->cra_name, "ctr(aes)") && !is_sec1() && DESC_TYPE(talitos_alg_template.desc_hdr_template) !=3D DESC_TYPE(DESC_HDR_TYPE_AESU_CTR_NONSNOOP)) { continue; diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/tali= tos.h index 5927dfe84770..a639c2f75d35 100644 --- a/drivers/crypto/talitos/talitos.h +++ b/drivers/crypto/talitos/talitos.h @@ -223,7 +223,6 @@ struct talitos_crypto_alg { #define TALITOS_FTR_HW_AUTH_CHECK 0x00000002 #define TALITOS_FTR_SHA224_HWINIT 0x00000004 #define TALITOS_FTR_HMAC_OK 0x00000008 -#define TALITOS_FTR_SEC1 0x00000010 =20 #if defined(CONFIG_CRYPTO_DEV_TALITOS1) && defined(CONFIG_CRYPTO_DEV_TALIT= OS2) DECLARE_STATIC_KEY_FALSE(talitos_is_sec1); @@ -252,20 +251,6 @@ static inline void talitos_init_branch(bool sec1) =20 #endif =20 -/* - * If both CONFIG_CRYPTO_DEV_TALITOS1 and CONFIG_CRYPTO_DEV_TALITOS2 are - * defined, we check the features which are set according to the device tr= ee. - * Otherwise, we answer true or false directly - */ -static inline bool has_ftr_sec1(struct talitos_private *priv) -{ - if (IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS1) && - IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS2)) - return priv->features & TALITOS_FTR_SEC1; - - return IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS1); -} - /* * TALITOS_xxx_LO addresses point to the low data bits (32-63) of the regi= ster */ @@ -504,10 +489,10 @@ static inline bool has_ftr_sec1(struct talitos_privat= e *priv) #define DESC_PTR_LNKTBL_NEXT 0x01 =20 static inline void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_= addr, - unsigned int len, bool is_sec1) + unsigned int len) { ptr->ptr =3D cpu_to_be32(lower_32_bits(dma_addr)); - if (is_sec1) { + if (is_sec1()) { ptr->len1 =3D cpu_to_be16(len); } else { ptr->len =3D cpu_to_be16(len); @@ -516,10 +501,10 @@ static inline void to_talitos_ptr(struct talitos_ptr = *ptr, dma_addr_t dma_addr, } =20 static inline void copy_talitos_ptr(struct talitos_ptr *dst_ptr, - struct talitos_ptr *src_ptr, bool is_sec1) + struct talitos_ptr *src_ptr) { dst_ptr->ptr =3D src_ptr->ptr; - if (is_sec1) { + if (is_sec1()) { dst_ptr->len1 =3D src_ptr->len1; } else { dst_ptr->len =3D src_ptr->len; @@ -527,26 +512,23 @@ static inline void copy_talitos_ptr(struct talitos_pt= r *dst_ptr, } } =20 -static inline unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr, - bool is_sec1) +static inline unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr) { - if (is_sec1) + if (is_sec1()) return be16_to_cpu(ptr->len1); else return be16_to_cpu(ptr->len); } =20 -static inline void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val, - bool is_sec1) +static inline void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val) { - if (!is_sec1) + if (!is_sec1()) ptr->j_extent =3D val; } =20 -static inline void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val, - bool is_sec1) +static inline void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val) { - if (!is_sec1) + if (!is_sec1()) ptr->j_extent |=3D val; } =20 @@ -559,10 +541,8 @@ static inline void __map_single_talitos_ptr(struct dev= ice *dev, unsigned long attrs) { dma_addr_t dma_addr =3D dma_map_single_attrs(dev, data, len, dir, attrs); - struct talitos_private *priv =3D dev_get_drvdata(dev); - bool is_sec1 =3D has_ftr_sec1(priv); =20 - to_talitos_ptr(ptr, dma_addr, len, is_sec1); + to_talitos_ptr(ptr, dma_addr, len); } =20 static inline void map_single_talitos_ptr(struct device *dev, @@ -589,11 +569,8 @@ static inline void unmap_single_talitos_ptr(struct dev= ice *dev, struct talitos_ptr *ptr, enum dma_data_direction dir) { - struct talitos_private *priv =3D dev_get_drvdata(dev); - bool is_sec1 =3D has_ftr_sec1(priv); - - dma_unmap_single(dev, be32_to_cpu(ptr->ptr), - from_talitos_ptr_len(ptr, is_sec1), dir); + dma_unmap_single(dev, be32_to_cpu(ptr->ptr), from_talitos_ptr_len(ptr), + dir); } =20 int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc, --=20 2.55.0 From nobody Thu Sep 24 13:42:19 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A698C399890; Wed, 23 Sep 2026 15:19:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790176800; cv=none; b=GeSWym7NOSnftnuM2J9YHRnzK9chXTHIipcosm/Eayqu30c+rElXT9D50NNxV2yjgM+sAE4HI6eqVWZR8IH27ogvk39tQGg+n+9YQhVjZtNmjqdtCHCxoW9QzepMIVd5AnqhV5iUoBAzJPSTbyt9F7H5dkVL6cnV57M+vUk4Ik8= ARC-Message-Signature: i=1; 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Wed, 23 Sep 2026 15:19:56 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id EBB5360580; Wed, 23 Sep 2026 15:19:55 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id D9CA010329217; Wed, 23 Sep 2026 17:19:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1790176794; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=aCtEf3lf4dYBZUGZNc1bmLEp7VdmKGPVLTMqbnvy/DQ=; b=nRHK+65ret3pJ5IWFpZQMvv5rRsnea10ILZvdPFM43GrZqyIsghpZS7/asiKbjWFDt8OXX PObvjcrIdvRaEgmdqFaHYbGU9XyG27mtHNNj/A+Ewv5PA8cBftjaPnIeWGw0g2xANTX6mm 0oAhqn+3+0Vxvuu1s+BXHNZUcpe9a6dAXIS4mlfMYdkqe475LFSqoxVOH5QPv34frDsrJg Pmi970z4V7qfI5mI2NGRLFnt/SAW03pWt2tnOHDxqttekqPHRu/ukFxjoqYxhdBLbRO91J ErT6/ElG6sOiLj/b9csjATClD9Zwaxo+T6P2tkJjuDECvwyXqKPnebpLmSsPMg== From: Paul Louvel Date: Wed, 23 Sep 2026 17:18:54 +0200 Subject: [PATCH v7 18/20] crypto: talitos - Introduce per-SEC-version descriptor and pointer structures Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-7-3-rc2_talitos_cleanup-v7-18-9a45261fc097@bootlin.com> References: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> In-Reply-To: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> To: Herbert Xu , "David S. Miller" Cc: Paul Louvel , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Christophe Leroy X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790176746; l=24178; i=paul.louvel@bootlin.com; s=20260313; h=from:subject:message-id; bh=JDM7T5fRceWmxidsusCwWheIeTm53sC2A42+2lmjAAA=; b=Ywy/tUqysxI3mpfO9OtVs2LoUlEFbxQQbbRvI0tN+yyptyhhiHn15WBn4fD6hZ4SPIkuImAVw Paz0ANwWXn9DfrfPTZsn2SHIzNTn07LnuLQjN68uysCx/CcCTlWdF1r X-Developer-Key: i=paul.louvel@bootlin.com; a=ed25519; pk=eLW50NT18UAvUT5cAcYf88zNbBCZDLFXuptpyLVhVIU= X-Last-TLS-Session-Version: TLSv1.3 The SEC1 and SEC2 hardware descriptor and pointer formats differ in many ways: - SEC1 pointers have a 16-bit reserved field followed by a 16-bit length and 32-bit address, while SEC2 pointers pack a 16-bit length, 8-bit jump/extent, 8-bit extended address, and 32-bit address. - SEC1 descriptors chain through a next_desc field absent from SEC2, while SEC2 has a hdr_lo field that SEC1 lacks. In the current code, reading those structures and mapping them to the documentation is not obvious. Instead of using anonymous union members, define two separate structures for hardware descriptor and pointer. The counterpart is that some added helpers are needed. Even if the structure is naturally aligned and no padding is added, add the __packed attribute to hint that these structures are used by the hardware. Signed-off-by: Paul Louvel --- drivers/crypto/talitos/talitos-aead.c | 42 +++++----- drivers/crypto/talitos/talitos-core.c | 20 ++--- drivers/crypto/talitos/talitos-hash.c | 34 ++++---- drivers/crypto/talitos/talitos-skcipher.c | 27 +++--- drivers/crypto/talitos/talitos.h | 131 +++++++++++++++++++++++---= ---- 5 files changed, 162 insertions(+), 92 deletions(-) diff --git a/drivers/crypto/talitos/talitos-aead.c b/drivers/crypto/talitos= /talitos-aead.c index d8058e75fb31..df0b4765986b 100644 --- a/drivers/crypto/talitos/talitos-aead.c +++ b/drivers/crypto/talitos/talitos-aead.c @@ -94,11 +94,11 @@ static void ipsec_esp_unmap(struct device *dev, unsigned int ivsize =3D crypto_aead_ivsize(aead); unsigned int authsize =3D crypto_aead_authsize(aead); unsigned int cryptlen =3D areq->cryptlen - (encrypt ? 0 : authsize); - bool is_ipsec_esp =3D edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP; - struct talitos_ptr *civ_ptr =3D &edesc->desc.ptr[is_ipsec_esp ? 2 : 3]; + bool is_ipsec_esp =3D from_talitos_desc_hdr(&edesc->desc) & DESC_HDR_TYPE= _IPSEC_ESP; + struct talitos_ptr *civ_ptr =3D from_talitos_desc_ptr(&edesc->desc, is_ip= sec_esp ? 2 : 3); =20 if (is_ipsec_esp) - unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], + unmap_single_talitos_ptr(dev, from_talitos_desc_ptr(&edesc->desc, 6), DMA_FROM_DEVICE); unmap_single_talitos_ptr(dev, civ_ptr, DMA_TO_DEVICE); =20 @@ -179,7 +179,7 @@ static void ipsec_esp_decrypt_hwauth_done(struct device= *dev, ipsec_esp_unmap(dev, edesc, req, false); =20 /* check ICV auth status */ - if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=3D + if (!err && ((from_talitos_desc_hdr_lo(desc) & DESC_HDR_LO_ICCR1_MASK) != =3D DESC_HDR_LO_ICCR1_PASS)) err =3D -EBADMSG; =20 @@ -208,13 +208,13 @@ static int ipsec_esp(struct talitos_edesc *edesc, str= uct aead_request *areq, int sg_count, ret; int elen =3D 0; bool sync_needed =3D false; - bool is_ipsec_esp =3D desc->hdr & DESC_HDR_TYPE_IPSEC_ESP; - struct talitos_ptr *civ_ptr =3D &desc->ptr[is_ipsec_esp ? 2 : 3]; - struct talitos_ptr *ckey_ptr =3D &desc->ptr[is_ipsec_esp ? 3 : 2]; + bool is_ipsec_esp =3D from_talitos_desc_hdr(desc) & DESC_HDR_TYPE_IPSEC_E= SP; + struct talitos_ptr *civ_ptr =3D from_talitos_desc_ptr(desc, is_ipsec_esp = ? 2 : 3); + struct talitos_ptr *ckey_ptr =3D from_talitos_desc_ptr(desc, is_ipsec_esp= ? 3 : 2); dma_addr_t dma_icv =3D edesc->dma_link_tbl + edesc->dma_len - authsize; =20 /* hmac key */ - to_talitos_ptr(&desc->ptr[0], ctx->dma_key, ctx->authkeylen); + to_talitos_ptr(from_talitos_desc_ptr(desc, 0), ctx->dma_key, ctx->authkey= len); =20 sg_count =3D edesc->src_nents ?: 1; if (is_sec1() && sg_count > 1) @@ -227,7 +227,7 @@ static int ipsec_esp(struct talitos_edesc *edesc, struc= t aead_request *areq, =20 /* hmac data */ ret =3D talitos_sg_map(dev, areq->src, areq->assoclen, edesc, - &desc->ptr[1], sg_count, 0, tbl_off); + from_talitos_desc_ptr(desc, 1), sg_count, 0, tbl_off); =20 if (ret > 1) { tbl_off +=3D ret; @@ -247,10 +247,10 @@ static int ipsec_esp(struct talitos_edesc *edesc, str= uct aead_request *areq, * extent is bytes of HMAC postpended to ciphertext, * typically 12 for ipsec */ - if (is_ipsec_esp && (desc->hdr & DESC_HDR_MODE1_MDEU_CICV)) + if (is_ipsec_esp && (from_talitos_desc_hdr(desc) & DESC_HDR_MODE1_MDEU_CI= CV)) elen =3D authsize; =20 - ret =3D talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->ptr[4], + ret =3D talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, from_talitos_= desc_ptr(desc, 4), sg_count, areq->assoclen, tbl_off, elen, false, 1); =20 @@ -270,7 +270,7 @@ static int ipsec_esp(struct talitos_edesc *edesc, struc= t aead_request *areq, elen =3D authsize; else elen =3D 0; - ret =3D talitos_sg_map_ext(dev, areq->dst, cryptlen, edesc, &desc->ptr[5], + ret =3D talitos_sg_map_ext(dev, areq->dst, cryptlen, edesc, from_talitos_= desc_ptr(desc, 5), sg_count, areq->assoclen, tbl_off, elen, is_ipsec_esp && !encrypt, 1); tbl_off +=3D ret; @@ -284,19 +284,19 @@ static int ipsec_esp(struct talitos_edesc *edesc, str= uct aead_request *areq, =20 /* icv data follows link tables */ to_talitos_ptr(tbl_ptr, dma_icv, authsize); - to_talitos_ptr_ext_or(&desc->ptr[5], authsize); + to_talitos_ptr_ext_or(from_talitos_desc_ptr(desc, 5), authsize); sync_needed =3D true; } else if (!encrypt) { - to_talitos_ptr(&desc->ptr[6], dma_icv, authsize); + to_talitos_ptr(from_talitos_desc_ptr(desc, 6), dma_icv, authsize); sync_needed =3D true; } else if (!is_ipsec_esp) { - talitos_sg_map(dev, areq->dst, authsize, edesc, &desc->ptr[6], + talitos_sg_map(dev, areq->dst, authsize, edesc, from_talitos_desc_ptr(de= sc, 6), sg_count, areq->assoclen + cryptlen, tbl_off); } =20 /* iv out */ if (is_ipsec_esp) - map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, + map_single_talitos_ptr(dev, from_talitos_desc_ptr(desc, 6), ivsize, ctx-= >iv, DMA_FROM_DEVICE); =20 if (sync_needed) @@ -339,7 +339,7 @@ static int aead_encrypt(struct aead_request *req) return PTR_ERR(edesc); =20 /* set encrypt */ - edesc->desc.hdr =3D ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT; + to_talitos_desc_hdr(&edesc->desc, ctx->desc_hdr_template | DESC_HDR_MODE0= _ENCRYPT); =20 return ipsec_esp(edesc, req, true, ipsec_esp_encrypt_done); } @@ -358,15 +358,15 @@ static int aead_decrypt(struct aead_request *req) if (IS_ERR(edesc)) return PTR_ERR(edesc); =20 - if ((edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP) && + if ((from_talitos_desc_hdr(&edesc->desc) & DESC_HDR_TYPE_IPSEC_ESP) && (priv->features & TALITOS_FTR_HW_AUTH_CHECK) && ((!edesc->src_nents && !edesc->dst_nents) || priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) { =20 /* decrypt and check the ICV */ - edesc->desc.hdr =3D ctx->desc_hdr_template | + to_talitos_desc_hdr(&edesc->desc, ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND | - DESC_HDR_MODE1_MDEU_CICV; + DESC_HDR_MODE1_MDEU_CICV); =20 /* reset integrity check result bits */ =20 @@ -375,7 +375,7 @@ static int aead_decrypt(struct aead_request *req) } =20 /* Have to check the ICV with software */ - edesc->desc.hdr =3D ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND; + to_talitos_desc_hdr(&edesc->desc, ctx->desc_hdr_template | DESC_HDR_DIR_I= NBOUND); =20 /* stash incoming ICV for later cmp with ICV generated by the h/w */ icvdata =3D edesc->buf + edesc->dma_len; diff --git a/drivers/crypto/talitos/talitos-core.c b/drivers/crypto/talitos= /talitos-core.c index 6fbaac923bef..2c274f1942d4 100644 --- a/drivers/crypto/talitos/talitos-core.c +++ b/drivers/crypto/talitos/talitos-core.c @@ -167,9 +167,7 @@ static void dma_map_request(struct device *dev, struct = talitos_request *request, =20 if (is_sec1()) { while (edesc) { - edesc->desc.hdr1 =3D edesc->desc.hdr; - - dma_desc =3D dma_map_single(dev, &edesc->desc.hdr1, + dma_desc =3D dma_map_single(dev, &edesc->desc.sec1.hdr, TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL); =20 @@ -180,7 +178,7 @@ static void dma_map_request(struct device *dev, struct = talitos_request *request, =20 /* Chain in any previous descriptors. */ =20 - prev_edesc->desc.next_desc =3D cpu_to_be32(dma_desc); + prev_edesc->desc.sec1.next_desc =3D cpu_to_be32(dma_desc); =20 dma_sync_single_for_device(dev, prev_dma_desc, TALITOS_DESC_SIZE, @@ -264,20 +262,20 @@ static __be32 get_request_hdr(struct device *dev, dma_sync_single_for_cpu(dev, request->dma_desc, TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL); =20 - return request->desc->hdr; + return request->desc->sec2.hdr; } =20 edesc =3D container_of(request->desc, struct talitos_edesc, desc); dma_desc =3D request->dma_desc; while (edesc->next_desc) { - dma_desc =3D be32_to_cpu(edesc->desc.next_desc); + dma_desc =3D be32_to_cpu(edesc->desc.sec1.next_desc); edesc =3D edesc->next_desc; } =20 dma_sync_single_for_cpu(dev, dma_desc, TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL); =20 - return edesc->desc.hdr1; + return edesc->desc.sec1.hdr; } =20 static void dma_unmap_request(struct device *dev, @@ -291,7 +289,7 @@ static void dma_unmap_request(struct device *dev, edesc =3D container_of(request->desc, struct talitos_edesc, desc); while (edesc->next_desc) { dma_unmap_single(dev, - be32_to_cpu(edesc->desc.next_desc), + be32_to_cpu(edesc->desc.sec1.next_desc), TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL); edesc =3D edesc->next_desc; } @@ -426,12 +424,12 @@ static __be32 search_desc_hdr_in_request(struct talit= os_request *request, struct talitos_edesc *edesc; =20 if (request->dma_desc =3D=3D cur_desc) { - return request->desc->hdr; + return from_talitos_desc_hdr(request->desc); } else if (is_sec1()) { edesc =3D container_of(request->desc, struct talitos_edesc, desc); while (edesc->next_desc) { - if (edesc->desc.next_desc =3D=3D cpu_to_be32(cur_desc)) - return edesc->next_desc->desc.hdr1; + if (edesc->desc.sec1.next_desc =3D=3D cpu_to_be32(cur_desc)) + return edesc->next_desc->desc.sec1.hdr; edesc =3D edesc->next_desc; } } diff --git a/drivers/crypto/talitos/talitos-hash.c b/drivers/crypto/talitos= /talitos-hash.c index 3c074eb1d825..140320b294d3 100644 --- a/drivers/crypto/talitos/talitos-hash.c +++ b/drivers/crypto/talitos/talitos-hash.c @@ -46,7 +46,7 @@ static void common_nonsnoop_hash_unmap(struct device *dev, struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(areq); struct talitos_desc *desc =3D &edesc->desc; =20 - unmap_single_talitos_ptr(dev, &desc->ptr[5], DMA_FROM_DEVICE); + unmap_single_talitos_ptr(dev, from_talitos_desc_ptr(desc, 5), DMA_FROM_DE= VICE); =20 if (edesc->last && req_ctx->last_request) memcpy(areq->result, req_ctx->hw_context, @@ -56,8 +56,8 @@ static void common_nonsnoop_hash_unmap(struct device *dev, talitos_sg_unmap(dev, edesc, edesc->src, NULL, 0, 0); =20 /* When using hashctx-in, must unmap it. */ - if (from_talitos_ptr_len(&desc->ptr[1])) - unmap_single_talitos_ptr(dev, &desc->ptr[1], + if (from_talitos_ptr_len(from_talitos_desc_ptr(desc, 1))) + unmap_single_talitos_ptr(dev, from_talitos_desc_ptr(desc, 1), DMA_TO_DEVICE); =20 if (edesc->dma_len) @@ -138,7 +138,7 @@ static void talitos_handle_buggy_hash(struct ahash_requ= est *areq, else memcpy(&req_ctx->padding_buf[56], &be_len, sizeof(be_len)); pr_err_once("Bug in SEC1, padding ourself\n"); - edesc->desc.hdr &=3D ~DESC_HDR_MODE0_MDEU_PAD; + and_talitos_desc_hdr(&edesc->desc, ~DESC_HDR_MODE0_MDEU_PAD); map_single_talitos_ptr(ctx->dev, ptr, sizeof(req_ctx->padding_buf), (char *)req_ctx->padding_buf, DMA_TO_DEVICE); } @@ -159,7 +159,7 @@ static void common_nonsnoop_hash(struct talitos_edesc *= edesc, =20 /* hash context in */ if (!edesc->first || !req_ctx->first_request || req_ctx->swinit) { - map_single_talitos_ptr_nosync(dev, &desc->ptr[1], + map_single_talitos_ptr_nosync(dev, from_talitos_desc_ptr(desc, 1), req_ctx->hw_context_size, req_ctx->hw_context, DMA_TO_DEVICE); @@ -170,7 +170,7 @@ static void common_nonsnoop_hash(struct talitos_edesc *= edesc, =20 /* HMAC key */ if (ctx->keylen) - to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen); + to_talitos_ptr(from_talitos_desc_ptr(desc, 2), ctx->dma_key, ctx->keylen= ); =20 sg_count =3D edesc->src_nents ?: 1; if (is_sec1() && sg_count > 1) @@ -181,7 +181,7 @@ static void common_nonsnoop_hash(struct talitos_edesc *= edesc, /* * data in */ - sg_count =3D talitos_sg_map(dev, edesc->src, length, edesc, &desc->ptr[3], + sg_count =3D talitos_sg_map(dev, edesc->src, length, edesc, from_talitos_= desc_ptr(desc, 3), sg_count, 0, 0); if (sg_count > 1) sync_needed =3D true; @@ -190,19 +190,19 @@ static void common_nonsnoop_hash(struct talitos_edesc= *edesc, =20 /* hash/HMAC out -or- hash context out */ if (edesc->last && req_ctx->last_request) - map_single_talitos_ptr(dev, &desc->ptr[5], + map_single_talitos_ptr(dev, from_talitos_desc_ptr(desc, 5), crypto_ahash_digestsize(tfm), req_ctx->hw_context, DMA_FROM_DEVICE); else - map_single_talitos_ptr_nosync(dev, &desc->ptr[5], + map_single_talitos_ptr_nosync(dev, from_talitos_desc_ptr(desc, 5), req_ctx->hw_context_size, req_ctx->hw_context, DMA_FROM_DEVICE); =20 /* last DWORD empty */ =20 - if (is_sec1() && from_talitos_ptr_len(&desc->ptr[3]) =3D=3D 0) - talitos_handle_buggy_hash(areq, edesc, &desc->ptr[3]); + if (is_sec1() && from_talitos_ptr_len(from_talitos_desc_ptr(desc, 3)) =3D= =3D 0) + talitos_handle_buggy_hash(areq, edesc, from_talitos_desc_ptr(desc, 3)); =20 if (sync_needed) dma_sync_single_for_device(dev, edesc->dma_link_tbl, @@ -249,19 +249,19 @@ ahash_process_req_prepare(struct ahash_request *areq,= unsigned int nbytes, } =20 edesc->src =3D scatterwalk_ffwd(edesc->bufsl, areq->src, offset); - edesc->desc.hdr =3D ctx->desc_hdr_template; + to_talitos_desc_hdr(&edesc->desc, ctx->desc_hdr_template); edesc->first =3D offset =3D=3D 0; edesc->last =3D nbytes - to_hash_this_desc =3D=3D 0; =20 /* On last one, request SEC to pad; otherwise continue */ if (req_ctx->last_request && edesc->last) - edesc->desc.hdr |=3D DESC_HDR_MODE0_MDEU_PAD; + or_talitos_desc_hdr(&edesc->desc, DESC_HDR_MODE0_MDEU_PAD); else - edesc->desc.hdr |=3D DESC_HDR_MODE0_MDEU_CONT; + or_talitos_desc_hdr(&edesc->desc, DESC_HDR_MODE0_MDEU_CONT); =20 /* request SEC to INIT hash. */ if (req_ctx->first_request && edesc->first && !req_ctx->swinit) - edesc->desc.hdr |=3D DESC_HDR_MODE0_MDEU_INIT; + or_talitos_desc_hdr(&edesc->desc, DESC_HDR_MODE0_MDEU_INIT); =20 /* * When the tfm context has a keylen, it's an HMAC. @@ -269,11 +269,11 @@ ahash_process_req_prepare(struct ahash_request *areq,= unsigned int nbytes, */ if (ctx->keylen && ((req_ctx->first_request && edesc->first) || (req_ctx->last_request && edesc->last))) - edesc->desc.hdr |=3D DESC_HDR_MODE0_MDEU_HMAC; + or_talitos_desc_hdr(&edesc->desc, DESC_HDR_MODE0_MDEU_HMAC); =20 /* clear the DN bit */ if (is_sec1() && !edesc->last) - edesc->desc.hdr &=3D ~DESC_HDR_DONE_NOTIFY; + and_talitos_desc_hdr(&edesc->desc, ~DESC_HDR_DONE_NOTIFY); =20 common_nonsnoop_hash(edesc, areq, to_hash_this_desc); =20 diff --git a/drivers/crypto/talitos/talitos-skcipher.c b/drivers/crypto/tal= itos/talitos-skcipher.c index d4762873d0cd..8318d28aea39 100644 --- a/drivers/crypto/talitos/talitos-skcipher.c +++ b/drivers/crypto/talitos/talitos-skcipher.c @@ -15,10 +15,10 @@ static void common_nonsnoop_unmap(struct device *dev, struct talitos_edesc *edesc, struct skcipher_request *areq) { - unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE); + unmap_single_talitos_ptr(dev, from_talitos_desc_ptr(&edesc->desc, 5), DMA= _FROM_DEVICE); =20 talitos_sg_unmap(dev, edesc, areq->src, areq->dst, areq->cryptlen, 0); - unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE); + unmap_single_talitos_ptr(dev, from_talitos_desc_ptr(&edesc->desc, 1), DMA= _TO_DEVICE); =20 if (edesc->dma_len) dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len, @@ -59,16 +59,18 @@ static int common_nonsnoop(struct talitos_edesc *edesc, unsigned int ivsize =3D crypto_skcipher_ivsize(cipher); int sg_count, ret; bool sync_needed =3D false; - bool is_ctr =3D (desc->hdr & DESC_HDR_SEL0_MASK) =3D=3D DESC_HDR_SEL0_AES= U && - (desc->hdr & DESC_HDR_MODE0_AESU_MASK) =3D=3D DESC_HDR_MODE0_AESU_= CTR; + bool is_ctr =3D (from_talitos_desc_hdr(desc) & DESC_HDR_SEL0_MASK) =3D=3D + DESC_HDR_SEL0_AESU && + (from_talitos_desc_hdr(desc) & + DESC_HDR_MODE0_AESU_MASK) =3D=3D DESC_HDR_MODE0_AESU_CTR; =20 /* first DWORD empty */ =20 /* cipher iv */ - to_talitos_ptr(&desc->ptr[1], edesc->iv_dma, ivsize); + to_talitos_ptr(from_talitos_desc_ptr(desc, 1), edesc->iv_dma, ivsize); =20 /* cipher key */ - to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen); + to_talitos_ptr(from_talitos_desc_ptr(desc, 2), ctx->dma_key, ctx->keylen); =20 sg_count =3D edesc->src_nents ?: 1; if (is_sec1() && sg_count > 1) @@ -81,8 +83,9 @@ static int common_nonsnoop(struct talitos_edesc *edesc, /* * cipher in */ - sg_count =3D talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->p= tr[3], - sg_count, 0, 0, 0, false, is_ctr ? 16 : 1); + sg_count =3D talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, + from_talitos_desc_ptr(desc, 3), sg_count, + 0, 0, 0, false, is_ctr ? 16 : 1); if (sg_count > 1) sync_needed =3D true; =20 @@ -93,13 +96,13 @@ static int common_nonsnoop(struct talitos_edesc *edesc, dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE); } =20 - ret =3D talitos_sg_map(dev, areq->dst, cryptlen, edesc, &desc->ptr[4], + ret =3D talitos_sg_map(dev, areq->dst, cryptlen, edesc, from_talitos_desc= _ptr(desc, 4), sg_count, 0, (edesc->src_nents + 1)); if (ret > 1) sync_needed =3D true; =20 /* iv out */ - map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, + map_single_talitos_ptr(dev, from_talitos_desc_ptr(desc, 5), ivsize, ctx->= iv, DMA_FROM_DEVICE); =20 /* last DWORD empty */ @@ -189,7 +192,7 @@ static int skcipher_encrypt(struct skcipher_request *ar= eq) return PTR_ERR(edesc); =20 /* set encrypt */ - edesc->desc.hdr =3D ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT; + to_talitos_desc_hdr(&edesc->desc, ctx->desc_hdr_template | DESC_HDR_MODE0= _ENCRYPT); =20 return common_nonsnoop(edesc, areq, skcipher_done); } @@ -213,7 +216,7 @@ static int skcipher_decrypt(struct skcipher_request *ar= eq) if (IS_ERR(edesc)) return PTR_ERR(edesc); =20 - edesc->desc.hdr =3D ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND; + to_talitos_desc_hdr(&edesc->desc, ctx->desc_hdr_template | DESC_HDR_DIR_I= NBOUND); =20 return common_nonsnoop(edesc, areq, skcipher_done); } diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/tali= tos.h index a639c2f75d35..accc5bf1797c 100644 --- a/drivers/crypto/talitos/talitos.h +++ b/drivers/crypto/talitos/talitos.h @@ -36,33 +36,49 @@ #define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK= _SIZE */ =20 /* descriptor pointer entry */ + +struct sec1_talitos_ptr { + __be16 res; + __be16 len; + __be32 ptr; +} __packed; + +struct sec2_talitos_ptr { + __be16 len; + u8 j_extent; + u8 eptr; + __be32 ptr; +} __packed; + struct talitos_ptr { union { - struct { /* SEC2 format */ - __be16 len; /* length */ - u8 j_extent; /* jump to sg link table and/or extent*/ - u8 eptr; /* extended address */ - }; - struct { /* SEC1 format */ - __be16 res; - __be16 len1; /* length */ - }; + struct sec1_talitos_ptr sec1; + struct sec2_talitos_ptr sec2; }; - __be32 ptr; /* address */ }; =20 -/* descriptor */ +/* descriptor format */ + +struct sec1_talitos_desc { + __be32 hdr; + struct sec1_talitos_ptr ptr[7]; + __be32 next_desc; +} __packed __aligned(4); + +struct sec2_talitos_desc { + __be32 hdr; + __be32 hdr_lo; + struct sec2_talitos_ptr ptr[7]; +} __packed __aligned(4); + struct talitos_desc { - __be32 hdr; /* header high bits */ union { - __be32 hdr_lo; /* header low bits */ - __be32 hdr1; /* header for SEC1 */ + struct sec1_talitos_desc sec1; + struct sec2_talitos_desc sec2; }; - struct talitos_ptr ptr[7]; /* ptr/len pair array */ - __be32 next_desc; /* next descriptor (SEC1) */ }; =20 -#define TALITOS_DESC_SIZE (sizeof(struct talitos_desc) - sizeof(__be32)) +#define TALITOS_DESC_SIZE (sizeof(struct talitos_desc)) =20 /* * talitos_edesc - s/w-extended descriptor @@ -488,48 +504,101 @@ static inline void talitos_init_branch(bool sec1) #define DESC_PTR_LNKTBL_RET 0x02 #define DESC_PTR_LNKTBL_NEXT 0x01 =20 +static inline __be32 from_talitos_ptr(struct talitos_ptr *ptr) +{ + if (is_sec1()) + return ptr->sec1.ptr; + return ptr->sec2.ptr; +} + +static inline __be32 from_talitos_desc_hdr(struct talitos_desc *desc) +{ + if (is_sec1()) + return desc->sec1.hdr; + return desc->sec2.hdr; +} + +static inline void to_talitos_desc_hdr(struct talitos_desc *desc, __be32 v= al) +{ + if (is_sec1()) + desc->sec1.hdr =3D val; + else + desc->sec2.hdr =3D val; +} + +static inline void or_talitos_desc_hdr(struct talitos_desc *desc, __be32 v= al) +{ + if (is_sec1()) + desc->sec1.hdr |=3D val; + else + desc->sec2.hdr |=3D val; +} + +static inline void and_talitos_desc_hdr(struct talitos_desc *desc, __be32 = val) +{ + if (is_sec1()) + desc->sec1.hdr &=3D val; + else + desc->sec2.hdr &=3D val; +} + +static inline __be32 from_talitos_desc_hdr_lo(struct talitos_desc *desc) +{ + return desc->sec2.hdr_lo; +} + +static inline struct talitos_ptr * +from_talitos_desc_ptr(struct talitos_desc *desc, int idx) +{ + if (is_sec1()) + return (struct talitos_ptr *)&desc->sec1.ptr[idx]; + return (struct talitos_ptr *)&desc->sec2.ptr[idx]; +} + static inline void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_= addr, unsigned int len) { - ptr->ptr =3D cpu_to_be32(lower_32_bits(dma_addr)); if (is_sec1()) { - ptr->len1 =3D cpu_to_be16(len); + ptr->sec1.ptr =3D cpu_to_be32(lower_32_bits(dma_addr)); + ptr->sec1.len =3D cpu_to_be16(len); } else { - ptr->len =3D cpu_to_be16(len); - ptr->eptr =3D upper_32_bits(dma_addr); + ptr->sec2.ptr =3D cpu_to_be32(lower_32_bits(dma_addr)); + ptr->sec2.len =3D cpu_to_be16(len); + ptr->sec2.eptr =3D upper_32_bits(dma_addr); } } =20 static inline void copy_talitos_ptr(struct talitos_ptr *dst_ptr, struct talitos_ptr *src_ptr) { - dst_ptr->ptr =3D src_ptr->ptr; if (is_sec1()) { - dst_ptr->len1 =3D src_ptr->len1; + dst_ptr->sec1.ptr =3D src_ptr->sec1.ptr; + dst_ptr->sec1.len =3D src_ptr->sec1.len; } else { - dst_ptr->len =3D src_ptr->len; - dst_ptr->eptr =3D src_ptr->eptr; + dst_ptr->sec2.ptr =3D src_ptr->sec2.ptr; + dst_ptr->sec2.len =3D src_ptr->sec2.len; + dst_ptr->sec2.eptr =3D src_ptr->sec2.eptr; } } =20 static inline unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr) { if (is_sec1()) - return be16_to_cpu(ptr->len1); + return be16_to_cpu(ptr->sec1.len); else - return be16_to_cpu(ptr->len); + return be16_to_cpu(ptr->sec2.len); } =20 static inline void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val) { if (!is_sec1()) - ptr->j_extent =3D val; + ptr->sec2.j_extent =3D val; } =20 static inline void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val) { if (!is_sec1()) - ptr->j_extent |=3D val; + ptr->sec2.j_extent |=3D val; } =20 /* @@ -569,8 +638,8 @@ static inline void unmap_single_talitos_ptr(struct devi= ce *dev, struct talitos_ptr *ptr, enum dma_data_direction dir) { - dma_unmap_single(dev, be32_to_cpu(ptr->ptr), from_talitos_ptr_len(ptr), - dir); + dma_unmap_single(dev, be32_to_cpu(from_talitos_ptr(ptr)), + from_talitos_ptr_len(ptr), dir); } =20 int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc, --=20 2.55.0 From nobody Thu Sep 24 13:42:19 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D99956C628; 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bh=2jWPpOqCMznalTTgnQVZZXdihTNKO3bN3YwU1/tcePg=; b=wRJCJ4HI+zQxdUErBPAyj9zAvxMNikIfxfMkaiU7tXZxrRTFVDyJu878WtPyYzTzCMcBdd v9TXf+aTH4bZ60+NWBZqqb06VUbtA0x5ue1PbmMp5BxBnLHz5NMyQs7nOQd5mMMVLv7elu ubL8iiphPL/5GoEVRRhYNm28xvmwLsZzsNcg0I8YCt9G30q3Ai1skTbPpgakXv5Vo8+lVq /kk/L+nh4wgKHD2agE0zhRf1qGmBrjD4Yn3GJLVDfCb5tad3D9ZTREnGkRW2kvhR7x7sgV 10cMHDSGU6r2TKD/ENjphOtAotn66dub0c+s7IwbuGRkCypOaw1YEv/gPdievA== From: Paul Louvel Date: Wed, 23 Sep 2026 17:18:55 +0200 Subject: [PATCH v7 19/20] crypto: talitos - Remove TALITOS_DESC_SIZE macro Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-7-3-rc2_talitos_cleanup-v7-19-9a45261fc097@bootlin.com> References: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> In-Reply-To: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> To: Herbert Xu , "David S. Miller" Cc: Paul Louvel , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Christophe Leroy X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790176746; l=3441; i=paul.louvel@bootlin.com; s=20260313; h=from:subject:message-id; bh=0fn9a5fI8mpJ9YsIbGo7WPqLxAqWQoB06cxqELNgtXs=; b=BfbbWSMRXesaC3s8t+G6OI+9gBuYeEXUKaRjhbIVp9N+2BwRNzhRO3Fj+heEhStatwh81y7EI RJummt32PvKBh8nDAV6rCHvb2DSgVnitGO0Q4lU8vMDznQBrxGgsOlW X-Developer-Key: i=paul.louvel@bootlin.com; a=ed25519; pk=eLW50NT18UAvUT5cAcYf88zNbBCZDLFXuptpyLVhVIU= X-Last-TLS-Session-Version: TLSv1.3 Now that TALITOS_DESC_SIZE is simply sizeof(struct talitos_desc) with no arithmetic, the macro is useless. Replace all occurrences with the underlying sizeof expression and remove the macro. Signed-off-by: Paul Louvel --- drivers/crypto/talitos/talitos-core.c | 16 ++++++++-------- drivers/crypto/talitos/talitos.h | 2 -- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/crypto/talitos/talitos-core.c b/drivers/crypto/talitos= /talitos-core.c index 2c274f1942d4..c31350679c99 100644 --- a/drivers/crypto/talitos/talitos-core.c +++ b/drivers/crypto/talitos/talitos-core.c @@ -168,7 +168,7 @@ static void dma_map_request(struct device *dev, struct = talitos_request *request, if (is_sec1()) { while (edesc) { dma_desc =3D dma_map_single(dev, &edesc->desc.sec1.hdr, - TALITOS_DESC_SIZE, + sizeof(struct talitos_desc), DMA_BIDIRECTIONAL); =20 if (!prev_edesc) { @@ -181,7 +181,7 @@ static void dma_map_request(struct device *dev, struct = talitos_request *request, prev_edesc->desc.sec1.next_desc =3D cpu_to_be32(dma_desc); =20 dma_sync_single_for_device(dev, prev_dma_desc, - TALITOS_DESC_SIZE, + sizeof(struct talitos_desc), DMA_TO_DEVICE); =20 next: @@ -190,7 +190,7 @@ static void dma_map_request(struct device *dev, struct = talitos_request *request, edesc =3D edesc->next_desc; } } else { - request->dma_desc =3D dma_map_single(dev, desc, TALITOS_DESC_SIZE, + request->dma_desc =3D dma_map_single(dev, desc, sizeof(struct talitos_de= sc), DMA_BIDIRECTIONAL); } } @@ -260,7 +260,7 @@ static __be32 get_request_hdr(struct device *dev, =20 if (!is_sec1()) { dma_sync_single_for_cpu(dev, request->dma_desc, - TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL); + sizeof(struct talitos_desc), DMA_BIDIRECTIONAL); =20 return request->desc->sec2.hdr; } @@ -272,7 +272,7 @@ static __be32 get_request_hdr(struct device *dev, edesc =3D edesc->next_desc; } =20 - dma_sync_single_for_cpu(dev, dma_desc, TALITOS_DESC_SIZE, + dma_sync_single_for_cpu(dev, dma_desc, sizeof(struct talitos_desc), DMA_BIDIRECTIONAL); =20 return edesc->desc.sec1.hdr; @@ -284,17 +284,17 @@ static void dma_unmap_request(struct device *dev, struct talitos_edesc *edesc; =20 if (is_sec1()) { - dma_unmap_single(dev, request->dma_desc, TALITOS_DESC_SIZE, + dma_unmap_single(dev, request->dma_desc, sizeof(struct talitos_desc), DMA_BIDIRECTIONAL); edesc =3D container_of(request->desc, struct talitos_edesc, desc); while (edesc->next_desc) { dma_unmap_single(dev, be32_to_cpu(edesc->desc.sec1.next_desc), - TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL); + sizeof(struct talitos_desc), DMA_BIDIRECTIONAL); edesc =3D edesc->next_desc; } } else { - dma_unmap_single(dev, request->dma_desc, TALITOS_DESC_SIZE, + dma_unmap_single(dev, request->dma_desc, sizeof(struct talitos_desc), DMA_BIDIRECTIONAL); } } diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/tali= tos.h index accc5bf1797c..28da0f507c91 100644 --- a/drivers/crypto/talitos/talitos.h +++ b/drivers/crypto/talitos/talitos.h @@ -78,8 +78,6 @@ struct talitos_desc { }; }; =20 -#define TALITOS_DESC_SIZE (sizeof(struct talitos_desc)) - /* * talitos_edesc - s/w-extended descriptor * @bufsl: scatterlist buffer --=20 2.55.0 From nobody Thu Sep 24 13:42:19 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31A5F57267F for ; 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bh=LnQXfNYZOYzL4bIDkcswTsJNPsN8lEiy6QszH3hhbpE=; b=BVTdJpcDkgdOkgV4fsz3+pnCsl01wXYnSfzqpYzD9JuutEWUfinYSOGf3WalZXddoE+yb7 sx19sby0G8etK5uwumzZu5mZw9fNGL9Tw57mYbRuHjyb2Sa83s0qzRcXCnOKr/CuMTUYmn L2DS1znRPwhTphkpmaRIdabXikhjQniQ7k8Z0oJX7BpRjr0se9JAUFlyc1MnnQpNhK/21w Y+6I9c2PH9/89fqRljzKnDklE4D+R7YODjmfJmoXX755tM8KTMgbR12Eb8aCFiblvwbdRx 3JyW1EC0KrOa160wUo0AUqF3nj12T71HPtXX+A2J57D6SRLV8btGm+zQZYDJqQ== From: Paul Louvel Date: Wed, 23 Sep 2026 17:18:56 +0200 Subject: [PATCH v7 20/20] MAINTAINERS: add entry for talitos driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-7-3-rc2_talitos_cleanup-v7-20-9a45261fc097@bootlin.com> References: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> In-Reply-To: <20260923-7-3-rc2_talitos_cleanup-v7-0-9a45261fc097@bootlin.com> To: Herbert Xu , "David S. Miller" Cc: Paul Louvel , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Christophe Leroy X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790176746; l=754; i=paul.louvel@bootlin.com; s=20260313; h=from:subject:message-id; bh=RhmXl3o9AEJHf4cRc6Z6Vr8c6k6nCxAjUcagIiCZW6s=; b=dPhrLtZh94g1Ojcbi3Kd0bFbwdJU3/D5ytj9nZ1a71tguZOjlzTTr8KALRvuh63AHMqd2XR0I KT9PufwvyphCvW1R89xxIw0TSL7izLk5R+UzJlVBZbh+bf/yFZ3VsDP X-Developer-Key: i=paul.louvel@bootlin.com; a=ed25519; pk=eLW50NT18UAvUT5cAcYf88zNbBCZDLFXuptpyLVhVIU= X-Last-TLS-Session-Version: TLSv1.3 An entry is missing for the Talitos crypto driver. Add it with myself as maintainer as I have worked on this crypto h/w device. Signed-off-by: Paul Louvel --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 6215fcb07770..c2f3ac4a572f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -26639,6 +26639,12 @@ L: platform-driver-x86@vger.kernel.org S: Maintained F: drivers/platform/x86/system76_acpi.c =20 +TALITOS CRYPTO DRIVER +M: Paul Louvel +L: linux-crypto@vger.kernel.org +S: Maintained +F: drivers/crypto/talitos/* + TASKSTATS STATISTICS INTERFACE M: Balbir Singh S: Maintained --=20 2.55.0