From nobody Thu Sep 24 13:41:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BCF3446BFC; Wed, 23 Sep 2026 07:24:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790148243; cv=none; b=VctqkSImm+aUnnKjNI1EpzQZBKpcYny3UfyvMbji+sjyobuhrY/Da6soLvhMhyMUuyyG3Lx00s218JV5RomcDg9VxX0zuIv3toyE3Cls3rjGZhKRTK0YZSL2wmBXZ0hz4TAm4bI4O8K/zH/GUh5bETlWAKiZoFnVICBuNMqezq8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790148243; c=relaxed/simple; bh=Yyi0dnUJzZFsu3n5Q4Sx1ZVuAY4ijHrDfpKarQMVXtk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QVrmJAr3HDTMB5/rawK4VPcLYm8ZWI/G1yUG9Ry0HV6TbVScwwe96nSJBsBa1lZyVkQI4is7EAAawH0wKraMN2YE42p5W7wWMkw+GY87BdCLyfDTBVChZKLiBRy1yuqSJ2lcUqWheJzPddK+j1ncSg5MOob2H26F1dK3wsRSj0E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=brFuQ060; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="brFuQ060" Received: by smtp.kernel.org (Postfix) with ESMTPS id A12F5C2BCB8; Wed, 23 Sep 2026 07:24:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790148242; bh=Yyi0dnUJzZFsu3n5Q4Sx1ZVuAY4ijHrDfpKarQMVXtk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=brFuQ060ViymlB+6l9K6xBNSfM1OfCCVpjVjB5ZZnHi2MvIvP/84/tDCfdOZNfW2a dowung1cgjuCbU4gi9bsf7pOsFO3zk+sBq4CEUv80r2w8QMExAybLYCqxdn1b2uGCm 8f/z+PuDZ4EX1Ggw/x82t3glsottQCQPxP1ZPPucWYCDuiP31fcoWe4/waQYrIIbCO N5pcKI0jsxXD+libuNZ2tzIbPaBg6IWBRtYkyF/hfxuSeXA5JPlyWcMIrdotBdXVNE QL4u86MnJOkXNzRo2w+clT6Ov3gtFIknDLR/Tx1oSVof+H3GeDkWAXApch7fTDHmpm ff/Y4VfWOSQ7Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CEDCC982EA; Wed, 23 Sep 2026 07:24:02 +0000 (UTC) From: Roman Vivchar via B4 Relay Date: Wed, 23 Sep 2026 10:23:34 +0300 Subject: [PATCH 1/3] cpufreq: mediatek: add support for CPU speedbin Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-6572-cpufreq-v1-1-41f7af6d6d1a@protonmail.com> References: <20260923-6572-cpufreq-v1-0-41f7af6d6d1a@protonmail.com> In-Reply-To: <20260923-6572-cpufreq-v1-0-41f7af6d6d1a@protonmail.com> To: "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Roman Vivchar X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790148240; l=3928; i=rva333@protonmail.com; s=20260510; h=from:subject:message-id; bh=8tS94U3qBY49lvfguXSecw1ZTRCCy8SxaUh/N0EXNSM=; b=GUglGD2ChmpxWy33le1togwI5locLZbOfUL2d63rF+2bFHVGo6eeNOMh4ujDuxgOTj5WYJ2Fr pXfvyLmrqiNClHhk/iqMkD4Y+xRZnUuUihx5rnaDPGh0rBlOQWgrot/ X-Developer-Key: i=rva333@protonmail.com; a=ed25519; pk=zww/nWjBGoQ4POXCG0BV6fx2iuXK6jx77rsKPA5YK5Y= X-Endpoint-Received: by B4 Relay for rva333@protonmail.com/20260510 with auth_id=777 X-Original-From: Roman Vivchar Reply-To: rva333@protonmail.com From: Roman Vivchar MediaTek SoCs are often released under the same marketing name, but with different suffix for the speedbin. For example, mt6572m has 1 GHz limit, mt6572a - 1.2 GHz, mt6572w - 1.4 GHz. Add code to support per-cluster 'opp-supported-hw' property. The DT is expected to pass a CPU speedbin using standard 'nvmem-cells' property under the CPU node. Signed-off-by: Roman Vivchar --- drivers/cpufreq/mediatek-cpufreq.c | 50 ++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 48 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-= cpufreq.c index 052ca7cd2f4f..f15135b2898b 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -57,6 +58,7 @@ struct mtk_cpu_dvfs_info { const struct mtk_cpufreq_platform_data *soc_data; int vtrack_max; bool ccifreq_bound; + int opp_token; }; =20 static struct platform_device *cpufreq_pdev; @@ -381,6 +383,38 @@ static struct device *of_get_cci(struct device *cpu_de= v) return &pdev->dev; } =20 +static int mtk_cpu_parse_speedbin(struct mtk_cpu_dvfs_info *info, int cpu) +{ + struct device *cpu_dev =3D get_cpu_device(cpu); + struct dev_pm_opp_config config =3D {}; + u32 val, opp_hw_ver; + int ret; + + ret =3D nvmem_cell_read_variable_le_u32(cpu_dev, "speed_grade", &val); + if (ret) { + if (ret =3D=3D -ENOENT) + /* speedbin is optional */ + return 0; + return dev_err_probe(cpu_dev, ret, "cpu%d: failed to read speedbin\n", c= pu); + } + + /* Convert the raw value to a bitmask */ + if (val >=3D 32) + return dev_err_probe(cpu_dev, -EINVAL, + "cpu%d: invalid speedbin value %u\n", cpu, val); + opp_hw_ver =3D BIT(val); + + config.supported_hw =3D &opp_hw_ver; + config.supported_hw_count =3D 1; + + info->opp_token =3D dev_pm_opp_set_config(cpu_dev, &config); + if (info->opp_token < 0) + return dev_err_probe(cpu_dev, info->opp_token, + "cpu%d: failed to set OPP config\n", cpu); + + return 0; +} + static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) { struct device *cpu_dev; @@ -450,18 +484,22 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs= _info *info, int cpu) } } =20 + ret =3D mtk_cpu_parse_speedbin(info, cpu); + if (ret) + goto out_disable_sram_reg; + /* Get OPP-sharing information from "operating-points-v2" bindings */ ret =3D dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus); if (ret) { dev_err_probe(cpu_dev, ret, "cpu%d: failed to get OPP-sharing information\n", cpu); - goto out_disable_sram_reg; + goto out_free_speedbin; } =20 ret =3D dev_pm_opp_of_cpumask_add_table(&info->cpus); if (ret) { dev_err_probe(cpu_dev, ret, "cpu%d: no OPP table\n", cpu); - goto out_disable_sram_reg; + goto out_free_speedbin; } =20 ret =3D clk_prepare_enable(info->cpu_clk); @@ -533,6 +571,10 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_= info *info, int cpu) out_free_opp_table: dev_pm_opp_of_cpumask_remove_table(&info->cpus); =20 +out_free_speedbin: + if (info->opp_token > 0) + dev_pm_opp_clear_config(info->opp_token); + out_disable_sram_reg: if (info->sram_reg) regulator_disable(info->sram_reg); @@ -573,6 +615,10 @@ static void mtk_cpu_dvfs_info_release(struct mtk_cpu_d= vfs_info *info) clk_disable_unprepare(info->inter_clk); clk_put(info->inter_clk); dev_pm_opp_of_cpumask_remove_table(&info->cpus); + + if (info->opp_token > 0) + dev_pm_opp_clear_config(info->opp_token); + dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb); if (info->soc_data->ccifreq_supported) put_device(info->cci_dev); --=20 2.55.0 From nobody Thu Sep 24 13:41:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BF7C451071; Wed, 23 Sep 2026 07:24:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790148243; cv=none; b=PmY0K+YXxJ0Zx5YfcVdM+ZDQHaDxQs0KsXVE6YK/km35U5WRlC9Xv/dWYUxbH9W+TXn//NA6PZysNtpSv274PTSu/iUZM9EwT+1UvaFYC2kCr2xRlMOY1qetpB+AmoPSHiaKAeucnpjOX02iNTFe0z2A2k/72a6LFACi9IAdXSY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790148243; c=relaxed/simple; bh=bMimWP7/2n7kxCpCnfJdRq+u+0JebIhQppMg7TsGX7Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Wed, 23 Sep 2026 07:24:02 +0000 (UTC) From: Roman Vivchar via B4 Relay Date: Wed, 23 Sep 2026 10:23:35 +0300 Subject: [PATCH 2/3] cpufreq: mediatek: add mt6572 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-6572-cpufreq-v1-2-41f7af6d6d1a@protonmail.com> References: <20260923-6572-cpufreq-v1-0-41f7af6d6d1a@protonmail.com> In-Reply-To: <20260923-6572-cpufreq-v1-0-41f7af6d6d1a@protonmail.com> To: "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Roman Vivchar X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790148240; l=1524; i=rva333@protonmail.com; s=20260510; h=from:subject:message-id; bh=b8RMk+Zv48cfJke7eSfTbaAxttUL1iUBiWM/BLYw9Fw=; b=WAtqaltRs4wSpqv0CO4qpYqEoudV+Gy+Tl/BfW9ztNKoM+pdXzu5ZvgkpisnwelUGwfCf0jXZ TU3bA3ie/SIAkFBJYaQbX87KwRldSLbbgOO/qXeUjDSAqfNG2EZuWf4 X-Developer-Key: i=rva333@protonmail.com; a=ed25519; pk=zww/nWjBGoQ4POXCG0BV6fx2iuXK6jx77rsKPA5YK5Y= X-Endpoint-Received: by B4 Relay for rva333@protonmail.com/20260510 with auth_id=777 X-Original-From: Roman Vivchar Reply-To: rva333@protonmail.com From: Roman Vivchar Add mt6572 SoC platform data for CPU frequency scaling. Signed-off-by: Roman Vivchar --- drivers/cpufreq/mediatek-cpufreq.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-= cpufreq.c index f15135b2898b..615bccc77c98 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -737,6 +737,14 @@ static const struct mtk_cpufreq_platform_data mt2701_p= latform_data =3D { .ccifreq_supported =3D false, }; =20 +static const struct mtk_cpufreq_platform_data mt6572_platform_data =3D { + .min_volt_shift =3D 100000, + .max_volt_shift =3D 200000, + .proc_max_volt =3D 1250000, + .sram_min_volt =3D 0, + .ccifreq_supported =3D false, +}; + static const struct mtk_cpufreq_platform_data mt7622_platform_data =3D { .min_volt_shift =3D 100000, .max_volt_shift =3D 200000, @@ -793,6 +801,7 @@ static const struct mtk_cpufreq_platform_data mt8516_pl= atform_data =3D { static const struct of_device_id mtk_cpufreq_machines[] __initconst __mayb= e_unused =3D { { .compatible =3D "mediatek,mt2701", .data =3D &mt2701_platform_data }, { .compatible =3D "mediatek,mt2712", .data =3D &mt2701_platform_data }, + { .compatible =3D "mediatek,mt6572", .data =3D &mt6572_platform_data }, { .compatible =3D "mediatek,mt7622", .data =3D &mt7622_platform_data }, { .compatible =3D "mediatek,mt7623", .data =3D &mt7623_platform_data }, { .compatible =3D "mediatek,mt7988a", .data =3D &mt7988_platform_data }, --=20 2.55.0 From nobody Thu Sep 24 13:41:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BED74508E0; Wed, 23 Sep 2026 07:24:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790148243; cv=none; b=Ua0r4t0Whkaf5nmopEGhh5nIKq2iMGL7AHdT1lECjf1jb55CUfAkX3SS1JSGmczQJUYtsn/I44MQMxF9uRgAWUxIWI1lJX4pBAdWYJGwPEP9sEkkngzccKC55PX2LVhDLfu8ZojZQJV4PbTxX4i9y71M1jdxjf2oqw7hbz2cgro= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790148243; c=relaxed/simple; bh=8qjNV9QZqkvKmCjMRy1A4HY8U9aaXcxKtUE7iWgaDg4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WVk5SCev1WOIyY2nxeuF850jJ5vNAzQZm5HWokNyuRKAl+VycKiy4W9N6nN1MURrfFxrD6HQfEksvP1idX1fN8FNPAATkdDcqKCVs3CadsnvCirLX6c9Ef0ZWoCoNyWWO6haI+1nAM5jCnMHhp6VcW5K9vBjcViphHyE/hzleag= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qy2f5CW7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qy2f5CW7" Received: by smtp.kernel.org (Postfix) with ESMTPS id D34A1C2BCFA; Wed, 23 Sep 2026 07:24:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790148242; bh=8qjNV9QZqkvKmCjMRy1A4HY8U9aaXcxKtUE7iWgaDg4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=qy2f5CW7rUNsHtY88qMWoL+eMP1gyYT4bSOqNpLQJ/srgDXyaRW/LcumAq3UIQtAT gDQxgwVZcdC1no7OygDnwyBbOg9cZbAS9pOUZS7/b+0+EWT6dlbLTEsMVg2dYDlqy4 qkQtQ6iLA8xKE34eIXSiS8b9E5gyoQmQJV9pXjpS+6jYBvUJv+VqeG6dgHKUr9NkO7 jZ5UrRJbPhrYIt1oPHdXDzBu9/LzA6+tAnl8Bmf0jelaxYoUW1yBfbW1KerwJhs5V1 HFDuM6VZi3ZaK5wOVxY697Vc3i1fTeeiFWoQRyN7ybPdRtznvTjiXTTL6NhYSbxEco 0hz4j4W+vh1ow== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BEC65C982FA; Wed, 23 Sep 2026 07:24:02 +0000 (UTC) From: Roman Vivchar via B4 Relay Date: Wed, 23 Sep 2026 10:23:36 +0300 Subject: [PATCH 3/3] cpufreq: dt-platdev: block the driver from probing on MediaTek mt6572 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260923-6572-cpufreq-v1-3-41f7af6d6d1a@protonmail.com> References: <20260923-6572-cpufreq-v1-0-41f7af6d6d1a@protonmail.com> In-Reply-To: <20260923-6572-cpufreq-v1-0-41f7af6d6d1a@protonmail.com> To: "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Roman Vivchar X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790148240; l=803; i=rva333@protonmail.com; s=20260510; h=from:subject:message-id; bh=pvNavw1TwxmxmNAxfAHmYvDXdUUIz8P51+5XyRZ6nPo=; b=YsrJCy5QZyZQ0x8+C3yQqVv16vsP+AsTxbfCOEpZ0WJhlCdxzGXzd1uQ5BVb3/jeTge8q1/k2 laGs8FQ7FQ8Byo/4hbiF1LPi5WxV62mitZXUae3HxZn9/6QXtWgWCY6 X-Developer-Key: i=rva333@protonmail.com; a=ed25519; pk=zww/nWjBGoQ4POXCG0BV6fx2iuXK6jx77rsKPA5YK5Y= X-Endpoint-Received: by B4 Relay for rva333@protonmail.com/20260510 with auth_id=777 X-Original-From: Roman Vivchar Reply-To: rva333@protonmail.com From: Roman Vivchar MediaTek SoCs use mediatek-cpufreq driver instead of generic one. Add mt6572 to the blocklist. Signed-off-by: Roman Vivchar Reviewed-by: AngeloGioacchino Del Regno --- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq= -dt-platdev.c index ff1204c666b1..ff7fb61eda74 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -132,6 +132,7 @@ static const struct of_device_id blocklist[] __initcons= t =3D { =20 { .compatible =3D "mediatek,mt2701", }, { .compatible =3D "mediatek,mt2712", }, + { .compatible =3D "mediatek,mt6572", }, { .compatible =3D "mediatek,mt7622", }, { .compatible =3D "mediatek,mt7623", }, { .compatible =3D "mediatek,mt8167", }, --=20 2.55.0