From nobody Thu Sep 24 14:26:25 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E78D14334A5; Tue, 22 Sep 2026 20:46:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790109993; cv=none; b=M3Y22Is5cC1qcDys/4HH8AcgMj/qP3SD1pf1zQdTvQHrEG/XqapPd7hpvVvVrFGhJfXGDPc58mNug33/ssxgaOL070rm8Wi9hnmZu7qZIRpd4wIe4uzXuUmYusMLv2VaF4TSZejUckSBYq+WFuZrQOeYh+h0zwvoGDgFyCon/gs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790109993; c=relaxed/simple; bh=kryAAzTAeZCZMWTsC4otulpVZ8szVC1RX2hypxRdDN4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CkAIaFOpg88hpRSCdfvf1W5GKFu93UbaR+Oc1+DtGA7OqI+0zp7rnWDZXQTapgE4/F7fMFvsFK6eZMszjGHmmXbudrrO9CT6r1sGMDPoeectvnAF+rd//YGKlGENMJtUOzMgwdG1QTExe2dvOn2g/YuudbLzDlxluV6H+IknVdQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=g9koUWlb; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="g9koUWlb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1790109988; x=1821645988; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kryAAzTAeZCZMWTsC4otulpVZ8szVC1RX2hypxRdDN4=; b=g9koUWlbbjYhrA2ZUIX02qd5R6M9Tdqi45yCyNXQ3K6kjvGu2Ne9VwkI y1rsfBzrDqRYpr9hI+R1VsEjcAHC6joRSGzqYAi+I7eNKeMtxNoOHVT3N vGu5tG6IsMS3TLj5ev+v6XwpfMutt+AcGIBs1Gt9WMRLQ6a/aNTgxqjIu O2HosFTdUER59I8Lb+vQYDQ5dq3YO63n6KLHnwn/FM+L958bqsfERFeDn SfQ2BBWCz6ba5hmorqrpn1nyW2L7e08IY2t5HAxDlfAB4k6h8wEfpCORG F1D73Bo8CI+iyK9JSRbmSJ/psz1foF8L/gZuBBxEjkV99c58C4HxqMkpG w==; X-CSE-ConnectionGUID: yafLHq36Ts2W0eorwFKvIA== X-CSE-MsgGUID: M9mYmickTfWAbJV85+TPwg== X-IronPort-AV: E=McAfee;i="6800,10657,11913"; a="90621936" X-IronPort-AV: E=Sophos;i="6.27,117,1787036400"; d="scan'208";a="90621936" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2026 13:45:52 -0700 X-CSE-ConnectionGUID: 0uJUlXfgS9WME37A1KC8YQ== X-CSE-MsgGUID: s7LUF9a8TamXdFzoU6+uTw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,117,1787036400"; d="scan'208";a="272493142" Received: from skuppusw-desk2.jf.intel.com ([10.165.154.101]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2026 13:45:51 -0700 From: Kuppuswamy Sathyanarayanan To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, rafael@kernel.org, lukas@wunner.de, terry.bowman@amd.com, kanie@linux.alibaba.com, olof@lixom.net, Kuppuswamy Sathyanarayanan Subject: [PATCH v14 1/4] PCI: Assume control of portdrv-related features only when portdrv enabled Date: Tue, 22 Sep 2026 13:45:45 -0700 Message-ID: <20260922204548.3884906-2-sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260922204548.3884906-1-sathyanarayanan.kuppuswamy@linux.intel.com> References: <20260922204548.3884906-1-sathyanarayanan.kuppuswamy@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Native control of PME, AER, DPC, and PCIe hotplug depends on the portdrv, so default to native handling of them only when CONFIG_PCIEPORTBUS is enabled. Native control of LTR and SHPC hotplug does not depend on portdrv, so keep defaulting those to native regardless. [bhelgaas: commit log] Link: https://lore.kernel.org/r/fcbe8a624166a1101a755edfef44a185d32ff493.16= 03766889.git.sathyanarayanan.kuppuswamy@linux.intel.com Signed-off-by: Kuppuswamy Sathyanarayanan Signed-off-by: Bjorn Helgaas --- Changes since v13 * Use a local IS_ENABLED(CONFIG_PCIEPORTBUS) variable instead of #ifdef (Lukas Wunner) v13 posting https://lore.kernel.org/r/20260919162655.3499010-1-sathyanarayanan.kuppuswa= my@linux.intel.com drivers/pci/probe.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 27008e2ea5af..1e487a213eb0 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -658,6 +658,8 @@ static const struct device_type pci_host_bridge_type = =3D { =20 static void pci_init_host_bridge(struct pci_host_bridge *bridge) { + bool port_services =3D IS_ENABLED(CONFIG_PCIEPORTBUS); + INIT_LIST_HEAD(&bridge->windows); INIT_LIST_HEAD(&bridge->dma_ranges); INIT_LIST_HEAD(&bridge->ports); @@ -668,12 +670,12 @@ static void pci_init_host_bridge(struct pci_host_brid= ge *bridge) * may implement its own AER handling and use _OSC to prevent the * OS from interfering. */ - bridge->native_aer =3D 1; - bridge->native_pcie_hotplug =3D 1; + bridge->native_aer =3D port_services; + bridge->native_pcie_hotplug =3D port_services; bridge->native_shpc_hotplug =3D 1; - bridge->native_pme =3D 1; + bridge->native_pme =3D port_services; bridge->native_ltr =3D 1; - bridge->native_dpc =3D 1; + bridge->native_dpc =3D port_services; bridge->domain_nr =3D PCI_DOMAIN_NR_NOT_SET; bridge->native_cxl_error =3D 1; bridge->dev.type =3D &pci_host_bridge_type; --=20 2.43.0 From nobody Thu Sep 24 14:26:25 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44A2D3CFF61; Tue, 22 Sep 2026 20:46:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790109997; cv=none; b=WfLIIpFAJFv9g7K4YnwGT2eQW51QxuzWhZFxYcYY6e/gjMRej/iUlpztRKWZLrH9at66BFB37kC0TjYwckcG95o81zm3YEJBqVq3F2srYRr77zx6sEmiHdCZKdYaaOR/zr/pjCCO9GqC7XByL+HNC/OhSf9xM6MPEGLJXdO2Aq8= ARC-Message-Signature: i=1; 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d="scan'208";a="272493146" Received: from skuppusw-desk2.jf.intel.com ([10.165.154.101]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2026 13:45:51 -0700 From: Kuppuswamy Sathyanarayanan To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, rafael@kernel.org, lukas@wunner.de, terry.bowman@amd.com, kanie@linux.alibaba.com, olof@lixom.net, Kuppuswamy Sathyanarayanan Subject: [PATCH v14 2/4] PCI/ACPI: Tidy _OSC control bit checking Date: Tue, 22 Sep 2026 13:45:46 -0700 Message-ID: <20260922204548.3884906-3-sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260922204548.3884906-1-sathyanarayanan.kuppuswamy@linux.intel.com> References: <20260922204548.3884906-1-sathyanarayanan.kuppuswamy@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add OSC_OWNER() helper to prettify checking the _OSC control bits to learn whether the platform has granted us control of PCI features. No functional change intended. [bhelgaas: split to separate patch, commit log] Signed-off-by: Kuppuswamy Sathyanarayanan Signed-off-by: Bjorn Helgaas Acked-by: Rafael J. Wysocki (Intel) --- Changes since v13 * No change. Picked up Rafael's Acked-by. v13 posting https://lore.kernel.org/r/20260919162655.3499010-1-sathyanarayanan.kuppuswa= my@linux.intel.com drivers/acpi/pci_root.c | 37 ++++++++++++++++++++++--------------- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c index 88c65f34e305..756dc2f055f5 100644 --- a/drivers/acpi/pci_root.c +++ b/drivers/acpi/pci_root.c @@ -993,6 +993,12 @@ static void acpi_pci_root_release_info(struct pci_host= _bridge *bridge) __acpi_pci_root_release_info(bridge->release_data); } =20 +#define OSC_OWNER(ctrl, bit, flag) \ + do { \ + if (!((ctrl) & (bit))) \ + flag =3D 0; \ + } while (0) + struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root, struct acpi_pci_root_ops *ops, struct acpi_pci_root_info *info, @@ -1003,6 +1009,7 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_= root *root, int node =3D acpi_get_node(device->handle); struct pci_bus *bus; struct pci_host_bridge *host_bridge; + u32 ctrl, ext_ctrl; =20 info->root =3D root; info->bridge =3D device; @@ -1028,21 +1035,21 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pc= i_root *root, goto out_release_info; =20 host_bridge =3D to_pci_host_bridge(bus->bridge); - if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL)) - host_bridge->native_pcie_hotplug =3D 0; - if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL)) - host_bridge->native_shpc_hotplug =3D 0; - if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL)) - host_bridge->native_aer =3D 0; - if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL)) - host_bridge->native_pme =3D 0; - if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL)) - host_bridge->native_ltr =3D 0; - if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL)) - host_bridge->native_dpc =3D 0; - - if (!(root->osc_ext_control_set & OSC_CXL_ERROR_REPORTING_CONTROL)) - host_bridge->native_cxl_error =3D 0; + + ctrl =3D root->osc_control_set; + ext_ctrl =3D root->osc_ext_control_set; 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d="scan'208";a="90621951" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2026 13:45:52 -0700 X-CSE-ConnectionGUID: hJL84l3OScuCFiKQ/HI7yw== X-CSE-MsgGUID: N6nbWw8/RziCJZ3IljsrzQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,117,1787036400"; d="scan'208";a="272493148" Received: from skuppusw-desk2.jf.intel.com ([10.165.154.101]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2026 13:45:51 -0700 From: Kuppuswamy Sathyanarayanan To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, rafael@kernel.org, lukas@wunner.de, terry.bowman@amd.com, kanie@linux.alibaba.com, olof@lixom.net, Kuppuswamy Sathyanarayanan Subject: [PATCH v14 3/4] PCI/ACPI: Centralize pcie_ports_native checking Date: Tue, 22 Sep 2026 13:45:47 -0700 Message-ID: <20260922204548.3884906-4-sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260922204548.3884906-1-sathyanarayanan.kuppuswamy@linux.intel.com> References: <20260922204548.3884906-1-sathyanarayanan.kuppuswamy@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If the user booted with "pcie_ports=3Dnative", we take control of the PCIe port services unconditionally, regardless of what _OSC says. Centralize the testing of pcie_ports_native in acpi_pci_root_create(), where we interpret the _OSC results, so other places only have to check host_bridge->native_X and we don't have to sprinkle tests of pcie_ports_native everywhere. Rather than overriding the host_bridge->native_X flags after the fact, fold "pcie_ports=3Dnative" into the _OSC control mask we evaluate, i.e., proceed as though the platform had granted control of the port services. That way there is a single mechanism deciding each native_X flag, and we can report exactly which features we are overriding _OSC for instead of just noting that we are overriding something: acpi PNP0A08:00: _OSC: OS forcing control ("pcie_ports=3Dnative") of [PCI= eHotplug PME AER DPC] Forcing host_bridge->native_aer also restores DPC service binding under "pcie_ports=3Dnative", which regressed in commit 97ca178c899d ("PCI/DPC: Allow DPC on all Downstream Ports when OS controls AER"). That commit replaced the AER service test in get_port_device_capability() with host->native_aer, so DPC stayed off when host_bridge->native_aer was not set. This also extends "pcie_ports=3Dnative" to host_bridge->native_dpc, which had no pcie_ports_native fallback before. That effect is narrow. native_dpc is only consumed by pci_dpc_recovered(), where with CONFIG_PCIE_EDR=3Dn it previously gave up immediately and now lets pciehp wait for DPC recovery before treating a Link Down as a hotplug event. host_bridge->native_ltr is deliberately not forced. "pcie_ports=3D" controls PCIe port services and LTR is not one. There is no PCIE_PORT_SERVICE_LTR, and native_ltr is only used by pci_configure_ltr() to enable ASPM L1.2, so forcing it would be an ASPM policy decision users did not ask for. SHPC hotplug is left alone for a simpler reason: SHPC is a conventional PCI feature rather than a PCIe one, so "pcie_ports=3D" has no bearing on it. Fixes: 97ca178c899d ("PCI/DPC: Allow DPC on all Downstream Ports when OS co= ntrols AER") Closes: https://lore.kernel.org/linux-pci/20260901064554.2178688-1-kanie@li= nux.alibaba.com/ [bhelgaas: commit log, rework OSC_PCIE_PORT_SERVICE_CONTROLS, logging] Link: https://lore.kernel.org/r/bc87c9e675118960949043a832bed86bc22becbd.16= 03766889.git.sathyanarayanan.kuppuswamy@linux.intel.com Signed-off-by: Kuppuswamy Sathyanarayanan Signed-off-by: Bjorn Helgaas Acked-by: Rafael J. Wysocki (Intel) # ACPI core Reviewed-by: Guixin Liu --- Changes since v13 * Added the Fixes: tag for 97ca178c899d. (Guixin Liu) * Reworded the commit log (Sashiko AI review). * No code change. Picked up Rafael's Acked-by. v13 posting https://lore.kernel.org/r/20260919162655.3499010-1-sathyanarayanan.kuppuswa= my@linux.intel.com drivers/acpi/pci_root.c | 36 +++++++++++++++++++++++++++++++ drivers/pci/hotplug/pciehp_core.c | 2 +- drivers/pci/pci-acpi.c | 3 --- drivers/pci/pcie/aer.c | 6 +++--- drivers/pci/pcie/aer_cxl_rch.c | 2 +- drivers/pci/pcie/err.c | 2 +- drivers/pci/pcie/portdrv.c | 6 +++--- 7 files changed, 45 insertions(+), 12 deletions(-) diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c index 756dc2f055f5..2494811dd69b 100644 --- a/drivers/acpi/pci_root.c +++ b/drivers/acpi/pci_root.c @@ -999,6 +999,19 @@ static void acpi_pci_root_release_info(struct pci_host= _bridge *bridge) flag =3D 0; \ } while (0) =20 +#define FLAG(x) ((x) ? '+' : '-') + +/* + * _OSC control bits for the features implemented by the PCIe port driver, + * i.e., the ones "pcie_ports=3Dnative" applies to. LTR and SHPC hotplug = are + * negotiated via _OSC as well, but they are not portdrv services, so + * "pcie_ports=3D" has no bearing on them. + */ +#define OSC_PCIE_PORT_SERVICE_CONTROLS (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL = | \ + OSC_PCI_EXPRESS_PME_CONTROL | \ + OSC_PCI_EXPRESS_AER_CONTROL | \ + OSC_PCI_EXPRESS_DPC_CONTROL) + struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root, struct acpi_pci_root_ops *ops, struct acpi_pci_root_info *info, @@ -1039,6 +1052,21 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci= _root *root, ctrl =3D root->osc_control_set; ext_ctrl =3D root->osc_ext_control_set; =20 + /* + * If the user specified "pcie_ports=3Dnative", use the PCIe port + * services regardless of what _OSC says, i.e., proceed as though the + * platform had granted us control of them. This may conflict with + * firmware that expects to own those features. + */ + if (pcie_ports_native) { + u32 override =3D OSC_PCIE_PORT_SERVICE_CONTROLS & ~ctrl; + + if (override) + decode_osc_control(root, "OS forcing control (\"pcie_ports=3Dnative\") = of", + override); + ctrl |=3D override; + } + OSC_OWNER(ctrl, OSC_PCI_EXPRESS_NATIVE_HP_CONTROL, host_bridge->native_pcie_hotplug); OSC_OWNER(ctrl, OSC_PCI_SHPC_NATIVE_HP_CONTROL, @@ -1051,6 +1079,14 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci= _root *root, OSC_OWNER(ext_ctrl, OSC_CXL_ERROR_REPORTING_CONTROL, host_bridge->native_cxl_error); =20 + dev_info(&root->device->dev, "OS native features: SHPCHotplug%c PCIeHotpl= ug%c PME%c AER%c DPC%c LTR%c\n", + FLAG(host_bridge->native_shpc_hotplug), + FLAG(host_bridge->native_pcie_hotplug), + FLAG(host_bridge->native_pme), + FLAG(host_bridge->native_aer), + FLAG(host_bridge->native_dpc), + FLAG(host_bridge->native_ltr)); + acpi_dev_power_up_children_with_adr(device); =20 pci_scan_child_bus(bus); diff --git a/drivers/pci/hotplug/pciehp_core.c b/drivers/pci/hotplug/pciehp= _core.c index 2cafd3b26f34..b42829cf1377 100644 --- a/drivers/pci/hotplug/pciehp_core.c +++ b/drivers/pci/hotplug/pciehp_core.c @@ -258,7 +258,7 @@ static bool pme_is_native(struct pcie_device *dev) const struct pci_host_bridge *host; =20 host =3D pci_find_host_bridge(dev->port->bus); - return pcie_ports_native || host->native_pme; + return host->native_pme; } =20 static void pciehp_disable_interrupt(struct pcie_device *dev) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 42d545edd7fa..1150f2fbabf4 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -812,9 +812,6 @@ bool pciehp_is_native(struct pci_dev *bridge) if (!IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)) return false; =20 - if (pcie_ports_native) - return true; - host =3D pci_find_host_bridge(bridge->bus); return host->native_pcie_hotplug; } diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index d8dcd238fda1..e84dd686582a 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -260,7 +260,7 @@ int pcie_aer_is_native(struct pci_dev *dev) if (!dev->aer_cap) return 0; =20 - return pcie_ports_native || host->native_aer; + return host->native_aer; } EXPORT_SYMBOL_NS_GPL(pcie_aer_is_native, "CXL"); =20 @@ -1847,7 +1847,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev= *dev) */ aer =3D root ? root->aer_cap : 0; =20 - if ((host->native_aer || pcie_ports_native) && aer) + if (host->native_aer && aer) aer_disable_irq(root); =20 if (type =3D=3D PCI_EXP_TYPE_RC_EC || type =3D=3D PCI_EXP_TYPE_RC_END) { @@ -1862,7 +1862,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev= *dev) pci_is_root_bus(dev->bus) ? "Root" : "Downstream", rc); } =20 - if ((host->native_aer || pcie_ports_native) && aer) { + if (host->native_aer && aer) { /* Clear Root Error Status */ pci_read_config_dword(root, aer + PCI_ERR_ROOT_STATUS, ®32); pci_write_config_dword(root, aer + PCI_ERR_ROOT_STATUS, reg32); diff --git a/drivers/pci/pcie/aer_cxl_rch.c b/drivers/pci/pcie/aer_cxl_rch.c index e471eefec9c4..b480dad8bbf4 100644 --- a/drivers/pci/pcie/aer_cxl_rch.c +++ b/drivers/pci/pcie/aer_cxl_rch.c @@ -31,7 +31,7 @@ static bool cxl_error_is_native(struct pci_dev *dev) { struct pci_host_bridge *host =3D pci_find_host_bridge(dev->bus); =20 - return (pcie_ports_native || host->native_aer); + return host->native_aer; } =20 static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c index d77403d8855b..1a7fc71c79d8 100644 --- a/drivers/pci/pcie/err.c +++ b/drivers/pci/pcie/err.c @@ -273,7 +273,7 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, * it is responsible for clearing this status. In that case, the * signaling device may not even be visible to the OS. */ - if (host->native_aer || pcie_ports_native) { + if (host->native_aer) { pcie_clear_device_status(dev); pci_aer_clear_nonfatal_status(dev); } diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c index a9cbfc1d2bc7..32fc623dd410 100644 --- a/drivers/pci/pcie/portdrv.c +++ b/drivers/pci/pcie/portdrv.c @@ -223,7 +223,7 @@ static int get_port_device_capability(struct pci_dev *d= ev) if (dev->is_pciehp && (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_ROOT_PORT || pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_DOWNSTREAM) && - (pcie_ports_native || host->native_pcie_hotplug)) { + host->native_pcie_hotplug) { services |=3D PCIE_PORT_SERVICE_HP; =20 /* @@ -240,14 +240,14 @@ static int get_port_device_capability(struct pci_dev = *dev) if ((pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_ROOT_PORT || pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC) && dev->aer_cap && pci_aer_available() && - (pcie_ports_native || host->native_aer)) + host->native_aer) services |=3D PCIE_PORT_SERVICE_AER; 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d="scan'208";a="272493150" Received: from skuppusw-desk2.jf.intel.com ([10.165.154.101]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2026 13:45:52 -0700 From: Kuppuswamy Sathyanarayanan To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, rafael@kernel.org, lukas@wunner.de, terry.bowman@amd.com, kanie@linux.alibaba.com, olof@lixom.net, Kuppuswamy Sathyanarayanan Subject: [PATCH v14 4/4] PCI: Centralize pci_aer_available() checking Date: Tue, 22 Sep 2026 13:45:48 -0700 Message-ID: <20260922204548.3884906-5-sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260922204548.3884906-1-sathyanarayanan.kuppuswamy@linux.intel.com> References: <20260922204548.3884906-1-sathyanarayanan.kuppuswamy@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Bjorn Helgaas "pci=3Dnoaer" tells us not to use AER. pci_aer_available() reports that, and it also reports the other cases where the OS cannot use AER at all, namely CONFIG_PCIEAER=3Dn and MSI being unavailable. Set host_bridge->native_aer from pci_aer_available() when we initialize the host bridge, so callers only have to look at native_aer and we do not have to test pci_aer_available() separately in each of them. Do this in pci_init_host_bridge() rather than in acpi_pci_root_create() so it also covers host bridges that are not described by ACPI and never reach acpi_pci_root_create(). This subsumes the CONFIG_PCIEPORTBUS check for native_aer, since pci_aer_available() is false when CONFIG_PCIEAER=3Dn and PCIEAER depends on PCIEPORTBUS. Signed-off-by: Bjorn Helgaas Co-developed-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kuppuswamy Sathyanarayanan --- Changes since v13 * No change. v13 posting https://lore.kernel.org/r/20260919162655.3499010-1-sathyanarayanan.kuppuswa= my@linux.intel.com drivers/pci/pcie/portdrv.c | 3 +-- drivers/pci/probe.c | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c index 32fc623dd410..9f8c6dd434c5 100644 --- a/drivers/pci/pcie/portdrv.c +++ b/drivers/pci/pcie/portdrv.c @@ -239,8 +239,7 @@ static int get_port_device_capability(struct pci_dev *d= ev) #ifdef CONFIG_PCIEAER if ((pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_ROOT_PORT || pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC) && - dev->aer_cap && pci_aer_available() && - host->native_aer) + dev->aer_cap && host->native_aer) services |=3D PCIE_PORT_SERVICE_AER; #endif =20 diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 1e487a213eb0..e1ca8096bcd5 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -670,7 +670,7 @@ static void pci_init_host_bridge(struct pci_host_bridge= *bridge) * may implement its own AER handling and use _OSC to prevent the * OS from interfering. */ - bridge->native_aer =3D port_services; + bridge->native_aer =3D pci_aer_available(); bridge->native_pcie_hotplug =3D port_services; bridge->native_shpc_hotplug =3D 1; bridge->native_pme =3D port_services; --=20 2.43.0