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Tue, 22 Sep 2026 19:04:21 +0800 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the P1 PMIC's regulator topology tree for DeepComputing FML13V05 board Signed-off-by: Sandie Cao --- .../spacemit/k3-deepcomputing-fml13v05.dts | 155 ++++++++++++++++++ 1 file changed, 155 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts b/a= rch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts index b5d5112de358..804abc85602a 100644 --- a/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts +++ b/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts @@ -22,6 +22,161 @@ memory@100000000 { device_type =3D "memory"; reg =3D <0x1 0x00000000 0x4 0x00000000>; }; + + reg_aux_vcc3v3: regulator-aux-vcc3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "AUX_VCC3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; + + reg_aux_vcc5v: regulator-aux-vcc5v { + compatible =3D "regulator-fixed"; + regulator-name =3D "AUX_VCC5V"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + }; +}; + +&i2c8 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c8_cfg>; + status =3D "okay"; + + p1@41 { + compatible =3D "spacemit,p1"; + reg =3D <0x41>; + interrupts =3D <64 IRQ_TYPE_LEVEL_HIGH>; + vin1-supply =3D <®_aux_vcc5v>; + vin2-supply =3D <®_aux_vcc5v>; + vin3-supply =3D <®_aux_vcc5v>; + vin4-supply =3D <®_aux_vcc5v>; + vin5-supply =3D <®_aux_vcc5v>; + vin6-supply =3D <®_aux_vcc5v>; + aldoin-supply =3D <®_aux_vcc5v>; + dldoin1-supply =3D <&buck4>; + dldoin2-supply =3D <&buck4>; + + regulators { + buck1: buck1 { + regulator-min-microvolt =3D <1050000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <5000>; + regulator-always-on; + }; + + buck2: buck2 { + regulator-min-microvolt =3D <1050000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <5000>; + regulator-always-on; + }; + + buck3: buck3 { + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-ramp-delay =3D <5000>; + regulator-always-on; + }; + + buck4: buck4 { + regulator-min-microvolt =3D <2100000>; + regulator-max-microvolt =3D <2100000>; + regulator-ramp-delay =3D <5000>; + regulator-always-on; + }; + + buck5: buck5 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-ramp-delay =3D <5000>; + regulator-always-on; + }; + + buck6: buck6 { + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <500000>; + regulator-ramp-delay =3D <5000>; + regulator-always-on; + }; + + aldo1: aldo1 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + aldo2: aldo2 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + aldo3: aldo3 { + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <3400000>; + }; + + aldo4: aldo4 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo1: dldo1 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo2: dldo2 { + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo3: dldo3 { + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo4: dldo4 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + }; + + dldo5: dldo5 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo6: dldo6 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo7: dldo7 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; }; =20 &uart0 { --=20 2.43.0 From nobody Thu Sep 24 16:07:27 2026 Received: from va-2-30.ptr.blmpb.com (va-2-30.ptr.blmpb.com [209.127.231.30]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 017FD539762 for ; Tue, 22 Sep 2026 11:04:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.127.231.30 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790075094; cv=none; b=Bm9ilPln08juceJrZu4Z+rq71liAFRi1TgE/Pw7g02Q3uXxhBpGmW51jGJosxHA6UMW21Khx8aybFtMm5WspphSOYEzzoRBPAd40pdT9+umAcfFyzPfRf9xGhhD12yAhLEgAmw6QYDhk3FFDBIbWLBUVz9yy+1AsYAq+X6AQXs8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790075094; c=relaxed/simple; bh=48yPuF0tDHCncmBzIxe6Adixm4tcOkeCt6YRyk9li4k=; h=Date:In-Reply-To:To:Content-Type:Subject:Mime-Version:References: Cc:From:Message-Id; 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charset="utf-8" Add USB device node (b, c, d) to DeepComputing FML13V05 board. USB A works on otg mode, it isn't configured currently. - 4 USB-C Ports - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1 - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz) - Port 3 & 4: USB 3.2 Gen 1 Signed-off-by: Sandie Cao --- .../spacemit/k3-deepcomputing-fml13v05.dts | 44 +++++++++++++ arch/riscv/boot/dts/spacemit/k3.dtsi | 66 +++++++++++++++++++ 2 files changed, 110 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts b/a= rch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts index 804abc85602a..55b0f63dcb2e 100644 --- a/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts +++ b/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts @@ -179,8 +179,52 @@ dldo7: dldo7 { }; }; =20 +&combophy { + spacemit,apmu =3D <&syscon_apmu 0x17>; + status =3D "okay"; +}; + &uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart0_0_cfg>; status =3D "okay"; }; + +&usb2_host { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + hub@1 { + compatible =3D "usb5e3,608"; + reg =3D <1>; + }; +}; + +&usb2_phy { + status =3D "okay"; +}; + +&usb3b_u2phy { + status =3D "okay"; +}; + +&usb3b { + status =3D "okay"; +}; + +&usb3c_u2phy { + status =3D "okay"; +}; + +&usb3c { + status =3D "okay"; +}; + +&usb3d_u2phy { + status =3D "okay"; +}; + +&usb3d { + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spa= cemit/k3.dtsi index b9977e78e096..ae3f8bb1e5ed 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -441,6 +441,72 @@ soc: soc { dma-noncoherent; ranges; =20 + usb3b: usb@81400000 { + compatible =3D "spacemit,k3-dwc3"; + reg =3D <0x0 0x81400000 0x0 0x10000>; + interrupts =3D <125 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent =3D <&saplic>; + clocks =3D <&syscon_apmu CLK_APMU_USB3_PORTB_BUS>; + clock-names =3D "usbdrd30"; + resets =3D <&syscon_apmu RESET_APMU_USB3_B_AHB>, + <&syscon_apmu RESET_APMU_USB3_B_VCC>, + <&syscon_apmu RESET_APMU_USB3_B_PHY>; + reset-names =3D "ahb", "vcc", "phy"; + phys =3D <&usb3b_u2phy>, + <&combophy 2 PHY_TYPE_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + phy_type =3D "utmi"; + snps,dis_enblslpm_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-ss-quirk; + dr_mode =3D "host"; + status =3D "disabled"; + }; + + usb3b_u2phy: phy@81500000 { + compatible =3D "spacemit,k3-usb2-phy"; + reg =3D <0x0 0x81500000 0x0 0x200>; + clocks =3D <&syscon_apmu CLK_APMU_USB2_BUS>; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + usb3c: usb@81700000 { + compatible =3D "spacemit,k3-dwc3"; + reg =3D <0x0 0x81700000 0x0 0x10000>; + interrupts =3D <148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent =3D <&saplic>; + clocks =3D <&syscon_apmu CLK_APMU_USB3_PORTC_BUS>; + clock-names =3D "usbdrd30"; + resets =3D <&syscon_apmu RESET_APMU_USB3_C_AHB>, + <&syscon_apmu RESET_APMU_USB3_C_VCC>, + <&syscon_apmu RESET_APMU_USB3_C_PHY>; + reset-names =3D "ahb", "vcc", "phy"; + phys =3D <&usb3c_u2phy>, + <&combophy 3 PHY_TYPE_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + phy_type =3D "utmi"; + snps,dis_enblslpm_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-ss-quirk; + dr_mode =3D "host"; + status =3D "disabled"; + }; + + usb3c_u2phy: phy@81800000 { + compatible =3D "spacemit,k3-usb2-phy"; + reg =3D <0x0 0x81800000 0x0 0x200>; + clocks =3D <&syscon_apmu CLK_APMU_USB2_BUS>; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + usb3d: usb@81a00000 { compatible =3D "spacemit,k3-dwc3"; reg =3D <0x0 0x81a00000 0x0 0x10000>; --=20 2.43.0 From nobody Thu Sep 24 16:07:27 2026 Received: from va-2-37.ptr.blmpb.com (va-2-37.ptr.blmpb.com [209.127.231.37]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8F375372D3 for ; Tue, 22 Sep 2026 11:05:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 22 Sep 2026 19:04:56 +0800 From: "Sandie Cao" Content-Transfer-Encoding: quoted-printable X-Lms-Return-Path: Subject: [PATCH 3/3] riscv: dts: spacemit: k3-deepcomputing-fml13v05: Enable SD card support Date: Tue, 22 Sep 2026 19:04:50 +0800 Message-Id: <20260922110450.3426070-1-sandie.cao@deepcomputing.io> X-Original-From: Sandie Cao References: <20260922110231.3426011-1-sandie.cao@deepcomputing.io> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 In-Reply-To: <20260922110231.3426011-1-sandie.cao@deepcomputing.io> X-Mailer: git-send-email 2.43.0 Content-Type: text/plain; charset="utf-8" Add the device tree node SDHCI-0 controller for Micro SD card slot. Signed-off-by: Sandie Cao --- .../spacemit/k3-deepcomputing-fml13v05.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts b/a= rch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts index 55b0f63dcb2e..5d3f07483d34 100644 --- a/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts +++ b/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts @@ -2,6 +2,7 @@ /* * Copyright (C) 2026 DeepComputing (HK) Limited */ +#include =20 #include "k3.dtsi" #include "k3-pinctrl.dtsi" @@ -184,6 +185,24 @@ &combophy { status =3D "okay"; }; =20 +&sdhci0 { + pinctrl-names =3D "default","uhs"; + pinctrl-0 =3D <&mmc1_cfg>; + pinctrl-1 =3D <&mmc1_uhs_cfg>; + bus-width =3D <4>; + cd-gpios =3D <&gpio K3_GPIO(88) GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + disable-wp; + cap-sd-highspeed; + vmmc-supply =3D <&aldo4>; + vqmmc-supply =3D <&aldo1>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status =3D "okay"; +}; + &uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart0_0_cfg>; --=20 2.43.0