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[84.3.243.148]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-49fde1e975asm7349825e9.14.2026.09.22.10.51.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 10:51:07 -0700 (PDT) From: Gabor Juhos Date: Tue, 22 Sep 2026 19:50:57 +0200 Subject: [PATCH] spi: spi-qpic-snand: fix read location register usage in qcom_spi_config_cw_read() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260922-qpic-snand-fix-cw_read-readloc-v1-1-67f6819fb3d7@gmail.com> X-B4-Tracking: v=1; b=H4sIAAAAAAAC/x2NUQrDIBAFryL73QVdJNRcpZQiukkXgkkV2oLk7 tnk58HAMK9D4yrcYDQdKn+lyVoU3M1AescyM0pWBrI02ECEn00SthJLxkn+mH6vyjHjOcua0Hs fnL2rmgk0slVW7Tp4PPf9ANcQsfxwAAAA X-Change-ID: 20260922-qpic-snand-fix-cw_read-readloc-4449108092d2 To: Mark Brown , Md Sadre Alam , Sricharan Ramabadhran , Varadarajan Narayanan Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Gabor Juhos X-Mailer: b4 0.14.3 While configuring a codeword read, the com_spi_config_cw_read() function unconditionally schedules writing of the regular read location registers. However these registers should be written only if the actual codeword is not the last one. Change the function to schedule writing of the registers corresponding to the acual codeword only. While at it, also drop the single-use 'reg' and 'num_cw' local variables and use the respective values directly in order to make the code easier to understand. Fixes: 7304d1909080 ("spi: spi-qpic: add driver for QCOM SPI NAND flash Int= erface") Signed-off-by: Gabor Juhos --- drivers/spi/spi-qpic-snand.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c index 05efe6313b7f..ce03599f90df 100644 --- a/drivers/spi/spi-qpic-snand.c +++ b/drivers/spi/spi-qpic-snand.c @@ -503,15 +503,14 @@ static void qcom_spi_set_read_loc(struct qcom_nand_co= ntroller *snandc, int cw, i static void qcom_spi_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc,= int cw) { - __le32 *reg =3D &snandc->regs->read_location0; - int num_cw =3D snandc->qspi->num_cw; - - qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SG= L); - if (cw =3D=3D (num_cw - 1)) { - reg =3D &snandc->regs->read_location_last0; - qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4, + if (cw =3D=3D (snandc->qspi->num_cw - 1)) + qcom_write_reg_dma(snandc, &snandc->regs->read_location_last0, + NAND_READ_LOCATION_LAST_CW_0, 4, + NAND_BAM_NEXT_SGL); + else + qcom_write_reg_dma(snandc, &snandc->regs->read_location0, + NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SGL); - } =20 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BA= M_NEXT_SGL); qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BA= M_NEXT_SGL); --- base-commit: 3d743adf090cd4c9a2120c1e02b0482e88aa0d2d change-id: 20260922-qpic-snand-fix-cw_read-readloc-4449108092d2 Best regards, --=20 Gabor Juhos