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Signed-off-by: Yijie Yang Signed-off-by: Jingyi Wang --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index eddf87fbd0cc..0e6b4fd8b275 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -187,6 +187,11 @@ properties: - qcom,mahua-crd - const: qcom,mahua =20 + - items: + - enum: + - qcom,maili-mtp + - const: qcom,maili + - description: Sierra Wireless MangOH Green with WP8548 Module items: - const: swir,mangoh-green-wp8548 --=20 2.34.1 From nobody Thu Sep 24 14:26:25 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7963A4570F8 for ; Tue, 22 Sep 2026 23:20:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Chunkai Deng Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/maili-ipcc.h | 62 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/maili-ipcc.h b/arch/arm64/boot/dts/qc= om/maili-ipcc.h new file mode 100644 index 000000000000..7cf66d20e9c1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/maili-ipcc.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DTS_MAILI_MAILBOX_IPCC_H +#define __DTS_MAILI_MAILBOX_IPCC_H + +/* Physical client IDs */ +#define IPCC_MPROC_AOP 0 +#define IPCC_MPROC_TZ 1 +#define IPCC_MPROC_MPSS 2 +#define IPCC_MPROC_LPASS 3 +#define IPCC_MPROC_SDC 4 +#define IPCC_MPROC_CDSP 5 +#define IPCC_MPROC_APSS 6 +#define IPCC_MPROC_SOCCP 12 +#define IPCC_MPROC_DCP 13 +#define IPCC_MPROC_QECP 14 +#define IPCC_MPROC_SPSS 15 +#define IPCC_MPROC_TME 16 +#define IPCC_MPROC_WPSS 17 + +#define IPCC_COMPUTE_L0_LPASS 1 +#define IPCC_COMPUTE_L0_CDSP 2 +#define IPCC_COMPUTE_L0_APSS 3 +#define IPCC_COMPUTE_L0_GPU 4 +#define IPCC_COMPUTE_L0_CVP 8 +#define IPCC_COMPUTE_L0_CAM 9 +#define IPCC_COMPUTE_L0_CAM1 10 +#define IPCC_COMPUTE_L0_DCP 11 +#define IPCC_COMPUTE_L0_VPU 12 +#define IPCC_COMPUTE_L0_SOCCP 16 + +#define IPCC_COMPUTE_L1_LPASS 1 +#define IPCC_COMPUTE_L1_CDSP 2 +#define IPCC_COMPUTE_L1_APSS 3 +#define IPCC_COMPUTE_L1_GPU 4 +#define IPCC_COMPUTE_L1_CVP 8 +#define IPCC_COMPUTE_L1_CAM 9 +#define IPCC_COMPUTE_L1_CAM1 10 +#define IPCC_COMPUTE_L1_DCP 11 +#define IPCC_COMPUTE_L1_VPU 12 +#define IPCC_COMPUTE_L1_SOCCP 16 + +#define IPCC_PERIPH_CDSP 2 +#define IPCC_PERIPH_APSS 3 +#define IPCC_PERIPH_PCIE0 4 +#define IPCC_PERIPH_PCIE1 15 + +#define IPCC_FENCE_LPASS 1 +#define IPCC_FENCE_CDSP 2 +#define IPCC_FENCE_APSS 3 +#define IPCC_FENCE_GPU 4 +#define IPCC_FENCE_CVP 8 +#define IPCC_FENCE_CAM 9 +#define IPCC_FENCE_CAM1 10 +#define IPCC_FENCE_DCP 11 +#define IPCC_FENCE_VPU 20 +#define IPCC_FENCE_SOCCP 24 + +#endif --=20 2.34.1 From nobody Thu Sep 24 14:26:25 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D709047668A for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33e96f47d52sm1412845eec.28.2026.09.22.16.20.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 16:20:10 -0700 (PDT) From: Jingyi Wang Date: Tue, 22 Sep 2026 16:20:00 -0700 Subject: [PATCH 3/5] arm64: dts: qcom: Introduce Maili SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260922-maili-dts-v1-3-ac2b1b76bfd9@oss.qualcomm.com> References: <20260922-maili-dts-v1-0-ac2b1b76bfd9@oss.qualcomm.com> In-Reply-To: <20260922-maili-dts-v1-0-ac2b1b76bfd9@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abel Vesa , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790119205; l=184133; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=Bd4vfmRA4irrzI87uOHO4APKDIyxBSvb7jO9YtXjfYs=; b=UrYoMt1E5mkTfD++TMoXc3hzODCfoqMQFKprCZJ2OpuPEw3Bh9jUgxjEgMpRUKrtY6zkwIcDR S3jlrw+KsDHARpCYKujdu8oPBCsAOAXqgkmuTsKLBysGkKhKCG4muz8 X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Proofpoint-ORIG-GUID: JSLWaeYV5pe_XApu79JbmBENVlEF_Rwh X-Authority-Analysis: v=2.4 cv=eauo7LEH c=1 sm=1 tr=0 ts=6ab30d2f cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=x7Rq2E7AioCEcJVirbYA:9 a=QEXdDO2ut3YA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIyMDMwNiBTYWx0ZWRfX0SRwwZhc6DMv b9Ovqm6RdKcPslihH2jFRpGxxEnP9OMkVgBzscS4BUe1b+g8F9SdCvxRWv4yoJzURjaiNVS3qYP OP/xRvXE2v3y30i9ovNYMiZv5jg9/6Oc159iE8tBGinzj0JTGdj85iEfVbVUPh3jlQt7jGctVHU 1k7lTp7H3ge9sCKHRNBwJkrNK0y9RDi+HOj6LoO5ZmyHHJKF2eAQWx/t8M0nSmzROZPJQyTncQ+ XIiAdjap3bSjKCvSbXqLwD+bt9cVxx0EFGfM3yERvoEvdYJBsliDe+Wz+PUztoSYhovN93/0jrB BJmRKckm3x5u1aIivKstfbCwb1qKWOXXZjPsP5Pub/nc+i+UJn6G1noFxFz1gaHnasm8bDv2X4c iCdSuZwQhtfHDTARHBMj+fZQQvsEA6Bpv0ZNrPeXQXHB7LAls6UIEpxBcCAICFTIVFRW0qdW07K 3Vvt3KfLehhT8Ke6zKw== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIyMDMwNiBTYWx0ZWRfX03PUbV7/Wd4h tWfZrZSFNORPxsgMNC7otghaCVzBa+f/0qjKVGcQFI14vd10kGKkHOsftd3D5jQa9feZwgWUnph JzGh3URDB2pQU4ebA2Isjbobqn3D1nw= X-Proofpoint-GUID: JSLWaeYV5pe_XApu79JbmBENVlEF_Rwh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-22_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 spamscore=0 malwarescore=0 bulkscore=0 adultscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609220306 Maili is Snapdragon SoC from Qualcomm. Features added in this patch: - CPUs with PSCI idle states and cpufreq - Interrupt-controller with PDC wakeup support - Timers, TCSR Clock Controllers - Reserved Shared memory - GCC and RPMHCC - TLMM - Interconnect - QuP with UART - SMMU - RPMHPD - UFS with Inline Crypto Engine - Watchdog - remoteprocs with smp2p and fastrpc - QUPv3 serial engine protocols - IPCC - PCIe - SPMI PMIC - USB - SD Card - videocc and gpucc - Adreno SMMU - BWMONs - LLCC - Temperature Sensor (TSENS) Written with help from Raviteja Laggyshetty (added interconnect nodes), Taniya Das (added Clock Controllers and cpufreq), Fenglin Wu (added RPMhPD and PMICs), Nitin Rawat (added UFS and SD Card), Kyle Deng (added IPCC and smp2p), Kumari Pallavi (added fastrpc), Vivek Pernamitta (added PCIe), Jyothi Kumar Seerapu(added QUPv3), Krishna Kurapati PSSNV(added USB) and Haritha S K (added TSENS). Co-developed-by: Yijie Yang Signed-off-by: Yijie Yang Signed-off-by: Jingyi Wang Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/maili.dtsi | 6956 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 6956 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/maili.dtsi b/arch/arm64/boot/dts/qcom= /maili.dtsi new file mode 100644 index 000000000000..886d307e536b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/maili.dtsi @@ -0,0 +1,6956 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "maili-ipcc.h" + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu6: cpu@0 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-3-0"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd6>, <&scmi_perf 0>; + power-domain-names =3D "psci", "perf"; + #cooling-cells =3D <2>; + }; + + cpu7: cpu@100 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-3-0"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd7>, <&scmi_perf 0>; + power-domain-names =3D "psci", "perf"; + #cooling-cells =3D <2>; + }; + + cpu3: cpu@200 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-3-1"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd3>, <&scmi_perf 2>; + power-domain-names =3D "psci", "perf"; + #cooling-cells =3D <2>; + }; + + cpu0: cpu@300 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-3-2"; + reg =3D <0x0 0x300>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd0>, <&scmi_perf 1>; + power-domain-names =3D "psci", "perf"; + #cooling-cells =3D <2>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-3-1"; + reg =3D <0x0 0x400>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd4>, <&scmi_perf 2>; + power-domain-names =3D "psci", "perf"; + #cooling-cells =3D <2>; + }; + + cpu1: cpu@500 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-3-2"; + reg =3D <0x0 0x500>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd1>, <&scmi_perf 1>; + power-domain-names =3D "psci", "perf"; + #cooling-cells =3D <2>; + }; + + cpu5: cpu@600 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-3-1"; + reg =3D <0x0 0x600>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd5>, <&scmi_perf 2>; + power-domain-names =3D "psci", "perf"; + #cooling-cells =3D <2>; + }; + + cpu2: cpu@700 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-3-2"; + reg =3D <0x0 0x700>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd2>, <&scmi_perf 1>; + power-domain-names =3D "psci", "perf"; + #cooling-cells =3D <2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu3>; + }; + + core1 { + cpu =3D <&cpu4>; + }; + + core2 { + cpu =3D <&cpu5>; + }; + }; + + cluster2 { + core0 { + cpu =3D <&cpu6>; + }; + + core1 { + cpu =3D <&cpu7>; + }; + }; + }; + + domain-idle-states { + cluster_cl5: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x01000054>; + entry-latency-us =3D <2150>; + exit-latency-us =3D <1983>; + min-residency-us =3D <17845>; + }; + + domain_ss3: domain-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x0200c354>; + entry-latency-us =3D <2800>; + exit-latency-us =3D <4400>; + min-residency-us =3D <19012>; + }; + }; + + idle-states { + entry-method =3D "psci"; + + cluster0_1_c4: cpu-sleep-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "retention"; + arm,psci-suspend-param =3D <0x00000004>; + entry-latency-us =3D <93>; + exit-latency-us =3D <129>; + min-residency-us =3D <1925>; + }; + + cluster2_c4: cpu-sleep-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "retention"; + arm,psci-suspend-param =3D <0x00000004>; + entry-latency-us =3D <172>; + exit-latency-us =3D <130>; + min-residency-us =3D <2356>; + }; + }; + }; + + firmware { + scm { + compatible =3D "qcom,scm-maili", "qcom,scm"; + qcom,dload-mode =3D <&tcsr 0x2000>; + interconnects =3D <&aggre_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + }; + + scmi { + compatible =3D "arm,scmi"; + mboxes =3D <&pdp0_mbox 0>, <&pdp0_mbox 1>; + mbox-names =3D "tx", "rx"; + shmem =3D <&pdp_tx>, <&pdp_rx>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_perf: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + }; + }; + + clk_virt: interconnect-0 { + compatible =3D "qcom,maili-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible =3D "qcom,maili-mc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + memory@a0000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x0 0xa0000000 0x0 0x0>; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster0_1_c4>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster0_1_c4>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster0_1_c4>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster0_1_c4>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster0_1_c4>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster0_1_c4>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster2_c4>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster2_c4>; + }; + + cluster_pd: power-domain-cluster { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_cl5>, + <&domain_ss3>; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + cpucp_slc_mem_sub: cpucp@81230000 { + reg =3D <0x0 0x81230000 0x0 0x1000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@81c60000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0x0 0x81c60000 0x0 0x20000>; + no-map; + }; + + pdp_ns_shared_mem: pdp-ns-shared@81f00000 { + reg =3D <0x0 0x81f00000 0x0 0x100000>; + no-map; + }; + + smem_mem: smem@82700000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x82700000 0x0 0x400000>; + hwlocks =3D <&tcsr_mutex 3>; + no-map; + }; + + dsm_partition_1_mem: dsm-partition-1@83500000 { + reg =3D <0x0 0x83500000 0x0 0x5180000>; + no-map; + }; + + dsm_partition_2_mem: dsm-partition-2@88680000 { + reg =3D <0x0 0x88680000 0x0 0x1700000>; + no-map; + }; + + mpss_mem: mpss@89e00000 { + reg =3D <0x0 0x89e00000 0x0 0x10400000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb@98400000 { + reg =3D <0x0 0x98400000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@99580000 { + reg =3D <0x0 0x99580000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@99590000 { + reg =3D <0x0 0x99590000 0x0 0xc000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode@9959c000 { + reg =3D <0x0 0x9959c000 0x0 0x4000>; + no-map; + }; + + camera_mem: camera@99600000 { + reg =3D <0x0 0x99600000 0x0 0x800000>; + no-map; + }; + + camera_2_mem: camera-2@99e00000 { + reg =3D <0x0 0x99e00000 0x0 0x800000>; + no-map; + }; + + video_mem: video@9a600000 { + reg =3D <0x0 0x9a600000 0x0 0x800000>; + no-map; + }; + + cvp_mem: cvp@9ae00000 { + reg =3D <0x0 0x9ae00000 0x0 0x800000>; + no-map; + }; + + cdsp_mem: cdsp@9b900000 { + reg =3D <0x0 0x9b900000 0x0 0x1900000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb@9d200000 { + reg =3D <0x0 0x9d200000 0x0 0x80000>; + no-map; + }; + + soccp_mem: soccp@a0480000 { + reg =3D <0x0 0xa0480000 0x0 0x500000>; + no-map; + }; + + soccp_dtb_mem: soccp-dtb@a0980000 { + reg =3D <0x0 0xa0980000 0x0 0x50000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb@a1380000 { + reg =3D <0x0 0xa1380000 0x0 0x80000>; + no-map; + }; + + adspslpi_mem: adspslpi@a1400000 { + reg =3D <0x0 0xa1400000 0x0 0x4600000>; + no-map; + }; + + mpss_crashdump_overlay_mem: mpss-crashdump-overlay@bd500000 { + reg =3D <0x0 0xbd500000 0x0 0xf00000>; + no-map; + }; + }; + + smp2p-adsp { + compatible =3D "qcom,smp2p"; + + interrupts-extended =3D <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem =3D <443>, <429>; + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-cdsp { + compatible =3D "qcom,smp2p"; + + interrupts-extended =3D <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem =3D <94>, <432>; + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-modem { + compatible =3D "qcom,smp2p"; + + interrupts-extended =3D <&ipcc IPCC_MPROC_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_MPROC_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem =3D <435>, <428>; + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <1>; + + smp2p_modem_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_modem_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-soccp { + compatible =3D "qcom,smp2p"; + + interrupts-extended =3D <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem =3D <617>, <616>; + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <19>; + + smp2p_soccp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_soccp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0 0x10 0>; + dma-ranges =3D <0 0 0 0 0x10 0>; + + gcc: clock-controller@100000 { + compatible =3D "qcom,maili-gcc"; + reg =3D <0x0 0x00100000 0x0 0x1f4200>; + + clocks =3D <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>, + <&pcie0_phy>, + <&pcie1_phy>, + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + gpi_dma2: dma-controller@800000 { + compatible =3D "qcom,maili-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x00800000 0x0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <12>; + dma-channel-mask =3D <0x1f>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0x36 0x0>; + dma-coherent; + }; + + qupv3_2: geniqup@8c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x008c0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + + iommus =3D <&apps_smmu 0x23 0x0>; + + dma-coherent; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + i2c8: i2c@880000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00880000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c8_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart8: serial@880000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00880000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart8_default>, <&qup_uart8_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + spi8: spi@880000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00880000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi8_data_clk>, <&qup_spi8_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c9: i2c@884000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00884000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c9_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart9: serial@884000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00884000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart9_default>, <&qup_uart9_cts_rts>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi9: spi@884000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00884000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi9_data_clk>, <&qup_spi9_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c10: i2c@888000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00888000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c10_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart10: serial@888000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00888000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart10_default>, <&qup_uart10_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + spi10: spi@888000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00888000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi10_data_clk>, <&qup_spi10_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c11: i2c@88c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x0088c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c11_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart11: serial@88c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x0088c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart11_default>, <&qup_uart11_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + spi11: spi@88c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x0088c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi11_data_clk>, <&qup_spi11_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c12: i2c@890000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00890000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c12_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart12: serial@890000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x00890000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart12_default>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + }; + + i2c_master_hub: geniqup@9c0000 { + compatible =3D "qcom,geni-se-i2c-master-hub"; + reg =3D <0x0 0x009c0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; + clock-names =3D "s-ahb"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + i2c_hub_0: i2c@980000 { + compatible =3D "qcom,geni-i2c-master-hub"; + reg =3D <0x0 0x00980000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_I2C_S0_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names =3D "se", + "core"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&hub_i2c0_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c_hub_1: i2c@984000 { + compatible =3D "qcom,geni-i2c-master-hub"; + reg =3D <0x0 0x00984000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_I2C_S1_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names =3D "se", + "core"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&hub_i2c1_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c_hub_2: i2c@988000 { + compatible =3D "qcom,geni-i2c-master-hub"; + reg =3D <0x0 0x00988000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_I2C_S2_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names =3D "se", + "core"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&hub_i2c2_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c_hub_3: i2c@98c000 { + compatible =3D "qcom,geni-i2c-master-hub"; + reg =3D <0x0 0x0098c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_I2C_S3_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names =3D "se", + "core"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&hub_i2c3_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c_hub_4: i2c@990000 { + compatible =3D "qcom,geni-i2c-master-hub"; + reg =3D <0x0 0x00990000 0x0 0x4000>; + + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_I2C_S4_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names =3D "se", + "core"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&hub_i2c4_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible =3D "qcom,maili-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x00a00000 0x0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <16>; + dma-channel-mask =3D <0x7f>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0xb6 0x0>; + dma-coherent; + }; + + qupv3_1: geniqup@ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x00ac0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_WRAP_1_M_AXI_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names =3D "m-ahb", "s-ahb"; + + iommus =3D <&apps_smmu 0xa3 0x0>; + + dma-coherent; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + i2c0: i2c@a80000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a80000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c0_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart0: serial@a80000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a80000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart0_default>, <&qup_uart0_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + spi0: spi@a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a80000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c1: i2c@a84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a84000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c1_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart1: serial@a84000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a84000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart1_default>, <&qup_uart1_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + spi1: spi@a84000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a84000 0x0 0x4000>; + + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi1_data_clk>, <&qup_spi1_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c2: i2c@a88000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a88000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c2_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart2: serial@a88000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a88000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart2_default>, <&qup_uart2_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + spi2: spi@a88000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a88000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c3: i2c@a8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a8c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c3_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart3: serial@a8c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a8c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart3_default>, <&qup_uart3_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + spi3: spi@a8c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a8c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi3_data_clk>, <&qup_spi3_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c4: i2c@a90000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a90000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c4_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart4: serial@a90000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a90000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart4_default>, <&qup_uart4_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + spi4: spi@a90000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a90000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi4_data_clk>, <&qup_spi4_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c5: i2c@a94000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a94000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c5_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart5: serial@a94000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a94000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart5_default>, <&qup_uart5_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + spi5: spi@a94000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a94000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi5_data_clk>, <&qup_spi5_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c6: i2c@a98000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a98000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c6_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart6: serial@a98000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a98000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart6_default>, <&qup_uart6_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + spi6: spi@a98000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a98000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c7: i2c@a9c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a9c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c7_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart7: serial@a9c000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x00a9c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart7_default>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + spi7: spi@a9c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a9c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 7 QCOM_GPI_SPI>, + <&gpi_dma1 1 7 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi7_data_clk>, <&qup_spi7_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + }; + + remoteproc_soccp: remoteproc@d00000 { + compatible =3D "qcom,maili-soccp-pas", "qcom,kaanapali-soccp-pas"; + reg =3D <0x0 0x00d00000 0x0 0x200000>; + + interrupts-extended =3D <&intc GIC_ESPI 231 IRQ_TYPE_EDGE_RISING>, + <&smp2p_soccp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_soccp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_soccp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_soccp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_soccp_in 9 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "pong"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names =3D "cx", + "mx"; + + memory-region =3D <&soccp_mem>, + <&soccp_dtb_mem>; + + qcom,smem-states =3D <&smp2p_soccp_out 0>, + <&smp2p_soccp_out 8>; + qcom,smem-state-names =3D "stop", + "ping"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "soccp"; + qcom,remote-pid =3D <19>; + }; + }; + + aggre_noc: interconnect@f00000 { + compatible =3D "qcom,maili-aggre-noc"; + reg =3D <0x0 0x00f00000 0x0 0x56200>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + usb_hsphy: phy@fe3000 { + compatible =3D "qcom,maili-m31-eusb2-phy", "qcom,sm8750-m31-eusb2-phy"; + reg =3D <0x0 0x00fe3000 0x0 0x29c>; + + clocks =3D <&tcsrcc TCSR_USB2_CLKREF_EN>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_dp_qmpphy: phy@fe8000 { + compatible =3D "qcom,maili-qmp-usb3-dp-phy", "qcom,hawi-qmp-usb3-dp-phy= "; + reg =3D <0x0 0x00fe8000 0x0 0x4000>; + + clocks =3D <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names =3D "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets =3D <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names =3D "phy", + "common"; + + power-domains =3D <&gcc GCC_USB3_PHY_GDSC>; + + #clock-cells =3D <1>; + #phy-cells =3D <1>; + + orientation-switch; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_dp_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb_dp_qmpphy_usb_ss_in: endpoint { + remote-endpoint =3D <&usb_dwc3_ss>; + }; + }; + + port@2 { + reg =3D <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + + rng@10c3000 { + compatible =3D "qcom,maili-trng", "qcom,trng"; + reg =3D <0x0 0x010c3000 0x0 0x1000>; + }; + + ipcc: mailbox@1106000 { + compatible =3D "qcom,maili-ipcc", "qcom,ipcc"; + reg =3D <0x0 0x01106000 0x0 0x1000>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + #mbox-cells =3D <2>; + }; + + cnoc_main: interconnect@1500000 { + compatible =3D "qcom,maili-cnoc-main"; + reg =3D <0x0 0x01500000 0x0 0x20000>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible =3D "qcom,maili-system-noc"; + reg =3D <0x0 0x01680000 0x0 0x20080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + pcie_anoc: interconnect@16c0000 { + compatible =3D "qcom,maili-pcie-anoc"; + reg =3D <0x0 0x016c0000 0x0 0x12400>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1780000 { + compatible =3D "qcom,maili-mmss-noc"; + reg =3D <0x0 0x01780000 0x0 0x5f800>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + gpi_dma3: dma-controller@1900000 { + compatible =3D "qcom,maili-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x01900000 0x0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <12>; + dma-channel-mask =3D <0x1f>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0xd6 0x0>; + dma-coherent; + }; + + qupv3_3: geniqup@19c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x019c0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + + iommus =3D <&apps_smmu 0xc3 0x0>; + + dma-coherent; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + i2c13: i2c@1980000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01980000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma3 0 0 QCOM_GPI_I2C>, + <&gpi_dma3 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c13_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart13: serial@1980000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x01980000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart13_default>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + spi13: spi@1980000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x01980000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma3 0 0 QCOM_GPI_SPI>, + <&gpi_dma3 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi13_data_clk>, <&qup_spi13_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c14: i2c@1984000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01984000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma3 0 1 QCOM_GPI_I2C>, + <&gpi_dma3 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c14_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart14: serial@1984000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x01984000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart14_default>, <&qup_uart14_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + spi14: spi@1984000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x01984000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma3 0 1 QCOM_GPI_SPI>, + <&gpi_dma3 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi14_data_clk>, <&qup_spi14_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c15: i2c@1988000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01988000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma3 0 2 QCOM_GPI_I2C>, + <&gpi_dma3 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c15_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart15: serial@1988000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x01988000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart15_default>, <&qup_uart15_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + spi15: spi@1988000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x01988000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma3 0 2 QCOM_GPI_SPI>, + <&gpi_dma3 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi15_data_clk>, <&qup_spi15_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c16: i2c@198c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x0198c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma3 0 3 QCOM_GPI_I2C>, + <&gpi_dma3 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c16_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart16: serial@198c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x0198c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart16_default>, <&qup_uart16_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + spi16: spi@198c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x0198c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma3 0 3 QCOM_GPI_SPI>, + <&gpi_dma3 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi16_data_clk>, <&qup_spi16_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c17: i2c@1990000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01990000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma3 0 4 QCOM_GPI_I2C>, + <&gpi_dma3 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c17_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart17: serial@1990000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x01990000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart17_default>, <&qup_uart17_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + spi17: spi@1990000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x01990000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma3 0 4 QCOM_GPI_SPI>, + <&gpi_dma3 1 4 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi17_data_clk>, <&qup_spi17_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c18: i2c@1994000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01994000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S5_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma3 0 5 QCOM_GPI_I2C>, + <&gpi_dma3 1 5 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c18_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart18: serial@1994000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x01994000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S5_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart18_default>, <&qup_uart18_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + spi18: spi@1994000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x01994000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S5_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma3 0 5 QCOM_GPI_SPI>, + <&gpi_dma3 1 5 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi18_data_clk>, <&qup_spi18_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + }; + + gpi_dma4: dma-controller@1a00000 { + compatible =3D "qcom,maili-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x01a00000 0x0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <12>; + dma-channel-mask =3D <0x1f>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0x136 0x0>; + dma-coherent; + }; + + qupv3_4: geniqup@1ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x01ac0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_WRAP_4_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_4_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + + iommus =3D <&apps_smmu 0x123 0x0>; + + dma-coherent; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + i2c19: i2c@1a80000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01a80000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma4 0 0 QCOM_GPI_I2C>, + <&gpi_dma4 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c19_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart19: serial@1a80000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x01a80000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart19_default>, <&qup_uart19_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + spi19: spi@1a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x01a80000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma4 0 0 QCOM_GPI_SPI>, + <&gpi_dma4 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi19_data_clk>, <&qup_spi19_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c20: i2c@1a84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01a84000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma4 0 1 QCOM_GPI_I2C>, + <&gpi_dma4 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c20_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart20: serial@1a84000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x01a84000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart20_default>, <&qup_uart20_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + spi20: spi@1a84000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x01a84000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma4 0 1 QCOM_GPI_SPI>, + <&gpi_dma4 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi20_data_clk>, <&qup_spi20_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c21: i2c@1a88000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01a88000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma4 0 2 QCOM_GPI_I2C>, + <&gpi_dma4 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c21_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart21: serial@1a88000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x01a88000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart21_default>, <&qup_uart21_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + spi21: spi@1a88000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x01a88000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma4 0 2 QCOM_GPI_SPI>, + <&gpi_dma4 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi21_data_clk>, <&qup_spi21_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c22: i2c@1a8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01a8c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma4 0 3 QCOM_GPI_I2C>, + <&gpi_dma4 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c22_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart22: serial@1a8c000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x01a8c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart22_default>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + i2c23: i2c@1a90000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01a90000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma4 0 4 QCOM_GPI_I2C>, + <&gpi_dma4 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c23_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart23: serial@1a90000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x01a90000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart23_default>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + }; + + pcie0: pcie@1c00000 { + device_type =3D "pci"; + compatible =3D "qcom,maili-pcie", "qcom,hawi-pcie"; + reg =3D <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d00000>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr", + "cnoc_sf_axi"; + + resets =3D <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + interconnects =3D <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + power-domains =3D <&gcc GCC_PCIE_0_GDSC>; + + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555>; + + operating-points-v2 =3D <&pcie0_opp_table>; + + iommu-map =3D <0x0 &apps_smmu 0x1000 0x1>, + <0x100 &apps_smmu 0x1001 0x1>; + + interrupt-map =3D <0 0 0 1 &intc 0 0 GIC_ESPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_ESPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_ESPI 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_ESPI 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask =3D <0 0 0 0x7>; + #interrupt-cells =3D <1>; + + msi-map =3D <0x0 &gic_its 0x1000 0x1>, + <0x100 &gic_its 0x1001 0x1>; + msi-map-mask =3D <0xff00>; + + linux,pci-domain =3D <0>; + bus-range =3D <0x00 0xff>; + + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + dma-coherent; + + status =3D "disabled"; + + pcie0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* 2.5 GT/s x1 */ + opp-2500000-1 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + opp-peak-kBps =3D <250000 1>; + opp-level =3D <1>; + }; + + /* 2.5 GT/s x2 */ + opp-5000000-1 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <1>; + }; + + /* 5.0 GT/s x1 */ + opp-5000000-2 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <2>; + }; + + /* 8.0 GT/s x1 */ + opp-8000000-3 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <984500 1>; + opp-level =3D <3>; + }; + + /* 5.0 GT/s x2 */ + opp-10000000-2 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + opp-peak-kBps =3D <1000000 1>; + opp-level =3D <2>; + }; + + /* 8.0 GT/s x2 */ + opp-16000000-3 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1969000 1>; + opp-level =3D <3>; + }; + }; + + pcie_port0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + phys =3D <&pcie0_phy>; + }; + }; + + pcie0_phy: phy@1c06000 { + compatible =3D "qcom,maili-qmp-gen3x2-pcie-phy", + "qcom,hawi-qmp-gen3x2-pcie-phy"; + reg =3D <0x0 0x01c06000 0x0 0x2000>; + + clocks =3D <&gcc GCC_PCIE_0_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&tcsrcc TCSR_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPE_DIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + assigned-clocks =3D <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + resets =3D <&gcc GCC_PCIE_0_PHY_BCR>, + <&gcc GCC_PCIE_0_NOCSR_COM_PHY_BCR>; + reset-names =3D "phy", + "phy_nocsr"; + + power-domains =3D <&gcc GCC_PCIE_0_PHY_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie0_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + pcie1: pcie@1c18000 { + device_type =3D "pci"; + compatible =3D "qcom,maili-pcie", "qcom,hawi-pcie"; + reg =3D <0x0 0x01c18000 0x0 0x3000>, + <0x0 0x64000000 0x0 0xf1d>, + <0x0 0x64000f20 0x0 0xa8>, + <0x0 0x64001000 0x0 0x1000>, + <0x0 0x64100000 0x0 0x100000>, + <0x0 0x01c1b000 0x0 0x1000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>, + <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x1bd00000>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7", "global"; + + clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr", + "cnoc_sf_axi"; + + resets =3D <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + interconnects =3D <&pcie_anoc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + power-domains =3D <&gcc GCC_PCIE_1_GDSC>; + + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555>; + + operating-points-v2 =3D <&pcie1_opp_table>; + + iommu-map =3D <0x0 &apps_smmu 0x1080 0x1>, + <0x100 &apps_smmu 0x1081 0x1>; + + interrupt-map =3D <0 0 0 1 &intc 0 0 GIC_ESPI 42 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_ESPI 43 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_ESPI 44 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_ESPI 45 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask =3D <0 0 0 0x7>; + #interrupt-cells =3D <1>; + + msi-map =3D <0x0 &gic_its 0x1080 0x1>, + <0x100 &gic_its 0x1081 0x1>; + msi-map-mask =3D <0xff00>; + linux,pci-domain =3D <1>; + bus-range =3D <0x00 0xff>; + + pinctrl-0 =3D <&pcie1_default_state>; + pinctrl-names =3D "default"; + + dma-coherent; + + status =3D "disabled"; + + pcie1_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* 2.5 GT/s x1 */ + opp-2500000-1 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + opp-peak-kBps =3D <250000 1>; + opp-level =3D <1>; + }; + + /* 2.5 GT/s x2 */ + opp-5000000-1 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <1>; + }; + + /* 5.0 GT/s x1 */ + opp-5000000-2 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <2>; + }; + + /* 8.0 GT/s x1 */ + opp-8000000-3 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <984500 1>; + opp-level =3D <3>; + }; + + /* 5.0 GT/s x2 */ + opp-10000000-2 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + opp-peak-kBps =3D <1000000 1>; + opp-level =3D <2>; + }; + + /* 8.0 GT/s x2 */ + opp-16000000-3 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1969000 1>; + opp-level =3D <3>; + }; + + /* 16.0 GT/s x1 */ + opp-16000000-4 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <1969000 1>; + opp-level =3D <4>; + }; + + /* 16.0 GT/s x2 */ + opp-32000000-3 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <4>; + }; + }; + + pcie_port1: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + phys =3D <&pcie1_phy>; + }; + }; + + pcie1_phy: phy@1c1e000 { + compatible =3D "qcom,maili-qmp-gen4x1-pcie-phy", + "qcom,hawi-qmp-gen4x1-pcie-phy"; + reg =3D <0x0 0x01c1e000 0x0 0x2000>; + + clocks =3D <&gcc GCC_PCIE_1_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&tcsrcc TCSR_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPE_DIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + assigned-clocks =3D <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + resets =3D <&gcc GCC_PCIE_1_PHY_BCR>, + <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; + reset-names =3D "phy", + "phy_nocsr"; + + power-domains =3D <&gcc GCC_PCIE_1_PHY_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie1_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + sdhc_2: mmc@1c44000 { + compatible =3D "qcom,maili-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0x0 0x01c44000 0x0 0x1000>; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + + clock-names =3D "iface", "core", "xo"; + + interconnects =3D <&aggre_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + + interconnect-names =3D "sdhc-ddr", "cpu-sdhc"; + + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&sdhc2_opp_table>; + + qcom,dll-config =3D <0x0007442c>; + qcom,ddr-config =3D <0x80040868>; + + iommus =3D <&apps_smmu 0x140 0x0>; + dma-coherent; + + bus-width =3D <4>; + max-sd-hs-hz =3D <37500000>; + + resets =3D <&gcc GCC_SDCC2_BCR>; + status =3D "disabled"; + + sdhc2_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + opp-peak-kBps =3D <160000 100000>; + opp-avg-kBps =3D <50000 0>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz =3D /bits/ 64 <202000000>; + opp-peak-kBps =3D <200000 120000>; + opp-avg-kBps =3D <104000 0>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + + }; + + ufs_mem_phy: phy@1d80000 { + compatible =3D "qcom,maili-qmp-ufs-phy", "qcom,hawi-qmp-ufs-phy"; + reg =3D <0x0 0x01d80000 0x0 0x4000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsrcc TCSR_UFS_CLKREF_EN>; + + clock-names =3D "ref", + "ref_aux", + "qref"; + + resets =3D <&ufs_mem_hc 0>; + reset-names =3D "ufsphy"; + + power-domains =3D <&gcc GCC_UFS_MEM_PHY_GDSC>; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + ufs_mem_hc: ufshc@1d84000 { + compatible =3D "qcom,maili-ufshc", + "qcom,ufshc", + "jedec,ufs-2.0"; + reg =3D <0x0 0x01d84000 0x0 0x3000>, + <0x0 0x01da0000 0x0 0x15000>; + + reg-names =3D "std", + "mcq"; + + interrupts =3D ; + + clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_5_CORE_CLK>, + <&rpmhcc RPMH_LN_BB_CLK3>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + operating-points-v2 =3D <&ufs_opp_table>; + + resets =3D <&gcc GCC_UFS_PHY_BCR>; + reset-names =3D "rst"; + + interconnects =3D <&aggre_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "ufs-ddr", + "cpu-ufs"; + + power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + iommus =3D <&apps_smmu 0x60 0x0>; + dma-coherent; + + msi-parent =3D <&gic_its 0x60>; + + lanes-per-direction =3D <2>; + limit-hs-gear =3D <5>; + + phys =3D <&ufs_mem_phy>; + phy-names =3D "ufsphy"; + + qcom,ice =3D <&ice>; + + #reset-cells =3D <1>; + + status =3D "disabled"; + + ufs_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-403000000 { + opp-hz =3D /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + ice: crypto@1d88000 { + compatible =3D "qcom,maili-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg =3D <0x0 0x01d88000 0x0 0x18000>; + + clocks =3D <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names =3D "core", + "iface"; + + power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; + }; + + videocc: clock-controller@20f0000 { + compatible =3D "qcom,maili-videocc"; + reg =3D <0x0 0x020f0000 0x0 0x10000>; + + clocks =3D <&bi_tcxo_div2>, + <&gcc GCC_VIDEO_AHB_CLK>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps =3D <&rpmhpd_opp_low_svs_d2>, + <&rpmhpd_opp_low_svs_d2>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + apps_smmu: iommu@2e00000 { + compatible =3D "qcom,maili-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x02e00000 0x0 0x100000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + + dma-coherent; + }; + + stdst_noc: interconnect@3000000 { + compatible =3D "qcom,maili-stdst-main"; + reg =3D <0x0 0x03000000 0x0 0xf9000>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + tcsr: syscon@3a70000 { + compatible =3D "qcom,maili-tcsr", "syscon"; + reg =3D <0x0 0x03a70000 0x0 0x10000>; + }; + + tcsr_mutex: hwlock@3ad3000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x03ad3000 0x0 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsrcc: clock-controller@3b13040 { + compatible =3D "qcom,maili-tcsrcc", "qcom,hawi-tcsrcc", "syscon"; + reg =3D <0x0 0x03b13040 0x0 0x50>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + gxclkctl: clock-controller@3d64000 { + compatible =3D "qcom,maili-gxclkctl", "qcom,kaanapali-gxclkctl"; + reg =3D <0x0 0x03d64000 0x0 0x6000>; + + power-domains =3D <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_GMXC>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells =3D <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,maili-gpucc"; + reg =3D <0x0 0x03d90000 0x0 0x9800>; + + clocks =3D <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_GMXC>; + required-opps =3D <&rpmhpd_opp_low_svs_d3>, + <&rpmhpd_opp_low_svs_d3>, + <&rpmhpd_opp_low_svs_d3>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible =3D "qcom,maili-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks =3D <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>; + clock-names =3D "hlos"; + power-domains =3D <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + + remoteproc_mpss: remoteproc@4000000 { + compatible =3D "qcom,maili-mpss-pas", "qcom,sm8650-mpss-pas"; + reg =3D <0x0 0x04000000 0x0 0x10000>; + + interrupts-extended =3D <&intc GIC_ESPI 328 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + interconnects =3D <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MSS>; + power-domain-names =3D "cx", + "mss"; + + memory-region =3D <&mpss_mem>, <&q6_mpss_dtb_mem>, + <&dsm_partition_1_mem>, <&dsm_partition_2_mem>, + <&mpss_crashdump_overlay_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_modem_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_MPROC_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_MPROC_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "mpss"; + qcom,remote-pid =3D <1>; + }; + }; + + remoteproc_adsp: remoteproc@7000000 { + compatible =3D "qcom,maili-adsp-pas", "qcom,sm8550-adsp-pas"; + reg =3D <0x0 0x07000000 0x0 0x10000>; + + interrupts-extended =3D <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + interconnects =3D <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWA= YS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains =3D <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names =3D "lcx", + "lmx"; + + memory-region =3D <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_adsp_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "lpass"; + qcom,remote-pid =3D <2>; + + fastrpc { + compatible =3D "qcom,maili-fastrpc", "qcom,kaanapali-fastrpc"; + qcom,glink-channels =3D "fastrpcglink-apps-dsp"; + label =3D "adsp"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + compute-cb@3 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <3>; + + iommus =3D <&apps_smmu 0x0c03 0x80>, + <&apps_smmu 0x0c43 0x20>; + dma-coherent; + }; + + compute-cb@4 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <4>; + + iommus =3D <&apps_smmu 0x0c04 0x80>, + <&apps_smmu 0x0c44 0x20>; + dma-coherent; + }; + + compute-cb@5 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <5>; + + iommus =3D <&apps_smmu 0x0c05 0x80>, + <&apps_smmu 0x0c45 0x20>; + dma-coherent; + }; + + compute-cb@6 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <6>; + + iommus =3D <&apps_smmu 0x0c06 0x80>, + <&apps_smmu 0x0c46 0x20>; + dma-coherent; + }; + + compute-cb@7 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <7>; + + iommus =3D <&apps_smmu 0x0c07 0x80>, + <&apps_smmu 0x0c47 0x20>; + dma-coherent; + }; + + compute-cb@8 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <8>; + + iommus =3D <&apps_smmu 0x0c08 0x80>, + <&apps_smmu 0x0c48 0x20>; + dma-coherent; + }; + }; + }; + }; + + lpass_lpiaon_noc: interconnect@7c00000 { + compatible =3D "qcom,maili-lpass-lpiaon-noc"; + reg =3D <0x0 0x07c00000 0x0 0x19080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + lpass_lpicx_noc: interconnect@7c20000 { + compatible =3D "qcom,maili-lpass-lpicx-noc"; + reg =3D <0x0 0x07c20000 0x0 0x46080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + llclpi_noc: interconnect@7cd0000 { + compatible =3D "qcom,maili-llclpi-noc"; + reg =3D <0x0 0x07cd0000 0x0 0x17200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + lpass_ag_noc: interconnect@8f40000 { + compatible =3D "qcom,maili-lpass-ag-noc"; + reg =3D <0x0 0x08f40000 0x0 0xc080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + usb: usb@a600000 { + compatible =3D "qcom,maili-dwc3", "qcom,snps-dwc3"; + reg =3D <0x0 0x0a600000 0x0 0xfc100>; + clocks =3D <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_STARDUSTNOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks =3D <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <200000000>; + + interrupts-extended =3D <&intc GIC_ESPI 196 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_ESPI 194 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_ESPI 195 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "dwc_usb3", + "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains =3D <&gcc GCC_USB30_PRIM_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + resets =3D <&gcc GCC_USB30_PRIM_BCR>; + + interconnects =3D <&aggre_noc MASTER_USB3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "usb-ddr", + "apps-usb"; + iommus =3D <&apps_smmu 0x40 0x0>; + + phys =3D <&usb_hsphy>, <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names =3D "usb2-phy", "usb3-phy"; + + snps,hird-threshold =3D /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; + dma-coherent; + + usb-role-switch; + wakeup-source; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb_dwc3_ss: endpoint { + remote-endpoint =3D <&usb_dp_qmpphy_usb_ss_in>; + }; + }; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,maili-pdc", "qcom,pdc"; + reg =3D <0x0 0x0b220000 0x0 0x10000>, + <0x0 0x179600f0 0x0 0xf4>; + interrupt-parent =3D <&intc>; + #interrupt-cells =3D <2>; + interrupt-controller; + qcom,pdc-ranges =3D <0 288 202>; + }; + + tsens0: thermal-sensor@c22b000 { + compatible =3D "qcom,maili-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c22b000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <12>; + #thermal-sensor-cells =3D <1>; + }; + + tsens1: thermal-sensor@c22c000 { + compatible =3D "qcom,maili-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c22c000 0x0 0x1000>, + <0x0 0x0c223000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <7>; + #thermal-sensor-cells =3D <1>; + }; + + tsens2: thermal-sensor@c22d000 { + compatible =3D "qcom,maili-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c22d000 0x0 0x1000>, + <0x0 0x0c224000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <6>; + #thermal-sensor-cells =3D <1>; + }; + + tsens3: thermal-sensor@c22e000 { + compatible =3D "qcom,maili-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c22e000 0x0 0x1000>, + <0x0 0x0c225000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <7>; + #thermal-sensor-cells =3D <1>; + }; + + tsens4: thermal-sensor@c22f000 { + compatible =3D "qcom,maili-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c22f000 0x0 0x1000>, + <0x0 0x0c226000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <9>; + #thermal-sensor-cells =3D <1>; + }; + + tsens5: thermal-sensor@c230000 { + compatible =3D "qcom,maili-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c230000 0x0 0x1000>, + <0x0 0x0c227000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <11>; + #thermal-sensor-cells =3D <1>; + }; + + tsens6: thermal-sensor@c231000 { + compatible =3D "qcom,maili-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c231000 0x0 0x1000>, + <0x0 0x0c228000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <8>; + #thermal-sensor-cells =3D <1>; + }; + + aoss_qmp: power-management@c300000 { + compatible =3D "qcom,maili-aoss-qmp", "qcom,aoss-qmp"; + reg =3D <0x0 0x0c300000 0x0 0x400>; + interrupts-extended =3D <&ipcc IPCC_MPROC_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_MPROC_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells =3D <0>; + }; + + arbiter@c400000 { + compatible =3D "qcom,maili-spmi-pmic-arb", + "qcom,glymur-spmi-pmic-arb"; + reg =3D <0x0 0x0c400000 0x0 0x3000>, + <0x0 0x0c900000 0x0 0x400000>, + <0x0 0x0c4c0000 0x0 0x400000>, + <0x0 0x0c403000 0x0 0x8000>; + reg-names =3D "core", + "chnls", + "obsrvr", + "chnl_map"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + qcom,channel =3D <0>; + qcom,ee =3D <0>; + + spmi_bus0: spmi@c426000 { + reg =3D <0x0 0x0c426000 0x0 0x4000>, + <0x0 0x0c8c0000 0x0 0x10000>, + <0x0 0x0c42a000 0x0 0x8000>; + reg-names =3D "cnfg", + "intr", + "chnl_owner"; + interrupts-extended =3D <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "periph_irq"; + interrupt-controller; + #interrupt-cells =3D <4>; + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + + spmi_bus1: spmi@c437000 { + reg =3D <0x0 0x0c437000 0x0 0x4000>, + <0x0 0x0c8d0000 0x0 0x10000>, + <0x0 0x0c43b000 0x0 0x8000>; + reg-names =3D "cnfg", + "intr", + "chnl_owner"; + interrupts-extended =3D <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "periph_irq"; + interrupt-controller; + #interrupt-cells =3D <4>; + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + }; + + tlmm: pinctrl@f100000 { + compatible =3D "qcom,maili-tlmm"; + reg =3D <0x0 0x0f100000 0x0 0x102000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 227>; + interrupt-controller; + #interrupt-cells =3D <2>; + wakeup-parent =3D <&pdc>; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio0", "gpio1"; + function =3D "qup2_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi8_data_clk: qup-spi8-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio0", "gpio1", "gpio2"; + function =3D "qup2_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart8_cts_rts: qup-uart8-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio0", "gpio1"; + function =3D "qup2_se0"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart8_default: qup-uart8-default-state { + /* TX, RX */ + pins =3D "gpio2", "gpio3"; + function =3D "qup2_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins =3D "gpio3"; + function =3D "qup2_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio4", "gpio5"; + function =3D "qup2_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi9_data_clk: qup-spi9-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio4", "gpio5", "gpio6"; + function =3D "qup2_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart9_cts_rts: qup-uart9-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio4", "gpio5"; + function =3D "qup2_se1"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart9_default: qup-uart9-default-state { + /* TX, RX */ + pins =3D "gpio6", "gpio7"; + function =3D "qup2_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi9_cs: qup-spi9-cs-state { + pins =3D "gpio7"; + function =3D "qup2_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_i2c14_data_clk: qup-i2c14-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio8", "gpio9"; + function =3D "qup3_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi14_data_clk: qup-spi14-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio8", "gpio9", "gpio10"; + function =3D "qup3_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart14_cts_rts: qup-uart14-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio8", "gpio9"; + function =3D "qup3_se1"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart14_default: qup-uart14-default-state { + /* TX, RX */ + pins =3D "gpio10", "gpio11"; + function =3D "qup3_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi14_cs: qup-spi14-cs-state { + pins =3D "gpio11"; + function =3D "qup3_se1"; + drive-strength =3D <6>; + bias-pull-up; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio12", "gpio13"; + function =3D "qup3_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi15_data_clk: qup-spi15-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio12", "gpio13", "gpio14"; + function =3D "qup3_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart15_cts_rts: qup-uart15-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio12", "gpio13"; + function =3D "qup3_se2"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart15_default: qup-uart15-default-state { + /* TX, RX */ + pins =3D "gpio14", "gpio15"; + function =3D "qup3_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi15_cs: qup-spi15-cs-state { + pins =3D "gpio15"; + function =3D "qup3_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_i2c16_data_clk: qup-i2c16-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio16", "gpio17"; + function =3D "qup3_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi16_data_clk: qup-spi16-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio16", "gpio17", "gpio18"; + function =3D "qup3_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart16_cts_rts: qup-uart16-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio16", "gpio17"; + function =3D "qup3_se3"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart16_default: qup-uart16-default-state { + /* TX, RX */ + pins =3D "gpio18", "gpio19"; + function =3D "qup3_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi16_cs: qup-spi16-cs-state { + pins =3D "gpio19"; + function =3D "qup3_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_i2c17_data_clk: qup-i2c17-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio20", "gpio21"; + function =3D "qup3_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi17_data_clk: qup-spi17-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio20", "gpio21", "gpio22"; + function =3D "qup3_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart17_cts_rts: qup-uart17-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio20", "gpio21"; + function =3D "qup3_se4"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart17_default: qup-uart17-default-state { + /* TX, RX */ + pins =3D "gpio22", "gpio23"; + function =3D "qup3_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi17_cs: qup-spi17-cs-state { + pins =3D "gpio23"; + function =3D "qup3_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_i2c18_data_clk: qup-i2c18-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio24", "gpio25"; + function =3D "qup3_se5"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi18_data_clk: qup-spi18-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio24", "gpio25", "gpio26"; + function =3D "qup3_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart18_cts_rts: qup-uart18-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio24", "gpio25"; + function =3D "qup3_se5"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart18_default: qup-uart18-default-state { + /* TX, RX */ + pins =3D "gpio26", "gpio27"; + function =3D "qup3_se5"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi18_cs: qup-spi18-cs-state { + pins =3D "gpio27"; + function =3D "qup3_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_i2c20_data_clk: qup-i2c20-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio28", "gpio29"; + function =3D "qup4_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi20_data_clk: qup-spi20-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio28", "gpio29", "gpio30"; + function =3D "qup4_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart20_cts_rts: qup-uart20-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio28", "gpio29"; + function =3D "qup4_se1"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart20_default: qup-uart20-default-state { + /* TX, RX */ + pins =3D "gpio30", "gpio31"; + function =3D "qup4_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi20_cs: qup-spi20-cs-state { + pins =3D "gpio31"; + function =3D "qup4_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_i2c21_data_clk: qup-i2c21-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio32", "gpio33"; + function =3D "qup4_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi21_data_clk: qup-spi21-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio32", "gpio33", "gpio34"; + function =3D "qup4_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart21_cts_rts: qup-uart21-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio32", "gpio33"; + function =3D "qup4_se2"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart21_default: qup-uart21-default-state { + /* TX, RX */ + pins =3D "gpio34", "gpio35"; + function =3D "qup4_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi21_cs: qup-spi21-cs-state { + pins =3D "gpio35"; + function =3D "qup4_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio36", "gpio37"; + function =3D "qup1_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi4_data_clk: qup-spi4-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio36", "gpio37", "gpio38"; + function =3D "qup1_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart4_cts_rts: qup-uart4-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio36", "gpio37"; + function =3D "qup1_se4"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart4_default: qup-uart4-default-state { + /* TX, RX */ + pins =3D "gpio38", "gpio39"; + function =3D "qup1_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins =3D "gpio39"; + function =3D "qup1_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio40", "gpio41"; + function =3D "qup1_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio40", "gpio41", "gpio42"; + function =3D "qup1_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart2_cts_rts: qup-uart2-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio40", "gpio41"; + function =3D "qup1_se2"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart2_default: qup-uart2-default-state { + /* TX, RX */ + pins =3D "gpio42", "gpio43"; + function =3D "qup1_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins =3D "gpio43"; + function =3D "qup1_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio44", "gpio45"; + function =3D "qup1_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio44", "gpio45", "gpio46"; + function =3D "qup1_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart3_cts_rts: qup-uart3-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio44", "gpio45"; + function =3D "qup1_se3"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart3_default: qup-uart3-default-state { + /* TX, RX */ + pins =3D "gpio46", "gpio47"; + function =3D "qup1_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins =3D "gpio47"; + function =3D "qup1_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_i2c19_data_clk: qup-i2c19-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio48", "gpio49"; + function =3D "qup4_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi19_data_clk: qup-spi19-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio48", "gpio49", "gpio50"; + function =3D "qup4_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart19_cts_rts: qup-uart19-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio48", "gpio49"; + function =3D "qup4_se0"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart19_default: qup-uart19-default-state { + /* TX, RX */ + pins =3D "gpio50", "gpio51"; + function =3D "qup4_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi19_cs: qup-spi19-cs-state { + pins =3D "gpio51"; + function =3D "qup4_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio52", "gpio53"; + function =3D "qup1_se5"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio52", "gpio53", "gpio54"; + function =3D "qup1_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart5_cts_rts: qup-uart5-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio52", "gpio53"; + function =3D "qup1_se5"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart5_default: qup-uart5-default-state { + /* TX, RX */ + pins =3D "gpio54", "gpio55"; + function =3D "qup1_se5"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins =3D "gpio55"; + function =3D "qup1_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + sdc2_default: sdc2-default-state { + card-detect-pins { + pins =3D "gpio55"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + clk-pins { + pins =3D "gpio56"; + function =3D "sdc2_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + cmd-pins { + pins =3D "gpio57"; + function =3D "sdc2_cmd"; + drive-strength =3D <10>; + bias-pull-up; + }; + + data-pins { + pins =3D "gpio74", "gpio75", "gpio76", "gpio77"; + function =3D "sdc2_data"; + drive-strength =3D <10>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + card-detect-pins { + pins =3D "gpio55"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + clk-pins { + pins =3D "gpio56"; + function =3D "sdc2_clk"; + drive-strength =3D <2>; + bias-disable; + }; + + cmd-pins { + pins =3D "gpio57"; + function =3D "sdc2_cmd"; + drive-strength =3D <2>; + bias-pull-up; + }; + + data-pins { + pins =3D "gpio74", "gpio75", "gpio76", "gpio77"; + function =3D "sdc2_data"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio56", "gpio57"; + function =3D "qup1_se6"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio56", "gpio57", "gpio58"; + function =3D "qup1_se6"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart6_cts_rts: qup-uart6-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio56", "gpio57"; + function =3D "qup1_se6"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart6_default: qup-uart6-default-state { + /* TX, RX */ + pins =3D "gpio58", "gpio59"; + function =3D "qup1_se6"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins =3D "gpio59"; + function =3D "qup1_se6"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio60", "gpio61"; + function =3D "qup1_se7"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi7_data_clk: qup-spi7-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio60", "gpio61", "gpio62"; + function =3D "qup1_se7"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart7_default: qup-uart7-state { + /* TX, RX */ + pins =3D "gpio62", "gpio63"; + function =3D "qup1_se7"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_spi7_cs: qup-spi7-cs-state { + pins =3D "gpio63"; + function =3D "qup1_se7"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio64", "gpio65"; + function =3D "qup3_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi13_data_clk: qup-spi13-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio64", "gpio65", "gpio66"; + function =3D "qup3_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart13_cts_rts: qup-uart13-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio64", "gpio65"; + function =3D "qup3_se0"; + drive-strength =3D <2>; + bias-pull-down; + }; + + hub_i2c0_data_clk: hub-i2c0-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio66", "gpio67"; + function =3D "i2chub0_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_uart13_default: qup-uart13-default-state { + /* TX, RX */ + pins =3D "gpio66", "gpio67"; + function =3D "qup3_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi13_cs: qup-spi13-cs-state { + pins =3D "gpio67"; + function =3D "qup3_se0"; + drive-strength =3D <6>; + bias-pull-up; + }; + + hub_i2c2_data_clk: hub-i2c2-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio68", "gpio69"; + function =3D "i2chub0_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + hub_i2c3_data_clk: hub-i2c3-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio70", "gpio71"; + function =3D "i2chub0_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + hub_i2c4_data_clk: hub-i2c4-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio72", "gpio73"; + function =3D "i2chub0_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio74", "gpio75"; + function =3D "qup1_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi1_data_clk: qup-spi1-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio74", "gpio75", "gpio76"; + function =3D "qup1_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart1_cts_rts: qup-uart1-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio74", "gpio75"; + function =3D "qup1_se1"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart1_default: qup-uart1-default-state { + /* TX, RX */ + pins =3D "gpio76", "gpio77"; + function =3D "qup1_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins =3D "gpio77"; + function =3D "qup1_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + hub_i2c1_data_clk: hub-i2c1-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio78", "gpio79"; + function =3D "i2chub0_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + pcie1_default_state: pcie1-default-state { + wake-n-pins { + pins =3D "gpio80"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio220"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + clkreq-n-pins { + pins =3D "gpio221"; + function =3D "pcie1_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie0_default_state: pcie0-default-state { + perst-n-pins { + pins =3D "gpio102"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + clkreq-n-pins { + pins =3D "gpio103"; + function =3D "pcie0_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + + wake-n-pins { + pins =3D "gpio104"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio117", "gpio118"; + function =3D "qup2_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi10_data_clk: qup-spi10-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio117", "gpio118", "gpio119"; + function =3D "qup2_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart10_cts_rts: qup-uart10-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio117", "gpio118"; + function =3D "qup2_se2"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart10_default: qup-uart10-default-state { + /* TX, RX */ + pins =3D "gpio119", "gpio120"; + function =3D "qup2_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins =3D "gpio120"; + function =3D "qup2_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_i2c22_data_clk: qup-i2c22-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio121", "gpio84"; + function =3D "qup4_se3_01"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_uart22_default: qup-uart22-default-state { + /* TX, RX */ + pins =3D "gpio121", "gpio98"; + function =3D "qup4_se3_23"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio122", "gpio123"; + function =3D "qup2_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi11_data_clk: qup-spi11-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio122", "gpio123", "gpio124"; + function =3D "qup2_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart11_cts_rts: qup-uart11-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio122", "gpio123"; + function =3D "qup2_se3"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart11_default: qup-uart11-default-state { + /* TX, RX */ + pins =3D "gpio124", "gpio125"; + function =3D "qup2_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi11_cs: qup-spi11-cs-state { + pins =3D "gpio125"; + function =3D "qup2_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_i2c23_data_clk: qup-i2c23-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio161", "gpio162"; + function =3D "qup4_se4_01"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_uart23_default: qup-uart23-default-state { + /* TX, RX */ + pins =3D "gpio161", "gpio162"; + function =3D "qup4_se4_23"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio208", "gpio209"; + function =3D "qup2_se4_01"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_uart12_default: qup-uart12-default-state { + /* TX, RX */ + pins =3D "gpio208", "gpio209"; + function =3D "qup2_se4_23"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio222", "gpio223"; + function =3D "qup1_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio222", "gpio223", "gpio224"; + function =3D "qup1_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart0_cts_rts: qup-uart0-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio222", "gpio223"; + function =3D "qup1_se0"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart0_default: qup-uart0-default-state { + /* TX, RX */ + pins =3D "gpio224", "gpio225"; + function =3D "qup1_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins =3D "gpio225"; + function =3D "qup1_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + }; + + sram@14680000 { + compatible =3D "qcom,maili-imem", "mmio-sram"; + reg =3D <0x0 0x14680000 0x0 0x1000>; + ranges =3D <0x0 0x0 0x14680000 0x1000>; + + no-memory-wc; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + pil-sram@94c { + compatible =3D "qcom,pil-reloc-info"; + reg =3D <0x94c 0xc8>; + }; + }; + + intc: interrupt-controller@17000000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x17000000 0x0 0x10000>, + <0x0 0x17080000 0x0 0x200000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + interrupts =3D ; + #interrupt-cells =3D <3>; + interrupt-controller; + #redistributor-regions =3D <1>; + + gic_its: msi-controller@17040000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x17040000 0x0 0x20000>; + msi-controller; + #msi-cells =3D <1>; + }; + }; + + watchdog@17600000 { + compatible =3D "qcom,apss-wdt-maili", "qcom,kpss-wdt"; + reg =3D <0x0 0x17600000 0x0 0x1000>; + clocks =3D <&sleep_clk>; + interrupts =3D ; + }; + + pdp0_mbox: mailbox@17610000 { + compatible =3D "qcom,maili-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; + reg =3D <0x0 0x17610000 0x0 0x8000>, <0x0 0x19990000 0x0 0x8000>; + interrupts =3D ; + #mbox-cells =3D <1>; + }; + + timer@17810000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x17810000 0x0 0x1000>; + + #address-cells =3D <2>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x0 0x0 0x20000000>; + + frame@17811000 { + reg =3D <0x0 0x17811000 0x1000>, + <0x0 0x17812000 0x1000>; + frame-number =3D <0>; + interrupts =3D , + ; + }; + + frame@17813000 { + reg =3D <0x0 0x17813000 0x1000>; + frame-number =3D <1>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17815000 { + reg =3D <0x0 0x17815000 0x1000>; + frame-number =3D <2>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17817000 { + reg =3D <0x0 0x17817000 0x1000>; + frame-number =3D <3>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17819000 { + reg =3D <0x0 0x17819000 0x1000>; + frame-number =3D <4>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@1781b000 { + reg =3D <0x0 0x1781b000 0x1000>; + frame-number =3D <5>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@1781d000 { + reg =3D <0x0 0x1781d000 0x1000>; + frame-number =3D <6>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + + apps_rsc: rsc@18900000 { + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0x0 0x18900000 0x0 0x10000>, + <0x0 0x18910000 0x0 0x10000>, + <0x0 0x18920000 0x0 0x10000>; + reg-names =3D "drv-0", "drv-1", "drv-2"; + interrupts =3D , + , + ; + + power-domains =3D <&cluster_pd>; + label =3D "apps_rsc"; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , + , + , + ; + qcom,tcs-offset =3D <0xd00>; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible =3D "qcom,maili-rpmh-clk", "qcom,hawi-rpmh-clk"; + #clock-cells =3D <1>; + clock-names =3D "xo"; + clocks =3D <&xo_board>; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,maili-rpmhpd", "qcom,hawi-rpmhpd"; + + operating-points-v2 =3D <&rpmhpd_opp_table>; + + #power-domain-cells =3D <1>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d3_0: opp-49 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d3: opp-50 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d2_1: opp-51 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d2: opp-52 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d1_1: opp-54 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d1_0: opp-55 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d1: opp-56 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d0_0: opp-59 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d0: opp-60 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_l0: opp-76 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_l1: opp-80 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_l2: opp-96 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l0: opp-144 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l2: opp-224 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l2_0: opp-225 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l2: opp-336 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l0: opp-400 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1_0: opp-417 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1_1: opp-418 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1_2: opp-419 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l2: opp-432 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l3: opp-448 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l3_0: opp-449 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l3_1: opp-450 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l3_2: opp-451 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l4: opp-452 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l5: opp-456 { + opp-level =3D ; + }; + + rpmhpd_opp_super_turbo_no_cpr: opp-480 { + opp-level =3D ; + }; + }; + }; + }; + + efuse@221c8000 { + compatible =3D "qcom,maili-qfprom", "qcom,qfprom"; + reg =3D <0x0 0x221c8000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + gpu_speed_bin: gpu-speed-bin@142 { + reg =3D <0x142 0x2>; + bits =3D <3 9>; + }; + }; + + nsp_noc: interconnect@260c0000 { + compatible =3D "qcom,maili-nsp-noc"; + reg =3D <0x0 0x260c0000 0x0 0x21280>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + remoteproc_cdsp: remoteproc@26300000 { + compatible =3D "qcom,maili-cdsp-pas", "qcom,hawi-cdsp-pas"; + reg =3D <0x0 0x26300000 0x0 0x10000>; + + interrupts-extended =3D <&intc GIC_ESPI 642 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + interconnects =3D <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_NSP>; + power-domain-names =3D "cx", + "mxc", + "nsp"; + + memory-region =3D <&cdsp_mem>, <&q6_cdsp_dtb_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_cdsp_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "cdsp"; + qcom,remote-pid =3D <5>; + + fastrpc { + compatible =3D "qcom,maili-fastrpc", "qcom,kaanapali-fastrpc"; + qcom,glink-channels =3D "fastrpcglink-apps-dsp"; + label =3D "cdsp"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + compute-cb@1 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <1>; + + iommus =3D <&apps_smmu 0x0801 0x40>, + <&apps_smmu 0x15c1 0x0>; + dma-coherent; + }; + + compute-cb@2 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <2>; + + iommus =3D <&apps_smmu 0x0802 0x40>, + <&apps_smmu 0x15c2 0x0>; + dma-coherent; + }; + + compute-cb@3 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <3>; + + iommus =3D <&apps_smmu 0x0803 0x40>, + <&apps_smmu 0x15c3 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <4>; + + iommus =3D <&apps_smmu 0x0804 0x40>, + <&apps_smmu 0x15c4 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <5>; + + iommus =3D <&apps_smmu 0x0805 0x40>, + <&apps_smmu 0x15c5 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <6>; + + iommus =3D <&apps_smmu 0x0806 0x40>, + <&apps_smmu 0x15c6 0x0>; + dma-coherent; + }; + + compute-cb@7 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <7>; + + iommus =3D <&apps_smmu 0x0807 0x40>, + <&apps_smmu 0x15c7 0x0>; + dma-coherent; + }; + + compute-cb@8 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <8>; + + iommus =3D <&apps_smmu 0x0808 0x40>, + <&apps_smmu 0x15c8 0x0>; + dma-coherent; + }; + + compute-cb@12 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <12>; + + iommus =3D <&apps_smmu 0x080c 0x40>, + <&apps_smmu 0x15cc 0x0>; + dma-coherent; + }; + }; + }; + }; + + pmu@310b7400 { + compatible =3D "qcom,maili-cpu-bwmon", "qcom,sdm845-bwmon"; + reg =3D <0x0 0x310b7400 0x0 0x600>; + + interrupts =3D ; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 =3D <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-0 { + opp-peak-kBps =3D <2188000>; + }; + + opp-1 { + opp-peak-kBps =3D <5412000>; + }; + + opp-2 { + opp-peak-kBps =3D <6220000>; + }; + + opp-3 { + opp-peak-kBps =3D <6832000>; + }; + + opp-4 { + opp-peak-kBps =3D <8368000>; + }; + + opp-5 { + opp-peak-kBps =3D <10944000>; + }; + + opp-6 { + opp-peak-kBps =3D <12748000>; + }; + + opp-7 { + opp-peak-kBps =3D <14744000>; + }; + + opp-8 { + opp-peak-kBps =3D <16896000>; + }; + + opp-9 { + opp-peak-kBps =3D <19120000>; + }; + + opp-10 { + opp-peak-kBps =3D <21332000>; + }; + }; + }; + + gem_noc: interconnect@31100000 { + compatible =3D "qcom,maili-gem-noc"; + reg =3D <0x0 0x31100000 0x0 0x160200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + config_noc: stdst_cfg: interconnect@313c0000 { + compatible =3D "qcom,maili-stdst-cfg"; + reg =3D <0x0 0x313c0000 0x0 0x9000>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system-cache-controller@31800000 { + compatible =3D "qcom,maili-llcc", "qcom,hawi-llcc"; + reg =3D <0x0 0x31800000 0x0 0x200000>, + <0x0 0x32800000 0x0 0x200000>, + <0x0 0x31c00000 0x0 0x200000>, + <0x0 0x32c00000 0x0 0x200000>, + <0x0 0x34800000 0x0 0x200000>, + <0x0 0x34c00000 0x0 0x200000>; + reg-names =3D "llcc0_base", + "llcc1_base", + "llcc2_base", + "llcc3_base", + "llcc_broadcast_base", + "llcc_broadcast_and_base"; + + interrupts =3D ; + memory-region =3D <&cpucp_slc_mem_sub>; + }; + + sram: sram@81f08000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x81f08000 0x0 0x200>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x81f08000 0x200>; + + pdp_rx: scp-sram-section@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x80>; + }; + + pdp_tx: scp-sram-section@80 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x80 0x80>; + }; + }; + }; + + thermal-zones { + camera-0-thermal { + thermal-sensors =3D <&tsens6 4>; + + trips { + camera-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + camera-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + camera-1-thermal { + thermal-sensors =3D <&tsens6 5>; + + trips { + camera-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + camera-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-0-thermal { + thermal-sensors =3D <&tsens2 0>; + + trips { + cpu-0-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-1-thermal { + thermal-sensors =3D <&tsens2 1>; + + trips { + cpu-0-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-2-thermal { + thermal-sensors =3D <&tsens2 2>; + + trips { + cpu-0-2-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-2-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-1-0-thermal { + thermal-sensors =3D <&tsens2 3>; + + trips { + cpu-1-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-1-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-1-1-thermal { + thermal-sensors =3D <&tsens2 4>; + + trips { + cpu-1-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-1-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-1-2-thermal { + thermal-sensors =3D <&tsens2 5>; + + trips { + cpu-1-2-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-1-2-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-2-0-thermal { + thermal-sensors =3D <&tsens0 6>; + + trips { + cpu-2-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-2-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-2-1-thermal { + thermal-sensors =3D <&tsens0 7>; + + trips { + cpu-2-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-2-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-3-0-thermal { + thermal-sensors =3D <&tsens0 0>; + + trips { + cpu-3-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-3-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-3-1-thermal { + thermal-sensors =3D <&tsens0 1>; + + trips { + cpu-3-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-3-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-4-0-thermal { + thermal-sensors =3D <&tsens0 8>; + + trips { + cpu-4-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-4-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-4-1-thermal { + thermal-sensors =3D <&tsens0 9>; + + trips { + cpu-4-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-4-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-5-0-thermal { + thermal-sensors =3D <&tsens0 2>; + + trips { + cpu-5-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-5-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-5-1-thermal { + thermal-sensors =3D <&tsens0 3>; + + trips { + cpu-5-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-5-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-6-0-thermal { + thermal-sensors =3D <&tsens0 10>; + + trips { + cpu-6-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-6-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-6-1-thermal { + thermal-sensors =3D <&tsens0 11>; + + trips { + cpu-6-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-6-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-7-0-thermal { + thermal-sensors =3D <&tsens0 4>; + + trips { + cpu-7-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-7-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-7-1-thermal { + thermal-sensors =3D <&tsens0 5>; + + trips { + cpu-7-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-7-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpullc-0-thermal { + thermal-sensors =3D <&tsens1 0>; + + trips { + cpullc-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpullc-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpullc-1-thermal { + thermal-sensors =3D <&tsens1 1>; + + trips { + cpullc-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpullc-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + ddr-thermal { + thermal-sensors =3D <&tsens6 7>; + + trips { + ddr-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + ddr-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpu-0-0-thermal { + thermal-sensors =3D <&tsens5 0>; + + trips { + gpu-0-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-0-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpu-0-1-thermal { + thermal-sensors =3D <&tsens5 1>; + + trips { + gpu-0-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-0-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpu-0-2-thermal { + thermal-sensors =3D <&tsens5 2>; + + trips { + gpu-0-2-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-0-2-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpu-1-0-thermal { + thermal-sensors =3D <&tsens5 3>; + + trips { + gpu-1-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-1-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpu-1-1-thermal { + thermal-sensors =3D <&tsens5 4>; + + trips { + gpu-1-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-1-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpu-1-2-thermal { + thermal-sensors =3D <&tsens5 5>; + + trips { + gpu-1-2-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-1-2-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpu-2-0-thermal { + thermal-sensors =3D <&tsens5 6>; + + trips { + gpu-2-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-2-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpu-2-1-thermal { + thermal-sensors =3D <&tsens5 7>; + + trips { + gpu-2-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-2-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpu-2-2-thermal { + thermal-sensors =3D <&tsens5 8>; + + trips { + gpu-2-2-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-2-2-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-0-thermal { + thermal-sensors =3D <&tsens5 9>; + + trips { + gpuss-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-1-thermal { + thermal-sensors =3D <&tsens5 10>; + + trips { + gpuss-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + mdmss-0-thermal { + thermal-sensors =3D <&tsens6 0>; + + trips { + mdmss-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + mdmss-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + mdmss-1-thermal { + thermal-sensors =3D <&tsens6 1>; + + trips { + mdmss-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + mdmss-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + mdmss-2-thermal { + thermal-sensors =3D <&tsens6 2>; + + trips { + mdmss-2-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + mdmss-2-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + mdmss-3-thermal { + thermal-sensors =3D <&tsens6 3>; + + trips { + mdmss-3-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + mdmss-3-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nspllv-0-0-thermal { + thermal-sensors =3D <&tsens3 3>; + + trips { + nspllv-0-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nspllv-0-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nspllv-0-1-thermal { + thermal-sensors =3D <&tsens3 4>; + + trips { + nspllv-0-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nspllv-0-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nspllv-1-0-thermal { + thermal-sensors =3D <&tsens3 5>; + + trips { + nspllv-1-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nspllv-1-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nspllv-1-1-thermal { + thermal-sensors =3D <&tsens3 6>; + + trips { + nspllv-1-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nspllv-1-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nspmxu0-0-0-thermal { + thermal-sensors =3D <&tsens4 1>; + + trips { + nspmxu0-0-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nspmxu0-0-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nspmxu0-0-1-thermal { + thermal-sensors =3D <&tsens4 2>; + + trips { + nspmxu0-0-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nspmxu0-0-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nspmxu0-1-0-thermal { + thermal-sensors =3D <&tsens4 3>; + + trips { + nspmxu0-1-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nspmxu0-1-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nspmxu0-1-1-thermal { + thermal-sensors =3D <&tsens4 4>; + + trips { + nspmxu0-1-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nspmxu0-1-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nspmxu1-0-0-thermal { + thermal-sensors =3D <&tsens4 5>; + + trips { + nspmxu1-0-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nspmxu1-0-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nspmxu1-0-1-thermal { + thermal-sensors =3D <&tsens4 6>; + + trips { + nspmxu1-0-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nspmxu1-0-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nspmxu1-1-0-thermal { + thermal-sensors =3D <&tsens4 7>; + + trips { + nspmxu1-1-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nspmxu1-1-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nspmxu1-1-1-thermal { + thermal-sensors =3D <&tsens4 8>; + + trips { + nspmxu1-1-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nspmxu1-1-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nspmxutop-thermal { + thermal-sensors =3D <&tsens4 0>; + + trips { + nspmxutop-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nspmxutop-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nspq6-thermal { + thermal-sensors =3D <&tsens3 0>; + + trips { + nspq6-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nspq6-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nspvxu-0-thermal { + thermal-sensors =3D <&tsens3 1>; + + trips { + nspvxu-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nspvxu-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nspvxu-1-thermal { + thermal-sensors =3D <&tsens3 2>; + + trips { + nspvxu-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nspvxu-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + qmx-0-thermal { + thermal-sensors =3D <&tsens1 2>; + + trips { + qmx-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + qmx-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + qmx-1-thermal { + thermal-sensors =3D <&tsens1 3>; + + trips { + qmx-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + qmx-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + qmx-2-thermal { + thermal-sensors =3D <&tsens1 4>; + + trips { + qmx-2-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + qmx-2-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33e96f47d52sm1412845eec.28.2026.09.22.16.20.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 16:20:11 -0700 (PDT) From: Jingyi Wang Date: Tue, 22 Sep 2026 16:20:01 -0700 Subject: [PATCH 4/5] arm64: dts: qcom: Add PMIC support for Maili platforms Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260922-maili-dts-v1-4-ac2b1b76bfd9@oss.qualcomm.com> References: <20260922-maili-dts-v1-0-ac2b1b76bfd9@oss.qualcomm.com> In-Reply-To: <20260922-maili-dts-v1-0-ac2b1b76bfd9@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abel Vesa , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang , Fenglin Wu X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790119205; l=3595; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=SHZeKzvusHFNFuYOntdlEiI1S4ayexSEHJ2wrStFqY4=; b=ZtQzTsRnoQSIJatSql1R2H6IaZlyykhfig8kv6jV4L09h06ck0aN4WYbiw+xR0P6H9YqJpU8+ 9h9/W4+dKDdDUM1p8Hm0Y9ghi6P/EySUYniHhQh78TqEbPpfdzygPJD X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Proofpoint-GUID: 2pwzwzol6207Im1zzmfQIa3YiYvsc3nW X-Authority-Analysis: v=2.4 cv=HdaB3SE8 c=1 sm=1 tr=0 ts=6ab30d2e cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=4ECTE-F74UkuUx1KzIYA:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-ORIG-GUID: 2pwzwzol6207Im1zzmfQIa3YiYvsc3nW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIyMDMwNiBTYWx0ZWRfX/TwMj6INM+n9 SeXPrLqQaDNd6uIefjIr7rL7DaKmbCRsGNR3qOJERmMKQYo77r2TX272iV7LRrjH8JFvFKJI3hG N2oJtQ0KFbNLF/1rH7SBnFWaCFa5e8+QWhdhMMxoO57gtVNd0gzuZolFenTSQ85h41x3ejCpYSU uUDAE0pl6bKy8KqXnFc8MrCAF7aT3DylZa95l58yw1+j6qGvzDo1TWoLo9K2qUoudsVZwGaVEvu uYaN6WCCZZhYeJogSktKBCMgHUbd3Jwa+2sCmrRYcSd1TpzGZLdR9UMKZGDDm23g5INZfsWTWHM dREVr8SvRRE2Jk1FDYL2Qzi6kpaaeTeQ9h+d3+rIzp6T3pa1+repO72nT3fT1HrG9X83LeJkbgT aKdSKe98JxSMZucJGId4XqF6ObbyQTjFajejTyMzhXD/DcIDz8Ley2ApM43WMlmu85FYZu7z1CU E/1HlE+wZBxM4Zt3Y4g== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIyMDMwNiBTYWx0ZWRfXw57Mbc24rAOb EBN/XTfyu+TGvGhEAwTd48a9Raaez2Ht8QwPBY/C0wurZCGacvBB1uhe9jDs2SFsUfrM3kdBxjv l5mmyII+r6+lGQhmrekg4FygxceiM9c= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-22_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609220306 From: Fenglin Wu Add PMIC files for pmic-arbiter device used on Maili QRD and MTP boards. Only one PMH0104 chip is used on SPMI bus-0 with SID 0x2 which is a new usage, hence add a new pmh0104-maili.dtsi. Also, add a new pmg1110.dtsi to support PMG1110 usage. Signed-off-by: Fenglin Wu Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/pmg1110.dtsi | 57 +++++++++++++++++++++++++= ++++ arch/arm64/boot/dts/qcom/pmh0104-maili.dtsi | 57 +++++++++++++++++++++++++= ++++ 2 files changed, 114 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmg1110.dtsi b/arch/arm64/boot/dts/qc= om/pmg1110.dtsi new file mode 100644 index 000000000000..31b05003b843 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmg1110.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pmg1110-thermal { + polling-delay-passive =3D <100>; + + thermal-sensors =3D <&pmg1110_k_e1_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + }; +}; + +&spmi_bus1 { + pmg1110_k_e1: pmic@9 { + compatible =3D "qcom,pmg1110", "qcom,spmi-pmic"; + reg =3D <0x9 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmg1110_k_e1_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pmg1110_k_e1_gpios: gpio@8800 { + compatible =3D "qcom,pmg1110-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmg1110_k_e1_gpios 0 0 4>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmh0104-maili.dtsi b/arch/arm64/boot/= dts/qcom/pmh0104-maili.dtsi new file mode 100644 index 000000000000..2f3906ccaa73 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmh0104-maili.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pmh0104-c-thermal { + polling-delay-passive =3D <100>; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33e96f47d52sm1412845eec.28.2026.09.22.16.20.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 16:20:12 -0700 (PDT) From: Jingyi Wang Date: Tue, 22 Sep 2026 16:20:02 -0700 Subject: [PATCH 5/5] arm64: dts: qcom: maili: Add base MTP board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260922-maili-dts-v1-5-ac2b1b76bfd9@oss.qualcomm.com> References: <20260922-maili-dts-v1-0-ac2b1b76bfd9@oss.qualcomm.com> In-Reply-To: <20260922-maili-dts-v1-0-ac2b1b76bfd9@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abel Vesa , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790119205; l=28026; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=5gKyuPmbQs/yXR5DzvUIWYPmXhAND+P46ZayWmgn4uM=; b=vKk/z2rLG48RrLiYOw19QGPyuIXC+LZoPDW8rnCjxPqcZYUMulXF09eRbqeno6VdOhQjjVXHO UnqhpcyWIcJAQD6nDZOLVomi044LeW7/90cEy38QT9/4G6aDD7dtLoK X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Proofpoint-GUID: N-MPuFasRvDPPiD2GoYKILMq4ar7-FUq X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIyMDMwNiBTYWx0ZWRfX+ZRtSwwxKvvZ wKpvEtUudlh+rEcFWTgXGx8LJkTl2OwUOq5cKxqrCOJzuK+oxZYFzmN5bMKa0eMluaHMPtfd5eC YZKZX4SR3OR0W5LEIj+hoVIz3oLj6QjphvSG9ptYT4rtG6OcOv4vro1cPlVBHmCJ3B4stdayD7w gwht3hpBwmdfak1b4+X/2IKPlJLxzT+4yqnH916Cl67aVN9eNjwllpt2Ni/VFfJNPqp3tktdkhD nXv8fqgsv/3CBMiTzezG5BSiRASDHHsE2+Ne1NCVRBrJBWawfvOzeGPC2xtnYlUTgrl6Kn8LRHC WnBUUXktdKk/63nacaS/yUv918KOUZLGp7U313USjsIhl3jnv8o/bLBkk0xCISSjSHvVZZMhJkm +RLoYoWruF/1lYS9vloHRJ2Y3+zoR//NhKnkJXmNjuLARqhArLy7R6VHC3qiLhEGa1cnpoU3NHg lV979Fr7aU4dKODIF/A== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIyMDMwNiBTYWx0ZWRfXyTnCZ7Ev8Sl2 zPGzE2TkoFvDU0Z71iTUxfSxc/TFM4oflPOi4L5hlkIcgpk7ydqn6vUdQRuBXgwq1YzTYDqxUDP l1WygfBNIuCxrlHQ5bGfybdR2grgaFU= X-Authority-Analysis: v=2.4 cv=QsDLTlyd c=1 sm=1 tr=0 ts=6ab30d2f cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=azjsmfPmHcDX3kzr_QYA:9 a=QEXdDO2ut3YA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-ORIG-GUID: N-MPuFasRvDPPiD2GoYKILMq4ar7-FUq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-22_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 lowpriorityscore=0 phishscore=0 bulkscore=0 suspectscore=0 impostorscore=0 adultscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609220306 Add initial support for Qualcomm Maili MTP board which enables booting to shell with UART console and features including UFS, remoteprocs, USB, PCIe, SD Card, PMICs and devices for keys and LEDs. Written with help from Fenglin Wu (added RPMhPD nodes and PMICs), Nitin Rawat (Added UFS and SD Card), Krishna Kurapati PSSNV(added USB) and Vivek Pernamitta(added PCIe). Co-developed-by: Yijie Yang Signed-off-by: Yijie Yang Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/maili-mtp.dts | 960 +++++++++++++++++++++++++++++= ++++ 2 files changed, 961 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index d6547fb18edf..753351c42921 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -60,6 +60,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-el2.dtb lemans-evk-ifp-mezzanine-dtbs :=3D lemans-evk.dtb lemans-evk-ifp-mezzanine= .dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-ifp-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D mahua-crd.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D maili-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D milos-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D milos-nothing-asteroids.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-arduino-monza.dtb diff --git a/arch/arm64/boot/dts/qcom/maili-mtp.dts b/arch/arm64/boot/dts/q= com/maili-mtp.dts new file mode 100644 index 000000000000..1fdc91e03271 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/maili-mtp.dts @@ -0,0 +1,960 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "maili.dtsi" +#include "pm8010-kaanapali.dtsi" /* SPMI1: SID-C/D */ +#include "pmd8028-kaanapali.dtsi" /* SPMI1: SID-4 */ +#include "pmg1110.dtsi" /* SPMI1: SID-9 */ +#include "pmh0101.dtsi" /* SPMI0: SID-1 */ +#include "pmh0104-maili.dtsi" /* SPMI0: SID-2 */ +#include "pmh0110-kaanapali.dtsi" /* SPMI0: SID-3/5/6/8 */ +#include "pmih0108-kaanapali.dtsi" /* SPMI1: SID-7 */ +#include "pmk8850.dtsi" /* SPMI0: SID-0 */ +#include "pmr735d-kaanapali.dtsi" /* SPMI1: SID-A */ + +/ { + model =3D "Qualcomm Technologies, Inc. Maili MTP"; + compatible =3D "qcom,maili-mtp", "qcom,maili"; + chassis-type =3D "handset"; + + aliases { + serial0 =3D &uart7; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + clocks { + bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + clocks =3D <&rpmhcc RPMH_CXO_CLK_A>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32764>; + #clock-cells =3D <0>; + }; + + xo_board: xo-board { + compatible =3D "fixed-clock"; + clock-frequency =3D <76800000>; + #clock-cells =3D <0>; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&volume_up_n>; + pinctrl-names =3D "default"; + + key-volume-up { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&pmh0110_i_e0_gpios 13 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + linux,can-disable; + wakeup-source; + }; + }; + + pmic-glink { + compatible =3D "qcom,maili-pmic-glink", + "qcom,kaanapali-pmic-glink", + "qcom,pmic-glink"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + connector@0 { + compatible =3D "usb-c-connector"; + reg =3D <0>; + + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint =3D <&usb_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint =3D <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_dp_out: endpoint { + + }; + }; + }; + }; + }; + + sdcard_vdd_3p0: sdcard-vdd-3p0 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "sdc-vdd123"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-enable-ramp-delay =3D <1500>; + + gpio =3D <&pmh0104_c_e0_gpios 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&sd_card_eldo_en>; + pinctrl-names =3D "default"; + + vin-supply =3D <&vreg_bob1>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pmh0101-rpmh-regulators"; + qcom,pmic-id =3D "B_E0"; + + vreg_bob1: bob1 { + regulator-name =3D "vreg_bob1"; + regulator-min-microvolt =3D <2500000>; + regulator-max-microvolt =3D <4224000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2: bob2 { + regulator-name =3D "vreg_bob2"; + regulator-min-microvolt =3D <2500000>; + regulator-max-microvolt =3D <3616000>; + regulator-initial-mode =3D ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name =3D "vreg_l1b_1p8"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name =3D "vreg_l2b_3p0"; + regulator-min-microvolt =3D <2600000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name =3D "vreg_l4b_1p8"; + regulator-min-microvolt =3D <1504000>; + regulator-max-microvolt =3D <1980000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name =3D "vreg_l5b_3p1"; + regulator-min-microvolt =3D <2300000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name =3D "vreg_l6b_1p8"; + regulator-min-microvolt =3D <1504000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name =3D "vreg_l7b_1p8"; + regulator-min-microvolt =3D <1504000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9b_2p5: ldo9 { + regulator-name =3D "vreg_l9b_2p5"; + regulator-min-microvolt =3D <2400000>; + regulator-max-microvolt =3D <2700000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name =3D "vreg_l10b_1p8"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name =3D "vreg_l11b_1p2"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1950000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name =3D "vreg_l12b_1p8"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name =3D "vreg_l13b_3p0"; + regulator-min-microvolt =3D <2650000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name =3D "vreg_l14b_3p2"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name =3D "vreg_l15b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1980000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l16b_2p9: ldo16 { + regulator-name =3D "vreg_l16b_2p9"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name =3D "vreg_l17b_2p5"; + regulator-min-microvolt =3D <2400000>; + regulator-max-microvolt =3D <2700000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l18b_1p2: ldo18 { + regulator-name =3D "vreg_l18b_1p2"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pmh0104-rpmh-regulators"; + qcom,pmic-id =3D "C_E0"; + + vreg_s3c_1p2: smps3 { + regulator-name =3D "vreg_s3c_1p2"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <2100000>; + regulator-initial-mode =3D ; + }; + + vreg_s4c_1p8: smps4 { + regulator-name =3D "vreg_s4c_1p8"; + regulator-min-microvolt =3D <1808000>; + regulator-max-microvolt =3D <2040000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "D_E0"; + + vreg_s7d_0p7: smps7 { + regulator-name =3D "vreg_s7d_0p7"; + regulator-min-microvolt =3D <713000>; + regulator-max-microvolt =3D <765000>; + regulator-initial-mode =3D ; + }; + + vreg_s8d_1p0: smps8 { + regulator-name =3D "vreg_s8d_1p0"; + regulator-min-microvolt =3D <1010000>; + regulator-max-microvolt =3D <1120000>; + regulator-initial-mode =3D ; + }; + + vreg_s9d_1p0: smps9 { + regulator-name =3D "vreg_s9d_1p0"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <1372000>; + regulator-initial-mode =3D ; + }; + + vreg_l1d_0p9: ldo1 { + regulator-name =3D "vreg_l1d_0p9"; + regulator-min-microvolt =3D <830000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2d_1p8: ldo2 { + regulator-name =3D "vreg_l2d_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3d_0p9: ldo3 { + regulator-name =3D "vreg_l3d_0p9"; + regulator-min-microvolt =3D <830000>; + regulator-max-microvolt =3D <950000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4d_0p9: ldo4 { + regulator-name =3D "vreg_l4d_0p9"; + regulator-min-microvolt =3D <830000>; + regulator-max-microvolt =3D <950000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-3 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "F_E0"; + + vreg_l3f_1p2: ldo3 { + regulator-name =3D "vreg_l3f_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4f_1p0: ldo4 { + regulator-name =3D "vreg_l4f_1p0"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1320000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-4 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "G_E0"; + + vreg_s7g_1p2: smps7 { + regulator-name =3D "vreg_s7g_1p2"; + regulator-min-microvolt =3D <1232000>; + regulator-max-microvolt =3D <1372000>; + regulator-initial-mode =3D ; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name =3D "vreg_l1g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2g_1p2: ldo2 { + regulator-name =3D "vreg_l2g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name =3D "vreg_l3g_1p2"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1320000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4g_1p2: ldo4 { + regulator-name =3D "vreg_l4g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1980000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-5 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "I_E0"; + + vreg_s1i_0p5: smps1 { + regulator-name =3D "vreg_s1i_0p5"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <570000>; + regulator-initial-mode =3D ; + }; + + vreg_s4i_0p9: smps4 { + regulator-name =3D "vreg_s4i_0p9"; + regulator-min-microvolt =3D <870000>; + regulator-max-microvolt =3D <970000>; + regulator-initial-mode =3D ; + }; + + vreg_s10i_1p0: smps10 { + regulator-name =3D "vreg_s10i_1p0"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1300000>; + regulator-initial-mode =3D ; + }; + + vreg_l1i_0p8: ldo1 { + regulator-name =3D "vreg_l1i_0p8"; + regulator-min-microvolt =3D <720000>; + regulator-max-microvolt =3D <950000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3i_0p9: ldo3 { + regulator-name =3D "vreg_l3i_0p9"; + regulator-min-microvolt =3D <825000>; + regulator-max-microvolt =3D <925000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4i_0p9: ldo4 { + regulator-name =3D "vreg_l4i_0p9"; + regulator-min-microvolt =3D <866000>; + regulator-max-microvolt =3D <958000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-6 { + compatible =3D "qcom,pmg1110-rpmh-regulators"; + qcom,pmic-id =3D "J_E1"; + + vreg_s1j_0p8: smps1 { + regulator-name =3D "vreg_s1j_0p8"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <1352000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-7 { + compatible =3D "qcom,pmr735d-rpmh-regulators"; + qcom,pmic-id =3D "K_E1"; + + vreg_l1k_0p7: ldo1 { + regulator-name =3D "vreg_l1k_0p7"; + regulator-min-microvolt =3D <713000>; + regulator-max-microvolt =3D <765000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2k_0p8: ldo2 { + regulator-name =3D "vreg_l2k_0p8"; + regulator-min-microvolt =3D <831000>; + regulator-max-microvolt =3D <892000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3k_1p2: ldo3 { + regulator-name =3D "vreg_l3k_1p2"; + regulator-min-microvolt =3D <1050000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4k_1p0: ldo4 { + regulator-name =3D "vreg_l4k_1p0"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5k_0p9: ldo5 { + regulator-name =3D "vreg_l5k_0p9"; + regulator-min-microvolt =3D <915000>; + regulator-max-microvolt =3D <970000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6k_1p0: ldo6 { + regulator-name =3D "vreg_l6k_1p0"; + regulator-min-microvolt =3D <1050000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7k_0p7: ldo7 { + regulator-name =3D "vreg_l7k_0p7"; + regulator-min-microvolt =3D <713000>; + regulator-max-microvolt =3D <765000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-8 { + compatible =3D "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id =3D "M_E1"; + + vreg_l1m_1p0: ldo1 { + regulator-name =3D "vreg_l1m_1p0"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2m_1p0: ldo2 { + regulator-name =3D "vreg_l2m_1p0"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name =3D "vreg_l3m_2p8"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <2900000>; + regulator-initial-mode =3D ; + }; + + vreg_l5m_2p8: ldo5 { + regulator-name =3D "vreg_l5m_2p8"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <3000000>; + regulator-initial-mode =3D ; + }; + + vreg_l6m_2p8: ldo6 { + regulator-name =3D "vreg_l6m_2p8"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <2900000>; + regulator-initial-mode =3D ; + }; + + vreg_l7m_2p2: ldo7 { + regulator-name =3D "vreg_l7m_2p2"; + regulator-min-microvolt =3D <2100000>; + regulator-max-microvolt =3D <2300000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-9 { + compatible =3D "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id =3D "N_E1"; + + vreg_l1n_0p8: ldo1 { + regulator-name =3D "vreg_l1n_0p8"; + regulator-min-microvolt =3D <720000>; + regulator-max-microvolt =3D <900000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2n_1p2: ldo2 { + regulator-name =3D "vreg_l2n_1p2"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1544000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3n_1p8: ldo3 { + regulator-name =3D "vreg_l3n_1p8"; + regulator-min-microvolt =3D <1792000>; + regulator-max-microvolt =3D <1900000>; + regulator-initial-mode =3D ; + }; + + vreg_l4n_1p8: ldo4 { + regulator-name =3D "vreg_l4n_1p8"; + regulator-min-microvolt =3D <1792000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + }; + + vreg_l5n_3p3: ldo5 { + regulator-name =3D "vreg_l5n_3p3"; + regulator-min-microvolt =3D <3200000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l6n_2p8: ldo6 { + regulator-name =3D "vreg_l6n_2p8"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <2900000>; + regulator-initial-mode =3D ; + }; + + vreg_l7n_3p3: ldo7 { + regulator-name =3D "vreg_l7n_3p3"; + regulator-min-microvolt =3D <3130000>; + regulator-max-microvolt =3D <3470000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&pcie0 { + status =3D "okay"; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l1d_0p9>; + vdda-pll-supply =3D <&vreg_l3g_1p2>; + + status =3D "okay"; +}; + +&pcie_port0 { + wake-gpios =3D <&tlmm 104 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&tlmm 102 GPIO_ACTIVE_LOW>; +}; + +&pcie1 { + status =3D "okay"; +}; + +&pcie1_phy { + vdda-phy-supply =3D <&vreg_l1d_0p9>; + vdda-pll-supply =3D <&vreg_l3g_1p2>; + + status =3D "okay"; +}; + +&pcie_port1 { + wake-gpios =3D <&tlmm 80 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&tlmm 220 GPIO_ACTIVE_LOW>; +}; + +&pmh0101_flash { + status =3D "okay"; + + led-0 { + function =3D LED_FUNCTION_FLASH; + function-enumerator =3D <0>; + color =3D ; + led-sources =3D <1>, <4>; + led-max-microamp =3D <500000>; + flash-max-microamp =3D <2000000>; + flash-max-timeout-us =3D <1280000>; + }; + + led-1 { + function =3D LED_FUNCTION_FLASH; + function-enumerator =3D <1>; + color =3D ; + led-sources =3D <2>, <3>; + led-max-microamp =3D <500000>; + flash-max-microamp =3D <2000000>; + flash-max-timeout-us =3D <1280000>; + }; +}; + +&pmh0104_c_e0_gpios { + sd_card_eldo_en: sd-card-eldo-en-state { + pins =3D "gpio5"; + function =3D "normal"; + qcom,drive-strength =3D ; + input-disable; + output-low; + power-source =3D <0>; + }; +}; + +&pmh0110_i_e0_gpios { + volume_up_n: volume-up-n-state { + pins =3D "gpio13"; + function =3D "normal"; + bias-pull-up; + input-enable; + power-source =3D <1>; + }; +}; + +&pmh0101_pwm { + status =3D "okay"; + + multi-led { + color =3D ; + function =3D LED_FUNCTION_STATUS; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@1 { + reg =3D <1>; + color =3D ; + }; + + led@2 { + reg =3D <2>; + color =3D ; + }; + + led@3 { + reg =3D <3>; + color =3D ; + }; + }; +}; + +&pmih0108_e1_eusb2_repeater { + vdd18-supply =3D <&vreg_l15b_1p8>; + vdd3-supply =3D <&vreg_l5b_3p1>; +}; + +&pon_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/maili/adsp.mbn", + "qcom/maili/adsp_dtb.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/maili/cdsp.mbn", + "qcom/maili/cdsp_dtb.mbn"; + + status =3D "okay"; +}; + +&remoteproc_mpss { + firmware-name =3D "qcom/maili/modem.mbn", + "qcom/maili/modem_dtb.mbn"; + + status =3D "okay"; +}; + +&remoteproc_soccp { + firmware-name =3D "qcom/maili/soccp.mbn", + "qcom/maili/soccp_dtb.mbn"; +}; + +&sdhc_2 { + cd-gpios =3D <&tlmm 55 GPIO_ACTIVE_LOW>; + + vmmc-supply =3D <&sdcard_vdd_3p0>; + vqmmc-supply =3D <&vreg_l16b_2p9>; + + bus-width =3D <4>; + no-sdio; + no-mmc; + + pinctrl-0 =3D <&sdc2_default>; + pinctrl-1 =3D <&sdc2_sleep>; + pinctrl-names =3D "default", "sleep"; + + status =3D "okay"; +}; + +&tlmm { + gpio-reserved-ranges =3D <36 4>, /* NFC eSE SPI */ + <119 2>, /* SoCCP */ + <144 2>, /* CXM UART */ + <211 1>; /* NFC Secure IO */ +}; + +&uart7 { + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 226 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l17b_2p5>; + vcc-max-microamp =3D <1200000>; + + vccq-supply =3D <&vreg_l1g_1p2>; + vccq-max-microamp =3D <1200000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l4i_0p9>; + vdda-pll-supply =3D <&vreg_l3g_1p2>; + + status =3D "okay"; +}; + +&usb { + status =3D "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply =3D <&vreg_l3g_1p2>; + vdda-pll-supply =3D <&vreg_l3i_0p9>; + + status =3D "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint =3D <&pmic_glink_ss_in>; +}; + +&usb_dwc3_hs { + remote-endpoint =3D <&pmic_glink_hs_in>; +}; + +&usb_hsphy { + vdd-supply =3D <&vreg_l3i_0p9>; + vdda12-supply =3D <&vreg_l3g_1p2>; + + phys =3D <&pmih0108_e1_eusb2_repeater>; + + status =3D "okay"; +}; --=20 2.34.1