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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a07dc7c7b0sm296927a91.2.2026.09.22.09.58.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 09:58:28 -0700 (PDT) From: Jeffrey Boody Date: Tue, 22 Sep 2026 09:57:33 -0700 Subject: [PATCH v2] dma-fence: deliver set_deadline callback even if fence is already signaled Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260922-dma-fence-set-deadline-v2-1-2338d6fac9aa@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAHyzsmoC/yXMQQrCQAxG4auUrA3UQTrWq4iLdPJXIzrKpBWh9 O6OuvwW7y3kKAanQ7NQwcvcHrkibBpKF8lnsGk1hTZ0bb+NrHfhETmBHRMrRG+WwRLjPu469DI o1fhZMNr7Nz6e/vZ5uCJN3xut6weRyXDvegAAAA== X-Change-ID: 20260917-dma-fence-set-deadline-a778746e9abd To: Sumit Semwal , =?utf-8?q?Christian_K=C3=B6nig?= , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org, linaro-mm-sig@lists.linaro.org, linux-kernel@vger.kernel.org, freedreno@lists.freedesktop.org, Jeffrey Boody , Jeff Boody X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790096307; l=5741; i=jeffrey.boody@oss.qualcomm.com; s=20260917; h=from:subject:message-id; bh=Q2oNZnZF0RuwKE57dbelijaEFxtwpHSXaVnTUH56ErQ=; b=w7w69/znW7DKQRjZ64vTloJSfKKJbep3F6kIELhdQ43C15+UqWoC8tDpDZr9mYXQqim304Ylp 5JqoOXZ97emD8q/IM9cYC+h1hALzXbDomS9D4tHSa2KBuNFFczDdZ7A X-Developer-Key: i=jeffrey.boody@oss.qualcomm.com; a=ed25519; pk=jfv+xezpcWlcNCnNmb0YYQmKBN9R4nYNB4N6GyqTBkg= X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIyMDI0NyBTYWx0ZWRfX7XWEbDUcD3/G boJEC4gpse4+Idn1UUbLrOIEiLTvwRBDPL+kC++Ar25jzUXljBiO6cycFiDfY9Rd5z8Sekzolsk H5OEuunWPDOPUoDSOj5woBS+oVqHz3E= X-Authority-Analysis: v=2.4 cv=ZYqIpcVA c=1 sm=1 tr=0 ts=6ab2b3b6 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=ymHyVybfssQjcaON3AkA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-ORIG-GUID: pLzt7U39oiW2_0dsBrQp9QQmoyk_WdQ6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIyMDI0NyBTYWx0ZWRfXyhpvT+UxnUgp Py2ZyV8DzJy1oxrUXPYKHPJVKgfFI88RagPkhX1j/l2uqLC6zqZHgZbhjPi68WlgTwSjAEkzH98 cwPdc3wX1jsxBPK8FE8dMWOXPeT1fxbxjkUET/gA0ddqmcxaaGPzS4AARx+KuTyPaz8AKswcFTx ktFApkicmlMsd1NazivuaJ37zvdy2YG0yt2ee1pQZAQLDGw98K/jL8V0e0W9sp6rWOJTXHpQDaN 9xy4vz5lKovaMEXrmIufeRIFkN920kDSGNcSBEr3Nf2srfhAN0CiszmlWlj2LNu1gyaM/nxqn8Q fYLLYLeaHDsZ7SC82J3mnVmwLW1Q5OjipB7rJ79Uq4HUTieDG7QBI4M8ytk+uYEcQO1QixGxE01 xcX8CNagjt2z7FgacGRl5X3xUo2BIREqsEtK6PrMcFPJaev5DCrO7R56ijZ4t9+SdnXz28AesWn yg4eYhVSZ+I3gkOLfkg== X-Proofpoint-GUID: pLzt7U39oiW2_0dsBrQp9QQmoyk_WdQ6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-22_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 malwarescore=0 spamscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1011 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609220247 The set_deadline callback is currently skipped if the fence has already been signaled. This prevents GPU drivers from performing power management adjustments when the deadline hint arrives after fence completion. In triple-buffered rendering, a staged frame may be completed well ahead of the vblank deadline. When a display driver delivers the deadline hint, the fence has already been signaled and the callback is silently dropped. This leaves the GPU driver unable to evaluate the headroom between the fence signal time and the vblank deadline, and therefore unable to reduce GPU frequency when the target headroom is exceeded. Remove the dma_fence_is_signaled() guard from dma_fence_set_deadline() so that the callback is invoked unconditionally when ops->set_deadline is present. Implementations of set_deadline must already tolerate concurrent and repeated calls; handling a post-signal invocation requires no additional locking. The fence signaler can compare the fence signal time against the supplied deadline to determine whether frequency scaling is warranted. Signed-off-by: Jeffrey Boody --- Signed-off-by: Jeff Boody --- drivers/dma-buf/dma-fence.c | 22 ++++++++++++++++++++-- drivers/gpu/drm/msm/msm_fence.c | 3 +++ include/linux/dma-fence.h | 11 ++++++++++- 3 files changed, 33 insertions(+), 3 deletions(-) diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index bd58688b81a7..ebc7c5ca6f69 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -999,8 +999,19 @@ EXPORT_SYMBOL(dma_fence_wait_any_timeout); * Multiple deadlines may be set on a given fence, even in parallel. See = the * documentation for &dma_fence_ops.set_deadline. * + * The deadline hint may also be delivered *after* the fence has already b= een + * signaled. This is intentional and supports the case where a fence sign= aler + * aware of a periodic deadline (e.g. vblank) and the fence's signal time = can + * evaluate the headroom between the two. In triple-buffered rendering, f= or + * example, a staged frame that is completed well ahead of the vblank dead= line + * represents excess headroom; delivering the deadline hint post-signal al= lows + * the fence signaler to consider reducing frequency for subsequent worklo= ads, + * rather than holding an unnecessarily high frequency. Implementations + * of &dma_fence_ops.set_deadline must therefore tolerate invocation on + * already-signaled fences. + * * The deadline hint is just that, a hint. The driver that created the fe= nce - * may react by increasing frequency, making different scheduling choices,= etc. + * may react by changing frequency, making different scheduling choices, e= tc. * Or doing nothing at all. */ =20 @@ -1016,6 +1027,13 @@ EXPORT_SYMBOL(dma_fence_wait_any_timeout); * to aid in power management decisions, such as boosting GPU frequency * if a periodic vblank deadline is approaching but the fence is not * yet signaled.. + * + * This function may also be called after the fence has already been + * signaled. In that case the fence signaler can compare the fence's sign= al + * time against the deadline to determine the available headroom. If the + * fence was signaled significantly ahead of the deadline, the fence + * signaler may choose to reduce frequency for subsequent workloads to + * avoid unnecessarily high power consumption. */ void dma_fence_set_deadline(struct dma_fence *fence, ktime_t deadline) { @@ -1023,7 +1041,7 @@ void dma_fence_set_deadline(struct dma_fence *fence, = ktime_t deadline) =20 rcu_read_lock(); ops =3D rcu_dereference(fence->ops); - if (ops && ops->set_deadline && !dma_fence_is_signaled(fence)) + if (ops && ops->set_deadline) ops->set_deadline(fence, deadline); rcu_read_unlock(); } diff --git a/drivers/gpu/drm/msm/msm_fence.c b/drivers/gpu/drm/msm/msm_fenc= e.c index 3dca8e09c192..3c5de96d4092 100644 --- a/drivers/gpu/drm/msm/msm_fence.c +++ b/drivers/gpu/drm/msm/msm_fence.c @@ -136,6 +136,9 @@ static void msm_fence_set_deadline(struct dma_fence *fe= nce, ktime_t deadline) unsigned long flags; ktime_t now; =20 + if (dma_fence_is_signaled(fence)) + return; + spin_lock_irqsave(&fctx->spinlock, flags); now =3D ktime_get(); =20 diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h index ffa99b930843..839ef2e5dad9 100644 --- a/include/linux/dma-fence.h +++ b/include/linux/dma-fence.h @@ -264,7 +264,16 @@ struct dma_fence_ops { * an upcoming deadline, such as vblank, by which point the waiter * would prefer the fence to be signaled by. This is intended to * give feedback to the fence signaler to aid in power management - * decisions, such as boosting GPU frequency. + * decisions, such as boosting GPU frequency if the deadline has + * not yet been met, or reducing GPU frequency if the fence was + * signaled significantly ahead of the deadline. + * + * This callback may be invoked even after the fence has been + * signaled. In this case, the signaler may use the deadline and + * the fence's signal time to evaluate whether the GPU frequency + * should be adjusted for future workloads. Implementations must + * therefore be prepared to handle calls on already-signaled fences + * without error. * * This is called without &dma_fence.lock held, it can be called * multiple times and from any context. Locking is up to the callee --- base-commit: f0100363d8c374bd8e9ea7c9ba02744f0b802ca4 change-id: 20260917-dma-fence-set-deadline-a778746e9abd Best regards, -- =20 Jeff Boody