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This SoC does not provide macro and dcodec clock so reflect that in the bindings. Shikra integrates LPASS codec version 4.1, which is not backwards compatible with the already described compatibles. Signed-off-by: Mohammad Rafi Shaik Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/sound/qcom,lpass-rx-macro.yaml | 17 +++++++++++++= ++++ .../devicetree/bindings/sound/qcom,lpass-va-macro.yaml | 17 +++++++++++++= ++++ 2 files changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.ya= ml b/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml index 4988e7ed6e34..69d7b7332d36 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - qcom,sc7280-lpass-rx-macro + - qcom,shikra-lpass-rx-macro - qcom,sm6115-lpass-rx-macro - qcom,sm8250-lpass-rx-macro - qcom,sm8450-lpass-rx-macro @@ -138,6 +139,22 @@ allOf: - const: dcodec - const: fsgen =20 + - if: + properties: + compatible: + enum: + - qcom,shikra-lpass-rx-macro + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: mclk + - const: npl + - const: fsgen + unevaluatedProperties: false =20 examples: diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.ya= ml b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml index aea31fbdad37..683ebf702ba8 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - qcom,sc7280-lpass-va-macro + - qcom,shikra-lpass-va-macro - qcom,sm6115-lpass-va-macro - qcom,sm8250-lpass-va-macro - qcom,sm8450-lpass-va-macro @@ -168,6 +169,22 @@ allOf: - const: macro - const: dcodec =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,shikra-lpass-va-macro + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: mclk + - const: npl + unevaluatedProperties: false =20 examples: --=20 2.34.1 From nobody Thu Sep 24 16:09:17 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B47CD4BFE8B for ; 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Add the missing case. Reviewed-by: Srinivas Kandagatla Signed-off-by: Mohammad Rafi Shaik Reviewed-by: Ajay Kumar Nandam --- sound/soc/codecs/lpass-macro-common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sound/soc/codecs/lpass-macro-common.h b/sound/soc/codecs/lpass= -macro-common.h index 10ad682019fa..573b2145e1c4 100644 --- a/sound/soc/codecs/lpass-macro-common.h +++ b/sound/soc/codecs/lpass-macro-common.h @@ -68,6 +68,8 @@ static inline const char *lpass_macro_get_codec_version_s= tring(int version) return "v2.7"; case LPASS_CODEC_VERSION_2_8: return "v2.8"; + case LPASS_CODEC_VERSION_2_9: + return "v2.9"; default: break; } --=20 2.34.1 From nobody Thu Sep 24 16:09:17 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18C234CA788 for ; Tue, 22 Sep 2026 09:43:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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The RX macro register layout of LPASS codec v4.1 matches the v2.5+ layout, so reuse the existing v2.5 register access helpers, controls and widgets for it. v4.1 additionally requires the FS counter to be bypassed before it is enabled during MCLK enable. This is a property of the codec version and not of the board, so key it off the version detected by the VA macro rather than off match data. Signed-off-by: Mohammad Rafi Shaik Reviewed-by: Ajay Kumar Nandam --- sound/soc/codecs/lpass-macro-common.h | 3 +++ sound/soc/codecs/lpass-rx-macro.c | 14 ++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/sound/soc/codecs/lpass-macro-common.h b/sound/soc/codecs/lpass= -macro-common.h index 573b2145e1c4..b52665b11e35 100644 --- a/sound/soc/codecs/lpass-macro-common.h +++ b/sound/soc/codecs/lpass-macro-common.h @@ -30,6 +30,7 @@ enum lpass_codec_version { LPASS_CODEC_VERSION_2_7, LPASS_CODEC_VERSION_2_8, LPASS_CODEC_VERSION_2_9, + LPASS_CODEC_VERSION_4_1, }; =20 struct lpass_macro { @@ -70,6 +71,8 @@ static inline const char *lpass_macro_get_codec_version_s= tring(int version) return "v2.8"; case LPASS_CODEC_VERSION_2_9: return "v2.9"; + case LPASS_CODEC_VERSION_4_1: + return "v4.1"; default: break; } diff --git a/sound/soc/codecs/lpass-rx-macro.c b/sound/soc/codecs/lpass-rx-= macro.c index c41eb8de6160..93ceee878b78 100644 --- a/sound/soc/codecs/lpass-rx-macro.c +++ b/sound/soc/codecs/lpass-rx-macro.c @@ -60,6 +60,7 @@ #define CDC_RX_FS_MCLK_CNT_ENABLE BIT(0) #define CDC_RX_FS_MCLK_CNT_CLR_MASK BIT(1) #define CDC_RX_FS_MCLK_CNT_CLR BIT(1) +#define CDC_RX_FS_CNT_BYPASS BIT(7) #define CDC_RX_CLK_RST_CTRL_SWR_CONTROL (0x0108) #define CDC_RX_SWR_CLK_EN_MASK BIT(0) #define CDC_RX_SWR_RESET_MASK BIT(1) @@ -652,6 +653,7 @@ struct rx_macro { bool is_ear_mode_on; bool hph_pwr_mode; bool hph_hd2_mode; + bool fs_cnt_bypass; struct snd_soc_component *component; unsigned long active_ch_mask[RX_MACRO_MAX_DAIS]; unsigned long active_ch_cnt[RX_MACRO_MAX_DAIS]; @@ -1613,6 +1615,7 @@ static bool rx_is_rw_register(struct device *dev, uns= igned int reg) case LPASS_CODEC_VERSION_2_6: case LPASS_CODEC_VERSION_2_7: case LPASS_CODEC_VERSION_2_8: + case LPASS_CODEC_VERSION_4_1: return rx_2_5_is_rw_register(dev, reg); default: break; @@ -2045,6 +2048,11 @@ static int rx_macro_mclk_enable(struct rx_macro *rx,= bool mclk_enable) CDC_RX_CLK_MCLK2_ENABLE); regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, CDC_RX_FS_MCLK_CNT_CLR_MASK, 0x00); + + if (rx->fs_cnt_bypass) + regmap_set_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, + CDC_RX_FS_CNT_BYPASS); + regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, CDC_RX_FS_MCLK_CNT_EN_MASK, CDC_RX_FS_MCLK_CNT_ENABLE); @@ -3652,6 +3660,7 @@ static int rx_macro_component_probe(struct snd_soc_co= mponent *component) case LPASS_CODEC_VERSION_2_6: case LPASS_CODEC_VERSION_2_7: case LPASS_CODEC_VERSION_2_8: + case LPASS_CODEC_VERSION_4_1: controls =3D rx_macro_2_5_snd_controls; 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LPASS codec v4.1 extends the VA macro with four adaptive filter (ADPT) blocks at 0x0800..0x09a4 and requires the FS counter to be bypassed before it is enabled. Add the new registers as a separate reg_default array, used by a v4.1 specific regmap config. The register layout has to be chosen before the regmap exists, i.e. before CDC_VA_TOP_CSR_CORE_ID_* can be read, so it comes from match data; probe then cross checks it against the version reported by the hardware. Signed-off-by: Mohammad Rafi Shaik --- sound/soc/codecs/lpass-va-macro.c | 281 ++++++++++++++++++++++++++++++++++= +++- 1 file changed, 274 insertions(+), 7 deletions(-) diff --git a/sound/soc/codecs/lpass-va-macro.c b/sound/soc/codecs/lpass-va-= macro.c index 03d6434a4a12..02dc3346924f 100644 --- a/sound/soc/codecs/lpass-va-macro.c +++ b/sound/soc/codecs/lpass-va-macro.c @@ -26,6 +26,7 @@ #define CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004) #define CDC_VA_FS_CONTROL_EN BIT(0) #define CDC_VA_FS_COUNTER_CLR BIT(1) +#define CDC_VA_FS_CNT_BYPASS BIT(7) #define CDC_VA_CLK_RST_CTRL_SWR_CONTROL (0x0008) #define CDC_VA_SWR_RESET_MASK BIT(1) #define CDC_VA_SWR_RESET_ENABLE BIT(1) @@ -156,7 +157,54 @@ #define CDC_VA_TX3_TX_PATH_SEC5 (0x05A4) #define CDC_VA_TX3_TX_PATH_SEC6 (0x05A8) =20 +/* LPASS codec v4.1 adaptive filter (ADPT) blocks */ +#define CDC_VA_CDC_ADPT0_ADPT_CTRL 0x0800 +#define CDC_VA_ADPT_CTRL_EN_MASK GENMASK(7, 0) +#define CDC_VA_CDC_ADPT0_ADPT_GAIN_0 0x0804 +#define CDC_VA_CDC_ADPT0_ADPT_GAIN_1 0x0808 +#define CDC_VA_CDC_ADPT0_DH_FSM_CTRL 0x080c +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_0 0x0810 +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_1 0x0814 +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_2 0x0818 +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_3 0x081c +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_4 0x0820 +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_5 0x0824 + +#define CDC_VA_CDC_ADPT1_ADPT_CTRL 0x0880 +#define CDC_VA_CDC_ADPT1_ADPT_GAIN_0 0x0884 +#define CDC_VA_CDC_ADPT1_ADPT_GAIN_1 0x0888 +#define CDC_VA_CDC_ADPT1_DH_FSM_CTRL 0x088c +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_0 0x0890 +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_1 0x0894 +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_2 0x0898 +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_3 0x089c +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_4 0x08a0 +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_5 0x08a4 + +#define CDC_VA_CDC_ADPT2_ADPT_CTRL 0x0900 +#define CDC_VA_CDC_ADPT2_ADPT_GAIN_0 0x0904 +#define CDC_VA_CDC_ADPT2_ADPT_GAIN_1 0x0908 +#define CDC_VA_CDC_ADPT2_DH_FSM_CTRL 0x090c +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_0 0x0910 +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_1 0x0914 +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_2 0x0918 +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_3 0x091c +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_4 0x0920 +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_5 0x0924 + +#define CDC_VA_CDC_ADPT3_ADPT_CTRL 0x0980 +#define CDC_VA_CDC_ADPT3_ADPT_GAIN_0 0x0984 +#define CDC_VA_CDC_ADPT3_ADPT_GAIN_1 0x0988 +#define CDC_VA_CDC_ADPT3_DH_FSM_CTRL 0x098c +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_0 0x0990 +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_1 0x0994 +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_2 0x0998 +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_3 0x099c +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_4 0x09a0 +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_5 0x09a4 + #define VA_MAX_OFFSET (0x07A8) +#define VA_4_1_MAX_OFFSET 0x09a4 =20 #define VA_MACRO_NUM_DECIMATORS 4 #define VA_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ @@ -210,7 +258,8 @@ struct va_macro { u16 dmic_clk_div; bool has_swr_master; bool has_npl_clk; - + bool fs_cnt_bypass; + bool has_adpt; int dec_mode[VA_MACRO_NUM_DECIMATORS]; struct regmap *regmap; struct clk *mclk; @@ -237,6 +286,7 @@ struct va_macro_data { bool has_swr_master; bool has_npl_clk; int version; + const struct regmap_config *regmap_config; }; =20 static const struct va_macro_data sm8250_va_data =3D { @@ -357,6 +407,127 @@ static const struct reg_default va_defaults[] =3D { { CDC_VA_TX3_TX_PATH_SEC6, 0x00}, }; =20 +static const struct reg_default va_4_1_defaults[] =3D { + /* VA macro */ + { CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, + { CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, + { CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00}, + { CDC_VA_TOP_CSR_TOP_CFG0, 0x00}, + { CDC_VA_TOP_CSR_DMIC0_CTL, 0x00}, + { CDC_VA_TOP_CSR_DMIC1_CTL, 0x00}, + { CDC_VA_TOP_CSR_DMIC2_CTL, 0x00}, + { CDC_VA_TOP_CSR_DMIC3_CTL, 0x00}, + { CDC_VA_TOP_CSR_DMIC_CFG, 0x80}, + { CDC_VA_TOP_CSR_DEBUG_BUS, 0x00}, + { CDC_VA_TOP_CSR_DEBUG_EN, 0x00}, + { CDC_VA_TOP_CSR_TX_I2S_CTL, 0x0C}, + { CDC_VA_TOP_CSR_I2S_CLK, 0x00}, + { CDC_VA_TOP_CSR_I2S_RESET, 0x00}, + { CDC_VA_TOP_CSR_CORE_ID_0, 0x00}, + { CDC_VA_TOP_CSR_CORE_ID_1, 0x00}, + { CDC_VA_TOP_CSR_CORE_ID_2, 0x00}, + { CDC_VA_TOP_CSR_CORE_ID_3, 0x00}, + { CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE}, + { CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE}, + { CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE}, + { CDC_VA_TOP_CSR_SWR_CTRL, 0x06}, + /* VA core */ + { CDC_VA_INP_MUX_ADC_MUX0_CFG0, 0x00}, + { CDC_VA_INP_MUX_ADC_MUX0_CFG1, 0x00}, + { CDC_VA_INP_MUX_ADC_MUX1_CFG0, 0x00}, + { CDC_VA_INP_MUX_ADC_MUX1_CFG1, 0x00}, + { CDC_VA_INP_MUX_ADC_MUX2_CFG0, 0x00}, + { CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0x00}, + { CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0x00}, + { CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0x00}, + { CDC_VA_TX0_TX_PATH_CTL, 0x04}, + { CDC_VA_TX0_TX_PATH_CFG0, 0x10}, + { CDC_VA_TX0_TX_PATH_CFG1, 0x0B}, + { CDC_VA_TX0_TX_VOL_CTL, 0x00}, + { CDC_VA_TX0_TX_PATH_SEC0, 0x00}, + { CDC_VA_TX0_TX_PATH_SEC1, 0x00}, + { CDC_VA_TX0_TX_PATH_SEC2, 0x01}, + { CDC_VA_TX0_TX_PATH_SEC3, 0x3C}, + { CDC_VA_TX0_TX_PATH_SEC4, 0x20}, + { CDC_VA_TX0_TX_PATH_SEC5, 0x00}, + { CDC_VA_TX0_TX_PATH_SEC6, 0x00}, + { CDC_VA_TX0_TX_PATH_SEC7, 0x25}, + { CDC_VA_TX1_TX_PATH_CTL, 0x04}, + { CDC_VA_TX1_TX_PATH_CFG0, 0x10}, + { CDC_VA_TX1_TX_PATH_CFG1, 0x0B}, + { CDC_VA_TX1_TX_VOL_CTL, 0x00}, + { CDC_VA_TX1_TX_PATH_SEC0, 0x00}, + { CDC_VA_TX1_TX_PATH_SEC1, 0x00}, + { CDC_VA_TX1_TX_PATH_SEC2, 0x01}, + { CDC_VA_TX1_TX_PATH_SEC3, 0x3C}, + { CDC_VA_TX1_TX_PATH_SEC4, 0x20}, + { CDC_VA_TX1_TX_PATH_SEC5, 0x00}, + { CDC_VA_TX1_TX_PATH_SEC6, 0x00}, + { CDC_VA_TX2_TX_PATH_CTL, 0x04}, + { CDC_VA_TX2_TX_PATH_CFG0, 0x10}, + { CDC_VA_TX2_TX_PATH_CFG1, 0x0B}, + { CDC_VA_TX2_TX_VOL_CTL, 0x00}, + { CDC_VA_TX2_TX_PATH_SEC0, 0x00}, + { CDC_VA_TX2_TX_PATH_SEC1, 0x00}, + { CDC_VA_TX2_TX_PATH_SEC2, 0x01}, + { CDC_VA_TX2_TX_PATH_SEC3, 0x3C}, + { CDC_VA_TX2_TX_PATH_SEC4, 0x20}, + { CDC_VA_TX2_TX_PATH_SEC5, 0x00}, + { CDC_VA_TX2_TX_PATH_SEC6, 0x00}, + { CDC_VA_TX3_TX_PATH_CTL, 0x04}, + { CDC_VA_TX3_TX_PATH_CFG0, 0x10}, + { CDC_VA_TX3_TX_PATH_CFG1, 0x0B}, + { CDC_VA_TX3_TX_VOL_CTL, 0x00}, + { CDC_VA_TX3_TX_PATH_SEC0, 0x00}, + { CDC_VA_TX3_TX_PATH_SEC1, 0x00}, + { CDC_VA_TX3_TX_PATH_SEC2, 0x01}, + { CDC_VA_TX3_TX_PATH_SEC3, 0x3C}, + { CDC_VA_TX3_TX_PATH_SEC4, 0x20}, + { CDC_VA_TX3_TX_PATH_SEC5, 0x00}, + { CDC_VA_TX3_TX_PATH_SEC6, 0x00}, + /* ADPT blocks */ + { CDC_VA_CDC_ADPT0_ADPT_CTRL, 0x51}, + { CDC_VA_CDC_ADPT0_ADPT_GAIN_0, 0x11}, + { CDC_VA_CDC_ADPT0_ADPT_GAIN_1, 0x01}, + { CDC_VA_CDC_ADPT0_DH_FSM_CTRL, 0x02}, + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_0, 0x77}, + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_1, 0x64}, + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_2, 0x00}, + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_3, 0x41}, + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_4, 0x04}, + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_5, 0x01}, + { CDC_VA_CDC_ADPT1_ADPT_CTRL, 0x51}, + { CDC_VA_CDC_ADPT1_ADPT_GAIN_0, 0x11}, + { CDC_VA_CDC_ADPT1_ADPT_GAIN_1, 0x01}, + { CDC_VA_CDC_ADPT1_DH_FSM_CTRL, 0x02}, + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_0, 0x77}, + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_1, 0x64}, + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_2, 0x00}, + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_3, 0x41}, + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_4, 0x04}, + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_5, 0x01}, + { CDC_VA_CDC_ADPT2_ADPT_CTRL, 0x51}, + { CDC_VA_CDC_ADPT2_ADPT_GAIN_0, 0x11}, + { CDC_VA_CDC_ADPT2_ADPT_GAIN_1, 0x01}, + { CDC_VA_CDC_ADPT2_DH_FSM_CTRL, 0x02}, + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_0, 0x77}, + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_1, 0x64}, + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_2, 0x00}, + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_3, 0x41}, + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_4, 0x04}, + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_5, 0x01}, + { CDC_VA_CDC_ADPT3_ADPT_CTRL, 0x51}, + { CDC_VA_CDC_ADPT3_ADPT_GAIN_0, 0x11}, + { CDC_VA_CDC_ADPT3_ADPT_GAIN_1, 0x01}, + { CDC_VA_CDC_ADPT3_DH_FSM_CTRL, 0x02}, + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_0, 0x77}, + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_1, 0x64}, + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_2, 0x00}, + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_3, 0x41}, + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_4, 0x04}, + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_5, 0x01}, +}; + static bool va_is_rw_register(struct device *dev, unsigned int reg) { switch (reg) { @@ -430,6 +601,46 @@ static bool va_is_rw_register(struct device *dev, unsi= gned int reg) case CDC_VA_TX3_TX_PATH_SEC4: case CDC_VA_TX3_TX_PATH_SEC5: case CDC_VA_TX3_TX_PATH_SEC6: + case CDC_VA_CDC_ADPT0_ADPT_CTRL: + case CDC_VA_CDC_ADPT0_ADPT_GAIN_0: + case CDC_VA_CDC_ADPT0_ADPT_GAIN_1: + case CDC_VA_CDC_ADPT0_DH_FSM_CTRL: + case CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_0: + case CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_1: + case CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_2: + case CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_3: + case CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_4: + case CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_5: + case CDC_VA_CDC_ADPT1_ADPT_CTRL: + case CDC_VA_CDC_ADPT1_ADPT_GAIN_0: + case CDC_VA_CDC_ADPT1_ADPT_GAIN_1: + case CDC_VA_CDC_ADPT1_DH_FSM_CTRL: + case CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_0: + case CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_1: + case CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_2: + case CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_3: + case CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_4: + case CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_5: + case CDC_VA_CDC_ADPT2_ADPT_CTRL: + case CDC_VA_CDC_ADPT2_ADPT_GAIN_0: + case CDC_VA_CDC_ADPT2_ADPT_GAIN_1: + case CDC_VA_CDC_ADPT2_DH_FSM_CTRL: + case CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_0: + case CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_1: + case CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_2: + case CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_3: + case CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_4: + case CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_5: + case CDC_VA_CDC_ADPT3_ADPT_CTRL: + case CDC_VA_CDC_ADPT3_ADPT_GAIN_0: + case CDC_VA_CDC_ADPT3_ADPT_GAIN_1: + case CDC_VA_CDC_ADPT3_DH_FSM_CTRL: + case CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_0: + case CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_1: + case CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_2: + case CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_3: + case CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_4: + case CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_5: return true; } =20 @@ -463,6 +674,27 @@ static const struct regmap_config va_regmap_config =3D= { .writeable_reg =3D va_is_rw_register, }; =20 +static const struct regmap_config va_4_1_regmap_config =3D { + .name =3D "va_macro", + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .cache_type =3D REGCACHE_MAPLE, + .reg_defaults =3D va_4_1_defaults, + .num_reg_defaults =3D ARRAY_SIZE(va_4_1_defaults), + .max_register =3D VA_4_1_MAX_OFFSET, + .volatile_reg =3D va_is_volatile_register, + .readable_reg =3D va_is_readable_register, + .writeable_reg =3D va_is_rw_register, +}; + +static const struct va_macro_data shikra_va_data =3D { + .has_swr_master =3D true, + .has_npl_clk =3D true, + .version =3D LPASS_CODEC_VERSION_4_1, + .regmap_config =3D &va_4_1_regmap_config, +}; + static int va_clk_rsc_fs_gen_request(struct va_macro *va, bool enable) { struct regmap *regmap =3D va->regmap; @@ -471,10 +703,14 @@ static int va_clk_rsc_fs_gen_request(struct va_macro = *va, bool enable) regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, CDC_VA_MCLK_CONTROL_EN, CDC_VA_MCLK_CONTROL_EN); - /* clear the fs counter */ + regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR, CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR); + + if (va->fs_cnt_bypass) + regmap_set_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, + CDC_VA_FS_CNT_BYPASS); regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR, CDC_VA_FS_CONTROL_EN); @@ -503,7 +739,7 @@ static int va_macro_mclk_enable(struct va_macro *va, bo= ol mclk_enable) if (mclk_enable) { va_clk_rsc_fs_gen_request(va, true); regcache_mark_dirty(regmap); - regcache_sync_region(regmap, 0x0, VA_MAX_OFFSET); + regcache_sync_region(regmap, 0x0, regmap_get_max_register(regmap)); } else { va_clk_rsc_fs_gen_request(va, false); } @@ -749,6 +985,7 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widg= et *w, unsigned int decimator; u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg; u16 tx_gain_ctl_reg; + u16 adpt_ctrl_reg; u8 hpf_cut_off_freq; =20 struct va_macro *va =3D snd_soc_component_get_drvdata(comp); @@ -763,6 +1000,7 @@ static int va_macro_enable_dec(struct snd_soc_dapm_wid= get *w, VA_MACRO_TX_PATH_OFFSET * decimator; tx_gain_ctl_reg =3D CDC_VA_TX0_TX_VOL_CTL + VA_MACRO_TX_PATH_OFFSET * decimator; + adpt_ctrl_reg =3D CDC_VA_CDC_ADPT0_ADPT_CTRL + decimator * VA_MACRO_TX_PA= TH_OFFSET; =20 switch (event) { case SND_SOC_DAPM_PRE_PMU: @@ -772,6 +1010,10 @@ static int va_macro_enable_dec(struct snd_soc_dapm_wi= dget *w, /* Enable TX PGA Mute */ break; case SND_SOC_DAPM_POST_PMU: + if (va->has_adpt) + snd_soc_component_update_bits(comp, adpt_ctrl_reg, + CDC_VA_ADPT_CTRL_EN_MASK, 0x00); + /* Enable TX CLK */ snd_soc_component_update_bits(comp, tx_vol_ctl_reg, CDC_VA_TX_PATH_CLK_EN_MASK, @@ -1526,6 +1768,14 @@ static int va_macro_set_lpass_codec_version(struct v= a_macro *va) default: break; } + } else if (maj =3D=3D 4) { + switch (min) { + case 1: + version =3D LPASS_CODEC_VERSION_4_1; + break; + default: + break; + } } =20 if (version =3D=3D LPASS_CODEC_VERSION_UNKNOWN) { @@ -1556,6 +1806,7 @@ static int va_macro_probe(struct platform_device *pde= v) return -ENOMEM; =20 va->dev =3D dev; + data =3D of_device_get_match_data(dev); =20 va->macro =3D devm_clk_get_optional(dev, "macro"); if (IS_ERR(va->macro)) @@ -1592,15 +1843,15 @@ static int va_macro_probe(struct platform_device *p= dev) goto err; } =20 - va->regmap =3D devm_regmap_init_mmio(dev, base, &va_regmap_config); + dev_set_drvdata(dev, va); + + va->regmap =3D devm_regmap_init_mmio(dev, base, + data->regmap_config ?: &va_regmap_config); if (IS_ERR(va->regmap)) { ret =3D -EINVAL; goto err; } =20 - dev_set_drvdata(dev, va); - - data =3D of_device_get_match_data(dev); va->has_swr_master =3D data->has_swr_master; va->has_npl_clk =3D data->has_npl_clk; =20 @@ -1654,6 +1905,21 @@ static int va_macro_probe(struct platform_device *pd= ev) goto err_rpm_put; } =20 + va->fs_cnt_bypass =3D (lpass_macro_get_codec_version() =3D=3D LPASS_CODEC= _VERSION_4_1); + va->has_adpt =3D (lpass_macro_get_codec_version() =3D=3D LPASS_CODEC_VERS= ION_4_1); + + /* + * The register layout comes from match data, as it has to be picked + * before CDC_VA_TOP_CSR_CORE_ID_* can be read. Make sure it describes + * the codec the hardware reports, so that the ADPT blocks are never + * programmed outside the register window. + */ + if (va->has_adpt && regmap_get_max_register(va->regmap) < VA_4_1_MAX_OFFS= ET) { + dev_err(dev, "v4.1 codec described by a pre-v4.1 compatible\n"); + ret =3D -EINVAL; + goto err_rpm_put; + } + if (va->has_swr_master) { /* Set default CLK div to 1 */ regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL0, @@ -1775,6 +2041,7 @@ static const struct of_device_id va_macro_dt_match[] = =3D { { .compatible =3D "qcom,sm8450-lpass-va-macro", .data =3D &sm8450_va_data= }, { .compatible =3D "qcom,sm8550-lpass-va-macro", .data =3D &sm8550_va_data= }, { .compatible =3D "qcom,sc8280xp-lpass-va-macro", .data =3D &sm8450_va_da= ta }, + { .compatible =3D "qcom,shikra-lpass-va-macro", .data =3D &shikra_va_data= }, {} }; MODULE_DEVICE_TABLE(of, va_macro_dt_match); --=20 2.34.1 From nobody Thu Sep 24 16:09:17 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8E904C1503 for ; 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a=ed25519-sha256; t=1790070192; l=9620; i=mohammad.rafi.shaik@oss.qualcomm.com; s=20260424; h=from:subject:message-id; bh=EypEwZqDJrmJfCSNQLvIDdsPJdsMZpNBzjQHWYZ6PHE=; b=Y3CGqAaUq0e6KuzxUlEBDMkwLdRr9CQDy+n07yBJ4FqN3rE0fR9xR3i5IHL0oAaLWcijvZ4IM hAV8OzqR+7uA5fmI1KAVw2HIC0IL6XehMUv7vpJ7J2yV4C/rI4RXaml X-Developer-Key: i=mohammad.rafi.shaik@oss.qualcomm.com; a=ed25519; pk=KZedmYgMGYOzuTpLGv56tdrL+pTLDP8pdmfQ91xemiA= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIyMDEzOSBTYWx0ZWRfX0nP5kPnjyxzB A6dX19iIWZhDcpdEPwPFjEtEBbu031eqeQ+bIqIfmyld1FXSQd9peyt1iuCNlLVfD2jC2g9giwv LyNqDLlb6+NCoAfXINwekY2fgN5xszjADlx81XKYMWY78rWD2j9fQuTEzvJkk8mEjpJERYsP89p WAGEX8S8oYCiIPngzryYI+mcB6S+YD67pAwszW4ow0bksXTiCKql51AvXb8gekgAZ0m8deoBkRO ECMTMem5cFznbwuCeu9L3LN/K5L3zpS9qCr14xtxmXGHaYoq0UaaCSRym5hE8WizNSVQUo4ED8g FTsHBcuCdSrZZpi0ECz1QDjUg44KeoVoyy1N1bUXawxs+YRv1fFfK14z8MbC4il5xQ6/gWBi+Ij 3VqDU/8U7M4h1ECM5+BBjToaf8Ya0SYZuWLpmBTBIF8LFf9DozxEnhuqgfUi0NOmfpBiqM0Zhof RIC8NhHMv3B+bttebPg== X-Authority-Analysis: v=2.4 cv=FdaiV5+6 c=1 sm=1 tr=0 ts=6ab24dcf cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=zFky0nD_-0bCEmkCyRUA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-ORIG-GUID: 9swrkE6kIELcpUXlQNcI2xaeBdH8P0Qe X-Proofpoint-GUID: 9swrkE6kIELcpUXlQNcI2xaeBdH8P0Qe X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIyMDEzOSBTYWx0ZWRfX8zWF4rQG+tMR K2KTQ2xtEdT3dpnjT5/xB4ID55RsNUF4Qkie/m7frAuY+4rGlvoiaLvZO0HRCW2foHM7aR29GKB 796PkMyycT1LZ7b+HksOUznsef0i1QI= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-21_07,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 spamscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609220139 The VA decimators can currently capture audio only from DMIC inputs. Add support for routing audio from SoundWire microphone (SMIC) inputs as well. Update the decimator source selection logic to switch between DMIC and SMIC sources based on the active input path. The ADC_DMIC_SEL bit of CDC_VA_TXn_TX_PATH_CFG0 is shared by the DMIC and the SoundWire mic mux, so a mixer write to the mux that is not part of the active path can leave it stale. Program it from the resolved mux state when the decimator is enabled, so capture does not depend on the order in which userspace restores the two controls. Add a helper to detect whether a decimator is using a SoundWire microphone input. Use this information to skip DMIC-specific HPF programming sequences when the decimator is configured for an SMIC source. This enables VA decimators to capture audio from either DMIC or SoundWire microphone inputs. Signed-off-by: Mohammad Rafi Shaik --- sound/soc/codecs/lpass-va-macro.c | 144 ++++++++++++++++++++++++++++++++++= +--- 1 file changed, 135 insertions(+), 9 deletions(-) diff --git a/sound/soc/codecs/lpass-va-macro.c b/sound/soc/codecs/lpass-va-= macro.c index 02dc3346924f..79abbdd158b7 100644 --- a/sound/soc/codecs/lpass-va-macro.c +++ b/sound/soc/codecs/lpass-va-macro.c @@ -794,10 +794,22 @@ static int va_macro_put_dec_enum(struct snd_kcontrol = *kcontrol, return -EINVAL; } =20 - if (val !=3D 0) - snd_soc_component_update_bits(component, mic_sel_reg, - CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK, - CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC); + if (val !=3D 0) { + /* + * SMIC enums use shift 0 (lower nibble of CFG0), + * DMIC enums use shift 4 (upper nibble of CFG0). + * Use e->shift_l to distinguish them without relying + * on widget name comparisons. + */ + if (e->shift_l =3D=3D 0) + snd_soc_component_update_bits(component, mic_sel_reg, + CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK, + CDC_VA_TX_PATH_ADC_DMIC_SEL_ADC); + else + snd_soc_component_update_bits(component, mic_sel_reg, + CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK, + CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC); + } =20 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); } @@ -978,6 +990,16 @@ static int va_macro_enable_dmic(struct snd_soc_dapm_wi= dget *w, return 0; } =20 +static bool is_amic_enabled(struct snd_soc_component *comp, int decimator) +{ + u16 adc_mux_reg; + + adc_mux_reg =3D CDC_VA_INP_MUX_ADC_MUX0_CFG1 + + VA_MACRO_ADC_MUX_CFG_OFFSET * decimator; + + return snd_soc_component_read(comp, adc_mux_reg) & BIT(0); +} + static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { @@ -987,7 +1009,6 @@ static int va_macro_enable_dec(struct snd_soc_dapm_wid= get *w, u16 tx_gain_ctl_reg; u16 adpt_ctrl_reg; u8 hpf_cut_off_freq; - struct va_macro *va =3D snd_soc_component_get_drvdata(comp); =20 decimator =3D w->shift; @@ -1004,6 +1025,17 @@ static int va_macro_enable_dec(struct snd_soc_dapm_w= idget *w, =20 switch (event) { case SND_SOC_DAPM_PRE_PMU: + /* + * ADC_DMIC_SEL is shared by the DMIC and the SoundWire mic + * mux, so a mixer write to the mux that is not part of the + * active path can leave it stale. Program it from the mux + * state DAPM resolved for this decimator. + */ + snd_soc_component_update_bits(comp, dec_cfg_reg, + CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK, + is_amic_enabled(comp, decimator) ? + CDC_VA_TX_PATH_ADC_DMIC_SEL_ADC : + CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC); snd_soc_component_update_bits(comp, dec_cfg_reg, CDC_VA_ADC_MODE_MASK, va->dec_mode[decimator] << CDC_VA_ADC_MODE_SHIFT); @@ -1018,9 +1050,10 @@ static int va_macro_enable_dec(struct snd_soc_dapm_w= idget *w, snd_soc_component_update_bits(comp, tx_vol_ctl_reg, CDC_VA_TX_PATH_CLK_EN_MASK, CDC_VA_TX_PATH_CLK_EN); - snd_soc_component_update_bits(comp, hpf_gate_reg, - CDC_VA_TX_HPF_ZERO_GATE_MASK, - CDC_VA_TX_HPF_ZERO_GATE); + if (!is_amic_enabled(comp, decimator)) + snd_soc_component_update_bits(comp, hpf_gate_reg, + CDC_VA_TX_HPF_ZERO_GATE_MASK, + CDC_VA_TX_HPF_ZERO_GATE); =20 usleep_range(1000, 1010); hpf_cut_off_freq =3D (snd_soc_component_read(comp, dec_cfg_reg) & @@ -1046,7 +1079,6 @@ static int va_macro_enable_dec(struct snd_soc_dapm_wi= dget *w, 0x0); } =20 - usleep_range(1000, 1010); snd_soc_component_update_bits(comp, hpf_gate_reg, CDC_VA_TX_HPF_ZERO_GATE_MASK, @@ -1246,6 +1278,39 @@ static const char * const adc_mux_text[] =3D { "VA_DMIC", "SWR_MIC" }; =20 +static const char * const smic_mux_text[] =3D { + "ZERO", "ADC0", "ADC1", "ADC2", "ADC3", "SWR_MIC0", "SWR_MIC1", + "SWR_MIC2", "SWR_MIC3", "SWR_MIC4", "SWR_MIC5", "SWR_MIC6", "SWR_MIC7" +}; + +static SOC_ENUM_SINGLE_DECL(va_smic0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG0, + 0, smic_mux_text); + +static SOC_ENUM_SINGLE_DECL(va_smic1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG0, + 0, smic_mux_text); + +static SOC_ENUM_SINGLE_DECL(va_smic2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG0, + 0, smic_mux_text); + +static SOC_ENUM_SINGLE_DECL(va_smic3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG0, + 0, smic_mux_text); + +static const struct snd_kcontrol_new va_smic0_mux =3D SOC_DAPM_ENUM_EXT("v= a_smic0", + va_smic0_enum, snd_soc_dapm_get_enum_double, + va_macro_put_dec_enum); + +static const struct snd_kcontrol_new va_smic1_mux =3D SOC_DAPM_ENUM_EXT("v= a_smic1", + va_smic1_enum, snd_soc_dapm_get_enum_double, + va_macro_put_dec_enum); + +static const struct snd_kcontrol_new va_smic2_mux =3D SOC_DAPM_ENUM_EXT("v= a_smic2", + va_smic2_enum, snd_soc_dapm_get_enum_double, + va_macro_put_dec_enum); + +static const struct snd_kcontrol_new va_smic3_mux =3D SOC_DAPM_ENUM_EXT("v= a_smic3", + va_smic3_enum, snd_soc_dapm_get_enum_double, + va_macro_put_dec_enum); + static SOC_ENUM_SINGLE_DECL(va_dec0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG1, 0, adc_mux_text); static SOC_ENUM_SINGLE_DECL(va_dec1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG1, @@ -1381,6 +1446,11 @@ static const struct snd_soc_dapm_widget va_macro_dap= m_widgets[] =3D { SND_SOC_DAPM_MUX("VA DMIC MUX2", SND_SOC_NOPM, 0, 0, &va_dmic2_mux), SND_SOC_DAPM_MUX("VA DMIC MUX3", SND_SOC_NOPM, 0, 0, &va_dmic3_mux), =20 + SND_SOC_DAPM_MUX("VA SMIC MUX0", SND_SOC_NOPM, 0, 0, &va_smic0_mux), + SND_SOC_DAPM_MUX("VA SMIC MUX1", SND_SOC_NOPM, 0, 0, &va_smic1_mux), + SND_SOC_DAPM_MUX("VA SMIC MUX2", SND_SOC_NOPM, 0, 0, &va_smic2_mux), + SND_SOC_DAPM_MUX("VA SMIC MUX3", SND_SOC_NOPM, 0, 0, &va_smic3_mux), + SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micb", 0, 0), SND_SOC_DAPM_INPUT("DMIC0 Pin"), SND_SOC_DAPM_INPUT("DMIC1 Pin"), @@ -1525,6 +1595,62 @@ static const struct snd_soc_dapm_route va_audio_map[= ] =3D { {"VA DMIC MUX3", "DMIC6", "VA DMIC6"}, {"VA DMIC MUX3", "DMIC7", "VA DMIC7"}, =20 + {"VA DEC0 MUX", "SWR_MIC", "VA SMIC MUX0"}, + {"VA SMIC MUX0", "ADC0", "VA SWR_ADC0"}, + {"VA SMIC MUX0", "ADC1", "VA SWR_ADC1"}, + {"VA SMIC MUX0", "ADC2", "VA SWR_ADC2"}, + {"VA SMIC MUX0", "ADC3", "VA SWR_ADC3"}, + {"VA SMIC MUX0", "SWR_MIC0", "VA SWR_MIC0"}, + {"VA SMIC MUX0", "SWR_MIC1", "VA SWR_MIC1"}, + {"VA SMIC MUX0", "SWR_MIC2", "VA SWR_MIC2"}, + {"VA SMIC MUX0", "SWR_MIC3", "VA SWR_MIC3"}, + {"VA SMIC MUX0", "SWR_MIC4", "VA SWR_MIC4"}, + {"VA SMIC MUX0", "SWR_MIC5", "VA SWR_MIC5"}, + {"VA SMIC MUX0", "SWR_MIC6", "VA SWR_MIC6"}, + {"VA SMIC MUX0", "SWR_MIC7", "VA SWR_MIC7"}, + + {"VA DEC1 MUX", "SWR_MIC", "VA SMIC MUX1"}, + {"VA SMIC MUX1", "ADC0", "VA SWR_ADC0"}, + {"VA SMIC MUX1", "ADC1", "VA SWR_ADC1"}, + {"VA SMIC MUX1", "ADC2", "VA SWR_ADC2"}, + {"VA SMIC MUX1", "ADC3", "VA SWR_ADC3"}, + {"VA SMIC MUX1", "SWR_MIC0", "VA SWR_MIC0"}, + {"VA SMIC MUX1", "SWR_MIC1", "VA SWR_MIC1"}, + {"VA SMIC MUX1", "SWR_MIC2", "VA SWR_MIC2"}, + {"VA SMIC MUX1", "SWR_MIC3", "VA SWR_MIC3"}, + {"VA SMIC MUX1", "SWR_MIC4", "VA SWR_MIC4"}, + {"VA SMIC MUX1", "SWR_MIC5", "VA SWR_MIC5"}, + {"VA SMIC MUX1", "SWR_MIC6", "VA SWR_MIC6"}, + {"VA SMIC MUX1", "SWR_MIC7", "VA SWR_MIC7"}, + + {"VA DEC2 MUX", "SWR_MIC", "VA SMIC MUX2"}, + {"VA SMIC MUX2", "ADC0", "VA SWR_ADC0"}, + {"VA SMIC MUX2", "ADC1", "VA SWR_ADC1"}, + {"VA SMIC MUX2", "ADC2", "VA SWR_ADC2"}, + {"VA SMIC MUX2", "ADC3", "VA SWR_ADC3"}, + {"VA SMIC MUX2", "SWR_MIC0", "VA SWR_MIC0"}, + {"VA SMIC MUX2", "SWR_MIC1", "VA SWR_MIC1"}, + {"VA SMIC MUX2", "SWR_MIC2", "VA SWR_MIC2"}, + {"VA SMIC MUX2", "SWR_MIC3", "VA SWR_MIC3"}, + {"VA SMIC MUX2", "SWR_MIC4", "VA SWR_MIC4"}, + {"VA SMIC MUX2", "SWR_MIC5", "VA SWR_MIC5"}, + {"VA SMIC MUX2", "SWR_MIC6", "VA SWR_MIC6"}, + {"VA SMIC MUX2", "SWR_MIC7", "VA SWR_MIC7"}, + + {"VA DEC3 MUX", "SWR_MIC", "VA SMIC MUX3"}, + {"VA SMIC MUX3", "ADC0", "VA SWR_ADC0"}, + {"VA SMIC MUX3", "ADC1", "VA SWR_ADC1"}, + {"VA SMIC MUX3", "ADC2", "VA SWR_ADC2"}, + {"VA SMIC MUX3", "ADC3", "VA SWR_ADC3"}, + {"VA SMIC MUX3", "SWR_MIC0", "VA SWR_MIC0"}, + {"VA SMIC MUX3", "SWR_MIC1", "VA SWR_MIC1"}, + {"VA SMIC MUX3", "SWR_MIC2", "VA SWR_MIC2"}, + {"VA SMIC MUX3", "SWR_MIC3", "VA SWR_MIC3"}, + {"VA SMIC MUX3", "SWR_MIC4", "VA SWR_MIC4"}, + {"VA SMIC MUX3", "SWR_MIC5", "VA SWR_MIC5"}, + {"VA SMIC MUX3", "SWR_MIC6", "VA SWR_MIC6"}, + {"VA SMIC MUX3", "SWR_MIC7", "VA SWR_MIC7"}, + { "VA DMIC0", NULL, "DMIC0 Pin" }, { "VA DMIC1", NULL, "DMIC1 Pin" }, { "VA DMIC2", NULL, "DMIC2 Pin" }, --=20 2.34.1 From nobody Thu Sep 24 16:09:17 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48CDC4BF935 for ; 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Tue, 22 Sep 2026 02:43:46 -0700 (PDT) Received: from hu-mohs-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-144f2a44cc8sm3776183c88.13.2026.09.22.02.43.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 02:43:45 -0700 (PDT) From: Mohammad Rafi Shaik Date: Tue, 22 Sep 2026 15:12:35 +0530 Subject: [PATCH v4 6/8] ASoC: dt-bindings: qcom: Add Hawi LPASS macro codecs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260922-add_shikra_support-v1-6-6c6cb6444caf@oss.qualcomm.com> References: <20260922-add_shikra_support-v1-0-6c6cb6444caf@oss.qualcomm.com> In-Reply-To: <20260922-add_shikra_support-v1-0-6c6cb6444caf@oss.qualcomm.com> To: Srinivas Kandagatla , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai Cc: Mohammad Rafi Shaik , linux-sound@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prasad Kumpatla X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790070192; l=4222; i=mohammad.rafi.shaik@oss.qualcomm.com; s=20260424; h=from:subject:message-id; bh=KVgaVRGJbpLL89dqvffhwrk/D2FqT70NA6HkMKnCdwE=; b=e4UagyTwv+76gXdrJcMQc1L6gMBVdCgkeTpPBHwxPf8ASkeSobe9fum54TROFlvAJwcb9kTne F5fnQPUS8yPDlwDK5ofSRW3YDSQzgmu/KKKjR6ze4EXwRIPzN2H3+/M X-Developer-Key: i=mohammad.rafi.shaik@oss.qualcomm.com; a=ed25519; pk=KZedmYgMGYOzuTpLGv56tdrL+pTLDP8pdmfQ91xemiA= X-Proofpoint-GUID: ItuI_1do2WaQP_8vtGvoMHkRnKeRHhYb X-Authority-Analysis: v=2.4 cv=B+0sQ+tM c=1 sm=1 tr=0 ts=6ab24dd3 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=MdR4w2dFWrRrHIxOyxQA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIyMDEzOSBTYWx0ZWRfX6qyg2g11zPJi FI3mtFrrUnk8r+EEa37zq1PmLh7H38SvwA1nvHSjQ4YZcwqbEfgygavOJAjUtRyd9Rg0zPftSvZ N951BG385bot1dtG4WMjRTCKpVU2Qb0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIyMDEzOSBTYWx0ZWRfX24uaXu7XzVW6 +Xk0flO1Udo6C7CjAVqlQGJ4yuOXrHOSXuBhD+Colthzuxm3L1uYFPpmO5QDH6zxzHwyzihabd+ LpuxmDHwZqUrW4j+y17hzCMS7/LODBMzCjaOynZ6ixLXPIOgm2dDUQDIK0MeADnix6yFUWY7FTa yBXvw4VqQC8vJKiu2fa1v9K0Iiirm5BImnz1vofdIcgEH9wTkJGxhoorIychntgddp/btG56tir 0Y9GBNaa7f5hGO4eTgbnjH4xSTu8lvyBGOk84MSAdry/pwXKhvmZwnqKLYSoZ3kHUeTcGZvf2bH Vt/31QjyF9g8H2U4A9xHZAcBogcZf0GupfcMBnMQlYONqUhQuSGmasttayZJYjIaLYCgmwKyM8Q RkrASEu/i9TbYNXKOZvRzWiLT/WiBSbNS0dS0riUFdgNekd3dEU9Yc66i9r6qsS69O4o37b2+tq pHv/sdXNR6aj2AMRpkg== X-Proofpoint-ORIG-GUID: ItuI_1do2WaQP_8vtGvoMHkRnKeRHhYb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-21_07,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 adultscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 phishscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609220139 From: Prasad Kumpatla Document compatibles for the RX, TX and VA macro codecs found in the Low Power Audio SubSystem (LPASS) of the Qualcomm Hawi SoC. All three macros differ from SM8550, so describe them as standalone compatibles with their own clock constraints rather than as SM8550 fallbacks: the RX macro uses the 'lpr' clock instead of the 'macro' clock, the TX macro is based on Bolero v4.0, and the VA macro takes an additional "heartbeatpulse" clock sourced from the LPASS VA CSR rate generator. Signed-off-by: Prasad Kumpatla Signed-off-by: Mohammad Rafi Shaik --- .../bindings/sound/qcom,lpass-rx-macro.yaml | 18 +++++++++++++++= +++ .../bindings/sound/qcom,lpass-tx-macro.yaml | 19 +++++++++++++++= ++++ .../bindings/sound/qcom,lpass-va-macro.yaml | 19 +++++++++++++++= ++++ 3 files changed, 56 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.ya= ml b/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml index 69d7b7332d36..1d3945190c1d 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml @@ -13,6 +13,7 @@ properties: compatible: oneOf: - enum: + - qcom,hawi-lpass-rx-macro - qcom,sc7280-lpass-rx-macro - qcom,shikra-lpass-rx-macro - qcom,sm6115-lpass-rx-macro @@ -139,6 +140,23 @@ allOf: - const: dcodec - const: fsgen =20 + - if: + properties: + compatible: + enum: + - qcom,hawi-lpass-rx-macro + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: mclk + - const: lpr + - const: dcodec + - const: fsgen + - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.ya= ml b/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml index d8682ff2e82c..2df72450d36f 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml @@ -13,6 +13,7 @@ properties: compatible: oneOf: - enum: + - qcom,hawi-lpass-tx-macro - qcom,sc7280-lpass-tx-macro - qcom,sm6115-lpass-tx-macro - qcom,sm8250-lpass-tx-macro @@ -142,6 +143,24 @@ allOf: - const: dcodec - const: fsgen =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-lpass-tx-macro + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: mclk + - const: lpr + - const: dcodec + - const: fsgen + unevaluatedProperties: false =20 examples: diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.ya= ml b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml index 683ebf702ba8..7d56f9c36056 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml @@ -13,6 +13,7 @@ properties: compatible: oneOf: - enum: + - qcom,hawi-lpass-va-macro - qcom,sc7280-lpass-va-macro - qcom,shikra-lpass-va-macro - qcom,sm6115-lpass-va-macro @@ -185,6 +186,24 @@ allOf: - const: mclk - const: npl =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-lpass-va-macro + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: mclk + - const: lpr + - const: dcodec + - const: heartbeatpulse + unevaluatedProperties: false =20 examples: --=20 2.34.1 From nobody Thu Sep 24 16:09:17 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 380814E4C2C for ; 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Tue, 22 Sep 2026 02:43:51 -0700 (PDT) Received: from hu-mohs-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-144f2a44cc8sm3776183c88.13.2026.09.22.02.43.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 02:43:51 -0700 (PDT) From: Mohammad Rafi Shaik Date: Tue, 22 Sep 2026 15:12:36 +0530 Subject: [PATCH v4 7/8] ASoC: qcom: lpass-tx-macro: Add support for Bolero v4.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260922-add_shikra_support-v1-7-6c6cb6444caf@oss.qualcomm.com> References: <20260922-add_shikra_support-v1-0-6c6cb6444caf@oss.qualcomm.com> In-Reply-To: <20260922-add_shikra_support-v1-0-6c6cb6444caf@oss.qualcomm.com> To: Srinivas Kandagatla , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai Cc: Mohammad Rafi Shaik , linux-sound@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prasad Kumpatla , Sarath Ganapathiraju X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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Add the additional CFG2 mux registers and per-path CFG2 registers to the register map, extend the maximum register offset to cover the new ADPT control register, and describe the new v4.0 decimator, SWR microphone, WSA and port-select mux widgets and their routes. The ADPT block has to be disabled before a decimator is enabled. This register only exists on v4.0, so gate the write on a has_adpt flag set from the match data rather than issuing it unconditionally. Add the "qcom,hawi-lpass-tx-macro" compatible and its match data to select the new widgets and routes. Co-developed-by: Sarath Ganapathiraju Signed-off-by: Sarath Ganapathiraju Signed-off-by: Prasad Kumpatla Signed-off-by: Mohammad Rafi Shaik --- sound/soc/codecs/lpass-macro-common.h | 1 + sound/soc/codecs/lpass-tx-macro.c | 442 ++++++++++++++++++++++++++++++= +++- 2 files changed, 442 insertions(+), 1 deletion(-) diff --git a/sound/soc/codecs/lpass-macro-common.h b/sound/soc/codecs/lpass= -macro-common.h index b52665b11e35..707b22a6bda6 100644 --- a/sound/soc/codecs/lpass-macro-common.h +++ b/sound/soc/codecs/lpass-macro-common.h @@ -16,6 +16,7 @@ enum lpass_version { LPASS_VER_9_2_0, LPASS_VER_10_0_0, LPASS_VER_11_0_0, + LPASS_VER_15_0_0, }; =20 enum lpass_codec_version { diff --git a/sound/soc/codecs/lpass-tx-macro.c b/sound/soc/codecs/lpass-tx-= macro.c index 6deaaabe43af..b1eee16e968c 100644 --- a/sound/soc/codecs/lpass-tx-macro.c +++ b/sound/soc/codecs/lpass-tx-macro.c @@ -67,6 +67,14 @@ #define CDC_TX_INP_MUX_ADC_MUX6_CFG1 (0x0134) #define CDC_TX_INP_MUX_ADC_MUX7_CFG0 (0x0138) #define CDC_TX_INP_MUX_ADC_MUX7_CFG1 (0x013C) +#define CDC_TX_INP_MUX_ADC_MUX0_CFG2 (0x0140) +#define CDC_TX_INP_MUX_ADC_MUX1_CFG2 (0x0144) +#define CDC_TX_INP_MUX_ADC_MUX2_CFG2 (0x0148) +#define CDC_TX_INP_MUX_ADC_MUX3_CFG2 (0x014C) +#define CDC_TX_INP_MUX_ADC_MUX4_CFG2 (0x0150) +#define CDC_TX_INP_MUX_ADC_MUX5_CFG2 (0x0154) +#define CDC_TX_INP_MUX_ADC_MUX6_CFG2 (0x0158) +#define CDC_TX_INP_MUX_ADC_MUX7_CFG2 (0x015C) #define CDC_TX_ANC0_CLK_RESET_CTL (0x0200) #define CDC_TX_ANC0_MODE_1_CTL (0x0204) #define CDC_TX_ANC0_MODE_2_CTL (0x0208) @@ -108,6 +116,16 @@ #define CDC_TX0_TX_PATH_SEC5 (0x0424) #define CDC_TX0_TX_PATH_SEC6 (0x0428) #define CDC_TX0_TX_PATH_SEC7 (0x042C) +#define CDC_TX0_TX_PATH_CFG2 (0x0430) +#define CDC_TX1_TX_PATH_CFG2 (0x04B0) +#define CDC_TX2_TX_PATH_CFG2 (0x0530) +#define CDC_TX3_TX_PATH_CFG2 (0x05B0) +#define CDC_TX4_TX_PATH_CFG2 (0x0630) +#define CDC_TX5_TX_PATH_CFG2 (0x06B0) +#define CDC_TX6_TX_PATH_CFG2 (0x0730) +#define CDC_TX7_TX_PATH_CFG2 (0x07B0) +#define CDC_ADPT0_ADPT_CTRL (0x0800) + #define CDC_TX0_MBHC_CTL_EN_MASK BIT(6) #define CDC_TX1_TX_PATH_CTL (0x0480) #define CDC_TX1_TX_PATH_CFG0 (0x0484) @@ -186,7 +204,7 @@ #define CDC_TX7_TX_PATH_SEC4 (0x07A0) #define CDC_TX7_TX_PATH_SEC5 (0x07A4) #define CDC_TX7_TX_PATH_SEC6 (0x07A8) -#define TX_MAX_OFFSET (0x07A8) +#define TX_MAX_OFFSET (CDC_ADPT0_ADPT_CTRL) =20 #define TX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ @@ -258,6 +276,7 @@ struct hpf_work { struct tx_macro_data { unsigned int flags; unsigned int ver; + bool has_adpt; const struct snd_soc_dapm_widget *extra_widgets; size_t extra_widgets_num; const struct snd_soc_dapm_route *extra_routes; @@ -327,6 +346,14 @@ static struct reg_default tx_defaults[] =3D { { CDC_TX_INP_MUX_ADC_MUX6_CFG1, 0x00}, { CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0x00}, { CDC_TX_INP_MUX_ADC_MUX7_CFG1, 0x00}, + { CDC_TX_INP_MUX_ADC_MUX0_CFG2, 0x00}, + { CDC_TX_INP_MUX_ADC_MUX1_CFG2, 0x00}, + { CDC_TX_INP_MUX_ADC_MUX2_CFG2, 0x00}, + { CDC_TX_INP_MUX_ADC_MUX3_CFG2, 0x00}, + { CDC_TX_INP_MUX_ADC_MUX4_CFG2, 0x00}, + { CDC_TX_INP_MUX_ADC_MUX5_CFG2, 0x00}, + { CDC_TX_INP_MUX_ADC_MUX6_CFG2, 0x00}, + { CDC_TX_INP_MUX_ADC_MUX7_CFG2, 0x00}, { CDC_TX_ANC0_CLK_RESET_CTL, 0x00}, { CDC_TX_ANC0_MODE_1_CTL, 0x00}, { CDC_TX_ANC0_MODE_2_CTL, 0x00}, @@ -432,6 +459,15 @@ static struct reg_default tx_defaults[] =3D { { CDC_TX7_TX_PATH_SEC4, 0x20}, { CDC_TX7_TX_PATH_SEC5, 0x00}, { CDC_TX7_TX_PATH_SEC6, 0x00}, + { CDC_TX0_TX_PATH_CFG2, 0x03}, + { CDC_TX1_TX_PATH_CFG2, 0x03}, + { CDC_TX2_TX_PATH_CFG2, 0x03}, + { CDC_TX3_TX_PATH_CFG2, 0x03}, + { CDC_TX4_TX_PATH_CFG2, 0x03}, + { CDC_TX5_TX_PATH_CFG2, 0x03}, + { CDC_TX6_TX_PATH_CFG2, 0x03}, + { CDC_TX7_TX_PATH_CFG2, 0x03}, + { CDC_ADPT0_ADPT_CTRL, 0x00}, }; =20 static bool tx_is_volatile_register(struct device *dev, unsigned int reg) @@ -502,6 +538,14 @@ static bool tx_is_rw_register(struct device *dev, unsi= gned int reg) case CDC_TX_INP_MUX_ADC_MUX6_CFG1: case CDC_TX_INP_MUX_ADC_MUX7_CFG0: case CDC_TX_INP_MUX_ADC_MUX7_CFG1: + case CDC_TX_INP_MUX_ADC_MUX0_CFG2: + case CDC_TX_INP_MUX_ADC_MUX1_CFG2: + case CDC_TX_INP_MUX_ADC_MUX2_CFG2: + case CDC_TX_INP_MUX_ADC_MUX3_CFG2: + case CDC_TX_INP_MUX_ADC_MUX4_CFG2: + case CDC_TX_INP_MUX_ADC_MUX5_CFG2: + case CDC_TX_INP_MUX_ADC_MUX6_CFG2: + case CDC_TX_INP_MUX_ADC_MUX7_CFG2: case CDC_TX0_TX_PATH_CTL: case CDC_TX0_TX_PATH_CFG0: case CDC_TX0_TX_PATH_CFG1: @@ -591,6 +635,15 @@ static bool tx_is_rw_register(struct device *dev, unsi= gned int reg) case CDC_TX7_TX_PATH_SEC4: case CDC_TX7_TX_PATH_SEC5: case CDC_TX7_TX_PATH_SEC6: + case CDC_TX0_TX_PATH_CFG2: + case CDC_TX1_TX_PATH_CFG2: + case CDC_TX2_TX_PATH_CFG2: + case CDC_TX3_TX_PATH_CFG2: + case CDC_TX4_TX_PATH_CFG2: + case CDC_TX5_TX_PATH_CFG2: + case CDC_TX6_TX_PATH_CFG2: + case CDC_TX7_TX_PATH_CFG2: + case CDC_ADPT0_ADPT_CTRL: return true; } =20 @@ -929,6 +982,9 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widg= et *w, =20 switch (event) { case SND_SOC_DAPM_PRE_PMU: + /* Disable the ADPT block before enabling the decimator */ + if (tx->data->has_adpt) + snd_soc_component_write_field(component, CDC_ADPT0_ADPT_CTRL, 0xFF, 0x0= ); adc_mux_reg =3D CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator); if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) { adc_reg =3D CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator); @@ -2027,6 +2083,377 @@ static const struct snd_soc_dapm_route tx_audio_map= _v9_2[] =3D { {"TX SMIC MUX7", "SWR_MIC11", "TX SWR_INPUT11"}, }; =20 +static const char * const adc_mux_text_v9_3[] =3D { + "MSM_DMIC", "SWR_MIC", "ANC_FB_TUNE1", "RX_SWR_MIC" +}; + +static SOC_ENUM_SINGLE_DECL(tx_dec0_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX0_CFG= 1, + 0, adc_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_dec1_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX1_CFG= 1, + 0, adc_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_dec2_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX2_CFG= 1, + 0, adc_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_dec3_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX3_CFG= 1, + 0, adc_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_dec4_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX4_CFG= 1, + 0, adc_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_dec5_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX5_CFG= 1, + 0, adc_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_dec6_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX6_CFG= 1, + 0, adc_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_dec7_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX7_CFG= 1, + 0, adc_mux_text_v9_3); + +static const struct snd_kcontrol_new tx_dec0_mux_v9_3 =3D + SOC_DAPM_ENUM("tx_dec0", tx_dec0_enum_v9_3); +static const struct snd_kcontrol_new tx_dec1_mux_v9_3 =3D + SOC_DAPM_ENUM("tx_dec1", tx_dec1_enum_v9_3); +static const struct snd_kcontrol_new tx_dec2_mux_v9_3 =3D + SOC_DAPM_ENUM("tx_dec2", tx_dec2_enum_v9_3); +static const struct snd_kcontrol_new tx_dec3_mux_v9_3 =3D + SOC_DAPM_ENUM("tx_dec3", tx_dec3_enum_v9_3); +static const struct snd_kcontrol_new tx_dec4_mux_v9_3 =3D + SOC_DAPM_ENUM("tx_dec4", tx_dec4_enum_v9_3); +static const struct snd_kcontrol_new tx_dec5_mux_v9_3 =3D + SOC_DAPM_ENUM("tx_dec5", tx_dec5_enum_v9_3); +static const struct snd_kcontrol_new tx_dec6_mux_v9_3 =3D + SOC_DAPM_ENUM("tx_dec6", tx_dec6_enum_v9_3); +static const struct snd_kcontrol_new tx_dec7_mux_v9_3 =3D + SOC_DAPM_ENUM("tx_dec7", tx_dec7_enum_v9_3); + +static const char * const smic_mux_text_v9_3[] =3D { + "ZERO", "SWR_MIC0", "SWR_MIC1", "SWR_MIC2", "SWR_MIC3", + "SWR_MIC4", "SWR_MIC5", "SWR_MIC6", "SWR_MIC7", +}; + +static SOC_ENUM_SINGLE_DECL(tx_smic0_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX0_CF= G0, + 0, smic_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_smic1_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX1_CF= G0, + 0, smic_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_smic2_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX2_CF= G0, + 0, smic_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_smic3_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX3_CF= G0, + 0, smic_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_smic4_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX4_CF= G0, + 0, smic_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_smic5_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX5_CF= G0, + 0, smic_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_smic6_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX6_CF= G0, + 0, smic_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_smic7_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX7_CF= G0, + 0, smic_mux_text_v9_3); + +static const struct snd_kcontrol_new tx_smic0_mux_v9_3 =3D SOC_DAPM_ENUM_E= XT("tx_smic0", + tx_smic0_enum_v9_3, snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum= ); +static const struct snd_kcontrol_new tx_smic1_mux_v9_3 =3D SOC_DAPM_ENUM_E= XT("tx_smic1", + tx_smic1_enum_v9_3, snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum= ); +static const struct snd_kcontrol_new tx_smic2_mux_v9_3 =3D SOC_DAPM_ENUM_E= XT("tx_smic2", + tx_smic2_enum_v9_3, snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum= ); +static const struct snd_kcontrol_new tx_smic3_mux_v9_3 =3D SOC_DAPM_ENUM_E= XT("tx_smic3", + tx_smic3_enum_v9_3, snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum= ); +static const struct snd_kcontrol_new tx_smic4_mux_v9_3 =3D SOC_DAPM_ENUM_E= XT("tx_smic4", + tx_smic4_enum_v9_3, snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum= ); +static const struct snd_kcontrol_new tx_smic5_mux_v9_3 =3D SOC_DAPM_ENUM_E= XT("tx_smic5", + tx_smic5_enum_v9_3, snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum= ); +static const struct snd_kcontrol_new tx_smic6_mux_v9_3 =3D SOC_DAPM_ENUM_E= XT("tx_smic6", + tx_smic6_enum_v9_3, snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum= ); +static const struct snd_kcontrol_new tx_smic7_mux_v9_3 =3D SOC_DAPM_ENUM_E= XT("tx_smic7", + tx_smic7_enum_v9_3, snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum= ); + +static const char * const tx_wsa_mux_text[] =3D { + "NO_WSA", "WSA1", "WSA2", "WSA3", "WSA4" +}; + +static SOC_ENUM_SINGLE_DECL(tx_wsa_mux0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG1, + 4, tx_wsa_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_wsa_mux1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG1, + 4, tx_wsa_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_wsa_mux2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG1, + 4, tx_wsa_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_wsa_mux3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG1, + 4, tx_wsa_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_wsa_mux4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG1, + 4, tx_wsa_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_wsa_mux5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG1, + 4, tx_wsa_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_wsa_mux6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG1, + 4, tx_wsa_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_wsa_mux7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG1, + 4, tx_wsa_mux_text); + +static const struct snd_kcontrol_new tx_wsa_mux0_mux =3D + SOC_DAPM_ENUM("tx_wsa_mux0", tx_wsa_mux0_enum); +static const struct snd_kcontrol_new tx_wsa_mux1_mux =3D + SOC_DAPM_ENUM("tx_wsa_mux1", tx_wsa_mux1_enum); +static const struct snd_kcontrol_new tx_wsa_mux2_mux =3D + SOC_DAPM_ENUM("tx_wsa_mux2", tx_wsa_mux2_enum); +static const struct snd_kcontrol_new tx_wsa_mux3_mux =3D + SOC_DAPM_ENUM("tx_wsa_mux3", tx_wsa_mux3_enum); +static const struct snd_kcontrol_new tx_wsa_mux4_mux =3D + SOC_DAPM_ENUM("tx_wsa_mux4", tx_wsa_mux4_enum); +static const struct snd_kcontrol_new tx_wsa_mux5_mux =3D + SOC_DAPM_ENUM("tx_wsa_mux5", tx_wsa_mux5_enum); +static const struct snd_kcontrol_new tx_wsa_mux6_mux =3D + SOC_DAPM_ENUM("tx_wsa_mux6", tx_wsa_mux6_enum); +static const struct snd_kcontrol_new tx_wsa_mux7_mux =3D + SOC_DAPM_ENUM("tx_wsa_mux7", tx_wsa_mux7_enum); + +static const char * const tx_psel_mux_text[] =3D { + "PORT0", "PORT1", "PORT2", "PORT3", "PORT4" +}; + +static SOC_ENUM_SINGLE_DECL(tx_psel_mux0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG= 2, + 0, tx_psel_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_psel_mux1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG= 2, + 0, tx_psel_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_psel_mux2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG= 2, + 0, tx_psel_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_psel_mux3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG= 2, + 0, tx_psel_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_psel_mux4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG= 2, + 0, tx_psel_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_psel_mux5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG= 2, + 0, tx_psel_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_psel_mux6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG= 2, + 0, tx_psel_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_psel_mux7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG= 2, + 0, tx_psel_mux_text); + +static const struct snd_kcontrol_new tx_psel_mux0_mux =3D + SOC_DAPM_ENUM("tx_psel_mux0", tx_psel_mux0_enum); +static const struct snd_kcontrol_new tx_psel_mux1_mux =3D + SOC_DAPM_ENUM("tx_psel_mux1", tx_psel_mux1_enum); +static const struct snd_kcontrol_new tx_psel_mux2_mux =3D + SOC_DAPM_ENUM("tx_psel_mux2", tx_psel_mux2_enum); +static const struct snd_kcontrol_new tx_psel_mux3_mux =3D + SOC_DAPM_ENUM("tx_psel_mux3", tx_psel_mux3_enum); +static const struct snd_kcontrol_new tx_psel_mux4_mux =3D + SOC_DAPM_ENUM("tx_psel_mux4", tx_psel_mux4_enum); +static const struct snd_kcontrol_new tx_psel_mux5_mux =3D + SOC_DAPM_ENUM("tx_psel_mux5", tx_psel_mux5_enum); +static const struct snd_kcontrol_new tx_psel_mux6_mux =3D + SOC_DAPM_ENUM("tx_psel_mux6", tx_psel_mux6_enum); +static const struct snd_kcontrol_new tx_psel_mux7_mux =3D + SOC_DAPM_ENUM("tx_psel_mux7", tx_psel_mux7_enum); + +static const struct snd_soc_dapm_widget tx_macro_dapm_widgets_v15[] =3D { + SND_SOC_DAPM_MUX("TX DEC0 MUX", SND_SOC_NOPM, 0, 0, &tx_dec0_mux_v9_3), + SND_SOC_DAPM_MUX("TX DEC1 MUX", SND_SOC_NOPM, 0, 0, &tx_dec1_mux_v9_3), + SND_SOC_DAPM_MUX("TX DEC2 MUX", SND_SOC_NOPM, 0, 0, &tx_dec2_mux_v9_3), + SND_SOC_DAPM_MUX("TX DEC3 MUX", SND_SOC_NOPM, 0, 0, &tx_dec3_mux_v9_3), + SND_SOC_DAPM_MUX("TX DEC4 MUX", SND_SOC_NOPM, 0, 0, &tx_dec4_mux_v9_3), + SND_SOC_DAPM_MUX("TX DEC5 MUX", SND_SOC_NOPM, 0, 0, &tx_dec5_mux_v9_3), + SND_SOC_DAPM_MUX("TX DEC6 MUX", SND_SOC_NOPM, 0, 0, &tx_dec6_mux_v9_3), + SND_SOC_DAPM_MUX("TX DEC7 MUX", SND_SOC_NOPM, 0, 0, &tx_dec7_mux_v9_3), + + SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux_v9_3), + SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux_v9_3), + SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux_v9_3), + SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux_v9_3), + SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux_v9_3), + SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux_v9_3), + SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux_v9_3), + SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux_v9_3), + + SND_SOC_DAPM_MUX("TX WSA MUX0", SND_SOC_NOPM, 0, 0, &tx_wsa_mux0_mux), + SND_SOC_DAPM_MUX("TX WSA MUX1", SND_SOC_NOPM, 0, 0, &tx_wsa_mux1_mux), + SND_SOC_DAPM_MUX("TX WSA MUX2", SND_SOC_NOPM, 0, 0, &tx_wsa_mux2_mux), + SND_SOC_DAPM_MUX("TX WSA MUX3", SND_SOC_NOPM, 0, 0, &tx_wsa_mux3_mux), + SND_SOC_DAPM_MUX("TX WSA MUX4", SND_SOC_NOPM, 0, 0, &tx_wsa_mux4_mux), + SND_SOC_DAPM_MUX("TX WSA MUX5", SND_SOC_NOPM, 0, 0, &tx_wsa_mux5_mux), + SND_SOC_DAPM_MUX("TX WSA MUX6", SND_SOC_NOPM, 0, 0, &tx_wsa_mux6_mux), + SND_SOC_DAPM_MUX("TX WSA MUX7", SND_SOC_NOPM, 0, 0, &tx_wsa_mux7_mux), + + SND_SOC_DAPM_MUX("TX PORT SEL MUX0", SND_SOC_NOPM, 0, 0, &tx_psel_mux0_mu= x), + SND_SOC_DAPM_MUX("TX PORT SEL MUX1", SND_SOC_NOPM, 0, 0, &tx_psel_mux1_mu= x), + SND_SOC_DAPM_MUX("TX PORT SEL MUX2", SND_SOC_NOPM, 0, 0, &tx_psel_mux2_mu= x), + SND_SOC_DAPM_MUX("TX PORT SEL MUX3", SND_SOC_NOPM, 0, 0, &tx_psel_mux3_mu= x), + SND_SOC_DAPM_MUX("TX PORT SEL MUX4", SND_SOC_NOPM, 0, 0, &tx_psel_mux4_mu= x), + SND_SOC_DAPM_MUX("TX PORT SEL MUX5", SND_SOC_NOPM, 0, 0, &tx_psel_mux5_mu= x), + SND_SOC_DAPM_MUX("TX PORT SEL MUX6", SND_SOC_NOPM, 0, 0, &tx_psel_mux6_mu= x), + SND_SOC_DAPM_MUX("TX PORT SEL MUX7", SND_SOC_NOPM, 0, 0, &tx_psel_mux7_mu= x), + + SND_SOC_DAPM_INPUT("TX SWR_INPUT"), +}; + +static const struct snd_soc_dapm_route tx_audio_map_v15[] =3D { + /* DEC0 */ + {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"}, + {"TX SMIC MUX0", NULL, "TX_SWR_CLK"}, + {"TX SMIC MUX0", "SWR_MIC0", "TX WSA MUX0"}, + {"TX SMIC MUX0", "SWR_MIC1", "TX WSA MUX0"}, + {"TX SMIC MUX0", "SWR_MIC2", "TX WSA MUX0"}, + {"TX SMIC MUX0", "SWR_MIC3", "TX WSA MUX0"}, + {"TX SMIC MUX0", "SWR_MIC4", "TX WSA MUX0"}, + {"TX SMIC MUX0", "SWR_MIC5", "TX WSA MUX0"}, + {"TX SMIC MUX0", "SWR_MIC6", "TX WSA MUX0"}, + {"TX SMIC MUX0", "SWR_MIC7", "TX WSA MUX0"}, + {"TX WSA MUX0", "NO_WSA", "TX PORT SEL MUX0"}, + {"TX WSA MUX0", "WSA1", "TX PORT SEL MUX0"}, + {"TX WSA MUX0", "WSA2", "TX PORT SEL MUX0"}, + {"TX WSA MUX0", "WSA3", "TX PORT SEL MUX0"}, + {"TX WSA MUX0", "WSA4", "TX PORT SEL MUX0"}, + {"TX PORT SEL MUX0", "PORT0", "TX SWR_INPUT"}, + {"TX PORT SEL MUX0", "PORT1", "TX SWR_INPUT"}, + {"TX PORT SEL MUX0", "PORT2", "TX SWR_INPUT"}, + {"TX PORT SEL MUX0", "PORT3", "TX SWR_INPUT"}, + {"TX PORT SEL MUX0", "PORT4", "TX SWR_INPUT"}, + + /* DEC1 */ + {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"}, + {"TX SMIC MUX1", NULL, "TX_SWR_CLK"}, + {"TX SMIC MUX1", "SWR_MIC0", "TX WSA MUX1"}, + {"TX SMIC MUX1", "SWR_MIC1", "TX WSA MUX1"}, + {"TX SMIC MUX1", "SWR_MIC2", "TX WSA MUX1"}, + {"TX SMIC MUX1", "SWR_MIC3", "TX WSA MUX1"}, + {"TX SMIC MUX1", "SWR_MIC4", "TX WSA MUX1"}, + {"TX SMIC MUX1", "SWR_MIC5", "TX WSA MUX1"}, + {"TX SMIC MUX1", "SWR_MIC6", "TX WSA MUX1"}, + {"TX SMIC MUX1", "SWR_MIC7", "TX WSA MUX1"}, + {"TX WSA MUX1", "NO_WSA", "TX PORT SEL MUX1"}, + {"TX WSA MUX1", "WSA1", "TX PORT SEL MUX1"}, + {"TX WSA MUX1", "WSA2", "TX PORT SEL MUX1"}, + {"TX WSA MUX1", "WSA3", "TX PORT SEL MUX1"}, + {"TX WSA MUX1", "WSA4", "TX PORT SEL MUX1"}, + {"TX PORT SEL MUX1", "PORT0", "TX SWR_INPUT"}, + {"TX PORT SEL MUX1", "PORT1", "TX SWR_INPUT"}, + {"TX PORT SEL MUX1", "PORT2", "TX SWR_INPUT"}, + {"TX PORT SEL MUX1", "PORT3", "TX SWR_INPUT"}, + {"TX PORT SEL MUX1", "PORT4", "TX SWR_INPUT"}, + + /* DEC2 */ + {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"}, + {"TX SMIC MUX2", NULL, "TX_SWR_CLK"}, + {"TX SMIC MUX2", "SWR_MIC0", "TX WSA MUX2"}, + {"TX SMIC MUX2", "SWR_MIC1", "TX WSA MUX2"}, + {"TX SMIC MUX2", "SWR_MIC2", "TX WSA MUX2"}, + {"TX SMIC MUX2", "SWR_MIC3", "TX WSA MUX2"}, + {"TX SMIC MUX2", "SWR_MIC4", "TX WSA MUX2"}, + {"TX SMIC MUX2", "SWR_MIC5", "TX WSA MUX2"}, + {"TX SMIC MUX2", "SWR_MIC6", "TX WSA MUX2"}, + {"TX SMIC MUX2", "SWR_MIC7", "TX WSA MUX2"}, + {"TX WSA MUX2", "NO_WSA", "TX PORT SEL MUX2"}, + {"TX WSA MUX2", "WSA1", "TX PORT SEL MUX2"}, + {"TX WSA MUX2", "WSA2", "TX PORT SEL MUX2"}, + {"TX WSA MUX2", "WSA3", "TX PORT SEL MUX2"}, + {"TX WSA MUX2", "WSA4", "TX PORT SEL MUX2"}, + {"TX PORT SEL MUX2", "PORT0", "TX SWR_INPUT"}, + {"TX PORT SEL MUX2", "PORT1", "TX SWR_INPUT"}, + {"TX PORT SEL MUX2", "PORT2", "TX SWR_INPUT"}, + {"TX PORT SEL MUX2", "PORT3", "TX SWR_INPUT"}, + {"TX PORT SEL MUX2", "PORT4", "TX SWR_INPUT"}, + + /* DEC3 */ + {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"}, + {"TX SMIC MUX3", NULL, "TX_SWR_CLK"}, + {"TX SMIC MUX3", "SWR_MIC0", "TX WSA MUX3"}, + {"TX SMIC MUX3", "SWR_MIC1", "TX WSA MUX3"}, + {"TX SMIC MUX3", "SWR_MIC2", "TX WSA MUX3"}, + {"TX SMIC MUX3", "SWR_MIC3", "TX WSA MUX3"}, + {"TX SMIC MUX3", "SWR_MIC4", "TX WSA MUX3"}, + {"TX SMIC MUX3", "SWR_MIC5", "TX WSA MUX3"}, + {"TX SMIC MUX3", "SWR_MIC6", "TX WSA MUX3"}, + {"TX SMIC MUX3", "SWR_MIC7", "TX WSA MUX3"}, + {"TX WSA MUX3", "NO_WSA", "TX PORT SEL MUX3"}, + {"TX WSA MUX3", "WSA1", "TX PORT SEL MUX3"}, + {"TX WSA MUX3", "WSA2", "TX PORT SEL MUX3"}, + {"TX WSA MUX3", "WSA3", "TX PORT SEL MUX3"}, + {"TX WSA MUX3", "WSA4", "TX PORT SEL MUX3"}, + {"TX PORT SEL MUX3", "PORT0", "TX SWR_INPUT"}, + {"TX PORT SEL MUX3", "PORT1", "TX SWR_INPUT"}, + {"TX PORT SEL MUX3", "PORT2", "TX SWR_INPUT"}, + {"TX PORT SEL MUX3", "PORT3", "TX SWR_INPUT"}, + {"TX PORT SEL MUX3", "PORT4", "TX SWR_INPUT"}, + + /* DEC4 */ + {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"}, + {"TX SMIC MUX4", NULL, "TX_SWR_CLK"}, + {"TX SMIC MUX4", "SWR_MIC0", "TX WSA MUX4"}, + {"TX SMIC MUX4", "SWR_MIC1", "TX WSA MUX4"}, + {"TX SMIC MUX4", "SWR_MIC2", "TX WSA MUX4"}, + {"TX SMIC MUX4", "SWR_MIC3", "TX WSA MUX4"}, + {"TX SMIC MUX4", "SWR_MIC4", "TX WSA MUX4"}, + {"TX SMIC MUX4", "SWR_MIC5", "TX WSA MUX4"}, + {"TX SMIC MUX4", "SWR_MIC6", "TX WSA MUX4"}, + {"TX SMIC MUX4", "SWR_MIC7", "TX WSA MUX4"}, + {"TX WSA MUX4", "NO_WSA", "TX PORT SEL MUX4"}, + {"TX WSA MUX4", "WSA1", "TX PORT SEL MUX4"}, + {"TX WSA MUX4", "WSA2", "TX PORT SEL MUX4"}, + {"TX WSA MUX4", "WSA3", "TX PORT SEL MUX4"}, + {"TX WSA MUX4", "WSA4", "TX PORT SEL MUX4"}, + {"TX PORT SEL MUX4", "PORT0", "TX SWR_INPUT"}, + {"TX PORT SEL MUX4", "PORT1", "TX SWR_INPUT"}, + {"TX PORT SEL MUX4", "PORT2", "TX SWR_INPUT"}, + {"TX PORT SEL MUX4", "PORT3", "TX SWR_INPUT"}, + {"TX PORT SEL MUX4", "PORT4", "TX SWR_INPUT"}, + + /* DEC5 */ + {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"}, + {"TX SMIC MUX5", NULL, "TX_SWR_CLK"}, + {"TX SMIC MUX5", "SWR_MIC0", "TX WSA MUX5"}, + {"TX SMIC MUX5", "SWR_MIC1", "TX WSA MUX5"}, + {"TX SMIC MUX5", "SWR_MIC2", "TX WSA MUX5"}, + {"TX SMIC MUX5", "SWR_MIC3", "TX WSA MUX5"}, + {"TX SMIC MUX5", "SWR_MIC4", "TX WSA MUX5"}, + {"TX SMIC MUX5", "SWR_MIC5", "TX WSA MUX5"}, + {"TX SMIC MUX5", "SWR_MIC6", "TX WSA MUX5"}, + {"TX SMIC MUX5", "SWR_MIC7", "TX WSA MUX5"}, + {"TX WSA MUX5", "NO_WSA", "TX PORT SEL MUX5"}, + {"TX WSA MUX5", "WSA1", "TX PORT SEL MUX5"}, + {"TX WSA MUX5", "WSA2", "TX PORT SEL MUX5"}, + {"TX WSA MUX5", "WSA3", "TX PORT SEL MUX5"}, + {"TX WSA MUX5", "WSA4", "TX PORT SEL MUX5"}, + {"TX PORT SEL MUX5", "PORT0", "TX SWR_INPUT"}, + {"TX PORT SEL MUX5", "PORT1", "TX SWR_INPUT"}, + {"TX PORT SEL MUX5", "PORT2", "TX SWR_INPUT"}, + {"TX PORT SEL MUX5", "PORT3", "TX SWR_INPUT"}, + {"TX PORT SEL MUX5", "PORT4", "TX SWR_INPUT"}, + + /* DEC6 */ + {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"}, + {"TX SMIC MUX6", NULL, "TX_SWR_CLK"}, + {"TX SMIC MUX6", "SWR_MIC0", "TX WSA MUX6"}, + {"TX SMIC MUX6", "SWR_MIC1", "TX WSA MUX6"}, + {"TX SMIC MUX6", "SWR_MIC2", "TX WSA MUX6"}, + {"TX SMIC MUX6", "SWR_MIC3", "TX WSA MUX6"}, + {"TX SMIC MUX6", "SWR_MIC4", "TX WSA MUX6"}, + {"TX SMIC MUX6", "SWR_MIC5", "TX WSA MUX6"}, + {"TX SMIC MUX6", "SWR_MIC6", "TX WSA MUX6"}, + {"TX SMIC MUX6", "SWR_MIC7", "TX WSA MUX6"}, + {"TX WSA MUX6", "NO_WSA", "TX PORT SEL MUX6"}, + {"TX WSA MUX6", "WSA1", "TX PORT SEL MUX6"}, + {"TX WSA MUX6", "WSA2", "TX PORT SEL MUX6"}, + {"TX WSA MUX6", "WSA3", "TX PORT SEL MUX6"}, + {"TX WSA MUX6", "WSA4", "TX PORT SEL MUX6"}, + {"TX PORT SEL MUX6", "PORT0", "TX SWR_INPUT"}, + {"TX PORT SEL MUX6", "PORT1", "TX SWR_INPUT"}, + {"TX PORT SEL MUX6", "PORT2", "TX SWR_INPUT"}, + {"TX PORT SEL MUX6", "PORT3", "TX SWR_INPUT"}, + {"TX PORT SEL MUX6", "PORT4", "TX SWR_INPUT"}, + + /* DEC7 */ + {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"}, + {"TX SMIC MUX7", NULL, "TX_SWR_CLK"}, + {"TX SMIC MUX7", "SWR_MIC0", "TX WSA MUX7"}, + {"TX SMIC MUX7", "SWR_MIC1", "TX WSA MUX7"}, + {"TX SMIC MUX7", "SWR_MIC2", "TX WSA MUX7"}, + {"TX SMIC MUX7", "SWR_MIC3", "TX WSA MUX7"}, + {"TX SMIC MUX7", "SWR_MIC4", "TX WSA MUX7"}, + {"TX SMIC MUX7", "SWR_MIC5", "TX WSA MUX7"}, + {"TX SMIC MUX7", "SWR_MIC6", "TX WSA MUX7"}, + {"TX SMIC MUX7", "SWR_MIC7", "TX WSA MUX7"}, + {"TX WSA MUX7", "NO_WSA", "TX PORT SEL MUX7"}, + {"TX WSA MUX7", "WSA1", "TX PORT SEL MUX7"}, + {"TX WSA MUX7", "WSA2", "TX PORT SEL MUX7"}, + {"TX WSA MUX7", "WSA3", "TX PORT SEL MUX7"}, + {"TX WSA MUX7", "WSA4", "TX PORT SEL MUX7"}, + {"TX PORT SEL MUX7", "PORT0", "TX SWR_INPUT"}, + {"TX PORT SEL MUX7", "PORT1", "TX SWR_INPUT"}, + {"TX PORT SEL MUX7", "PORT2", "TX SWR_INPUT"}, + {"TX PORT SEL MUX7", "PORT3", "TX SWR_INPUT"}, + {"TX PORT SEL MUX7", "PORT4", "TX SWR_INPUT"}, +}; + static const struct snd_kcontrol_new tx_macro_snd_controls[] =3D { SOC_SINGLE_S8_TLV("TX_DEC0 Volume", CDC_TX0_TX_VOL_CTL, @@ -2477,6 +2904,16 @@ static const struct tx_macro_data lpass_ver_11 =3D { .extra_routes_num =3D ARRAY_SIZE(tx_audio_map_v9_2), }; =20 +static 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recognise. Add LPASS_CODEC_VERSION_4_0 and its "v4.0" version string, and detect it in the VA macro when the hardware reports major version 4, minor 0. The RX macro register layout of LPASS codec v4.0 matches the v2.5+ layout, so reuse the existing v2.5 register access helpers, controls, widgets and register defaults for it. Unlike v4.1, v4.0 does not need the FS counter bypass or the adaptive filter blocks, so those stay keyed off v4.1 only. Add the "qcom,hawi-lpass-rx-macro" and "qcom,hawi-lpass-va-macro" compatibles, both pointing at the sm8550 match data, so the version is read back from the hardware at probe. Signed-off-by: Prasad Kumpatla Signed-off-by: Mohammad Rafi Shaik --- sound/soc/codecs/lpass-macro-common.h | 3 +++ sound/soc/codecs/lpass-rx-macro.c | 5 +++++ sound/soc/codecs/lpass-va-macro.c | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/sound/soc/codecs/lpass-macro-common.h b/sound/soc/codecs/lpass= -macro-common.h index 707b22a6bda6..a51a6012a7ec 100644 --- a/sound/soc/codecs/lpass-macro-common.h +++ b/sound/soc/codecs/lpass-macro-common.h @@ -31,6 +31,7 @@ enum lpass_codec_version { LPASS_CODEC_VERSION_2_7, LPASS_CODEC_VERSION_2_8, LPASS_CODEC_VERSION_2_9, + LPASS_CODEC_VERSION_4_0, LPASS_CODEC_VERSION_4_1, }; =20 @@ -72,6 +73,8 @@ static inline const char *lpass_macro_get_codec_version_s= tring(int version) return "v2.8"; case LPASS_CODEC_VERSION_2_9: return "v2.9"; + case LPASS_CODEC_VERSION_4_0: + return "v4.0"; case LPASS_CODEC_VERSION_4_1: return "v4.1"; default: diff --git a/sound/soc/codecs/lpass-rx-macro.c b/sound/soc/codecs/lpass-rx-= macro.c index 93ceee878b78..b7c1eff05ce6 100644 --- a/sound/soc/codecs/lpass-rx-macro.c +++ b/sound/soc/codecs/lpass-rx-macro.c @@ -1615,6 +1615,7 @@ static bool rx_is_rw_register(struct device *dev, uns= igned int reg) case LPASS_CODEC_VERSION_2_6: case LPASS_CODEC_VERSION_2_7: case LPASS_CODEC_VERSION_2_8: + case LPASS_CODEC_VERSION_4_0: case LPASS_CODEC_VERSION_4_1: return rx_2_5_is_rw_register(dev, reg); default: @@ -3660,6 +3661,7 @@ static int rx_macro_component_probe(struct snd_soc_co= mponent *component) case LPASS_CODEC_VERSION_2_6: case LPASS_CODEC_VERSION_2_7: case LPASS_CODEC_VERSION_2_8: + case LPASS_CODEC_VERSION_4_0: case LPASS_CODEC_VERSION_4_1: controls =3D rx_macro_2_5_snd_controls; num_controls =3D ARRAY_SIZE(rx_macro_2_5_snd_controls); @@ -3846,6 +3848,7 @@ static int rx_macro_probe(struct platform_device *pde= v) case LPASS_CODEC_VERSION_2_6: case LPASS_CODEC_VERSION_2_7: case LPASS_CODEC_VERSION_2_8: + case LPASS_CODEC_VERSION_4_0: case LPASS_CODEC_VERSION_4_1: rx->rxn_reg_stride =3D 0xc0; rx->rxn_reg_stride2 =3D 0x0; @@ -3959,6 +3962,8 @@ static const struct of_device_id rx_macro_dt_match[] = =3D { .data =3D (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK, }, { .compatible =3D "qcom,sm8550-lpass-rx-macro", + }, { + .compatible =3D "qcom,hawi-lpass-rx-macro", }, { .compatible =3D "qcom,sc8280xp-lpass-rx-macro", .data =3D (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK, diff --git a/sound/soc/codecs/lpass-va-macro.c b/sound/soc/codecs/lpass-va-= macro.c index 79abbdd158b7..46ae627ca594 100644 --- a/sound/soc/codecs/lpass-va-macro.c +++ b/sound/soc/codecs/lpass-va-macro.c @@ -1896,6 +1896,9 @@ static int va_macro_set_lpass_codec_version(struct va= _macro *va) } } else if (maj =3D=3D 4) { switch (min) { + case 0: + version =3D LPASS_CODEC_VERSION_4_0; + break; case 1: version =3D LPASS_CODEC_VERSION_4_1; break; @@ -2166,6 +2169,7 @@ static const struct of_device_id va_macro_dt_match[] = =3D { { .compatible =3D "qcom,sm8250-lpass-va-macro", .data =3D &sm8250_va_data= }, { .compatible =3D "qcom,sm8450-lpass-va-macro", .data =3D &sm8450_va_data= }, { .compatible =3D "qcom,sm8550-lpass-va-macro", .data =3D &sm8550_va_data= }, + { .compatible =3D "qcom,hawi-lpass-va-macro", .data =3D &sm8550_va_data }, { .compatible =3D "qcom,sc8280xp-lpass-va-macro", .data =3D &sm8450_va_da= ta }, { .compatible =3D "qcom,shikra-lpass-va-macro", .data =3D &shikra_va_data= }, {} --=20 2.34.1