From nobody Thu Sep 24 18:43:55 2026 Received: from mout-p-102.mailbox.org (mout-p-102.mailbox.org [80.241.56.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E8B8442139; Mon, 21 Sep 2026 20:28:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.152 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790022521; cv=none; b=KisgF414/Xx6fTD/F2+dDq+P1xT6/dcWUBWzyrIxDMPuD6PiGeTw4Dshir1gFwRoyO+VFy83HiBIuhhRx4LlYCY1l8JZSVS1kbq2cW4SDVhri0vIAgkSLZ3/0GTW+mdR7BAnw4O5lVZMCzmoy5etaNG8zmBHY3ZwWG2etpPXtyw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790022521; c=relaxed/simple; bh=+JqVKvxLKf/GFd72xLlGoGvsFIwW3ePXA+r1R0W9KcI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pa+BN8hEl9KIAw2KxkcwpSKBJZkjxKx3WG9B+n16ZIwdX9zm9CfDNESl/hxNMgNHz6vQFqajkKTmAL4g1O0MiuzuJ+RhATRLTvapozHu4I59IzXBT3l/4AOHFdE1cPyIU/drNshcznkhfBVXQdwlF7DfDiYhGmp/nhZWNlrwBT0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org; spf=pass smtp.mailfrom=mailbox.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=Nqkelfz4; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=aAGoDHTQ; arc=none smtp.client-ip=80.241.56.152 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mailbox.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="Nqkelfz4"; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="aAGoDHTQ" Received: from smtp102.mailbox.org (smtp102.mailbox.org [10.196.197.102]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-102.mailbox.org (Postfix) with ESMTPS id 4hpZYx4KGWzKp24; Mon, 21 Sep 2026 22:28:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1790022517; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ceA6mK483bKMAa122cXPY0QbjibJDrrII+F8biDCyfA=; b=Nqkelfz4vovobeQPCo429v+nbRJosAH9T3UTC9HyZKBFfV/W3w8jRCxg4pbGsPQ+nkRgRz EdxOC36NKVGwq5UizsfiABGEBSJ96Z4ihZg6pyLirkwPMOYbC30O6yIcSZh3fw7o2gLILb G7+aa1tWJ6HtkTG2joObBWZFbnCV2C6Au3RQ1ilneAkL+B74pRSGgQvpexLrY85nqBx32H ijarvNRCU+V6NUFRCa1qsjC8DqnI/BwpjQ+nia5DdkQBEi5gnK66iuWUWTENdWhPi5Whyg pjCjh+YyCDvnXiDtinwtyxwObIhrTXx0F8hIPjfDThAopoMmUFCfN3MuT6j7oQ== From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1790022515; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ceA6mK483bKMAa122cXPY0QbjibJDrrII+F8biDCyfA=; b=aAGoDHTQ9CXIjGHZyvzVG4Jinqpdbg9bfQLscOBq09By9NBNg5z3RKCW/AFXmg7miupgIz lNmhN4vmdO1nEqgo0Wk+rvA12tlPIqKI7rvFIlnnYpNUwYoVsyuq3ao3MrT2PxAo68R09W zzKQFrYcEvdY2hVgzjkga9L8ObqTcQL362lgvliothILdp7FYFwkjthy3Knx2VeyWCn70E 0IoiJoPGXMx2C/6PkJeaPDu3mywlclHsRmQ47EwdApDVA2H+TctiuRAsOG+fsLO/xviHU6 Ae+LiIbSuOX+rIdFWIBDXjhQ6ATM623OWLwfmosFLA9Na8getpp7gR//Wk/Qfg== To: linux-pci@vger.kernel.org Cc: Marek Vasut , Krzysztof Kozlowski , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Lorenzo Pieralisi , Manivannan Sadhasivam , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v5 1/6] dt-bindings: PCI: rcar-gen4-pci-host: Add R-Car X5H PCIe4 compatible Date: Mon, 21 Sep 2026 22:27:43 +0200 Message-ID: <20260921202823.72620-2-marek.vasut+renesas@mailbox.org> In-Reply-To: <20260921202823.72620-1-marek.vasut+renesas@mailbox.org> References: <20260921202823.72620-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MBO-RS-ID: fd16c348a752c289b40 X-MBO-RS-META: jk7ohqq7mc5js46eezweopdk5dqw6dko Document bindings for R-Car X5H (R8A78000) PCIe4 host module. The binding document is deliberately using "renesas,rcar-gen5-pcie4" DT compatible string to discern R-Car X5H PCIe4 controller supported by this binding, from R-Car X5H PCIe6 controller which will use a separate binding. The R-Car X5H PCIe4 controller does no longer include PHY register range, the PHY is now a separate IP and referenced via the 'phy' DT property. The 'reg' and 'reg-names' DT properties therefore differ between R-Car Gen4 PCIe and R-Car X5H PCIe4, and the difference is handled in the allOf section. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczy=C5=84ski" Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Lorenzo Pieralisi Cc: Manivannan Sadhasivam Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: Add RB from Krzysztof V3: No change V4: Rebase on next-20260904 V5: No change --- .../bindings/pci/rcar-gen4-pci-host.yaml | 74 +++++++++++++------ 1 file changed, 52 insertions(+), 22 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml = b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml index 64f456c6a75a1..9767a52f3904e 100644 --- a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml @@ -10,30 +10,20 @@ title: Renesas R-Car Gen4 PCIe Host maintainers: - Yoshihiro Shimoda =20 -allOf: - - $ref: snps,dw-pcie.yaml# - properties: compatible: - items: - - enum: - - renesas,r8a779f0-pcie # R-Car S4-8 - - renesas,r8a779g0-pcie # R-Car V4H - - renesas,r8a779h0-pcie # R-Car V4M - - const: renesas,rcar-gen4-pcie # R-Car Gen4 - - reg: - maxItems: 7 - - reg-names: - items: - - const: dbi - - const: dbi2 - - const: atu - - const: dma - - const: app - - const: phy - - const: config + oneOf: + - items: + - enum: + - renesas,r8a779f0-pcie # R-Car S4-8 + - renesas,r8a779g0-pcie # R-Car V4H + - renesas,r8a779h0-pcie # R-Car V4M + - const: renesas,rcar-gen4-pcie # R-Car Gen4 + + - items: + - enum: + - renesas,r8a78000-pcie4 # R-Car X5H PCIe4 + - const: renesas,rcar-gen5-pcie4 # R-Car Gen5 PCIe4 =20 interrupts: maxItems: 4 @@ -84,6 +74,46 @@ required: - resets - reset-names =20 +allOf: + - $ref: snps,dw-pcie.yaml# + - if: + properties: + compatible: + contains: + const: renesas,rcar-gen4-pcie + then: + properties: + reg: + maxItems: 7 + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: atu + - const: dma + - const: app + - const: phy + - const: config + - if: + properties: + compatible: + contains: + const: renesas,rcar-gen5-pcie4 + then: + properties: + reg: + maxItems: 6 + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: atu + - const: dma + - const: app + - const: config + unevaluatedProperties: false =20 examples: --=20 2.53.0 From nobody Thu Sep 24 18:43:55 2026 Received: from mout-p-103.mailbox.org (mout-p-103.mailbox.org [80.241.56.161]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08C62443ABC; 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h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=C6fKxRgnNxcw2W0jJNPuWEGwLL+Q4+J+8SS/wCBjkbA=; b=RZNsGSINK0zrASFMeaYqQgUkVWijphmZJcSDNQscrq1ouEYXxrA1KaaEdcz1I4RS4wZ7aF 89Bs3NCQ4EApYElQhJ5zOg/eWBpLu6boJXzO22+6WnSxfxl+DHmwY1peSWeglhtBir5nqP WuqdYi5h+/zY29moqJY30SG9n65F52gFuYQddQkS+P+Fvc5gtsEuB27FmVz/ZzmQ5OjGhf 6KpseYHO+wOYSG1ZGNAc/RiZZnB2s9PRU4SiKSoxzq4Bt7GB0IM7OIWEj4+BvaMd8gaFMU zGJ6zwY4Jdv5gBrTnN2foDRbZViX+npT/zKU24iXQDfhY8IZl5QYyhjd3Y4CfA== From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1790022519; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=C6fKxRgnNxcw2W0jJNPuWEGwLL+Q4+J+8SS/wCBjkbA=; b=buSPNDX/Zx2c35SV8yL1QBxcKtjlNiwNP5a43EntUuafo1UEULEDGBwqOE6xg/++CfYbTb eC3MHqCX4A63JFNOGn0/Jygv6NbO4E6LRwZCWRSrzTZVjLIPouKj79TtkVGzaFa3wImru0 gld9GofKL1FrBrzA6uFI7LdIYU9wUD+edOsNHWuSY9uw/yAlL9+oGLZX6nMq0X3pBvmbCE c3dlfQZ4DWFXeFkauULU3hdQ6ikaAPO/8T1H+anfxeoyUY742aXP1jVu23K1CVcuT1PC7w JTXk04OdIhZnVyOyW9jC/ism/OohmD4/uVgnDwvXBIqVm6j18y8AVNK50uYUDw== To: linux-pci@vger.kernel.org Cc: Marek Vasut , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Lorenzo Pieralisi , Manivannan Sadhasivam , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v5 2/6] PCI: dwc: rcar-gen4: Rework rcar_gen4_pcie_drvdata .additional_common_init into .init Date: Mon, 21 Sep 2026 22:27:44 +0200 Message-ID: <20260921202823.72620-3-marek.vasut+renesas@mailbox.org> In-Reply-To: <20260921202823.72620-1-marek.vasut+renesas@mailbox.org> References: <20260921202823.72620-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MBO-RS-ID: 412f7a5c403a8386a79 X-MBO-RS-META: cb6xnry8oy6unth61b85cm3kfm98jf1x Rework the current complicated initialization callchain that invokes host_init->common_init->additional_common_init() for host and ep_init->common_init->additional_common_init() for endpoint into simpler host_init->init() and ep_init->init() . The init callback is now always implmented for all R-Car Gen4 SoCs, therefore there is no need to check whether the callback is not NULL. For R-Car S4 the .init callback is rcar_gen4_pcie_common_init(), for R-Car V4H and V4M the .init callback is implemented using a new function rcar_gen4_v4h_v4m_pcie_init() which calls the common rcar_gen4_pcie_common_init() followed by R-Car V4H and V4M specific hardware initialization. The hardware initialization sequence remains unchanged. Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczy=C5=84ski" Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Lorenzo Pieralisi Cc: Manivannan Sadhasivam Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: Rename additional_common_init to init, reworked from previous patch PCI: dwc: rcar-gen4: Return error code from .additional_common_init V3: No change V4: Rebase on next-20260904 V5: No change --- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 56 ++++++++++++--------- 1 file changed, 32 insertions(+), 24 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/cont= roller/dwc/pcie-rcar-gen4.c index 5a076aa3f4904..a19ebbab2f8c3 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -87,7 +87,7 @@ MODULE_FIRMWARE(RCAR_GEN4_PCIE_FIRMWARE_NAME); =20 struct rcar_gen4_pcie; struct rcar_gen4_pcie_drvdata { - void (*additional_common_init)(struct rcar_gen4_pcie *rcar); + int (*init)(struct rcar_gen4_pcie *rcar); int (*ltssm_control)(struct rcar_gen4_pcie *rcar, bool enable); enum dw_pcie_device_mode mode; }; @@ -241,9 +241,6 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_= pcie *rcar) reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc); fsleep(1000); =20 - if (rcar->drvdata->additional_common_init) - rcar->drvdata->additional_common_init(rcar); - return 0; =20 err_unprepare: @@ -252,6 +249,31 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4= _pcie *rcar) return ret; } =20 +static int rcar_gen4_v4h_v4m_pcie_init(struct rcar_gen4_pcie *rcar) +{ + struct dw_pcie *dw =3D &rcar->dw; + u32 val; + int ret; + + /* R-Car Gen4 common initialization. */ + ret =3D rcar_gen4_pcie_common_init(rcar); + if (ret) + return ret; + + /* R-Car V4H and V4M specific additional initialization. */ + val =3D dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW); + val &=3D ~PORT_LANE_SKEW_INSERT_MASK; + if (dw->num_lanes < 4) + val |=3D BIT(6); + dw_pcie_writel_dbi(dw, PCIE_PORT_LANE_SKEW, val); + + val =3D readl(rcar->base + PCIEPWRMNGCTRL); + val |=3D APP_CLK_REQ_N | APP_CLK_PM_EN; + writel(val, rcar->base + PCIEPWRMNGCTRL); + + return 0; +} + static void rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie *rcar) { struct dw_pcie *dw =3D &rcar->dw; @@ -474,7 +496,7 @@ static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *= pp) =20 gpiod_set_value_cansleep(dw->pe_rst, 1); =20 - ret =3D rcar_gen4_pcie_common_init(rcar); + ret =3D rcar->drvdata->init(rcar); if (ret) return ret; =20 @@ -543,7 +565,7 @@ static int rcar_gen4_pcie_ep_pre_init(struct dw_pcie_ep= *ep) =20 writel(0, rcar->base + PCIEDMAINTSTSEN); =20 - ret =3D rcar_gen4_pcie_common_init(rcar); + ret =3D rcar->drvdata->init(rcar); if (ret) return ret; =20 @@ -739,22 +761,6 @@ static int r8a779f0_pcie_ltssm_control(struct rcar_gen= 4_pcie *rcar, bool enable) return 0; } =20 -static void rcar_gen4_pcie_additional_common_init(struct rcar_gen4_pcie *r= car) -{ - struct dw_pcie *dw =3D &rcar->dw; - u32 val; - - val =3D dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW); - val &=3D ~PORT_LANE_SKEW_INSERT_MASK; - if (dw->num_lanes < 4) - val |=3D BIT(6); - dw_pcie_writel_dbi(dw, PCIE_PORT_LANE_SKEW, val); - - val =3D readl(rcar->base + PCIEPWRMNGCTRL); - val |=3D APP_CLK_REQ_N | APP_CLK_PM_EN; - writel(val, rcar->base + PCIEPWRMNGCTRL); -} - static void rcar_gen4_pcie_phy_reg_update_bits(struct rcar_gen4_pcie *rcar, u32 offset, u32 mask, u32 val) { @@ -906,23 +912,25 @@ static int rcar_gen4_pcie_ltssm_control(struct rcar_g= en4_pcie *rcar, bool enable } =20 static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie =3D { + .init =3D rcar_gen4_pcie_common_init, .ltssm_control =3D r8a779f0_pcie_ltssm_control, .mode =3D DW_PCIE_RC_TYPE, }; =20 static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie_ep =3D { + .init =3D rcar_gen4_pcie_common_init, .ltssm_control =3D r8a779f0_pcie_ltssm_control, .mode =3D DW_PCIE_EP_TYPE, }; =20 static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie =3D { - .additional_common_init =3D rcar_gen4_pcie_additional_common_init, + .init =3D rcar_gen4_v4h_v4m_pcie_init, .ltssm_control =3D rcar_gen4_pcie_ltssm_control, .mode =3D DW_PCIE_RC_TYPE, }; =20 static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie_ep =3D { - .additional_common_init =3D rcar_gen4_pcie_additional_common_init, + .init =3D rcar_gen4_v4h_v4m_pcie_init, .ltssm_control =3D rcar_gen4_pcie_ltssm_control, .mode =3D DW_PCIE_EP_TYPE, }; --=20 2.53.0 From nobody Thu Sep 24 18:43:55 2026 Received: from mout-p-101.mailbox.org (mout-p-101.mailbox.org [80.241.56.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DA5F441022; Mon, 21 Sep 2026 20:28:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.151 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790022528; cv=none; b=t16SgTAtAcBvnx+6B/D69aDCPcg1fWrHgWU8lFg7Jx1Qklq+PPt1YKWMaJbNgkunEnRdbGGiDfEehgk6wd2BR1Xil+Qvz+YAYgKqd9309JnIFW1foh1m3Pa2BdPUeRVqVl8IvmRmZVp7wGX7nOZTn3QRbQkZ97U5t1hwMLYa++M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="cielqIQ6" Received: from smtp102.mailbox.org (smtp102.mailbox.org [10.196.197.102]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-101.mailbox.org (Postfix) with ESMTPS id 4hpZZ407P2z8tcC; Mon, 21 Sep 2026 22:28:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1790022524; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Qy7vZHH1+7XkDNOHgWs6VdP38RbGsa3jTFiOU8vhUxw=; b=NP8k+XDSjr+C6G8wucJAYa2QlIh1mptudDxcS/P55w9MTM4O7agv6MXbaWn+fzDE/j3/f6 kmah4lsTgLOVmBM2KMUlEXUlG9jbbrv/XgiovgPDMmqPRH3Ik16dxg2AjeYva3dQ/XlNeX xoRw7jju7hPAW8qWcYuYSUnfl1lgVDuh1driJEHgkK+RmogMqU6X2WVyQ0bnOERe9gKjW2 Cg9xRCPRQXWW5IrbAczqMKp3VHpYyJUgpcxuoULJnu3fzUHevgEV7VfxpHUHLXnBqHzMji F+msKS9bDlzGAypgFfVb66HiTOvAEK766CSe/HVCq7VPPbvQo8PpnIAIWOti8g== From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1790022522; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Qy7vZHH1+7XkDNOHgWs6VdP38RbGsa3jTFiOU8vhUxw=; b=cielqIQ6FXcX9e9dRkkrPPaKl/J/u95hGT+NokQRj3j5MWy6Vq0ZGMovPiPV36+LzE7SQe yvOItBRQVOqM+39WDTaJbQsPrxIBD67cHcbA+WndN+0aYIAIp2MACN0l2EmhR+ATRd9wHa y/BFSXsYWHDRYuSpbQFqvx/6pE65w8/xpOd2P0PgMM5A4O2xWZF3QEs7gmKhrQIqCswsyV RMVY4r5Vl5cIGfFg0Txj2EQL23vyKbRyLmlUQBqBrdm5INJGhetJC4khFhP9Es+BfAV5HF QpMHrmSAr5/XMp/mQQyYRQOAatt5ahyeTDcEsOtanNVX3ByF1HcXFsXWicQLgA== To: linux-pci@vger.kernel.org Cc: Marek Vasut , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Lorenzo Pieralisi , Manivannan Sadhasivam , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v5 3/6] PCI: dwc: rcar-gen4: Add .deinit callback Date: Mon, 21 Sep 2026 22:27:45 +0200 Message-ID: <20260921202823.72620-4-marek.vasut+renesas@mailbox.org> In-Reply-To: <20260921202823.72620-1-marek.vasut+renesas@mailbox.org> References: <20260921202823.72620-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MBO-RS-ID: 8660a7c8be3e74b2fdd X-MBO-RS-META: igkiijsoqt5rroca9haazyzodn1whizz Add .deinit callback in preparation for R-Car Gen5 support. The .deinit callback will be used to tear down the PHY on R-Car Gen5. Thus far, it does what rcar_gen4_pcie_common_deinit() used to do directly. Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczy=C5=84ski" Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Lorenzo Pieralisi Cc: Manivannan Sadhasivam Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V3: New patch V4: Rebase on next-20260904 V5: No change --- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/cont= roller/dwc/pcie-rcar-gen4.c index a19ebbab2f8c3..04871ac11c348 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -88,6 +88,7 @@ MODULE_FIRMWARE(RCAR_GEN4_PCIE_FIRMWARE_NAME); struct rcar_gen4_pcie; struct rcar_gen4_pcie_drvdata { int (*init)(struct rcar_gen4_pcie *rcar); + void (*deinit)(struct rcar_gen4_pcie *rcar); int (*ltssm_control)(struct rcar_gen4_pcie *rcar, bool enable); enum dw_pcie_device_mode mode; }; @@ -520,7 +521,7 @@ static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *= pp) return 0; =20 err: - rcar_gen4_pcie_common_deinit(rcar); + rcar->drvdata->deinit(rcar); return ret; } =20 @@ -530,7 +531,7 @@ static void rcar_gen4_pcie_host_deinit(struct dw_pcie_r= p *pp) struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); =20 gpiod_set_value_cansleep(dw->pe_rst, 1); - rcar_gen4_pcie_common_deinit(rcar); + rcar->drvdata->deinit(rcar); } =20 static const struct dw_pcie_host_ops rcar_gen4_pcie_host_ops =3D { @@ -580,7 +581,7 @@ static void rcar_gen4_pcie_ep_post_deinit(struct dw_pci= e_ep *ep) struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); =20 writel(0, rcar->base + PCIEDMAINTSTSEN); - rcar_gen4_pcie_common_deinit(rcar); + rcar->drvdata->deinit(rcar); } =20 static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, @@ -913,24 +914,28 @@ static int rcar_gen4_pcie_ltssm_control(struct rcar_g= en4_pcie *rcar, bool enable =20 static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie =3D { .init =3D rcar_gen4_pcie_common_init, + .deinit =3D rcar_gen4_pcie_common_deinit, .ltssm_control =3D r8a779f0_pcie_ltssm_control, .mode =3D DW_PCIE_RC_TYPE, }; =20 static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie_ep =3D { .init =3D rcar_gen4_pcie_common_init, + .deinit =3D rcar_gen4_pcie_common_deinit, .ltssm_control =3D r8a779f0_pcie_ltssm_control, .mode =3D DW_PCIE_EP_TYPE, }; =20 static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie =3D { .init =3D rcar_gen4_v4h_v4m_pcie_init, + .deinit =3D rcar_gen4_pcie_common_deinit, .ltssm_control =3D rcar_gen4_pcie_ltssm_control, .mode =3D DW_PCIE_RC_TYPE, }; =20 static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie_ep =3D { .init =3D rcar_gen4_v4h_v4m_pcie_init, + .deinit =3D rcar_gen4_pcie_common_deinit, .ltssm_control =3D rcar_gen4_pcie_ltssm_control, .mode =3D DW_PCIE_EP_TYPE, }; --=20 2.53.0 From nobody Thu Sep 24 18:43:55 2026 Received: from mout-p-101.mailbox.org (mout-p-101.mailbox.org [80.241.56.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03721441600; Mon, 21 Sep 2026 20:28:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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bh=A87Z7T1Dz9zhLDGnRE7Zqhy/TF7eJojsOyBuIgO8RjQ=; b=aygeOC++roJpylHvj/PKS+PshAfuE43hGATWyVN3BS/ZniHWM9ZWsQ1SIzmGFIGbBarohc 1FKDVfKd3JSKJK/6CzUYxbJhRgOkE0c6wjDMfTe+Gdeoytl0m9ZqdqxYZ6xwn6Dc9VauF8 aDTKW81+A50IxAVq3As6b0FH9DJ0po6lWgqMB7mFNwedmy+yZZ0ZjjrCFJpOROjqQ6difU 9MdjusWmbl41OYyMPlk2nnH2k1fZASCuDptjBptnSB8CGFa0knZ7NjWd4lJtkfznX4GSs8 CrXrYNWniXQU6vCnKHLYOoIGKY7NYp78e6ELCH94Q8CsxlX8Ucj86bcR6lyQqQ== From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1790022525; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=A87Z7T1Dz9zhLDGnRE7Zqhy/TF7eJojsOyBuIgO8RjQ=; b=EtsFTY7Pbfnpv3grDWbFs1XOoFy76qGWWrAgOCJ8i2OhxQeMQyASm31oUfrmv7q6qzdEOX 6XV3qGwR7mDhWh22YyTbqDCp7Dj0jYIFgViLkHNITejJWMC3NwB74LPzk6pZWbSEBrlBbc wM3wOIymK7R6jt4UaQU5yxM/JlADZSXgLuYG+asA72vJp/mGj7H862ETJm2JJD/Z39uXnt OakpYUFevTZny2qTxJRbmS4TGYdl/FK/COqM7Q0JIbSWzgoIiuAJQrQFPZlsaGuf3HwekN lugImo0LQc/2l08XNpAnxWEydT5n4uTLbHIkCl8iDU/yzquUc+E6wACM7rF/2g== To: linux-pci@vger.kernel.org Cc: Marek Vasut , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Lorenzo Pieralisi , Manivannan Sadhasivam , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v5 4/6] PCI: dwc: rcar-gen4: Split .start_link into ltssm_control and speed_control Date: Mon, 21 Sep 2026 22:27:46 +0200 Message-ID: <20260921202823.72620-5-marek.vasut+renesas@mailbox.org> In-Reply-To: <20260921202823.72620-1-marek.vasut+renesas@mailbox.org> References: <20260921202823.72620-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MBO-RS-ID: a098deee36f747c98c8 X-MBO-RS-META: u8zngxeiz8ad9y87u54n9ngqnon41pit Introduce new .speed_control callback and implement it on R-Car Gen4. The callback implements the second half of what is currently present in rcar_gen4_pcie_start_link(), and rcar_gen4_pcie_start_link() does call the .speed_control callback. This is a preparatory patch for R-Car Gen5 support, where the .speed_control implementation is different. Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczy=C5=84ski" Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Lorenzo Pieralisi Cc: Manivannan Sadhasivam Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: No change V3: No change V4: Rebase on next-20260904 V5: No change --- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 39 ++++++++++++++------- 1 file changed, 26 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/cont= roller/dwc/pcie-rcar-gen4.c index 04871ac11c348..c768a9c7b3b76 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -90,6 +90,7 @@ struct rcar_gen4_pcie_drvdata { int (*init)(struct rcar_gen4_pcie *rcar); void (*deinit)(struct rcar_gen4_pcie *rcar); int (*ltssm_control)(struct rcar_gen4_pcie *rcar, bool enable); + int (*speed_control)(struct rcar_gen4_pcie *rcar); enum dw_pcie_device_mode mode; }; =20 @@ -141,20 +142,10 @@ static int rcar_gen4_pcie_speed_change(struct dw_pcie= *dw) return -ETIMEDOUT; } =20 -/* - * Enable LTSSM of this controller and manually initiate the speed change. - * Always return 0. - */ -static int rcar_gen4_pcie_start_link(struct dw_pcie *dw) +static int rcar_gen4_pcie_speed_control(struct rcar_gen4_pcie *rcar) { - struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); - int i, changes, ret; - - if (rcar->drvdata->ltssm_control) { - ret =3D rcar->drvdata->ltssm_control(rcar, true); - if (ret) - return ret; - } + struct dw_pcie *dw =3D &rcar->dw; + int i, changes; =20 /* * Require direct speed change with retrying here if the max_link_speed @@ -178,6 +169,24 @@ static int rcar_gen4_pcie_start_link(struct dw_pcie *d= w) return 0; } =20 +/* + * Enable LTSSM of this controller and manually initiate the speed change. + * Always return 0. + */ +static int rcar_gen4_pcie_start_link(struct dw_pcie *dw) +{ + struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); + int ret; + + if (rcar->drvdata->ltssm_control) { + ret =3D rcar->drvdata->ltssm_control(rcar, true); + if (ret) + return ret; + } + + return rcar->drvdata->speed_control(rcar); +} + static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw) { struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); @@ -916,6 +925,7 @@ static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_p= cie =3D { .init =3D rcar_gen4_pcie_common_init, .deinit =3D rcar_gen4_pcie_common_deinit, .ltssm_control =3D r8a779f0_pcie_ltssm_control, + .speed_control =3D rcar_gen4_pcie_speed_control, .mode =3D DW_PCIE_RC_TYPE, }; =20 @@ -923,6 +933,7 @@ static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_p= cie_ep =3D { .init =3D rcar_gen4_pcie_common_init, .deinit =3D rcar_gen4_pcie_common_deinit, .ltssm_control =3D r8a779f0_pcie_ltssm_control, + .speed_control =3D rcar_gen4_pcie_speed_control, .mode =3D DW_PCIE_EP_TYPE, }; =20 @@ -930,6 +941,7 @@ static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_= pcie =3D { .init =3D rcar_gen4_v4h_v4m_pcie_init, .deinit =3D rcar_gen4_pcie_common_deinit, .ltssm_control =3D rcar_gen4_pcie_ltssm_control, + .speed_control =3D rcar_gen4_pcie_speed_control, .mode =3D DW_PCIE_RC_TYPE, }; =20 @@ -937,6 +949,7 @@ static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_= pcie_ep =3D { .init =3D rcar_gen4_v4h_v4m_pcie_init, .deinit =3D rcar_gen4_pcie_common_deinit, .ltssm_control =3D rcar_gen4_pcie_ltssm_control, + .speed_control =3D rcar_gen4_pcie_speed_control, .mode =3D DW_PCIE_EP_TYPE, }; =20 --=20 2.53.0 From nobody Thu Sep 24 18:43:55 2026 Received: from mout-p-101.mailbox.org (mout-p-101.mailbox.org [80.241.56.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4ED9D43E083; Mon, 21 Sep 2026 20:28:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.151 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790022534; cv=none; b=Ztphhepm/DmY2cOHDV3XIsPJms72kQtmzoJvWHLnVhoaD8MAmTATjbWhmjcjP0lkXVOb1hyU35Mz9KPAHRMNAifj3K15e/3nwGHcZ7fzOTcgo+nOvhVxrmP5oRGvYDq7xUcNtXWcL+6XQBQoB8BTXyscUbra4O79XQz/Bqtp4IY= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MBO-RS-META: pa3p4r5xuo49khe3dkchriqt5gzfs3dp X-MBO-RS-ID: 617eae1b13ac2019f2a Handle PERST via both GPIO and reset subsystem. On R-Car Gen4, the PERST signal is operated as a GPIO, on R-Car Gen5 it might only be accessible via SCMI reset via reset subsystem. Support both options. This is a preparatory patch for R-Car Gen5 support. Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczy=C5=84ski" Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Lorenzo Pieralisi Cc: Manivannan Sadhasivam Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: - Use dev_err_probe() for perst in rcar_gen4_pcie_get_resources() - Use of_get_next_available_child() to obtain root port OF node - Switch to of_reset_control_get_optional_exclusive() to deal with R-Car Gen4, where the PERST is handled as GPIO instead of reset - Rename rcar_gen4_pcie_host_perst() to rcar_gen4_pcie_host_perst_asser= t() and use bool type for assert and deassert selection - Add missing reset_control_put() into rcar_gen4_pcie_probe() fail path V3: - Handle controllers without root port DT node - Swap fail path order V4: Rebase on next-20260904 V5: Use either GPIO or reset perst --- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 41 +++++++++++++++++++-- 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/cont= roller/dwc/pcie-rcar-gen4.c index c768a9c7b3b76..cf1f5de451820 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -99,6 +99,7 @@ struct rcar_gen4_pcie { void __iomem *base; void __iomem *phy_base; struct platform_device *pdev; + struct reset_control *perst; const struct rcar_gen4_pcie_drvdata *drvdata; }; #define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw) @@ -317,12 +318,25 @@ static void rcar_gen4_pcie_unprepare(struct rcar_gen4= _pcie *rcar) =20 static int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar) { + struct device *dev =3D rcar->dw.dev; + struct device_node *root_port; + rcar->phy_base =3D devm_platform_ioremap_resource_byname(rcar->pdev, "phy= "); if (IS_ERR(rcar->phy_base)) return PTR_ERR(rcar->phy_base); =20 + root_port =3D of_get_next_available_child(dev->of_node, NULL); + if (root_port) { + rcar->perst =3D of_reset_control_get_optional_exclusive(root_port, "pers= t"); + of_node_put(root_port); + if (IS_ERR(rcar->perst)) + return dev_err_probe(dev, PTR_ERR(rcar->perst), "Failed to get PERST#\n= "); + } + /* Renesas-specific registers */ rcar->base =3D devm_platform_ioremap_resource_byname(rcar->pdev, "app"); + if (IS_ERR(rcar->base)) + reset_control_put(rcar->perst); =20 return PTR_ERR_OR_ZERO(rcar->base); } @@ -494,6 +508,21 @@ static int rcar_gen4_pcie_enable_device(struct pci_hos= t_bridge *bridge, return 0; } =20 +static void rcar_gen4_pcie_host_perst_assert(struct dw_pcie_rp *pp, bool a= ssert) +{ + struct dw_pcie *dw =3D to_dw_pcie_from_pp(pp); + struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); + + if (dw->pe_rst) { + gpiod_set_value_cansleep(dw->pe_rst, assert); + } else { + if (assert) + reset_control_assert(rcar->perst); + else + reset_control_deassert(rcar->perst); + } +} + /* Host mode */ static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp) { @@ -504,7 +533,7 @@ static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *= pp) if (pp->bridge) pp->bridge->enable_device =3D rcar_gen4_pcie_enable_device; =20 - gpiod_set_value_cansleep(dw->pe_rst, 1); + rcar_gen4_pcie_host_perst_assert(pp, true); =20 ret =3D rcar->drvdata->init(rcar); if (ret) @@ -525,7 +554,7 @@ static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *= pp) =20 msleep(PCIE_T_PVPERL_MS); /* pe_rst requires 100msec delay */ =20 - gpiod_set_value_cansleep(dw->pe_rst, 0); + rcar_gen4_pcie_host_perst_assert(pp, false); =20 return 0; =20 @@ -539,7 +568,7 @@ static void rcar_gen4_pcie_host_deinit(struct dw_pcie_r= p *pp) struct dw_pcie *dw =3D to_dw_pcie_from_pp(pp); struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); =20 - gpiod_set_value_cansleep(dw->pe_rst, 1); + rcar_gen4_pcie_host_perst_assert(pp, true); rcar->drvdata->deinit(rcar); } =20 @@ -713,7 +742,7 @@ static int rcar_gen4_pcie_probe(struct platform_device = *pdev) =20 err =3D rcar_gen4_pcie_prepare(rcar); if (err) - return err; + goto err_prepare; =20 err =3D rcar_gen4_add_dw_pcie(rcar); if (err) @@ -724,6 +753,9 @@ static int rcar_gen4_pcie_probe(struct platform_device = *pdev) err_unprepare: rcar_gen4_pcie_unprepare(rcar); =20 +err_prepare: + reset_control_put(rcar->perst); + return err; } =20 @@ -747,6 +779,7 @@ static void rcar_gen4_pcie_remove(struct platform_devic= e *pdev) =20 rcar_gen4_remove_dw_pcie(rcar); rcar_gen4_pcie_unprepare(rcar); + reset_control_put(rcar->perst); } =20 static int r8a779f0_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool e= nable) --=20 2.53.0 From nobody Thu Sep 24 18:43:55 2026 Received: from mout-p-102.mailbox.org (mout-p-102.mailbox.org [80.241.56.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 048FC443C23; Mon, 21 Sep 2026 20:28:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.152 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790022538; cv=none; b=JwkJ3iNCesSWMBAQmegPEF6yR5oGmLLJLDzFcOXIyYI/LfZv1CABn8OROzpGKtjsFK3cqzeWm8+CqEFfuhoMGmU/2aWa9GNecCL3Jvh4Svz5jNTh2qIyzVXu7ESVRKJBn5HLCX96h3rZqrBca2seHR9koJKnlLGcNe1z+x8/lJs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790022538; c=relaxed/simple; bh=gflCJYehwqRA2ONqpVrAYerTW4zcVLODVRSBQYyOT5k=; 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bh=H9jgSPHv8HYMEeDUiEhBHigmhwQiWCWhHOYIrM3SqNQ=; b=viiQTDk/eTWGA3AOXekypEJiCw2DcTDK/zpxofv7MPJPZxyHDOGQefA/6fz0FC2XseM4ZK Vvcqp7x3LxLzTww3AU4dTfp8irxZd7op8FSp625jKd3IVYkzJhXGW4dZ5n3M+4rZctSnR/ de56NVSrlWH1+2t/GCFrOxwCSqWsHiPGi72n7BkP6fGkqzL3uwFBSnHc6uniToBFRwZI0m 124RQpQKZbuB45qj+TduInjq9n9poNFzl3Pzm8jxnA9vBh/x+n35AYeaVAAww5GS/9XuGV AQ8P9N3i7EqV3oNdZjfaFuvT3PaFSBkqiAjdCt9wUEpDnJdgfpivW303Y/wXzQ== To: linux-pci@vger.kernel.org Cc: Marek Vasut , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Lorenzo Pieralisi , Manivannan Sadhasivam , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v5 6/6] PCI: dwc: rcar-gen4: Add support for R-Car X5H PCIe4 Date: Mon, 21 Sep 2026 22:27:48 +0200 Message-ID: <20260921202823.72620-7-marek.vasut+renesas@mailbox.org> In-Reply-To: <20260921202823.72620-1-marek.vasut+renesas@mailbox.org> References: <20260921202823.72620-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MBO-RS-META: 4wd3aag7bo6b76xzysxrrkeysfqn8b6i X-MBO-RS-ID: 10001d16929ce4a3789 Add support for R8A78000 (R-Car X5H) PCIe4. This driver previously supported R-Car Gen4 S4/V4H/V4M. PCIe features of R-Car X5H PCIe4 are almost all the same. The controller initialization sequence is slightly different and is factored out into controller specific callbacks, in a manner similar to previous R-Car Gen4 handling. The controller does have a PHY attached to it, but the PHY is operated by a separate PHY driver, the PHY driver instance binding is handled in rcar_gen4_pcie_get_resources() and controlled in the aforementioned controller specific callbacks. The controller driver is deliberately using "renesas,rcar-gen5-pcie4" DT compatible string to discern R-Car X5H PCIe4 controller supported by this driver, from R-Car X5H PCIe6 controller which will most likely use a separate driver. The R-Car X5H PCIe4 controller embeds HDMA instead of EDMA embedded in the R-Car Gen4 PCIe controller, "dw-edma" driver supports both DMA variants. Endpoint mode is currently not implemented for R-Car Gen5 PCIe4. Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczy=C5=84ski" Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Lorenzo Pieralisi Cc: Manivannan Sadhasivam Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: No change V3: - Disable clock in case of PHY init failure in rcar_gen5_pcie_init() - Add .deinit callback and tear down Gen5 PHY in it - Use 16bit accessors on LNKCTL register V4: Rebase on next-20260904 V5: Use read_poll_timeout() with 500ms timeout for the controller link up d= etection --- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 120 +++++++++++++++++++- 1 file changed, 118 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/cont= roller/dwc/pcie-rcar-gen4.c index cf1f5de451820..0b7ae4a693085 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -36,6 +37,7 @@ =20 /* MSI Capability */ #define MSICAP0 0x0050 +#define MSICAP0_MMESCAP_MASK GENMASK(19, 17) #define MSICAP0_MSIE BIT(16) =20 /* PCIe Interrupt Status 0 */ @@ -74,6 +76,11 @@ #define PCIEPWRMNGCTRL 0x0070 #define APP_CLK_REQ_N BIT(11) #define APP_CLK_PM_EN BIT(10) +#define APP_READY_ENTR_L23 BIT(6) +#define APP_REQ_ENTR_L1 BIT(5) + +/* PCI Express capability */ +#define EXPCAP(x) (0x0070 + (x)) =20 #define RCAR_NUM_SPEED_CHANGE_RETRIES 10 #define RCAR_MAX_LINK_SPEED 4 @@ -98,6 +105,7 @@ struct rcar_gen4_pcie { struct dw_pcie dw; void __iomem *base; void __iomem *phy_base; + struct phy *phy; struct platform_device *pdev; struct reset_control *perst; const struct rcar_gen4_pcie_drvdata *drvdata; @@ -170,6 +178,27 @@ static int rcar_gen4_pcie_speed_control(struct rcar_ge= n4_pcie *rcar) return 0; } =20 +static int rcar_gen5_pcie_speed_control(struct rcar_gen4_pcie *rcar) +{ + struct dw_pcie *dw =3D &rcar->dw; + u32 lnkcap =3D dw_pcie_readl_dbi(dw, EXPCAP(PCI_EXP_LNKCAP)); + u32 lnksta =3D dw_pcie_readw_dbi(dw, EXPCAP(PCI_EXP_LNKSTA)); + u32 val; + + if ((lnksta & PCI_EXP_LNKSTA_CLS) =3D=3D (lnkcap & PCI_EXP_LNKCAP_SLS)) + return 0; + + /* Retrain link */ + val =3D dw_pcie_readw_dbi(dw, EXPCAP(PCI_EXP_LNKCTL)); + val |=3D PCI_EXP_LNKCTL_RL; + dw_pcie_writew_dbi(dw, EXPCAP(PCI_EXP_LNKCTL), val); + + /* Wait for link retrain, 500ms must be enough for all link rates. */ + return read_poll_timeout(dw_pcie_readw_dbi, lnksta, !(lnksta & PCI_EXP_LN= KSTA_LT), + 1000, 5 * PCIE_RESET_CONFIG_WAIT_MS * USEC_PER_MSEC, + false, dw, EXPCAP(PCI_EXP_LNKSTA)); +} + /* * Enable LTSSM of this controller and manually initiate the speed change. * Always return 0. @@ -285,6 +314,49 @@ static int rcar_gen4_v4h_v4m_pcie_init(struct rcar_gen= 4_pcie *rcar) return 0; } =20 +static int rcar_gen5_pcie_init(struct rcar_gen4_pcie *rcar) +{ + struct dw_pcie *dw =3D &rcar->dw; + int ret; + u32 val; + + /* R-Car Gen4 and Gen5 common initialization. */ + ret =3D rcar_gen4_pcie_common_init(rcar); + if (ret) + return ret; + + /* R-Car Gen5 specific additional initialization. */ + ret =3D phy_init(rcar->phy); + if (ret) + goto err_unprepare; + + dw_pcie_dbi_ro_wr_en(dw); + + val =3D dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW); + val &=3D ~PORT_LANE_SKEW_INSERT_MASK; + if (dw->num_lanes < 8) + val |=3D BIT(6); + dw_pcie_writel_dbi(dw, PCIE_PORT_LANE_SKEW, val); + + val =3D dw_pcie_readl_dbi(dw, MSICAP0); + FIELD_MODIFY(MSICAP0_MMESCAP_MASK, &val, 4); + dw_pcie_writel_dbi(dw, MSICAP0, val); + + dw_pcie_dbi_ro_wr_dis(dw); + + val =3D readl(rcar->base + PCIEPWRMNGCTRL); + val |=3D APP_CLK_REQ_N | APP_CLK_PM_EN | + APP_READY_ENTR_L23 | APP_REQ_ENTR_L1; + writel(val, rcar->base + PCIEPWRMNGCTRL); + + return 0; + +err_unprepare: + clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks); + + return ret; +} + static void rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie *rcar) { struct dw_pcie *dw =3D &rcar->dw; @@ -293,6 +365,12 @@ static void rcar_gen4_pcie_common_deinit(struct rcar_g= en4_pcie *rcar) clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks); } =20 +static void rcar_gen5_pcie_deinit(struct rcar_gen4_pcie *rcar) +{ + phy_exit(rcar->phy); + rcar_gen4_pcie_common_deinit(rcar); +} + static int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar) { struct device *dev =3D rcar->dw.dev; @@ -322,8 +400,12 @@ static int rcar_gen4_pcie_get_resources(struct rcar_ge= n4_pcie *rcar) struct device_node *root_port; =20 rcar->phy_base =3D devm_platform_ioremap_resource_byname(rcar->pdev, "phy= "); - if (IS_ERR(rcar->phy_base)) - return PTR_ERR(rcar->phy_base); + if (IS_ERR(rcar->phy_base)) { + rcar->phy_base =3D NULL; + rcar->phy =3D devm_phy_get(dev, NULL); + if (IS_ERR(rcar->phy)) + return PTR_ERR(rcar->phy); + } =20 root_port =3D of_get_next_available_child(dev->of_node, NULL); if (root_port) { @@ -804,6 +886,28 @@ static int r8a779f0_pcie_ltssm_control(struct rcar_gen= 4_pcie *rcar, bool enable) return 0; } =20 +static int rcar_gen5_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool = enable) +{ + u32 val; + + val =3D readl(rcar->base + PCIERSTCTRL1); + if (enable) { + val |=3D APP_LTSSM_ENABLE; + val &=3D ~APP_HOLD_PHY_RST; + } else { + val &=3D ~APP_LTSSM_ENABLE; + val |=3D APP_HOLD_PHY_RST; + } + writel(val, rcar->base + PCIERSTCTRL1); + + if (enable) + phy_power_on(rcar->phy); + else + phy_power_off(rcar->phy); + + return 0; +} + static void rcar_gen4_pcie_phy_reg_update_bits(struct rcar_gen4_pcie *rcar, u32 offset, u32 mask, u32 val) { @@ -986,6 +1090,14 @@ static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen= 4_pcie_ep =3D { .mode =3D DW_PCIE_EP_TYPE, }; =20 +static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen5_pcie =3D { + .init =3D rcar_gen5_pcie_init, + .deinit =3D rcar_gen5_pcie_deinit, + .ltssm_control =3D rcar_gen5_pcie_ltssm_control, + .speed_control =3D rcar_gen5_pcie_speed_control, + .mode =3D DW_PCIE_RC_TYPE, +}; + static const struct of_device_id rcar_gen4_pcie_of_match[] =3D { { .compatible =3D "renesas,r8a779f0-pcie", @@ -1003,6 +1115,10 @@ static const struct of_device_id rcar_gen4_pcie_of_m= atch[] =3D { .compatible =3D "renesas,rcar-gen4-pcie-ep", .data =3D &drvdata_rcar_gen4_pcie_ep, }, + { + .compatible =3D "renesas,rcar-gen5-pcie4", + .data =3D &drvdata_rcar_gen5_pcie, + }, {}, }; MODULE_DEVICE_TABLE(of, rcar_gen4_pcie_of_match); --=20 2.53.0