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AKwUvBzArCyctfF3Vuvg5AkutmKH0X1Sg2F5rElV+cdZNopZFXhK6ODweFOFHTqEvKMbUC6CqU4AClibKzVEz2k=@vger.kernel.org X-Gm-Message-State: AFuF++lUj+mdcxwlqhfCdj5UQnGMw9NIgD0Jl9zlKHob/AiSkpw8GKKQ nvrHstD9c0FVXMlyuv7unlP1Cw/Q6nXrJzFFtvcvgeFYKfqPkNOTbesd3GGWEXoV5r8owhveT8Y b6iC1rg== X-Received: from pgdj21.prod.google.com ([2002:a05:6a02:5215:b0:cc7:4a9d:af5f]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a21:140a:b0:3dd:a196:69ec with SMTP id adf61e73a8af0-3dda1967806mr11525924637.71.1790018061422; Mon, 21 Sep 2026 12:14:21 -0700 (PDT) Reply-To: Sean Christopherson Date: Mon, 21 Sep 2026 12:14:09 -0700 In-Reply-To: <20260921191418.950933-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260921191418.950933-1-seanjc@google.com> X-Mailer: git-send-email 2.55.0.1082.g2b9226bbc0-goog Message-ID: <20260921191418.950933-2-seanjc@google.com> Subject: [PATCH v4 01/10] perf/x86/intel: Ensure guest PEBS path doesn't set unwanted PERF_GLOBAL_CTRL bits From: Sean Christopherson To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Sean Christopherson , Paolo Bonzini Cc: Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Dapeng Mi , Jim Mattson , Mingwei Zhang , Stephane Eranian , Sashiko Bot Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When reinstating PEBS counters into PERF_GLOBAL_CTRL for a KVM guest, mask the value with perf's desired/original PERF_GLOBAL_CTRL value to ensure KVM doesn't unintentionally set reserved bits in PERF_GLOBAL_CTRL. E.g. if the guest's PEBS_ENABLE value had bit 63, "Enable Precise Store", set, then using the raw guest PEBS value would propagate bit 63 to the guest's PERF_GLOBAL_CTRL value (which thankfully would be a failed VM-Entry, not a VMX Abort). The only reason this bug isn't reachable is because KVM doesn't support "Enable Precise Store" (which is probably a KVM bug?), i.e. bit 63 can't be set in kvm_pmu->pebs_enable and thus not in arr[pebs_enable].guest. In other words, this _should_ be a glorified nop in the current code base. Fixes: c59a1f106f5c ("KVM: x86/pmu: Add IA32_PEBS_ENABLE MSR emulation for = extended PEBS") Reviewed-by: Dapeng Mi Signed-off-by: Sean Christopherson --- arch/x86/events/intel/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index e36f340e2dc2..f4674d93a5e2 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5392,7 +5392,7 @@ static struct perf_guest_switch_msr *intel_guest_get_= msrs(int *nr, void *data) arr[pebs_enable].guest &=3D ~kvm_pmu->host_cross_mapped_mask; arr[global_ctrl].guest &=3D ~kvm_pmu->host_cross_mapped_mask; /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */ - arr[global_ctrl].guest |=3D arr[pebs_enable].guest; + arr[global_ctrl].guest |=3D intel_ctrl & arr[pebs_enable].guest; } =20 return arr; --=20 2.55.0.1082.g2b9226bbc0-goog From nobody Thu Sep 24 18:40:17 2026 Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 948DD511E67 for ; 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Mon, 21 Sep 2026 12:14:22 -0700 (PDT) Reply-To: Sean Christopherson Date: Mon, 21 Sep 2026 12:14:10 -0700 In-Reply-To: <20260921191418.950933-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260921191418.950933-1-seanjc@google.com> X-Mailer: git-send-email 2.55.0.1082.g2b9226bbc0-goog Message-ID: <20260921191418.950933-3-seanjc@google.com> Subject: [PATCH v4 02/10] perf/x86/intel: Don't write PEBS_ENABLED on host<=>guest xfers if CPU has isolation From: Sean Christopherson To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Sean Christopherson , Paolo Bonzini Cc: Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Dapeng Mi , Jim Mattson , Mingwei Zhang , Stephane Eranian , Sashiko Bot Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When filling the list of MSRs to be loaded by KVM on VM-Enter and VM-Exit, *never* insert an entry for PEBS_ENABLED if the CPU properly isolates PEBS events, in which case disabling counters via PERF_GLOBAL_CTRL is sufficient to prevent unwanted PEBS events in the guest (or host). Because perf loads PEBS_ENABLE with the unfiltered cpu_hw_events.pebs_enabled, i.e. with both host and guest masks, there is no need to load different values for the guest versus host, perf+KVM can and should simply control which counters are enabled/disabled via PERF_GLOBAL_CTRL. Avoiding touching PEBS_ENABLED "fixes" a bug where PEBS_ENABLED can end up with "stuck" bits if a PEBS event is throttled between generating the list and actually entering the guest (Intel CPUs can't arbtitrarily block NMIs). Fixes in quotes because leaving PEBS_ENABLED as-is doesn't fix the underlying problem of perf (via PMIs) being able to modify state after the perf<=3D>KVM handoff. But not writing PEBS_ENABLED is desirable no matter what, as stating the obvious, leaving PEBS_ENABLED as-is avoids three MSR writes on every VMX transition: one each on entry/exit, and one more explicit WRMSR to zero PEBS_ENABLED before VM-Entry (KVM assumes the only reason PEBS_ENABLED is in the load list is if the CPU lacks isolation and thus needs a quiescent period). Opportunistically add comments to (better) explain the rules for generating the set of PEBS counters that will be active while the guest is running, along with a FIXME for the suspected hack-a-fix where perf disables guest PEBS if _any_ PEBS event is configured to count in the host (commit 854250329c02 ("KVM: x86/pmu: Disable guest PEBS temporarily in two rare situations") doesn't explain the motivation, at all). Fixes: c59a1f106f5c ("KVM: x86/pmu: Add IA32_PEBS_ENABLE MSR emulation for = extended PEBS") Cc: Jim Mattson Cc: Mingwei Zhang Cc: Stephane Eranian Reviewed-by: Dapeng Mi Signed-off-by: Sean Christopherson --- arch/x86/events/intel/core.c | 55 ++++++++++++++++++++++++------------ 1 file changed, 37 insertions(+), 18 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index f4674d93a5e2..3f8d4d037b4e 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5325,12 +5325,15 @@ static struct perf_guest_switch_msr *intel_guest_ge= t_msrs(int *nr, void *data) struct kvm_pmu *kvm_pmu =3D (struct kvm_pmu *)data; u64 intel_ctrl =3D hybrid(cpuc->pmu, intel_ctrl); u64 pebs_mask =3D cpuc->pebs_enabled & x86_pmu.pebs_capable; - int global_ctrl, pebs_enable; + u64 guest_pebs_mask; + int global_ctrl; =20 /* * In addition to obeying exclude_guest/exclude_host, remove bits being * used for PEBS when running a guest, because PEBS writes to virtual - * addresses (not physical addresses). + * addresses (not physical addresses). If the guest wants to utilize + * PEBS, and PEBS can safely enabled in the guest, bits for the guest's + * PEBS-enabled counters will be OR'd back in as appropriate. */ *nr =3D 0; global_ctrl =3D (*nr)++; @@ -5377,24 +5380,40 @@ static struct perf_guest_switch_msr *intel_guest_ge= t_msrs(int *nr, void *data) }; } =20 - pebs_enable =3D (*nr)++; - arr[pebs_enable] =3D (struct perf_guest_switch_msr){ - .msr =3D MSR_IA32_PEBS_ENABLE, - .host =3D cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask, - .guest =3D pebs_mask & ~cpuc->intel_ctrl_host_mask & kvm_pmu->pebs_enabl= e, - }; + /* + * Restrict guest PEBS events to counters that (a) perf supports, (b) + * the guest wants to use for PEBS, (c) are not excluded from counting + * in the guest, and (d) _are_ excluded from counting in the host. + */ + guest_pebs_mask =3D pebs_mask & intel_ctrl & kvm_pmu->pebs_enable & + ~cpuc->intel_ctrl_host_mask & + cpuc->intel_ctrl_guest_mask; =20 - if (arr[pebs_enable].host) { - /* Disable guest PEBS if host PEBS is enabled. */ - arr[pebs_enable].guest =3D 0; - } else { - /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */ - arr[pebs_enable].guest &=3D ~kvm_pmu->host_cross_mapped_mask; - arr[global_ctrl].guest &=3D ~kvm_pmu->host_cross_mapped_mask; - /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */ - arr[global_ctrl].guest |=3D intel_ctrl & arr[pebs_enable].guest; - } + /* + * Disable counters where the guest PMC is different than the host PMC + * being used on behalf of the guest, as the PEBS record includes + * PERF_GLOBAL_STATUS, i.e. the guest will see overflow status for the + * wrong counter(s). + */ + guest_pebs_mask &=3D ~kvm_pmu->host_cross_mapped_mask; =20 + /* + * FIXME: Allow guest and host usage of PEBS events to co-exist instead + * of disabling guest PEBS entirely if the host is using PEBS. + * What exactly goes wrong if guest and host are using PEBS is + * unknown. + */ + if (pebs_mask & ~cpuc->intel_ctrl_guest_mask) + guest_pebs_mask =3D 0; + + /* + * Do NOT mess with PEBS_ENABLED. As above, disabling counters via + * PERF_GLOBAL_CTRL is sufficient, and loading a stale PEBS_ENABLED, + * e.g. on VM-Exit, can put the system in a bad state. Simply enable + * counters in PERF_GLOBAL_CTRL, as perf load PEBS_ENABLED with the + * full value, i.e. perf *also* relies on PERF_GLOBAL_CTRL. + */ + arr[global_ctrl].guest |=3D guest_pebs_mask; return arr; } =20 --=20 2.55.0.1082.g2b9226bbc0-goog From nobody Thu Sep 24 18:40:17 2026 Received: from mail-pg1-f200.google.com (mail-pg1-f200.google.com [209.85.215.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE762511E7E for ; Mon, 21 Sep 2026 19:14:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.200 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790018066; cv=none; b=BTBm9GwDxlIot0x+IHtaNGsfjAtGhjBH1KKp46agItJcp7afqt7vMsmaAZzoQzCy4spFVOImMwfLo+ifzSjOb4yLToC9KJn1ICZPApolfcdYSDg8ACQm5cylplAmae448vxhTkXod6w7vSz230hvEZuJ7j1YD/X11++Kq0mbJd4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" When filling the list of MSRs to be loaded by KVM on VM-Enter and VM-Exit, load the guest values for DS_AREA and (conditionally) MSR_PEBS_DATA_CFG if and only if PEBS will be active in the guest, i.e. only if a PEBS record may be generated while running the guest. As shown by the !pebs_ept path, it's perfectly safe to run with the host's DS_AREA, so long as PEBS-enabled counters are disabled via PERF_GLOBAL_CTRL. Omitting DS_AREA and MSR_PEBS_DATA_CFG when PEBS is unused saves two MSR writes per MSR on each VMX transition, i.e. eliminates two/four pointless MSR writes on each VMX roundtrip when PEBS isn't being used by the guest. Fixes: c59a1f106f5c ("KVM: x86/pmu: Add IA32_PEBS_ENABLE MSR emulation for = extended PEBS") Cc: Jim Mattson Cc: Mingwei Zhang Cc: Stephane Eranian Reviewed-by: Jim Mattson Reviewed-by: Dapeng Mi Signed-off-by: Sean Christopherson --- arch/x86/events/intel/core.c | 39 +++++++++++++++++++++++------------- 1 file changed, 25 insertions(+), 14 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 3f8d4d037b4e..4905296d99a4 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5363,23 +5363,14 @@ static struct perf_guest_switch_msr *intel_guest_ge= t_msrs(int *nr, void *data) return arr; } =20 + /* + * If the guest won't use PEBS or the CPU doesn't support PEBS in the + * guest, then there's nothing more to do as disabling PMCs via + * PERF_GLOBAL_CTRL is sufficient on CPUs with guest/host isolation. + */ if (!kvm_pmu || !x86_pmu.pebs_ept) return arr; =20 - arr[(*nr)++] =3D (struct perf_guest_switch_msr){ - .msr =3D MSR_IA32_DS_AREA, - .host =3D (unsigned long)cpuc->ds, - .guest =3D kvm_pmu->ds_area, - }; - - if (x86_pmu.intel_cap.pebs_baseline) { - arr[(*nr)++] =3D (struct perf_guest_switch_msr){ - .msr =3D MSR_PEBS_DATA_CFG, - .host =3D cpuc->active_pebs_data_cfg, - .guest =3D kvm_pmu->pebs_data_cfg, - }; - } - /* * Restrict guest PEBS events to counters that (a) perf supports, (b) * the guest wants to use for PEBS, (c) are not excluded from counting @@ -5406,6 +5397,26 @@ static struct perf_guest_switch_msr *intel_guest_get= _msrs(int *nr, void *data) if (pebs_mask & ~cpuc->intel_ctrl_guest_mask) guest_pebs_mask =3D 0; =20 + /* + * Context switch DS_AREA and PEBS_DATA_CFG if and only if PEBS will be + * active in the guest; if no records will be generated while the guest + * is running, then simply keep the host values resident in hardware. + */ + arr[(*nr)++] =3D (struct perf_guest_switch_msr){ + .msr =3D MSR_IA32_DS_AREA, + .host =3D (unsigned long)cpuc->ds, + .guest =3D guest_pebs_mask ? kvm_pmu->ds_area : (unsigned long)cpuc->ds, + }; + + if (x86_pmu.intel_cap.pebs_baseline) { + arr[(*nr)++] =3D (struct perf_guest_switch_msr){ + .msr =3D MSR_PEBS_DATA_CFG, + .host =3D cpuc->active_pebs_data_cfg, + .guest =3D guest_pebs_mask ? kvm_pmu->pebs_data_cfg : + cpuc->active_pebs_data_cfg, + }; + } + /* * Do NOT mess with PEBS_ENABLED. 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charset="utf-8" Drop "support" for passing a NULL @data/@kvm_pmu param when getting guest MSRs. KVM, the only in-tree user, unconditionally passes a non-NULL pointer, and carrying code that suggests @data may be NULL is confusing, e.g. incorrectly implies that there are scenarios where KVM doesn't pass a PMU context. Fixes: 8183a538cd95 ("KVM: x86/pmu: Add IA32_DS_AREA MSR emulation to suppo= rt guest DS") Cc: Jim Mattson Cc: Mingwei Zhang Cc: Stephane Eranian Reviewed-by: Jim Mattson Reviewed-by: Dapeng Mi Signed-off-by: Sean Christopherson --- arch/x86/events/intel/core.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 4905296d99a4..0db55d90c3ca 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5364,11 +5364,11 @@ static struct perf_guest_switch_msr *intel_guest_ge= t_msrs(int *nr, void *data) } =20 /* - * If the guest won't use PEBS or the CPU doesn't support PEBS in the - * guest, then there's nothing more to do as disabling PMCs via - * PERF_GLOBAL_CTRL is sufficient on CPUs with guest/host isolation. + * If the CPU doesn't support PEBS in the guest, then there's nothing + * more to do as disabling PMCs via PERF_GLOBAL_CTRL is sufficient on + * CPUs with guest/host isolation. */ - if (!kvm_pmu || !x86_pmu.pebs_ept) + if (!x86_pmu.pebs_ept) return arr; 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AKwUvByD6L8HHAoppi72EQwgUAjL3wjnPJ40FyVksv97oygXfyJqi+uikn+FW5uQ/EZPughHpfU4Tre0LU7u4Xk=@vger.kernel.org X-Gm-Message-State: AFuF++kAw9VrtWvAmJGpiFUomJrl7KMXLW5o4YzcZ74xlyrg0owpUspN IF0hZvwowDs0FXd2CX7CZJibWMSCdg+3Co9lnyWBjGQ0Z7wRQfl0lZqXlHhgc+LUGvB7s0HugkB qkzVgUA== X-Received: from pgdj29.prod.google.com ([2002:a05:6a02:521d:b0:cc4:b575:5b04]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:ad08:b0:874:705d:f652 with SMTP id d2e1a72fcca58-874dea02e76mr15115482b3a.32.1790018066169; Mon, 21 Sep 2026 12:14:26 -0700 (PDT) Reply-To: Sean Christopherson Date: Mon, 21 Sep 2026 12:14:13 -0700 In-Reply-To: <20260921191418.950933-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260921191418.950933-1-seanjc@google.com> X-Mailer: git-send-email 2.55.0.1082.g2b9226bbc0-goog Message-ID: <20260921191418.950933-6-seanjc@google.com> Subject: [PATCH v4 05/10] perf/x86/intel: Invert names of intel_ctrl_{guest,host}_mask From: Sean Christopherson To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Sean Christopherson , Paolo Bonzini Cc: Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Dapeng Mi , Jim Mattson , Mingwei Zhang , Stephane Eranian , Sashiko Bot Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename intel_ctrl_{guest,host}_mask to intel_ctrl_exclude_{host,guest}_mask to more accurately capture what they actually track. Specifically, an event that is excluded from the guest is NOT guaranteed to count in the host, and vice versa, as it legal (albeit bizarre) to configure an event to exclude both the host and the guest, i.e. to not count at all. Subjectively (though anyone who disagrees is wrong), aligning with perf_event_attr.exclude_{guest,host} also makes all related code much easier to follow. No functional change intended. Suggested-by: Jim Mattson Reviewed-by: Dapeng Mi Signed-off-by: Sean Christopherson --- arch/x86/events/intel/core.c | 22 +++++++++++----------- arch/x86/events/intel/lbr.c | 2 +- arch/x86/events/perf_event.h | 4 ++-- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 0db55d90c3ca..859aba923a6a 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -2787,7 +2787,7 @@ static void __intel_pmu_enable_all(int added, bool pm= i) } =20 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, - intel_ctrl & ~cpuc->intel_ctrl_guest_mask); + intel_ctrl & ~cpuc->intel_ctrl_exclude_host_mask); =20 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { struct perf_event *event =3D @@ -2985,9 +2985,9 @@ static inline void intel_set_masks(struct perf_event = *event, int idx) struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); =20 if (event->attr.exclude_host) - __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); + __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_exclude_host_mask); if (event->attr.exclude_guest) - __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); + __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_exclude_guest_mask); if (event_is_checkpointed(event)) __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status); } @@ -2996,8 +2996,8 @@ static inline void intel_clear_masks(struct perf_even= t *event, int idx) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); =20 - __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); - __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); + __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_exclude_host_mask); + __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_exclude_guest_mask); __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status); } =20 @@ -3779,7 +3779,7 @@ static int x86_pmu_handle_guest_pebs(struct pt_regs *= regs, struct perf_sample_data *data) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); - u64 guest_pebs_idxs =3D cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask; + u64 guest_pebs_idxs =3D cpuc->pebs_enabled & ~cpuc->intel_ctrl_exclude_gu= est_mask; struct perf_event *event =3D NULL; int bit; =20 @@ -5339,8 +5339,8 @@ static struct perf_guest_switch_msr *intel_guest_get_= msrs(int *nr, void *data) global_ctrl =3D (*nr)++; arr[global_ctrl] =3D (struct perf_guest_switch_msr){ .msr =3D MSR_CORE_PERF_GLOBAL_CTRL, - .host =3D intel_ctrl & ~cpuc->intel_ctrl_guest_mask, - .guest =3D intel_ctrl & ~cpuc->intel_ctrl_host_mask & ~pebs_mask, + .host =3D intel_ctrl & ~cpuc->intel_ctrl_exclude_host_mask, + .guest =3D intel_ctrl & ~cpuc->intel_ctrl_exclude_guest_mask & ~pebs_mas= k, }; =20 if (!x86_pmu.ds_pebs) @@ -5377,8 +5377,8 @@ static struct perf_guest_switch_msr *intel_guest_get_= msrs(int *nr, void *data) * in the guest, and (d) _are_ excluded from counting in the host. */ guest_pebs_mask =3D pebs_mask & intel_ctrl & kvm_pmu->pebs_enable & - ~cpuc->intel_ctrl_host_mask & - cpuc->intel_ctrl_guest_mask; + ~cpuc->intel_ctrl_exclude_guest_mask & + cpuc->intel_ctrl_exclude_host_mask; =20 /* * Disable counters where the guest PMC is different than the host PMC @@ -5394,7 +5394,7 @@ static struct perf_guest_switch_msr *intel_guest_get_= msrs(int *nr, void *data) * What exactly goes wrong if guest and host are using PEBS is * unknown. */ - if (pebs_mask & ~cpuc->intel_ctrl_guest_mask) + if (pebs_mask & ~cpuc->intel_ctrl_exclude_host_mask) guest_pebs_mask =3D 0; =20 /* diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index cbe5c762008d..710292cf3f9b 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -714,7 +714,7 @@ static inline bool vlbr_exclude_host(void) struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); =20 return test_bit(INTEL_PMC_IDX_FIXED_VLBR, - (unsigned long *)&cpuc->intel_ctrl_guest_mask); + (unsigned long *)&cpuc->intel_ctrl_exclude_host_mask); } =20 void intel_pmu_lbr_enable_all(bool pmi) diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 0bc2fe486070..87733dd52846 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -540,8 +540,8 @@ struct cpu_hw_events { /* * Intel host/guest exclude bits */ - u64 intel_ctrl_guest_mask; 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Mon, 21 Sep 2026 12:14:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1790018068; x=1790622868; darn=vger.kernel.org; h=content-type:cc:to:from:subject:message-id:references:mime-version :in-reply-to:date:reply-to:from:to:cc:subject:date:message-id :reply-to:content-type; bh=We/XQ6s6KSgxA61rBAufhIwuk9J/sx0XOSn2ewH01aA=; b=SZ9uxArJTesY+RQDcpIVr+oXTop+MK/K0YSReGJ42W3WKevKnI6n+ZQdHBQ0h+fIjN myfMHuDpCYuvN/xnJNrXcZf7V6aiZM2IRx3ZMTh+nnVfm3wkO0mPmMMrYvfg58zudSb9 DmpUAF3kC0mwaaSmGYWzE/fVQ0MKiAhp/nUgHh5YrxFukUhp8BegNSkJrLMWi3ANGL2l PuoczdAA3bWVuByvWCQDZfOIj19FOzTZCDfwfLZcG1RymEcbDRxR0gsDm7Pa4Y9K2KSA lay98l0t1cg6U1cbgKtzM9rieILGIE6nBmAJg2pCm0C0MkoR9uRwIpKsNjrEYhHNbFZL ottg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1790018068; x=1790622868; h=content-type:cc:to:from:subject:message-id:references:mime-version :in-reply-to:date:reply-to:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to:content-type; 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charset="utf-8" Have perf define a struct for getting guest PEBS data from KVM instead of poking into the kvm_pmu structure. Passing in an entire "struct kvm_pmu" _as an opaque pointer_ to get at four fields is silly, especially since one of the fields exists purely to convey information to perf, i.e. isn't used by KVM. Perf should also own its APIs, i.e. define what fields/data it needs, not rely on KVM to throw fields into data structures that effectively hold KVM-internal state. Opportunistically rephrase the comment about cross-mapped counters to explain *why* PEBS needs to be disabled. Reviewed-by: Dapeng Mi Reviewed-by: Jim Mattson Signed-off-by: Sean Christopherson --- arch/x86/events/core.c | 5 +++-- arch/x86/events/intel/core.c | 16 ++++++++-------- arch/x86/events/perf_event.h | 3 ++- arch/x86/include/asm/kvm_host.h | 9 --------- arch/x86/include/asm/perf_event.h | 12 ++++++++++-- arch/x86/kvm/vmx/pmu_intel.c | 17 ++++++++++++++--- arch/x86/kvm/vmx/vmx.c | 11 ++++++++--- arch/x86/kvm/vmx/vmx.h | 2 +- 8 files changed, 46 insertions(+), 29 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index ef9b8df2e1f7..9b1a9032e36d 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -862,9 +862,10 @@ void x86_pmu_disable_all(void) } } =20 -struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data) +struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, + struct x86_guest_pebs *guest_pebs) { - return static_call(x86_pmu_guest_get_msrs)(nr, data); + return static_call(x86_pmu_guest_get_msrs)(nr, guest_pebs); } EXPORT_SYMBOL_FOR_KVM(perf_guest_get_msrs); =20 diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 859aba923a6a..66cacfeb47d3 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -14,7 +14,6 @@ #include #include #include -#include =20 #include #include @@ -5318,11 +5317,11 @@ static int intel_pmu_hw_config(struct perf_event *e= vent) * when it uses {RD,WR}MSR, which should be handled by the KVM context, * specifically in the intel_pmu_{get,set}_msr(). */ -static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *d= ata) +static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, + struct x86_guest_pebs *guest_pebs) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); struct perf_guest_switch_msr *arr =3D cpuc->guest_switch_msrs; - struct kvm_pmu *kvm_pmu =3D (struct kvm_pmu *)data; u64 intel_ctrl =3D hybrid(cpuc->pmu, intel_ctrl); u64 pebs_mask =3D cpuc->pebs_enabled & x86_pmu.pebs_capable; u64 guest_pebs_mask; @@ -5376,7 +5375,7 @@ static struct perf_guest_switch_msr *intel_guest_get_= msrs(int *nr, void *data) * the guest wants to use for PEBS, (c) are not excluded from counting * in the guest, and (d) _are_ excluded from counting in the host. */ - guest_pebs_mask =3D pebs_mask & intel_ctrl & kvm_pmu->pebs_enable & + guest_pebs_mask =3D pebs_mask & intel_ctrl & guest_pebs->enable & ~cpuc->intel_ctrl_exclude_guest_mask & cpuc->intel_ctrl_exclude_host_mask; =20 @@ -5386,7 +5385,7 @@ static struct perf_guest_switch_msr *intel_guest_get_= msrs(int *nr, void *data) * PERF_GLOBAL_STATUS, i.e. the guest will see overflow status for the * wrong counter(s). */ - guest_pebs_mask &=3D ~kvm_pmu->host_cross_mapped_mask; + guest_pebs_mask &=3D ~guest_pebs->cross_mapped_mask; =20 /* * FIXME: Allow guest and host usage of PEBS events to co-exist instead @@ -5405,14 +5404,14 @@ static struct perf_guest_switch_msr *intel_guest_ge= t_msrs(int *nr, void *data) arr[(*nr)++] =3D (struct perf_guest_switch_msr){ .msr =3D MSR_IA32_DS_AREA, .host =3D (unsigned long)cpuc->ds, - .guest =3D guest_pebs_mask ? kvm_pmu->ds_area : (unsigned long)cpuc->ds, + .guest =3D guest_pebs_mask ? guest_pebs->ds_area : (unsigned long)cpuc->= ds, }; =20 if (x86_pmu.intel_cap.pebs_baseline) { arr[(*nr)++] =3D (struct perf_guest_switch_msr){ .msr =3D MSR_PEBS_DATA_CFG, .host =3D cpuc->active_pebs_data_cfg, - .guest =3D guest_pebs_mask ? kvm_pmu->pebs_data_cfg : + .guest =3D guest_pebs_mask ? guest_pebs->data_cfg : cpuc->active_pebs_data_cfg, }; } @@ -5428,7 +5427,8 @@ static struct perf_guest_switch_msr *intel_guest_get_= msrs(int *nr, void *data) return arr; } =20 -static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, void *da= ta) +static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, + struct x86_guest_pebs *guest_pebs) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); struct perf_guest_switch_msr *arr =3D cpuc->guest_switch_msrs; diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 87733dd52846..68ece64ff8cd 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -1230,7 +1230,8 @@ struct x86_pmu { /* * Intel host/guest support (KVM) */ - struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr, void *data); + struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr, + struct x86_guest_pebs *guest_pebs); =20 /* * Check period value for PERF_EVENT_IOC_PERIOD ioctl. diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 57d37491c7c0..20b9db3f5203 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -608,15 +608,6 @@ struct kvm_pmu { u64 pebs_data_cfg; u64 pebs_data_cfg_rsvd; =20 - /* - * If a guest counter is cross-mapped to host counter with different - * index, its PEBS capability will be temporarily disabled. - * - * The user should make sure that this mask is updated - * after disabling interrupts and before perf_guest_get_msrs(); - */ - u64 host_cross_mapped_mask; - /* * The gate to release perf_events not marked in * pmc_in_use only once in a vcpu time slice. diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 12f7db8c57b4..27f9c5bee7b0 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -819,11 +819,19 @@ extern void perf_load_guest_lvtpc(u32 guest_lvtpc); extern void perf_put_guest_lvtpc(void); #endif =20 +struct x86_guest_pebs { + u64 enable; + u64 ds_area; + u64 data_cfg; + u64 cross_mapped_mask; +}; #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL) -extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *da= ta); +extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, + struct x86_guest_pebs *guest_pebs); extern void x86_perf_get_lbr(struct x86_pmu_lbr *lbr); #else -struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data); +struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, + struct x86_guest_pebs *guest_pebs); static inline void x86_perf_get_lbr(struct x86_pmu_lbr *lbr) { memset(lbr, 0, sizeof(*lbr)); diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index bfa8612fb450..a21e146ad4f2 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -747,11 +747,21 @@ static void intel_pmu_cleanup(struct kvm_vcpu *vcpu) intel_pmu_release_guest_lbr_event(vcpu); } =20 -void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu) +u64 intel_pmu_get_cross_mapped_mask(struct kvm_pmu *pmu) { - struct kvm_pmc *pmc =3D NULL; + u64 host_cross_mapped_mask; + struct kvm_pmc *pmc; int bit, hw_idx; =20 + /* + * Provide a mask of counters that are cross-mapped between the guest + * and the host, i.e. where a guest PMC is mapped to a host PMC with a + * different index. PEBS records hold a PERF_GLOBAL_STATUS snapshot, + * and so PEBS-enabled counters need to hold the correct index so as + * not to confuse the guest. + */ + host_cross_mapped_mask =3D 0; + kvm_for_each_pmc(pmu, pmc, bit, (unsigned long *)&pmu->global_ctrl) { if (!pmc_is_locally_enabled(pmc) || !pmc_is_globally_enabled(pmc) || !pmc->perf_event) @@ -763,8 +773,9 @@ void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu) */ hw_idx =3D pmc->perf_event->hw.idx; if (hw_idx !=3D pmc->idx && hw_idx > -1) - pmu->host_cross_mapped_mask |=3D BIT_ULL(hw_idx); + host_cross_mapped_mask |=3D BIT_ULL(hw_idx); } + return host_cross_mapped_mask; } =20 static bool intel_pmu_is_mediated_pmu_supported(struct x86_pmu_capability = *host_pmu) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 612ab07d4100..b097db296792 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7363,12 +7363,17 @@ static void atomic_switch_perf_msrs(struct vcpu_vmx= *vmx) if (kvm_vcpu_has_mediated_pmu(&vmx->vcpu)) return; =20 - pmu->host_cross_mapped_mask =3D 0; + struct x86_guest_pebs guest_pebs =3D { + .enable =3D pmu->pebs_enable, + .ds_area =3D pmu->ds_area, + .data_cfg =3D pmu->pebs_data_cfg, + }; + if (pmu->pebs_enable & pmu->global_ctrl) - intel_pmu_cross_mapped_check(pmu); + guest_pebs.cross_mapped_mask =3D intel_pmu_get_cross_mapped_mask(pmu); =20 /* Note, nr_msrs may be garbage if perf_guest_get_msrs() returns NULL. */ - msrs =3D perf_guest_get_msrs(&nr_msrs, (void *)pmu); + msrs =3D perf_guest_get_msrs(&nr_msrs, &guest_pebs); if (!msrs) return; =20 diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index dc8517f15bc4..5c4e2cf6256c 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -664,7 +664,7 @@ static __always_inline struct vcpu_vmx *to_vmx(struct k= vm_vcpu *vcpu) return container_of(vcpu, struct vcpu_vmx, vcpu); } =20 -void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu); +u64 intel_pmu_get_cross_mapped_mask(struct kvm_pmu *pmu); int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu); 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charset="utf-8" Now that perf operates on a KVM-provided snapshot of PMU state, handled cross-mapped PEBS counters entirely in KVM by clearing unusable counters from the to-be-enabled mask instead of foisting the work on perf. No functional change intended. Reviewed-by: Dapeng Mi Signed-off-by: Sean Christopherson --- arch/x86/events/intel/core.c | 8 -------- arch/x86/include/asm/perf_event.h | 1 - arch/x86/kvm/vmx/vmx.c | 10 ++++++++-- 3 files changed, 8 insertions(+), 11 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 66cacfeb47d3..d9315bb2f221 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5379,14 +5379,6 @@ static struct perf_guest_switch_msr *intel_guest_get= _msrs(int *nr, ~cpuc->intel_ctrl_exclude_guest_mask & cpuc->intel_ctrl_exclude_host_mask; =20 - /* - * Disable counters where the guest PMC is different than the host PMC - * being used on behalf of the guest, as the PEBS record includes - * PERF_GLOBAL_STATUS, i.e. the guest will see overflow status for the - * wrong counter(s). - */ - guest_pebs_mask &=3D ~guest_pebs->cross_mapped_mask; - /* * FIXME: Allow guest and host usage of PEBS events to co-exist instead * of disabling guest PEBS entirely if the host is using PEBS. diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 27f9c5bee7b0..5c92d43bbef8 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -823,7 +823,6 @@ struct x86_guest_pebs { u64 enable; u64 ds_area; u64 data_cfg; - u64 cross_mapped_mask; }; #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL) extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index b097db296792..8f7d0620f44c 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7369,8 +7369,14 @@ static void atomic_switch_perf_msrs(struct vcpu_vmx = *vmx) .data_cfg =3D pmu->pebs_data_cfg, }; =20 - if (pmu->pebs_enable & pmu->global_ctrl) - guest_pebs.cross_mapped_mask =3D intel_pmu_get_cross_mapped_mask(pmu); + /* + * Disable counters where the guest PMC is different than the host PMC + * being used on behalf of the guest, as the PEBS record includes + * PERF_GLOBAL_STATUS, i.e. the guest will see overflow status for the + * wrong counter(s). + */ + if (guest_pebs.enable & pmu->global_ctrl) + guest_pebs.enable &=3D ~intel_pmu_get_cross_mapped_mask(pmu); =20 /* Note, nr_msrs may be garbage if perf_guest_get_msrs() returns NULL. */ msrs =3D perf_guest_get_msrs(&nr_msrs, &guest_pebs); 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charset="utf-8" Drop a redundant check that a PMC is globally enabled when looking for PEBS counters that are cross-mapped between the guest and the host. The for-loop explicitly iterates over pmu->global_ctrl, and since PEBS requires PMU v2+, kvm_pmu_has_perf_global_ctrl() must be true, and thus pmc_is_globally_enabled() is simply checking that the bit is set in pmu->global_ctrl. No functional change intended. Reviewed-by: Dapeng Mi Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/pmu_intel.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index a21e146ad4f2..040b8e80cf86 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -763,8 +763,7 @@ u64 intel_pmu_get_cross_mapped_mask(struct kvm_pmu *pmu) host_cross_mapped_mask =3D 0; =20 kvm_for_each_pmc(pmu, pmc, bit, (unsigned long *)&pmu->global_ctrl) { - if (!pmc_is_locally_enabled(pmc) || - !pmc_is_globally_enabled(pmc) || !pmc->perf_event) + if (!pmc_is_locally_enabled(pmc) || !pmc->perf_event) continue; =20 /* --=20 2.55.0.1082.g2b9226bbc0-goog From nobody Thu Sep 24 18:40:17 2026 Received: from mail-pf1-f199.google.com (mail-pf1-f199.google.com [209.85.210.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B36AB517BAF for ; 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Mon, 21 Sep 2026 12:14:30 -0700 (PDT) Reply-To: Sean Christopherson Date: Mon, 21 Sep 2026 12:14:17 -0700 In-Reply-To: <20260921191418.950933-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260921191418.950933-1-seanjc@google.com> X-Mailer: git-send-email 2.55.0.1082.g2b9226bbc0-goog Message-ID: <20260921191418.950933-10-seanjc@google.com> Subject: [PATCH v4 09/10] KVM: VMX: Only tell perf to enable PEBS counters for fully enabled PMCs From: Sean Christopherson To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Sean Christopherson , Paolo Bonzini Cc: Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Dapeng Mi , Jim Mattson , Mingwei Zhang , Stephane Eranian , Sashiko Bot Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When passing the guest's requested PEBS_ENABLE (or rather, KVM's version of PEBS_ENABLE on behalf of the guest), omit counters that are locally disable and/or don't have a perf event (due to contention), in addition to omitting counters that are cross-mapped in the host. In practice, this should be a nop as perf will already have disabled the associated counter, i.e. cpuc->pebs_enabled should have been cleared, but paranoia is cheap, and the existing code _looks_ wrong. Reviewed-by: Dapeng Mi Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/pmu_intel.c | 30 ++++++++++++++++-------------- arch/x86/kvm/vmx/vmx.c | 11 +---------- arch/x86/kvm/vmx/vmx.h | 15 ++++++++++++++- 3 files changed, 31 insertions(+), 25 deletions(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 040b8e80cf86..472cf51298b4 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -747,34 +747,36 @@ static void intel_pmu_cleanup(struct kvm_vcpu *vcpu) intel_pmu_release_guest_lbr_event(vcpu); } =20 -u64 intel_pmu_get_cross_mapped_mask(struct kvm_pmu *pmu) +u64 __intel_pmu_compute_pebs_enable(struct kvm_pmu *pmu) { - u64 host_cross_mapped_mask; + u64 guest_pebs_enable =3D pmu->pebs_enable & pmu->global_ctrl; + u64 pebs_enable =3D 0; struct kvm_pmc *pmc; int bit, hw_idx; =20 /* - * Provide a mask of counters that are cross-mapped between the guest - * and the host, i.e. where a guest PMC is mapped to a host PMC with a - * different index. PEBS records hold a PERF_GLOBAL_STATUS snapshot, - * and so PEBS-enabled counters need to hold the correct index so as - * not to confuse the guest. + * Omit counters that are locally disabled, don't have a perf event, or + * ended up with a perf event that is using a different counter than + * the guest, i.e. where the guest PMC is different than the host PMC + * being used on behalf of the guest. PEBS records include + * PERF_GLOBAL_STATUS, and so using a counter with a different index + * means the guest will see overflow status for the wrong counter(s). */ - host_cross_mapped_mask =3D 0; - - kvm_for_each_pmc(pmu, pmc, bit, (unsigned long *)&pmu->global_ctrl) { + kvm_for_each_pmc(pmu, pmc, bit, (unsigned long *)&guest_pebs_enable) { if (!pmc_is_locally_enabled(pmc) || !pmc->perf_event) continue; =20 /* - * A negative index indicates the event isn't mapped to a + * Note, a negative index indicates the event isn't mapped to a * physical counter in the host, e.g. due to contention. */ hw_idx =3D pmc->perf_event->hw.idx; - if (hw_idx !=3D pmc->idx && hw_idx > -1) - host_cross_mapped_mask |=3D BIT_ULL(hw_idx); + if (hw_idx !=3D pmc->idx) + continue; + + pebs_enable |=3D BIT_ULL(pmc->idx); } - return host_cross_mapped_mask; + return pebs_enable; } =20 static bool intel_pmu_is_mediated_pmu_supported(struct x86_pmu_capability = *host_pmu) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 8f7d0620f44c..2d0443562a16 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7364,20 +7364,11 @@ static void atomic_switch_perf_msrs(struct vcpu_vmx= *vmx) return; =20 struct x86_guest_pebs guest_pebs =3D { - .enable =3D pmu->pebs_enable, + .enable =3D intel_pmu_compute_pebs_enable(pmu), .ds_area =3D pmu->ds_area, .data_cfg =3D pmu->pebs_data_cfg, }; =20 - /* - * Disable counters where the guest PMC is different than the host PMC - * being used on behalf of the guest, as the PEBS record includes - * PERF_GLOBAL_STATUS, i.e. the guest will see overflow status for the - * wrong counter(s). - */ - if (guest_pebs.enable & pmu->global_ctrl) - guest_pebs.enable &=3D ~intel_pmu_get_cross_mapped_mask(pmu); - /* Note, nr_msrs may be garbage if perf_guest_get_msrs() returns NULL. */ msrs =3D perf_guest_get_msrs(&nr_msrs, &guest_pebs); if (!msrs) diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index 5c4e2cf6256c..1db461060c7e 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -664,7 +664,20 @@ static __always_inline struct vcpu_vmx *to_vmx(struct = kvm_vcpu *vcpu) return container_of(vcpu, struct vcpu_vmx, vcpu); } =20 -u64 intel_pmu_get_cross_mapped_mask(struct kvm_pmu *pmu); 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Mon, 21 Sep 2026 12:14:31 -0700 (PDT) Reply-To: Sean Christopherson Date: Mon, 21 Sep 2026 12:14:18 -0700 In-Reply-To: <20260921191418.950933-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260921191418.950933-1-seanjc@google.com> X-Mailer: git-send-email 2.55.0.1082.g2b9226bbc0-goog Message-ID: <20260921191418.950933-11-seanjc@google.com> Subject: [PATCH v4 10/10] perf/x86/intel: Check only PMC bits in PEBS_ENABLED when detecting host PEBS usage From: Sean Christopherson To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Sean Christopherson , Paolo Bonzini Cc: Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Dapeng Mi , Jim Mattson , Mingwei Zhang , Stephane Eranian , Sashiko Bot Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When checking to see if guest PEBS usage should be disabled due to host PEBS usage, filter out non-counter bits in PEBS_ENABLE to avoid getting false positives in the unlikely scenario that "Enable Precise Store" is enabled without PEBS actually being active for any PMCs. Note, the other "hidden" usage of pebs_mask is already explicitly masked with intel_ctrl: .guest =3D intel_ctrl & ~cpuc->intel_ctrl_exclude_guest_mask & ~pebs_mask, I.e. removing the non-counter bits from pebs_mask doesn't change the value that is loaded into arr[global_ctrl].guest. Fixes: 854250329c02 ("KVM: x86/pmu: Disable guest PEBS temporarily in two r= are situations") Suggested-by: Dapeng Mi Reported-by: Sashiko Bot Closes: https://lore.kernel.org/all/20260508234018.F06AEC2BCB0@smtp.kernel.= org Signed-off-by: Sean Christopherson --- arch/x86/events/intel/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index d9315bb2f221..1ff0586c7b71 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5323,7 +5323,7 @@ static struct perf_guest_switch_msr *intel_guest_get_= msrs(int *nr, struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); struct perf_guest_switch_msr *arr =3D cpuc->guest_switch_msrs; u64 intel_ctrl =3D hybrid(cpuc->pmu, intel_ctrl); - u64 pebs_mask =3D cpuc->pebs_enabled & x86_pmu.pebs_capable; + u64 pebs_mask =3D intel_ctrl & cpuc->pebs_enabled & x86_pmu.pebs_capable; u64 guest_pebs_mask; int global_ctrl; =20 @@ -5375,7 +5375,7 @@ static struct perf_guest_switch_msr *intel_guest_get_= msrs(int *nr, * the guest wants to use for PEBS, (c) are not excluded from counting * in the guest, and (d) _are_ excluded from counting in the host. */ - guest_pebs_mask =3D pebs_mask & intel_ctrl & guest_pebs->enable & + guest_pebs_mask =3D pebs_mask & guest_pebs->enable & ~cpuc->intel_ctrl_exclude_guest_mask & cpuc->intel_ctrl_exclude_host_mask; =20 --=20 2.55.0.1082.g2b9226bbc0-goog