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charset="utf-8" Update the top-level description to also explicitly mention vendor-prefixed header paths and what the asterisk wildcard represents. Signed-off-by: Ayman Chaudhry Reviewed-by: Geert Uytterhoeven --- v1->v2: - New patch .../devicetree/bindings/power/renesas,rcar-sysc.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml= b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml index b67aa170b2c1..68b4696d7c59 100644 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml @@ -13,8 +13,11 @@ maintainers: description: | The R-Car (RZ/G) System Controller provides power management for the CPU cores and various coprocessors. - The power domain IDs for consumers are defined in header files: - include/dt-bindings/power/r8*-sysc.h + The power domain IDs for consumers are defined in the below header files + (where the asterisk serves as a wildcard matching the specific SoC + identifier): + include/dt-bindings/power/r8*-sysc.h or + include/dt-bindings/power/renesas,r8*-sysc.h =20 properties: compatible: --=20 2.34.1 From nobody Thu Sep 24 18:43:34 2026 Received: from OS0P286CU011.outbound.protection.outlook.com (mail-japanwestazon11010064.outbound.protection.outlook.com [52.101.228.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2FC64A205D; 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Mon, 21 Sep 2026 22:45:05 +0900 (JST) From: Ayman Chaudhry To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Ayman Chaudhry , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Paterson , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 2/9] dt-bindings: power: Add r8a774a3 SYSC power domain definitions Date: Mon, 21 Sep 2026 13:44:22 +0000 Message-ID: <20260921134432.50338-3-ayman.chaudhry.kc@renesas.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260921134432.50338-1-ayman.chaudhry.kc@renesas.com> References: <20260921134432.50338-1-ayman.chaudhry.kc@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF00005622:EE_|OSZPR01MB7035:EE_ X-MS-Office365-Filtering-Correlation-Id: 2645ca26-67f5-402e-61c2-08df17e68d7f X-LD-Processed: 53d82571-da19-47e4-9cb4-625a166a4a2a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|23010399003|376014|82310400026|36860700016|10067099003|56012099006|11063799006|22082099003|18002099003; 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charset="utf-8" Add power domain indices for the Renesas RZ/G2M v3.0 (a.k.a. R8A774A3) SoC. Signed-off-by: Ayman Chaudhry Reviewed-by: Geert Uytterhoeven --- v1->v2: - Updated commit message - Renamed file to include vendor prefix - Added vendor prefix to include macros - Added Reviewed-by tag .../dt-bindings/power/renesas,r8a774a3-sysc.h | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 include/dt-bindings/power/renesas,r8a774a3-sysc.h diff --git a/include/dt-bindings/power/renesas,r8a774a3-sysc.h b/include/dt= -bindings/power/renesas,r8a774a3-sysc.h new file mode 100644 index 000000000000..ddee6812e9a4 --- /dev/null +++ b/include/dt-bindings/power/renesas,r8a774a3-sysc.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2026 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_RENESAS_R8A774A3_SYSC_H__ +#define __DT_BINDINGS_POWER_RENESAS_R8A774A3_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A774A3_PD_CA57_CPU0 0 +#define R8A774A3_PD_CA57_CPU1 1 +#define R8A774A3_PD_CA53_CPU0 5 +#define R8A774A3_PD_CA53_CPU1 6 +#define R8A774A3_PD_CA53_CPU2 7 +#define R8A774A3_PD_CA53_CPU3 8 +#define R8A774A3_PD_CA57_SCU 12 +#define R8A774A3_PD_A3VC 14 +#define R8A774A3_PD_3DG_A 17 +#define R8A774A3_PD_3DG_B 18 +#define R8A774A3_PD_CA53_SCU 21 +#define R8A774A3_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A774A3_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_RENESAS_R8A774A3_SYSC_H__ */ --=20 2.34.1 From nobody Thu Sep 24 18:43:34 2026 Received: from OS0P286CU011.outbound.protection.outlook.com (mail-japanwestazon11010028.outbound.protection.outlook.com [52.101.228.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C8DD4A1DF5; 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charset="utf-8" Add support for Renesas RZ/G2M v3.0 (a.k.a. R8A774A3) SoC power areas to the R-Car SYSC driver. The RZ/G2M v3.0 SYSC is similar to the RZ/G2M v1.3 SYSC, however it lacks the A2VC0 power area. Signed-off-by: Ayman Chaudhry Reviewed-by: Geert Uytterhoeven --- v1->v2: - Added space before closing brace for `ca57-cpu1` area - Updated include path to SYSC dt-bindings - Added Reviewed-by tag drivers/pmdomain/renesas/Kconfig | 4 +++ drivers/pmdomain/renesas/Makefile | 1 + drivers/pmdomain/renesas/r8a774a3-sysc.c | 45 ++++++++++++++++++++++++ drivers/pmdomain/renesas/rcar-sysc.c | 3 ++ drivers/pmdomain/renesas/rcar-sysc.h | 1 + 5 files changed, 54 insertions(+) create mode 100644 drivers/pmdomain/renesas/r8a774a3-sysc.c diff --git a/drivers/pmdomain/renesas/Kconfig b/drivers/pmdomain/renesas/Kc= onfig index f2f52d3c29a0..df19b95c4655 100644 --- a/drivers/pmdomain/renesas/Kconfig +++ b/drivers/pmdomain/renesas/Kconfig @@ -37,6 +37,10 @@ config SYSC_R8A774A1 bool "System Controller support for R8A774A1 (RZ/G2M)" if COMPILE_TEST select SYSC_RCAR =20 +config SYSC_R8A774A3 + bool "System Controller support for R8A774A3 (RZ/G2M v3.0)" if COMPILE_TE= ST + select SYSC_RCAR + config SYSC_R8A774B1 bool "System Controller support for R8A774B1 (RZ/G2N)" if COMPILE_TEST select SYSC_RCAR diff --git a/drivers/pmdomain/renesas/Makefile b/drivers/pmdomain/renesas/M= akefile index 17849aad37a5..8eda820478e4 100644 --- a/drivers/pmdomain/renesas/Makefile +++ b/drivers/pmdomain/renesas/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_SYSC_R8A7743) +=3D r8a7743-sysc.o obj-$(CONFIG_SYSC_R8A7745) +=3D r8a7745-sysc.o obj-$(CONFIG_SYSC_R8A77470) +=3D r8a77470-sysc.o obj-$(CONFIG_SYSC_R8A774A1) +=3D r8a774a1-sysc.o +obj-$(CONFIG_SYSC_R8A774A3) +=3D r8a774a3-sysc.o obj-$(CONFIG_SYSC_R8A774B1) +=3D r8a774b1-sysc.o obj-$(CONFIG_SYSC_R8A774C0) +=3D r8a774c0-sysc.o obj-$(CONFIG_SYSC_R8A774E1) +=3D r8a774e1-sysc.o diff --git a/drivers/pmdomain/renesas/r8a774a3-sysc.c b/drivers/pmdomain/re= nesas/r8a774a3-sysc.c new file mode 100644 index 000000000000..58c98700bd55 --- /dev/null +++ b/drivers/pmdomain/renesas/r8a774a3-sysc.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G2M v3.0 System Controller + * Copyright (C) 2026 Renesas Electronics Corp. + * + * Based on Renesas R-Car M3-W System Controller + * Copyright (C) 2016 Glider bvba + */ + +#include + +#include + +#include "rcar-sysc.h" + +static const struct rcar_sysc_area r8a774a3_areas[] __initconst =3D { + { "always-on", 0, 0, R8A774A3_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, + { "ca57-scu", 0x1c0, 0, R8A774A3_PD_CA57_SCU, R8A774A3_PD_ALWAYS_ON, + PD_SCU }, + { "ca57-cpu0", 0x80, 0, R8A774A3_PD_CA57_CPU0, R8A774A3_PD_CA57_SCU, + PD_CPU_NOCR }, + { "ca57-cpu1", 0x80, 1, R8A774A3_PD_CA57_CPU1, R8A774A3_PD_CA57_SCU, + PD_CPU_NOCR }, + { "ca53-scu", 0x140, 0, R8A774A3_PD_CA53_SCU, R8A774A3_PD_ALWAYS_ON, + PD_SCU }, + { "ca53-cpu0", 0x200, 0, R8A774A3_PD_CA53_CPU0, R8A774A3_PD_CA53_SCU, + PD_CPU_NOCR }, + { "ca53-cpu1", 0x200, 1, R8A774A3_PD_CA53_CPU1, R8A774A3_PD_CA53_SCU, + PD_CPU_NOCR }, + { "ca53-cpu2", 0x200, 2, R8A774A3_PD_CA53_CPU2, R8A774A3_PD_CA53_SCU, + PD_CPU_NOCR }, + { "ca53-cpu3", 0x200, 3, R8A774A3_PD_CA53_CPU3, R8A774A3_PD_CA53_SCU, + PD_CPU_NOCR }, + { "a3vc", 0x380, 0, R8A774A3_PD_A3VC, R8A774A3_PD_ALWAYS_ON }, + { "a2vc1", 0x3c0, 1, R8A774A3_PD_A2VC1, R8A774A3_PD_A3VC }, + { "3dg-a", 0x100, 0, R8A774A3_PD_3DG_A, R8A774A3_PD_ALWAYS_ON }, + { "3dg-b", 0x100, 1, R8A774A3_PD_3DG_B, R8A774A3_PD_3DG_A }, +}; + +const struct rcar_sysc_info r8a774a3_sysc_info __initconst =3D { + .areas =3D r8a774a3_areas, + .num_areas =3D ARRAY_SIZE(r8a774a3_areas), + .extmask_offs =3D 0x2f8, + .extmask_val =3D BIT(0), +}; diff --git a/drivers/pmdomain/renesas/rcar-sysc.c b/drivers/pmdomain/renesa= s/rcar-sysc.c index bd7bb9cbd9da..3c8a44c6d772 100644 --- a/drivers/pmdomain/renesas/rcar-sysc.c +++ b/drivers/pmdomain/renesas/rcar-sysc.c @@ -284,6 +284,9 @@ static const struct of_device_id rcar_sysc_matches[] __= initconst =3D { #ifdef CONFIG_SYSC_R8A774A1 { .compatible =3D "renesas,r8a774a1-sysc", .data =3D &r8a774a1_sysc_info = }, #endif +#ifdef CONFIG_SYSC_R8A774A3 + { .compatible =3D "renesas,r8a774a3-sysc", .data =3D &r8a774a3_sysc_info = }, +#endif #ifdef CONFIG_SYSC_R8A774B1 { .compatible =3D "renesas,r8a774b1-sysc", .data =3D &r8a774b1_sysc_info = }, #endif diff --git a/drivers/pmdomain/renesas/rcar-sysc.h b/drivers/pmdomain/renesa= s/rcar-sysc.h index ef598ecc710a..b264e727883b 100644 --- a/drivers/pmdomain/renesas/rcar-sysc.h +++ b/drivers/pmdomain/renesas/rcar-sysc.h @@ -61,6 +61,7 @@ extern const struct rcar_sysc_info r8a7743_sysc_info; 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charset="utf-8" Select SYSC_R8A774A3 config option if ARCH_R8A774A3 is enabled so that System Controller driver is enabled on Renesas RZ/G2M v3.0 SoC. Signed-off-by: Ayman Chaudhry Reviewed-by: Geert Uytterhoeven --- v1->v2: - Added Reviewed-by tag drivers/soc/renesas/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 0f6d53abd86c..5445fba0879d 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -231,6 +231,7 @@ config ARCH_R8A774A3 bool "ARM64 Platform support for R8A774A3 (RZ/G2M v3.0)" default y if ARCH_RENESAS select ARCH_RCAR_GEN3 + select SYSC_R8A774A3 help This enables support for the Renesas RZ/G2M SoC (version 3.0). =20 --=20 2.34.1 From nobody Thu Sep 24 18:43:34 2026 Received: from TYVP286CU001.outbound.protection.outlook.com (mail-japaneastazon11011038.outbound.protection.outlook.com [52.101.125.38]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DA9048595F; Mon, 21 Sep 2026 13:45:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 21 Sep 2026 22:45:16 +0900 (JST) From: Ayman Chaudhry To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Ayman Chaudhry , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Paterson , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 5/9] dt-bindings: clock: Add r8a774a3 CPG Core Clock definitions Date: Mon, 21 Sep 2026 13:44:25 +0000 Message-ID: <20260921134432.50338-6-ayman.chaudhry.kc@renesas.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260921134432.50338-1-ayman.chaudhry.kc@renesas.com> References: <20260921134432.50338-1-ayman.chaudhry.kc@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY1PEPF0000BAD7:EE_|OS7PR01MB18410:EE_ X-MS-Office365-Filtering-Correlation-Id: 82860b84-304d-43a9-1896-08df17e694e1 X-LD-Processed: 53d82571-da19-47e4-9cb4-625a166a4a2a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|23010399003|376014|7416014|10067099003|5023799004|11063799006|3023799007|22082099003|18002099003|56012099006; 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charset="utf-8" Add all the Renesas RZ/G2M v3.0 (a.k.a. R8A774A3) SoC Clock Pulse Generator Core Clock Outputs, as listed in Table 11.3 ("List of Clocks [RZ/G2M V1.3, RZ/G2M V3.0]") of the RZ/G2 Hardware User's Manual. Signed-off-by: Ayman Chaudhry Reviewed-by: Geert Uytterhoeven --- v1->v2: - Renamed file to include vendor prefix - Added vendor prefix to include macros - Added Reviewed-by tag .../clock/renesas,r8a774a3-cpg-mssr.h | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 include/dt-bindings/clock/renesas,r8a774a3-cpg-mssr.h diff --git a/include/dt-bindings/clock/renesas,r8a774a3-cpg-mssr.h b/includ= e/dt-bindings/clock/renesas,r8a774a3-cpg-mssr.h new file mode 100644 index 000000000000..09121a30e066 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r8a774a3-cpg-mssr.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2026 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A774A3_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R8A774A3_CPG_MSSR_H__ + +#include + +/* r8a774a3 CPG Core Clocks */ +#define R8A774A3_CLK_Z 0 +#define R8A774A3_CLK_Z2 1 +#define R8A774A3_CLK_ZG 2 +#define R8A774A3_CLK_ZTR 3 +#define R8A774A3_CLK_ZTRD2 4 +#define R8A774A3_CLK_ZT 5 +#define R8A774A3_CLK_ZX 6 +#define R8A774A3_CLK_S0D1 7 +#define R8A774A3_CLK_S0D2 8 +#define R8A774A3_CLK_S0D3 9 +#define R8A774A3_CLK_S0D4 10 +#define R8A774A3_CLK_S0D6 11 +#define R8A774A3_CLK_S0D8 12 +#define R8A774A3_CLK_S0D12 13 +#define R8A774A3_CLK_S1D2 14 +#define R8A774A3_CLK_S1D4 15 +#define R8A774A3_CLK_S2D1 16 +#define R8A774A3_CLK_S2D2 17 +#define R8A774A3_CLK_S2D4 18 +#define R8A774A3_CLK_S3D1 19 +#define R8A774A3_CLK_S3D2 20 +#define R8A774A3_CLK_S3D4 21 +#define R8A774A3_CLK_LB 22 +#define R8A774A3_CLK_CL 23 +#define R8A774A3_CLK_ZB3 24 +#define R8A774A3_CLK_ZB3D2 25 +#define R8A774A3_CLK_ZB3D4 26 +#define R8A774A3_CLK_CR 27 +#define R8A774A3_CLK_CRD2 28 +#define R8A774A3_CLK_SD0H 29 +#define R8A774A3_CLK_SD0 30 +#define R8A774A3_CLK_SD1H 31 +#define R8A774A3_CLK_SD1 32 +#define R8A774A3_CLK_SD2H 33 +#define R8A774A3_CLK_SD2 34 +#define R8A774A3_CLK_SD3H 35 +#define R8A774A3_CLK_SD3 36 +#define R8A774A3_CLK_RPC 37 +#define R8A774A3_CLK_RPCD2 38 +#define R8A774A3_CLK_MSO 39 +#define R8A774A3_CLK_CANFD 40 +#define R8A774A3_CLK_HDMI 41 +#define R8A774A3_CLK_CSI0 42 +#define R8A774A3_CLK_CP 43 +#define R8A774A3_CLK_CPEX 44 +#define R8A774A3_CLK_R 45 +#define R8A774A3_CLK_OSC 46 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A774A3_CPG_MSSR_H__ */ --=20 2.34.1 From nobody Thu Sep 24 18:43:34 2026 Received: from TY3P286CU002.outbound.protection.outlook.com (mail-japaneastazon11010049.outbound.protection.outlook.com [52.101.229.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCCC04A1E00; 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Mon, 21 Sep 2026 22:45:21 +0900 (JST) From: Ayman Chaudhry To: Geert Uytterhoeven , Stephen Boyd , Brian Masney , Jerome Brunet , Magnus Damm Cc: Ayman Chaudhry , linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Chris Paterson , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 6/9] clk: renesas: Add support for RZ/G2M v3.0 Date: Mon, 21 Sep 2026 13:44:26 +0000 Message-ID: <20260921134432.50338-7-ayman.chaudhry.kc@renesas.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260921134432.50338-1-ayman.chaudhry.kc@renesas.com> References: <20260921134432.50338-1-ayman.chaudhry.kc@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYO1EPF00005020:EE_|TY6PR01MB17996:EE_ X-MS-Office365-Filtering-Correlation-Id: 005e184e-b3d4-43c4-e277-08df17e69756 X-LD-Processed: 53d82571-da19-47e4-9cb4-625a166a4a2a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|23010399003|1800799024|36860700016|22082099003|18002099003|56012099006|11063799006|5023799004|10067099003|3023799007; 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charset="utf-8" Add initial support for Renesas RZ/G2M v3.0 (a.k.a. R8A774A3) SoC, including basic core clocks, and SCIF2 (serial console) and INTC-AP (GIC) module clocks. The RZ/G2M v3.0 CPG is similar to the RZ/G2M v1.3, however it lacks some modules such as the FCPCI. Signed-off-by: Ayman Chaudhry Reviewed-by: Geert Uytterhoeven --- v1->v2: - Updated include path to CPG dt-bindings - Added Reviewed-by tag drivers/clk/renesas/Kconfig | 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r8a774a3-cpg-mssr.c | 168 ++++++++++++++++++++++++ drivers/clk/renesas/renesas-cpg-mssr.c | 6 + drivers/clk/renesas/renesas-cpg-mssr.h | 1 + 5 files changed, 181 insertions(+) create mode 100644 drivers/clk/renesas/r8a774a3-cpg-mssr.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 46b929e9872b..a02ca6b096c0 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -13,6 +13,7 @@ config CLK_RENESAS select CLK_R8A7745 if ARCH_R8A7745 select CLK_R8A77470 if ARCH_R8A77470 select CLK_R8A774A1 if ARCH_R8A774A1 + select CLK_R8A774A3 if ARCH_R8A774A3 select CLK_R8A774B1 if ARCH_R8A774B1 select CLK_R8A774C0 if ARCH_R8A774C0 select CLK_R8A774E1 if ARCH_R8A774E1 @@ -93,6 +94,10 @@ config CLK_R8A774A1 bool "RZ/G2M clock support" if COMPILE_TEST select CLK_RCAR_GEN3_CPG =20 +config CLK_R8A774A3 + bool "RZ/G2M v3.0 clock support" if COMPILE_TEST + select CLK_RCAR_GEN3_CPG + config CLK_R8A774B1 bool "RZ/G2N clock support" if COMPILE_TEST select CLK_RCAR_GEN3_CPG diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 658f8aac5127..5c1b798118db 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_CLK_R8A7743) +=3D r8a7743-cpg-mssr.o obj-$(CONFIG_CLK_R8A7745) +=3D r8a7745-cpg-mssr.o obj-$(CONFIG_CLK_R8A77470) +=3D r8a77470-cpg-mssr.o obj-$(CONFIG_CLK_R8A774A1) +=3D r8a774a1-cpg-mssr.o +obj-$(CONFIG_CLK_R8A774A3) +=3D r8a774a3-cpg-mssr.o obj-$(CONFIG_CLK_R8A774B1) +=3D r8a774b1-cpg-mssr.o obj-$(CONFIG_CLK_R8A774C0) +=3D r8a774c0-cpg-mssr.o obj-$(CONFIG_CLK_R8A774E1) +=3D r8a774e1-cpg-mssr.o diff --git a/drivers/clk/renesas/r8a774a3-cpg-mssr.c b/drivers/clk/renesas/= r8a774a3-cpg-mssr.c new file mode 100644 index 000000000000..64c5106a9a54 --- /dev/null +++ b/drivers/clk/renesas/r8a774a3-cpg-mssr.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * r8a774a3 Clock Pulse Generator / Module Standby and Software Reset + * + * Copyright (C) 2026 Renesas Electronics Corp. + * + * Based on r8a7796-cpg-mssr.c + * + * Copyright (C) 2016 Glider bvba + */ + +#include +#include +#include +#include + +#include + +#include "renesas-cpg-mssr.h" +#include "rcar-gen3-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK =3D R8A774A3_CLK_OSC, + + /* External Input Clocks */ + CLK_EXTAL, + CLK_EXTALR, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_PLL0, + CLK_PLL1, + CLK_PLL2, + CLK_PLL3, + CLK_PLL4, + CLK_PLL1_DIV2, + CLK_PLL1_DIV4, + CLK_S0, + CLK_S1, + CLK_S2, + CLK_S3, + + /* Module Clocks */ + MOD_CLK_BASE +}; + +static const struct cpg_core_clk r8a774a3_core_clks[] __initconst =3D { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + DEF_INPUT("extalr", CLK_EXTALR), + + /* Internal Core Clocks */ + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), + DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), + DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), + + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), + DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), + + /* Core Clock Outputs */ + DEF_GEN3_Z("z", R8A774A3_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2,= 8), + DEF_GEN3_Z("z2", R8A774A3_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2= , 0), + DEF_FIXED("s0d3", R8A774A3_CLK_S0D3, CLK_S0, 3, 1), + DEF_FIXED("s3d1", R8A774A3_CLK_S3D1, CLK_S3, 1, 1), + DEF_FIXED("s3d4", R8A774A3_CLK_S3D4, CLK_S3, 4, 1), +}; + +static const struct mssr_mod_clk r8a774a3_mod_clks[] __initconst =3D { + DEF_MOD("scif2", 310, R8A774A3_CLK_S3D4), + DEF_MOD("intc-ap", 408, R8A774A3_CLK_S0D3), +}; + +static const unsigned int r8a774a3_crit_mod_clks[] __initconst =3D { + MOD_CLK_ID(408), /* INTC-AP (GIC) */ +}; + +/* + * CPG Clock Data + */ + +/* + * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC + * 14 13 19 17 (MHz) + *------------------------------------------------------------------------- + * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16 + * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16 + * 0 0 1 0 Prohibited setting + * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16 + * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19 + * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19 + * 0 1 1 0 Prohibited setting + * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19 + * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24 + * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24 + * 1 0 1 0 Prohibited setting + * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24 + * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32 + * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32 + * 1 1 1 0 Prohibited setting + * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32 + */ +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ + (((md) & BIT(13)) >> 11) | \ + (((md) & BIT(19)) >> 18) | \ + (((md) & BIT(17)) >> 17)) + +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initcon= st =3D { + /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ + { 1, 192, 1, 192, 1, 16, }, + { 1, 192, 1, 128, 1, 16, }, + { 0, /* Prohibited setting */ }, + { 1, 192, 1, 192, 1, 16, }, + { 1, 160, 1, 160, 1, 19, }, + { 1, 160, 1, 106, 1, 19, }, + { 0, /* Prohibited setting */ }, + { 1, 160, 1, 160, 1, 19, }, + { 1, 128, 1, 128, 1, 24, }, + { 1, 128, 1, 84, 1, 24, }, + { 0, /* Prohibited setting */ }, + { 1, 128, 1, 128, 1, 24, }, + { 2, 192, 1, 192, 1, 32, }, + { 2, 192, 1, 128, 1, 32, }, + { 0, /* Prohibited setting */ }, + { 2, 192, 1, 192, 1, 32, }, +}; + +static int __init r8a774a3_cpg_mssr_init(struct device *dev) +{ + const struct rcar_gen3_cpg_pll_config *cpg_pll_config; + u32 cpg_mode; + int error; + + error =3D rcar_rst_read_mode_pins(&cpg_mode); + if (error) + return error; + + cpg_pll_config =3D &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; + if (!cpg_pll_config->extal_div) { + dev_err(dev, "Prohibited setting (cpg_mode=3D0x%x)\n", cpg_mode); + return -EINVAL; + } + + return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); +} + +const struct cpg_mssr_info r8a774a3_cpg_mssr_info __initconst =3D { + /* Core Clocks */ + .core_clks =3D r8a774a3_core_clks, + .num_core_clks =3D ARRAY_SIZE(r8a774a3_core_clks), + .last_dt_core_clk =3D LAST_DT_CORE_CLK, + .num_total_core_clks =3D MOD_CLK_BASE, + + /* Module Clocks */ + .mod_clks =3D r8a774a3_mod_clks, + .num_mod_clks =3D ARRAY_SIZE(r8a774a3_mod_clks), + .num_hw_mod_clks =3D 12 * 32, + + /* Critical Module Clocks */ + .crit_mod_clks =3D r8a774a3_crit_mod_clks, + .num_crit_mod_clks =3D ARRAY_SIZE(r8a774a3_crit_mod_clks), + + /* Callbacks */ + .init =3D r8a774a3_cpg_mssr_init, + .cpg_clk_register =3D rcar_gen3_cpg_clk_register, +}; diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/r= enesas-cpg-mssr.c index df9c2a8c8e70..ffac4409a161 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -944,6 +944,12 @@ static const struct of_device_id cpg_mssr_match[] =3D { .data =3D &r8a774a1_cpg_mssr_info, }, #endif +#ifdef CONFIG_CLK_R8A774A3 + { + .compatible =3D "renesas,r8a774a3-cpg-mssr", + .data =3D &r8a774a3_cpg_mssr_info, + }, +#endif #ifdef CONFIG_CLK_R8A774B1 { .compatible =3D "renesas,r8a774b1-cpg-mssr", diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/r= enesas-cpg-mssr.h index 5bef6f34dcb2..dc3015b3032d 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -191,6 +191,7 @@ extern const struct cpg_mssr_info r8a7743_cpg_mssr_info; extern const struct cpg_mssr_info r8a7745_cpg_mssr_info; extern const struct cpg_mssr_info r8a77470_cpg_mssr_info; extern const struct cpg_mssr_info r8a774a1_cpg_mssr_info; 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charset="utf-8" Add initial Device Tree Source Include (DTSI) file for the Renesas RZ/G2M v3.0 (a.k.a. R8A774A3) SoC with basic support. Signed-off-by: Ayman Chaudhry Reviewed-by: Geert Uytterhoeven --- v1->v2: - Updated include path to CPG, SYSC dt-bindings - Replaced underscores of node names with hyphens - Updated licensing to "GPL-2.0-only OR BSD-2-Clause" - Added soc: label to soc node - Updated register sizes for clock-controller and reset-controller nodes to not use odd sizes - Updated register size for system-controller node to not have a leading 0 in the register size - Added Reviewed-by tag arch/arm64/boot/dts/renesas/r8a774a3.dtsi | 302 ++++++++++++++++++++++ 1 file changed, 302 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a774a3.dtsi diff --git a/arch/arm64/boot/dts/renesas/r8a774a3.dtsi b/arch/arm64/boot/dt= s/renesas/r8a774a3.dtsi new file mode 100644 index 000000000000..e8adafbf0104 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774a3.dtsi @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +/* + * Device Tree Source for the r8a774a3 SoC + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +/ { + compatible =3D "renesas,r8a774a3"; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + + cluster0_opp: opp-table-0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-microvolt =3D <820000>; + clock-latency-ns =3D <300000>; + }; + opp-1000000000 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-microvolt =3D <820000>; + clock-latency-ns =3D <300000>; + }; + opp-1500000000 { + opp-hz =3D /bits/ 64 <1500000000>; + opp-microvolt =3D <820000>; + clock-latency-ns =3D <300000>; + opp-suspend; + }; + }; + + cluster1_opp: opp-table-1 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-microvolt =3D <820000>; + clock-latency-ns =3D <300000>; + }; + opp-1000000000 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-microvolt =3D <820000>; + clock-latency-ns =3D <300000>; + }; + opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-microvolt =3D <820000>; + clock-latency-ns =3D <300000>; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&a57_0>; + }; + core1 { + cpu =3D <&a57_1>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&a53_0>; + }; + core1 { + cpu =3D <&a53_1>; + }; + core2 { + cpu =3D <&a53_2>; + }; + core3 { + cpu =3D <&a53_3>; + }; + }; + }; + + a57_0: cpu@0 { + compatible =3D "arm,cortex-a57"; + reg =3D <0x0>; + device_type =3D "cpu"; + power-domains =3D <&sysc R8A774A3_PD_CA57_CPU0>; + next-level-cache =3D <&L2_CA57>; + enable-method =3D "psci"; + dynamic-power-coefficient =3D <854>; + clocks =3D <&cpg CPG_CORE R8A774A3_CLK_Z>; + operating-points-v2 =3D <&cluster0_opp>; + capacity-dmips-mhz =3D <1024>; + }; + + a57_1: cpu@1 { + compatible =3D "arm,cortex-a57"; + reg =3D <0x1>; + device_type =3D "cpu"; + power-domains =3D <&sysc R8A774A3_PD_CA57_CPU1>; + next-level-cache =3D <&L2_CA57>; + enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R8A774A3_CLK_Z>; + operating-points-v2 =3D <&cluster0_opp>; + capacity-dmips-mhz =3D <1024>; + }; + + a53_0: cpu@100 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x100>; + device_type =3D "cpu"; + power-domains =3D <&sysc R8A774A3_PD_CA53_CPU0>; + next-level-cache =3D <&L2_CA53>; + enable-method =3D "psci"; + dynamic-power-coefficient =3D <277>; + clocks =3D <&cpg CPG_CORE R8A774A3_CLK_Z2>; + operating-points-v2 =3D <&cluster1_opp>; + capacity-dmips-mhz =3D <560>; + }; + + a53_1: cpu@101 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x101>; + device_type =3D "cpu"; + power-domains =3D <&sysc R8A774A3_PD_CA53_CPU1>; + next-level-cache =3D <&L2_CA53>; + enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R8A774A3_CLK_Z2>; + operating-points-v2 =3D <&cluster1_opp>; + capacity-dmips-mhz =3D <560>; + }; + + a53_2: cpu@102 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x102>; + device_type =3D "cpu"; + power-domains =3D <&sysc R8A774A3_PD_CA53_CPU2>; + next-level-cache =3D <&L2_CA53>; + enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R8A774A3_CLK_Z2>; + operating-points-v2 =3D <&cluster1_opp>; + capacity-dmips-mhz =3D <560>; + }; + + a53_3: cpu@103 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x103>; + device_type =3D "cpu"; + power-domains =3D <&sysc R8A774A3_PD_CA53_CPU3>; + next-level-cache =3D <&L2_CA53>; + enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R8A774A3_CLK_Z2>; + operating-points-v2 =3D <&cluster1_opp>; + capacity-dmips-mhz =3D <560>; + }; + + L2_CA57: cache-controller-0 { + compatible =3D "cache"; + power-domains =3D <&sysc R8A774A3_PD_CA57_SCU>; + cache-unified; + cache-level =3D <2>; + }; + + L2_CA53: cache-controller-1 { + compatible =3D "cache"; + power-domains =3D <&sysc R8A774A3_PD_CA53_SCU>; + cache-unified; + cache-level =3D <2>; + }; + }; + + extal_clk: extal { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + bootph-all; + }; + + extalr_clk: extalr { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + bootph-all; + }; + + pmu-a53 { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D , + , + , + ; + interrupt-affinity =3D <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; + }; + + pmu-a57 { + compatible =3D "arm,cortex-a57-pmu"; + interrupts =3D , + ; + interrupt-affinity =3D <&a57_0>, <&a57_1>; + }; + + psci { + compatible =3D "arm,psci-1.0", "arm,psci-0.2"; + method =3D "smc"; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <0>; + }; + + soc: soc { + compatible =3D "simple-bus"; + bootph-all; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + cpg: clock-controller@e6150000 { + compatible =3D "renesas,r8a774a3-cpg-mssr"; + reg =3D <0 0xe6150000 0 0x1000>; + clocks =3D <&extal_clk>, <&extalr_clk>; + clock-names =3D "extal", "extalr"; + #clock-cells =3D <2>; + #power-domain-cells =3D <0>; + #reset-cells =3D <1>; + bootph-all; + }; + + rst: reset-controller@e6160000 { + compatible =3D "renesas,r8a774a3-rst"; + reg =3D <0 0xe6160000 0 0x200>; + bootph-all; + }; + + sysc: system-controller@e6180000 { + compatible =3D "renesas,r8a774a3-sysc"; + reg =3D <0 0xe6180000 0 0x400>; + #power-domain-cells =3D <1>; + }; + + scif2: serial@e6e88000 { + compatible =3D "renesas,scif-r8a774a3", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg =3D <0 0xe6e88000 0 0x40>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A774A3_CLK_S3D1>, + <&scif_clk>; + clock-names =3D "fck", "brg_int", "scif_clk"; + power-domains =3D <&sysc R8A774A3_PD_ALWAYS_ON>; + resets =3D <&cpg 310>; + status =3D "disabled"; + }; + + gic: interrupt-controller@f1010000 { + compatible =3D "arm,gic-400"; + #interrupt-cells =3D <3>; + #address-cells =3D <0>; + interrupt-controller; + reg =3D <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD 408>; + clock-names =3D "clk"; + power-domains =3D <&sysc R8A774A3_PD_ALWAYS_ON>; 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charset="utf-8" Add support for the HiHope RZ/G2M v3.0 (a.k.a. R8A774A3) SoC main board. The RZ/G2M v3.0 SoC main board is similar to the RZ/G2M v1.3 SoC main board, so there are already DTSI files available in the kernel. These DTSI files will be included once additional support (e.g. I2C, GPIO and sound) is added for the RZ/G2M v3.0 SoC. Signed-off-by: Ayman Chaudhry Reviewed-by: Geert Uytterhoeven --- v1->v2: - Dropped bootargs from chosen. - Updated licensing to "GPL-2.0-only OR BSD-2-Clause" arch/arm64/boot/dts/renesas/Makefile | 2 + .../dts/renesas/r8a774a3-hihope-rzg2m.dts | 49 +++++++++++++++++++ 2 files changed, 51 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/ren= esas/Makefile index b742baf509a1..9817f3ada6f9 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -8,6 +8,8 @@ dtb-$(CONFIG_ARCH_R8A774A1) +=3D r8a774a1-hihope-rzg2m-rev2= .dtb dtb-$(CONFIG_ARCH_R8A774A1) +=3D r8a774a1-hihope-rzg2m-rev2-ex.dtb dtb-$(CONFIG_ARCH_R8A774A1) +=3D r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.= dtb =20 +dtb-$(CONFIG_ARCH_R8A774A3) +=3D r8a774a3-hihope-rzg2m.dtb + dtb-$(CONFIG_ARCH_R8A774B1) +=3D r8a774b1-beacon-rzg2n-kit.dtb dtb-$(CONFIG_ARCH_R8A774B1) +=3D r8a774b1-hihope-rzg2n.dtb dtb-$(CONFIG_ARCH_R8A774B1) +=3D r8a774b1-hihope-rzg2n-ex.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m.dts b/arch/a= rm64/boot/dts/renesas/r8a774a3-hihope-rzg2m.dts new file mode 100644 index 000000000000..cd46af2a924a --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m.dts @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +/* + * Device Tree Source for the HiHope RZ/G2M v3.0 SoC main board + * + *Copyright (C) 2026 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a774a3.dtsi" + +/ { + model =3D "HopeRun HiHope RZ/G2M v3.0 main board based on r8a774a3"; + compatible =3D "hoperun,hihope-rzg2m", "renesas,r8a774a3"; + + memory@48000000 { + device_type =3D "memory"; + /* First 128MiB is reserved for secure area */ + reg =3D <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@600000000 { + device_type =3D "memory"; + reg =3D <0x6 0x00000000 0x0 0x80000000>; + }; + + aliases { + serial0 =3D &scif2; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&extal_clk { + clock-frequency =3D <16666666>; +}; + +&extalr_clk { + clock-frequency =3D <32768>; +}; + +&scif2 { + status =3D "okay"; +}; + +&scif_clk { + clock-frequency =3D <14745600>; +}; --=20 2.34.1 From nobody Thu Sep 24 18:43:34 2026 Received: from TYVP286CU001.outbound.protection.outlook.com (mail-japaneastazon11011060.outbound.protection.outlook.com [52.101.125.60]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 470284A205B; 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Mon, 21 Sep 2026 22:45:34 +0900 (JST) From: Ayman Chaudhry To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Ayman Chaudhry , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Paterson , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 9/9] arm64: dts: renesas: Add HiHope RZ/G2M v3.0 SoC sub board support Date: Mon, 21 Sep 2026 13:44:29 +0000 Message-ID: <20260921134432.50338-10-ayman.chaudhry.kc@renesas.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260921134432.50338-1-ayman.chaudhry.kc@renesas.com> References: <20260921134432.50338-1-ayman.chaudhry.kc@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY1PEPF0000BADA:EE_|TY4PR01MB14588:EE_ X-MS-Office365-Filtering-Correlation-Id: d2281467-ae97-456f-6d66-08df17e69ebb X-LD-Processed: 53d82571-da19-47e4-9cb4-625a166a4a2a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|376014|23010399003|82310400026|11063799006|56012099006|10067099003|22082099003|18002099003; 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charset="utf-8" The HiHope RZ/G2M sub board sits below the HiHope RZ/G2M v3.0 (a.k.a. R8A774A3) SoC main board. The RZ/G2M v3.0 SoC sub board is similar to the RZ/G2M v1.3 SoC sub board, so there are already DTSI files available in the kernel. These DTSI files will be included once additional support (e.g. CAN, PCIe and ethernet) is added for the RZ/G2M v3.0 SoC. Signed-off-by: Ayman Chaudhry Reviewed-by: Geert Uytterhoeven --- v1->v2: - Corrected indentation - Updated licensing to "GPL-2.0-only OR BSD-2-Clause" arch/arm64/boot/dts/renesas/Makefile | 1 + .../boot/dts/renesas/r8a774a3-hihope-rzg2m-ex.dts | 14 ++++++++++++++ 2 files changed, 15 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m-ex.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/ren= esas/Makefile index 9817f3ada6f9..10a138216221 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_R8A774A1) +=3D r8a774a1-hihope-rzg2m-rev2= -ex.dtb dtb-$(CONFIG_ARCH_R8A774A1) +=3D r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.= dtb =20 dtb-$(CONFIG_ARCH_R8A774A3) +=3D r8a774a3-hihope-rzg2m.dtb +dtb-$(CONFIG_ARCH_R8A774A3) +=3D r8a774a3-hihope-rzg2m-ex.dtb =20 dtb-$(CONFIG_ARCH_R8A774B1) +=3D r8a774b1-beacon-rzg2n-kit.dtb dtb-$(CONFIG_ARCH_R8A774B1) +=3D r8a774b1-hihope-rzg2n.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m-ex.dts b/arc= h/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m-ex.dts new file mode 100644 index 000000000000..d346a4009ec8 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m-ex.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +/* + * Device Tree Source for the HiHope RZ/G2M v3.0 SoC sub board + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include "r8a774a3-hihope-rzg2m.dts" + +/ { + model =3D "HopeRun HiHope RZ/G2M v3.0 with sub board"; + compatible =3D "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m", + "renesas,r8a774a3"; +}; --=20 2.34.1