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Mon, 21 Sep 2026 03:25:31 -0700 (PDT) From: Akari Tsuyukusa To: Stephen Boyd , Brian Masney , Jerome Brunet , Matthias Brugger , AngeloGioacchino Del Regno Cc: Takashi Sakamoto , Danilo Krummrich , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Bjorn Helgaas , Akari Tsuyukusa , Nicolas Frattaroli , Chen-Yu Tsai , Laura Nao , Sjoerd Simons , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list:ARM/Mediatek SoC support), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support) Subject: [PATCH 1/6] clk: mediatek: Fix MT6779 clock onecell IDs Date: Mon, 21 Sep 2026 19:25:17 +0900 Message-ID: <20260921102522.1640072-2-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260921102522.1640072-1-akkun11.open@gmail.com> References: <20260921102522.1640072-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the missing dummy slot for clock ID 0 in the MT6779 audio, camera, image, IPE, MFG, multimedia, VDEC and VENC clock providers. Also register the missing SSPM infracfg clock and reserve the binding-defined MDP WDMA0 slot in the multimedia provider. This fixes the onecell clock data allocation so all registered clock IDs are within bounds. Assisted-by: GPT-5.6 Luna Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt6779-aud.c | 1 + drivers/clk/mediatek/clk-mt6779-cam.c | 1 + drivers/clk/mediatek/clk-mt6779-img.c | 1 + drivers/clk/mediatek/clk-mt6779-ipe.c | 1 + drivers/clk/mediatek/clk-mt6779-mfg.c | 1 + drivers/clk/mediatek/clk-mt6779-mm.c | 2 ++ drivers/clk/mediatek/clk-mt6779-vdec.c | 1 + drivers/clk/mediatek/clk-mt6779-venc.c | 1 + drivers/clk/mediatek/clk-mt6779.c | 1 + 9 files changed, 10 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt6779-aud.c b/drivers/clk/mediatek/c= lk-mt6779-aud.c index 30c290fd6b84..6be054816a4b 100644 --- a/drivers/clk/mediatek/clk-mt6779-aud.c +++ b/drivers/clk/mediatek/clk-mt6779-aud.c @@ -33,6 +33,7 @@ static const struct mtk_gate_regs audio1_cg_regs =3D { &mtk_clk_gate_ops_no_setclr) =20 static const struct mtk_gate audio_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "aud_dummy"), /* AUDIO0 */ GATE_AUDIO0(CLK_AUD_AFE, "aud_afe", "audio_sel", 2), GATE_AUDIO0(CLK_AUD_22M, "aud_22m", "aud_eng1_sel", 8), diff --git a/drivers/clk/mediatek/clk-mt6779-cam.c b/drivers/clk/mediatek/c= lk-mt6779-cam.c index f397b55606de..35c313b48b16 100644 --- a/drivers/clk/mediatek/clk-mt6779-cam.c +++ b/drivers/clk/mediatek/clk-mt6779-cam.c @@ -23,6 +23,7 @@ static const struct mtk_gate_regs cam_cg_regs =3D { &mtk_clk_gate_ops_setclr) =20 static const struct mtk_gate cam_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "cam_dummy"), GATE_CAM(CLK_CAM_LARB10, "camsys_larb10", "cam_sel", 0), GATE_CAM(CLK_CAM_DFP_VAD, "camsys_dfp_vad", "cam_sel", 1), GATE_CAM(CLK_CAM_LARB11, "camsys_larb11", "cam_sel", 2), diff --git a/drivers/clk/mediatek/clk-mt6779-img.c b/drivers/clk/mediatek/c= lk-mt6779-img.c index 474a59a4ca9e..b5efc2cfe189 100644 --- a/drivers/clk/mediatek/clk-mt6779-img.c +++ b/drivers/clk/mediatek/clk-mt6779-img.c @@ -23,6 +23,7 @@ static const struct mtk_gate_regs img_cg_regs =3D { &mtk_clk_gate_ops_setclr) =20 static const struct mtk_gate img_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "img_dummy"), GATE_IMG(CLK_IMG_LARB5, "imgsys_larb5", "img_sel", 0), GATE_IMG(CLK_IMG_LARB6, "imgsys_larb6", "img_sel", 1), GATE_IMG(CLK_IMG_DIP, "imgsys_dip", "img_sel", 2), diff --git a/drivers/clk/mediatek/clk-mt6779-ipe.c b/drivers/clk/mediatek/c= lk-mt6779-ipe.c index c2314654f43a..284d5adb8a6e 100644 --- a/drivers/clk/mediatek/clk-mt6779-ipe.c +++ b/drivers/clk/mediatek/clk-mt6779-ipe.c @@ -23,6 +23,7 @@ static const struct mtk_gate_regs ipe_cg_regs =3D { &mtk_clk_gate_ops_setclr) =20 static const struct mtk_gate ipe_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "ipe_dummy"), GATE_IPE(CLK_IPE_LARB7, "ipe_larb7", "ipe_sel", 0), GATE_IPE(CLK_IPE_LARB8, "ipe_larb8", "ipe_sel", 1), GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "ipe_sel", 2), diff --git a/drivers/clk/mediatek/clk-mt6779-mfg.c b/drivers/clk/mediatek/c= lk-mt6779-mfg.c index 21793cb6e6e3..dd7d98d7de7d 100644 --- a/drivers/clk/mediatek/clk-mt6779-mfg.c +++ b/drivers/clk/mediatek/clk-mt6779-mfg.c @@ -24,6 +24,7 @@ static const struct mtk_gate_regs mfg_cg_regs =3D { &mtk_clk_gate_ops_setclr) =20 static const struct mtk_gate mfg_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "mfg_dummy"), GATE_MFG(CLK_MFGCFG_BG3D, "mfg_bg3d", "mfg_sel", 0), }; =20 diff --git a/drivers/clk/mediatek/clk-mt6779-mm.c b/drivers/clk/mediatek/cl= k-mt6779-mm.c index 30bbab308388..3b3053385021 100644 --- a/drivers/clk/mediatek/clk-mt6779-mm.c +++ b/drivers/clk/mediatek/clk-mt6779-mm.c @@ -32,6 +32,7 @@ static const struct mtk_gate_regs mm1_cg_regs =3D { &mtk_clk_gate_ops_setclr) =20 static const struct mtk_gate mm_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "mm_dummy"), /* MM0 */ GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0), GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1), @@ -76,6 +77,7 @@ static const struct mtk_gate mm_clks[] =3D { GATE_MM1(CLK_MM_26M, "mm_26m", "f_f26m_ck", 7), GATE_MM1(CLK_MM_MM_R2Y, "mm_mmsys_r2y", "mm_sel", 8), GATE_MM1(CLK_MM_DISP_RSZ, "mm_disp_rsz", "mm_sel", 9), + GATE_DUMMY(CLK_MM_MDP_WDMA0, "mm_mdp_wdma0_dummy"), GATE_MM1(CLK_MM_MDP_AAL, "mm_mdp_aal", "mm_sel", 10), GATE_MM1(CLK_MM_MDP_HDR, "mm_mdp_hdr", "mm_sel", 11), GATE_MM1(CLK_MM_DBI_MM_CK, "mm_dbi_mmck", "mm_sel", 12), diff --git a/drivers/clk/mediatek/clk-mt6779-vdec.c b/drivers/clk/mediatek/= clk-mt6779-vdec.c index 458d012f023c..1e4922f8a037 100644 --- a/drivers/clk/mediatek/clk-mt6779-vdec.c +++ b/drivers/clk/mediatek/clk-mt6779-vdec.c @@ -33,6 +33,7 @@ static const struct mtk_gate_regs vdec1_cg_regs =3D { &mtk_clk_gate_ops_setclr_inv) =20 static const struct mtk_gate vdec_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "vdec_dummy"), /* VDEC0 */ GATE_VDEC0_I(CLK_VDEC_VDEC, "vdec_cken", "vdec_sel", 0), /* VDEC1 */ diff --git a/drivers/clk/mediatek/clk-mt6779-venc.c b/drivers/clk/mediatek/= clk-mt6779-venc.c index 70cebc274031..0d3ffdf50beb 100644 --- a/drivers/clk/mediatek/clk-mt6779-venc.c +++ b/drivers/clk/mediatek/clk-mt6779-venc.c @@ -24,6 +24,7 @@ static const struct mtk_gate_regs venc_cg_regs =3D { &mtk_clk_gate_ops_setclr_inv) =20 static const struct mtk_gate venc_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "venc_dummy"), GATE_VENC_I(CLK_VENC_GCON_LARB, "venc_larb", "venc_sel", 0), GATE_VENC_I(CLK_VENC_GCON_VENC, "venc_venc", "venc_sel", 4), GATE_VENC_I(CLK_VENC_GCON_JPGENC, "venc_jpgenc", "venc_sel", 8), diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-m= t6779.c index 4b9dcb910b03..70d8a970b5bd 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -1014,6 +1014,7 @@ static const struct mtk_gate infra_clks[] =3D { "fufs_sel", 13), GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk", "axi_sel", 14), + GATE_DUMMY(CLK_INFRA_SSPM, "infra_sspm_dummy"), GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16), GATE_INFRA2(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk", --=20 2.55.0 From nobody Thu Sep 24 20:33:42 2026 Received: from mail-pz2-f41.google.com (mail-pz2-f41.google.com [74.125.228.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 266D4471267 for ; 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charset="utf-8" Add the missing dummy clock at ID 0 to the MT6797 image, multimedia, VDEC and VENC clock providers. This keeps the descriptor-based onecell allocations consistent with the binding clock IDs and prevents out-of-bounds accesses. Assisted-by: GPT-5.6 Luna Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt6797-img.c | 1 + drivers/clk/mediatek/clk-mt6797-mm.c | 1 + drivers/clk/mediatek/clk-mt6797-vdec.c | 1 + drivers/clk/mediatek/clk-mt6797-venc.c | 1 + 4 files changed, 4 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt6797-img.c b/drivers/clk/mediatek/c= lk-mt6797-img.c index 338c69234f24..2a42ec0a4b14 100644 --- a/drivers/clk/mediatek/clk-mt6797-img.c +++ b/drivers/clk/mediatek/clk-mt6797-img.c @@ -20,6 +20,7 @@ static const struct mtk_gate_regs img_cg_regs =3D { GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate img_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "img_dummy"), GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_sel", 11), GATE_IMG(CLK_IMG_DPE, "img_dpe", "mm_sel", 10), GATE_IMG(CLK_IMG_DIP, "img_dip", "mm_sel", 6), diff --git a/drivers/clk/mediatek/clk-mt6797-mm.c b/drivers/clk/mediatek/cl= k-mt6797-mm.c index ddb40b8a1a7d..d2349c1d2a55 100644 --- a/drivers/clk/mediatek/clk-mt6797-mm.c +++ b/drivers/clk/mediatek/clk-mt6797-mm.c @@ -30,6 +30,7 @@ static const struct mtk_gate_regs mm1_cg_regs =3D { GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate mm_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "mm_dummy"), GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0), GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1), GATE_MM0(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 2), diff --git a/drivers/clk/mediatek/clk-mt6797-vdec.c b/drivers/clk/mediatek/= clk-mt6797-vdec.c index d832f48123f5..73339310fb51 100644 --- a/drivers/clk/mediatek/clk-mt6797-vdec.c +++ b/drivers/clk/mediatek/clk-mt6797-vdec.c @@ -31,6 +31,7 @@ static const struct mtk_gate_regs vdec1_cg_regs =3D { GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr_inv) =20 static const struct mtk_gate vdec_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "vdec_dummy"), GATE_VDEC0(CLK_VDEC_CKEN_ENG, "vdec_cken_eng", "vdec_sel", 8), GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "vdec_sel", 4), GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt6797-venc.c b/drivers/clk/mediatek/= clk-mt6797-venc.c index fd4446f4a9d7..f616d61a0de4 100644 --- a/drivers/clk/mediatek/clk-mt6797-venc.c +++ b/drivers/clk/mediatek/clk-mt6797-venc.c @@ -22,6 +22,7 @@ static const struct mtk_gate_regs venc_cg_regs =3D { GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) =20 static const struct mtk_gate venc_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "venc_dummy"), GATE_VENC(CLK_VENC_0, "venc_0", "mm_sel", 0), GATE_VENC(CLK_VENC_1, "venc_1", "venc_sel", 4), GATE_VENC(CLK_VENC_2, "venc_2", "venc_sel", 8), --=20 2.55.0 From nobody Thu Sep 24 20:33:42 2026 Received: from mail-pz2-f12.google.com (mail-pz2-f12.google.com [74.125.228.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94C46471262 for ; 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charset="utf-8" Reserve the binding-defined CLK_TOP_HDMTX_CLKDIG_CTS slot in the MT8167 top clock provider with a dummy clock. The clock is not implemented by the topckgen driver, but the slot must remain present in the onecell data to keep the descriptor allocation large enough for the registered IDs. Assisted-by: GPT-5.6 Luna Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt8167.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-m= t8167.c index c64d918c37de..c88c41aa7fdf 100644 --- a/drivers/clk/mediatek/clk-mt8167.c +++ b/drivers/clk/mediatek/clk-mt8167.c @@ -746,6 +746,7 @@ static const struct mtk_gate_regs top5_cg_regs =3D { GATE_MTK(_id, _name, _parent, &top5_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr) =20 static const struct mtk_gate top_clks[] =3D { + GATE_DUMMY(CLK_TOP_HDMTX_CLKDIG_CTS, "hdmtx_clkdig_cts_dummy"), /* TOP0 */ GATE_TOP0(CLK_TOP_PWM_MM, "pwm_mm", "pwm_mm_sel", 0), GATE_TOP0(CLK_TOP_CAM_MM, "cam_mm", "camtg_mm_sel", 1), --=20 2.55.0 From nobody Thu Sep 24 20:33:42 2026 Received: from mail-pz2-f41.google.com (mail-pz2-f41.google.com [74.125.228.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 540063BB10D for ; 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Mon, 21 Sep 2026 03:25:40 -0700 (PDT) Received: from buffalo-ssd.taila54753.ts.net ([240b:253:4760:f400:1ebf:ceff:fe7f:5e0b]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-877a94f238csm2909174b3a.21.2026.09.21.03.25.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2026 03:25:40 -0700 (PDT) From: Akari Tsuyukusa To: Stephen Boyd , Brian Masney , Jerome Brunet , Matthias Brugger , AngeloGioacchino Del Regno Cc: Takashi Sakamoto , Danilo Krummrich , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Bjorn Helgaas , Akari Tsuyukusa , Nicolas Frattaroli , Chen-Yu Tsai , Laura Nao , Sjoerd Simons , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list:ARM/Mediatek SoC support), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support) Subject: [PATCH 4/6] clk: mediatek: Reserve missing MT8173 topckgen IDs Date: Mon, 21 Sep 2026 19:25:20 +0900 Message-ID: <20260921102522.1640072-5-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260921102522.1640072-1-akkun11.open@gmail.com> References: <20260921102522.1640072-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Reserve the unused clock ID 2 and the binding-defined CLK_TOP_HDMITX_DIG_CTS slot in the MT8173 topckgen provider. Neither clock is implemented by topckgen: ID 2 corresponds to the removed DPI clock, while the HDMI digital clock is provided by the HDMI PHY. Keep both onecell slots populated with dummy clocks so the descriptor-based allocation covers the complete registered ID range. Assisted-by: GPT-5.6 Luna Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt8173-topckgen.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8173-topckgen.c b/drivers/clk/media= tek/clk-mt8173-topckgen.c index 42c37541cebb..9c50f66766b4 100644 --- a/drivers/clk/mediatek/clk-mt8173-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8173-topckgen.c @@ -624,6 +624,11 @@ static const struct mtk_composite top_muxes[] =3D { MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1), }; =20 +static const struct mtk_gate top_dummy_clks[] =3D { + GATE_DUMMY(2, "topck_reserved_2"), + GATE_DUMMY(CLK_TOP_HDMITX_DIG_CTS, "hdmitx_dig_cts_dummy"), +}; + static const struct mtk_clk_desc topck_desc =3D { .fixed_clks =3D fixed_clks, .num_fixed_clks =3D ARRAY_SIZE(fixed_clks), @@ -631,6 +636,8 @@ static const struct mtk_clk_desc topck_desc =3D { .num_factor_clks =3D ARRAY_SIZE(top_divs), .composite_clks =3D top_muxes, .num_composite_clks =3D ARRAY_SIZE(top_muxes), + .clks =3D top_dummy_clks, + .num_clks =3D ARRAY_SIZE(top_dummy_clks), .clk_lock =3D &mt8173_top_clk_lock, }; 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Mon, 21 Sep 2026 03:25:43 -0700 (PDT) From: Akari Tsuyukusa To: Stephen Boyd , Brian Masney , Jerome Brunet , Matthias Brugger , AngeloGioacchino Del Regno Cc: Takashi Sakamoto , Danilo Krummrich , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Bjorn Helgaas , Akari Tsuyukusa , Nicolas Frattaroli , Chen-Yu Tsai , Laura Nao , Sjoerd Simons , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list:ARM/Mediatek SoC support), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support) Subject: [PATCH 5/6] clk: mediatek: Reserve missing MT8196 MDP clock IDs Date: Mon, 21 Sep 2026 19:25:21 +0900 Message-ID: <20260921102522.1640072-6-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260921102522.1640072-1-akkun11.open@gmail.com> References: <20260921102522.1640072-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Reserve the binding-defined CLK_MDP_SMI0_SMI and CLK_MDP1_SMI0_SMI IDs with dummy clocks in the MT8196 MDP clock providers. These clocks are not implemented by the current MDP clock driver and have no known consumers. Keeping the slots occupied preserves the binding-defined ID space and prevents out-of-bounds accesses in the descriptor-based onecell data. Assisted-by: GPT-5.6 Luna Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt8196-mdpsys.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8196-mdpsys.c b/drivers/clk/mediate= k/clk-mt8196-mdpsys.c index 7667d88f0eb0..2d8997d34201 100644 --- a/drivers/clk/mediatek/clk-mt8196-mdpsys.c +++ b/drivers/clk/mediatek/clk-mt8196-mdpsys.c @@ -66,6 +66,7 @@ static const struct mtk_gate mdp1_clks[] =3D { /* MDP1-0 */ GATE_MDP0(CLK_MDP1_MDP_MUTEX0, "mdp1_mdp_mutex0", "mdp", 0), GATE_MDP0(CLK_MDP1_SMI0, "mdp1_smi0", "mdp", 1), + GATE_DUMMY(CLK_MDP1_SMI0_SMI, "mdp1_smi0_smi_dummy"), GATE_MDP0(CLK_MDP1_APB_BUS, "mdp1_apb_bus", "mdp", 2), GATE_MDP0(CLK_MDP1_MDP_RDMA0, "mdp1_mdp_rdma0", "mdp", 3), GATE_MDP0(CLK_MDP1_MDP_RDMA1, "mdp1_mdp_rdma1", "mdp", 4), @@ -118,6 +119,7 @@ static const struct mtk_gate mdp_clks[] =3D { /* MDP0 */ GATE_MDP0(CLK_MDP_MDP_MUTEX0, "mdp_mdp_mutex0", "mdp", 0), GATE_MDP0(CLK_MDP_SMI0, "mdp_smi0", "mdp", 1), + GATE_DUMMY(CLK_MDP_SMI0_SMI, "mdp_smi0_smi_dummy"), GATE_MDP0(CLK_MDP_APB_BUS, "mdp_apb_bus", "mdp", 2), GATE_MDP0(CLK_MDP_MDP_RDMA0, "mdp_mdp_rdma0", "mdp", 3), GATE_MDP0(CLK_MDP_MDP_RDMA1, "mdp_mdp_rdma1", "mdp", 4), --=20 2.55.0 From nobody Thu Sep 24 20:33:42 2026 Received: from mail-pz2-f41.google.com (mail-pz2-f41.google.com [74.125.228.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 380C5470EA8 for ; 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Mon, 21 Sep 2026 03:25:46 -0700 (PDT) Received: from buffalo-ssd.taila54753.ts.net ([240b:253:4760:f400:1ebf:ceff:fe7f:5e0b]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-877a94f238csm2909174b3a.21.2026.09.21.03.25.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2026 03:25:46 -0700 (PDT) From: Akari Tsuyukusa To: Stephen Boyd , Brian Masney , Jerome Brunet , Matthias Brugger , AngeloGioacchino Del Regno Cc: Takashi Sakamoto , Danilo Krummrich , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Bjorn Helgaas , Akari Tsuyukusa , Nicolas Frattaroli , Chen-Yu Tsai , Laura Nao , Sjoerd Simons , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list:ARM/Mediatek SoC support), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support) Subject: [PATCH 6/6] clk: mediatek: Reserve missing MT8516 top clock IDs Date: Mon, 21 Sep 2026 19:25:22 +0900 Message-ID: <20260921102522.1640072-7-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260921102522.1640072-1-akkun11.open@gmail.com> References: <20260921102522.1640072-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Reserve the binding-defined CLK_TOP_EMI_DDRPHY_SEL and CLK_TOP_DDRPHYCFG_SEL slots in the MT8516 top clock provider with dummy clocks. These muxes are not implemented by the Linux MT8516 clock driver, but their binding IDs must remain represented in the onecell data to preserve a valid ID-to-slot mapping. Assisted-by: GPT-5.6 Luna Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt8516.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-m= t8516.c index 342a59019fea..b64674559878 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -545,6 +545,8 @@ static const struct mtk_gate_regs top5_cg_regs =3D { GATE_MTK(_id, _name, _parent, &top5_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 static const struct mtk_gate top_clks[] =3D { + GATE_DUMMY(CLK_TOP_EMI_DDRPHY_SEL, "emi_ddrphy_sel_dummy"), + GATE_DUMMY(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel_dummy"), /* TOP1 */ GATE_TOP1(CLK_TOP_THEM, "them", "ahb_infra_sel", 1), GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2), --=20 2.55.0