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charset="utf-8" The Stream6 Input Threshold control points at stream index 4, which is already used by Stream5. The threshold get and put callbacks derive the lane ID from the register offset, so the duplicate index makes Stream6 operate on lane 4 and leaves lane 5 inaccessible from userspace. Use stream index 5 for Stream6. Fixes: a2df8c2d5b36 ("ASoC: tegra: Add Tegra186 based ASRC driver") Signed-off-by: Sheetal Reviewed-by: Thierry Reding --- sound/soc/tegra/tegra186_asrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/tegra/tegra186_asrc.c b/sound/soc/tegra/tegra186_asr= c.c index 7f360dfaf8b1..d8ae5d997615 100644 --- a/sound/soc/tegra/tegra186_asrc.c +++ b/sound/soc/tegra/tegra186_asrc.c @@ -828,7 +828,7 @@ static const struct snd_kcontrol_new tegra186_asrc_cont= rols[] =3D { tegra186_asrc_put_input_threshold), =20 SOC_SINGLE_EXT("Stream6 Input Threshold", - ASRC_STREAM_REG(TEGRA186_ASRC_RX_THRESHOLD, 4), 0, 3, 0, + ASRC_STREAM_REG(TEGRA186_ASRC_RX_THRESHOLD, 5), 0, 3, 0, tegra186_asrc_get_input_threshold, tegra186_asrc_put_input_threshold), =20 --=20 2.43.0 From nobody Thu Sep 24 20:02:33 2026 Received: from BL0PR03CU003.outbound.protection.outlook.com (mail-eastusazon11012047.outbound.protection.outlook.com [52.101.53.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19BE545C6EE; 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charset="utf-8" Replace the separate integer and fractional ASRC ratio controls with a single two-value control for each stream. This is a userspace-visible control ABI change, but: 1. Keeping writable compatibility controls would preserve the non-atomic update path that can expose a transient mixed ratio to hardware. 2. This is limited to only the Tegra ASRC driver. Validate both values before programming hardware. The fractional field keeps the existing 32-bit maximum, while the integer field is rejected when it exceeds the hardware field width. ALSA exposes one min and max range for all values in an integer-array control, so the paired ratio controls advertise the fractional field's full 32-bit range. The put callback validates the integer part separately against the hardware field width. Serialize ratio-source changes, stream setup, and ratio updates with a driver mutex so cached ratio state and paired hardware programming remain consistent. Unlock and re-lock the ASRC stream before programming a software ratio when the new ratio differs from the cached ratio by more than 20%. Large ratio jumps require the hardware lock to be refreshed around the paired integer/fractional update. Roll back the previous hardware pair and lock state if a paired ratio update fails after partially programming the hardware. Signed-off-by: Sheetal --- sound/soc/tegra/tegra186_asrc.c | 443 ++++++++++++++++++++------------ sound/soc/tegra/tegra186_asrc.h | 4 + 2 files changed, 276 insertions(+), 171 deletions(-) diff --git a/sound/soc/tegra/tegra186_asrc.c b/sound/soc/tegra/tegra186_asr= c.c index d8ae5d997615..2b67d23f5fa7 100644 --- a/sound/soc/tegra/tegra186_asrc.c +++ b/sound/soc/tegra/tegra186_asrc.c @@ -19,6 +19,9 @@ #include "tegra186_asrc.h" #include "tegra_cif.h" =20 +#define TEGRA186_ASRC_RATIO_PERCENT_SCALE 100 +#define TEGRA186_ASRC_RATIO_UNLOCK_THRESHOLD_PERCENT 20 + #define ASRC_STREAM_SOURCE_SELECT(id) \ (TEGRA186_ASRC_CFG + ((id) * TEGRA186_ASRC_STREAM_STRIDE)) =20 @@ -65,13 +68,125 @@ static const struct reg_default tegra186_asrc_reg_defa= ults[] =3D { { TEGRA186_ASRC_CYA, 0x0}, }; =20 -static void tegra186_asrc_lock_stream(struct tegra186_asrc *asrc, - unsigned int id) +static int tegra186_asrc_set_stream_lock(struct tegra186_asrc *asrc, + unsigned int id, bool lock) { - regmap_write(asrc->regmap, - ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_LOCK_STATUS, - id), - 1); + return regmap_write(asrc->regmap, + ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_LOCK_STATUS, + id), + lock); +} + +static int tegra186_asrc_write_ratio_pair(struct tegra186_asrc *asrc, + unsigned int id, + unsigned int int_part, + unsigned int frac_part) +{ + int ret; + + ret =3D regmap_write(asrc->regmap, + ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, id), + int_part); + if (ret) + return ret; + + return regmap_write(asrc->regmap, + ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, id), + frac_part); +} + +static int tegra186_asrc_read_ratio_pair(struct tegra186_asrc *asrc, + unsigned int id, unsigned int *int_part, + unsigned int *frac_part) +{ + int ret; + + ret =3D regmap_read(asrc->regmap, + ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, id), + int_part); + if (ret) + return ret; + + return regmap_read(asrc->regmap, + ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, id), + frac_part); +} + +static void tegra186_asrc_cache_ratio(struct tegra186_asrc *asrc, + unsigned int id, unsigned int int_part, + unsigned int frac_part) +{ + asrc->lane[id].int_part =3D int_part; + asrc->lane[id].frac_part =3D frac_part; +} + +static int tegra186_asrc_apply_ratio(struct tegra186_asrc *asrc, + unsigned int id, unsigned int int_part, + unsigned int frac_part, bool unlock) +{ + unsigned int old_int_part, old_frac_part, old_lock; + int ret, restore_ret; + + ret =3D tegra186_asrc_read_ratio_pair(asrc, id, &old_int_part, + &old_frac_part); + if (ret) + return ret; + + ret =3D regmap_read(asrc->regmap, + ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_LOCK_STATUS, id), + &old_lock); + if (ret) + return ret; + + if (unlock) { + ret =3D tegra186_asrc_set_stream_lock(asrc, id, false); + if (ret) + return ret; + } + + ret =3D tegra186_asrc_write_ratio_pair(asrc, id, int_part, frac_part); + if (ret) + goto restore_ratio; + + ret =3D tegra186_asrc_set_stream_lock(asrc, id, true); + if (!ret) + return 0; + +restore_ratio: + restore_ret =3D tegra186_asrc_write_ratio_pair(asrc, id, + old_int_part, + old_frac_part); + if (!restore_ret) { + if (old_lock) + restore_ret =3D tegra186_asrc_set_stream_lock(asrc, id, + true); + else + restore_ret =3D tegra186_asrc_set_stream_lock(asrc, id, + false); + } + + return ret ?: restore_ret; +} + +static int tegra186_asrc_apply_cached_ratio(struct tegra186_asrc *asrc, + unsigned int id) +{ + return tegra186_asrc_apply_ratio(asrc, id, asrc->lane[id].int_part, + asrc->lane[id].frac_part, false); +} + +static bool tegra186_asrc_need_unlock(u64 old_ratio, u64 new_ratio) +{ + u64 ratio_diff; + + if (!old_ratio || !new_ratio) + return false; + + ratio_diff =3D (old_ratio > new_ratio) ? + (old_ratio - new_ratio) : (new_ratio - old_ratio); + + return ((ratio_diff * TEGRA186_ASRC_RATIO_PERCENT_SCALE) > + (old_ratio * TEGRA186_ASRC_RATIO_UNLOCK_THRESHOLD_PERCENT)); } =20 static int tegra186_asrc_runtime_suspend(struct device *dev) @@ -87,7 +202,7 @@ static int tegra186_asrc_runtime_suspend(struct device *= dev) static int tegra186_asrc_runtime_resume(struct device *dev) { struct tegra186_asrc *asrc =3D dev_get_drvdata(dev); - int id; + int id, ret, first_err =3D 0; =20 regcache_cache_only(asrc->regmap, false); =20 @@ -103,25 +218,23 @@ static int tegra186_asrc_runtime_resume(struct device= *dev) =20 regcache_sync(asrc->regmap); =20 + mutex_lock(&asrc->ratio_lock); for (id =3D 0; id < TEGRA186_ASRC_STREAM_MAX; id++) { if (asrc->lane[id].ratio_source !=3D TEGRA186_ASRC_RATIO_SOURCE_SW) continue; =20 - regmap_write(asrc->regmap, - ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, - id), - asrc->lane[id].int_part); - - regmap_write(asrc->regmap, - ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, - id), - asrc->lane[id].frac_part); - - tegra186_asrc_lock_stream(asrc, id); + ret =3D tegra186_asrc_apply_cached_ratio(asrc, id); + if (ret) { + dev_err(dev, "Failed to restore ratio for lane %d: %d\n", + id, ret); + if (!first_err) + first_err =3D ret; + } } + mutex_unlock(&asrc->ratio_lock); =20 - return 0; + return first_err; } =20 static int tegra186_asrc_set_audio_cif(struct tegra186_asrc *asrc, @@ -186,7 +299,7 @@ static int tegra186_asrc_out_hw_params(struct snd_pcm_s= ubstream *substream, { struct device *dev =3D dai->dev; struct tegra186_asrc *asrc =3D snd_soc_dai_get_drvdata(dai); - int ret, id =3D dai->id - 7; + int ret =3D 0, id =3D dai->id - 7; =20 /* Set output threshold */ regmap_write(asrc->regmap, @@ -217,20 +330,22 @@ static int tegra186_asrc_out_hw_params(struct snd_pcm= _substream *substream, TEGRA186_ASRC_STREAM_DEFAULT_HW_COMP_BIAS_VALUE); } =20 + mutex_lock(&asrc->ratio_lock); + /* Set lock */ regmap_update_bits(asrc->regmap, ASRC_STREAM_REG(TEGRA186_ASRC_CFG, id), 1, asrc->lane[id].ratio_source); =20 if (asrc->lane[id].ratio_source =3D=3D TEGRA186_ASRC_RATIO_SOURCE_SW) { - regmap_write(asrc->regmap, - ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, id), - asrc->lane[id].int_part); - regmap_write(asrc->regmap, - ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, id), - asrc->lane[id].frac_part); - tegra186_asrc_lock_stream(asrc, id); + ret =3D tegra186_asrc_apply_cached_ratio(asrc, id); + if (ret) + dev_err(dev, "Can't apply cached ratio for ASRC stream %d: %d\n", + id, ret); } + mutex_unlock(&asrc->ratio_lock); + if (ret) + return ret; =20 return ret; } @@ -257,112 +372,132 @@ static int tegra186_asrc_put_ratio_source(struct sn= d_kcontrol *kcontrol, struct snd_soc_component *cmpnt =3D snd_kcontrol_chip(kcontrol); struct tegra186_asrc *asrc =3D snd_soc_component_get_drvdata(cmpnt); unsigned int id =3D asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; + unsigned int new_source =3D ucontrol->value.enumerated.item[0]; + unsigned int old_source, int_part =3D 0, frac_part =3D 0; bool change =3D false; + int ret; =20 - asrc->lane[id].ratio_source =3D ucontrol->value.enumerated.item[0]; + mutex_lock(&asrc->ratio_lock); =20 - regmap_update_bits_check(asrc->regmap, asrc_private->reg, - TEGRA186_ASRC_STREAM_RATIO_TYPE_MASK, - asrc->lane[id].ratio_source, - &change); + old_source =3D asrc->lane[id].ratio_source; =20 - return change ? 1 : 0; -} + if (old_source =3D=3D TEGRA186_ASRC_RATIO_SOURCE_ARAD && + new_source =3D=3D TEGRA186_ASRC_RATIO_SOURCE_SW) { + ret =3D tegra186_asrc_read_ratio_pair(asrc, id, &int_part, + &frac_part); + if (ret) { + mutex_unlock(&asrc->ratio_lock); + return ret; + } + } =20 -static int tegra186_asrc_get_ratio_int(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct soc_mixer_control *asrc_private =3D - (struct soc_mixer_control *)kcontrol->private_value; - struct snd_soc_component *cmpnt =3D snd_kcontrol_chip(kcontrol); - struct tegra186_asrc *asrc =3D snd_soc_component_get_drvdata(cmpnt); - unsigned int id =3D asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; + ret =3D regmap_update_bits_check(asrc->regmap, asrc_private->reg, + TEGRA186_ASRC_STREAM_RATIO_TYPE_MASK, + new_source, &change); + if (ret) { + mutex_unlock(&asrc->ratio_lock); + return ret; + } =20 - regmap_read(asrc->regmap, - ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, id), - &asrc->lane[id].int_part); + asrc->lane[id].ratio_source =3D new_source; + if (old_source =3D=3D TEGRA186_ASRC_RATIO_SOURCE_ARAD && + new_source =3D=3D TEGRA186_ASRC_RATIO_SOURCE_SW) + tegra186_asrc_cache_ratio(asrc, id, int_part, frac_part); =20 - ucontrol->value.integer.value[0] =3D asrc->lane[id].int_part; + mutex_unlock(&asrc->ratio_lock); =20 - return 0; + return change ? 1 : 0; } =20 -static int tegra186_asrc_put_ratio_int(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) +static int tegra186_asrc_get_ratio(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) { - struct soc_mixer_control *asrc_private =3D - (struct soc_mixer_control *)kcontrol->private_value; + struct soc_mreg_control *asrc_private =3D + (struct soc_mreg_control *)kcontrol->private_value; struct snd_soc_component *cmpnt =3D snd_kcontrol_chip(kcontrol); struct tegra186_asrc *asrc =3D snd_soc_component_get_drvdata(cmpnt); - unsigned int id =3D asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; - bool change =3D false; + unsigned int id =3D asrc_private->regbase; + unsigned int int_part, frac_part; + int ret; + + mutex_lock(&asrc->ratio_lock); =20 if (asrc->lane[id].ratio_source =3D=3D TEGRA186_ASRC_RATIO_SOURCE_ARAD) { - dev_err(cmpnt->dev, - "Lane %d ratio source is ARAD, invalid SW update\n", - id); - return -EINVAL; + ret =3D tegra186_asrc_read_ratio_pair(asrc, id, &int_part, + &frac_part); + } else { + int_part =3D asrc->lane[id].int_part; + frac_part =3D asrc->lane[id].frac_part; + ret =3D 0; } =20 - asrc->lane[id].int_part =3D ucontrol->value.integer.value[0]; - - regmap_update_bits_check(asrc->regmap, - ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, - id), - TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK, - asrc->lane[id].int_part, &change); + mutex_unlock(&asrc->ratio_lock); + if (ret) + return ret; =20 - tegra186_asrc_lock_stream(asrc, id); + ucontrol->value.integer.value[0] =3D int_part; + ucontrol->value.integer.value[1] =3D frac_part; =20 - return change ? 1 : 0; + return 0; } =20 -static int tegra186_asrc_get_ratio_frac(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) +static int tegra186_asrc_put_ratio(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) { struct soc_mreg_control *asrc_private =3D (struct soc_mreg_control *)kcontrol->private_value; struct snd_soc_component *cmpnt =3D snd_kcontrol_chip(kcontrol); struct tegra186_asrc *asrc =3D snd_soc_component_get_drvdata(cmpnt); - unsigned int id =3D asrc_private->regbase / TEGRA186_ASRC_STREAM_STRIDE; - - regmap_read(asrc->regmap, - ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, id), - &asrc->lane[id].frac_part); + unsigned int id =3D asrc_private->regbase; + unsigned int int_part, frac_part; + u64 old_ratio, new_ratio; + long int_val =3D ucontrol->value.integer.value[0]; + long frac_val =3D ucontrol->value.integer.value[1]; + bool change =3D false, unlock =3D false; + int ret =3D 0; + + if (int_val < 0 || int_val > TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK) + return -EINVAL; =20 - ucontrol->value.integer.value[0] =3D asrc->lane[id].frac_part; + if (frac_val < 0 || frac_val > TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK) + return -EINVAL; =20 - return 0; -} + int_part =3D int_val; + frac_part =3D frac_val; =20 -static int tegra186_asrc_put_ratio_frac(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct soc_mreg_control *asrc_private =3D - (struct soc_mreg_control *)kcontrol->private_value; - struct snd_soc_component *cmpnt =3D snd_kcontrol_chip(kcontrol); - struct tegra186_asrc *asrc =3D snd_soc_component_get_drvdata(cmpnt); - unsigned int id =3D asrc_private->regbase / TEGRA186_ASRC_STREAM_STRIDE; - bool change =3D false; + mutex_lock(&asrc->ratio_lock); =20 if (asrc->lane[id].ratio_source =3D=3D TEGRA186_ASRC_RATIO_SOURCE_ARAD) { dev_err(cmpnt->dev, "Lane %d ratio source is ARAD, invalid SW update\n", id); - return -EINVAL; + ret =3D -EINVAL; + goto out_unlock; } =20 - asrc->lane[id].frac_part =3D ucontrol->value.integer.value[0]; + old_ratio =3D ((u64)asrc->lane[id].int_part << 32) | + asrc->lane[id].frac_part; + new_ratio =3D ((u64)int_part << 32) | frac_part; + + if (!new_ratio) { + ret =3D -EINVAL; + goto out_unlock; + } =20 - regmap_update_bits_check(asrc->regmap, - ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, - id), - TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, - asrc->lane[id].frac_part, &change); + change =3D old_ratio !=3D new_ratio; + if (!change) + goto out_unlock; =20 - tegra186_asrc_lock_stream(asrc, id); + unlock =3D tegra186_asrc_need_unlock(old_ratio, new_ratio); =20 - return change ? 1 : 0; + ret =3D tegra186_asrc_apply_ratio(asrc, id, int_part, frac_part, unlock); + if (!ret) + tegra186_asrc_cache_ratio(asrc, id, int_part, frac_part); + +out_unlock: + mutex_unlock(&asrc->ratio_lock); + + return ret ?: change; } =20 static int tegra186_asrc_get_hwcomp_disable(struct snd_kcontrol *kcontrol, @@ -651,99 +786,63 @@ ASRC_SOURCE_DECL(src_select4, 3); ASRC_SOURCE_DECL(src_select5, 4); ASRC_SOURCE_DECL(src_select6, 5); =20 -#define SOC_SINGLE_EXT_FRAC(xname, xregbase, xmax, xget, xput) \ +static int tegra186_asrc_ratio_param_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + struct soc_mreg_control *mc =3D + (struct soc_mreg_control *)kcontrol->private_value; + + /* + * ALSA exposes one range for all values in an integer array. The + * fractional part needs the full 32-bit range; the integer part is + * validated against the hardware field width in the put callback. + */ + uinfo->type =3D SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count =3D 2; + uinfo->value.integer.min =3D mc->min; + uinfo->value.integer.max =3D mc->max; + + return 0; +} + +#define SOC_SINGLE_EXT_ARRAY(xname, xregbase, xmax, xget, xput) \ { \ .iface =3D SNDRV_CTL_ELEM_IFACE_MIXER, \ .name =3D (xname), \ - .info =3D snd_soc_info_xr_sx, \ + .info =3D tegra186_asrc_ratio_param_info, \ .get =3D xget, \ .put =3D xput, \ \ .private_value =3D (unsigned long)&(struct soc_mreg_control) \ { \ .regbase =3D xregbase, \ - .regcount =3D 1, \ + .regcount =3D 2, \ .nbits =3D 32, \ .invert =3D 0, \ .min =3D 0, \ - .max =3D xmax \ + .max =3D (xmax) \ } \ } =20 static const struct snd_kcontrol_new tegra186_asrc_controls[] =3D { - /* Controls for integer part of ratio */ - SOC_SINGLE_EXT("Ratio1 Integer Part", - ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, 0), - 0, TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK, 0, - tegra186_asrc_get_ratio_int, - tegra186_asrc_put_ratio_int), - - SOC_SINGLE_EXT("Ratio2 Integer Part", - ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, 1), - 0, TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK, 0, - tegra186_asrc_get_ratio_int, - tegra186_asrc_put_ratio_int), - - SOC_SINGLE_EXT("Ratio3 Integer Part", - ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, 2), - 0, TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK, 0, - tegra186_asrc_get_ratio_int, - tegra186_asrc_put_ratio_int), - - SOC_SINGLE_EXT("Ratio4 Integer Part", - ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, 3), - 0, TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK, 0, - tegra186_asrc_get_ratio_int, - tegra186_asrc_put_ratio_int), - - SOC_SINGLE_EXT("Ratio5 Integer Part", - ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, 4), - 0, TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK, 0, - tegra186_asrc_get_ratio_int, - tegra186_asrc_put_ratio_int), - - SOC_SINGLE_EXT("Ratio6 Integer Part", - ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, 5), - 0, TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK, 0, - tegra186_asrc_get_ratio_int, - tegra186_asrc_put_ratio_int), - - /* Controls for fractional part of ratio */ - SOC_SINGLE_EXT_FRAC("Ratio1 Fractional Part", - ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, 0), - TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, - tegra186_asrc_get_ratio_frac, - tegra186_asrc_put_ratio_frac), - - SOC_SINGLE_EXT_FRAC("Ratio2 Fractional Part", - ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, 1), - TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, - tegra186_asrc_get_ratio_frac, - tegra186_asrc_put_ratio_frac), - - SOC_SINGLE_EXT_FRAC("Ratio3 Fractional Part", - ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, 2), - TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, - tegra186_asrc_get_ratio_frac, - tegra186_asrc_put_ratio_frac), - - SOC_SINGLE_EXT_FRAC("Ratio4 Fractional Part", - ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, 3), - TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, - tegra186_asrc_get_ratio_frac, - tegra186_asrc_put_ratio_frac), - - SOC_SINGLE_EXT_FRAC("Ratio5 Fractional Part", - ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, 4), - TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, - tegra186_asrc_get_ratio_frac, - tegra186_asrc_put_ratio_frac), - - SOC_SINGLE_EXT_FRAC("Ratio6 Fractional Part", - ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, 5), - TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, - tegra186_asrc_get_ratio_frac, - tegra186_asrc_put_ratio_frac), + /* Controls for ASRC */ + SOC_SINGLE_EXT_ARRAY("Ratio1", 0, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MA= SK, + tegra186_asrc_get_ratio, tegra186_asrc_put_ratio), + + SOC_SINGLE_EXT_ARRAY("Ratio2", 1, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MA= SK, + tegra186_asrc_get_ratio, tegra186_asrc_put_ratio), + + SOC_SINGLE_EXT_ARRAY("Ratio3", 2, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MA= SK, + tegra186_asrc_get_ratio, tegra186_asrc_put_ratio), + + SOC_SINGLE_EXT_ARRAY("Ratio4", 3, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MA= SK, + tegra186_asrc_get_ratio, tegra186_asrc_put_ratio), + + SOC_SINGLE_EXT_ARRAY("Ratio5", 4, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MA= SK, + tegra186_asrc_get_ratio, tegra186_asrc_put_ratio), + + SOC_SINGLE_EXT_ARRAY("Ratio6", 5, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MA= SK, + tegra186_asrc_get_ratio, tegra186_asrc_put_ratio), =20 /* Source of ratio provider */ SOC_ENUM_EXT("Ratio1 Source", src_select1, @@ -1011,6 +1110,8 @@ static int tegra186_asrc_platform_probe(struct platfo= rm_device *pdev) TEGRA186_ASRC_STREAM_DEFAULT_OUTPUT_HW_COMP_THRESH_CFG; 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charset="utf-8" Cache software ratio control updates when the ASRC device is runtime suspended or when the target stream is not active. Program the cached ratio when the stream is configured, and restore it after runtime resume. Take a runtime PM reference for ratio-source changes when the ASRC device is runtime-active, even if the target stream is not active, so a hardware-to-software source transition can safely capture the live ratio pair and update the source-select register. If the ASRC device is suspended, avoid waking it from a control update, update the cached source state, and mark the cached ratio invalid so the first software apply refreshes the ratio lock state. This also avoids unsafe volatile-register access during suspended control updates. For hardware-sourced ratios, return the cached pair when the device is not runtime active instead of waking it only for a mixer read. Return an error from runtime resume if restoring a cached ratio fails. This lets the PM core see that resume did not fully restore the stream state instead of leaving the hardware running with stale ratio registers. Signed-off-by: Sheetal --- sound/soc/tegra/tegra186_asrc.c | 106 ++++++++++++++++++++++++++------ sound/soc/tegra/tegra186_asrc.h | 1 + 2 files changed, 89 insertions(+), 18 deletions(-) diff --git a/sound/soc/tegra/tegra186_asrc.c b/sound/soc/tegra/tegra186_asr= c.c index 2b67d23f5fa7..389bc1a294e1 100644 --- a/sound/soc/tegra/tegra186_asrc.c +++ b/sound/soc/tegra/tegra186_asrc.c @@ -118,6 +118,7 @@ static void tegra186_asrc_cache_ratio(struct tegra186_a= src *asrc, { asrc->lane[id].int_part =3D int_part; asrc->lane[id].frac_part =3D frac_part; + asrc->lane[id].ratio_valid =3D true; } =20 static int tegra186_asrc_apply_ratio(struct tegra186_asrc *asrc, @@ -171,8 +172,15 @@ static int tegra186_asrc_apply_ratio(struct tegra186_a= src *asrc, static int tegra186_asrc_apply_cached_ratio(struct tegra186_asrc *asrc, unsigned int id) { - return tegra186_asrc_apply_ratio(asrc, id, asrc->lane[id].int_part, - asrc->lane[id].frac_part, false); + int ret; + + ret =3D tegra186_asrc_apply_ratio(asrc, id, asrc->lane[id].int_part, + asrc->lane[id].frac_part, + !asrc->lane[id].ratio_valid); + if (!ret) + asrc->lane[id].ratio_valid =3D true; + + return ret; } =20 static bool tegra186_asrc_need_unlock(u64 old_ratio, u64 new_ratio) @@ -375,19 +383,32 @@ static int tegra186_asrc_put_ratio_source(struct snd_= kcontrol *kcontrol, unsigned int new_source =3D ucontrol->value.enumerated.item[0]; unsigned int old_source, int_part =3D 0, frac_part =3D 0; bool change =3D false; - int ret; + int pm_ret, ret; =20 mutex_lock(&asrc->ratio_lock); =20 old_source =3D asrc->lane[id].ratio_source; =20 + pm_ret =3D pm_runtime_get_if_active(cmpnt->dev); + if (pm_ret < 0) { + mutex_unlock(&asrc->ratio_lock); + return pm_ret; + } + if (old_source =3D=3D TEGRA186_ASRC_RATIO_SOURCE_ARAD && new_source =3D=3D TEGRA186_ASRC_RATIO_SOURCE_SW) { - ret =3D tegra186_asrc_read_ratio_pair(asrc, id, &int_part, - &frac_part); - if (ret) { - mutex_unlock(&asrc->ratio_lock); - return ret; + if (pm_ret > 0) { + ret =3D tegra186_asrc_read_ratio_pair(asrc, id, + &int_part, + &frac_part); + if (ret) { + pm_runtime_put(cmpnt->dev); + asrc->lane[id].ratio_valid =3D false; + mutex_unlock(&asrc->ratio_lock); + return ret; + } + } else { + asrc->lane[id].ratio_valid =3D false; } } =20 @@ -395,15 +416,20 @@ static int tegra186_asrc_put_ratio_source(struct snd_= kcontrol *kcontrol, TEGRA186_ASRC_STREAM_RATIO_TYPE_MASK, new_source, &change); if (ret) { + if (pm_ret > 0) + pm_runtime_put(cmpnt->dev); mutex_unlock(&asrc->ratio_lock); return ret; } =20 asrc->lane[id].ratio_source =3D new_source; if (old_source =3D=3D TEGRA186_ASRC_RATIO_SOURCE_ARAD && - new_source =3D=3D TEGRA186_ASRC_RATIO_SOURCE_SW) + new_source =3D=3D TEGRA186_ASRC_RATIO_SOURCE_SW && pm_ret > 0) tegra186_asrc_cache_ratio(asrc, id, int_part, frac_part); =20 + if (pm_ret > 0) + pm_runtime_put(cmpnt->dev); + mutex_unlock(&asrc->ratio_lock); =20 return change ? 1 : 0; @@ -422,18 +448,33 @@ static int tegra186_asrc_get_ratio(struct snd_kcontro= l *kcontrol, =20 mutex_lock(&asrc->ratio_lock); =20 - if (asrc->lane[id].ratio_source =3D=3D TEGRA186_ASRC_RATIO_SOURCE_ARAD) { + int_part =3D asrc->lane[id].int_part; + frac_part =3D asrc->lane[id].frac_part; + + if (asrc->lane[id].ratio_source !=3D TEGRA186_ASRC_RATIO_SOURCE_ARAD) + goto done; + + ret =3D pm_runtime_get_if_active(cmpnt->dev); + if (ret < 0) { + mutex_unlock(&asrc->ratio_lock); + return ret; + } + + if (ret > 0) { ret =3D tegra186_asrc_read_ratio_pair(asrc, id, &int_part, &frac_part); - } else { - int_part =3D asrc->lane[id].int_part; - frac_part =3D asrc->lane[id].frac_part; - ret =3D 0; + if (ret) { + pm_runtime_put(cmpnt->dev); + mutex_unlock(&asrc->ratio_lock); + return ret; + } + pm_runtime_put(cmpnt->dev); + asrc->lane[id].int_part =3D int_part; + asrc->lane[id].frac_part =3D frac_part; } =20 +done: mutex_unlock(&asrc->ratio_lock); - if (ret) - return ret; =20 ucontrol->value.integer.value[0] =3D int_part; ucontrol->value.integer.value[1] =3D frac_part; @@ -454,7 +495,7 @@ static int tegra186_asrc_put_ratio(struct snd_kcontrol = *kcontrol, long int_val =3D ucontrol->value.integer.value[0]; long frac_val =3D ucontrol->value.integer.value[1]; bool change =3D false, unlock =3D false; - int ret =3D 0; + int ret =3D 0, pm_ret; =20 if (int_val < 0 || int_val > TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK) return -EINVAL; @@ -488,12 +529,40 @@ static int tegra186_asrc_put_ratio(struct snd_kcontro= l *kcontrol, if (!change) goto out_unlock; =20 - unlock =3D tegra186_asrc_need_unlock(old_ratio, new_ratio); + unlock =3D !asrc->lane[id].ratio_valid || + tegra186_asrc_need_unlock(old_ratio, new_ratio); + + pm_ret =3D pm_runtime_get_if_active(cmpnt->dev); + if (pm_ret < 0) { + ret =3D pm_ret; + goto out_unlock; + } + + if (!pm_ret) { + asrc->lane[id].int_part =3D int_part; + asrc->lane[id].frac_part =3D frac_part; + ret =3D 1; + goto out_unlock; + } + + ret =3D regmap_read(asrc->regmap, ASRC_STREAM_REG(TEGRA186_ASRC_STATUS, i= d), + &pm_ret); + if (ret) + goto out_pm_put; + + if (!(pm_ret & TEGRA186_ASRC_STREAM_EN)) { + asrc->lane[id].int_part =3D int_part; + asrc->lane[id].frac_part =3D frac_part; + ret =3D 1; + goto out_pm_put; + } =20 ret =3D tegra186_asrc_apply_ratio(asrc, id, int_part, frac_part, unlock); if (!ret) tegra186_asrc_cache_ratio(asrc, id, int_part, frac_part); =20 +out_pm_put: + pm_runtime_put(cmpnt->dev); out_unlock: mutex_unlock(&asrc->ratio_lock); =20 @@ -1103,6 +1172,7 @@ static int tegra186_asrc_platform_probe(struct platfo= rm_device *pdev) asrc->lane[i].ratio_source =3D TEGRA186_ASRC_RATIO_SOURCE_SW; asrc->lane[i].int_part =3D 1; asrc->lane[i].frac_part =3D 0; + asrc->lane[i].ratio_valid =3D true; asrc->lane[i].hwcomp_disable =3D 0; asrc->lane[i].input_thresh =3D TEGRA186_ASRC_STREAM_DEFAULT_INPUT_HW_COMP_THRESH_CFG; diff --git a/sound/soc/tegra/tegra186_asrc.h b/sound/soc/tegra/tegra186_asr= c.h index 9cc8cec6c204..dabfd2e2c904 100644 --- a/sound/soc/tegra/tegra186_asrc.h +++ b/sound/soc/tegra/tegra186_asrc.h @@ -99,6 +99,7 @@ struct tegra186_asrc_lane { unsigned int int_part; unsigned int frac_part; + bool ratio_valid; unsigned int ratio_source; unsigned int hwcomp_disable; unsigned int input_thresh; --=20 2.43.0